------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  1(TIDL_DataConvertLayer) [1, 1] --[300 x 3 x  300] => [3 x 300 x  300] *** [300] ***[ COL] ***[0, 0, 0, 900, 900]**** [1], [0],[1] -[0 ]---
  IN: DDR, DMA,    384(   900),    384(   900),  12c(  300),  42300( 271104),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),  12c(  300),  46500( 288000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  15f90( 90000),  15f90( 90000),    3(    3),  41f00( 270080),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_BatchNormLayer) [2, 2] --[3 x 300 x  300] => [3 x 300 x  300] *** [3] ***[ COL] ***[0, 0, 0, 90000, 90000]**** [1], [0],[1] -[1 ]---
  IN:MSMC, DMA,  15f90( 90000),  15f90( 90000),    3(    3),  41f00( 270080),   0,        0 ||||  L2, DMA,  15f90( 90000),  15f90( 90000),    3(    3),  41f00( 270080),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  15f90( 90000),  15f90( 90000),    3(    3),  41f00( 270080),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_ConvolutionLayer) [3, 3] --[3 x 300 x  300] => [32 x 150 x  150] *** [3] ***[ROW_L] ***[300, 300, 300, 64800, 90000]**** [2], [1],[2] -[2 ]---
  IN:MSMC, DMA,  15f90( 90000),  15f90( 90000),    3(    3),  41f00( 270080),   0,        0 ||||  L2, DMA,  1fb6c(129900),  1fb6c(129900),    3(    3),  5f300( 389888),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   5840( 22592),   57e4( 22500),   20(   32),  b3500( 734464),   0,    41f00 
  WT:DDR_PERSIST, DMA,     1b(    27),     1b(    27),   20(   32),    480(   1152),   0,        0 ||||  L2, DMA,     1b(    27),     1b(    27),   20(   32),    480(   1152),   0,    5f300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  4(TIDL_ConvolutionLayer) [4, 4] --[32 x 150 x  150] => [32 x 150 x  150] *** [1] ***[ COL] ***[0, 0, 0, 22500, 22500]**** [4], [1],[4] -[3 ]---
  IN:MSMC, DMA,   5840( 22592),   57e4( 22500),   20(   32),  b3500( 734464),   0,    41f00 ||||  L2, DMA,   57e4( 22500),   57e4( 22500),   10(   16),  57f00( 360192),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   5840( 22592),   57e4( 22500),   20(   32),  b0800( 722944),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),   60(   96),    480(   1152),   0,      480 ||||  L2, DMA,      9(     9),      9(     9),   60(   96),    480(   1152),   0,    57f00 
 STG:MSMC, DMA_ONCE,      9(     9),      9(     9),   60(   96),    480(   1152),   0,   2d1800 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  5(TIDL_ConvolutionLayer) [5, 5] --[32 x 150 x  150] => [64 x 150 x  150] *** [32] ***[ROW_L] ***[0, 0, 0, 6848, 22500]**** [4], [1],[4] -[4 ]---
  IN:MSMC, DMA,   5840( 22592),   57e4( 22500),   20(   32),  b0800( 722944),   0,        0 ||||  L2, DMA,   35c0( 13760),   35c0( 13760),   20(   32),  6ee00( 454144),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   5840( 22592),   57e4( 22500),   40(   64), 161000(1445888),   0,        0 
  WT:DDR_PERSIST, DMA,     20(    32),     20(    32),   40(   64),    980(   2432),   0,      900 ||||  L2, DMA,     20(    32),     20(    32),   40(   64),    980(   2432),   0,    6ee00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  6(TIDL_ConvolutionLayer) [6, 6] --[64 x 150 x  150] => [64 x 75 x  75] *** [1] ***[ COL] ***[0, 0, 0, 22500, 22500]**** [8], [1],[8] -[5 ]---
  IN:MSMC, DMA,   5840( 22592),   57e4( 22500),   40(   64), 161000(1445888),   0,        0 ||||  L2, DMA,   57e4( 22500),   57e4( 22500),   10(   16),  57f00( 360192),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1640(  5696),   15f9(  5625),   40(   64),  59000( 364544),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),   c0(  192),    880(   2176),   0,     1280 ||||  L2, DMA,      9(     9),      9(     9),   c0(  192),    880(   2176),   0,    57f00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  7(TIDL_ConvolutionLayer) [7, 7] --[64 x 75 x  75] => [128 x 75 x  75] *** [64] ***[ROW_L] ***[0, 0, 0, 3456, 5625]**** [2], [1],[2] -[6 ]---
  IN:MSMC, DMA,   1640(  5696),   15f9(  5625),   40(   64),  59000( 364544),   0,        0 ||||  L2, DMA,   1b40(  6976),   1b40(  6976),   40(   64),  6d080( 446592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1640(  5696),   15f9(  5625),   80(  128),  b2000( 729088),   0,        0 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   80(  128),   2300(   8960),   0,     1b00 ||||  L2, DMA,     40(    64),     40(    64),   80(  128),   2300(   8960),   0,    6d080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  8(TIDL_ConvolutionLayer) [8, 8] --[128 x 75 x  75] => [128 x 75 x  75] *** [1] ***[ COL] ***[0, 0, 0, 5625, 5625]**** [16], [1],[16] -[7 ]---
  IN:MSMC, DMA,   1640(  5696),   15f9(  5625),   80(  128),  b2000( 729088),   0,        0 ||||  L2, DMA,   15f9(  5625),   15f9(  5625),   10(   16),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1640(  5696),   15f9(  5625),   80(  128),  b2000( 729088),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  180(  384),   1080(   4224),   0,     3e00 ||||  L2, DMA,      9(     9),      9(     9),  180(  384),   1080(   4224),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  9(TIDL_ConvolutionLayer) [9, 9] --[128 x 75 x  75] => [128 x 75 x  75] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 5625]**** [4], [1],[4] -[8 ]---
  IN:MSMC, DMA,   1640(  5696),   15f9(  5625),   80(  128),  b2000( 729088),   0,        0 ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  66d00( 421120),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1640(  5696),   15f9(  5625),   80(  128),  b2000( 729088),   0,        0 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),   80(  128),   4300(  17152),   0,     4e80 ||||  L2, DMA,     c0(   192),     80(   128),   80(  128),   6300(  25344),   0,    66d00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  10(TIDL_ConvolutionLayer) [10, 10] --[128 x 75 x  75] => [128 x 38 x  38] *** [1] ***[ COL] ***[0, 0, 0, 5625, 5625]**** [4], [1],[4] -[9 ]---
  IN:MSMC, DMA,   1640(  5696),   15f9(  5625),   80(  128),  b2000( 729088),   0,        0 ||||  L2, DMA,   15f9(  5625),   15f9(  5625),   40(   64),  57f00( 360192),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5c0(  1472),    5a4(  1444),   80(  128),  2e000( 188416),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  180(  384),   1080(   4224),   0,     9180 ||||  L2, DMA,      9(     9),      9(     9),  180(  384),   1080(   4224),   0,    57f00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  11(TIDL_ConvolutionLayer) [11, 11] --[128 x 38 x  38] => [256 x 38 x  38] *** [128] ***[ROW_L] ***[0, 0, 0, 1444, 1444]**** [1], [1],[1] -[10 ]---
  IN:MSMC, DMA,    5c0(  1472),    5a4(  1444),   80(  128),  2e000( 188416),   0,        0 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),   80(  128),  2e080( 188544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5c0(  1472),    5a4(  1444),  100(  256),  5c000( 376832),   0,        0 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  100(  256),   8600(  34304),   0,     a200 ||||  L2, DMA,     c0(   192),     80(   128),  100(  256),   c600(  50688),   0,    2e080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  12(TIDL_ConvolutionLayer) [12, 12] --[256 x 38 x  38] => [256 x 38 x  38] *** [1] ***[ COL] ***[0, 0, 0, 1444, 1444]**** [1], [1],[1] -[11 ]---
  IN:MSMC, DMA,    5c0(  1472),    5a4(  1444),  100(  256),  5c000( 376832),   0,        0 ||||  L2, DMA,    5a4(  1444),    5a4(  1444),  100(  256),  5a480( 369792),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5c0(  1472),    5a4(  1444),  100(  256),  5c000( 376832),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  300(  768),   2100(   8448),   0,    12800 ||||  L2, DMA,      9(     9),      9(     9),  300(  768),   2100(   8448),   0,    5a480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  13(TIDL_ConvolutionLayer) [13, 13] --[256 x 38 x  38] => [256 x 38 x  38] *** [256] ***[ROW_L] ***[0, 0, 0, 640, 1444]**** [3], [1],[3] -[12 ]---
  IN:MSMC, DMA,    5c0(  1472),    5a4(  1444),  100(  256),  5c000( 376832),   0,        0 ||||  L2, DMA,    540(  1344),    540(  1344),  100(  256),  54300( 344832),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5c0(  1472),    5a4(  1444),  100(  256),  5c000( 376832),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),  100(  256),  10600(  67072),   0,    14900 ||||  L2, DMA,    140(   320),    100(   256),  100(  256),  14600(  83456),   0,    54300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  14(TIDL_ConvolutionLayer) [14, 14] --[256 x 38 x  38] => [256 x 19 x  19] *** [1] ***[ COL] ***[0, 0, 0, 1444, 1444]**** [1], [1],[1] -[13 ]---
  IN:MSMC, DMA,    5c0(  1472),    5a4(  1444),  100(  256),  5c000( 376832),   0,        0 ||||  L2, DMA,    5a4(  1444),    5a4(  1444),  100(  256),  5a480( 369792),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  100(  256),  1c000( 114688),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  300(  768),   2100(   8448),   0,    24f00 ||||  L2, DMA,      9(     9),      9(     9),  300(  768),   2100(   8448),   0,    5a480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  15(TIDL_ConvolutionLayer) [15, 15] --[256 x 19 x  19] => [512 x 19 x  19] *** [256] ***[ROW_L] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[14 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  100(  256),  1c000( 114688),   0,        0 ||||  L2, DMA,    1c0(   448),    1c0(   448),  100(  256),  1c080( 114816),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),  200(  512),  20c00( 134144),   0,    27000 ||||  L2, DMA,    140(   320),    100(   256),  200(  512),  28c00( 166912),   0,    1c080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  16(TIDL_ConvolutionLayer) [16, 16] --[512 x 19 x  19] => [512 x 19 x  19] *** [1] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[15 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    169(   361),    169(   361),  200(  512),  2d280( 184960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    47c00 ||||  L2, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    2d280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  17(TIDL_ConvolutionLayer) [17, 17] --[512 x 19 x  19] => [512 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 361]**** [6], [1],[6] -[16 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  200(  512),  40c00( 265216),   0,    4be00 ||||  L2, DMA,    240(   576),    200(   512),  200(  512),  48c00( 297984),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  18(TIDL_ConvolutionLayer) [18, 18] --[512 x 19 x  19] => [512 x 19 x  19] *** [1] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[17 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    169(   361),    169(   361),  200(  512),  2d280( 184960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    8ca00 ||||  L2, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    2d280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  19(TIDL_ConvolutionLayer) [19, 19] --[512 x 19 x  19] => [512 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 361]**** [6], [1],[6] -[18 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  200(  512),  40c00( 265216),   0,    90c00 ||||  L2, DMA,    240(   576),    200(   512),  200(  512),  48c00( 297984),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  20(TIDL_ConvolutionLayer) [20, 20] --[512 x 19 x  19] => [512 x 19 x  19] *** [1] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[19 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    169(   361),    169(   361),  200(  512),  2d280( 184960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    d1800 ||||  L2, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    2d280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  21(TIDL_ConvolutionLayer) [21, 21] --[512 x 19 x  19] => [512 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 361]**** [6], [1],[6] -[20 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  200(  512),  40c00( 265216),   0,    d5a00 ||||  L2, DMA,    240(   576),    200(   512),  200(  512),  48c00( 297984),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  22(TIDL_ConvolutionLayer) [22, 22] --[512 x 19 x  19] => [512 x 19 x  19] *** [1] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[21 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    169(   361),    169(   361),  200(  512),  2d280( 184960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,   116600 ||||  L2, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    2d280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  23(TIDL_ConvolutionLayer) [23, 23] --[512 x 19 x  19] => [512 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 361]**** [6], [1],[6] -[22 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  200(  512),  40c00( 265216),   0,   11a800 ||||  L2, DMA,    240(   576),    200(   512),  200(  512),  48c00( 297984),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  24(TIDL_ConvolutionLayer) [24, 24] --[512 x 19 x  19] => [512 x 19 x  19] *** [1] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[23 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    169(   361),    169(   361),  200(  512),  2d280( 184960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,   15b400 ||||  L2, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    2d280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  25(TIDL_ConvolutionLayer) [25, 25] --[512 x 19 x  19] => [512 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 361]**** [6], [1],[6] -[24 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  200(  512),  40c00( 265216),   0,   15f600 ||||  L2, DMA,    240(   576),    200(   512),  200(  512),  48c00( 297984),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  27(TIDL_ConvolutionLayer) [26, 27] --[512 x 19 x  19] => [12 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[25 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    1c0(   448),    1c0(   448),  200(  512),  38080( 229504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),    c(   12),   1500(   5376),   0,    38000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),    c(   12),   1880(   6272),   0,   1a0200 ||||  L2, DMA,    240(   576),    200(   512),    c(   12),   1b80(   7040),   0,    38080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  26(TIDL_ConvolutionLayer) [27, 26] --[512 x 19 x  19] => [512 x 10 x  10] *** [1] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [1],[1] -[25 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    169(   361),    169(   361),  200(  512),  2d280( 184960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),  200(  512),  18000(  98304),   0,    cad00 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,   1a1a80 ||||  L2, DMA,      9(     9),      9(     9),  600( 1536),   4200(  16896),   0,    2d280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  29(TIDL_ConvolutionLayer) [28, 29] --[512 x 10 x  10] => [1024 x 10 x  10] *** [512] ***[ROW_L] ***[0, 0, 0, 100, 100]**** [1], [4],[4] -[26 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  200(  512),  18000(  98304),   0,    cad00 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18080(  98432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    cad00 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  400( 1024),  81800( 530432),   0,   1a5c80 ||||  L2, DMA,    240(   576),    200(   512),  200(  512),  49800( 301056),   0,    18080 
 STG:MSMC, DMA,    246(   582),    200(   512),  400( 1024),  91800( 595968),   0,    39500 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  30(TIDL_ConvolutionLayer) [29, 30] --[1024 x 10 x  10] => [1024 x 10 x  10] *** [1] ***[ COL] ***[0, 0, 0, 100, 100]**** [1], [1],[1] -[29 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    cad00 ||||  L2, DMA,     64(   100),     64(   100),  400( 1024),  19080( 102528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    39500 
  WT:DDR_PERSIST, DMA,      9(     9),      9(     9),  c00( 3072),   8400(  33792),   0,   227480 ||||  L2, DMA,      9(     9),      9(     9),  c00( 3072),   8400(  33792),   0,    19080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  31(TIDL_ConvolutionLayer) [30, 31] --[1024 x 10 x  10] => [1024 x 10 x  10] *** [1024] ***[ROW_L] ***[0, 0, 0, 100, 100]**** [1], [16],[16] -[30 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    39500 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    39500 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  400( 1024), 101800(1054720),   0,   22f880 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  23800( 145408),   0,    30080 
 STG:MSMC, DMA,    446(  1094),    400(  1024),  400( 1024), 111800(1120256),   0,    69500 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  33(TIDL_ConvolutionLayer) [31, 33] --[1024 x 10 x  10] => [24 x 10 x  10] *** [1024] ***[ROW_L] ***[0, 0, 0, 100, 100]**** [1], [1],[1] -[31 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    39500 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),   18(   24),   1200(   4608),   0,    69500 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),   18(   24),   6100(  24832),   0,   331080 ||||  L2, DMA,    440(  1088),    400(  1024),   18(   24),   6700(  26368),   0,    30080 
 STG:MSMC, DMA_ONCE,    440(  1088),    400(  1024),   18(   24),   6700(  26368),   0,   2cb100 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  32(TIDL_ConvolutionLayer) [32, 32] --[1024 x 10 x  10] => [256 x 10 x  10] *** [1024] ***[ROW_L] ***[0, 0, 0, 100, 100]**** [1], [1],[1] -[31 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    39500 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20080( 131200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),  100(  256),   c000(  49152),   0,    6a700 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  100(  256),  40600( 263680),   0,   337180 ||||  L2, DMA,    440(  1088),    400(  1024),  100(  256),  44600( 280064),   0,    20080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  35(TIDL_ConvolutionLayer) [33, 35] --[256 x 10 x  10] => [512 x 5 x  5] *** [256] ***[ROW_L] ***[10, 10, 10, 90, 100]**** [1], [8],[8] -[32 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  100(  256),   c000(  49152),   0,    6a700 ||||  L2, DMA,     c0(   192),     c0(   192),  100(  256),   c080(  49280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     19(    25),     19(    25),  200(  512),   3200(  12800),   0,   19f300 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120c00(1182720),   0,   377780 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4ac00( 306176),   0,     c080 
 STG:MSMC, DMA_ONCE,    946(  2374),    900(  2304),  200(  512), 128c00(1215488),   0,   1a2500 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  37(TIDL_ConvolutionLayer) [34, 37] --[512 x 5 x  5] => [24 x 5 x  5] *** [512] ***[ROW_L] ***[0, 0, 0, 25, 25]**** [1], [1],[1] -[35 ]---
  IN:MSMC, DMA,     19(    25),     19(    25),  200(  512),   3200(  12800),   0,   19f300 ||||  L2, DMA,     19(    25),     19(    25),  200(  512),   3280(  12928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     19(    25),     19(    25),   18(   24),    280(    640),   0,    6a700 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),   18(   24),   3100(  12544),   0,   498380 ||||  L2, DMA,    240(   576),    200(   512),   18(   24),   3700(  14080),   0,     3280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  36(TIDL_ConvolutionLayer) [35, 36] --[512 x 5 x  5] => [128 x 5 x  5] *** [512] ***[ROW_L] ***[0, 0, 0, 25, 25]**** [1], [1],[1] -[35 ]---
  IN:MSMC, DMA,     19(    25),     19(    25),  200(  512),   3200(  12800),   0,   19f300 ||||  L2, DMA,     19(    25),     19(    25),  200(  512),   3280(  12928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     19(    25),     19(    25),   80(  128),    c80(   3200),   0,    6b280 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),   80(  128),  10300(  66304),   0,   49b480 ||||  L2, DMA,    240(   576),    200(   512),   80(  128),  12300(  74496),   0,     3280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  39(TIDL_ConvolutionLayer) [36, 39] --[128 x 5 x  5] => [256 x 3 x  3] *** [128] ***[ROW_L] ***[5, 5, 0, 20, 25]**** [1], [1],[1] -[36 ]---
  IN:MSMC, DMA,     19(    25),     19(    25),   80(  128),    c80(   3200),   0,    6b280 ||||  L2, DMA,     19(    25),     19(    25),   80(  128),    d80(   3456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      9(     9),      9(     9),  100(  256),    900(   2304),   0,    6a980 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48600( 296448),   0,   4ab780 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c600( 312832),   0,      d80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  41(TIDL_ConvolutionLayer) [37, 41] --[256 x 3 x  3] => [24 x 3 x  3] *** [256] ***[ROW_L] ***[0, 0, 0, 9, 9]**** [1], [1],[1] -[39 ]---
  IN:MSMC, DMA,      9(     9),      9(     9),  100(  256),    900(   2304),   0,    6a980 ||||  L2, DMA,      9(     9),      9(     9),  100(  256),    980(   2432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      9(     9),      9(     9),   18(   24),    100(    256),   0,    6b280 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   18(   24),   1900(   6400),   0,   4f3d80 ||||  L2, DMA,    140(   320),    100(   256),   18(   24),   1f00(   7936),   0,      980 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  40(TIDL_ConvolutionLayer) [38, 40] --[256 x 3 x  3] => [128 x 3 x  3] *** [256] ***[ROW_L] ***[0, 0, 0, 9, 9]**** [1], [1],[1] -[39 ]---
  IN:MSMC, DMA,      9(     9),      9(     9),  100(  256),    900(   2304),   0,    6a980 ||||  L2, DMA,      9(     9),      9(     9),  100(  256),    980(   2432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      9(     9),      9(     9),   80(  128),    480(   1152),   0,    6b780 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8300(  33536),   0,   4f5680 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a300(  41728),   0,      980 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  43(TIDL_ConvolutionLayer) [39, 43] --[128 x 3 x  3] => [256 x 2 x  2] *** [128] ***[ROW_L] ***[3, 3, 0, 6, 9]**** [1], [1],[1] -[40 ]---
  IN:MSMC, DMA,      9(     9),      9(     9),   80(  128),    480(   1152),   0,    6b780 ||||  L2, DMA,      9(     9),      9(     9),   80(  128),    580(   1408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),  100(  256),    400(   1024),   0,    6b380 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48600( 296448),   0,   4fd980 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c600( 312832),   0,      580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  45(TIDL_ConvolutionLayer) [40, 45] --[256 x 2 x  2] => [24 x 2 x  2] *** [256] ***[ROW_L] ***[0, 0, 0, 4, 4]**** [1], [1],[1] -[43 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),  100(  256),    400(   1024),   0,    6b380 ||||  L2, DMA,      4(     4),      4(     4),  100(  256),    480(   1152),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),   18(   24),     80(    128),   0,    6b780 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   18(   24),   1900(   6400),   0,   545f80 ||||  L2, DMA,    140(   320),    100(   256),   18(   24),   1f00(   7936),   0,      480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  44(TIDL_ConvolutionLayer) [41, 44] --[256 x 2 x  2] => [64 x 2 x  2] *** [256] ***[ROW_L] ***[0, 0, 0, 4, 4]**** [1], [1],[1] -[43 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),  100(  256),    400(   1024),   0,    6b380 ||||  L2, DMA,      4(     4),      4(     4),  100(  256),    480(   1152),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),   40(   64),    100(    256),   0,    6b880 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   40(   64),   4180(  16768),   0,   547880 ||||  L2, DMA,    140(   320),    100(   256),   40(   64),   5180(  20864),   0,      480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  47(TIDL_ConvolutionLayer) [42, 47] --[64 x 2 x  2] => [128 x 1 x  1] *** [64] ***[ROW_L] ***[2, 2, 2, 2, 4]**** [1], [1],[1] -[44 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),   40(   64),    100(    256),   0,    6b880 ||||  L2, DMA,      4(     4),      4(     4),   40(   64),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      1(     1),      1(     1),   80(  128),     80(    128),   0,    6b800 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   80(  128),  12300(  74496),   0,   54ba00 ||||  L2, DMA,    240(   576),    240(   576),   80(  128),  12300(  74496),   0,      180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  48(TIDL_ConvolutionLayer) [43, 48] --[128 x 1 x  1] => [24 x 1 x  1] *** [128] ***[ROW_L] ***[0, 0, 0, 1, 1]**** [1], [1],[1] -[47 ]---
  IN:MSMC, DMA,      1(     1),      1(     1),   80(  128),     80(    128),   0,    6b800 ||||  L2, DMA,      1(     1),      1(     1),   80(  128),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      1(     1),      1(     1),   18(   24),     80(    128),   0,    6b880 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),   18(   24),    d00(   3328),   0,   55dd00 ||||  L2, DMA,     c0(   192),     80(   128),   18(   24),   1300(   4864),   0,      100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  28(TIDL_ConvolutionLayer) [44, 28] --[512 x 19 x  19] => [273 x 19 x  19] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 361]**** [2], [1],[2] -[25 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),  200(  512),  38000( 229376),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48080( 295040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    169(   361),  111(  273),  1de00( 122368),   0,        0 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  111(  273),  22880( 141440),   0,   55ea00 ||||  L2, DMA,    240(   576),    200(   512),  111(  273),  26d00( 158976),   0,    48080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  34(TIDL_ConvolutionLayer) [45, 34] --[1024 x 10 x  10] => [546 x 10 x  10] *** [1024] ***[ROW_L] ***[0, 0, 0, 100, 100]**** [1], [9],[9] -[31 ]---
  IN:MSMC, DMA,     c0(   192),     64(   100),  400( 1024),  30000( 196608),   0,    39500 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     64(   100),  222(  546),  19980( 104832),   0,    1de00 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  222(  546),  89500( 562432),   0,   581280 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22d00( 142592),   0,    30080 
 STG:MSMC, DMA,    501(  1281),    400(  1024),  222(  546),  aad00( 699648),   0,    6b900 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  38(TIDL_ConvolutionLayer) [46, 38] --[512 x 5 x  5] => [546 x 5 x  5] *** [512] ***[ROW_L] ***[0, 0, 0, 25, 25]**** [1], [1],[1] -[35 ]---
  IN:MSMC, DMA,     19(    25),     19(    25),  200(  512),   3200(  12800),   0,   19f300 ||||  L2, DMA,     19(    25),     19(    25),  200(  512),   3280(  12928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     19(    25),     19(    25),  222(  546),   3580(  13696),   0,    39500 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  222(  546),  45100( 282880),   0,   60a780 ||||  L2, DMA,    240(   576),    200(   512),  222(  546),  4d980( 317824),   0,     3280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  42(TIDL_ConvolutionLayer) [47, 42] --[256 x 3 x  3] => [546 x 3 x  3] *** [256] ***[ROW_L] ***[0, 0, 0, 9, 9]**** [1], [1],[1] -[39 ]---
  IN:MSMC, DMA,      9(     9),      9(     9),  100(  256),    900(   2304),   0,    6a980 ||||  L2, DMA,      9(     9),      9(     9),  100(  256),    980(   2432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      9(     9),      9(     9),  222(  546),   1380(   4992),   0,    3ca80 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),  222(  546),  22f00( 143104),   0,   64f880 ||||  L2, DMA,    140(   320),    100(   256),  222(  546),  2b780( 178048),   0,      980 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  46(TIDL_ConvolutionLayer) [48, 46] --[256 x 2 x  2] => [546 x 2 x  2] *** [256] ***[ROW_L] ***[0, 0, 0, 4, 4]**** [1], [1],[1] -[43 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),  100(  256),    400(   1024),   0,    6b380 ||||  L2, DMA,      4(     4),      4(     4),  100(  256),    480(   1152),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),  222(  546),    900(   2304),   0,    3de00 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),  222(  546),  22f00( 143104),   0,   672780 ||||  L2, DMA,    140(   320),    100(   256),  222(  546),  2b780( 178048),   0,      480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  49(TIDL_ConvolutionLayer) [49, 49] --[128 x 1 x  1] => [546 x 1 x  1] *** [128] ***[ROW_L] ***[0, 0, 0, 1, 1]**** [1], [1],[1] -[47 ]---
  IN:MSMC, DMA,      1(     1),      1(     1),   80(  128),     80(    128),   0,    6b800 ||||  L2, DMA,      1(     1),      1(     1),   80(  128),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      1(     1),      1(     1),  222(  546),    280(    640),   0,    37780 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  222(  546),  11e00(  73216),   0,   695680 ||||  L2, DMA,     c0(   192),     80(   128),  222(  546),  1a680( 108160),   0,      100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  50(TIDL_DetectionOutputLayer) [50, 50] --[12 x 19 x  19] => [1 x 1405 x  1] *** [12] ***[ COL] ***[0, 0, 0, 361, 361]**** [1], [0],[1] -[27 33 37 41 45 48 28 34 38 42 46 49 ]---
  IN:MSMC, DMA,    1c0(   448),    169(   361),    c(   12),   1500(   5376),   0,    38000 ||||  L2, DMA,    1c8(   456),    1c8(   456),    c(   12),   1580(   5504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1640(  5696),   15f4(  5620),    1(    1),   1680(   5760),   0,    3e700 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  51(TIDL_OdOutputReformatLayer) [51, 51] --[1 x 1405 x  1] => [1 x 4 x  200] *** [1] ***[ COL] ***[0, 0, 0, 1405, 1405]**** [1], [0],[1] -[50 ]---
  IN:MSMC, DMA,   1640(  5696),   15f4(  5620),    1(    1),   1680(   5760),   0,    3e700 ||||  L2, DMA,    57d(  1405),    57d(  1405),    1(    1),    580(   1408),   0,        0 
 OUT:MSMC, CPU,    320(   800),    320(   800),    2(    2),    680(   1664),   0,        0 |||| DDR, DMA,    c80(  3200),    c80(  3200),    1(    1),   1080(   4224),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  52(TIDL_OdOutputReformatLayer) [53, 52] --[1 x 1405 x  1] => [1 x 200 x  1] *** [1] ***[ COL] ***[0, 0, 0, 1405, 1405]**** [1], [0],[1] -[50 ]---
  IN:MSMC, DMA,   1640(  5696),   15f4(  5620),    1(    1),   1680(   5760),   0,    3e700 ||||  L2, DMA,    57d(  1405),    57d(  1405),    1(    1),    580(   1408),   0,        0 
 OUT:MSMC, CPU,     c8(   200),     c8(   200),    2(    2),    200(    512),   0,        0 |||| DDR, DMA,    320(   800),    320(   800),    1(    1),    780(   1920),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  53(TIDL_OdOutputReformatLayer) [55, 53] --[1 x 1405 x  1] => [1 x 200 x  1] *** [1] ***[ COL] ***[0, 0, 0, 1405, 1405]**** [1], [0],[1] -[50 ]---
  IN:MSMC, DMA,   1640(  5696),   15f4(  5620),    1(    1),   1680(   5760),   0,    3e700 ||||  L2, DMA,    57d(  1405),    57d(  1405),    1(    1),    580(   1408),   0,        0 
 OUT:MSMC, CPU,     c8(   200),     c8(   200),    2(    2),    200(    512),   0,        0 |||| DDR, DMA,    320(   800),    320(   800),    1(    1),    780(   1920),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  54(TIDL_OdOutputReformatLayer) [57, 54] --[1 x 1405 x  1] => [1 x 1 x  1] *** [1] ***[ COL] ***[0, 0, 0, 1405, 1405]**** [1], [0],[1] -[50 ]---
  IN:MSMC, DMA,   1640(  5696),   15f4(  5620),    1(    1),   1680(   5760),   0,    3e700 ||||  L2, DMA,    57d(  1405),    57d(  1405),    1(    1),    580(   1408),   0,        0 
 OUT:MSMC, CPU,      1(     1),      1(     1),    2(    2),     80(    128),   0,        0 |||| DDR, DMA,      4(     4),      4(     4),    1(    1),    480(   1152),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
