==================================================================================================================================================
				pcie1-EN pcie2-DIS
==================================================================================================================================================

file dra7.dtsi stings 292-360 

	axi@0 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51000000 0x51000000 0x3000
				  0x0	     0x20000000 0x10000000>;
			status = "okay";
			pcie1: pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 232 0x4>, <0 233 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0          0x03000 0 0x00010000
					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				ti,hwmods = "pcie1";
				phys = <&pcie1_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
						<0 0 0 2 &pcie1_intc 2>,
						<0 0 0 3 &pcie1_intc 3>,
						<0 0 0 4 &pcie1_intc 4>;
				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};

		axi@1 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51800000 0x51800000 0x3000
				  0x0	     0x30000000 0x10000000>;
			status = "disabled";
			pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 355 0x4>, <0 356 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0          0x03000 0 0x00010000
					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				ti,hwmods = "pcie2";
				phys = <&pcie2_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 1>,
						<0 0 0 2 &pcie2_intc 2>,
						<0 0 0 3 &pcie2_intc 3>,
						<0 0 0 4 &pcie2_intc 4>;
				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};
		
file dra7.dtsi stings 1616-1656

	pcie1_phy: pciephy@4a094000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a094000 0x80>, /* phy_rx */
				      <0x4a094400 0x64>; /* phy_tx */
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <&scm_conf_pcie 0x1c>;
				syscon-pcs = <&scm_conf_pcie 0x10>;
				clocks = <&dpll_pcie_ref_ck>,
					 <&dpll_pcie_ref_m2ldo_ck>,
					 <&optfclk_pciephy1_32khz>,
					 <&optfclk_pciephy1_clk>,
					 <&optfclk_pciephy1_div_clk>,
					 <&optfclk_pciephy_div>,
					 <&sys_clkin1>;
				clock-names = "dpll_ref", "dpll_ref_m2",
					      "wkupclk", "refclk",
					      "div-clk", "phy-div", "sysclk";
				#phy-cells = <0>;
				status = "okay";
			};

			pcie2_phy: pciephy@4a095000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a095000 0x80>, /* phy_rx */
				      <0x4a095400 0x64>; /* phy_tx */
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <&scm_conf_pcie 0x20>;
				syscon-pcs = <&scm_conf_pcie 0x10>;
				clocks = <&dpll_pcie_ref_ck>,
					 <&dpll_pcie_ref_m2ldo_ck>,
					 <&optfclk_pciephy2_32khz>,
					 <&optfclk_pciephy2_clk>,
					 <&optfclk_pciephy2_div_clk>,
					 <&optfclk_pciephy_div>,
					 <&sys_clkin1>;
				clock-names = "dpll_ref", "dpll_ref_m2",
					      "wkupclk", "refclk",
					      "div-clk", "phy-div", "sysclk";
				#phy-cells = <0>;
				status = "okay";
			};

lspci output

00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0, IRQ 436
	Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
	Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: 20200000-202fffff
	Capabilities: [40] Power Management version 3
	Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
	Capabilities: [70] Express Root Port (Slot-), MSI 00
	Capabilities: [100] Advanced Error Reporting
	Kernel driver in use: pcieport

01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
	Flags: fast devsel
	Memory at 20200000 (32-bit, non-prefetchable) [disabled] [size=512K]
	I/O ports at 1000 [disabled] [size=32]
	Memory at 20280000 (32-bit, non-prefetchable) [disabled] [size=16K]
	Capabilities: [40] Power Management version 3
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
	Capabilities: [70] MSI-X: Enable- Count=5 Masked-
	Capabilities: [a0] Express Endpoint, MSI 00
	Capabilities: [100] Advanced Error Reporting
	Capabilities: [140] Device Serial Number 00-a0-c9-ff-ff-00-00-00
	Capabilities: [1a0] Transaction Processing Hints
	
==================================================================================================================================================
				pcie1-DIS pcie2-EN
==================================================================================================================================================

pcie2  file dra7.dtsi stings 292-360 

axi@0 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51000000 0x51000000 0x3000
				  0x0	     0x20000000 0x10000000>;
			status = "disabled";
			pcie1: pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 232 0x4>, <0 233 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0          0x03000 0 0x00010000
					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				ti,hwmods = "pcie1";
				phys = <&pcie1_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
						<0 0 0 2 &pcie1_intc 2>,
						<0 0 0 3 &pcie1_intc 3>,
						<0 0 0 4 &pcie1_intc 4>;
				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};

		axi@1 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51800000 0x51800000 0x3000
				  0x0	     0x30000000 0x10000000>;
			status = "okay";
			pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 355 0x4>, <0 356 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0          0x03000 0 0x00010000
					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				ti,hwmods = "pcie2";
				phys = <&pcie2_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 1>,
						<0 0 0 2 &pcie2_intc 2>,
						<0 0 0 3 &pcie2_intc 3>,
						<0 0 0 4 &pcie2_intc 4>;
				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};
		
file dra7.dtsi stings 1616-1656

pcie1_phy: pciephy@4a094000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a094000 0x80>, /* phy_rx */
				      <0x4a094400 0x64>; /* phy_tx */
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <&scm_conf_pcie 0x1c>;
				syscon-pcs = <&scm_conf_pcie 0x10>;
				clocks = <&dpll_pcie_ref_ck>,
					 <&dpll_pcie_ref_m2ldo_ck>,
					 <&optfclk_pciephy1_32khz>,
					 <&optfclk_pciephy1_clk>,
					 <&optfclk_pciephy1_div_clk>,
					 <&optfclk_pciephy_div>,
					 <&sys_clkin1>;
				clock-names = "dpll_ref", "dpll_ref_m2",
					      "wkupclk", "refclk",
					      "div-clk", "phy-div", "sysclk";
				#phy-cells = <0>;
				status = "disabled";
			};

			pcie2_phy: pciephy@4a095000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a095000 0x80>, /* phy_rx */
				      <0x4a095400 0x64>; /* phy_tx */
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <&scm_conf_pcie 0x20>;
				syscon-pcs = <&scm_conf_pcie 0x10>;
				clocks = <&dpll_pcie_ref_ck>,
					 <&dpll_pcie_ref_m2ldo_ck>,
					 <&optfclk_pciephy2_32khz>,
					 <&optfclk_pciephy2_clk>,
					 <&optfclk_pciephy2_div_clk>,
					 <&optfclk_pciephy_div>,
					 <&sys_clkin1>;
				clock-names = "dpll_ref", "dpll_ref_m2",
					      "wkupclk", "refclk",
					      "div-clk", "phy-div", "sysclk";
				#phy-cells = <0>;
				status = "okay";
			};
		};
		
lspci output -v for pcie2

00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0, IRQ 436
	Memory at 30100000 (32-bit, non-prefetchable) [size=1M]
	Memory at 30020000 (32-bit, non-prefetchable) [size=64K]
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: 30200000-302fffff
	Capabilities: [40] Power Management version 3
	Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
	Capabilities: [70] Express Root Port (Slot-), MSI 00
	Capabilities: [100] Advanced Error Reporting
	Kernel driver in use: pcieport

01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
	Flags: fast devsel
	Memory at 30200000 (32-bit, non-prefetchable) [disabled] [size=512K]
	I/O ports at 1000 [disabled] [size=32]
	Memory at 30280000 (32-bit, non-prefetchable) [disabled] [size=16K]
	Capabilities: [40] Power Management version 3
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
	Capabilities: [70] MSI-X: Enable- Count=5 Masked-
	Capabilities: [a0] Express Endpoint, MSI 00
	Capabilities: [100] Advanced Error Reporting
	Capabilities: [140] Device Serial Number 00-a0-c9-ff-ff-00-00-00
	Capabilities: [1a0] Transaction Processing Hints
==================================================================================================================================================
				pcie1-EN pcie2-EN
==================================================================================================================================================
file dra7.dtsi stings 292-360

axi@0 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51000000 0x51000000 0x3000
				  0x0	     0x20000000 0x10000000>;
			status = "okay";
			pcie1: pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 232 0x4>, <0 233 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0          0x03000 0 0x00010000
					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				ti,hwmods = "pcie1";
				phys = <&pcie1_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
						<0 0 0 2 &pcie1_intc 2>,
						<0 0 0 3 &pcie1_intc 3>,
						<0 0 0 4 &pcie1_intc 4>;
				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};

		axi@1 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51800000 0x51800000 0x3000
				  0x0	     0x30000000 0x10000000>;
			status = "okay";
			pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 355 0x4>, <0 356 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0          0x03000 0 0x00010000
					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				ti,hwmods = "pcie2";
				phys = <&pcie2_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 1>,
						<0 0 0 2 &pcie2_intc 2>,
						<0 0 0 3 &pcie2_intc 3>,
						<0 0 0 4 &pcie2_intc 4>;
				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};


file dra7.dtsi stings 1616-1656

	pcie1_phy: pciephy@4a094000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a094000 0x80>, /* phy_rx */
				      <0x4a094400 0x64>; /* phy_tx */
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <&scm_conf_pcie 0x1c>;
				syscon-pcs = <&scm_conf_pcie 0x10>;
				clocks = <&dpll_pcie_ref_ck>,
					 <&dpll_pcie_ref_m2ldo_ck>,
					 <&optfclk_pciephy1_32khz>,
					 <&optfclk_pciephy1_clk>,
					 <&optfclk_pciephy1_div_clk>,
					 <&optfclk_pciephy_div>,
					 <&sys_clkin1>;
				clock-names = "dpll_ref", "dpll_ref_m2",
					      "wkupclk", "refclk",
					      "div-clk", "phy-div", "sysclk";
				#phy-cells = <0>;
				status = "okay";
			};

			pcie2_phy: pciephy@4a095000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a095000 0x80>, /* phy_rx */
				      <0x4a095400 0x64>; /* phy_tx */
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <&scm_conf_pcie 0x20>;
				syscon-pcs = <&scm_conf_pcie 0x10>;
				clocks = <&dpll_pcie_ref_ck>,
					 <&dpll_pcie_ref_m2ldo_ck>,
					 <&optfclk_pciephy2_32khz>,
					 <&optfclk_pciephy2_clk>,
					 <&optfclk_pciephy2_div_clk>,
					 <&optfclk_pciephy_div>,
					 <&sys_clkin1>;
				clock-names = "dpll_ref", "dpll_ref_m2",
					      "wkupclk", "refclk",
					      "div-clk", "phy-div", "sysclk";
				#phy-cells = <0>;
				status = "okay";
			};
			
lspci output для pcie1, pcie2 видно, что работает только pcie1

00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0, IRQ 438
	Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
	Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: 20200000-202fffff
	Capabilities: [40] Power Management version 3
	Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
	Capabilities: [70] Express Root Port (Slot-), MSI 00
	Capabilities: [100] Advanced Error Reporting
	Kernel driver in use: pcieport

01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
	Flags: fast devsel
	Memory at 20200000 (32-bit, non-prefetchable) [disabled] [size=512K]
	I/O ports at 1000 [disabled] [size=32]
	Memory at 20280000 (32-bit, non-prefetchable) [disabled] [size=16K]
	Capabilities: [40] Power Management version 3
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
	Capabilities: [70] MSI-X: Enable- Count=5 Masked-
	Capabilities: [a0] Express Endpoint, MSI 00
	Capabilities: [100] Advanced Error Reporting
	Capabilities: [140] Device Serial Number 00-a0-c9-ff-ff-00-00-00
	Capabilities: [1a0] Transaction Processing Hints
================================================================================================================================