(venv) yeverino@yeverino-pc:~/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools$ ./scripts/run_python_examples.sh X64 Architecture Running 4 Models - ['cl-tfl-mobilenet_v1_1.0_224', 'ss-tfl-deeplabv3_mnv2_ade20k_float', 'od-tfl-ssd_mobilenet_v2_300_float', 'od-tfl-ssd_mobilenet_v1_1_default_1'] Running_Model : cl-tfl-mobilenet_v1_1.0_224 Running_Model : ss-tfl-deeplabv3_mnv2_ade20k_float Running_Model : od-tfl-ssd_mobilenet_v2_300_float Running_Model : od-tfl-ssd_mobilenet_v1_1_default_1 TIDL Meta PipeLine (Proto) File : Number of OD backbone nodes = 0 Size of odBackboneNodeIds = 0 TIDL Meta PipeLine (Proto) File : Number of OD backbone nodes = 0 Size of odBackboneNodeIds = 0 Warning : concat requires 4D input tensors - only 3 dims present.. Ignore if object detection network Number of subgraphs:1 , 67 nodes delegated out of 67 nodes Number of subgraphs:1 , 81 nodes delegated out of 81 nodes Number of subgraphs:1 , 34 nodes delegated out of 34 nodes Warning : concat requires 4D input tensors - only 3 dims present.. Ignore if object detection network Warning : concat requires 4D input tensors - only 3 dims present.. Ignore if object detection network Number of subgraphs:1 , 107 nodes delegated out of 107 nodes Warning : concat requires 4D input tensors - only 3 dims present.. Ignore if object detection network WARNING: Batch Norm Layer scale_logits's coeff cannot be found(or not match) in coef file, Random bias will be generated! Only for evaluation usage! Results are all random! Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* ************** Frame index 1 : Running float import ************* ************** Frame index 1 : Running float import ************* INFORMATION: [TIDL_ResizeLayer] ResizeBilinear_TIDL_0 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] ResizeBilinear_TIDL_1 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] ResizeBilinear Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] decoder/ResizeBilinear Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] ResizeBilinear_1 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 6 WARNINGS 0 ERRORS ** **************************************************** 0.0s: VX_ZONE_INIT:Enabled 0.11s: VX_ZONE_ERROR:Enabled 0.12s: VX_ZONE_WARNING:Enabled 0.1271s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** 0.0s: VX_ZONE_INIT:Enabled 0.15s: VX_ZONE_ERROR:Enabled 0.16s: VX_ZONE_WARNING:Enabled 0.439s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.8s: VX_ZONE_ERROR:Enabled 0.9s: VX_ZONE_WARNING:Enabled 0.401s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** 0.0s: VX_ZONE_INIT:Enabled 0.11s: VX_ZONE_ERROR:Enabled 0.12s: VX_ZONE_WARNING:Enabled 0.368s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! ************ Frame index 1 : Running float inference **************** ************ Frame index 1 : Running float inference **************** ************ Frame index 2 : Running fixed point mode for calibration **************** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-tfl-mobilenet_v1_1.0_224/tempDir/86_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ************ Frame index 2 : Running fixed point mode for calibration **************** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 564.22 .... ..... ... .... ..... # 1 . .. ************ Frame index 1 : Running float inference **************** T 556.42 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-tfl-mobilenet_v1_1.0_224/tempDir/86_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 844.05 .... ..... ... .... ..... # 1 . .. T 817.92 .... ..... ... .... ..... # 1 . .. T 843.43 .... ..... ... .... ..... ************ Frame index 2 : Running fixed point mode for calibration **************** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v2_300_float/tempDir/264_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 821.83 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-tfl-mobilenet_v1_1.0_224/tempDir/86_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 825.07 .... ..... ... .... ..... # 1 . .. T 1881.09 .... ..... ... .... ..... # 1 . .. T 825.71 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ T 1158.42 .... ..... ... .... ..... # 1 . .. Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-tfl-mobilenet_v1_1.0_224/tempDir/86_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 816.59 .... ..... ... .... ..... # 1 . .. T 1142.34 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ T 1870.21 .... ..... ... .... ..... T 819.11 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-tfl-mobilenet_v1_1.0_224/tempDir/86_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v2_300_float/tempDir/264_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 832.80 .... ..... ... .... ..... # 1 . .. ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 817.88 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-tfl-mobilenet_v1_1.0_224/tempDir/86_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1507.03 .... ..... ... .... ..... # 1 . .. T 1160.00 .... ..... ... .... ..... # 1 . .. T 819.00 .... ..... ... .... ..... # 1 . .. T 1158.49 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ T 1497.98 .... ..... ... .... ..... T 820.98 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 1, Name : cl-tfl-mobilenet_v1_1.0_224 , Total time : 5948.71, Offload Time : 0.00 , DDR RW MBs : 0.00, Output File : py_out_cl-tfl-mobilenet_v1_1.0_224_ADE_val_00001801.jpg ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v2_300_float/tempDir/264_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1464.62 .... ..... ... .... ..... # 1 . .. T 1159.07 .... ..... ... .... ..... # 1 . .. T 1466.14 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ T 1151.53 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v2_300_float/tempDir/264_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ************ Frame index 1 : Running float inference **************** T 1484.26 .... ..... ... .... ..... # 1 . .. T 1129.11 .... ..... ... .... ..... # 1 . .. T 1480.87 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ T 1121.32 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v2_300_float/tempDir/264_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1431.90 .... ..... ... .... ..... # 1 . .. T 1141.07 .... ..... ... .... ..... # 1 . .. T 1451.64 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v2_300_float/tempDir/264_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1143.71 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ T 1457.33 .... ..... ... .... ..... # 1 . .. ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 4, Name : od-tfl-ssd_mobilenet_v1_1_default_1 , Total time : 12360.07, Offload Time : 0.00 , DDR RW MBs : 0.00, Output File : py_out_od-tfl-ssd_mobilenet_v1_1_default_1_ADE_val_00001801.jpg T 1445.46 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 3, Name : od-tfl-ssd_mobilenet_v2_300_float , Total time : 13116.23, Offload Time : 0.00 , DDR RW MBs : 0.00, Output File : py_out_od-tfl-ssd_mobilenet_v2_300_float_ADE_val_00001801.jpg ************ Frame index 2 : Running fixed point mode for calibration **************** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-tfl-deeplabv3_mnv2_ade20k_float/tempDir/201_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 16349.89 .... ..... ... .... ..... # 1 . .. T 16338.69 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-tfl-deeplabv3_mnv2_ade20k_float/tempDir/201_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 10616.14 .... ..... ... .... ..... # 1 . .. T 10887.80 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-tfl-deeplabv3_mnv2_ade20k_float/tempDir/201_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 10677.69 .... ..... ... .... ..... # 1 . .. T 10428.37 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-tfl-deeplabv3_mnv2_ade20k_float/tempDir/201_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 9864.95 .... ..... ... .... ..... # 1 . .. T 9873.50 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-tfl-deeplabv3_mnv2_ade20k_float/tempDir/201_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 10216.42 .... ..... ... .... ..... # 1 . .. T 10214.27 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-tfl-deeplabv3_mnv2_ade20k_float/tempDir/201_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 11036.83 .... ..... ... .... ..... # 1 . .. T 11022.86 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found INFORMATION: [TIDL_ResizeLayer] ResizeBilinear_TIDL_0 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] ResizeBilinear_TIDL_1 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] ResizeBilinear Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] decoder/ResizeBilinear Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] ResizeBilinear_1 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. **************************************************** ** 5 WARNINGS 0 ERRORS ** **************************************************** Completed_Model : 2, Name : ss-tfl-deeplabv3_mnv2_ade20k_float , Total time : 86285.95, Offload Time : 0.00 , DDR RW MBs : 0.00, Output File : py_out_ss-tfl-deeplabv3_mnv2_ade20k_float_ADE_val_00001801.jpg Running 4 Models - ['cl-tfl-mobilenet_v1_1.0_224', 'ss-tfl-deeplabv3_mnv2_ade20k_float', 'od-tfl-ssd_mobilenet_v2_300_float', 'od-tfl-ssd_mobilenet_v1_1_default_1'] Running_Model : cl-tfl-mobilenet_v1_1.0_224 Running_Model : ss-tfl-deeplabv3_mnv2_ade20k_float Running_Model : od-tfl-ssd_mobilenet_v2_300_float Running_Model : od-tfl-ssd_mobilenet_v1_1_default_1 Number of subgraphs:1 , 34 nodes delegated out of 34 nodes Number of subgraphs:1 , 81 nodes delegated out of 81 nodes Number of subgraphs:1 , 107 nodes delegated out of 107 nodes Number of subgraphs:1 , 67 nodes delegated out of 67 nodes 0.0s: VX_ZONE_INIT:Enabled 0.10s: VX_ZONE_ERROR:Enabled 0.11s: VX_ZONE_WARNING:Enabled 0.0s: VX_ZONE_INIT:Enabled 0.11s: VX_ZONE_ERROR:Enabled 0.12s: VX_ZONE_WARNING:Enabled 0.376s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! 0.335s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.10s: VX_ZONE_ERROR:Enabled 0.12s: VX_ZONE_WARNING:Enabled 0.319s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.13s: VX_ZONE_ERROR:Enabled 0.14s: VX_ZONE_WARNING:Enabled 0.450s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! , 0 0.752788 warplane, military plane ,, 1 0.140961 missile ,, 2 0.085273 projectile, missile ,, 3 0.008170 cannon ,, 4 0.006913 aircraft carrier, carrier, flattop, attack aircraft carrier , Saving image to ../../../output_images/ Completed_Model : 1, Name : cl-tfl-mobilenet_v1_1.0_224 , Total time : 774.75, Offload Time : 774.74 , DDR RW MBs : 0.00, Output File : py_out_cl-tfl-mobilenet_v1_1.0_224_airshow.jpg Saving image to ../../../output_images/ Completed_Model : 4, Name : od-tfl-ssd_mobilenet_v1_1_default_1 , Total time : 1126.81, Offload Time : 1126.80 , DDR RW MBs : 0.00, Output File : py_out_od-tfl-ssd_mobilenet_v1_1_default_1_ADE_val_00001801.jpg Saving image to ../../../output_images/ Completed_Model : 3, Name : od-tfl-ssd_mobilenet_v2_300_float , Total time : 1364.21, Offload Time : 1364.20 , DDR RW MBs : 0.00, Output File : py_out_od-tfl-ssd_mobilenet_v2_300_float_ADE_val_00001801.jpg Saving image to ../../../output_images/ Completed_Model : 2, Name : ss-tfl-deeplabv3_mnv2_ade20k_float , Total time : 7200.87, Offload Time : 7200.87 , DDR RW MBs : 0.00, Output File : py_out_ss-tfl-deeplabv3_mnv2_ade20k_float_ADE_val_00001801.jpg Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider'] Running 4 Models - ['cl-ort-resnet18-v1', 'cl-ort-caffe_squeezenet_v1_1', 'ss-ort-deeplabv3lite_mobilenetv2', 'od-ort-ssd-lite_mobilenetv2_fpn'] Running_Model : cl-ort-resnet18-v1 Running_Model : cl-ort-caffe_squeezenet_v1_1 Running_Model : ss-ort-deeplabv3lite_mobilenetv2 Running_Model : od-ort-ssd-lite_mobilenetv2_fpn 2022-08-25 15:51:15.346438545 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346469857 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346498617 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346504094 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346509638 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346515708 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346520883 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346525708 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346530539 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346535698 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346540854 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346549972 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346557197 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346563989 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346578174 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346583251 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346589135 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346595132 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346602224 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:51:15.346607413 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 68, Total Nodes - 68 Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 124, Total Nodes - 124 TIDL Meta PipeLine (Proto) File : ../../../models/public/ssd-lite_mobilenetv2_fpn.prototxt ssd Number of OD backbone nodes = 159 Size of odBackboneNodeIds = 159 Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 494, Total Nodes - 494 Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 52, Total Nodes - 52 Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* INFORMATION: [TIDL_ResizeLayer] 571 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] 576 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 3 WARNINGS 0 ERRORS ** **************************************************** 0.0s: VX_ZONE_INIT:Enabled 0.10s: VX_ZONE_ERROR:Enabled 0.11s: VX_ZONE_WARNING:Enabled 0.314s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** 0.0s: VX_ZONE_INIT:Enabled 0.13s: VX_ZONE_ERROR:Enabled 0.14s: VX_ZONE_WARNING:Enabled 0.495s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! ********** Frame Index 1 : Running float inference ********** ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ ************** Frame index 1 : Running float import ************* Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . ..WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** 0.0s: VX_ZONE_INIT:Enabled 0.12s: VX_ZONE_ERROR:Enabled 0.13s: VX_ZONE_WARNING:Enabled 0.423s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! T 400.88 .... ..... ... .... ..... # 1 . .. T 390.75 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 387.55 .... ..... ... .... ..... # 1 . .. T 389.22 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ********** Frame Index 1 : Running float inference ********** T 391.64 .... ..... ... .... ..... # 1 . .. T 390.54 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 390.73 .... ..... ... .... ..... # 1 . ..TIDL Meta PipeLine (Proto) File : ../../../models/public/ssd-lite_mobilenetv2_fpn.prototxt ssd Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal T 397.12 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ************** Frame index 1 : Running float import ************* ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ INFORMATION: [TIDL_ResizeLayer] Resize_153 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] Resize_156 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target. **************************************************** ** 3 WARNINGS 0 ERRORS ** **************************************************** Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. 0.0s: VX_ZONE_INIT:Enabled 0.8s: VX_ZONE_ERROR:Enabled 0.31s: VX_ZONE_WARNING:Enabled 0.373s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ T 392.84 .... ..... ... .... ..... # 1 . .. Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 385.79 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ********** Frame Index 1 : Running float inference ********** T 382.72 .... ..... ... .... ..... # 1 . .. T 385.16 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 2, Name : cl-ort-caffe_squeezenet_v1_1 , Total time : 3597.14, Offload Time : 395.59 , DDR RW MBs : 0, Output File : py_out_cl-ort-caffe_squeezenet_v1_1_ADE_val_00001801.jpg T 1749.38 .... ..... ... .... ..... # 1 . .. ********** Frame Index 1 : Running float inference ********** T 1740.90 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 840.90 .... ..... ... .... ..... # 1 . .. T 850.99 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 843.80 .... ..... ... .... ..... # 1 . .. T 845.47 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 838.10 .... ..... ... .... ..... # 1 . .. T 835.33 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ T 3591.73 .... ..... ... .... ..... # 1 . .. Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 843.41 .... ..... ... .... ..... # 1 . .. T 5773.56 .... ..... ... .... ..... # 1 . .. T 839.60 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 841.50 .... ..... ... .... ..... # 1 . .. T 3559.90 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 833.52 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 1, Name : cl-ort-resnet18-v1 , Total time : 9664.37, Offload Time : 1779.34 , DDR RW MBs : 0, Output File : py_out_cl-ort-resnet18-v1_ADE_val_00001801.jpg T 5715.73 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 4766.19 .... ..... ... .... ..... # 1 . .. T 4885.42 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6968.61 .... ..... ... .... ..... # 1 . .. T 4669.00 .... ..... ... .... ..... # 1 . .. T 6950.81 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 4636.90 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 4544.35 .... ..... ... .... ..... # 1 . .. T 6180.20 .... ..... ... .... ..... # 1 . .. T 4497.14 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6157.44 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 4924.53 .... ..... ... .... ..... # 1 . .. T 6108.79 .... ..... ... .... ..... # 1 . .. T 4911.11 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6062.99 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 4869.97 .... ..... ... .... ..... # 1 . .. T 4896.26 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found INFORMATION: [TIDL_ResizeLayer] Resize_153 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] Resize_156 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. **************************************************** ** 2 WARNINGS 0 ERRORS ** **************************************************** Completed_Model : 4, Name : od-ort-ssd-lite_mobilenetv2_fpn , Total time : 31844.27, Offload Time : 3480.02 , DDR RW MBs : 0, Output File : py_out_od-ort-ssd-lite_mobilenetv2_fpn_ADE_val_00001801.jpg T 6064.10 .... ..... ... .... ..... # 1 . .. T 5916.88 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6735.29 .... ..... ... .... ..... # 1 . .. T 6796.08 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found INFORMATION: [TIDL_ResizeLayer] 571 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] 576 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. **************************************************** ** 2 WARNINGS 0 ERRORS ** **************************************************** Completed_Model : 3, Name : ss-ort-deeplabv3lite_mobilenetv2 , Total time : 44373.92, Offload Time : 5585.52 , DDR RW MBs : 0, Output File : py_out_ss-ort-deeplabv3lite_mobilenetv2_ADE_val_00001801.jpg Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider'] Running 4 Models - ['cl-ort-resnet18-v1', 'cl-ort-caffe_squeezenet_v1_1', 'ss-ort-deeplabv3lite_mobilenetv2', 'od-ort-ssd-lite_mobilenetv2_fpn'] Running_Model : cl-ort-resnet18-v1 Running_Model : cl-ort-caffe_squeezenet_v1_1 Running_Model : ss-ort-deeplabv3lite_mobilenetv2 Running_Model : od-ort-ssd-lite_mobilenetv2_fpn libtidl_onnxrt_EP loaded 0x33e4380 libtidl_onnxrt_EP loaded 0x35ecb60 2022-08-25 15:52:45.284875432 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284910812 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284917333 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284922754 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284928719 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284934566 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284939832 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284944830 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284949616 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284954795 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284960104 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284969026 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284974145 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284979596 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284984913 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284990114 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.284995727 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.285001187 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.285006365 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2022-08-25 15:52:45.285011602 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. libtidl_onnxrt_EP loaded 0x3480790 Final number of subgraphs created are : 1, - Offloaded Nodes - 68, Total Nodes - 68 0.0s: VX_ZONE_INIT:Enabled 0.16s: VX_ZONE_ERROR:Enabled 0.17s: VX_ZONE_WARNING:Enabled 0.343s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! libtidl_onnxrt_EP loaded 0x3d09920 Final number of subgraphs created are : 1, - Offloaded Nodes - 124, Total Nodes - 124 0.0s: VX_ZONE_INIT:Enabled 0.14s: VX_ZONE_ERROR:Enabled 0.16s: VX_ZONE_WARNING:Enabled 0.360s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! Final number of subgraphs created are : 1, - Offloaded Nodes - 52, Total Nodes - 52 Final number of subgraphs created are : 1, - Offloaded Nodes - 494, Total Nodes - 494 0.0s: VX_ZONE_INIT:Enabled 0.10s: VX_ZONE_ERROR:Enabled 0.11s: VX_ZONE_WARNING:Enabled 0.360s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.11s: VX_ZONE_ERROR:Enabled 0.12s: VX_ZONE_WARNING:Enabled 0.301s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! , 0 0.518756 warplane, military plane ,, 1 0.321064 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 2 0.108971 airliner ,, 3 0.020307 missile ,, 4 0.015969 projectile, missile , Saving image to ../../../output_images/ Completed_Model : 2, Name : cl-ort-caffe_squeezenet_v1_1 , Total time : 375.61, Offload Time : 375.57 , DDR RW MBs : 0, Output File : py_out_cl-ort-caffe_squeezenet_v1_1_airshow.jpg , 0 23.311415 warplane, military plane ,, 1 22.239624 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 2 18.488363 projectile, missile ,, 3 18.220415 missile ,, 4 15.540942 wing , Saving image to ../../../output_images/ Completed_Model : 1, Name : cl-ort-resnet18-v1 , Total time : 848.76, Offload Time : 848.73 , DDR RW MBs : 0, Output File : py_out_cl-ort-resnet18-v1_airshow.jpg Saving image to ../../../output_images/ Completed_Model : 4, Name : od-ort-ssd-lite_mobilenetv2_fpn , Total time : 3548.84, Offload Time : 3548.76 , DDR RW MBs : 0, Output File : py_out_od-ort-ssd-lite_mobilenetv2_fpn_ADE_val_00001801.jpg Saving image to ../../../output_images/ Completed_Model : 3, Name : ss-ort-deeplabv3lite_mobilenetv2 , Total time : 4593.90, Offload Time : 4593.85 , DDR RW MBs : 0, Output File : py_out_ss-ort-deeplabv3lite_mobilenetv2_ADE_val_00001801.jpg ../../../models/public/mobilenetv2-1.0.onnx Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... Running graph on host for tensor data collection... Importing subgraph into TIDL... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 300.32 .... ..... ... .... ..... # 1 . .. T 298.97 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 445.31 .... ..... ... .... ..... # 1 . .. T 444.84 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 442.81 .... ..... ... .... ..... # 1 . .. T 447.80 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 452.45 .... ..... ... .... ..... # 1 . .. T 450.65 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 440.97 .... ..... ... .... ..... # 1 . .. T 442.89 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 438.36 .... ..... ... .... ..... # 1 . .. T 438.65 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 445.37 .... ..... ... .... ..... # 1 . .. T 445.72 .... ..... ... .... ..... ***************** Calibration iteration number 5 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 442.21 .... ..... ... .... ..... # 1 . .. T 441.26 .... ..... ... .... ..... ***************** Calibration iteration number 6 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 438.68 .... ..... ... .... ..... # 1 . .. T 440.58 .... ..... ... .... ..... ***************** Calibration iteration number 7 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 438.44 .... ..... ... .... ..... # 1 . .. T 439.99 .... ..... ... .... ..... ***************** Calibration iteration number 8 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 437.38 .... ..... ... .... ..... # 1 . .. T 439.11 .... ..... ... .... ..... ***************** Calibration iteration number 9 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-onnx_mobilenetv2 Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. Running graph on host for tensor data collection... Importing subgraph into TIDL... Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5686.90 .... ..... ... .... ..... # 1 . .. T 5683.92 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5931.13 .... ..... ... .... ..... # 1 . .. T 5933.63 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5905.92 .... ..... ... .... ..... # 1 . .. T 5947.85 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5958.90 .... ..... ... .... ..... # 1 . .. T 5981.07 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5978.14 .... ..... ... .... ..... # 1 . .. T 5944.94 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5962.77 .... ..... ... .... ..... # 1 . .. T 5943.00 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-tflite_inceptionnetv3 ../../../models/public/mobilenetv2-1.0.onnx Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... Running graph on host for tensor data collection... Importing subgraph into TIDL... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 296.05 .... ..... ... .... ..... # 1 . .. T 292.00 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 437.83 .... ..... ... .... ..... # 1 . .. T 439.32 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 434.37 .... ..... ... .... ..... # 1 . .. T 440.45 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 441.38 .... ..... ... .... ..... # 1 . .. T 444.97 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 442.69 .... ..... ... .... ..... # 1 . .. T 440.69 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 440.89 .... ..... ... .... ..... # 1 . .. T 439.32 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 438.87 .... ..... ... .... ..... # 1 . .. T 436.76 .... ..... ... .... ..... ***************** Calibration iteration number 5 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 438.74 .... ..... ... .... ..... # 1 . .. T 443.14 .... ..... ... .... ..... ***************** Calibration iteration number 6 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 438.43 .... ..... ... .... ..... # 1 . .. T 437.28 .... ..... ... .... ..... ***************** Calibration iteration number 7 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 434.27 .... ..... ... .... ..... # 1 . .. T 433.41 .... ..... ... .... ..... ***************** Calibration iteration number 8 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 434.59 .... ..... ... .... ..... # 1 . .. T 434.95 .... ..... ... .... ..... ***************** Calibration iteration number 9 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-onnx_mobilenetv2_device Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. Running graph on host for tensor data collection... Importing subgraph into TIDL... Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5643.09 .... ..... ... .... ..... # 1 . .. T 5661.58 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5876.77 .... ..... ... .... ..... # 1 . .. T 5863.65 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5871.34 .... ..... ... .... ..... # 1 . .. T 5900.75 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5897.96 .... ..... ... .... ..... # 1 . .. T 5859.27 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5906.27 .... ..... ... .... ..... # 1 . .. T 5927.52 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5955.96 .... ..... ... .... ..... # 1 . .. T 5916.10 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation substitute string tidl_net_ not found **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-tflite_inceptionnetv3_device Traceback (most recent call last): File "tvm_compilation_mxnet_example.py", line 37, in from gluoncv import model_zoo ModuleNotFoundError: No module named 'gluoncv' Running Inference on Model - ../../../model-artifacts/cl-dlr-tflite_inceptionnetv3 2022-08-25 16:56:47,059 INFO Could not find libdlr.so in model artifact. Using dlr from /home/yeverino/Documents/git/fordos_tilinux64_host/venv/dlr/libdlr.so 0.0s: VX_ZONE_INIT:Enabled 0.9s: VX_ZONE_ERROR:Enabled 0.10s: VX_ZONE_WARNING:Enabled 0.322s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! Processing time in ms : 5816.4 , 0 0.490434 warplane, military plane ,, 1 0.351332 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 2 0.019505 projectile, missile ,, 3 0.017461 missile ,, 4 0.002945 wing , Saving image to ../../../output_images/ Completed_Model : 1, Name : cl-dlr-tflite_inceptionnetv3 , Total time : 5816.41, Offload Time : 5816.41 , DDR RW MBs : 0, Output File : py_out_cl-dlr-tflite_inceptionnetv3_airshow.jpg Running Inference on Model - ../../../model-artifacts/cl-dlr-onnx_mobilenetv2 2022-08-25 16:57:05,279 INFO Could not find libdlr.so in model artifact. Using dlr from /home/yeverino/Documents/git/fordos_tilinux64_host/venv/dlr/libdlr.so 17.626766s: VX_ZONE_INIT:Enabled 17.626780s: VX_ZONE_ERROR:Enabled 17.626781s: VX_ZONE_WARNING:Enabled 17.626890s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!! Processing time in ms : 404.3 , 0 12.805455 missile ,, 1 12.437883 projectile, missile ,, 2 11.810268 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 3 11.685690 warplane, military plane ,, 4 10.086417 airship, dirigible , Saving image to ../../../output_images/ Completed_Model : 2, Name : cl-dlr-onnx_mobilenetv2 , Total time : 404.31, Offload Time : 404.31 , DDR RW MBs : 0, Output File : py_out_cl-dlr-onnx_mobilenetv2_airshow.jpg (venv) yeverino@yeverino-pc:~/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools$