|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-88-g982f5c2 built Wed Mar 1 18:42:41 UTC 2023)          |
| SoC    | J721S2 SR1.0                                                          |
| SYSFW  | ABI: 3.1 (firmware version 0x0008 '8.6.3--v08.06.03 (Chill Capybar)') |
|--------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                                        | Status              | Clock Frequency |
|--------------------------------------------------------------------------------------------------------------------------------------------------|
|     4     |     0    | DEV_A72SS0_ARM_CLK_CLK                                                            | CLK_STATE_READY     | 2000000000      |
|     4     |     1    | DEV_A72SS0_MSMC_CLK                                                               | CLK_STATE_READY     | 1000000000      |
|     4     |     2    | DEV_A72SS0_PLL_CTRL_CLK                                                           | CLK_STATE_READY     | 500000000       |
|     4     |     6    | DEV_A72SS0_A72_DIVH_CLK8_OBSCLK_OUT_CLK                                           | CLK_STATE_READY     | 0               |
|   202     |     0    | DEV_A72SS0_CORE0_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 2000000000      |
|   203     |     0    | DEV_A72SS0_CORE1_ARM_CLK_CLK                                                      | CLK_STATE_READY     | 2000000000      |
|   134     |     0    | DEV_AGGR_ATB0_DBG_CLK                                                             | CLK_STATE_READY     | 250000000       |
|     2     |     0    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT                                                    | CLK_STATE_READY     | 0               |
|     2     |     1    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1                                                  | CLK_STATE_READY     | 0               |
|     2     |     2    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2                                                  | CLK_STATE_READY     | 0               |
|     2     |     3    | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3                                                  | CLK_STATE_READY     | 0               |
|     2     |     4    | DEV_ATL0_ATL_CLK                                                                  | CLK_STATE_READY     | 294912000       |
|     2     |     5    | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 294912000       |
|     2     |     6    | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                         | CLK_STATE_READY     | 200000000       |
|     2     |     9    | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK                       | CLK_STATE_READY     | 200000000       |
|     2     |    10    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                               | CLK_STATE_READY     | 0               |
|     2     |    11    | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                   | CLK_STATE_READY     | 0               |
|     2     |    13    | DEV_ATL0_VBUS_CLK                                                                 | CLK_STATE_READY     | 250000000       |
|     2     |    14    | DEV_ATL0_ATL_IO_PORT_AWS                                                          | CLK_STATE_READY     | 0               |
|     2     |    15    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |    16    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |    17    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
|     2     |    18    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
|     2     |    19    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
|     2     |    27    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
|     2     |    28    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0                 | CLK_STATE_READY     | 0               |
|     2     |    29    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |    30    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |    31    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |    39    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|     2     |    40    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               |
|     2     |    47    | DEV_ATL0_ATL_IO_PORT_AWS_1                                                        | CLK_STATE_READY     | 0               |
|     2     |    48    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    49    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    50    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    51    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    52    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    60    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    61    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    62    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    63    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    64    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    72    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|     2     |    73    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
|     2     |    80    | DEV_ATL0_ATL_IO_PORT_AWS_2                                                        | CLK_STATE_READY     | 0               |
|     2     |    81    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    82    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    83    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    84    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    85    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    93    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    94    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |    95    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    96    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |    97    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   105    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   106    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   113    | DEV_ATL0_ATL_IO_PORT_AWS_3                                                        | CLK_STATE_READY     | 0               |
|     2     |   114    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   115    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   116    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |   117    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |   118    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |   126    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |   127    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT_DUP0               | CLK_STATE_READY     | 0               |
|     2     |   128    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   129    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   130    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   138    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   139    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   146    | DEV_ATL0_ATL_IO_PORT_BWS                                                          | CLK_STATE_READY     | 0               |
|     2     |   147    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   148    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   149    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   150    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   151    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   159    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   160    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   161    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   162    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   163    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                      | CLK_STATE_READY     | 0               |
|     2     |   171    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|     2     |   172    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                     | CLK_STATE_READY     | 0               |
|     2     |   179    | DEV_ATL0_ATL_IO_PORT_BWS_1                                                        | CLK_STATE_READY     | 0               |
|     2     |   180    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   181    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   182    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   183    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   184    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   192    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   193    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   194    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   195    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   196    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   204    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   205    | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   212    | DEV_ATL0_ATL_IO_PORT_BWS_2                                                        | CLK_STATE_READY     | 0               |
|     2     |   213    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   214    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   215    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   216    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   217    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   225    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   226    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   227    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   228    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   229    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   237    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   238    | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   245    | DEV_ATL0_ATL_IO_PORT_BWS_3                                                        | CLK_STATE_READY     | 0               |
|     2     |   246    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   247    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   248    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   249    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   250    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSR_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   258    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_0_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   259    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_1_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   260    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_2_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   261    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_3_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   262    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_MCASP_MAIN_4_MCASP_AFSX_POUT                    | CLK_STATE_READY     | 0               |
|     2     |   270    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|     2     |   271    | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                   | CLK_STATE_READY     | 0               |
|   157     |     1    | DEV_BOARD0_DSI0_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |     2    | DEV_BOARD0_I2C4_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |     4    | DEV_BOARD0_CSI0_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |     5    | DEV_BOARD0_CSI0_RXCLKP_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |     6    | DEV_BOARD0_HYP0_TXPMCLK_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |     7    | DEV_BOARD0_MCAN1_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |     8    | DEV_BOARD0_MCAN17_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |     9    | DEV_BOARD0_MMC1_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |    10    | DEV_BOARD0_MCU_OBSCLK0_IN                                                         | CLK_STATE_READY     | 1000000000      |
|   157     |    11    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0                              | CLK_STATE_READY     | 1000000000      |
|   157     |    12    | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   157     |    43    | DEV_BOARD0_I2C0_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |    44    | DEV_BOARD0_SPI7_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |    45    | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT                                                  | CLK_STATE_READY     | 0               |
|   157     |    46    | DEV_BOARD0_MCASP3_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |    47    | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT                                                  | CLK_STATE_READY     | 0               |
|   157     |    48    | DEV_BOARD0_MCU_OSPI0_DQS_OUT                                                      | CLK_STATE_READY     | 0               |
|   157     |    49    | DEV_BOARD0_HYP0_TXFLCLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |    50    | DEV_BOARD0_MCU_OSPI0_LBCLKO_OUT                                                   | CLK_STATE_READY     | 0               |
|   157     |    51    | DEV_BOARD0_MCASP3_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |    52    | DEV_BOARD0_HYP0_RXPMCLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |    54    | DEV_BOARD0_MCASP1_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |    55    | DEV_BOARD0_MCU_SPI1_CLK_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |    56    | DEV_BOARD0_MCAN9_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |    57    | DEV_BOARD0_I2C6_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |    58    | DEV_BOARD0_MCU_SPI0_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |    59    | DEV_BOARD0_OBSCLK1_IN                                                             | CLK_STATE_READY     | 500000000       |
|   157     |    60    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 500000000       |
|   157     |    61    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 192000000       |
|   157     |    62    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 600000000       |
|   157     |    63    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 250000000       |
|   157     |    64    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 196608000       |
|   157     |    65    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 400000000       |
|   157     |    66    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 800000000       |
|   157     |    67    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066665000      |
|   157     |    72    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
|   157     |    73    | DEV_BOARD0_OBSCLK1_IN_PARENT_OBSCLK1_MUX_OUT0                                     | CLK_STATE_READY     | 0               |
|   157     |    74    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1000000000      |
|   157     |    76    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
|   157     |    77    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
|   157     |    79    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 600000000       |
|   157     |    85    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 480000000       |
|   157     |    86    | DEV_BOARD0_OBSCLK1_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                      | CLK_STATE_READY     | 0               |
|   157     |    87    | DEV_BOARD0_OBSCLK1_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK         | CLK_STATE_READY     | 12500000        |
|   157     |    88    | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                              | CLK_STATE_READY     | 32768           |
|   157     |    89    | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0               | CLK_STATE_READY     | 500000000       |
|   157     |    90    | DEV_BOARD0_OBSCLK1_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                               | CLK_STATE_READY     | 0               |
|   157     |    91    | DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 19200000        |
|   157     |    92    | DEV_BOARD0_MCU_OSPI1_LBCLKO_OUT                                                   | CLK_STATE_READY     | 0               |
|   157     |    93    | DEV_BOARD0_MCASP3_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |    95    | DEV_BOARD0_MCASP2_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |    96    | DEV_BOARD0_TRC_CLK_IN                                                             | CLK_STATE_READY     | 0               |
|   157     |   100    | DEV_BOARD0_CSI1_RXCLKN_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   102    | DEV_BOARD0_MCASP0_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   103    | DEV_BOARD0_MCU_OSPI0_CLK_IN                                                       | CLK_STATE_READY     | 0               |
|   157     |   105    | DEV_BOARD0_GPMC0_FCLK_MUX_IN                                                      | CLK_STATE_READY     | 133333333       |
|   157     |   106    | DEV_BOARD0_MCU_SPI0_CLK_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   108    | DEV_BOARD0_MCU_RGMII1_RXC_OUT                                                     | CLK_STATE_READY     | 0               |
|   157     |   109    | DEV_BOARD0_MCASP0_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   110    | DEV_BOARD0_CSI1_RXCLKP_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   111    | DEV_BOARD0_MCU_SYSCLKOUT0_IN                                                      | CLK_STATE_READY     | 250000000       |
|   157     |   112    | DEV_BOARD0_SPI5_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   113    | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT                                                  | CLK_STATE_READY     | 0               |
|   157     |   114    | DEV_BOARD0_SPI0_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   116    | DEV_BOARD0_SPI6_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   117    | DEV_BOARD0_I2C1_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   118    | DEV_BOARD0_DSI1_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |   119    | DEV_BOARD0_MCAN0_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   120    | DEV_BOARD0_MCASP0_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   121    | DEV_BOARD0_RMII_REF_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   123    | DEV_BOARD0_MCAN14_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   125    | DEV_BOARD0_MCU_I2C0_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   126    | DEV_BOARD0_SPI6_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   128    | DEV_BOARD0_MCASP3_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   129    | DEV_BOARD0_MCU_SPI1_CLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   130    | DEV_BOARD0_SERDES0_REFCLK_P_IN                                                    | CLK_STATE_READY     | 0               |
|   157     |   131    | DEV_BOARD0_SERDES0_REFCLK_P_OUT                                                   | CLK_STATE_READY     | 0               |
|   157     |   132    | DEV_BOARD0_MCASP1_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   134    | DEV_BOARD0_MCASP1_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   135    | DEV_BOARD0_SPI1_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   136    | DEV_BOARD0_I2C3_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   137    | DEV_BOARD0_MCU_I2C0_SCL_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   138    | DEV_BOARD0_HYP1_TXPMCLK_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   139    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN                                                   | CLK_STATE_NOT_READY | 0               |
|   157     |   140    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   141    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   142    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   143    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   144    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   152    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   153    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   154    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   155    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   156    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   164    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT           | CLK_STATE_NOT_READY | 0               |
|   157     |   165    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1         | CLK_STATE_NOT_READY | 0               |
|   157     |   166    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2         | CLK_STATE_NOT_READY | 0               |
|   157     |   167    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3         | CLK_STATE_NOT_READY | 0               |
|   157     |   168    | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK          | CLK_STATE_READY     | 196608000       |
|   157     |   173    | DEV_BOARD0_MCASP2_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   175    | DEV_BOARD0_MMC1_CLKLB_OUT                                                         | CLK_STATE_READY     | 0               |
|   157     |   176    | DEV_BOARD0_WKUP_I2C0_SCL_OUT                                                      | CLK_STATE_READY     | 0               |
|   157     |   177    | DEV_BOARD0_SYSCLKOUT0_IN                                                          | CLK_STATE_READY     | 125000000       |
|   157     |   178    | DEV_BOARD0_I2C1_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   179    | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN                                                    | CLK_STATE_READY     | 0               |
|   157     |   180    | DEV_BOARD0_SPI3_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   181    | DEV_BOARD0_MCAN13_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   182    | DEV_BOARD0_WKUP_I2C0_SCL_IN                                                       | CLK_STATE_READY     | 0               |
|   157     |   183    | DEV_BOARD0_DSI1_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |   184    | DEV_BOARD0_CPTS0_RFT_CLK_OUT                                                      | CLK_STATE_READY     | 0               |
|   157     |   185    | DEV_BOARD0_MCU_I2C1_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   186    | DEV_BOARD0_MCASP0_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   187    | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN                                                    | CLK_STATE_READY     | 0               |
|   157     |   188    | DEV_BOARD0_MCASP0_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   190    | DEV_BOARD0_MCU_I3C0_SDA_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   191    | DEV_BOARD0_MCASP0_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   192    | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT                                                  | CLK_STATE_READY     | 0               |
|   157     |   193    | DEV_BOARD0_MCAN3_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   194    | DEV_BOARD0_MMC1_CLKLB_IN                                                          | CLK_STATE_READY     | 0               |
|   157     |   195    | DEV_BOARD0_MCASP2_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   198    | DEV_BOARD0_HFOSC1_CLK_OUT                                                         | CLK_STATE_READY     | 0               |
|   157     |   199    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   200    | DEV_BOARD0_MCAN4_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   201    | DEV_BOARD0_MCASP4_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   202    | DEV_BOARD0_CSI1_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |   203    | DEV_BOARD0_MCASP3_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   204    | DEV_BOARD0_LED_CLK_OUT                                                            | CLK_STATE_READY     | 0               |
|   157     |   206    | DEV_BOARD0_MCAN7_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   207    | DEV_BOARD0_MCU_MDIO0_MDC_IN                                                       | CLK_STATE_READY     | 0               |
|   157     |   209    | DEV_BOARD0_MCASP4_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   210    | DEV_BOARD0_I2C2_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   212    | DEV_BOARD0_SPI1_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   213    | DEV_BOARD0_HYP1_RXPMCLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   214    | DEV_BOARD0_MCU_HYPERBUS0_CK_IN                                                    | CLK_STATE_READY     | 0               |
|   157     |   215    | DEV_BOARD0_MCASP2_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   216    | DEV_BOARD0_MCASP3_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   217    | DEV_BOARD0_MCAN15_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   218    | DEV_BOARD0_SPI0_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   219    | DEV_BOARD0_MCAN12_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   220    | DEV_BOARD0_MCASP2_ACLKR_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   221    | DEV_BOARD0_MCU_CLKOUT0_IN                                                         | CLK_STATE_READY     | 50000000        |
|   157     |   222    | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5                | CLK_STATE_READY     | 50000000        |
|   157     |   223    | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10               | CLK_STATE_READY     | 25000000        |
|   157     |   224    | DEV_BOARD0_MCU_OSPI1_DQS_OUT                                                      | CLK_STATE_READY     | 0               |
|   157     |   226    | DEV_BOARD0_CSI0_RXCLKN_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   227    | DEV_BOARD0_TCK_OUT                                                                | CLK_STATE_READY     | 0               |
|   157     |   228    | DEV_BOARD0_CSI1_TXCLKN_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |   229    | DEV_BOARD0_MCU_MCAN0_RX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   230    | DEV_BOARD0_MCASP4_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   231    | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN                                                   | CLK_STATE_READY     | 0               |
|   157     |   232    | DEV_BOARD0_MCASP4_ACLKR_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   233    | DEV_BOARD0_MCAN11_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   234    | DEV_BOARD0_I2C5_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   235    | DEV_BOARD0_MCU_I2C1_SCL_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   236    | DEV_BOARD0_I2C0_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   237    | DEV_BOARD0_MCAN6_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   238    | DEV_BOARD0_MCU_I3C0_SCL_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   239    | DEV_BOARD0_MMC1_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   240    | DEV_BOARD0_VOUT0_EXTPCLKIN_OUT                                                    | CLK_STATE_READY     | 0               |
|   157     |   241    | DEV_BOARD0_EXT_REFCLK1_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   242    | DEV_BOARD0_I2C5_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   243    | DEV_BOARD0_MCAN16_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   244    | DEV_BOARD0_MCU_RGMII1_TXC_IN                                                      | CLK_STATE_READY     | 0               |
|   157     |   245    | DEV_BOARD0_MCASP4_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   246    | DEV_BOARD0_GPMC0_CLKOUT_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   247    | DEV_BOARD0_GPMC0_CLK_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   248    | DEV_BOARD0_I2C6_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   249    | DEV_BOARD0_I2C4_SCL_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   250    | DEV_BOARD0_SERDES0_REFCLK_N_IN                                                    | CLK_STATE_READY     | 0               |
|   157     |   251    | DEV_BOARD0_OBSCLK0_IN                                                             | CLK_STATE_READY     | 500000000       |
|   157     |   252    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 500000000       |
|   157     |   253    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 192000000       |
|   157     |   254    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 600000000       |
|   157     |   255    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 250000000       |
|   157     |   256    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 196608000       |
|   157     |   257    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_5_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 400000000       |
|   157     |   258    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK                    | CLK_STATE_READY     | 800000000       |
|   157     |   259    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_26_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066665000      |
|   157     |   264    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1066500000      |
|   157     |   265    | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0                                     | CLK_STATE_READY     | 0               |
|   157     |   266    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_14_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 1000000000      |
|   157     |   268    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
|   157     |   269    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 594000000       |
|   157     |   271    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 600000000       |
|   157     |   277    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK                   | CLK_STATE_READY     | 480000000       |
|   157     |   278    | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                      | CLK_STATE_READY     | 0               |
|   157     |   279    | DEV_BOARD0_OBSCLK0_IN_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK         | CLK_STATE_READY     | 12500000        |
|   157     |   280    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT                              | CLK_STATE_READY     | 32768           |
|   157     |   281    | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0               | CLK_STATE_READY     | 500000000       |
|   157     |   282    | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT                               | CLK_STATE_READY     | 0               |
|   157     |   283    | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                              | CLK_STATE_READY     | 19200000        |
|   157     |   284    | DEV_BOARD0_MCAN2_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   285    | DEV_BOARD0_MCASP2_ACLKX_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   287    | DEV_BOARD0_MCU_EXT_REFCLK0_OUT                                                    | CLK_STATE_READY     | 0               |
|   157     |   288    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   289    | DEV_BOARD0_SPI2_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   290    | DEV_BOARD0_HYP0_RXFLCLK_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   291    | DEV_BOARD0_SPI3_CLK_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   292    | DEV_BOARD0_MCASP1_AFSR_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   293    | DEV_BOARD0_I2C2_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   294    | DEV_BOARD0_MCAN10_RX_OUT                                                          | CLK_STATE_READY     | 0               |
|   157     |   295    | DEV_BOARD0_MCAN5_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   296    | DEV_BOARD0_MCU_I3C0_SCL_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   297    | DEV_BOARD0_MCU_MCAN1_RX_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   299    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN                                                   | CLK_STATE_NOT_READY | 0               |
|   157     |   300    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   301    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   302    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   303    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   304    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT             | CLK_STATE_READY     | 0               |
|   157     |   312    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   313    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   314    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   315    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   316    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT             | CLK_STATE_READY     | 0               |
|   157     |   324    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT           | CLK_STATE_NOT_READY | 0               |
|   157     |   325    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1         | CLK_STATE_NOT_READY | 0               |
|   157     |   326    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2         | CLK_STATE_NOT_READY | 0               |
|   157     |   327    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3         | CLK_STATE_NOT_READY | 0               |
|   157     |   328    | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK          | CLK_STATE_READY     | 196608000       |
|   157     |   333    | DEV_BOARD0_HYP1_TXFLCLK_OUT                                                       | CLK_STATE_READY     | 0               |
|   157     |   334    | DEV_BOARD0_SPI5_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   335    | DEV_BOARD0_I2C3_SCL_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   336    | DEV_BOARD0_MCAN8_RX_OUT                                                           | CLK_STATE_READY     | 0               |
|   157     |   338    | DEV_BOARD0_RGMII1_RXC_OUT                                                         | CLK_STATE_READY     | 0               |
|   157     |   339    | DEV_BOARD0_SERDES0_REFCLK_N_OUT                                                   | CLK_STATE_READY     | 0               |
|   157     |   340    | DEV_BOARD0_CSI0_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |   341    | DEV_BOARD0_SPI7_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   342    | DEV_BOARD0_RGMII1_TXC_IN                                                          | CLK_STATE_READY     | 0               |
|   157     |   343    | DEV_BOARD0_HYP1_RXFLCLK_IN                                                        | CLK_STATE_READY     | 0               |
|   157     |   344    | DEV_BOARD0_MDIO1_MDC_IN                                                           | CLK_STATE_READY     | 0               |
|   157     |   345    | DEV_BOARD0_SPI2_CLK_IN                                                            | CLK_STATE_READY     | 0               |
|   157     |   346    | DEV_BOARD0_DSI0_TXCLKP_IN                                                         | CLK_STATE_READY     | 0               |
|   157     |   347    | DEV_BOARD0_MCASP4_AFSX_OUT                                                        | CLK_STATE_READY     | 0               |
|   157     |   352    | DEV_BOARD0_VOUT0_PCLK_IN                                                          | CLK_STATE_READY     | 600000000       |
|   150     |     0    | DEV_CMPEVENT_INTRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
|   179     |     0    | DEV_CODEC0_VPU_PCLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
|   179     |     1    | DEV_CODEC0_VPU_BCLK_CLK                                                           | CLK_STATE_READY     | 400000000       |
|   179     |     2    | DEV_CODEC0_VPU_CCLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
|   179     |     3    | DEV_CODEC0_VPU_ACLK_CLK                                                           | CLK_STATE_READY     | 600000000       |
|     8     |     0    | DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_CLK                                             | CLK_STATE_READY     | 1000000000      |
|     8     |     1    | DEV_COMPUTE_CLUSTER0_C71SS0_0_PLL_CTRL_CLK                                        | CLK_STATE_READY     | 500000000       |
|     8     |     3    | DEV_COMPUTE_CLUSTER0_C71SS0_0_C7X_DIVH_CLK4_OBSCLK_OUT_CLK                        | CLK_STATE_READY     | 0               |
|    11     |     0    | DEV_COMPUTE_CLUSTER0_C71SS1_0_C7X_CLK                                             | CLK_STATE_READY     | 1000000000      |
|    11     |     1    | DEV_COMPUTE_CLUSTER0_C71SS1_0_PLL_CTRL_CLK                                        | CLK_STATE_READY     | 500000000       |
|    14     |     1    | DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK                                                | CLK_STATE_READY     | 500000000       |
|    15     |     1    | DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK                                           | CLK_STATE_READY     | 500000000       |
|    15     |     2    | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK                                      | CLK_STATE_READY     | 500000000       |
|    18     |     0    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK1_CLK_CLK                                    | CLK_STATE_READY     | 1000000000      |
|    18     |     1    | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_0_CLK2_CLK_CLK                                    | CLK_STATE_READY     | 500000000       |
|    25     |     0    | DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_0_MSMC_CLK1_CLK                               | CLK_STATE_READY     | 500000000       |
|    26     |     0    | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK                                            | CLK_STATE_READY     | 500000000       |
|    27     |     3    | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVP_CLK1_CLK_CLK                               | CLK_STATE_READY     | 1000000000      |
|    27     |     4    | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_0_DIVH_CLK2_CLK_CLK                               | CLK_STATE_READY     | 500000000       |
|    28     |     0    | DEV_CPSW1_MDIO_MDCLK_O                                                            | CLK_STATE_READY     | 0               |
|    28     |     1    | DEV_CPSW1_CPTS_GENF0                                                              | CLK_STATE_READY     | 0               |
|    28     |     3    | DEV_CPSW1_CPTS_RFT_CLK                                                            | CLK_STATE_READY     | 200000000       |
|    28     |     4    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                   | CLK_STATE_READY     | 200000000       |
|    28     |     5    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 250000000       |
|    28     |     6    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
|    28     |     7    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                           | CLK_STATE_READY     | 0               |
|    28     |     8    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                         | CLK_STATE_READY     | 0               |
|    28     |     9    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               |
|    28     |    10    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|    28     |    11    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|    28     |    12    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|    28     |    13    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|    28     |    18    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 500000000       |
|    28     |    19    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK           | CLK_STATE_READY     | 500000000       |
|    28     |    20    | DEV_CPSW1_GMII1_MR_CLK                                                            | CLK_STATE_READY     | 25000000        |
|    28     |    21    | DEV_CPSW1_GMII_RFT_CLK                                                            | CLK_STATE_READY     | 125000000       |
|    28     |    22    | DEV_CPSW1_RGMII1_RXC_I                                                            | CLK_STATE_READY     | 0               |
|    28     |    26    | DEV_CPSW1_RMII_MHZ_50_CLK                                                         | CLK_STATE_READY     | 0               |
|    28     |    27    | DEV_CPSW1_RGMII1_TXC_O                                                            | CLK_STATE_READY     | 0               |
|    28     |    28    | DEV_CPSW1_CPPI_CLK_CLK                                                            | CLK_STATE_READY     | 320000000       |
|    28     |    29    | DEV_CPSW1_RGMII_MHZ_5_CLK                                                         | CLK_STATE_READY     | 5000000         |
|    28     |    30    | DEV_CPSW1_GMII1_MT_CLK                                                            | CLK_STATE_READY     | 25000000        |
|    28     |    32    | DEV_CPSW1_RGMII_MHZ_50_CLK                                                        | CLK_STATE_READY     | 50000000        |
|    28     |    33    | DEV_CPSW1_RGMII_MHZ_250_CLK                                                       | CLK_STATE_READY     | 250000000       |
|    36     |     0    | DEV_CPT2_AGGR0_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
|    30     |     0    | DEV_CPT2_AGGR1_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
|    32     |     0    | DEV_CPT2_AGGR2_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
|    34     |     0    | DEV_CPT2_AGGR3_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
|    33     |     0    | DEV_CPT2_AGGR4_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
|    31     |     0    | DEV_CPT2_AGGR5_VCLK_CLK                                                           | CLK_STATE_READY     | 250000000       |
|   136     |     0    | DEV_CSI_PSILSS0_MAIN_CLK                                                          | CLK_STATE_READY     | 125000000       |
|    38     |     0    | DEV_CSI_RX_IF0_PPI_D_RX_ULPS_ESC                                                  | CLK_STATE_READY     | 0               |
|    38     |     1    | DEV_CSI_RX_IF0_VBUS_CLK_CLK                                                       | CLK_STATE_READY     | 250000000       |
|    38     |     2    | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK                                                    | CLK_STATE_READY     | 0               |
|    38     |     3    | DEV_CSI_RX_IF0_MAIN_CLK_CLK                                                       | CLK_STATE_READY     | 500000000       |
|    38     |     4    | DEV_CSI_RX_IF0_VP_CLK_CLK                                                         | CLK_STATE_READY     | 720000000       |
|    39     |     0    | DEV_CSI_RX_IF1_PPI_D_RX_ULPS_ESC                                                  | CLK_STATE_READY     | 0               |
|    39     |     1    | DEV_CSI_RX_IF1_VBUS_CLK_CLK                                                       | CLK_STATE_READY     | 250000000       |
|    39     |     2    | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK                                                    | CLK_STATE_READY     | 0               |
|    39     |     3    | DEV_CSI_RX_IF1_MAIN_CLK_CLK                                                       | CLK_STATE_READY     | 500000000       |
|    39     |     4    | DEV_CSI_RX_IF1_VP_CLK_CLK                                                         | CLK_STATE_READY     | 720000000       |
|    40     |     1    | DEV_CSI_TX_IF_V2_0_VBUS_CLK_CLK                                                   | CLK_STATE_READY     | 250000000       |
|    40     |     2    | DEV_CSI_TX_IF_V2_0_MAIN_CLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
|    40     |     3    | DEV_CSI_TX_IF_V2_0_DPHY_TXBYTECLKHS_CL_CLK                                        | CLK_STATE_READY     | 0               |
|    40     |     5    | DEV_CSI_TX_IF_V2_0_ESC_CLK_CLK                                                    | CLK_STATE_READY     | 20000000        |
|    41     |     1    | DEV_CSI_TX_IF_V2_1_VBUS_CLK_CLK                                                   | CLK_STATE_READY     | 250000000       |
|    41     |     2    | DEV_CSI_TX_IF_V2_1_MAIN_CLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
|    41     |     3    | DEV_CSI_TX_IF_V2_1_DPHY_TXBYTECLKHS_CL_CLK                                        | CLK_STATE_READY     | 0               |
|    41     |     5    | DEV_CSI_TX_IF_V2_1_ESC_CLK_CLK                                                    | CLK_STATE_READY     | 20000000        |
|    43     |     0    | DEV_DCC0_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    43     |     1    | DEV_DCC0_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    43     |     2    | DEV_DCC0_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 133333333       |
|    43     |     3    | DEV_DCC0_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 80000000        |
|    43     |     4    | DEV_DCC0_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    43     |     5    | DEV_DCC0_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
|    43     |     6    | DEV_DCC0_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 500000000       |
|    43     |     7    | DEV_DCC0_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
|    43     |     8    | DEV_DCC0_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    43     |     9    | DEV_DCC0_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    43     |    10    | DEV_DCC0_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    43     |    11    | DEV_DCC0_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    43     |    12    | DEV_DCC0_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    44     |     0    | DEV_DCC1_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 50000000        |
|    44     |     1    | DEV_DCC1_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    44     |     2    | DEV_DCC1_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    44     |     3    | DEV_DCC1_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 192000000       |
|    44     |     4    | DEV_DCC1_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 320000000       |
|    44     |     5    | DEV_DCC1_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 192000000       |
|    44     |     6    | DEV_DCC1_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 192000000       |
|    44     |     7    | DEV_DCC1_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    44     |     8    | DEV_DCC1_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    44     |     9    | DEV_DCC1_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    44     |    10    | DEV_DCC1_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    44     |    11    | DEV_DCC1_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
|    44     |    12    | DEV_DCC1_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    45     |     0    | DEV_DCC2_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 24000000        |
|    45     |     1    | DEV_DCC2_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 20000000        |
|    45     |     3    | DEV_DCC2_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 100000000       |
|    45     |     4    | DEV_DCC2_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 225000000       |
|    45     |     5    | DEV_DCC2_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 300000000       |
|    45     |     6    | DEV_DCC2_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    45     |     7    | DEV_DCC2_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    45     |     8    | DEV_DCC2_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    45     |     9    | DEV_DCC2_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    45     |    10    | DEV_DCC2_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    45     |    11    | DEV_DCC2_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
|    45     |    12    | DEV_DCC2_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    46     |     0    | DEV_DCC3_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 196608000       |
|    46     |     1    | DEV_DCC3_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    46     |     2    | DEV_DCC3_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 300000000       |
|    46     |     5    | DEV_DCC3_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    46     |     6    | DEV_DCC3_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    46     |     7    | DEV_DCC3_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 500000000       |
|    46     |     8    | DEV_DCC3_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    46     |     9    | DEV_DCC3_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    46     |    10    | DEV_DCC3_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    46     |    11    | DEV_DCC3_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
|    46     |    12    | DEV_DCC3_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    47     |     0    | DEV_DCC4_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    47     |     2    | DEV_DCC4_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 266625000       |
|    47     |     3    | DEV_DCC4_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 266666250       |
|    47     |     4    | DEV_DCC4_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    47     |     5    | DEV_DCC4_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    47     |     7    | DEV_DCC4_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 297000000       |
|    47     |     8    | DEV_DCC4_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    47     |     9    | DEV_DCC4_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    47     |    10    | DEV_DCC4_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    47     |    11    | DEV_DCC4_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    47     |    12    | DEV_DCC4_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    48     |     1    | DEV_DCC5_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 300000000       |
|    48     |     2    | DEV_DCC5_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 297000000       |
|    48     |     3    | DEV_DCC5_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 240000000       |
|    48     |     4    | DEV_DCC5_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 360000000       |
|    48     |     6    | DEV_DCC5_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 0               |
|    48     |     7    | DEV_DCC5_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
|    48     |     8    | DEV_DCC5_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    48     |     9    | DEV_DCC5_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    48     |    10    | DEV_DCC5_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    48     |    11    | DEV_DCC5_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 500000000       |
|    48     |    12    | DEV_DCC5_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    49     |     0    | DEV_DCC6_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     1    | DEV_DCC6_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     2    | DEV_DCC6_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     3    | DEV_DCC6_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     4    | DEV_DCC6_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     5    | DEV_DCC6_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     6    | DEV_DCC6_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     7    | DEV_DCC6_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |     8    | DEV_DCC6_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    49     |     9    | DEV_DCC6_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    49     |    10    | DEV_DCC6_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    49     |    11    | DEV_DCC6_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 125000000       |
|    49     |    12    | DEV_DCC6_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    50     |     0    | DEV_DCC7_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 0               |
|    50     |     1    | DEV_DCC7_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 0               |
|    50     |     2    | DEV_DCC7_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 500000000       |
|    50     |     5    | DEV_DCC7_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 0               |
|    50     |     6    | DEV_DCC7_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 120000000       |
|    50     |     7    | DEV_DCC7_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 0               |
|    50     |     8    | DEV_DCC7_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    50     |     9    | DEV_DCC7_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    50     |    10    | DEV_DCC7_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    50     |    11    | DEV_DCC7_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    50     |    12    | DEV_DCC7_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    51     |     0    | DEV_DCC8_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 32000           |
|    51     |     1    | DEV_DCC8_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 32768           |
|    51     |     2    | DEV_DCC8_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
|    51     |     3    | DEV_DCC8_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
|    51     |     4    | DEV_DCC8_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
|    51     |     6    | DEV_DCC8_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    51     |     7    | DEV_DCC8_DCC_CLKSRC7_CLK                                                          | CLK_STATE_READY     | 200000000       |
|    51     |     8    | DEV_DCC8_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    51     |     9    | DEV_DCC8_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    51     |    10    | DEV_DCC8_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    51     |    11    | DEV_DCC8_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    51     |    12    | DEV_DCC8_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|    52     |     0    | DEV_DCC9_DCC_CLKSRC0_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    52     |     1    | DEV_DCC9_DCC_CLKSRC1_CLK                                                          | CLK_STATE_READY     | 125000000       |
|    52     |     2    | DEV_DCC9_DCC_CLKSRC2_CLK                                                          | CLK_STATE_READY     | 0               |
|    52     |     3    | DEV_DCC9_DCC_CLKSRC3_CLK                                                          | CLK_STATE_READY     | 0               |
|    52     |     4    | DEV_DCC9_DCC_CLKSRC4_CLK                                                          | CLK_STATE_READY     | 0               |
|    52     |     5    | DEV_DCC9_DCC_CLKSRC5_CLK                                                          | CLK_STATE_READY     | 294912000       |
|    52     |     6    | DEV_DCC9_DCC_CLKSRC6_CLK                                                          | CLK_STATE_READY     | 196608000       |
|    52     |     8    | DEV_DCC9_DCC_INPUT00_CLK                                                          | CLK_STATE_READY     | 19200000        |
|    52     |     9    | DEV_DCC9_DCC_INPUT01_CLK                                                          | CLK_STATE_READY     | 0               |
|    52     |    10    | DEV_DCC9_DCC_INPUT02_CLK                                                          | CLK_STATE_READY     | 12500000        |
|    52     |    11    | DEV_DCC9_DCC_INPUT10_CLK                                                          | CLK_STATE_READY     | 250000000       |
|    52     |    12    | DEV_DCC9_VBUS_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|   138     |     0    | DEV_DDR0_DDRSS_DDR_PLL_CLK                                                        | CLK_STATE_READY     | 1066500000      |
|   138     |     1    | DEV_DDR0_DDRSS_VBUS_CLK                                                           | CLK_STATE_READY     | 250000000       |
|   138     |     2    | DEV_DDR0_PLL_CTRL_CLK                                                             | CLK_STATE_READY     | 500000000       |
|   138     |     7    | DEV_DDR0_DDRSS_CFG_CLK                                                            | CLK_STATE_READY     | 125000000       |
|   139     |     0    | DEV_DDR1_DDRSS_DDR_PLL_CLK                                                        | CLK_STATE_READY     | 1066665000      |
|   139     |     1    | DEV_DDR1_DDRSS_VBUS_CLK                                                           | CLK_STATE_READY     | 250000000       |
|   139     |     2    | DEV_DDR1_PLL_CTRL_CLK                                                             | CLK_STATE_READY     | 500000000       |
|   139     |     7    | DEV_DDR1_DDRSS_CFG_CLK                                                            | CLK_STATE_READY     | 125000000       |
|    57     |     1    | DEV_DEBUGSS_WRAP0_ATB_CLK                                                         | CLK_STATE_READY     | 250000000       |
|    57     |    16    | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK                                                 | CLK_STATE_READY     | 0               |
|    57     |    17    | DEV_DEBUGSS_WRAP0_CORE_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    57     |    28    | DEV_DEBUGSS_WRAP0_TREXPT_CLK                                                      | CLK_STATE_READY     | 300000000       |
|    57     |    41    | DEV_DEBUGSS_WRAP0_JTAG_TCK                                                        | CLK_STATE_READY     | 0               |
|   137     |     0    | DEV_DEBUGSUSPENDRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
|    58     |     0    | DEV_DMPAC0_CLK                                                                    | CLK_STATE_READY     | 480000000       |
|    62     |     0    | DEV_DMPAC0_SDE_0_CLK                                                              | CLK_STATE_READY     | 480000000       |
|   374     |     0    | DEV_DMPAC0_UTC_0_PSIL_LEAF_CLK                                                    | CLK_STATE_READY     | 480000000       |
|   140     |     0    | DEV_DMPAC_VPAC_PSILSS0_MAIN_CLK                                                   | CLK_STATE_READY     | 250000000       |
|   152     |     0    | DEV_DPHY_RX0_IO_RX_CL_L_M                                                         | CLK_STATE_READY     | 0               |
|   152     |     1    | DEV_DPHY_RX0_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               |
|   152     |     2    | DEV_DPHY_RX0_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   152     |     3    | DEV_DPHY_RX0_IO_RX_CL_L_P                                                         | CLK_STATE_READY     | 0               |
|   152     |     4    | DEV_DPHY_RX0_JTAG_TCK                                                             | CLK_STATE_READY     | 0               |
|   152     |     8    | DEV_DPHY_RX0_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               |
|   153     |     0    | DEV_DPHY_RX1_IO_RX_CL_L_M                                                         | CLK_STATE_READY     | 0               |
|   153     |     1    | DEV_DPHY_RX1_PPI_RX_BYTE_CLK                                                      | CLK_STATE_READY     | 0               |
|   153     |     2    | DEV_DPHY_RX1_MAIN_CLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   153     |     3    | DEV_DPHY_RX1_IO_RX_CL_L_P                                                         | CLK_STATE_READY     | 0               |
|   153     |     4    | DEV_DPHY_RX1_JTAG_TCK                                                             | CLK_STATE_READY     | 0               |
|   153     |     8    | DEV_DPHY_RX1_PPI_D_RX_ULPS_ESC                                                    | CLK_STATE_READY     | 0               |
|   363     |     1    | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
|   363     |     2    | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
|   363     |     5    | DEV_DPHY_TX0_CLK                                                                  | CLK_STATE_READY     | 125000000       |
|   363     |     8    | DEV_DPHY_TX0_PSM_CLK                                                              | CLK_STATE_READY     | 20000000        |
|   363     |    12    | DEV_DPHY_TX0_CK_M                                                                 | CLK_STATE_READY     | 0               |
|   363     |    14    | DEV_DPHY_TX0_DPHY_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
|   363     |    15    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   363     |    16    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   363     |    17    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                | CLK_STATE_READY     | 125000000       |
|   363     |    18    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                | CLK_STATE_READY     | 100000000       |
|   363     |    19    | DEV_DPHY_TX0_TAP_TCK                                                              | CLK_STATE_READY     | 0               |
|   363     |    20    | DEV_DPHY_TX0_CK_P                                                                 | CLK_STATE_READY     | 0               |
|   363     |    22    | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
|   363     |    23    | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK                                               | CLK_STATE_READY     | 0               |
|   363     |    24    | DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
|   364     |     1    | DEV_DPHY_TX1_IP2_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
|   364     |     2    | DEV_DPHY_TX1_IP1_PPI_TXBYTECLKHS_CL_CLK                                           | CLK_STATE_READY     | 0               |
|   364     |     5    | DEV_DPHY_TX1_CLK                                                                  | CLK_STATE_READY     | 125000000       |
|   364     |     8    | DEV_DPHY_TX1_PSM_CLK                                                              | CLK_STATE_READY     | 20000000        |
|   364     |    12    | DEV_DPHY_TX1_CK_M                                                                 | CLK_STATE_READY     | 0               |
|   364     |    14    | DEV_DPHY_TX1_DPHY_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
|   364     |    15    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   364     |    16    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   364     |    17    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK                | CLK_STATE_READY     | 125000000       |
|   364     |    18    | DEV_DPHY_TX1_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK                | CLK_STATE_READY     | 100000000       |
|   364     |    19    | DEV_DPHY_TX1_TAP_TCK                                                              | CLK_STATE_READY     | 0               |
|   364     |    20    | DEV_DPHY_TX1_CK_P                                                                 | CLK_STATE_READY     | 0               |
|   364     |    22    | DEV_DPHY_TX1_IP1_PPI_M_TXCLKESC_CLK                                               | CLK_STATE_READY     | 20000000        |
|   364     |    23    | DEV_DPHY_TX1_IP1_PPI_M_RXCLKESC_CLK                                               | CLK_STATE_READY     | 0               |
|   158     |     0    | DEV_DSS0_DSS_FUNC_CLK                                                             | CLK_STATE_READY     | 600000000       |
|   158     |     1    | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK                                                   | CLK_STATE_READY     | 297000000       |
|   158     |     2    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK                                                | CLK_STATE_READY     | 594000000       |
|   158     |     3    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |     4    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0                     | CLK_STATE_READY     | 594000000       |
|   158     |     5    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK                                                | CLK_STATE_READY     | 594000000       |
|   158     |     6    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |     7    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
|   158     |     8    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0               | CLK_STATE_READY     | 600000000       |
|   158     |     9    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |    10    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK                                                   | CLK_STATE_READY     | 297000000       |
|   158     |    11    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK         | CLK_STATE_READY     | 297000000       |
|   158     |    12    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK         | CLK_STATE_READY     | 297000000       |
|   158     |    13    | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                       | CLK_STATE_READY     | 300000000       |
|   158     |    14    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK                                                | CLK_STATE_READY     | 594000000       |
|   158     |    15    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |    16    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |    17    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
|   158     |    18    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK                                                | CLK_STATE_READY     | 594000000       |
|   158     |    19    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |    20    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK      | CLK_STATE_READY     | 594000000       |
|   158     |    21    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0 | CLK_STATE_READY     | 594000000       |
|   158     |    22    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0                    | CLK_STATE_READY     | 600000000       |
|   158     |    23    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0               | CLK_STATE_READY     | 600000000       |
|   158     |    24    | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK                                                 | CLK_STATE_READY     | 0               |
|   158     |    25    | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK                                                 | CLK_STATE_READY     | 0               |
|   158     |    26    | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
|   158     |    27    | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
|   158     |    28    | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
|   158     |    29    | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK                                                  | CLK_STATE_READY     | 0               |
|   158     |    30    | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK                                               | CLK_STATE_READY     | 0               |
|   154     |     0    | DEV_DSS_DSI0_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
|   154     |     1    | DEV_DSS_DSI0_SYS_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   154     |     2    | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK                                                    | CLK_STATE_READY     | 0               |
|   154     |     3    | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK                                                    | CLK_STATE_READY     | 20000000        |
|   154     |     4    | DEV_DSS_DSI0_DPI_0_CLK                                                            | CLK_STATE_READY     | 0               |
|   154     |     5    | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               |
|   155     |     0    | DEV_DSS_DSI1_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
|   155     |     1    | DEV_DSS_DSI1_SYS_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   155     |     2    | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK                                                    | CLK_STATE_READY     | 0               |
|   155     |     3    | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK                                                    | CLK_STATE_READY     | 20000000        |
|   155     |     4    | DEV_DSS_DSI1_DPI_0_CLK                                                            | CLK_STATE_READY     | 0               |
|   155     |     5    | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK                                             | CLK_STATE_READY     | 0               |
|   156     |     0    | DEV_DSS_EDP0_PHY_LN0_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |     1    | DEV_DSS_EDP0_PHY_LN2_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |     2    | DEV_DSS_EDP0_PHY_LN3_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |     3    | DEV_DSS_EDP0_PHY_LN2_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |     4    | DEV_DSS_EDP0_PHY_LN3_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |     6    | DEV_DSS_EDP0_DPI_2_2X_CLK                                                         | CLK_STATE_READY     | 0               |
|   156     |     7    | DEV_DSS_EDP0_PHY_LN0_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |     8    | DEV_DSS_EDP0_PHY_LN2_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |     9    | DEV_DSS_EDP0_DPI_3_CLK                                                            | CLK_STATE_READY     | 0               |
|   156     |    10    | DEV_DSS_EDP0_PHY_LN1_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |    11    | DEV_DSS_EDP0_PHY_LN1_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |    12    | DEV_DSS_EDP0_PHY_LN1_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    13    | DEV_DSS_EDP0_DPI_5_CLK                                                            | CLK_STATE_READY     | 0               |
|   156     |    14    | DEV_DSS_EDP0_PHY_LN2_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |    16    | DEV_DSS_EDP0_PHY_LN1_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    18    | DEV_DSS_EDP0_DPI_2_CLK                                                            | CLK_STATE_READY     | 0               |
|   156     |    19    | DEV_DSS_EDP0_DPTX_MOD_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   156     |    20    | DEV_DSS_EDP0_PHY_LN1_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    21    | DEV_DSS_EDP0_PHY_LN1_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    22    | DEV_DSS_EDP0_PHY_LN0_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    24    | DEV_DSS_EDP0_PHY_LN3_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    25    | DEV_DSS_EDP0_PLL_CTRL_CLK                                                         | CLK_STATE_READY     | 500000000       |
|   156     |    26    | DEV_DSS_EDP0_PHY_LN0_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    27    | DEV_DSS_EDP0_PHY_LN3_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    28    | DEV_DSS_EDP0_PHY_LN3_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |    29    | DEV_DSS_EDP0_PHY_LN2_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    30    | DEV_DSS_EDP0_DPI_4_CLK                                                            | CLK_STATE_READY     | 0               |
|   156     |    31    | DEV_DSS_EDP0_PHY_LN0_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    33    | DEV_DSS_EDP0_PHY_LN0_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   156     |    34    | DEV_DSS_EDP0_PHY_LN3_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   156     |    35    | DEV_DSS_EDP0_AIF_I2S_CLK                                                          | CLK_STATE_READY     | 0               |
|   156     |    36    | DEV_DSS_EDP0_PHY_LN2_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|    92     |     0    | DEV_ECAP0_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
|    93     |     0    | DEV_ECAP1_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
|    94     |     0    | DEV_ECAP2_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
|    95     |     0    | DEV_ELM0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   160     |     0    | DEV_EPWM0_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   161     |     0    | DEV_EPWM1_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   162     |     0    | DEV_EPWM2_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   163     |     0    | DEV_EPWM3_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   164     |     0    | DEV_EPWM4_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   165     |     0    | DEV_EPWM5_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   100     |     0    | DEV_EQEP0_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   101     |     0    | DEV_EQEP1_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   102     |     0    | DEV_EQEP2_VBUS_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   103     |     0    | DEV_ESM0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   111     |     0    | DEV_GPIO0_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|   112     |     0    | DEV_GPIO2_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|   113     |     0    | DEV_GPIO4_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|   114     |     0    | DEV_GPIO6_MMR_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|   148     |     0    | DEV_GPIOMUX_INTRTR0_INTR_CLK                                                      | CLK_STATE_READY     | 125000000       |
|   117     |     0    | DEV_GPMC0_VBUSM_CLK                                                               | CLK_STATE_READY     | 250000000       |
|   117     |     1    | DEV_GPMC0_PO_GPMC_DEV_CLK                                                         | CLK_STATE_READY     | 0               |
|   117     |     2    | DEV_GPMC0_FUNC_CLK                                                                | CLK_STATE_READY     | 133333333       |
|   117     |     3    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK                       | CLK_STATE_READY     | 133333333       |
|   117     |     4    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6                      | CLK_STATE_READY     | 100000000       |
|   117     |     5    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4                      | CLK_STATE_READY     | 150000000       |
|   117     |     6    | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4              | CLK_STATE_READY     | 125000000       |
|   117     |     7    | DEV_GPMC0_PI_GPMC_RET_CLK                                                         | CLK_STATE_READY     | 0               |
|    61     |     0    | DEV_GTC0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
|    61     |     1    | DEV_GTC0_GTC_CLK                                                                  | CLK_STATE_READY     | 200000000       |
|    61     |     2    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                         | CLK_STATE_READY     | 200000000       |
|    61     |     3    | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                       | CLK_STATE_READY     | 250000000       |
|    61     |     4    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                             | CLK_STATE_READY     | 0               |
|    61     |     5    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                                 | CLK_STATE_READY     | 0               |
|    61     |     6    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                               | CLK_STATE_READY     | 0               |
|    61     |     7    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                   | CLK_STATE_READY     | 0               |
|    61     |     8    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                        | CLK_STATE_NOT_READY | 0               |
|    61     |     9    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                        | CLK_STATE_NOT_READY | 0               |
|    61     |    10    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                        | CLK_STATE_NOT_READY | 0               |
|    61     |    11    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                        | CLK_STATE_NOT_READY | 0               |
|    61     |    16    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                          | CLK_STATE_READY     | 500000000       |
|    61     |    17    | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                 | CLK_STATE_READY     | 500000000       |
|   214     |     0    | DEV_I2C0_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   214     |     1    | DEV_I2C0_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   214     |     2    | DEV_I2C0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   214     |     3    | DEV_I2C0_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   215     |     0    | DEV_I2C1_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   215     |     1    | DEV_I2C1_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   215     |     2    | DEV_I2C1_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   215     |     3    | DEV_I2C1_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   216     |     0    | DEV_I2C2_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   216     |     1    | DEV_I2C2_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   216     |     2    | DEV_I2C2_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   216     |     3    | DEV_I2C2_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   217     |     0    | DEV_I2C3_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   217     |     1    | DEV_I2C3_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   217     |     2    | DEV_I2C3_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   217     |     3    | DEV_I2C3_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   218     |     0    | DEV_I2C4_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   218     |     1    | DEV_I2C4_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   218     |     2    | DEV_I2C4_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   218     |     3    | DEV_I2C4_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   219     |     0    | DEV_I2C5_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   219     |     1    | DEV_I2C5_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   219     |     2    | DEV_I2C5_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   219     |     3    | DEV_I2C5_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   220     |     0    | DEV_I2C6_PORSCL                                                                   | CLK_STATE_READY     | 0               |
|   220     |     1    | DEV_I2C6_PISYS_CLK                                                                | CLK_STATE_READY     | 96000000        |
|   220     |     2    | DEV_I2C6_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   220     |     3    | DEV_I2C6_PISCL                                                                    | CLK_STATE_READY     | 0               |
|   130     |     0    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_PLL_CTRL_CLK                                  | CLK_STATE_READY     | 500000000       |
|   130     |     1    | DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0_GPU_PLL_CLK                                   | CLK_STATE_READY     | 800000000       |
|   131     |     0    | DEV_J7AM_32_64_ATB_FUNNEL0_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
|   132     |     0    | DEV_J7AM_32_64_ATB_FUNNEL1_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
|   133     |     0    | DEV_J7AM_32_64_ATB_FUNNEL2_DBG_CLK                                                | CLK_STATE_READY     | 250000000       |
|   135     |     0    | DEV_J7AM_BOLT_PGD0_WKUP_OSC0_CLK                                                  | CLK_STATE_READY     | 19200000        |
|   141     |     0    | DEV_J7AM_HWA_ATB_FUNNEL0_DBG_CLK                                                  | CLK_STATE_READY     | 250000000       |
|   142     |     0    | DEV_J7AM_MAIN_16FF0_WKUP_OSC0_CLK                                                 | CLK_STATE_READY     | 19200000        |
|   144     |     0    | DEV_J7AM_PULSAR_ATB_FUNNEL0_DBG_CLK                                               | CLK_STATE_READY     | 250000000       |
|   120     |     0    | DEV_LED0_VBUS_CLK                                                                 | CLK_STATE_READY     | 250000000       |
|   120     |     1    | DEV_LED0_LED_CLK                                                                  | CLK_STATE_READY     | 0               |
|   121     |     0    | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 125000000       |
|   122     |     0    | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 125000000       |
|   182     |     0    | DEV_MCAN0_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   182     |     1    | DEV_MCAN0_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   182     |     2    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   182     |     3    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   182     |     4    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   182     |     5    | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   182     |     6    | DEV_MCAN0_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   183     |     0    | DEV_MCAN1_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   183     |     1    | DEV_MCAN1_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   183     |     2    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   183     |     3    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   183     |     4    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   183     |     5    | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   183     |     6    | DEV_MCAN1_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   192     |     0    | DEV_MCAN10_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   192     |     1    | DEV_MCAN10_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   192     |     2    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   192     |     3    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   192     |     4    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   192     |     5    | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   192     |     6    | DEV_MCAN10_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   193     |     0    | DEV_MCAN11_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   193     |     1    | DEV_MCAN11_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   193     |     2    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   193     |     3    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   193     |     4    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   193     |     5    | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   193     |     6    | DEV_MCAN11_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   194     |     0    | DEV_MCAN12_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   194     |     1    | DEV_MCAN12_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   194     |     2    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   194     |     3    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   194     |     4    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   194     |     5    | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   194     |     6    | DEV_MCAN12_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   195     |     0    | DEV_MCAN13_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   195     |     1    | DEV_MCAN13_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   195     |     2    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   195     |     3    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   195     |     4    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   195     |     5    | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   195     |     6    | DEV_MCAN13_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   197     |     0    | DEV_MCAN14_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   197     |     1    | DEV_MCAN14_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   197     |     2    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   197     |     3    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   197     |     4    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   197     |     5    | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   197     |     6    | DEV_MCAN14_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   199     |     0    | DEV_MCAN15_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   199     |     1    | DEV_MCAN15_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   199     |     2    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   199     |     3    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   199     |     4    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   199     |     5    | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   199     |     6    | DEV_MCAN15_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   201     |     0    | DEV_MCAN16_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   201     |     1    | DEV_MCAN16_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   201     |     2    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   201     |     3    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   201     |     4    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   201     |     5    | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   201     |     6    | DEV_MCAN16_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   206     |     0    | DEV_MCAN17_MCANSS_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   206     |     1    | DEV_MCAN17_MCANSS_CCLK_CLK                                                        | CLK_STATE_READY     | 80000000        |
|   206     |     2    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK               | CLK_STATE_READY     | 80000000        |
|   206     |     3    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|   206     |     4    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   206     |     5    | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   206     |     6    | DEV_MCAN17_MCANSS_CAN_RXD                                                         | CLK_STATE_READY     | 0               |
|   184     |     0    | DEV_MCAN2_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   184     |     1    | DEV_MCAN2_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   184     |     2    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   184     |     3    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   184     |     4    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   184     |     5    | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   184     |     6    | DEV_MCAN2_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   185     |     0    | DEV_MCAN3_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   185     |     1    | DEV_MCAN3_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   185     |     2    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   185     |     3    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   185     |     4    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   185     |     5    | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   185     |     6    | DEV_MCAN3_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   186     |     0    | DEV_MCAN4_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   186     |     1    | DEV_MCAN4_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   186     |     2    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   186     |     3    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   186     |     4    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   186     |     5    | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   186     |     6    | DEV_MCAN4_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   187     |     0    | DEV_MCAN5_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   187     |     1    | DEV_MCAN5_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   187     |     2    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   187     |     3    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   187     |     4    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   187     |     5    | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   187     |     6    | DEV_MCAN5_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   188     |     0    | DEV_MCAN6_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   188     |     1    | DEV_MCAN6_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   188     |     2    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   188     |     3    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   188     |     4    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   188     |     5    | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   188     |     6    | DEV_MCAN6_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   189     |     0    | DEV_MCAN7_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   189     |     1    | DEV_MCAN7_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   189     |     2    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   189     |     3    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   189     |     4    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   189     |     5    | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   189     |     6    | DEV_MCAN7_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   190     |     0    | DEV_MCAN8_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   190     |     1    | DEV_MCAN8_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   190     |     2    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   190     |     3    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   190     |     4    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   190     |     5    | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   190     |     6    | DEV_MCAN8_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   191     |     0    | DEV_MCAN9_MCANSS_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   191     |     1    | DEV_MCAN9_MCANSS_CCLK_CLK                                                         | CLK_STATE_READY     | 80000000        |
|   191     |     2    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK                | CLK_STATE_READY     | 80000000        |
|   191     |     3    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|   191     |     4    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   191     |     5    | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|   191     |     6    | DEV_MCAN9_MCANSS_CAN_RXD                                                          | CLK_STATE_READY     | 0               |
|   209     |     0    | DEV_MCASP0_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
|   209     |     1    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
|   209     |     2    | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
|   209     |     5    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
|   209     |     6    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
|   209     |     7    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
|   209     |     8    | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
|   209     |     9    | DEV_MCASP0_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
|   209     |    10    | DEV_MCASP0_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
|   209     |    11    | DEV_MCASP0_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
|   209     |    12    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   209     |    13    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   209     |    14    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   209     |    15    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   209     |    20    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   209     |    21    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   209     |    22    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   209     |    23    | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   209     |    28    | DEV_MCASP0_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
|   209     |    29    | DEV_MCASP0_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
|   209     |    30    | DEV_MCASP0_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   209     |    31    | DEV_MCASP0_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
|   209     |    32    | DEV_MCASP0_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
|   209     |    33    | DEV_MCASP0_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
|   209     |    34    | DEV_MCASP0_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
|   209     |    35    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   209     |    36    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   209     |    37    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   209     |    38    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   209     |    43    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   209     |    44    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   209     |    45    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   209     |    46    | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   209     |    51    | DEV_MCASP0_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
|   210     |     0    | DEV_MCASP1_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
|   210     |     1    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
|   210     |     2    | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
|   210     |     5    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
|   210     |     6    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
|   210     |     7    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
|   210     |     8    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
|   210     |     9    | DEV_MCASP1_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
|   210     |    10    | DEV_MCASP1_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
|   210     |    11    | DEV_MCASP1_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
|   210     |    12    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   210     |    13    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   210     |    14    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   210     |    15    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   210     |    20    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   210     |    21    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   210     |    22    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   210     |    23    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   210     |    28    | DEV_MCASP1_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
|   210     |    29    | DEV_MCASP1_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
|   210     |    30    | DEV_MCASP1_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   210     |    31    | DEV_MCASP1_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
|   210     |    32    | DEV_MCASP1_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
|   210     |    33    | DEV_MCASP1_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
|   210     |    34    | DEV_MCASP1_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
|   210     |    35    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   210     |    36    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   210     |    37    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   210     |    38    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   210     |    43    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   210     |    44    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   210     |    45    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   210     |    46    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   210     |    51    | DEV_MCASP1_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
|   211     |     0    | DEV_MCASP2_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
|   211     |     1    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
|   211     |     2    | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
|   211     |     5    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
|   211     |     6    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
|   211     |     7    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
|   211     |     8    | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
|   211     |     9    | DEV_MCASP2_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
|   211     |    10    | DEV_MCASP2_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
|   211     |    11    | DEV_MCASP2_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
|   211     |    12    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   211     |    13    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   211     |    14    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   211     |    15    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   211     |    20    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   211     |    21    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   211     |    22    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   211     |    23    | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   211     |    28    | DEV_MCASP2_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
|   211     |    29    | DEV_MCASP2_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
|   211     |    30    | DEV_MCASP2_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   211     |    31    | DEV_MCASP2_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
|   211     |    32    | DEV_MCASP2_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
|   211     |    33    | DEV_MCASP2_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
|   211     |    34    | DEV_MCASP2_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
|   211     |    35    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   211     |    36    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   211     |    37    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   211     |    38    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   211     |    43    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   211     |    44    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   211     |    45    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   211     |    46    | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   211     |    51    | DEV_MCASP2_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
|   212     |     0    | DEV_MCASP3_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
|   212     |     1    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
|   212     |     2    | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
|   212     |     5    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
|   212     |     6    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
|   212     |     7    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
|   212     |     8    | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
|   212     |     9    | DEV_MCASP3_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
|   212     |    10    | DEV_MCASP3_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
|   212     |    11    | DEV_MCASP3_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
|   212     |    12    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   212     |    13    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   212     |    14    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   212     |    15    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   212     |    20    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   212     |    21    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   212     |    22    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   212     |    23    | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   212     |    28    | DEV_MCASP3_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
|   212     |    29    | DEV_MCASP3_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
|   212     |    30    | DEV_MCASP3_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   212     |    31    | DEV_MCASP3_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
|   212     |    32    | DEV_MCASP3_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
|   212     |    33    | DEV_MCASP3_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
|   212     |    34    | DEV_MCASP3_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
|   212     |    35    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   212     |    36    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   212     |    37    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   212     |    38    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   212     |    43    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   212     |    44    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   212     |    45    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   212     |    46    | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   212     |    51    | DEV_MCASP3_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
|   213     |     0    | DEV_MCASP4_AUX_CLK                                                                | CLK_STATE_READY     | 196608000       |
|   213     |     1    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK                       | CLK_STATE_READY     | 196608000       |
|   213     |     2    | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                       | CLK_STATE_READY     | 200000000       |
|   213     |     5    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                        | CLK_STATE_NOT_READY | 0               |
|   213     |     6    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                      | CLK_STATE_NOT_READY | 0               |
|   213     |     7    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                      | CLK_STATE_NOT_READY | 0               |
|   213     |     8    | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                      | CLK_STATE_NOT_READY | 0               |
|   213     |     9    | DEV_MCASP4_MCASP_AFSX_POUT                                                        | CLK_STATE_READY     | 0               |
|   213     |    10    | DEV_MCASP4_MCASP_AHCLKR_POUT                                                      | CLK_STATE_READY     | 0               |
|   213     |    11    | DEV_MCASP4_MCASP_AHCLKR_PIN                                                       | CLK_STATE_READY     | 0               |
|   213     |    12    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   213     |    13    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   213     |    14    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   213     |    15    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   213     |    20    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   213     |    21    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   213     |    22    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   213     |    23    | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   213     |    28    | DEV_MCASP4_MCASP_ACLKX_POUT                                                       | CLK_STATE_READY     | 0               |
|   213     |    29    | DEV_MCASP4_MCASP_AFSR_POUT                                                        | CLK_STATE_READY     | 0               |
|   213     |    30    | DEV_MCASP4_VBUSP_CLK                                                              | CLK_STATE_READY     | 250000000       |
|   213     |    31    | DEV_MCASP4_MCASP_ACLKR_POUT                                                       | CLK_STATE_READY     | 0               |
|   213     |    32    | DEV_MCASP4_MCASP_AHCLKX_POUT                                                      | CLK_STATE_READY     | 0               |
|   213     |    33    | DEV_MCASP4_MCASP_ACLKX_PIN                                                        | CLK_STATE_READY     | 0               |
|   213     |    34    | DEV_MCASP4_MCASP_AHCLKX_PIN                                                       | CLK_STATE_READY     | 0               |
|   213     |    35    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT                         | CLK_STATE_READY     | 0               |
|   213     |    36    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                        | CLK_STATE_READY     | 19200000        |
|   213     |    37    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   213     |    38    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                  | CLK_STATE_READY     | 0               |
|   213     |    43    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT               | CLK_STATE_NOT_READY | 0               |
|   213     |    44    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1             | CLK_STATE_NOT_READY | 0               |
|   213     |    45    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2             | CLK_STATE_NOT_READY | 0               |
|   213     |    46    | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3             | CLK_STATE_NOT_READY | 0               |
|   213     |    51    | DEV_MCASP4_MCASP_ACLKR_PIN                                                        | CLK_STATE_READY     | 0               |
|   339     |     0    | DEV_MCSPI0_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   339     |     1    | DEV_MCSPI0_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   339     |     2    | DEV_MCSPI0_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   339     |     3    | DEV_MCSPI0_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   339     |     4    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT                             | CLK_STATE_READY     | 0               |
|   339     |     5    | DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|   340     |     0    | DEV_MCSPI1_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   340     |     1    | DEV_MCSPI1_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   340     |     2    | DEV_MCSPI1_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   340     |     3    | DEV_MCSPI1_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   340     |     4    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT                             | CLK_STATE_READY     | 0               |
|   340     |     5    | DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|   341     |     0    | DEV_MCSPI2_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   341     |     1    | DEV_MCSPI2_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   341     |     2    | DEV_MCSPI2_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   341     |     3    | DEV_MCSPI2_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   341     |     4    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT                             | CLK_STATE_READY     | 0               |
|   341     |     5    | DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|   342     |     0    | DEV_MCSPI3_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   342     |     1    | DEV_MCSPI3_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   342     |     2    | DEV_MCSPI3_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   342     |     3    | DEV_MCSPI3_IO_CLKSPII_CLK                                                         | CLK_STATE_NOT_READY | 0               |
|   342     |     4    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|   342     |     5    | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI3_CLK_LPBK_MUX_OUT0                           | CLK_STATE_READY     | 0               |
|   343     |     0    | DEV_MCSPI4_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   343     |     1    | DEV_MCSPI4_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   343     |     2    | DEV_MCSPI4_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   343     |     3    | DEV_MCSPI4_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   344     |     0    | DEV_MCSPI5_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   344     |     1    | DEV_MCSPI5_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   344     |     2    | DEV_MCSPI5_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   344     |     3    | DEV_MCSPI5_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   344     |     4    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI5_CLK_OUT                             | CLK_STATE_READY     | 0               |
|   344     |     5    | DEV_MCSPI5_IO_CLKSPII_CLK_PARENT_SPI_MAIN_5_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|   345     |     0    | DEV_MCSPI6_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   345     |     1    | DEV_MCSPI6_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   345     |     2    | DEV_MCSPI6_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   345     |     3    | DEV_MCSPI6_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   345     |     4    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI6_CLK_OUT                             | CLK_STATE_READY     | 0               |
|   345     |     5    | DEV_MCSPI6_IO_CLKSPII_CLK_PARENT_SPI_MAIN_6_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|   346     |     0    | DEV_MCSPI7_IO_CLKSPIO_CLK                                                         | CLK_STATE_READY     | 0               |
|   346     |     1    | DEV_MCSPI7_VBUSP_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   346     |     2    | DEV_MCSPI7_CLKSPIREF_CLK                                                          | CLK_STATE_READY     | 50000000        |
|   346     |     3    | DEV_MCSPI7_IO_CLKSPII_CLK                                                         | CLK_STATE_READY     | 0               |
|   346     |     4    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI7_CLK_OUT                             | CLK_STATE_READY     | 0               |
|   346     |     5    | DEV_MCSPI7_IO_CLKSPII_CLK_PARENT_SPI_MAIN_7_IO_CLKSPIO_CLK                        | CLK_STATE_NOT_READY | 0               |
|     0     |     0    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK                                                    | CLK_STATE_READY     | 19200000        |
|     0     |     1    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                     | CLK_STATE_READY     | 19200000        |
|     0     |     2    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK            | CLK_STATE_READY     | 60000000        |
|     0     |     3    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK            | CLK_STATE_READY     | 58823529        |
|     0     |     4    | DEV_MCU_ADC12FC_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                 | CLK_STATE_READY     | 0               |
|     0     |     5    | DEV_MCU_ADC12FC_16FFC0_VBUS_CLK                                                   | CLK_STATE_READY     | 333333333       |
|     0     |     6    | DEV_MCU_ADC12FC_16FFC0_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       |
|     1     |     0    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK                                                    | CLK_STATE_READY     | 19200000        |
|     1     |     1    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                     | CLK_STATE_READY     | 19200000        |
|     1     |     2    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK            | CLK_STATE_READY     | 60000000        |
|     1     |     3    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK            | CLK_STATE_READY     | 58823529        |
|     1     |     4    | DEV_MCU_ADC12FC_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                 | CLK_STATE_READY     | 0               |
|     1     |     5    | DEV_MCU_ADC12FC_16FFC1_VBUS_CLK                                                   | CLK_STATE_READY     | 333333333       |
|     1     |     6    | DEV_MCU_ADC12FC_16FFC1_SYS_CLK                                                    | CLK_STATE_READY     | 500000000       |
|    29     |     0    | DEV_MCU_CPSW0_MDIO_MDCLK_O                                                        | CLK_STATE_READY     | 0               |
|    29     |     1    | DEV_MCU_CPSW0_CPTS_GENF0                                                          | CLK_STATE_READY     | 0               |
|    29     |     3    | DEV_MCU_CPSW0_CPTS_RFT_CLK                                                        | CLK_STATE_READY     | 500000000       |
|    29     |     4    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK               | CLK_STATE_READY     | 200000000       |
|    29     |     5    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK             | CLK_STATE_READY     | 250000000       |
|    29     |     6    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                   | CLK_STATE_READY     | 0               |
|    29     |     7    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
|    29     |     8    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|    29     |     9    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
|    29     |    10    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK              | CLK_STATE_NOT_READY | 0               |
|    29     |    11    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK              | CLK_STATE_NOT_READY | 0               |
|    29     |    12    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK              | CLK_STATE_NOT_READY | 0               |
|    29     |    13    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK              | CLK_STATE_NOT_READY | 0               |
|    29     |    18    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                | CLK_STATE_READY     | 500000000       |
|    29     |    19    | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2      | CLK_STATE_READY     | 500000000       |
|    29     |    20    | DEV_MCU_CPSW0_GMII1_MR_CLK                                                        | CLK_STATE_READY     | 25000000        |
|    29     |    21    | DEV_MCU_CPSW0_GMII_RFT_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    29     |    22    | DEV_MCU_CPSW0_RGMII1_RXC_I                                                        | CLK_STATE_READY     | 0               |
|    29     |    26    | DEV_MCU_CPSW0_RMII_MHZ_50_CLK                                                     | CLK_STATE_READY     | 0               |
|    29     |    27    | DEV_MCU_CPSW0_RGMII1_TXC_O                                                        | CLK_STATE_READY     | 0               |
|    29     |    28    | DEV_MCU_CPSW0_CPPI_CLK_CLK                                                        | CLK_STATE_READY     | 333333333       |
|    29     |    29    | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK                                                     | CLK_STATE_READY     | 5000000         |
|    29     |    30    | DEV_MCU_CPSW0_GMII1_MT_CLK                                                        | CLK_STATE_READY     | 25000000        |
|    29     |    32    | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK                                                    | CLK_STATE_READY     | 50000000        |
|    29     |    33    | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK                                                   | CLK_STATE_READY     | 250000000       |
|    37     |     0    | DEV_MCU_CPT2_AGGR0_VCLK_CLK                                                       | CLK_STATE_READY     | 333333333       |
|    53     |     0    | DEV_MCU_DCC0_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 200000000       |
|    53     |     1    | DEV_MCU_DCC0_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 60000000        |
|    53     |     2    | DEV_MCU_DCC0_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 80000000        |
|    53     |     3    | DEV_MCU_DCC0_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 96000000        |
|    53     |     4    | DEV_MCU_DCC0_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 133333333       |
|    53     |     5    | DEV_MCU_DCC0_DCC_CLKSRC5_CLK                                                      | CLK_STATE_READY     | 32000           |
|    53     |     6    | DEV_MCU_DCC0_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 32768           |
|    53     |     7    | DEV_MCU_DCC0_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 0               |
|    53     |     8    | DEV_MCU_DCC0_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
|    53     |     9    | DEV_MCU_DCC0_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 32000           |
|    53     |    10    | DEV_MCU_DCC0_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
|    53     |    11    | DEV_MCU_DCC0_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 333333333       |
|    53     |    12    | DEV_MCU_DCC0_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
|    54     |     0    | DEV_MCU_DCC1_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 250000000       |
|    54     |     1    | DEV_MCU_DCC1_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 200000000       |
|    54     |     2    | DEV_MCU_DCC1_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 80000000        |
|    54     |     3    | DEV_MCU_DCC1_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 166666666       |
|    54     |     4    | DEV_MCU_DCC1_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 250000000       |
|    54     |     5    | DEV_MCU_DCC1_DCC_CLKSRC5_CLK                                                      | CLK_STATE_READY     | 58823529        |
|    54     |     6    | DEV_MCU_DCC1_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 0               |
|    54     |     7    | DEV_MCU_DCC1_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 500000000       |
|    54     |     8    | DEV_MCU_DCC1_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
|    54     |     9    | DEV_MCU_DCC1_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 32768           |
|    54     |    10    | DEV_MCU_DCC1_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
|    54     |    11    | DEV_MCU_DCC1_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 250000000       |
|    54     |    12    | DEV_MCU_DCC1_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
|    55     |     0    | DEV_MCU_DCC2_DCC_CLKSRC0_CLK                                                      | CLK_STATE_READY     | 0               |
|    55     |     1    | DEV_MCU_DCC2_DCC_CLKSRC1_CLK                                                      | CLK_STATE_READY     | 0               |
|    55     |     2    | DEV_MCU_DCC2_DCC_CLKSRC2_CLK                                                      | CLK_STATE_READY     | 0               |
|    55     |     3    | DEV_MCU_DCC2_DCC_CLKSRC3_CLK                                                      | CLK_STATE_READY     | 192000000       |
|    55     |     4    | DEV_MCU_DCC2_DCC_CLKSRC4_CLK                                                      | CLK_STATE_READY     | 0               |
|    55     |     6    | DEV_MCU_DCC2_DCC_CLKSRC6_CLK                                                      | CLK_STATE_READY     | 12500000        |
|    55     |     7    | DEV_MCU_DCC2_DCC_CLKSRC7_CLK                                                      | CLK_STATE_READY     | 19200000        |
|    55     |     8    | DEV_MCU_DCC2_DCC_INPUT00_CLK                                                      | CLK_STATE_READY     | 19200000        |
|    55     |     9    | DEV_MCU_DCC2_DCC_INPUT01_CLK                                                      | CLK_STATE_READY     | 0               |
|    55     |    10    | DEV_MCU_DCC2_DCC_INPUT02_CLK                                                      | CLK_STATE_READY     | 12500000        |
|    55     |    11    | DEV_MCU_DCC2_DCC_INPUT10_CLK                                                      | CLK_STATE_READY     | 333333333       |
|    55     |    12    | DEV_MCU_DCC2_VBUS_CLK                                                             | CLK_STATE_READY     | 166666666       |
|   105     |     0    | DEV_MCU_ESM0_CLK                                                                  | CLK_STATE_READY     | 166666666       |
|   107     |     0    | DEV_MCU_FSS0_FSAS_0_GCLK                                                          | CLK_STATE_READY     | 1000000000      |
|   108     |     1    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK                                      | CLK_STATE_READY     | 166666666       |
|   108     |     2    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK                                      | CLK_STATE_READY     | 83333333        |
|   108     |     3    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK                                          | CLK_STATE_READY     | 83333333        |
|   108     |     6    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK                                          | CLK_STATE_READY     | 166666666       |
|   108     |     7    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N                                          | CLK_STATE_READY     | 0               |
|   108     |     8    | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P                                          | CLK_STATE_READY     | 0               |
|   108     |    11    | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK                                                | CLK_STATE_READY     | 1000000000      |
|   109     |     0    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK                                                 | CLK_STATE_READY     | 0               |
|   109     |     1    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT                | CLK_STATE_READY     | 0               |
|   109     |     2    | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK           | CLK_STATE_READY     | 0               |
|   109     |     3    | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
|   109     |     4    | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK                                                 | CLK_STATE_READY     | 0               |
|   109     |     5    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK                                                 | CLK_STATE_READY     | 166666666       |
|   109     |     6    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK         | CLK_STATE_READY     | 133333333       |
|   109     |     7    | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK         | CLK_STATE_READY     | 166666666       |
|   109     |     8    | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK                                                  | CLK_STATE_READY     | 0               |
|   109     |     9    | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
|   110     |     0    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK                                                 | CLK_STATE_READY     | 0               |
|   110     |     1    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT                | CLK_STATE_READY     | 0               |
|   110     |     2    | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK           | CLK_STATE_NOT_READY | 0               |
|   110     |     3    | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
|   110     |     4    | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK                                                 | CLK_STATE_READY     | 0               |
|   110     |     5    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK                                                 | CLK_STATE_READY     | 133333333       |
|   110     |     6    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK         | CLK_STATE_READY     | 133333333       |
|   110     |     7    | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK         | CLK_STATE_READY     | 166666666       |
|   110     |     8    | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK                                                  | CLK_STATE_READY     | 0               |
|   110     |     9    | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK                                                 | CLK_STATE_READY     | 1000000000      |
|   221     |     0    | DEV_MCU_I2C0_PORSCL                                                               | CLK_STATE_READY     | 0               |
|   221     |     1    | DEV_MCU_I2C0_PISYS_CLK                                                            | CLK_STATE_READY     | 96000000        |
|   221     |     2    | DEV_MCU_I2C0_CLK                                                                  | CLK_STATE_READY     | 166666666       |
|   221     |     3    | DEV_MCU_I2C0_PISCL                                                                | CLK_STATE_READY     | 0               |
|   222     |     0    | DEV_MCU_I2C1_PORSCL                                                               | CLK_STATE_READY     | 0               |
|   222     |     1    | DEV_MCU_I2C1_PISYS_CLK                                                            | CLK_STATE_READY     | 96000000        |
|   222     |     2    | DEV_MCU_I2C1_CLK                                                                  | CLK_STATE_READY     | 166666666       |
|   222     |     3    | DEV_MCU_I2C1_PISCL                                                                | CLK_STATE_READY     | 0               |
|   118     |     0    | DEV_MCU_I3C0_I3C_SCL_DI                                                           | CLK_STATE_READY     | 0               |
|   118     |     1    | DEV_MCU_I3C0_I3C_SCL_DO                                                           | CLK_STATE_READY     | 0               |
|   118     |     2    | DEV_MCU_I3C0_I3C_SCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
|   118     |     3    | DEV_MCU_I3C0_I3C_PCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
|   118     |     4    | DEV_MCU_I3C0_I3C_SDA_DI                                                           | CLK_STATE_READY     | 0               |
|   119     |     2    | DEV_MCU_I3C1_I3C_SCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
|   119     |     3    | DEV_MCU_I3C1_I3C_PCLK_CLK                                                         | CLK_STATE_READY     | 166666666       |
|   207     |     0    | DEV_MCU_MCAN0_MCANSS_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|   207     |     1    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK                                                     | CLK_STATE_READY     | 80000000        |
|   207     |     2    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK             | CLK_STATE_READY     | 80000000        |
|   207     |     3    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   207     |     4    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK             | CLK_STATE_READY     | 80000000        |
|   207     |     5    | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|   207     |     6    | DEV_MCU_MCAN0_MCANSS_CAN_RXD                                                      | CLK_STATE_READY     | 0               |
|   208     |     0    | DEV_MCU_MCAN1_MCANSS_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|   208     |     1    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK                                                     | CLK_STATE_READY     | 80000000        |
|   208     |     2    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK             | CLK_STATE_READY     | 80000000        |
|   208     |     3    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|   208     |     4    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK             | CLK_STATE_READY     | 80000000        |
|   208     |     5    | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|   208     |     6    | DEV_MCU_MCAN1_MCANSS_CAN_RXD                                                      | CLK_STATE_READY     | 0               |
|   347     |     0    | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
|   347     |     1    | DEV_MCU_MCSPI0_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
|   347     |     2    | DEV_MCU_MCSPI0_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
|   347     |     3    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK                                                     | CLK_STATE_READY     | 0               |
|   347     |     4    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT                     | CLK_STATE_READY     | 0               |
|   347     |     5    | DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK                     | CLK_STATE_READY     | 0               |
|   348     |     0    | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
|   348     |     1    | DEV_MCU_MCSPI1_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
|   348     |     2    | DEV_MCU_MCSPI1_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
|   348     |     3    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK                                                     | CLK_STATE_NOT_READY | 0               |
|   348     |     4    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK                    | CLK_STATE_NOT_READY | 0               |
|   348     |     5    | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_MCU_SPI1_CLK_LPBK_MUX_OUT0                   | CLK_STATE_READY     | 0               |
|   349     |     0    | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK                                                     | CLK_STATE_READY     | 0               |
|   349     |     1    | DEV_MCU_MCSPI2_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
|   349     |     2    | DEV_MCU_MCSPI2_CLKSPIREF_CLK                                                      | CLK_STATE_READY     | 50000000        |
|   349     |     3    | DEV_MCU_MCSPI2_IO_CLKSPII_CLK                                                     | CLK_STATE_READY     | 0               |
|   268     |     0    | DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK                                             | CLK_STATE_READY     | 1000000000      |
|   269     |     0    | DEV_MCU_NAVSS0_MCRC_0_CLK                                                         | CLK_STATE_READY     | 1000000000      |
|   270     |     0    | DEV_MCU_NAVSS0_MODSS_VD2CLK                                                       | CLK_STATE_READY     | 1000000000      |
|   271     |     0    | DEV_MCU_NAVSS0_PROXY0_CLK_CLK                                                     | CLK_STATE_READY     | 1000000000      |
|   272     |     0    | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK                                                   | CLK_STATE_READY     | 1000000000      |
|   273     |     0    | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK                                                    | CLK_STATE_READY     | 1000000000      |
|   274     |     0    | DEV_MCU_NAVSS0_UDMASS_VD2CLK                                                      | CLK_STATE_READY     | 1000000000      |
|   275     |     0    | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK                                              | CLK_STATE_READY     | 1000000000      |
|   176     |     0    | DEV_MCU_PBIST0_CLK6_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   176     |     1    | DEV_MCU_PBIST0_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   176     |     3    | DEV_MCU_PBIST0_CLK3_CLK                                                           | CLK_STATE_READY     | 166666666       |
|   176     |     4    | DEV_MCU_PBIST0_CLK7_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   176     |     6    | DEV_MCU_PBIST0_CLK4_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   176     |     7    | DEV_MCU_PBIST0_CLK5_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   176     |     8    | DEV_MCU_PBIST0_CLK1_CLK                                                           | CLK_STATE_READY     | 500000000       |
|   176     |     9    | DEV_MCU_PBIST0_CLK2_CLK                                                           | CLK_STATE_READY     | 333333333       |
|   177     |     0    | DEV_MCU_PBIST1_CLK6_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   177     |     1    | DEV_MCU_PBIST1_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   177     |     3    | DEV_MCU_PBIST1_CLK3_CLK                                                           | CLK_STATE_READY     | 333333333       |
|   177     |     4    | DEV_MCU_PBIST1_CLK7_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   177     |     6    | DEV_MCU_PBIST1_CLK4_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   177     |     7    | DEV_MCU_PBIST1_CLK5_CLK                                                           | CLK_STATE_READY     | 166666666       |
|   177     |     8    | DEV_MCU_PBIST1_CLK1_CLK                                                           | CLK_STATE_READY     | 500000000       |
|   177     |     9    | DEV_MCU_PBIST1_CLK2_CLK                                                           | CLK_STATE_READY     | 400000000       |
|   178     |     1    | DEV_MCU_PBIST2_CLK8_CLK                                                           | CLK_STATE_READY     | 83333333        |
|   284     |     0    | DEV_MCU_R5FSS0_CORE0_CPU_CLK                                                      | CLK_STATE_READY     | 1000000000      |
|   284     |     1    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 1000000000      |
|   284     |     2    | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3    | CLK_STATE_READY     | 333333333       |
|   284     |     3    | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK                                                | CLK_STATE_READY     | 1000000000      |
|   284     |     4    | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE                                              | CLK_STATE_READY     | 333333333       |
|   285     |     0    | DEV_MCU_R5FSS0_CORE1_CPU_CLK                                                      | CLK_STATE_READY     | 1000000000      |
|   285     |     1    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 1000000000      |
|   285     |     2    | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3    | CLK_STATE_READY     | 333333333       |
|   285     |     3    | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK                                                | CLK_STATE_READY     | 1000000000      |
|   285     |     4    | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE                                              | CLK_STATE_READY     | 333333333       |
|   295     |     0    | DEV_MCU_RTI0_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       |
|   295     |     1    | DEV_MCU_RTI0_RTI_CLK                                                              | CLK_STATE_READY     | 19200000        |
|   295     |     2    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                               | CLK_STATE_READY     | 19200000        |
|   295     |     3    | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                               | CLK_STATE_READY     | 32768           |
|   295     |     4    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK          | CLK_STATE_READY     | 12500000        |
|   295     |     5    | DEV_MCU_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK            | CLK_STATE_READY     | 32000           |
|   296     |     0    | DEV_MCU_RTI1_VBUSP_CLK                                                            | CLK_STATE_READY     | 166666666       |
|   296     |     1    | DEV_MCU_RTI1_RTI_CLK                                                              | CLK_STATE_READY     | 19200000        |
|   296     |     2    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                               | CLK_STATE_READY     | 19200000        |
|   296     |     3    | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                               | CLK_STATE_READY     | 32768           |
|   296     |     4    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK          | CLK_STATE_READY     | 12500000        |
|   296     |     5    | DEV_MCU_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK            | CLK_STATE_READY     | 32000           |
|    35     |     0    | DEV_MCU_TIMER0_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
|    35     |     1    | DEV_MCU_TIMER0_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 62500000        |
|    35     |     2    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|    35     |     3    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
|    35     |     4    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
|    35     |     5    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
|    35     |     6    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|    35     |     7    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
|    35     |     8    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
|    35     |     9    | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
|    35     |    10    | DEV_MCU_TIMER0_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    83     |     1    | DEV_MCU_TIMER1_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    83     |     2    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1                        | CLK_STATE_READY     | 19200000        |
|    83     |     3    | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM               | CLK_STATE_READY     | 0               |
|    83     |    10    | DEV_MCU_TIMER1_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    84     |     0    | DEV_MCU_TIMER2_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
|    84     |     1    | DEV_MCU_TIMER2_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    84     |     2    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|    84     |     3    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
|    84     |     4    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
|    84     |     5    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
|    84     |     6    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|    84     |     7    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
|    84     |     8    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
|    84     |     9    | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
|    84     |    10    | DEV_MCU_TIMER2_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    85     |     1    | DEV_MCU_TIMER3_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    85     |     2    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3                        | CLK_STATE_READY     | 19200000        |
|    85     |     3    | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM               | CLK_STATE_READY     | 0               |
|    85     |    10    | DEV_MCU_TIMER3_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    86     |     0    | DEV_MCU_TIMER4_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
|    86     |     1    | DEV_MCU_TIMER4_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    86     |     2    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|    86     |     3    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
|    86     |     4    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
|    86     |     5    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
|    86     |     6    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|    86     |     7    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
|    86     |     8    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
|    86     |     9    | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
|    86     |    10    | DEV_MCU_TIMER4_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    87     |     1    | DEV_MCU_TIMER5_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    87     |     2    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5                        | CLK_STATE_READY     | 19200000        |
|    87     |     3    | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM               | CLK_STATE_READY     | 0               |
|    87     |    10    | DEV_MCU_TIMER5_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    88     |     0    | DEV_MCU_TIMER6_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
|    88     |     1    | DEV_MCU_TIMER6_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    88     |     2    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|    88     |     3    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
|    88     |     4    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
|    88     |     5    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
|    88     |     6    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|    88     |     7    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
|    88     |     8    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
|    88     |     9    | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
|    88     |    10    | DEV_MCU_TIMER6_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    89     |     1    | DEV_MCU_TIMER7_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    89     |     2    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7                        | CLK_STATE_READY     | 19200000        |
|    89     |     3    | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM               | CLK_STATE_READY     | 0               |
|    89     |    10    | DEV_MCU_TIMER7_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    90     |     0    | DEV_MCU_TIMER8_TIMER_PWM                                                          | CLK_STATE_READY     | 0               |
|    90     |     1    | DEV_MCU_TIMER8_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 19200000        |
|    90     |     2    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                      | CLK_STATE_READY     | 19200000        |
|    90     |     3    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16  | CLK_STATE_READY     | 62500000        |
|    90     |     4    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY     | 12500000        |
|    90     |     5    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK             | CLK_STATE_READY     | 200000000       |
|    90     |     6    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY     | 0               |
|    90     |     7    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                      | CLK_STATE_READY     | 32768           |
|    90     |     8    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0                  | CLK_STATE_READY     | 0               |
|    90     |     9    | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK   | CLK_STATE_READY     | 32000           |
|    90     |    10    | DEV_MCU_TIMER8_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|    91     |     1    | DEV_MCU_TIMER9_TIMER_TCLK_CLK                                                     | CLK_STATE_READY     | 62500000        |
|    91     |     2    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9                        | CLK_STATE_READY     | 62500000        |
|    91     |     3    | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM               | CLK_STATE_READY     | 0               |
|    91     |    10    | DEV_MCU_TIMER9_TIMER_HCLK_CLK                                                     | CLK_STATE_READY     | 166666666       |
|   149     |     2    | DEV_MCU_UART0_VBUSP_CLK                                                           | CLK_STATE_READY     | 166666666       |
|   149     |     3    | DEV_MCU_UART0_FCLK_CLK                                                            | CLK_STATE_READY     | 96000000        |
|   149     |     4    | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                    | CLK_STATE_READY     | 96000000        |
|   149     |     5    | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK                 | CLK_STATE_READY     | 192000000       |
|    98     |     1    | DEV_MMCSD0_EMMCSS_XIN_CLK                                                         | CLK_STATE_READY     | 200000000       |
|    98     |     2    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
|    98     |     3    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK                | CLK_STATE_READY     | 192000000       |
|    98     |     4    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
|    98     |     5    | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK                | CLK_STATE_READY     | 200000000       |
|    98     |     7    | DEV_MMCSD0_EMMCSS_VBUS_CLK                                                        | CLK_STATE_READY     | 250000000       |
|    99     |     1    | DEV_MMCSD1_EMMCSDSS_XIN_CLK                                                       | CLK_STATE_READY     | 200000000       |
|    99     |     2    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
|    99     |     3    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK              | CLK_STATE_READY     | 192000000       |
|    99     |     4    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
|    99     |     5    | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK              | CLK_STATE_READY     | 200000000       |
|    99     |     6    | DEV_MMCSD1_EMMCSDSS_IO_CLK_O                                                      | CLK_STATE_READY     | 0               |
|    99     |     7    | DEV_MMCSD1_EMMCSDSS_IO_CLK_I                                                      | CLK_STATE_READY     | 0               |
|    99     |     8    | DEV_MMCSD1_EMMCSDSS_VBUS_CLK                                                      | CLK_STATE_READY     | 250000000       |
|   224     |     0    | DEV_NAVSS0_CPTS0_GENF2                                                            | CLK_STATE_READY     | 0               |
|   224     |     1    | DEV_NAVSS0_CPTS0_GENF3                                                            | CLK_STATE_READY     | 0               |
|   225     |     0    | DEV_NAVSS0_BCDMA_0_CLK                                                            | CLK_STATE_READY     | 500000000       |
|   226     |     0    | DEV_NAVSS0_CPTS_0_TS_GENF0                                                        | CLK_STATE_READY     | 0               |
|   226     |     2    | DEV_NAVSS0_CPTS_0_TS_GENF1                                                        | CLK_STATE_READY     | 0               |
|   226     |     4    | DEV_NAVSS0_CPTS_0_VBUSP_GCLK                                                      | CLK_STATE_READY     | 500000000       |
|   226     |     5    | DEV_NAVSS0_CPTS_0_RCLK                                                            | CLK_STATE_READY     | 200000000       |
|   226     |     6    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK                   | CLK_STATE_READY     | 200000000       |
|   226     |     7    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK                 | CLK_STATE_READY     | 250000000       |
|   226     |     8    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
|   226     |     9    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                           | CLK_STATE_READY     | 0               |
|   226     |    10    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                         | CLK_STATE_READY     | 0               |
|   226     |    11    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                             | CLK_STATE_READY     | 0               |
|   226     |    12    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|   226     |    13    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|   226     |    14    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|   226     |    15    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK                  | CLK_STATE_NOT_READY | 0               |
|   226     |    20    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK                    | CLK_STATE_READY     | 500000000       |
|   226     |    21    | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK           | CLK_STATE_READY     | 500000000       |
|   227     |     0    | DEV_NAVSS0_INTR_0_INTR_CLK                                                        | CLK_STATE_READY     | 500000000       |
|   228     |     0    | DEV_NAVSS0_MAILBOX1_0_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   229     |     0    | DEV_NAVSS0_MAILBOX1_1_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   238     |     0    | DEV_NAVSS0_MAILBOX1_10_VCLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
|   239     |     0    | DEV_NAVSS0_MAILBOX1_11_VCLK_CLK                                                   | CLK_STATE_READY     | 500000000       |
|   230     |     0    | DEV_NAVSS0_MAILBOX1_2_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   231     |     0    | DEV_NAVSS0_MAILBOX1_3_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   232     |     0    | DEV_NAVSS0_MAILBOX1_4_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   233     |     0    | DEV_NAVSS0_MAILBOX1_5_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   234     |     0    | DEV_NAVSS0_MAILBOX1_6_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   235     |     0    | DEV_NAVSS0_MAILBOX1_7_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   236     |     0    | DEV_NAVSS0_MAILBOX1_8_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   237     |     0    | DEV_NAVSS0_MAILBOX1_9_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   240     |     0    | DEV_NAVSS0_MAILBOX_0_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   241     |     0    | DEV_NAVSS0_MAILBOX_1_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   250     |     0    | DEV_NAVSS0_MAILBOX_10_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   251     |     0    | DEV_NAVSS0_MAILBOX_11_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   242     |     0    | DEV_NAVSS0_MAILBOX_2_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   243     |     0    | DEV_NAVSS0_MAILBOX_3_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   244     |     0    | DEV_NAVSS0_MAILBOX_4_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   245     |     0    | DEV_NAVSS0_MAILBOX_5_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   246     |     0    | DEV_NAVSS0_MAILBOX_6_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   247     |     0    | DEV_NAVSS0_MAILBOX_7_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   248     |     0    | DEV_NAVSS0_MAILBOX_8_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   249     |     0    | DEV_NAVSS0_MAILBOX_9_VCLK_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   252     |     0    | DEV_NAVSS0_MCRC_0_CLK                                                             | CLK_STATE_READY     | 500000000       |
|   253     |     0    | DEV_NAVSS0_MODSS_VD2CLK                                                           | CLK_STATE_READY     | 500000000       |
|   254     |     0    | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK                                                   | CLK_STATE_READY     | 500000000       |
|   255     |     0    | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK                                                   | CLK_STATE_READY     | 500000000       |
|   256     |     0    | DEV_NAVSS0_PROXY_0_CLK_CLK                                                        | CLK_STATE_READY     | 500000000       |
|   257     |     0    | DEV_NAVSS0_PVU_0_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       |
|   258     |     0    | DEV_NAVSS0_PVU_1_CLK_CLK                                                          | CLK_STATE_READY     | 500000000       |
|   259     |     0    | DEV_NAVSS0_RINGACC_0_SYS_CLK                                                      | CLK_STATE_READY     | 500000000       |
|   260     |     0    | DEV_NAVSS0_SPINLOCK_0_CLK                                                         | CLK_STATE_READY     | 500000000       |
|   261     |     0    | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT                                                | CLK_STATE_READY     | 0               |
|   261     |     1    | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   262     |     0    | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT                                                | CLK_STATE_READY     | 0               |
|   262     |     1    | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK                                                    | CLK_STATE_READY     | 500000000       |
|   263     |     0    | DEV_NAVSS0_UDMAP_0_SYS_CLK                                                        | CLK_STATE_READY     | 500000000       |
|   264     |     0    | DEV_NAVSS0_UDMASS_VD2CLK                                                          | CLK_STATE_READY     | 500000000       |
|   265     |     0    | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK                                                  | CLK_STATE_READY     | 500000000       |
|   266     |     0    | DEV_NAVSS0_VIRTSS_VD2CLK                                                          | CLK_STATE_READY     | 500000000       |
|   171     |     1    | DEV_PBIST0_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   172     |     1    | DEV_PBIST1_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   175     |     1    | DEV_PBIST10_CLK8_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   168     |     4    | DEV_PBIST11_CLK7_CLK                                                              | CLK_STATE_READY     | 125000000       |
|   174     |     1    | DEV_PBIST2_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   170     |     1    | DEV_PBIST3_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   173     |     1    | DEV_PBIST4_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   167     |     1    | DEV_PBIST5_CLK8_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   276     |     0    | DEV_PCIE1_PCIE_LANE0_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |     1    | DEV_PCIE1_PCIE_LANE0_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |     2    | DEV_PCIE1_PCIE_LANE0_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |     3    | DEV_PCIE1_PCIE_LANE0_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |     4    | DEV_PCIE1_PCIE_LANE3_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |     5    | DEV_PCIE1_PCIE_LANE3_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |     6    | DEV_PCIE1_PCIE_LANE2_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |     7    | DEV_PCIE1_PCIE_LANE1_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |     8    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK                                                      | CLK_STATE_READY     | 200000000       |
|   276     |     9    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK             | CLK_STATE_READY     | 200000000       |
|   276     |    10    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK           | CLK_STATE_READY     | 250000000       |
|   276     |    11    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT                 | CLK_STATE_READY     | 0               |
|   276     |    12    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                     | CLK_STATE_READY     | 0               |
|   276     |    13    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                   | CLK_STATE_READY     | 0               |
|   276     |    14    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                       | CLK_STATE_READY     | 0               |
|   276     |    15    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK            | CLK_STATE_NOT_READY | 0               |
|   276     |    16    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK            | CLK_STATE_NOT_READY | 0               |
|   276     |    17    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK            | CLK_STATE_NOT_READY | 0               |
|   276     |    18    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK            | CLK_STATE_NOT_READY | 0               |
|   276     |    23    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK              | CLK_STATE_READY     | 500000000       |
|   276     |    24    | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK     | CLK_STATE_READY     | 500000000       |
|   276     |    26    | DEV_PCIE1_PCIE_LANE3_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    27    | DEV_PCIE1_PCIE_LANE2_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |    28    | DEV_PCIE1_PCIE_LANE1_RXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    29    | DEV_PCIE1_PCIE_LANE0_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |    30    | DEV_PCIE1_PCIE_LANE2_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    31    | DEV_PCIE1_PCIE_LANE3_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    32    | DEV_PCIE1_PCIE_LANE2_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    33    | DEV_PCIE1_PCIE_LANE1_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    34    | DEV_PCIE1_PCIE_LANE2_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    35    | DEV_PCIE1_PCIE_PM_CLK                                                             | CLK_STATE_READY     | 12500000        |
|   276     |    36    | DEV_PCIE1_PCIE_LANE1_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    37    | DEV_PCIE1_PCIE_LANE1_TXMCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    38    | DEV_PCIE1_PCIE_LANE0_REFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    39    | DEV_PCIE1_PCIE_LANE1_RXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |    40    | DEV_PCIE1_PCIE_LANE3_TXFCLK                                                       | CLK_STATE_READY     | 0               |
|   276     |    41    | DEV_PCIE1_PCIE_CBA_CLK                                                            | CLK_STATE_READY     | 250000000       |
|   276     |    42    | DEV_PCIE1_PCIE_LANE2_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   276     |    43    | DEV_PCIE1_PCIE_LANE3_TXCLK                                                        | CLK_STATE_READY     | 0               |
|   143     |     0    | DEV_PSC0_SLOW_CLK                                                                 | CLK_STATE_READY     | 20833333        |
|   143     |     1    | DEV_PSC0_CLK                                                                      | CLK_STATE_READY     | 125000000       |
|   279     |     0    | DEV_R5FSS0_CORE0_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
|   279     |     1    | DEV_R5FSS0_CORE0_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
|   280     |     0    | DEV_R5FSS0_CORE1_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
|   280     |     1    | DEV_R5FSS0_CORE1_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
|   281     |     0    | DEV_R5FSS1_CORE0_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
|   281     |     1    | DEV_R5FSS1_CORE0_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
|   282     |     0    | DEV_R5FSS1_CORE1_CPU_CLK                                                          | CLK_STATE_READY     | 1000000000      |
|   282     |     1    | DEV_R5FSS1_CORE1_INTERFACE_CLK                                                    | CLK_STATE_READY     | 1000000000      |
|   286     |     0    | DEV_RTI0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   286     |     1    | DEV_RTI0_RTI_CLK                                                                  | CLK_STATE_READY     | 19200000        |
|   286     |     2    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                   | CLK_STATE_READY     | 19200000        |
|   286     |     3    | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                   | CLK_STATE_READY     | 32768           |
|   286     |     4    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK              | CLK_STATE_READY     | 12500000        |
|   286     |     5    | DEV_RTI0_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                | CLK_STATE_READY     | 32000           |
|   286     |     6    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                    | CLK_STATE_READY     | 0               |
|   286     |     7    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                               | CLK_STATE_READY     | 0               |
|   286     |     8    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                               | CLK_STATE_READY     | 0               |
|   286     |     9    | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                               | CLK_STATE_READY     | 0               |
|   287     |     0    | DEV_RTI1_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   287     |     1    | DEV_RTI1_RTI_CLK                                                                  | CLK_STATE_READY     | 19200000        |
|   287     |     2    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                   | CLK_STATE_READY     | 19200000        |
|   287     |     3    | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                   | CLK_STATE_READY     | 32768           |
|   287     |     4    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK              | CLK_STATE_READY     | 12500000        |
|   287     |     5    | DEV_RTI1_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK                | CLK_STATE_READY     | 32000           |
|   287     |     6    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                    | CLK_STATE_READY     | 0               |
|   287     |     7    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                               | CLK_STATE_READY     | 0               |
|   287     |     8    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                               | CLK_STATE_READY     | 0               |
|   287     |     9    | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                               | CLK_STATE_READY     | 0               |
|   290     |     0    | DEV_RTI15_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   290     |     1    | DEV_RTI15_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   290     |     2    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   290     |     3    | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   290     |     4    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   290     |     5    | DEV_RTI15_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   290     |     6    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   290     |     7    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   290     |     8    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   290     |     9    | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   288     |     0    | DEV_RTI16_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   288     |     1    | DEV_RTI16_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   288     |     2    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   288     |     3    | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   288     |     4    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   288     |     5    | DEV_RTI16_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   288     |     6    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   288     |     7    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   288     |     8    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   288     |     9    | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   289     |     0    | DEV_RTI17_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   289     |     1    | DEV_RTI17_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   289     |     2    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   289     |     3    | DEV_RTI17_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   289     |     4    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   289     |     5    | DEV_RTI17_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   289     |     6    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   289     |     7    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   289     |     8    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   289     |     9    | DEV_RTI17_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   291     |     0    | DEV_RTI28_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   291     |     1    | DEV_RTI28_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   291     |     2    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   291     |     3    | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   291     |     4    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   291     |     5    | DEV_RTI28_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   291     |     6    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   291     |     7    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   291     |     8    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   291     |     9    | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   292     |     0    | DEV_RTI29_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   292     |     1    | DEV_RTI29_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   292     |     2    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   292     |     3    | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   292     |     4    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   292     |     5    | DEV_RTI29_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   292     |     6    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   292     |     7    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   292     |     8    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   292     |     9    | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   293     |     0    | DEV_RTI30_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   293     |     1    | DEV_RTI30_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   293     |     2    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   293     |     3    | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   293     |     4    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   293     |     5    | DEV_RTI30_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   293     |     6    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   293     |     7    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   293     |     8    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   293     |     9    | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   294     |     0    | DEV_RTI31_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   294     |     1    | DEV_RTI31_RTI_CLK                                                                 | CLK_STATE_READY     | 19200000        |
|   294     |     2    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                  | CLK_STATE_READY     | 19200000        |
|   294     |     3    | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                                  | CLK_STATE_READY     | 32768           |
|   294     |     4    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK             | CLK_STATE_READY     | 12500000        |
|   294     |     5    | DEV_RTI31_RTI_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK               | CLK_STATE_READY     | 32000           |
|   294     |     6    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                                   | CLK_STATE_READY     | 0               |
|   294     |     7    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0                              | CLK_STATE_READY     | 0               |
|   294     |     8    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1                              | CLK_STATE_READY     | 0               |
|   294     |     9    | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2                              | CLK_STATE_READY     | 0               |
|   145     |     0    | DEV_SA2_CPSW_PSILSS0_MAIN_CLK                                                     | CLK_STATE_READY     | 500000000       |
|   145     |     1    | DEV_SA2_CPSW_PSILSS0_MAIN_2_CLK                                                   | CLK_STATE_READY     | 250000000       |
|   297     |     0    | DEV_SA2_UL0_PKA_IN_CLK                                                            | CLK_STATE_READY     | 400000000       |
|   297     |     1    | DEV_SA2_UL0_X1_CLK                                                                | CLK_STATE_READY     | 125000000       |
|   297     |     2    | DEV_SA2_UL0_X2_CLK                                                                | CLK_STATE_READY     | 250000000       |
|   365     |     0    | DEV_SERDES_10G0_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   365     |     1    | DEV_SERDES_10G0_CMN_REFCLK_M                                                      | CLK_STATE_READY     | 0               |
|   365     |     1    | DEV_SERDES_10G0_CMN_REFCLK_M                                                      | CLK_STATE_READY     | 0               |
|   365     |     2    | DEV_SERDES_10G0_CMN_REFCLK_P                                                      | CLK_STATE_READY     | 0               |
|   365     |     2    | DEV_SERDES_10G0_CMN_REFCLK_P                                                      | CLK_STATE_READY     | 0               |
|   365     |     3    | DEV_SERDES_10G0_CORE_REF_CLK                                                      | CLK_STATE_READY     | 19200000        |
|   365     |     4    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                       | CLK_STATE_READY     | 19200000        |
|   365     |     5    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                        | CLK_STATE_READY     | 0               |
|   365     |     6    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK             | CLK_STATE_READY     | 125000000       |
|   365     |     7    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK             | CLK_STATE_READY     | 100000000       |
|   365     |     9    | DEV_SERDES_10G0_IP1_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    10    | DEV_SERDES_10G0_IP1_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    11    | DEV_SERDES_10G0_IP1_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    12    | DEV_SERDES_10G0_IP1_LN0_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    13    | DEV_SERDES_10G0_IP1_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    14    | DEV_SERDES_10G0_IP1_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    15    | DEV_SERDES_10G0_IP1_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    16    | DEV_SERDES_10G0_IP1_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    17    | DEV_SERDES_10G0_IP1_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    18    | DEV_SERDES_10G0_IP1_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    19    | DEV_SERDES_10G0_IP1_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    20    | DEV_SERDES_10G0_IP1_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    21    | DEV_SERDES_10G0_IP1_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    22    | DEV_SERDES_10G0_IP1_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    23    | DEV_SERDES_10G0_IP1_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    24    | DEV_SERDES_10G0_IP1_LN2_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
|   365     |    25    | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK              | CLK_STATE_NOT_READY | 0               |
|   365     |    26    | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK              | CLK_STATE_NOT_READY | 0               |
|   365     |    27    | DEV_SERDES_10G0_IP1_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    28    | DEV_SERDES_10G0_IP1_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    29    | DEV_SERDES_10G0_IP1_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    30    | DEV_SERDES_10G0_IP1_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    31    | DEV_SERDES_10G0_IP1_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    32    | DEV_SERDES_10G0_IP1_LN3_TXCLK                                                     | CLK_STATE_NOT_READY | 0               |
|   365     |    33    | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK              | CLK_STATE_NOT_READY | 0               |
|   365     |    34    | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK              | CLK_STATE_NOT_READY | 0               |
|   365     |    35    | DEV_SERDES_10G0_IP1_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    36    | DEV_SERDES_10G0_IP1_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    37    | DEV_SERDES_10G0_IP2_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    38    | DEV_SERDES_10G0_IP2_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    39    | DEV_SERDES_10G0_IP2_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    40    | DEV_SERDES_10G0_IP2_LN0_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    41    | DEV_SERDES_10G0_IP2_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    42    | DEV_SERDES_10G0_IP2_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    43    | DEV_SERDES_10G0_IP2_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    44    | DEV_SERDES_10G0_IP2_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    45    | DEV_SERDES_10G0_IP2_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    46    | DEV_SERDES_10G0_IP2_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    47    | DEV_SERDES_10G0_IP2_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    48    | DEV_SERDES_10G0_IP2_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    49    | DEV_SERDES_10G0_IP2_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    50    | DEV_SERDES_10G0_IP2_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    51    | DEV_SERDES_10G0_IP2_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    52    | DEV_SERDES_10G0_IP2_LN2_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    53    | DEV_SERDES_10G0_IP2_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    54    | DEV_SERDES_10G0_IP2_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    55    | DEV_SERDES_10G0_IP2_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    56    | DEV_SERDES_10G0_IP2_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    57    | DEV_SERDES_10G0_IP2_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    58    | DEV_SERDES_10G0_IP2_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    59    | DEV_SERDES_10G0_IP2_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    60    | DEV_SERDES_10G0_IP2_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    67    | DEV_SERDES_10G0_IP3_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    68    | DEV_SERDES_10G0_IP3_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    69    | DEV_SERDES_10G0_IP3_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    70    | DEV_SERDES_10G0_IP3_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    71    | DEV_SERDES_10G0_IP3_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    72    | DEV_SERDES_10G0_IP3_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    79    | DEV_SERDES_10G0_IP3_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    80    | DEV_SERDES_10G0_IP3_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    81    | DEV_SERDES_10G0_IP3_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    82    | DEV_SERDES_10G0_IP3_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    83    | DEV_SERDES_10G0_IP3_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    84    | DEV_SERDES_10G0_IP3_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    85    | DEV_SERDES_10G0_IP4_LN0_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    86    | DEV_SERDES_10G0_IP4_LN0_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    87    | DEV_SERDES_10G0_IP4_LN0_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    88    | DEV_SERDES_10G0_IP4_LN0_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    89    | DEV_SERDES_10G0_IP4_LN0_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    90    | DEV_SERDES_10G0_IP4_LN0_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    91    | DEV_SERDES_10G0_IP4_LN1_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    92    | DEV_SERDES_10G0_IP4_LN1_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    93    | DEV_SERDES_10G0_IP4_LN1_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    94    | DEV_SERDES_10G0_IP4_LN1_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    95    | DEV_SERDES_10G0_IP4_LN1_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    96    | DEV_SERDES_10G0_IP4_LN1_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    97    | DEV_SERDES_10G0_IP4_LN2_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |    98    | DEV_SERDES_10G0_IP4_LN2_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |    99    | DEV_SERDES_10G0_IP4_LN2_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   100    | DEV_SERDES_10G0_IP4_LN2_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |   101    | DEV_SERDES_10G0_IP4_LN2_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   102    | DEV_SERDES_10G0_IP4_LN2_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   103    | DEV_SERDES_10G0_IP4_LN3_REFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   104    | DEV_SERDES_10G0_IP4_LN3_RXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |   105    | DEV_SERDES_10G0_IP4_LN3_RXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   106    | DEV_SERDES_10G0_IP4_LN3_TXCLK                                                     | CLK_STATE_READY     | 0               |
|   365     |   107    | DEV_SERDES_10G0_IP4_LN3_TXFCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   108    | DEV_SERDES_10G0_IP4_LN3_TXMCLK                                                    | CLK_STATE_READY     | 0               |
|   365     |   130    | DEV_SERDES_10G0_TAP_TCK                                                           | CLK_STATE_READY     | 0               |
|    42     |     0    | DEV_STM0_CORE_CLK                                                                 | CLK_STATE_READY     | 250000000       |
|    42     |     1    | DEV_STM0_VBUSP_CLK                                                                | CLK_STATE_READY     | 125000000       |
|    42     |     2    | DEV_STM0_ATB_CLK                                                                  | CLK_STATE_READY     | 250000000       |
|    63     |     0    | DEV_TIMER0_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
|    63     |     1    | DEV_TIMER0_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    63     |     2    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|    63     |     3    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|    63     |     4    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
|    63     |     5    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
|    63     |     6    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
|    63     |     7    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|    63     |     8    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
|    63     |     9    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
|    63     |    10    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
|    63     |    11    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
|    63     |    12    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
|    63     |    13    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
|    63     |    14    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
|    63     |    15    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
|    63     |    16    | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_READY     | 0               |
|    63     |    18    | DEV_TIMER0_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    64     |     1    | DEV_TIMER1_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    64     |     2    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1                           | CLK_STATE_READY     | 19200000        |
|    64     |     3    | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM                  | CLK_STATE_READY     | 0               |
|    64     |    18    | DEV_TIMER1_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    73     |     0    | DEV_TIMER10_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
|    73     |     1    | DEV_TIMER10_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    73     |     2    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|    73     |     3    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|    73     |     4    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
|    73     |     5    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
|    73     |     6    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
|    73     |     7    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|    73     |     8    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
|    73     |     9    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
|    73     |    10    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
|    73     |    11    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
|    73     |    12    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
|    73     |    13    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
|    73     |    14    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
|    73     |    15    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
|    73     |    16    | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               |
|    73     |    18    | DEV_TIMER10_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    74     |     1    | DEV_TIMER11_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    74     |     2    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11                         | CLK_STATE_READY     | 19200000        |
|    74     |     3    | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
|    74     |    18    | DEV_TIMER11_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    75     |     0    | DEV_TIMER12_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
|    75     |     1    | DEV_TIMER12_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    75     |     2    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|    75     |     3    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|    75     |     4    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
|    75     |     5    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
|    75     |     6    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
|    75     |     7    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|    75     |     8    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
|    75     |     9    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
|    75     |    10    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
|    75     |    11    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
|    75     |    12    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
|    75     |    13    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
|    75     |    14    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
|    75     |    15    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
|    75     |    16    | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               |
|    75     |    18    | DEV_TIMER12_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    76     |     1    | DEV_TIMER13_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    76     |     2    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13                         | CLK_STATE_READY     | 19200000        |
|    76     |     3    | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
|    76     |    18    | DEV_TIMER13_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    77     |     0    | DEV_TIMER14_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
|    77     |     1    | DEV_TIMER14_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    77     |     2    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|    77     |     3    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|    77     |     4    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK             | CLK_STATE_READY     | 250000000       |
|    77     |     5    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK    | CLK_STATE_READY     | 12500000        |
|    77     |     6    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK               | CLK_STATE_READY     | 250000000       |
|    77     |     7    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                     | CLK_STATE_READY     | 0               |
|    77     |     8    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                         | CLK_STATE_READY     | 0               |
|    77     |     9    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                         | CLK_STATE_READY     | 32768           |
|    77     |    10    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                       | CLK_STATE_READY     | 0               |
|    77     |    11    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK               | CLK_STATE_READY     | 192000000       |
|    77     |    12    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK             | CLK_STATE_READY     | 225000000       |
|    77     |    13    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK               | CLK_STATE_READY     | 196608000       |
|    77     |    14    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                 | CLK_STATE_READY     | 0               |
|    77     |    15    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                 | CLK_STATE_READY     | 0               |
|    77     |    16    | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                    | CLK_STATE_READY     | 0               |
|    77     |    18    | DEV_TIMER14_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    78     |     1    | DEV_TIMER15_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    78     |     2    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15                         | CLK_STATE_READY     | 19200000        |
|    78     |     3    | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
|    78     |    18    | DEV_TIMER15_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    79     |     0    | DEV_TIMER16_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
|    79     |     1    | DEV_TIMER16_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    79     |     2    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT16                         | CLK_STATE_READY     | 19200000        |
|    79     |     3    | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_MAIN_TIMER16_AFS_SEL_OUT0                       | CLK_STATE_READY     | 0               |
|    79     |    34    | DEV_TIMER16_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    80     |     1    | DEV_TIMER17_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    80     |     2    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER17_AFS_EN_OUT0                        | CLK_STATE_READY     | 19200000        |
|    80     |     3    | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
|    80     |    34    | DEV_TIMER17_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    81     |     0    | DEV_TIMER18_TIMER_PWM                                                             | CLK_STATE_READY     | 0               |
|    81     |     1    | DEV_TIMER18_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    81     |     2    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT18                         | CLK_STATE_READY     | 19200000        |
|    81     |     3    | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_MAIN_TIMER18_AFS_SEL_OUT0                       | CLK_STATE_READY     | 0               |
|    81     |    34    | DEV_TIMER18_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    82     |     1    | DEV_TIMER19_TIMER_TCLK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|    82     |     2    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER19_AFS_EN_OUT0                        | CLK_STATE_READY     | 19200000        |
|    82     |     3    | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM                | CLK_STATE_NOT_READY | 0               |
|    82     |    34    | DEV_TIMER19_TIMER_HCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|    65     |     0    | DEV_TIMER2_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
|    65     |     1    | DEV_TIMER2_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    65     |     2    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|    65     |     3    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|    65     |     4    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
|    65     |     5    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
|    65     |     6    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
|    65     |     7    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|    65     |     8    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
|    65     |     9    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
|    65     |    10    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
|    65     |    11    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
|    65     |    12    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
|    65     |    13    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
|    65     |    14    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
|    65     |    15    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
|    65     |    16    | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_READY     | 0               |
|    65     |    18    | DEV_TIMER2_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    66     |     1    | DEV_TIMER3_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    66     |     2    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3                           | CLK_STATE_READY     | 19200000        |
|    66     |     3    | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM                  | CLK_STATE_READY     | 0               |
|    66     |    18    | DEV_TIMER3_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    67     |     0    | DEV_TIMER4_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
|    67     |     1    | DEV_TIMER4_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    67     |     2    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|    67     |     3    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|    67     |     4    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
|    67     |     5    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
|    67     |     6    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
|    67     |     7    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|    67     |     8    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
|    67     |     9    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
|    67     |    10    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
|    67     |    11    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
|    67     |    12    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
|    67     |    13    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
|    67     |    14    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
|    67     |    15    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
|    67     |    16    | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_READY     | 0               |
|    67     |    18    | DEV_TIMER4_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    68     |     1    | DEV_TIMER5_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    68     |     2    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5                           | CLK_STATE_READY     | 19200000        |
|    68     |     3    | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM                  | CLK_STATE_READY     | 0               |
|    68     |    18    | DEV_TIMER5_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    69     |     0    | DEV_TIMER6_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
|    69     |     1    | DEV_TIMER6_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    69     |     2    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|    69     |     3    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|    69     |     4    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
|    69     |     5    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
|    69     |     6    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
|    69     |     7    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|    69     |     8    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
|    69     |     9    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
|    69     |    10    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
|    69     |    11    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
|    69     |    12    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
|    69     |    13    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
|    69     |    14    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
|    69     |    15    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
|    69     |    16    | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_READY     | 0               |
|    69     |    18    | DEV_TIMER6_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    70     |     1    | DEV_TIMER7_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    70     |     2    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7                           | CLK_STATE_READY     | 19200000        |
|    70     |     3    | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM                  | CLK_STATE_READY     | 0               |
|    70     |    18    | DEV_TIMER7_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    71     |     0    | DEV_TIMER8_TIMER_PWM                                                              | CLK_STATE_READY     | 0               |
|    71     |     1    | DEV_TIMER8_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    71     |     2    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                          | CLK_STATE_READY     | 19200000        |
|    71     |     3    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                           | CLK_STATE_READY     | 0               |
|    71     |     4    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT8_CLK              | CLK_STATE_READY     | 250000000       |
|    71     |     5    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7AM_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK     | CLK_STATE_READY     | 12500000        |
|    71     |     6    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK                | CLK_STATE_READY     | 250000000       |
|    71     |     7    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                      | CLK_STATE_READY     | 0               |
|    71     |     8    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                          | CLK_STATE_READY     | 0               |
|    71     |     9    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT                          | CLK_STATE_READY     | 32768           |
|    71     |    10    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                        | CLK_STATE_READY     | 0               |
|    71     |    11    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK                | CLK_STATE_READY     | 192000000       |
|    71     |    12    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK              | CLK_STATE_READY     | 225000000       |
|    71     |    13    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK                | CLK_STATE_READY     | 196608000       |
|    71     |    14    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF2                  | CLK_STATE_READY     | 0               |
|    71     |    15    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512J7AM_MAIN_0_CPTS0_GENF3                  | CLK_STATE_READY     | 0               |
|    71     |    16    | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MAIN_0_CPTS_GENF0                     | CLK_STATE_READY     | 0               |
|    71     |    18    | DEV_TIMER8_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|    72     |     1    | DEV_TIMER9_TIMER_TCLK_CLK                                                         | CLK_STATE_READY     | 19200000        |
|    72     |     2    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9                           | CLK_STATE_READY     | 19200000        |
|    72     |     3    | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM                  | CLK_STATE_NOT_READY | 0               |
|    72     |    18    | DEV_TIMER9_TIMER_HCLK_CLK                                                         | CLK_STATE_READY     | 125000000       |
|   124     |     0    | DEV_TIMESYNC_INTRTR0_INTR_CLK                                                     | CLK_STATE_READY     | 125000000       |
|   146     |     2    | DEV_UART0_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   146     |     3    | DEV_UART0_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   350     |     2    | DEV_UART1_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   350     |     3    | DEV_UART1_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   351     |     2    | DEV_UART2_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   351     |     3    | DEV_UART2_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   352     |     2    | DEV_UART3_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   352     |     3    | DEV_UART3_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   353     |     2    | DEV_UART4_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   353     |     3    | DEV_UART4_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   354     |     2    | DEV_UART5_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   354     |     3    | DEV_UART5_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   355     |     2    | DEV_UART6_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   355     |     3    | DEV_UART6_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   356     |     2    | DEV_UART7_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   356     |     3    | DEV_UART7_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   357     |     2    | DEV_UART8_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   357     |     3    | DEV_UART8_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   358     |     2    | DEV_UART9_VBUSP_CLK                                                               | CLK_STATE_READY     | 125000000       |
|   358     |     3    | DEV_UART9_FCLK_CLK                                                                | CLK_STATE_READY     | 48000000        |
|   360     |     1    | DEV_USB0_PIPE_RXFCLK                                                              | CLK_STATE_NOT_READY | 0               |
|   360     |     2    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXFCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |     3    | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXFCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |     4    | DEV_USB0_USB2_APB_PCLK_CLK                                                        | CLK_STATE_READY     | 125000000       |
|   360     |     5    | DEV_USB0_PIPE_TXCLK                                                               | CLK_STATE_READY     | 0               |
|   360     |     7    | DEV_USB0_PIPE_TXFCLK                                                              | CLK_STATE_NOT_READY | 0               |
|   360     |     8    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXFCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |     9    | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXFCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |    10    | DEV_USB0_PIPE_REFCLK                                                              | CLK_STATE_NOT_READY | 0               |
|   360     |    11    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_REFCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |    12    | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_REFCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |    13    | DEV_USB0_PCLK_CLK                                                                 | CLK_STATE_READY     | 125000000       |
|   360     |    15    | DEV_USB0_CLK_LPM_CLK                                                              | CLK_STATE_READY     | 24000000        |
|   360     |    16    | DEV_USB0_USB2_REFCLOCK_CLK                                                        | CLK_STATE_READY     | 19200000        |
|   360     |    17    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                         | CLK_STATE_READY     | 19200000        |
|   360     |    18    | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT                          | CLK_STATE_READY     | 0               |
|   360     |    19    | DEV_USB0_PIPE_RXCLK                                                               | CLK_STATE_NOT_READY | 0               |
|   360     |    20    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_RXCLK                      | CLK_STATE_NOT_READY | 0               |
|   360     |    21    | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_RXCLK                      | CLK_STATE_NOT_READY | 0               |
|   360     |    22    | DEV_USB0_ACLK_CLK                                                                 | CLK_STATE_READY     | 500000000       |
|   360     |    23    | DEV_USB0_BUF_CLK                                                                  | CLK_STATE_READY     | 250000000       |
|   360     |    25    | DEV_USB0_USB2_TAP_TCK                                                             | CLK_STATE_READY     | 0               |
|   360     |    26    | DEV_USB0_PIPE_TXMCLK                                                              | CLK_STATE_NOT_READY | 0               |
|   360     |    27    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN3_TXMCLK                    | CLK_STATE_NOT_READY | 0               |
|   360     |    28    | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP3_LN1_TXMCLK                    | CLK_STATE_NOT_READY | 0               |
|   361     |     0    | DEV_VPAC0_LDC0_CLK_CLK                                                            | CLK_STATE_READY     | 720000000       |
|   361     |     1    | DEV_VPAC0_NF_CLK_CLK                                                              | CLK_STATE_READY     | 720000000       |
|   361     |     2    | DEV_VPAC0_MAIN_CLK                                                                | CLK_STATE_READY     | 720000000       |
|   361     |     3    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT1_CLK                      | CLK_STATE_READY     | 720000000       |
|   361     |     4    | DEV_VPAC0_MAIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK                       | CLK_STATE_READY     | 600000000       |
|   361     |     5    | DEV_VPAC0_VISS0_CLK_CLK                                                           | CLK_STATE_READY     | 720000000       |
|   361     |     6    | DEV_VPAC0_PSIL_LEAF_CLK                                                           | CLK_STATE_READY     | 500000000       |
|   361     |     7    | DEV_VPAC0_MSC_CLK                                                                 | CLK_STATE_READY     | 720000000       |
|   362     |     0    | DEV_VUSR_DUAL0_V0_RXFL_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |     1    | DEV_VUSR_DUAL0_VUSRX_LN0_TXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |     2    | DEV_VUSR_DUAL0_V0_CLK                                                             | CLK_STATE_READY     | 500000000       |
|   362     |     3    | DEV_VUSR_DUAL0_V1_TXPM_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |     4    | DEV_VUSR_DUAL0_VUSRX_LN1_TXMCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |     5    | DEV_VUSR_DUAL0_V1_TXFL_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |     6    | DEV_VUSR_DUAL0_VUSRX_LN0_RXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |     7    | DEV_VUSR_DUAL0_VUSRX_LN2_RXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |     8    | DEV_VUSR_DUAL0_VUSRX_LN2_REFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |     9    | DEV_VUSR_DUAL0_VUSRX_LN3_RXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |    10    | DEV_VUSR_DUAL0_VUSRX_LN1_RXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    11    | DEV_VUSR_DUAL0_VUSRX_LN0_REFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    12    | DEV_VUSR_DUAL0_VUSRX_LN1_TXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |    13    | DEV_VUSR_DUAL0_VUSRX_LN3_RXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    14    | DEV_VUSR_DUAL0_VUSRX_LN3_TXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |    15    | DEV_VUSR_DUAL0_VUSRX_LN3_TXMCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    16    | DEV_VUSR_DUAL0_VUSRX_LN3_TXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    17    | DEV_VUSR_DUAL0_VUSRX_LN0_TXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |    18    | DEV_VUSR_DUAL0_V1_CLK                                                             | CLK_STATE_READY     | 500000000       |
|   362     |    19    | DEV_VUSR_DUAL0_V0_TXFL_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |    20    | DEV_VUSR_DUAL0_VUSRX_LN0_RXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    21    | DEV_VUSR_DUAL0_VUSRX_LN2_RXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |    22    | DEV_VUSR_DUAL0_V0_TXPM_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |    23    | DEV_VUSR_DUAL0_V0_RXPM_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |    24    | DEV_VUSR_DUAL0_VUSRX_LN1_REFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    25    | DEV_VUSR_DUAL0_V1_RXPM_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |    26    | DEV_VUSR_DUAL0_V1_RXFL_CLK                                                        | CLK_STATE_READY     | 0               |
|   362     |    27    | DEV_VUSR_DUAL0_VUSRX_LN2_TXCLK                                                    | CLK_STATE_READY     | 0               |
|   362     |    28    | DEV_VUSR_DUAL0_VUSRX_LN2_TXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    29    | DEV_VUSR_DUAL0_VUSRX_LN0_TXMCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    30    | DEV_VUSR_DUAL0_VUSRX_LN2_TXMCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    31    | DEV_VUSR_DUAL0_VUSRX_LN1_TXFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    32    | DEV_VUSR_DUAL0_VUSRX_LN3_REFCLK                                                   | CLK_STATE_READY     | 0               |
|   362     |    33    | DEV_VUSR_DUAL0_VUSRX_LN1_RXCLK                                                    | CLK_STATE_READY     | 0               |
|   151     |     0    | DEV_WKUP_DDPA0_DDPA_CLK                                                           | CLK_STATE_READY     | 166666666       |
|   104     |     0    | DEV_WKUP_ESM0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
|   115     |     0    | DEV_WKUP_GPIO0_MMR_CLK                                                            | CLK_STATE_READY     | 27777777        |
|   116     |     0    | DEV_WKUP_GPIO1_MMR_CLK                                                            | CLK_STATE_READY     | 27777777        |
|   125     |     0    | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK                                                 | CLK_STATE_READY     | 166666666       |
|   304     |     0    | DEV_WKUP_HSM0_DAP_CLK                                                             | CLK_STATE_READY     | 1000000000      |
|   223     |     0    | DEV_WKUP_I2C0_PORSCL                                                              | CLK_STATE_READY     | 0               |
|   223     |     1    | DEV_WKUP_I2C0_PISYS_CLK                                                           | CLK_STATE_READY     | 96000000        |
|   223     |     2    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK                   | CLK_STATE_READY     | 96000000        |
|   223     |     3    | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 19200000        |
|   223     |     4    | DEV_WKUP_I2C0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
|   223     |     5    | DEV_WKUP_I2C0_PISCL                                                               | CLK_STATE_READY     | 0               |
|   147     |     0    | DEV_WKUP_J7AM_WAKEUP_16FF0_PLL_CTRL_WKUP_CLK24_CLK                                | CLK_STATE_READY     | 1000000000      |
|   147     |     1    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_12P5M_CLK                                   | CLK_STATE_READY     | 12500000        |
|   147     |     2    | DEV_WKUP_J7AM_WAKEUP_16FF0_WKUP_RCOSC_32K_CLK                                     | CLK_STATE_READY     | 32000           |
|   123     |     0    | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK                                                | CLK_STATE_READY     | 12500000        |
|   126     |     0    | DEV_WKUP_PSC0_SLOW_CLK                                                            | CLK_STATE_READY     | 41666666        |
|   126     |     1    | DEV_WKUP_PSC0_CLK                                                                 | CLK_STATE_READY     | 166666666       |
|   359     |     2    | DEV_WKUP_UART0_VBUSP_CLK                                                          | CLK_STATE_READY     | 166666666       |
|   359     |     3    | DEV_WKUP_UART0_FCLK_CLK                                                           | CLK_STATE_READY     | 96000000        |
|   359     |     4    | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUP_USART_CLKSEL_OUT0                             | CLK_STATE_READY     | 96000000        |
|   359     |     5    | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT                            | CLK_STATE_READY     | 19200000        |
|   180     |     0    | DEV_WKUP_VTM0_FIX_REF_CLK                                                         | CLK_STATE_READY     | 19200000        |
|   180     |     1    | DEV_WKUP_VTM0_FIX_REF2_CLK                                                        | CLK_STATE_READY     | 12500000        |
|   180     |     2    | DEV_WKUP_VTM0_VBUSP_CLK                                                           | CLK_STATE_READY     | 166666666       |
|--------------------------------------------------------------------------------------------------------------------------------------------------|