------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  1(TIDL_DataConvertLayer) [1, 1] --[3 x 256 x  256] => [3 x 256 x  256] *** [3] ***[ COL] ***[0, 0, 0, 88064, 262144]**** [9], [0],[9] -[0 ]---
  IN: DDR, DMA,  40000(262144),  40000(262144),    3(    3),  c0400( 787456),   0,        0 ||||  L2, DMA,  2b000(176128),  2b000(176128),    1(    1),  2b000( 176128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  10040( 65600),  10000( 65536),    3(    3),  30100( 196864),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_ConvolutionLayer) [2, 2] --[3 x 256 x  256] => [24 x 128 x  128] *** [3] ***[ROW_L] ***[256, 256, 0, 37376, 65536]**** [2], [1],[2] -[1 ]---
  IN:MSMC, DMA,  10040( 65600),  10000( 65536),    3(    3),  30100( 196864),   0,        0 ||||  L2, DMA,  12540( 75072),  12540( 75072),    3(    3),  37080( 225408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   4040( 16448),   4001( 16385),   18(   24),  60600( 394752),   0,    30100 
  WT:DDR_PERSIST, DMA_ONCE,     1b(    27),     1b(    27),   18(   24),    300(    768),   0,        0 ||||MSMC, DMA_ONCE,     1b(    27),     1b(    27),   18(   24),    300(    768),   0,    f1c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_ConvolutionLayer) [3, 3] --[24 x 128 x  128] => [24 x 128 x  128] *** [1] ***[ COL] ***[0, 0, 0, 16384, 16384]**** [6], [1],[6] -[2 ]---
  IN:MSMC, DMA,   4040( 16448),   4001( 16385),   18(   24),  60600( 394752),   0,    30100 ||||  L2, DMA,   4000( 16384),   4000( 16384),    8(    8),  20080( 131200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   4040( 16448),   4000( 16384),   18(   24),  60600( 394752),   0,        0 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),   90(  144),    600(   1536),   0,      300 ||||MSMC, DMA,      a(    10),      a(    10),   90(  144),    600(   1536),   0,    90700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  4(TIDL_ConvolutionLayer) [4, 4] --[24 x 128 x  128] => [12 x 128 x  128] *** [24] ***[ROW_L] ***[0, 0, 0, 4512, 16384]**** [4], [1],[4] -[3 ]---
  IN:MSMC, DMA,   4040( 16448),   4000( 16384),   18(   24),  60600( 394752),   0,        0 ||||  L2, DMA,   2340(  9024),   2340(  9024),   18(   24),  37200( 225792),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   4040( 16448),   4000( 16384),    c(   12),  30300( 197376),   0,        0 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),    c(   12),    180(    384),   0,      900 ||||MSMC, DMA,     18(    24),     18(    24),    c(   12),    180(    384),   0,    60600 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  5(TIDL_ConvolutionLayer) [5, 5] --[12 x 128 x  128] => [72 x 128 x  128] *** [12] ***[ROW_L] ***[0, 0, 0, 3520, 16384]**** [5], [1],[5] -[4 ]---
  IN:MSMC, DMA,   4040( 16448),   4000( 16384),    c(   12),  30300( 197376),   0,        0 ||||  L2, DMA,   1bc0(  7104),   1bc0(  7104),    c(   12),  17680(  95872),   0,        0 
 OUT:MSMC, CPU,    dc0(  3520),    dc0(  3520),   48(   72),  7bc00( 506880),   0,    30780 |||| DDR, DMA,   5280( 21120),   4000( 16384),   48(   72), 173800(1521664),   0,    c0400 
  WT:DDR_PERSIST, DMA,      c(    12),      c(    12),   48(   72),    480(   1152),   0,      a80 ||||MSMC, DMA,      c(    12),      c(    12),   48(   72),    480(   1152),   0,    30300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  6(TIDL_ConvolutionLayer) [6, 6] --[72 x 128 x  128] => [72 x 64 x  64] *** [1] ***[ COL] ***[0, 0, 0, 16384, 16384]**** [12], [1],[12] -[5 ]---
  IN: DDR, DMA,   5280( 21120),   4000( 16384),   48(   72), 173800(1521664),   0,    c0400 ||||  L2, DMA,   4000( 16384),   4000( 16384),    c(   12),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   48(   72),  49200( 299520),   0,    31400 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  1b0(  432),   1100(   4352),   0,      f00 ||||MSMC, DMA,      a(    10),      a(    10),  1b0(  432),   1100(   4352),   0,    30300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  7(TIDL_ConvolutionLayer) [7, 7] --[72 x 64 x  64] => [18 x 64 x  64] *** [72] ***[ROW_L] ***[0, 0, 0, 1504, 4096]**** [3], [1],[3] -[6 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   48(   72),  49200( 299520),   0,    31400 ||||  L2, DMA,    bc0(  3008),    bc0(  3008),   48(   72),  35480( 218240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,        0 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),   12(   18),    580(   1408),   0,     2000 ||||MSMC, DMA,     c0(   192),     48(    72),   12(   18),    e00(   3584),   0,    12480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  8(TIDL_ConvolutionLayer) [8, 8] --[18 x 64 x  64] => [108 x 64 x  64] *** [18] ***[ROW_L] ***[0, 0, 0, 4096, 4096]**** [1], [1],[1] -[7 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,        0 ||||  L2, DMA,   1040(  4160),   1040(  4160),   12(   18),  12500(  75008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   6c(  108),  6db00( 449280),   0,    13e00 
  WT:DDR_PERSIST, DMA,     12(    18),     12(    18),   6c(  108),    980(   2432),   0,     2580 ||||MSMC, DMA,     12(    18),     12(    18),   6c(  108),    980(   2432),   0,    12480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  9(TIDL_ConvolutionLayer) [9, 9] --[108 x 64 x  64] => [108 x 64 x  64] *** [1] ***[ COL] ***[0, 0, 0, 4096, 4096]**** [27], [1],[27] -[8 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   6c(  108),  6db00( 449280),   0,    13e00 ||||  L2, DMA,   1000(  4096),   1000(  4096),    8(    8),   8080(  32896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   6c(  108),  6db00( 449280),   0,    13e00 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  288(  648),   1980(   6528),   0,     2f00 ||||MSMC, DMA,      a(    10),      a(    10),  288(  648),   1980(   6528),   0,    12480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  10(TIDL_ConvolutionLayer) [10, 10] --[108 x 64 x  64] => [18 x 64 x  64] *** [108] ***[ROW_C] ***[0, 0, 0, 1024, 4096]**** [4], [1],[4] -[9 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   6c(  108),  6db00( 449280),   0,    13e00 ||||  L2, DMA,    800(  2048),    800(  2048),   6c(  108),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,    13e00 
  WT:DDR_PERSIST, DMA,     6c(   108),     6c(   108),   12(   18),    800(   2048),   0,     4880 ||||MSMC, DMA,     c0(   192),     6c(   108),   12(   18),    e00(   3584),   0,    12480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  11(TIDL_EltWiseLayer) [11, 11] --[36 x 64 x  64] => [18 x 64 x  64] *** [36] ***[ COL] ***[0, 0, 0, 4096, 4096]**** [2], [0],[2] -[7 10 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,        0 ||||  L2, DMA,   1040(  4160),   1040(  4160),   12(   18),  24900( 149760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  12(TIDL_ConvolutionLayer) [12, 12] --[18 x 64 x  64] => [108 x 64 x  64] *** [18] ***[ROW_L] ***[0, 0, 0, 4096, 4096]**** [1], [1],[1] -[11 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,        0 ||||  L2, DMA,   1040(  4160),   1040(  4160),   12(   18),  12500(  75008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   6c(  108),  6db00( 449280),   0,    12480 
  WT:DDR_PERSIST, DMA,     12(    18),     12(    18),   6c(  108),    980(   2432),   0,     5080 ||||MSMC, DMA,     12(    18),     12(    18),   6c(  108),    980(   2432),   0,    7ff80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  13(TIDL_ConvolutionLayer) [13, 13] --[108 x 64 x  64] => [108 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 4096, 4096]**** [6], [1],[6] -[12 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   6c(  108),  6db00( 449280),   0,    12480 ||||  L2, DMA,   1000(  4096),   1000(  4096),   24(   36),  24080( 147584),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   6c(  108),  1cb00( 117504),   0,    12480 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  288(  648),   1980(   6528),   0,     5a00 ||||MSMC, DMA,      a(    10),      a(    10),  288(  648),   1980(   6528),   0,    7ff80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  14(TIDL_ConvolutionLayer) [14, 14] --[108 x 32 x  32] => [24 x 32 x  32] *** [108] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[13 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   6c(  108),  1cb00( 117504),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   6c(  108),  1cb80( 117632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 
  WT:DDR_PERSIST, DMA,     6c(   108),     6c(   108),   18(   24),    a80(   2688),   0,     7380 ||||MSMC, DMA,     c0(   192),     6c(   108),   18(   24),   1280(   4736),   0,    2ef80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  15(TIDL_ConvolutionLayer) [15, 15] --[24 x 32 x  32] => [144 x 32 x  32] *** [24] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[14 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   18(   24),   6680(  26240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    18a80 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),   90(  144),   1000(   4096),   0,     7e00 ||||MSMC, DMA,     18(    24),     18(    24),   90(  144),   1000(   4096),   0,    3ee80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  16(TIDL_ConvolutionLayer) [16, 16] --[144 x 32 x  32] => [144 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [36], [1],[36] -[15 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    18a80 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    18a80 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  360(  864),   2200(   8704),   0,     8e00 ||||MSMC, DMA,      a(    10),      a(    10),  360(  864),   2200(   8704),   0,    3ee80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  17(TIDL_ConvolutionLayer) [17, 17] --[144 x 32 x  32] => [24 x 32 x  32] *** [144] ***[ROW_L] ***[0, 0, 0, 736, 1024]**** [2], [1],[2] -[16 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    18a80 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),   90(  144),  33c80( 212096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    18a80 
  WT:DDR_PERSIST, DMA,     90(   144),     90(   144),   18(   24),    e00(   3584),   0,     b000 ||||MSMC, DMA,     c0(   192),     90(   144),   18(   24),   1280(   4736),   0,    3ee80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  18(TIDL_EltWiseLayer) [18, 18] --[48 x 32 x  32] => [24 x 32 x  32] *** [48] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[14 17 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   18(   24),   cc00(  52224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  19(TIDL_ConvolutionLayer) [19, 19] --[24 x 32 x  32] => [144 x 32 x  32] *** [24] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[18 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   18(   24),   6680(  26240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    1ac80 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),   90(  144),   1000(   4096),   0,     be00 ||||MSMC, DMA,     18(    24),     18(    24),   90(  144),   1000(   4096),   0,    18a80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  20(TIDL_ConvolutionLayer) [20, 20] --[144 x 32 x  32] => [144 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [36], [1],[36] -[19 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    1ac80 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    1ac80 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  360(  864),   2200(   8704),   0,     ce00 ||||MSMC, DMA,      a(    10),      a(    10),  360(  864),   2200(   8704),   0,    18a80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  21(TIDL_ConvolutionLayer) [21, 21] --[144 x 32 x  32] => [24 x 32 x  32] *** [144] ***[ROW_L] ***[0, 0, 0, 736, 1024]**** [2], [1],[2] -[20 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    1ac80 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),   90(  144),  33c80( 212096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    1a400 
  WT:DDR_PERSIST, DMA,     90(   144),     90(   144),   18(   24),    e00(   3584),   0,     f000 ||||MSMC, DMA,     c0(   192),     90(   144),   18(   24),   1280(   4736),   0,    18a80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  22(TIDL_EltWiseLayer) [22, 22] --[48 x 32 x  32] => [24 x 32 x  32] *** [48] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[18 21 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   18(   24),   cc00(  52224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  23(TIDL_ConvolutionLayer) [23, 23] --[24 x 32 x  32] => [144 x 32 x  32] *** [24] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[22 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   18(   24),   6600(  26112),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   18(   24),   6680(  26240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    12480 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),   90(  144),   1000(   4096),   0,     fe00 ||||MSMC, DMA,     18(    24),     18(    24),   90(  144),   1000(   4096),   0,    38880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  24(TIDL_ConvolutionLayer) [24, 24] --[144 x 32 x  32] => [144 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [36], [1],[36] -[23 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    12480 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    12480 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  360(  864),   2200(   8704),   0,    10e00 ||||MSMC, DMA,      a(    10),      a(    10),  360(  864),   2200(   8704),   0,    38880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  25(TIDL_ConvolutionLayer) [25, 25] --[144 x 32 x  32] => [48 x 32 x  32] *** [144] ***[ROW_L] ***[0, 0, 0, 736, 1024]**** [2], [1],[2] -[24 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   90(  144),  26400( 156672),   0,    12480 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),   90(  144),  33c80( 212096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 
  WT:DDR_PERSIST, DMA,     90(   144),     90(   144),   30(   48),   1c00(   7168),   0,    13000 ||||MSMC, DMA,     c0(   192),     90(   144),   30(   48),   2500(   9472),   0,    38880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  26(TIDL_ConvolutionLayer) [26, 26] --[48 x 32 x  32] => [288 x 32 x  32] *** [48] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[25 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),   cc80(  52352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    14c00 ||||MSMC, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  27(TIDL_ConvolutionLayer) [27, 27] --[288 x 32 x  32] => [288 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [72], [1],[72] -[26 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    18680 ||||MSMC, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  28(TIDL_ConvolutionLayer) [28, 28] --[288 x 32 x  32] => [48 x 32 x  32] *** [288] ***[ROW_L] ***[0, 0, 0, 352, 1024]**** [3], [1],[3] -[27 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 ||||  L2, DMA,    2c0(   704),    2c0(   704),  120(  288),  31a00( 203264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    1f080 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   30(   48),   3700(  14080),   0,    1ca00 ||||MSMC, DMA,    140(   320),    120(   288),   30(   48),   3d00(  15616),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  29(TIDL_EltWiseLayer) [29, 29] --[96 x 32 x  32] => [48 x 32 x  32] *** [96] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[25 28 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),  19800( 104448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  30(TIDL_ConvolutionLayer) [30, 30] --[48 x 32 x  32] => [288 x 32 x  32] *** [48] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[29 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),   cc80(  52352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    20100 ||||MSMC, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  31(TIDL_ConvolutionLayer) [31, 31] --[288 x 32 x  32] => [288 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [72], [1],[72] -[30 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    23b80 ||||MSMC, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  32(TIDL_ConvolutionLayer) [32, 32] --[288 x 32 x  32] => [48 x 32 x  32] *** [288] ***[ROW_L] ***[0, 0, 0, 352, 1024]**** [3], [1],[3] -[31 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 ||||  L2, DMA,    2c0(   704),    2c0(   704),  120(  288),  31a00( 203264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    1f080 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   30(   48),   3700(  14080),   0,    27f00 ||||MSMC, DMA,    140(   320),    120(   288),   30(   48),   3d00(  15616),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  33(TIDL_EltWiseLayer) [33, 33] --[96 x 32 x  32] => [48 x 32 x  32] *** [96] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[29 32 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),  19800( 104448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  34(TIDL_ConvolutionLayer) [34, 34] --[48 x 32 x  32] => [288 x 32 x  32] *** [48] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[33 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),   cc80(  52352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    2b600 ||||MSMC, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  35(TIDL_ConvolutionLayer) [35, 35] --[288 x 32 x  32] => [288 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [72], [1],[72] -[34 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    2f080 ||||MSMC, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  36(TIDL_ConvolutionLayer) [36, 36] --[288 x 32 x  32] => [48 x 32 x  32] *** [288] ***[ROW_L] ***[0, 0, 0, 352, 1024]**** [3], [1],[3] -[35 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    1f080 ||||  L2, DMA,    2c0(   704),    2c0(   704),  120(  288),  31a00( 203264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    1f080 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   30(   48),   3700(  14080),   0,    33400 ||||MSMC, DMA,    140(   320),    120(   288),   30(   48),   3d00(  15616),   0,    6b880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  37(TIDL_EltWiseLayer) [37, 37] --[96 x 32 x  32] => [48 x 32 x  32] *** [96] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[33 36 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),  19800( 104448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  38(TIDL_ConvolutionLayer) [38, 38] --[48 x 32 x  32] => [288 x 32 x  32] *** [48] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[37 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   30(   48),   cc00(  52224),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   30(   48),   cc80(  52352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    12480 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    36b00 ||||MSMC, DMA,     30(    48),     30(    48),  120(  288),   3a80(  14976),   0,    5ec80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  39(TIDL_ConvolutionLayer) [39, 39] --[288 x 32 x  32] => [288 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [72], [1],[72] -[38 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    12480 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    12480 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    3a580 ||||MSMC, DMA,      a(    10),      a(    10),  6c0( 1728),   4380(  17280),   0,    5ec80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  40(TIDL_ConvolutionLayer) [40, 40] --[288 x 32 x  32] => [72 x 32 x  32] *** [288] ***[ROW_L] ***[0, 0, 0, 352, 1024]**** [3], [1],[3] -[39 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  120(  288),  4c800( 313344),   0,    12480 ||||  L2, DMA,    2c0(   704),    2c0(   704),  120(  288),  31a00( 203264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    12480 
  WT:DDR_PERSIST, DMA_ONCE,    120(   288),    120(   288),   48(   72),   5280(  21120),   0,    3e900 ||||MSMC, DMA_ONCE,    140(   320),    120(   288),   48(   72),   5b80(  23424),   0,    ec080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  41(TIDL_ConvolutionLayer) [41, 41] --[72 x 32 x  32] => [432 x 32 x  32] *** [72] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[40 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   48(   72),  13280(  78464),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    3a180 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),  1b0(  432),   8080(  32896),   0,    43b80 ||||MSMC, DMA,     c0(   192),     48(    72),  1b0(  432),  14b00(  84736),   0,    25680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  42(TIDL_ConvolutionLayer) [42, 42] --[432 x 32 x  32] => [432 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [108], [1],[108] -[41 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    3a180 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    25680 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  a20( 2592),   6580(  25984),   0,    4bc00 ||||MSMC, DMA,      a(    10),      a(    10),  a20( 2592),   6580(  25984),   0,    acd80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  43(TIDL_ConvolutionLayer) [43, 43] --[432 x 32 x  32] => [72 x 32 x  32] *** [432] ***[ROW_C] ***[0, 0, 0, 256, 1024]**** [4], [1],[4] -[42 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    25680 ||||  L2, DMA,    200(   512),    200(   512),  1b0(  432),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    25680 
  WT:DDR_PERSIST, DMA,    1b0(   432),    1b0(   432),   48(   72),   7b00(  31488),   0,    52180 ||||MSMC, DMA,    1c0(   448),    1b0(   432),   48(   72),   7f80(  32640),   0,    98280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  44(TIDL_EltWiseLayer) [44, 44] --[144 x 32 x  32] => [72 x 32 x  32] *** [144] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[40 43 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   48(   72),  26400( 156672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  45(TIDL_ConvolutionLayer) [45, 45] --[72 x 32 x  32] => [432 x 32 x  32] *** [72] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[44 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   48(   72),  13280(  78464),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    3a180 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),  1b0(  432),   8080(  32896),   0,    59c80 ||||MSMC, DMA,     c0(   192),     48(    72),  1b0(  432),  14b00(  84736),   0,    25680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  46(TIDL_ConvolutionLayer) [46, 46] --[432 x 32 x  32] => [432 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [108], [1],[108] -[45 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    3a180 ||||  L2, DMA,    400(  1024),    400(  1024),    8(    8),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    25680 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  a20( 2592),   6580(  25984),   0,    61d00 ||||MSMC, DMA,      a(    10),      a(    10),  a20( 2592),   6580(  25984),   0,    acd80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  47(TIDL_ConvolutionLayer) [47, 47] --[432 x 32 x  32] => [72 x 32 x  32] *** [432] ***[ROW_C] ***[0, 0, 0, 256, 1024]**** [4], [1],[4] -[46 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    25680 ||||  L2, DMA,    200(   512),    200(   512),  1b0(  432),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    25680 
  WT:DDR_PERSIST, DMA,    1b0(   432),    1b0(   432),   48(   72),   7b00(  31488),   0,    68280 ||||MSMC, DMA,    1c0(   448),    1b0(   432),   48(   72),   7f80(  32640),   0,    98280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  48(TIDL_EltWiseLayer) [48, 48] --[144 x 32 x  32] => [72 x 32 x  32] *** [144] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [2], [0],[2] -[44 47 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   48(   72),  26400( 156672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    39080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  49(TIDL_ConvolutionLayer) [49, 49] --[72 x 32 x  32] => [432 x 32 x  32] *** [72] ***[ROW_L] ***[0, 0, 0, 1024, 1024]**** [1], [1],[1] -[48 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   48(   72),  13200(  78336),   0,    39080 ||||  L2, DMA,    440(  1088),    440(  1088),   48(   72),  13280(  78464),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    26f80 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),  1b0(  432),   8080(  32896),   0,    6fd80 ||||MSMC, DMA,     c0(   192),     48(    72),  1b0(  432),  14b00(  84736),   0,    12480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  50(TIDL_ConvolutionLayer) [50, 50] --[432 x 32 x  32] => [432 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [144], [1],[144] -[49 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    26f80 ||||  L2, DMA,    400(  1024),    400(  1024),    6(    6),   1880(   6272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    12480 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10),  a20( 2592),   6580(  25984),   0,    77e00 ||||MSMC, DMA,      a(    10),      a(    10),  a20( 2592),   6580(  25984),   0,    99b80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  51(TIDL_ConvolutionLayer) [51, 51] --[432 x 32 x  32] => [120 x 32 x  32] *** [432] ***[ROW_C] ***[0, 0, 0, 256, 1024]**** [4], [1],[4] -[50 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  1b0(  432),  72c00( 470016),   0,    12480 ||||  L2, DMA,    200(   512),    200(   512),  1b0(  432),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 
  WT:DDR_PERSIST, DMA_ONCE,    1b0(   432),    1b0(   432),   78(  120),   cc80(  52352),   0,    7e380 ||||MSMC, DMA_ONCE,    1c0(   448),    1b0(   432),   78(  120),   d400(  54272),   0,    dec80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  52(TIDL_ConvolutionLayer) [52, 52] --[120 x 32 x  32] => [720 x 32 x  32] *** [120] ***[ROW_L] ***[0, 0, 0, 320, 1024]**** [4], [1],[4] -[51 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 ||||  L2, DMA,    2c0(   704),    2c0(   704),   78(  120),  14d00(  85248),   0,        0 
 OUT:MSMC, CPU,    140(   320),    140(   320),  2d0(  720),  70800( 460800),   0,    54a00 |||| DDR, DMA,    640(  1600),    400(  1024),  2d0(  720), 119800(1153024),   0,    c0400 
  WT:DDR_PERSIST, DMA,     78(   120),     78(   120),  2d0(  720),  15d00(  89344),   0,    8b000 ||||MSMC, DMA,     c0(   192),     78(   120),  2d0(  720),  22780( 141184),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  53(TIDL_ConvolutionLayer) [53, 53] --[720 x 32 x  32] => [720 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [240], [1],[240] -[52 ]---
  IN: DDR, DMA,    640(  1600),    400(  1024),  2d0(  720), 119800(1153024),   0,    c0400 ||||  L2, DMA,    400(  1024),    400(  1024),    6(    6),   1880(   6272),   0,        0 
 OUT:MSMC, CPU,    440(  1088),    400(  1024),    6(    6),   1980(   6528),   0,    3cb80 |||| DDR, DMA,    400(  1024),    400(  1024),  2d0(  720),  b4400( 738304),   0,   1d9c00 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10), 10e0( 4320),   a900(  43264),   0,    a0d00 ||||MSMC, DMA,      a(    10),      a(    10), 10e0( 4320),   a900(  43264),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  54(TIDL_ConvolutionLayer) [54, 54] --[720 x 32 x  32] => [120 x 32 x  32] *** [720] ***[ROW_L] ***[0, 0, 0, 96, 1024]**** [11], [1],[11] -[53 ]---
  IN: DDR, DMA,    400(  1024),    400(  1024),  2d0(  720),  b4400( 738304),   0,   1d9c00 ||||  L2, DMA,     c0(   192),     c0(   192),  2d0(  720),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    4aa80 
  WT:DDR_PERSIST, DMA,    2d0(   720),    2d0(   720),   78(  120),  15380(  86912),   0,    ab600 ||||MSMC, DMA,    340(   832),    2d0(   720),   78(  120),  18800( 100352),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  55(TIDL_EltWiseLayer) [55, 55] --[240 x 32 x  32] => [120 x 32 x  32] *** [240] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [4], [0],[4] -[51 54 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   3c(   60),  1fe00( 130560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  56(TIDL_ConvolutionLayer) [56, 56] --[120 x 32 x  32] => [720 x 32 x  32] *** [120] ***[ROW_L] ***[0, 0, 0, 320, 1024]**** [4], [1],[4] -[55 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 ||||  L2, DMA,    2c0(   704),    2c0(   704),   78(  120),  14d00(  85248),   0,        0 
 OUT:MSMC, CPU,    140(   320),    140(   320),  2d0(  720),  70800( 460800),   0,    54a00 |||| DDR, DMA,    640(  1600),    400(  1024),  2d0(  720), 119800(1153024),   0,    c0400 
  WT:DDR_PERSIST, DMA,     78(   120),     78(   120),  2d0(  720),  15d00(  89344),   0,    c0980 ||||MSMC, DMA,     c0(   192),     78(   120),  2d0(  720),  22780( 141184),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  57(TIDL_ConvolutionLayer) [57, 57] --[720 x 32 x  32] => [720 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [240], [1],[240] -[56 ]---
  IN: DDR, DMA,    640(  1600),    400(  1024),  2d0(  720), 119800(1153024),   0,    c0400 ||||  L2, DMA,    400(  1024),    400(  1024),    6(    6),   1880(   6272),   0,        0 
 OUT:MSMC, CPU,    440(  1088),    400(  1024),    6(    6),   1980(   6528),   0,    3cb80 |||| DDR, DMA,    400(  1024),    400(  1024),  2d0(  720),  b4400( 738304),   0,   1d9c00 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10), 10e0( 4320),   a900(  43264),   0,    d6680 ||||MSMC, DMA,      a(    10),      a(    10), 10e0( 4320),   a900(  43264),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  58(TIDL_ConvolutionLayer) [58, 58] --[720 x 32 x  32] => [120 x 32 x  32] *** [720] ***[ROW_L] ***[0, 0, 0, 96, 1024]**** [11], [1],[11] -[57 ]---
  IN: DDR, DMA,    400(  1024),    400(  1024),  2d0(  720),  b4400( 738304),   0,   1d9c00 ||||  L2, DMA,     c0(   192),     c0(   192),  2d0(  720),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    4aa80 
  WT:DDR_PERSIST, DMA,    2d0(   720),    2d0(   720),   78(  120),  15380(  86912),   0,    e0f80 ||||MSMC, DMA,    340(   832),    2d0(   720),   78(  120),  18800( 100352),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  59(TIDL_EltWiseLayer) [59, 59] --[240 x 32 x  32] => [120 x 32 x  32] *** [240] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [4], [0],[4] -[55 58 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 ||||  L2, DMA,    440(  1088),    440(  1088),   3c(   60),  1fe00( 130560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  60(TIDL_ConvolutionLayer) [60, 60] --[120 x 32 x  32] => [720 x 32 x  32] *** [120] ***[ROW_L] ***[0, 0, 0, 320, 1024]**** [4], [1],[4] -[59 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   78(  120),  1fe00( 130560),   0,    12480 ||||  L2, DMA,    2c0(   704),    2c0(   704),   78(  120),  14d00(  85248),   0,        0 
 OUT:MSMC, CPU,    140(   320),    140(   320),  2d0(  720),  70800( 460800),   0,    54a00 |||| DDR, DMA,    640(  1600),    400(  1024),  2d0(  720), 119800(1153024),   0,    c0400 
  WT:DDR_PERSIST, DMA,     78(   120),     78(   120),  2d0(  720),  15d00(  89344),   0,    f6300 ||||MSMC, DMA,     c0(   192),     78(   120),  2d0(  720),  22780( 141184),   0,    32280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  61(TIDL_ConvolutionLayer) [61, 61] --[720 x 32 x  32] => [720 x 32 x  32] *** [1] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [480], [1],[480] -[60 ]---
  IN: DDR, DMA,    640(  1600),    400(  1024),  2d0(  720), 119800(1153024),   0,    c0400 ||||  L2, DMA,    400(  1024),    400(  1024),    3(    3),    c80(   3200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  2d0(  720),  bf400( 783360),   0,    12480 
  WT:DDR_PERSIST, DMA,      a(    10),      a(    10), 10e0( 4320),   a900(  43264),   0,   10c000 ||||MSMC, DMA,      a(    10),      a(    10), 10e0( 4320),   a900(  43264),   0,    d1880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  62(TIDL_ConvolutionLayer) [62, 62] --[720 x 32 x  32] => [240 x 32 x  32] *** [720] ***[ROW_L] ***[0, 0, 0, 96, 1024]**** [11], [88],[88] -[61 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  2d0(  720),  bf400( 783360),   0,    12480 ||||  L2, DMA,     c0(   192),     c0(   192),  2d0(  720),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),   f0(  240),  3fc00( 261120),   0,    12480 
  WT:DDR_PERSIST, DMA,    2d0(   720),    2d0(   720),   f0(  240),  2a700( 173824),   0,   116900 ||||MSMC, DMA,    340(   832),    2d0(   720),   40(   64),   d400(  54272),   0,    d1880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  63(TIDL_ConvolutionLayer) [63, 63] --[240 x 32 x  32] => [256 x 32 x  32] *** [240] ***[ROW_L] ***[0, 0, 0, 416, 1024]**** [3], [1],[3] -[62 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   f0(  240),  3fc00( 261120),   0,    12480 ||||  L2, DMA,    340(   832),    340(   832),   f0(  240),  30e80( 200320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    400(  1024),  100(  256),  44000( 278528),   0,    52080 
  WT:DDR_PERSIST, DMA,     f0(   240),     f0(   240),  100(  256),   f400(  62464),   0,   141000 ||||MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14400(  82944),   0,    96080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  64(TIDL_ConvolutionLayer) [64, 64] --[240 x 32 x  32] => [256 x 32 x  32] *** [240] ***[ROW_L] ***[396, 416, 198, 192, 1024]**** [5], [40],[40] -[62 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   f0(  240),  3fc00( 261120),   0,    12480 ||||  L2, DMA,    340(   832),    340(   832),   f0(  240),  30e00( 200192),   0,        0 
 OUT:MSMC, CPU,    140(   320),     c0(   192),   80(  128),   a000(  40960),   0,    b9480 |||| DDR, DMA,    640(  1600),    400(  1024),  100(  256),  64400( 410624),   0,    c0400 
  WT:DDR_PERSIST, DMA,    870(  2160),    870(  2160),  100(  256),  87400( 553984),   0,   150400 ||||MSMC, DMA,    8c0(  2240),    870(  2160),   40(   64),  23400( 144384),   0,    96080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  65(TIDL_ConvolutionLayer) [65, 65] --[240 x 32 x  32] => [256 x 32 x  32] *** [240] ***[ROW_L] ***[792, 800, 396, 32, 1024]**** [20], [160],[160] -[62 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   f0(  240),  3fc00( 261120),   0,    12480 ||||  L2, DMA,    380(   896),    380(   896),   f0(  240),  34980( 215424),   0,        0 
 OUT:MSMC, CPU,    1c0(   448),     20(    32),   80(  128),   e000(  57344),   0,    b9480 |||| DDR, DMA,    700(  1792),    400(  1024),  100(  256),  70400( 459776),   0,   124800 
  WT:DDR_PERSIST, DMA,    870(  2160),    870(  2160),  100(  256),  87400( 553984),   0,   1d7800 ||||MSMC, DMA,    8c0(  2240),    870(  2160),   40(   64),  23400( 144384),   0,    96080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  66(TIDL_ConvolutionLayer) [66, 66] --[240 x 32 x  32] => [256 x 32 x  32] *** [240] ***[ROW_L] ***[0, 0, 594, 1024, 1024]**** [1], [0],[8] -[62 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),   f0(  240),  3fc00( 261120),   0,    12480 ||||MSMC, DMA,    440(  1088),    400(  1024),   f0(  240),  3fc00( 261120),   0,    12480 
 OUT:  L2, CPU,    400(  1024),    400(  1024),   40(   64),  20000( 131072),   0,        0 |||| DDR, DMA,    800(  2048),    400(  1024),  100(  256),  80400( 525312),   0,   194c00 
  WT:DDR_PERSIST, DMA,    870(  2160),    870(  2160),  100(  256),  87400( 553984),   0,   25ec00 ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  67(TIDL_ConcatLayer) [67, 67] --[1024 x 32 x  32] => [1024 x 32 x  32] *** [1024] ***[ COL] ***[0, 0, 0, 1024, 1024]**** [16], [0],[16] -[63 64 65 66 ]---
  IN:MSMC, DMA,    440(  1088),    400(  1024),  100(  256),  44000( 278528),   0,    52080 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:MSMC, CPU,    440(  1088),    400(  1024),   80(  128),  22000( 139264),   0,    12480 |||| DDR, DMA,    440(  1088),    440(  1088),  400( 1024), 110400(1115136),  20,   215060 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  68(TIDL_ConvolutionLayer) [68, 68] --[1024 x 32 x  32] => [256 x 32 x  32] *** [1024] ***[ROW_L] ***[0, 0, 0, 96, 1024]**** [11], [1],[11] -[67 ]---
  IN: DDR, DMA,    440(  1088),    440(  1088),  400( 1024), 110400(1115136),  20,   215060 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30400( 197632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    440(  1088),  100(  256),  44000( 278528),  20,    124e0 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  100(  256),  40400( 263168),   0,   2e6000 ||||MSMC, DMA,    440(  1088),    400(  1024),  100(  256),  44400( 279552),   0,    96080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 1,  0],  To fill zero OUT: [ 1,  0]
------  69(TIDL_ResizeLayer) [69, 69] --[256 x 32 x  32] => [256 x 64 x  64] *** [256] ***[ COL] ***[0, 0, 0, 1088, 1088]**** [8], [0],[8] -[68 ]---
  IN:MSMC, DMA,    440(  1088),    440(  1088),  100(  256),  44000( 278528),   0,    124e0 ||||  L2, DMA,    440(  1088),    440(  1088),   40(   64),  11000(  69632),   0,        0 
 OUT:MSMC, CPU,   11c0(  4544),   1180(  4480),   40(   64),  47000( 290816),   0,    56500 |||| DDR, DMA,   1080(  4224),   1080(  4224),  100(  256), 108400(1082368),  40,   1fa0c0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  70(TIDL_ConvolutionLayer) [70, 70] --[18 x 64 x  64] => [48 x 64 x  64] *** [18] ***[ROW_L] ***[0, 0, 0, 4096, 4096]**** [1], [1],[1] -[11 ]---
  IN:MSMC, DMA,   1040(  4160),   1000(  4096),   12(   18),  12480(  74880),   0,        0 ||||  L2, DMA,   1040(  4160),   1040(  4160),   12(   18),  12500(  75008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),   1000(  4096),   30(   48),  30c00( 199680),   0,        0 
  WT:DDR_PERSIST, DMA,     12(    18),     12(    18),   30(   48),    480(   1152),   0,   326400 ||||MSMC, DMA,     12(    18),     12(    18),   30(   48),    480(   1152),   0,    564e0 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  71(TIDL_ConcatLayer) [71, 71] --[304 x 64 x  64] => [304 x 64 x  64] *** [304] ***[ COL] ***[0, 0, 0, 4096, 4096]**** [19], [0],[19] -[69 70 ]---
  IN: DDR, DMA,   1080(  4224),   1080(  4224),  100(  256), 108480(1082496),  40,   1fa0c0 ||||  L2, DMA,   10c0(  4288),   10c0(  4288),   20(   32),  21800( 137216),   0,        0 
 OUT:MSMC, CPU,   1040(  4160),   1000(  4096),   20(   32),  20800( 133120),   0,    30c00 |||| DDR, DMA,   1080(  4224),   1080(  4224),  130(  304), 139c00(1285120),  40,    c0440 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  72(TIDL_ConvolutionLayer) [72, 72] --[304 x 64 x  64] => [256 x 64 x  64] *** [304] ***[ROW_L] ***[130, 160, 65, 256, 4096]**** [16], [1],[16] -[71 ]---
  IN: DDR, DMA,   1080(  4224),   1080(  4224),  130(  304), 139c00(1285120),  40,    c0440 ||||  L2, DMA,    2c0(   704),    2c0(   704),  130(  304),  35280( 217728),   0,        0 
 OUT:MSMC, CPU,    140(   320),    100(   256),  100(  256),  28000( 163840),   0,        0 |||| DDR, DMA,   12c0(  4800),   1080(  4224),  100(  256), 12c400(1229824),  40,   1fa040 
  WT:DDR_PERSIST, DMA,    ab0(  2736),    ab0(  2736),  100(  256),  ab400( 701440),   0,   326880 ||||MSMC, DMA,    ac0(  2752),    ab0(  2736),  100(  256),  ac400( 705536),   0,    30c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  73(TIDL_ConvolutionLayer) [73, 73] --[256 x 64 x  64] => [256 x 64 x  64] *** [256] ***[ROW_L] ***[130, 160, 65, 320, 4096]**** [13], [1],[13] -[72 ]---
  IN: DDR, DMA,   12c0(  4800),   1080(  4224),  100(  256), 12c400(1229824),  40,   1fa040 ||||  L2, DMA,    340(   832),    340(   832),  100(  256),  34e80( 216704),   0,        0 
 OUT:MSMC, CPU,    140(   320),    140(   320),  100(  256),  28000( 163840),   0,    94400 |||| DDR, DMA,   12c0(  4800),   1080(  4224),  100(  256), 12c400(1229824),  40,    c0440 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  100(  256),  90400( 590848),   0,   3d1c80 ||||MSMC, DMA,    940(  2368),    900(  2304),  100(  256),  94400( 607232),   0,        0 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  74(TIDL_ConvolutionLayer) [74, 74] --[256 x 64 x  64] => [2 x 64 x  64] *** [256] ***[ROW_L] ***[0, 0, 0, 416, 4096]**** [10], [1],[10] -[73 ]---
  IN: DDR, DMA,   12c0(  4800),   1080(  4224),  100(  256), 12c400(1229824),  40,    c0440 ||||  L2, DMA,    340(   832),    340(   832),  100(  256),  34d80( 216448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   10c0(  4288),   1080(  4224),    2(    2),   2180(   8576),  40,    20940 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),    2(    2),    280(    640),   0,   462080 ||||MSMC, DMA,    140(   320),    100(   256),    2(    2),    300(    768),   0,        0 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 1,  0],  To fill zero OUT: [ 1,  0]
------  75(TIDL_ResizeLayer) [75, 75] --[2 x 64 x  64] => [2 x 256 x  256] *** [2] ***[ COL] ***[0, 0, 0, 4224, 4224]**** [1], [0],[1] -[74 ]---
  IN:MSMC, DMA,   10c0(  4288),   1080(  4224),    2(    2),   2180(   8576),   0,    20940 ||||  L2, DMA,   10c0(  4288),   10c0(  4288),    2(    2),   2180(   8576),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  10440( 66624),  10400( 66560),    2(    2),  20880( 133248), 200,       80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 2,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  76(TIDL_DataConvertLayer) [76, 76] --[2 x 256 x  256] => [2 x 256 x  256] *** [2] ***[ COL] ***[0, 0, 0, 32768, 65536]**** [4], [0],[4] -[75 ]---
  IN:MSMC, DMA,  10440( 66624),  10400( 66560),    2(    2),  20900( 133376), 200,       80 ||||  L2, DMA,  10000( 65536),  10000( 65536),    1(    1),  10000(  65536),   0,        0 
 OUT:MSMC, CPU,  20000(131072),  20000(131072),    2(    2),  40000( 262144),   0,    20900 |||| DDR, DMA,  40000(262144),  40000(262144),    2(    2),  80400( 525312),   0,    c0400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
