# Enable counter (ICSSG_GLOBAL_CFG[0] CNT_ENABLE = 1h)
devmem2 0x0B02E000 w 0x0
# Reset Count Register (ICSSG_COUNT_REG0, ICSSG_COUNT_REG1) by writing FFFFFFFFh to clear
devmem2 0x0B02E010 w 0xFFFFFFFF
# Clear overflow status register (ICSSG_GLOBAL_STATUS_REG[0] CNT_OVF = 1h)
devmem2 0x0B02E004 w 0x1
# Clear compare status (ICSSG_CMP_STATUS_REG[15-0] CMP_STATUS) by writing FFFFFFFFh to clear
devmem2 0x0B02E074 w 0xFFFFFFFF

# Set compare values ICSSG_CMP7_REG0
devmem2 0x0B02E0B0 w 0xffff

# Enable compare events (ICSSG_CMP_CFG_REG[8] CMP_EN = 1h)
devmem2 0x0B02E070 w 0x101
# Set increment value (ICSSG_GLOBAL_CFG_REG[7-4] DEFAULT_INC)
devmem2 0x0B02E000 w 0x110
# Set compensation value (ICSSG_COMPEN_REG[22-0] COMPEN_CNT)
devmem2 0x0B02E008 w 0xf

# Clearing TRIP_RESET and PWM0_TRIP_CMP0_EN
devmem2 0x0B026134 w 0x00060000

# Active state -> toogle, Trip state -> high, Initial state -> high
devmem2 0x0B02614C w 0x00000022

# Enable counter (ICSSG_GLOBAL_CFG[0] CNT_ENABLE = 1h)
devmem2 0x0B02E000 w 0x1