diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 0bc4805ec..71c655245 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -2,7 +2,7 @@
 /*
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  */
-
+/* THIS ONE*/
 /dts-v1/;
 
 #include "k3-j721e-som-p0.dtsi"
@@ -106,7 +106,7 @@
 
 		port {
 			dp_connector_in: endpoint {
-				remote-endpoint = <&dp_bridge_output>;
+			remote-endpoint = <&dp_bridge_output>;
 			};
 		};
 	};
@@ -258,13 +258,15 @@
 };
 
 &main_uart3 {
-	/* UART not brought out */
-	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_default>;
+	status = "okay";
 };
 
 &main_uart5 {
-	/* UART not brought out */
-	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5_pins_default>;
+	status = "okay";
 };
 
 &main_uart6 {
@@ -278,13 +280,15 @@
 };
 
 &main_uart8 {
-	/* UART not brought out */
-	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart8_pins_default>;
+	status = "okay";
 };
 
 &main_uart9 {
-	/* UART not brought out */
-	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart9_pins_default>;
+	status = "okay";
 };
 
 &main_gpio2 {
@@ -336,6 +340,13 @@
 		>;
 	};
 
+	main_i2c2_pins_default: main-i2c2-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x1C8, PIN_INPUT_PULLUP, 2) /* (AA1) I2C2_SCL */
+			J721E_IOPAD(0x1CC, PIN_INPUT_PULLUP, 2) /* (AB5) I2C2_SDA */
+		>;
+	};
+	
 	main_i2c3_pins_default: main-i2c3-pins-default {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
@@ -372,7 +383,9 @@
 
 	main_usbss0_pins_default: main_usbss0_pins_default {
 		pinctrl-single,pins = <
-			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+			/* J721E_IOPAD(0x290, PIN_OUTPUT, 0) *//* (U6) USB0_DRVVBUS */
+			J721E_IOPAD(0x290, PIN_INPUT_PULLUP, 7) /* (U6) GPIO1_29 USB0.USB0_DRVVBUS */
+
 			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
 		>;
 	};
@@ -414,6 +427,36 @@
 			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
 		>;
 	};
+	
+	uart3_pins_default: uart3_pins_default {
+			pinctrl-single,pins = <
+			J721E_IOPAD(0x070, PIN_OUTPUT, 14) /* (AC21) UART3_TX */
+			J721E_IOPAD(0x074, PIN_INPUT, 14) /* (Y23) UART3_RX */
+		>;
+	};
+	uart5_pins_default: uart5_pins_default {
+			pinctrl-single,pins = <
+			J721E_IOPAD(0x100, PIN_INPUT, 14) /* (AE29) UART5_RX */
+			J721E_IOPAD(0x104, PIN_OUTPUT, 14) /* (AD28) UART5_TX */
+		>;
+	};
+	uart8_pins_default: uart8_pins_default {
+			pinctrl-single,pins = <
+			J721E_IOPAD(0x128, PIN_OUTPUT, 14) /* (AA25) UART8_TX */
+			J721E_IOPAD(0x124, PIN_INPUT, 14) /* (Y24) UART8_RX */
+		>;
+	};
+	uart9_pins_default: uart9_pins_default {
+			pinctrl-single,pins = <
+			J721E_IOPAD(0x264, PIN_OUTPUT, 1) /* (T29) UART9_TX */
+			J721E_IOPAD(0x260, PIN_INPUT, 1) /* (T28) UART9_RX */
+		>;
+	};
+	pcie2_pins_default: pcie2_pins_default {
+			pinctrl-single,pins = <
+			J721E_IOPAD(0x118, PIN_INPUT_PULLUP, 7) /* (AC26) GPIO0_69 SSD_LDSW_EN */
+		>;
+	};
 };
 
 &dss {
@@ -465,18 +508,50 @@
 	};
 };
 
+&wkup_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	eeprom_som_id@50 {
+		compatible = "atmel,24512","st,24c512";
+		reg = <0x50>;
+		pagesize = <128>;
+	};
+
+	eeprom_bb_id@51 {
+		compatible = "atmel,24512","st,24c512";
+		reg = <0x51>;
+		pagesize = <128>;
+	};
+
+	eeprom_csi_id@52 {
+		compatible = "atmel,24512","st,24c512";
+		reg = <0x52>;
+		pagesize = <128>;
+	};
+
+	eeprom_exp_id@53 {
+		compatible = "atmel,24512","st,24c512";
+		reg = <0x53>;
+		pagesize = <128>;
+	};
+};
+
 &main_i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_i2c0_pins_default>;
 	clock-frequency = <400000>;
 
+	/* This device needs to be removed (currently required to complete boot)*/
 	exp1: gpio@20 {
 		compatible = "ti,tca6416";
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
-
+	
+	/* This device needs to be removed (currently required to complete boot)*/
 	exp2: gpio@22 {
 		compatible = "ti,tca6424";
 		reg = <0x22>;
@@ -499,54 +574,110 @@
 			line-name = "MCASP/TRACE_MUX_S1";
 		};
 	};
+
+	exp8: gpio@74 {
+		compatible = "nxp,pca9539";
+		reg = <0x74>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"can1_faultN", "can2_stbN", "can2_en", "can2_faultN", "load_sw_en", "load_sw_diag_en", "mcan4_stbN", "test_point",
+			"buff_in0", "buff_in1", "buff_out0", "buff_out1", "iso_in0", "iso_in1", "iso_out0", "iso_out1";
+	};
+	
+	/*May not be initializaed properly*/
+	adc_bb: adc@4a {
+		compatible = "ti,ads1115";
+		reg = <0x4a>;
+	};
+
+	/*TODO: CDCI6214 PCIe Clock Driver?*/
+	/*TODO PCA2129 Real Time Clock*/
 };
 
 &main_i2c1 {
+	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_i2c1_pins_default>;
 	clock-frequency = <400000>;
 
-	exp4: gpio@20 {
-		compatible = "ti,tca6408";
-		reg = <0x20>;
+	/*TODO: Chane exp number to something smaller when unused devices are removed*/
+	exp9: gpio@75 {
+		compatible = "nxp,pca9539";
+		reg = <0x75>;
+		
 		gpio-controller;
 		#gpio-cells = <2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
-		interrupt-parent = <&main_gpio1>;
-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		p0 {
-			/* P0 - DP0_PWR_SW_EN */
+		gpio-line-names = 
+			"exp_bd_present", "serdes_board_present", "usbc_mode_sel0", "usbc_mode_sel1", "exp_io_rstN", "ssd_rstN", "test_point", "test_point",
+			"cdci1_oe2-3", "cdci1_oe1-4", "cdci2_rstz", "test_point", "test_point", "adc_mux_s0", "adc_mux_s1", "adc_mux_s2";
+
+	};
+	
+	/*TODO: Chane exp number to something smaller when unused devices are removed*/
+	exp10: gpio@76 {
+		compatible = "nxp,pca9539";
+		reg = <0x76>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		p04 {
+			/* P04 - 941 PDB */ 
+			gpio-hog;
+			gpios = <4 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "941 PDB";
+		};
+
+		p06 {
+			/* P06 - DSI_MUX_SEL */
 			gpio-hog;
-			gpios = <0 GPIO_ACTIVE_HIGH>;
+			gpios = <6 GPIO_ACTIVE_HIGH>;
 			output-high;
-			line-name = "DP0_PWR_SW_EN";
+			line-name = "DSI_MUX_SELe";
 		};
 	};
+	
+	/*TODO: Chane exp number to something smaller when unused devices are removed*/
+	exp11: gpio@77 {
+		compatible = "nxp,pca9539";
+		reg = <0x77>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+	
+	/*TODO:THIS DRIVER DOESN' EXIST Port from TDA2x*/
+	serializer@16 {
+		compatible = "ti,ds90ub941q";
+		reg = <0x16>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		// Allow the slave address to be automatically populated 
+		// remote real address, local alias address 
+		ranges = <0x00 0x2e>;
+		vin-supply = <&vsys_5v0>;
+		// PDB 
+		gpios = <&exp10 4 GPIO_ACTIVE_HIGH>;
+	};
+	
+	
 };
 
-&main_i2c3 {
+&main_i2c2 {
+	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c3_pins_default>;
+	pinctrl-0 = <&main_i2c2_pins_default>;
 	clock-frequency = <400000>;
 
-	exp3: gpio@20 {
-		compatible = "ti,tca6408";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
+};
 
-		p0 {
-			/* P0 - CODEC_RSTz */
-			gpio-hog;
-			gpios = <0 GPIO_ACTIVE_HIGH>;
-			output-high;
-			line-name = "CODEC_RSTz";
-		};
-	};
+
+&main_i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c3_pins_default>;
+	clock-frequency = <400000>;
 
 	pcm3168a_1: audio-codec@44 {
 		compatible = "ti,pcm3168a";
@@ -700,7 +831,7 @@
 };
 
 &usb0 {
-	dr_mode = "otg";
+	dr_mode = "host";
 	maximum-speed = "super-speed";
 	phys = <&serdes3_usb_link>;
 	phy-names = "cdns3,usb3-phy";
@@ -726,8 +857,8 @@
 
 &main_sdhci1 {
 	/* SD/MMC */
-	vmmc-supply = <&vdd_mmc1>;
-	vqmmc-supply = <&vdd_sd_dv_alt>;
+	/*vmmc-supply = <&vdd_mmc1>;*/
+	/*vqmmc-supply = <&vdd_sd_dv_alt>;*/
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_mmc1_pins_default>;
 	disable-wp;
@@ -771,15 +902,19 @@
 &serdes_wiz2 {
 	lane0-mode = <PHY_TYPE_PCIE>;
 	lane1-mode = <PHY_TYPE_PCIE>;
+	// num-lanes = <2>;
+	num-lanes = <1>;
 };
 
 &serdes2 {
 	serdes2_pcie_link: link@0 {
 		reg = <0>;
-		cdns,num-lanes = <2>;
+		// cdns,num-lanes = <2>;
+		cdns,num-lanes = <1>;
 		#phy-cells = <0>;
 		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
+		// resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
+		resets = <&serdes_wiz2 1>;
 	};
 };
 
@@ -795,7 +930,11 @@
 
 &pcie2 {
 	pci-mode = <PCI_MODE_RC>;
-	num-lanes = <2>;
+	// num-lanes = <2>;
+	num-lanes = <1>;
+	// max-link-speed = <3>; (default from k3-j721e.dtsi)
+	max-link-speed = <1>;
+
 };
 
 &pcie0_rc {
@@ -811,7 +950,10 @@
 };
 
 &pcie2_rc {
-	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_pins_default>;
+	reset-gpios = <&exp9 5 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes2_pcie_link>;
 	phy-names = "pcie_phy";
 };
