diff -ru qnx_baseline/examples/gpio/common.mk qnx/examples/gpio/common.mk
--- qnx_baseline/examples/gpio/common.mk	2024-02-05 08:26:07.653658397 -0800
+++ qnx/examples/gpio/common.mk	2024-02-05 08:40:23.000000000 -0800
@@ -45,12 +45,21 @@
 PINFO TAGID=$(PSDK_QNX_TAGID)
 endef
 
+include $(PSDK_QNX_PATH)/qnx/psdk_qnx_build.mk
+
+#Add extra include path
+EXTRA_INCVPATH += $(PDK_INSTALL_PATH)
 
 #Add source path
 EXTRA_SRCVPATH+=$(PROJECT_ROOT)/src
 
 LIBS = c
 
+EXTRA_LIBVPATH += $(PSDK_QNX_PATH)/qnx/pdk_libs/pdk/aarch64/so.le/
+EXTRA_LIBVPATH += $(PSDK_QNX_PATH)/qnx/pdk_libs/sciclient/aarch64/so.le/
+
+LIBS += ti-pdk
+LIBS += ti-sciclient
 
 include $(MKFILES_ROOT)/qtargets.mk
 
diff -ru qnx_baseline/examples/gpio/src/gpio.c qnx/examples/gpio/src/gpio.c
--- qnx_baseline/examples/gpio/src/gpio.c	2024-02-05 10:26:50.114290746 -0800
+++ qnx/examples/gpio/src/gpio.c	2024-02-05 13:14:25.000000000 -0800
@@ -45,6 +45,19 @@
 #include <sys/mman.h>
 #include <string.h>
 
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc/j721e/src/cslr_soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/hw_types.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/arch/csl_arch.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+#include <ti/drv/sciclient/sciclient.h>
+#include <ti/csl/csl_clec.h>
+#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_devices.h>
+#include <ti/drv/sciclient/include/sciclient_rm.h>
+
+
 #define GPIOPID               0x000
 #define GPIO_PCR              0x004
 #define GPIO_BINTEN           0x008
@@ -114,6 +127,10 @@
 #define GPIO6_BASE 0x00630000
 #define GPIO7_BASE 0x00631000 // TRM says 0x68000000, but reading version reg seems like 0x00631000 is right
 
+#define WKUP_GPIO1_BASE (0x42100000UL)
+#define WKUP_GPIO0_BASE (0x42110000UL)
+
+
 /* GPIO MUX output port to GIC IRQ value
  * as defined in TRM */
 #define GPIOMUX_INTRTR0_OUTP_8 392
@@ -203,16 +220,23 @@
 	// 2 Banks of 16 pins per GPIO instance
 	gpio_bank = gpio_num / 16;
 
+
 	// GPIO 0,2,4,6 have 8 banks per instance.
 	if ((gpio_module == 0) || (gpio_module == 2) || (gpio_module == 4)
 			|| (gpio_module == 6))
 	{
 		mux_val = 256 + (gpio_module / 2 * 8) + gpio_num / 16;
 	}
-	else // GPIO 1,3,5,7 only have 3 banks
+	else if ((gpio_module == 1) || (gpio_module == 3) || (gpio_module == 5)
+			|| (gpio_module == 7)) // GPIO 1,3,5,7 only have 3 banks
 	{
 		mux_val = 288 + (gpio_module / 2 * 3) + gpio_num / 16;
 	}
+	else // WKUP GPIO has 6 banks per instances
+	{
+		mux_val = 159 + ((gpio_module - 8 )/ 2 * 6) + gpio_num / 16;
+	}
+
 	printf("GPIO%d_%d, module/%d inst/%d bank/%d mux_val/%d\n", gpio_module,
 			gpio_num, gpio_module, gpio_num, gpio_bank, mux_val);
 
@@ -243,6 +267,12 @@
 	case 7:
 		base_address = GPIO7_BASE;
 		break;
+	case 8:
+		base_address = WKUP_GPIO0_BASE;
+		break;
+	case 9:
+		base_address = WKUP_GPIO1_BASE;
+		break;
 	default:
 		printUsage();
 		exit(1);
@@ -265,14 +295,6 @@
 		exit(-1);
 	}
 
-	/* Virtual Address for base address of GPIO Mux */
-	GPIO_MUX_BASE_ADDR = mmap_device_io(GPIO_MUX_BASE_SIZE,
-			GPIO_MUX_BASE_PHY_ADDR);
-	if (GPIO_MUX_BASE_ADDR == 0)
-	{
-		printf("mmap_device_io failed for GPIO Mux\n");
-		exit(-1);
-	}
 
 	/* Virtual Address GIC Interrupt configuration register */
 	GIC_ICFG_BASE_ADDR = mmap_device_io(GIC_ICFG_SIZE, GIC_ICFG_BASE_PHY_ADDR);
@@ -316,19 +338,7 @@
 		//
 		// See TRM for further information
 		//
-		int mux_offset = (interrupt - GPIOMUX_INTRTR0_OUTP_8) * 4;
 
-		// Disable Mux
-		current_value = in32(GPIO_MUX_BASE_ADDR + mux_offset);
-		printf("setting 0x%08lx to 0x%08x\n",
-				GPIO_MUX_BASE_PHY_ADDR + mux_offset,
-				current_value & ~(1 << 16));
-		out32(GPIO_MUX_BASE_ADDR + mux_offset, current_value & ~(1 << 16));
-
-		// Map input bank identifier to output interrupt
-		printf("setting 0x%08lx to 0x%08x\n",
-				GPIO_MUX_BASE_PHY_ADDR + mux_offset, mux_val);
-		out32(GPIO_MUX_BASE_ADDR + mux_offset, mux_val);
 
 		// Set GIC to be edge triggered
 		// NOTE: Setting of GIC at should be done using
@@ -336,22 +346,102 @@
 		// This code is included here, only to hi-lite that the GIC needs
 		// to be configured, and to allow the interrupt portion of this
 		// demo applicaiton to function.
-		uint32_t gic_offset = (interrupt / 16) * 4;
+		uint32_t gic_offset = ((interrupt + 32) / 16) * 4;
 		current_value = in32(GIC_ICFG_BASE_ADDR + gic_offset);
-		printf("setting 0x%08lx to 0x%08x\n",
+		printf("GIC Setting 0x%08lx to 0x%08x\n",
 				GIC_ICFG_BASE_PHY_ADDR + gic_offset,
-				current_value | (0x2 << (interrupt % 16) * 2));
+				current_value | (0x2 << ((interrupt + 32) % 16) * 2));
 		out32(GIC_ICFG_BASE_ADDR + gic_offset,
-				current_value | (0x2 << (interrupt % 16) * 2));
+				current_value | (0x2 << ((interrupt + 32) % 16) * 2));
 
-		// Enable Mux
-		current_value = in32(GPIO_MUX_BASE_ADDR + mux_offset);
-		printf("setting 0x%08lx to 0x%08x\n",
-				GPIO_MUX_BASE_PHY_ADDR + mux_offset, current_value | (1 << 16));
-		out32(GPIO_MUX_BASE_ADDR + mux_offset, current_value | (1 << 16));
+		{
+		    struct tisci_msg_rm_irq_set_req     rmIrqReq;
+		    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
+		    uint16_t src_id = 0U, src_index = 0U, dst_id,dst_host_irq;
+			int32_t retVal=CSL_PASS;
+
+
+		    /* We route bank interrupts to the cpu interrupts */
+		    switch (base_address)
+		    {
+		        case (uint32_t)WKUP_GPIO0_BASE:
+		            src_id = TISCI_DEV_WKUP_GPIO0;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO0 */
+		            break;
+		        case (uint32_t)WKUP_GPIO1_BASE:
+		            src_id = TISCI_DEV_WKUP_GPIO1;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO1 */
+		            break;
+		        case (uint32_t)GPIO0_BASE:
+		            src_id = TISCI_DEV_GPIO0;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721E_DEV_GPIO0 */
+		            break;
+		        case (uint32_t)GPIO2_BASE:
+		            src_id = TISCI_DEV_GPIO2;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721E_DEV_GPIO2 */
+		            break;
+		        case (uint32_t)GPIO4_BASE:
+		            src_id = TISCI_DEV_GPIO4;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721E_DEV_GPIO4 */
+		            break;
+		        case (uint32_t)GPIO6_BASE:
+		            src_id = TISCI_DEV_GPIO6;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide  for J721E_DEV_GPIO6 */
+		            break;
+		        case (uint32_t)GPIO1_BASE:
+		            src_id = TISCI_DEV_GPIO1;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide  for J721E_DEV_GPIO1 */
+		            break;
+		        case (uint32_t)GPIO3_BASE:
+		            src_id = TISCI_DEV_GPIO3;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide  for J721E_DEV_GPIO3 */
+		            break;
+		        case (uint32_t)GPIO5_BASE:
+		            src_id = TISCI_DEV_GPIO5;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide  for J721E_DEV_GPIO5 */
+		            break;
+		        case (uint32_t)GPIO7_BASE:
+		            src_id = TISCI_DEV_GPIO7;
+		            src_index = (uint16_t)gpio_bank;  /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide  for J721E_DEV_GPIO7 */
+		            break;
+		        default:
+		            break;
+		    }
+
+
+		    /* GPIO uses bank interrupts. So choose the bank interrupts from bus_gpio_bank with valid values from
+		     * the DMSC firmware user guide */
+		    dst_id = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS;
+		    dst_host_irq = interrupt + 32; //(uint16_t)intCfg[pinNum].intNum;
+
+			(void)memset (&rmIrqReq,0,sizeof(rmIrqReq));
+
+			rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+			rmIrqReq.src_id = src_id;
+			rmIrqReq.src_index = src_index;  /* This is the event coming out of the peripheral */
+
+			/* Set the destination interrupt */
+			rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
+			rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+
+			/* Set the destination based on the core */
+			rmIrqReq.dst_id       = dst_id;
+			rmIrqReq.dst_host_irq = dst_host_irq;
+
+
+			printf("srcId/%d srcIdx/%d, dstId/%d dstIrq/%d\n", rmIrqReq.src_id, rmIrqReq.src_index, rmIrqReq.dst_id, rmIrqReq.dst_host_irq);
+			retVal = Sciclient_rmIrqSet(
+					(const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
+					 &rmIrqResp,
+					 SCICLIENT_SERVICE_WAIT_FOREVER);
 
-		printf("Attaching to gpio%d_%d gpio_bank/%d interrupt/%d mux_val/%d\n",
-				gpio_module, gpio_num, gpio_bank, interrupt, mux_val);
+			if(retVal==CSL_PASS) {
+				printf("Sciclient_rmIrqSet worked %d\n", retVal);
+			}
+			else {
+				printf("Sciclient_rmIrqSet failed, may already be allocated %d\n", retVal);
+			}
+		}
 	}
 
 	/* Set GPIO as input */
@@ -362,7 +452,7 @@
 		/* Set GPIO_DIR01 to 1 to input */
 		current_value = INREG32(
 				BASE_ADDR + GPIO_DIR01 + ((gpio_bank/2) * 0x28));
-		printf("setting 0x%lx to 0x%x\n",
+		printf("0x%lx to 0x%x\n",
 				base_address + GPIO_DIR01 + ((gpio_bank / 2) * 0x28),
 				current_value | (1 << (gpio_num)));
 		OUTREG32((BASE_ADDR + GPIO_DIR01 + ((gpio_bank/2) * 0x28)),
@@ -380,7 +470,7 @@
 		/* Set GPIO_DIR01 to 1 to output */
 		current_value = INREG32(
 				BASE_ADDR + GPIO_DIR01 + ((gpio_bank/2) * 0x28));
-		printf("setting 0x%lx to 0x%x\n",
+		printf("0x%lx to 0x%x\n",
 				base_address + GPIO_DIR01 + ((gpio_bank / 2) * 0x28),
 				current_value & ~(1 << (gpio_num)));
 		OUTREG32((BASE_ADDR + GPIO_DIR01 + ((gpio_bank/2) * 0x28)),
@@ -397,6 +487,7 @@
 		/* Set GPIO_SETDATAOUT to 1 */
 		if (gpioHigh)
 		{
+			printf("GPIO should now be high\n");
 			current_value = INREG32(
 					BASE_ADDR + GPIO_SET_DATA01 + ((gpio_bank/2) * 0x28));
 			printf("setting 0x%lx to 0x%x\n",
@@ -404,12 +495,12 @@
 					(current_value | (1 << gpio_num)));
 			OUTREG32(BASE_ADDR + GPIO_SET_DATA01 + ((gpio_bank/2) * 0x28),
 					(current_value | (1 << gpio_num)));
-			printf("GPIO should now be high\n");
 		}
 
 		/* Set GPIO_CLEARDATAOUT to 1 (ie set output to 0) */
 		else
 		{
+			printf("GPIO should now be low\n");
 			current_value = INREG32(
 					BASE_ADDR + GPIO_CLR_DATA01 + ((gpio_bank/2) * 0x28));
 			printf("setting 0x%lx to 0x%x\n",
@@ -417,7 +508,6 @@
 					current_value & ~(1 << (gpio_num)));
 			OUTREG32(BASE_ADDR + GPIO_CLR_DATA01 + ((gpio_bank/2) * 0x28),
 					current_value | (1 << (gpio_num)));
-			printf("GPIO should now be low\n");
 		}
 		// Dump
 		dumpGpioRegs(base_address);
@@ -502,7 +592,9 @@
 	 */
 	if (attachToInterrupt)
 	{
-		id = InterruptAttachEvent(interrupt, &event, _NTO_INTR_FLAGS_TRK_MSK);
+
+		id = InterruptAttachEvent(interrupt + 32, &event, _NTO_INTR_FLAGS_TRK_MSK);
+
 		for (;;)
 		{
 			InterruptWait(0, NULL);
@@ -519,7 +611,7 @@
 					++irqCount);
 
 			/* Unmask interrupt */
-			InterruptUnmask(interrupt, id);
+			InterruptUnmask(interrupt + 32, id);
 
 			/* Clear the interrupt status */
 			printf("setting 0x%lx to 0x%x\n",
@@ -605,21 +697,6 @@
 void dumpGpioRegs(int base_address)
 {
 
-	/* GPIO Interrupt Mux */
-	/* Need to search Mux's for input port */
-	int mux_offset = 0;
-
-	for (int i = 0; i < 32; i++)
-	{
-		mux_offset = i * 4;
-		if ((INREG32(GPIO_MUX_BASE_ADDR + mux_offset) & 0x1FF) == mux_val)
-		{
-			printf(
-					" GPIOMUX_INTRTR0_MUXCNTL_%d               0x%08lx = 0x%08x\n",
-					8 + gpio_bank, GPIO_MUX_BASE_PHY_ADDR + mux_offset,
-					INREG32(GPIO_MUX_BASE_ADDR + mux_offset));
-		}
-	}
 
 	/* Registers common to all Banks */
 	printf(" GPIOPID               0x%08x = 0x%08x\n", base_address + GPIOPID,
@@ -791,5 +868,7 @@
 				INREG32(BASE_ADDR + GPIO_INTSTAT8));
 	}
 	printf("\n");
+
 }
 
+
Only in qnx_baseline/examples/gpio/src: gpio.c.orig
diff -ru qnx_baseline/examples/gpio/src/gpio.use qnx/examples/gpio/src/gpio.use
--- qnx_baseline/examples/gpio/src/gpio.use	2024-02-05 08:26:07.653658397 -0800
+++ qnx/examples/gpio/src/gpio.use	2024-02-05 13:15:52.084695567 -0800
@@ -44,10 +44,10 @@
          by using the below command line, commands:
          
          # Set PADCONFIG for GPIO0_0
-         out32 0x0011c000 0x40007
+         k3conf write 0x0011c000 0x40007
          
          # Configure GPIO module, Interrupt Mux, and attach interrupt
-         gpio-j7 -m0 -n0 -a392 -i -r1 &
+         gpio -m0 -n0 -a392 -i -r1 &
          
          # To see bit fields being set / unset, when pushing / holding SW10
          gpio -m0 -n0 -d
