------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  1(TIDL_TopKLayer) [1, 1] --[1 x 64 x  8192] => [3 x 3 x  8192] *** [1] ***[ COL] ***[0, 0, 0, 174848, 1048576]**** [6], [0],[6] -[0 ]---
  IN: DDR, DMA, 100000(1048576), 100000(1048576),    1(    1), 100400(1049600),   0,        0 ||||  L2, DMA,  55600(349696),  55600(349696),    1(    1),  55600( 349696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   c000( 49152),   c000( 49152),    3(    3),  24080( 147584),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_SliceLayer) [2, 2] --[3 x 8192 x  3] => [1 x 8192 x  3] *** [3] ***[ COL] ***[0, 0, 0, 49152, 49152]**** [1], [0],[1] -[1 ]---
  IN:MSMC, DMA,   c000( 49152),   c000( 49152),    3(    3),  24080( 147584),   0,        0 ||||  L2, DMA,   c000( 49152),   c000( 49152),    3(    3),  24000( 147456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff |||| DDR, CPU,   c000( 49152),   c000( 49152),    1(    1),   c400(  50176),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_SliceLayer) [4, 3] --[3 x 8192 x  3] => [2 x 8192 x  3] *** [3] ***[ COL] ***[0, 0, 0, 49152, 49152]**** [1], [0],[1] -[1 ]---
  IN:MSMC, DMA,   c000( 49152),   c000( 49152),    3(    3),  24080( 147584),   0,        0 ||||  L2, DMA,   c000( 49152),   c000( 49152),    3(    3),  24000( 147456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff |||| DDR, CPU,   c000( 49152),   c000( 49152),    2(    2),  18400(  99328),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
