------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  8(TIDL_DataConvertLayer) [1, 8] --[3 x 640 x  384] => [3 x 640 x  384] *** [3] ***[ COL] ***[0, 0, 0, 163840, 983040]**** [18], [0],[18] -[0 ]---
  IN: DDR, DMA,  f0000(983040),  f0000(983040),    3(    3), 2d0400(2950144),   0,        0 ||||  L2, DMA,  50000(327680),  50000(327680),    1(    1),  50000( 327680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    3(    3),  b5482( 742530), 282,       7e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  9(TIDL_ConvolutionLayer) [2, 9] --[3 x 640 x  384] => [32 x 640 x  384] *** [3] ***[ROW_L] ***[1284, 1344, 1344, 45120, 247427]**** [6], [1],[6] -[8 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    3(    3),  b5482( 742530),   0,       7e ||||  L2, DMA,  165c0( 91584),  165c0( 91584),    3(    3),  6f280( 455296),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),   20(   32), 78d802(7919618), 282,       7e 
  WT:DDR_PERSIST, DMA,     21(    33),     21(    33),   20(   32),    480(   1152),   0,        0 ||||  L2, DMA,     21(    33),     21(    33),   20(   32),    480(   1152),   0,    6f280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  10(TIDL_BatchNormLayer) [3, 10] --[32 x 640 x  384] => [32 x 640 x  384] *** [32] ***[ COL] ***[0, 0, 0, 123072, 246144]**** [64], [0],[64] -[9 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),   20(   32), 78d802(7919618), 282,       7e ||||  L2, DMA,  3c180(246144),  3c180(246144),    1(    1),  3c180( 246144),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),   20(   32), 78d802(7919618), 282,       7e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  11(TIDL_ConvolutionLayer) [4, 11] --[32 x 640 x  384] => [64 x 320 x  192] *** [32] ***[ROW_L] ***[642, 642, 642, 2564, 246786]**** [96], [1],[96] -[10 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),   20(   32), 78d802(7919618),   0,       7e ||||  L2, DMA,   16c0(  5824),   16c0(  5824),   20(   32),  68580( 427392),   0,        0 
 OUT:MSMC, CPU,    2c0(   704),    282(   642),   40(   64),  16000(  90112),   0,   78d880 |||| DDR, DMA,   f780( 63360),   f343( 62275),   40(   64), 3de442(4056130), 142,       3e 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   40(   64),   4880(  18560),   0,      480 ||||  L2, DMA,    140(   320),    121(   289),   40(   64),   5000(  20480),   0,    68580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  12(TIDL_BatchNormLayer) [5, 12] --[64 x 320 x  192] => [64 x 320 x  192] *** [64] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [32], [0],[32] -[11 ]---
  IN: DDR, DMA,   f780( 63360),   f343( 62275),   40(   64), 3de442(4056130), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   40(   64), 3cf042(3993666), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  13(TIDL_ConvolutionLayer) [6, 13] --[64 x 320 x  192] => [64 x 320 x  192] *** [64] ***[ROW_L] ***[644, 704, 704, 2368, 62275]**** [27], [1],[27] -[12 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   40(   64), 3cf042(3993666),   0,       3e ||||  L2, DMA,   1540(  5440),   1540(  5440),   40(   64),  63780( 407424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   40(   64), 3cf042(3993666), 142,       3e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,     4d00 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  14(TIDL_BatchNormLayer) [7, 14] --[64 x 320 x  192] => [64 x 320 x  192] *** [64] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [32], [0],[32] -[13 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   40(   64), 3cf042(3993666), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   40(   64), 3cf042(3993666), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  15(TIDL_ConvolutionLayer) [8, 15] --[64 x 320 x  192] => [128 x 160 x  96] *** [64] ***[ROW_L] ***[322, 322, 322, 1926, 61954]**** [32], [1],[32] -[14 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   40(   64), 3cf042(3993666),   0,       3e ||||  L2, DMA,   10c0(  4288),   10c0(  4288),   40(   64),  51180( 332160),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3cf0de 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   80(  128),  12080(  73856),   0,     dd80 ||||  L2, DMA,    2c0(   704),    241(   577),   80(  128),  16000(  90112),   0,    51180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  16(TIDL_BatchNormLayer) [9, 16] --[128 x 160 x  96] => [128 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [16], [0],[16] -[15 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3cf0de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  18(TIDL_ConvolutionLayer) [10, 18] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 15456]**** [10], [1],[10] -[16 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  69200( 430592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   40(   64),   2080(   8320),   0,    1fe00 ||||  L2, DMA,     c0(   192),     81(   129),   40(   64),   3000(  12288),   0,    69200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  20(TIDL_BatchNormLayer) [11, 20] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[18 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  17(TIDL_ConvolutionLayer) [12, 17] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 15456]**** [10], [1],[10] -[16 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  69200( 430592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   40(   64),   2080(   8320),   0,    21e80 ||||  L2, DMA,     c0(   192),     81(   129),   40(   64),   3000(  12288),   0,    69200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  19(TIDL_BatchNormLayer) [13, 19] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[17 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  21(TIDL_ConvolutionLayer) [14, 21] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 2880, 15779]**** [6], [1],[6] -[19 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,    f70de ||||  L2, DMA,   1840(  6208),   1840(  6208),   40(   64),  63d00( 408832),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee15e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    23f00 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63d00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  22(TIDL_BatchNormLayer) [15, 22] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[21 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee15e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee15e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  23(TIDL_ConvolutionLayer) [16, 23] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 2880, 15779]**** [6], [1],[6] -[22 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,   1ee15e ||||  L2, DMA,   1840(  6208),   1840(  6208),   40(   64),  63d00( 408832),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee15e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    2cf80 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63d00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  24(TIDL_BatchNormLayer) [17, 24] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[23 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee15e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee15e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  25(TIDL_ConvolutionLayer) [18, 25] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 2880, 15779]**** [6], [1],[6] -[24 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,   1ee15e ||||  L2, DMA,   1840(  6208),   1840(  6208),   40(   64),  63d00( 408832),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   2e51de 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    36000 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63d00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  26(TIDL_BatchNormLayer) [19, 26] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[25 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   2e51de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   2e51de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  27(TIDL_ConvolutionLayer) [20, 27] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 2880, 15779]**** [6], [1],[6] -[26 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,   2e51de ||||  L2, DMA,   1840(  6208),   1840(  6208),   40(   64),  63d00( 408832),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   2e51de 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    3f080 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63d00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  28(TIDL_BatchNormLayer) [21, 28] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[27 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   2e51de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   2e51de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  29(TIDL_ConcatLayer) [22, 29] --[256 x 160 x  96] => [256 x 160 x  96] *** [256] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [32], [0],[32] -[20 19 24 28 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,   3dc25e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  30(TIDL_ConvolutionLayer) [23, 30] --[256 x 160 x  96] => [256 x 160 x  96] *** [256] ***[ROW_L] ***[0, 0, 0, 640, 15456]**** [25], [1],[25] -[29 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,   3dc25e ||||  L2, DMA,    540(  1344),    540(  1344),  100(  256),  57980( 358784),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,       5e 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),  100(  256),  10100(  65792),   0,    48100 ||||  L2, DMA,    140(   320),    101(   257),  100(  256),  14000(  81920),   0,    57980 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  31(TIDL_BatchNormLayer) [24, 31] --[256 x 160 x  96] => [256 x 160 x  96] *** [256] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [32], [0],[32] -[30 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  34(TIDL_ConvolutionLayer) [25, 34] --[256 x 160 x  96] => [128 x 160 x  96] *** [256] ***[ROW_L] ***[324, 384, 384, 64, 15779]**** [241], [1],[241] -[31 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),   0,       5e ||||  L2, DMA,    200(   512),    200(   512),  100(  256),  23c00( 146432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3dc0de 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),   80(  128),  48080( 295040),   0,    58200 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    23c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  37(TIDL_BatchNormLayer) [26, 37] --[128 x 160 x  96] => [128 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [16], [0],[16] -[34 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3dc0de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:MSMC, CPU,   3cc0( 15552),   3c60( 15456),   10(   16),  3cc00( 248832),   0,   5ca100 |||| DDR, DMA,   3da3( 15779),   3da3( 15779),   80(  128), 1ed5a2(2020770),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  32(TIDL_ConvolutionLayer) [27, 32] --[256 x 160 x  96] => [128 x 160 x  96] *** [256] ***[ROW_L] ***[0, 0, 0, 704, 15456]**** [22], [1],[22] -[31 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,       5e ||||  L2, DMA,    5c0(  1472),    5c0(  1472),  100(  256),  5f700( 390912),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3dc0de 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,    a0280 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    5f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  35(TIDL_BatchNormLayer) [28, 35] --[128 x 160 x  96] => [128 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [16], [0],[16] -[32 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3dc0de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,   3dc0de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  38(TIDL_ConvolutionLayer) [29, 38] --[128 x 160 x  96] => [128 x 80 x  48] *** [128] ***[ROW_L] ***[162, 162, 162, 966, 15618]**** [16], [1],[16] -[35 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),   0,   3dc0de ||||  L2, DMA,    840(  2112),    840(  2112),   80(  128),  45500( 283904),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    f40(  3904),    f01(  3841),   80(  128),  7a000( 499712),   0,   5ca100 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,    a8300 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    45500 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  40(TIDL_BatchNormLayer) [30, 40] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3840, 3840]**** [4], [0],[4] -[38 ]---
  IN:MSMC, DMA,    f40(  3904),    f01(  3841),   80(  128),  7a000( 499712),   0,   5ca100 ||||  L2, DMA,    f50(  3920),    f50(  3920),   40(   64),  3d400( 250880),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    f40(  3904),    f00(  3840),   80(  128),  7a000( 499712),   0,   3dc080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  33(TIDL_PoolingLayer) [31, 33] --[256 x 160 x  96] => [256 x 80 x  48] *** [256] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [32], [0],[32] -[31 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    f40(  3904),    f00(  3840),  100(  256),  f4000( 999424),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  36(TIDL_ConvolutionLayer) [32, 36] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3840]**** [5], [1],[5] -[33 ]---
  IN:MSMC, DMA,    f40(  3904),    f00(  3840),  100(  256),  f4000( 999424),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64900( 411904),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    f40(  3904),    f00(  3840),   80(  128),  7a000( 499712),   0,        0 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,    cc380 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  39(TIDL_BatchNormLayer) [33, 39] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3840, 3840]**** [4], [0],[4] -[36 ]---
  IN:MSMC, DMA,    f40(  3904),    f00(  3840),   80(  128),  7a000( 499712),   0,        0 ||||  L2, DMA,    f50(  3920),    f50(  3920),   40(   64),  3d400( 250880),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    f40(  3904),    f00(  3840),   80(  128),  7a000( 499712),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  41(TIDL_ConcatLayer) [34, 41] --[256 x 80 x  48] => [256 x 80 x  48] *** [256] ***[ COL] ***[0, 0, 0, 3840, 3840]**** [8], [0],[8] -[39 40 ]---
  IN:MSMC, DMA,    f40(  3904),    f00(  3840),   80(  128),  7a000( 499712),   0,        0 ||||  L2, DMA,    f50(  3920),    f50(  3920),   40(   64),  3d400( 250880),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,    820ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  43(TIDL_ConvolutionLayer) [35, 43] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3888]**** [6], [1],[6] -[41 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,    820ae ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64c00( 412672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,    d4400 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  45(TIDL_BatchNormLayer) [36, 45] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[43 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  42(TIDL_ConvolutionLayer) [37, 42] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3888]**** [6], [1],[6] -[41 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,    820ae ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64c00( 412672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    820ae 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,    dc480 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  44(TIDL_BatchNormLayer) [38, 44] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[42 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    820ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    820ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  46(TIDL_ConvolutionLayer) [39, 46] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1024, 4051]**** [4], [1],[4] -[44 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,    820ae ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46800( 288768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   10412e 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,    e4500 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  47(TIDL_BatchNormLayer) [40, 47] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[46 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   10412e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   10412e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  48(TIDL_ConvolutionLayer) [41, 48] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1024, 4051]**** [4], [1],[4] -[47 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,   10412e ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46800( 288768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   10412e 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   108580 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  49(TIDL_BatchNormLayer) [42, 49] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[48 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   10412e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   10412e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  50(TIDL_ConvolutionLayer) [43, 50] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1024, 4051]**** [4], [1],[4] -[49 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,   10412e ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46800( 288768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1861ae 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   12c600 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  51(TIDL_BatchNormLayer) [44, 51] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[50 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1861ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1861ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  52(TIDL_ConvolutionLayer) [45, 52] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1024, 4051]**** [4], [1],[4] -[51 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,   1861ae ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46800( 288768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1861ae 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   150680 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  53(TIDL_BatchNormLayer) [46, 53] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[52 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1861ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1861ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  54(TIDL_ConcatLayer) [47, 54] --[512 x 80 x  48] => [512 x 80 x  48] *** [512] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [16], [0],[16] -[45 44 49 53 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:MSMC, CPU,    f40(  3904),    f30(  3888),   40(   64),  3d000( 249856),   0,   208200 |||| DDR, DMA,    fd3(  4051),    fd3(  4051),  200(  512), 1faa52(2075218),  52,   1ed62e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  55(TIDL_ConvolutionLayer) [48, 55] --[512 x 80 x  48] => [512 x 80 x  48] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 3888]**** [61], [1],[61] -[54 ]---
  IN: DDR, DMA,    fd3(  4051),    fd3(  4051),  200(  512), 1faa52(2075218),  52,   1ed62e ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18e80( 102016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),  200(  512), 208052(2130002),  52,    820ae 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  200(  512),  40200( 262656),   0,   174700 ||||  L2, DMA,    240(   576),    201(   513),  200(  512),  48000( 294912),   0,    18e80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  56(TIDL_BatchNormLayer) [49, 56] --[512 x 80 x  48] => [512 x 80 x  48] *** [512] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [16], [0],[16] -[55 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  200(  512), 208052(2130002),  52,    820ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),  200(  512), 208052(2130002),  52,    820ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  59(TIDL_ConvolutionLayer) [50, 59] --[512 x 80 x  48] => [128 x 80 x  48] *** [512] ***[ROW_L] ***[0, 0, 0, 320, 3888]**** [13], [1],[13] -[56 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  200(  512), 208052(2130002),  52,    820ae ||||  L2, DMA,    2c0(   704),    2c0(   704),  200(  512),  58d80( 363904),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),   80(  128),  10080(  65664),   0,   1b4900 ||||  L2, DMA,    240(   576),    201(   513),   80(  128),  12000(  73728),   0,    58d80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  62(TIDL_BatchNormLayer) [51, 62] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[59 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  57(TIDL_ConvolutionLayer) [52, 57] --[512 x 80 x  48] => [256 x 80 x  48] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 3888]**** [16], [1],[16] -[56 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  200(  512), 208052(2130002),  52,    820ae ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48e00( 298496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,   28a12e 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   1c4980 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48e00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  60(TIDL_BatchNormLayer) [53, 60] --[256 x 80 x  48] => [256 x 80 x  48] *** [256] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [8], [0],[8] -[57 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,   28a12e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,   28a12e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  63(TIDL_ConvolutionLayer) [54, 63] --[256 x 80 x  48] => [256 x 40 x  24] *** [256] ***[ROW_L] ***[82, 82, 82, 162, 3970]**** [24], [96],[96] -[60 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),   0,   28a12e ||||  L2, DMA,    1c0(   448),    1c0(   448),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    3c1(   961),  100(  256),  44000( 278528),   0,   422180 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   1e4a80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    1ce00 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   38e180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  65(TIDL_BatchNormLayer) [55, 65] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 960, 960]**** [1], [0],[1] -[63 ]---
  IN:MSMC, DMA,    440(  1088),    3c1(   961),  100(  256),  44000( 278528),   0,   422180 ||||  L2, DMA,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,   28a100 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  58(TIDL_PoolingLayer) [56, 58] --[512 x 80 x  48] => [512 x 40 x  24] *** [512] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [16], [0],[16] -[56 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  200(  512), 208052(2130002),  52,    820ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),  200(  512),  78000( 491520),   0,    82080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  61(TIDL_ConvolutionLayer) [57, 61] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 960]**** [4], [1],[4] -[58 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),  200(  512),  78000( 491520),   0,    82080 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,    82080 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   274b80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  64(TIDL_BatchNormLayer) [58, 64] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 960, 960]**** [1], [0],[1] -[61 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,    82080 ||||  L2, DMA,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,    82080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  66(TIDL_ConcatLayer) [59, 66] --[512 x 40 x  24] => [512 x 40 x  24] *** [512] ***[ COL] ***[0, 0, 0, 960, 960]**** [4], [0],[4] -[64 65 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,    82080 ||||  L2, DMA,    3c0(   960),    3c0(   960),  100(  256),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,    c6156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  68(TIDL_ConvolutionLayer) [60, 68] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 984]**** [4], [1],[4] -[66 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,    c6156 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    820d6 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   294c80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  70(TIDL_BatchNormLayer) [61, 70] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[68 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    820d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    820d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  67(TIDL_ConvolutionLayer) [62, 67] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 984]**** [4], [1],[4] -[66 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,    c6156 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    c6156 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   2b4d80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  69(TIDL_BatchNormLayer) [63, 69] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[67 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    c6156 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    c6156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  71(TIDL_ConvolutionLayer) [64, 71] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ROW_L] ***[84, 128, 128, 192, 1067]**** [5], [20],[20] -[69 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,    c6156 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   19e1d6 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   2d4e80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   10a180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  72(TIDL_BatchNormLayer) [65, 72] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[71 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   19e1d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   10a1d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  73(TIDL_ConvolutionLayer) [66, 73] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ROW_L] ***[84, 128, 128, 192, 1067]**** [5], [20],[20] -[72 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,   10a1d6 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   10a1d6 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   364f80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   14e200 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  74(TIDL_BatchNormLayer) [67, 74] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[73 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   10a1d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   10a1d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  75(TIDL_ConvolutionLayer) [68, 75] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ROW_L] ***[84, 128, 128, 192, 1067]**** [5], [20],[20] -[74 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,   10a1d6 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1e2256 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   3f5080 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   14e200 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  76(TIDL_BatchNormLayer) [69, 76] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[75 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1e2256 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   14e256 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  77(TIDL_ConvolutionLayer) [70, 77] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ROW_L] ***[84, 128, 128, 192, 1067]**** [5], [20],[20] -[76 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,   14e256 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   14e256 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   485180 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   192280 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  78(TIDL_BatchNormLayer) [71, 78] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[77 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   14e256 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   14e256 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  0],  To fill zero OUT: [ 0,  0]
------  79(TIDL_ConcatLayer) [72, 79] --[1024 x 40 x  24] => [1024 x 40 x  24] *** [1024] ***[ COL] ***[0, 0, 0, 984, 984]**** [8], [0],[8] -[70 69 74 78 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    820d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   192956 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  80(TIDL_ConvolutionLayer) [73, 80] --[1024 x 40 x  24] => [1024 x 40 x  24] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 984]**** [16], [256],[256] -[79 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   192956 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30380( 197504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   1920d6 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  400( 1024), 100400(1049600),   0,   515280 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30380 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  400( 1024), 110000(1114112),   0,    82080 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  81(TIDL_BatchNormLayer) [74, 81] --[1024 x 40 x  24] => [1024 x 40 x  24] *** [1024] ***[ COL] ***[0, 0, 0, 984, 984]**** [8], [0],[8] -[80 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   1920d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,    820d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  84(TIDL_ConvolutionLayer) [75, 84] --[1024 x 40 x  24] => [256 x 40 x  24] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 984]**** [16], [1],[16] -[81 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,    820d6 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20380( 131968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   192156 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,   615680 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20380 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  87(TIDL_BatchNormLayer) [76, 87] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[84 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   192156 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   192156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  82(TIDL_ConvolutionLayer) [77, 82] --[1024 x 40 x  24] => [512 x 40 x  24] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 984]**** [16], [128],[128] -[81 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,    820d6 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30380( 197504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,   25e1d6 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  200(  512),  80200( 524800),   0,   655780 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30380 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  200(  512),  88000( 557056),   0,   1d6180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  85(TIDL_BatchNormLayer) [78, 85] --[512 x 40 x  24] => [512 x 40 x  24] *** [512] ***[ COL] ***[0, 0, 0, 984, 984]**** [4], [0],[4] -[82 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,   25e1d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,   1d61d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  88(TIDL_ConvolutionLayer) [79, 88] --[512 x 40 x  24] => [512 x 20 x  12] *** [512] ***[ROW_L] ***[42, 42, 42, 82, 1026]**** [12], [192],[192] -[85 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),   0,   1d61d6 ||||  L2, DMA,    100(   256),    100(   256),  200(  512),  20380( 131968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f1(   241),  200(  512),  2a800( 174080),   0,   25e200 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),  200(  512), 240200(2359808),   0,   6d5980 ||||  L2, DMA,   1240(  4672),   1201(  4609),   44(   68),  4d900( 317696),   0,    20380 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  90(TIDL_BatchNormLayer) [80, 90] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[88 ]---
  IN:MSMC, DMA,    140(   320),     f1(   241),  200(  512),  2a800( 174080),   0,   25e200 ||||  L2, DMA,    140(   320),    140(   320),  200(  512),  28000( 163840),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  200(  512),  28000( 163840),   0,   1d6180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  83(TIDL_PoolingLayer) [81, 83] --[1024 x 40 x  24] => [1024 x 20 x  12] *** [1024] ***[ COL] ***[0, 0, 0, 984, 984]**** [8], [0],[8] -[81 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,    820d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  400( 1024),  50000( 327680),   0,    82080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  86(TIDL_ConvolutionLayer) [82, 86] --[1024 x 20 x  12] => [512 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 240]**** [4], [32],[32] -[83 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  400( 1024),  50000( 327680),   0,    82080 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  200(  512),  28000( 163840),   0,    82080 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  200(  512),  80200( 524800),   0,   915b80 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30080 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  200(  512),  88000( 557056),   0,    d2080 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  89(TIDL_BatchNormLayer) [83, 89] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[86 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  200(  512),  28000( 163840),   0,    82080 ||||  L2, DMA,    140(   320),    140(   320),  200(  512),  28000( 163840),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  200(  512),  28000( 163840),   0,    82080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  91(TIDL_ConcatLayer) [84, 91] --[1024 x 20 x  12] => [1024 x 20 x  12] *** [1024] ***[ COL] ***[0, 0, 0, 240, 240]**** [2], [0],[2] -[89 90 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  200(  512),  28000( 163840),   0,    82080 ||||  L2, DMA,    140(   320),    140(   320),  400( 1024),  50000( 327680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  400( 1024),  50016( 327702),  16,    aa0ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  93(TIDL_ConvolutionLayer) [85, 93] --[1024 x 20 x  12] => [256 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 252]**** [4], [1],[4] -[91 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  400( 1024),  50016( 327702),  16,    aa0ea ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20080( 131200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    820ea 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,   995d80 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  95(TIDL_BatchNormLayer) [86, 95] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[93 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    820ea ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    820ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  92(TIDL_ConvolutionLayer) [87, 92] --[1024 x 20 x  12] => [256 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 252]**** [4], [1],[4] -[91 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  400( 1024),  50016( 327702),  16,    aa0ea ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20080( 131200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    9636a 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,   9d5e80 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  94(TIDL_BatchNormLayer) [88, 94] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[92 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    9636a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    9616a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  96(TIDL_ConvolutionLayer) [89, 96] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[94 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,    9616a ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   13e1ea 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   a15f80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    aa180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  97(TIDL_BatchNormLayer) [90, 97] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[96 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   13e1ea ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   13e1ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  98(TIDL_ConvolutionLayer) [91, 98] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[97 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,   13e1ea ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   13e1ea 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   aa6080 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    aa180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  99(TIDL_BatchNormLayer) [92, 99] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[98 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   13e1ea ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    aa1ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  100(TIDL_ConvolutionLayer) [93, 100] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[99 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,    aa1ea ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   15226a 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   b36180 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    be200 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  101(TIDL_BatchNormLayer) [94, 101] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[100 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   15226a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   15226a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  102(TIDL_ConvolutionLayer) [95, 102] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[101 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,   15226a ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   15226a 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   bc6280 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    be200 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  103(TIDL_BatchNormLayer) [96, 103] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[102 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,   15226a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    be26a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  104(TIDL_ConcatLayer) [97, 104] --[1024 x 20 x  12] => [1024 x 20 x  12] *** [1024] ***[ COL] ***[0, 0, 0, 252, 252]**** [4], [0],[4] -[95 94 99 103 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    820ea ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,   1d61d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 2,  2], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  105(TIDL_ConvolutionLayer) [98, 105] --[1024 x 20 x  12] => [1024 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 264]**** [5], [80],[80] -[104 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,   1d61d2 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,   1d61d2 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  400( 1024), 100400(1049600),   0,   c56380 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30080 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  400( 1024), 110000(1114112),   0,    82080 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  2],  To fill zero OUT: [ 0,  0]
------  106(TIDL_BatchNormLayer) [99, 106] --[1024 x 20 x  12] => [1024 x 20 x  12] *** [1024] ***[ COL] ***[0, 0, 0, 264, 264]**** [4], [0],[4] -[105 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,   1d61d2 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,    b2152 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  108(TIDL_ConvolutionLayer) [100, 108] --[1024 x 20 x  12] => [256 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 264]**** [5], [1],[5] -[106 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,    b2152 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20100( 131328),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    820d2 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,   d56780 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  2],  To fill zero OUT: [ 0,  0]
------  110(TIDL_BatchNormLayer) [101, 110] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[108 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    820d2 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    820d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  2],  To fill zero OUT: [ 2,  2]
------  112(TIDL_ConvolutionLayer) [102, 112] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[110 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    820d2 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    9e100 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,   d96880 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  114(TIDL_BatchNormLayer) [103, 114] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[112 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    9e100 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    9e100 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  107(TIDL_ConvolutionLayer) [104, 107] --[1024 x 20 x  12] => [256 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 264]**** [5], [1],[5] -[106 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,    b2152 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20100( 131328),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,   d9ea80 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  2],  To fill zero OUT: [ 0,  0]
------  109(TIDL_BatchNormLayer) [105, 109] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[107 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    ea1d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 2,  2],  To fill zero OUT: [ 2,  2]
------  111(TIDL_ConvolutionLayer) [106, 111] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[109 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    ea1d2 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    b2100 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,   ddeb80 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  113(TIDL_BatchNormLayer) [107, 113] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[111 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    b2100 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,   106200 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  115(TIDL_ConcatLayer) [108, 115] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 264, 264]**** [2], [0],[2] -[109 113 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    ea1d2 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  200(  512),  3802e( 229422),  2e,    b2152 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  116(TIDL_ConvolutionLayer) [109, 116] --[512 x 20 x  12] => [256 x 20 x  12] *** [512] ***[ROW_L] ***[46, 64, 64, 64, 309]**** [4], [28],[28] -[115 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  200(  512),  3802e( 229422),  17,    b2152 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18080(  98432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),  100(  256), 120100(1179904),   0,   de6d80 ||||  L2, DMA,   1240(  4672),   1201(  4609),   4c(   76),  56b00( 355072),   0,    18080 
 STG:MSMC, DMA,   15ac(  5548),   1201(  4609),  100(  256), 15ac00(1420288),   0,   1d6180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  2],  To fill zero OUT: [ 0,  0]
------  117(TIDL_BatchNormLayer) [110, 117] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[116 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  2],  To fill zero OUT: [ 2,  2]
------  118(TIDL_ConvolutionLayer) [111, 118] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[117 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    b2152 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    ce180 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,   f06e80 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  119(TIDL_BatchNormLayer) [112, 119] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[118 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    ce180 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    ce180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  120(TIDL_ConcatLayer) [113, 120] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 264, 264]**** [2], [0],[2] -[117 119 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  200(  512),  3802e( 229422),  2e,    e21d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  121(TIDL_ConvolutionLayer) [114, 121] --[512 x 20 x  12] => [256 x 20 x  12] *** [512] ***[ROW_L] ***[0, 0, 0, 264, 264]**** [1], [1],[1] -[120 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  200(  512),  3802e( 229422),  2e,    e21d2 ||||  L2, DMA,    140(   320),    140(   320),  200(  512),  28000( 163840),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   f0f080 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    28000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  2],  To fill zero OUT: [ 0,  0]
------  122(TIDL_BatchNormLayer) [115, 122] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[121 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    da1d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 2,  2],  To fill zero OUT: [ 2,  2]
------  123(TIDL_ConvolutionLayer) [116, 123] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[122 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    da1d2 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    b2100 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,   f2f180 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  124(TIDL_BatchNormLayer) [117, 124] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[123 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    b2100 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    f6200 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  125(TIDL_ConcatLayer) [118, 125] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 264, 264]**** [2], [0],[2] -[122 124 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    da1d2 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    b216a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  126(TIDL_PoolingLayer) [119, 126] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[125 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,    b216a ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    da1ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  127(TIDL_PoolingLayer) [120, 127] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[126 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,    da1ea ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    da1ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  128(TIDL_PoolingLayer) [121, 128] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[127 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,    da1ea ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,   10226a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  129(TIDL_PoolingLayer) [122, 129] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[128 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,   10226a ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,   10226a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  130(TIDL_PoolingLayer) [123, 130] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[129 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,   10226a ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,   12a2ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  131(TIDL_PoolingLayer) [124, 131] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[130 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,   12a2ea ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,   12a2ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  0],  To fill zero OUT: [ 0,  0]
------  132(TIDL_ConcatLayer) [125, 132] --[2048 x 20 x  12] => [2048 x 20 x  12] *** [2048] ***[ COL] ***[0, 0, 0, 252, 252]**** [4], [0],[4] -[125 127 129 131 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    b216a ||||  L2, DMA,    150(   336),    150(   336),  400( 1024),  54000( 344064),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  800( 2048),  e002e( 917550),  2e,   1d61d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 2,  2], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  133(TIDL_ConvolutionLayer) [126, 133] --[2048 x 20 x  12] => [256 x 20 x  12] *** [2048] ***[ROW_L] ***[0, 0, 0, 64, 264]**** [5], [30],[30] -[132 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  800( 2048),  e002e( 917550),  2e,   1d61d2 ||||  L2, DMA,     80(   128),     80(   128),  800( 2048),  40100( 262400),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,   140652 
  WT:DDR_PERSIST, DMA,    801(  2049),    801(  2049),  100(  256),  80100( 524544),   0,   f37380 ||||  L2, DMA,    840(  2112),    801(  2049),   5c(   92),  2f700( 194304),   0,    40100 
 STG:MSMC, DMA,    8e5(  2277),    801(  2049),  100(  256),  8e500( 582912),   0,    b2100 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  2],  To fill zero OUT: [ 0,  0]
------  134(TIDL_BatchNormLayer) [127, 134] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[133 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,   140652 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    ea1d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 2,  2],  To fill zero OUT: [ 2,  2]
------  135(TIDL_ConvolutionLayer) [128, 135] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[134 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    ea1d2 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    b2100 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,   fb7480 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  136(TIDL_BatchNormLayer) [129, 136] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[135 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    b2100 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,   106200 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  137(TIDL_ConcatLayer) [130, 137] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 264, 264]**** [2], [0],[2] -[134 136 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    ea1d2 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  200(  512),  3802e( 229422),  2e,    b2152 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  138(TIDL_ConvolutionLayer) [131, 138] --[512 x 20 x  12] => [256 x 20 x  12] *** [512] ***[ROW_L] ***[46, 64, 64, 64, 309]**** [4], [28],[28] -[137 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  200(  512),  3802e( 229422),  17,    b2152 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18080(  98432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),  100(  256), 120100(1179904),   0,   fbf680 ||||  L2, DMA,   1240(  4672),   1201(  4609),   4c(   76),  56b00( 355072),   0,    18080 
 STG:MSMC, DMA,   15ac(  5548),   1201(  4609),  100(  256), 15ac00(1420288),   0,   1d6180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  2],  To fill zero OUT: [ 0,  0]
------  139(TIDL_BatchNormLayer) [132, 139] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[138 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 1,  2],  To fill zero OUT: [ 2,  2]
------  140(TIDL_ConvolutionLayer) [133, 140] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[139 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    b2152 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    ce180 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,  10df780 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  141(TIDL_BatchNormLayer) [134, 141] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[140 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    ce180 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    ce180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  142(TIDL_ConcatLayer) [135, 142] --[1024 x 20 x  12] => [1024 x 20 x  12] *** [1024] ***[ COL] ***[0, 0, 0, 264, 264]**** [4], [0],[4] -[139 141 110 114 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    b2152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,    e21d2 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  143(TIDL_ConvolutionLayer) [136, 143] --[1024 x 20 x  12] => [256 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 264]**** [5], [1],[5] -[142 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  400( 1024),  7002e( 458798),  2e,    e21d2 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20100( 131328),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    820d2 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,  10e7980 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 0,  2],  To fill zero OUT: [ 0,  0]
------  144(TIDL_BatchNormLayer) [137, 144] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 264, 264]**** [1], [0],[1] -[143 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    820d2 ||||  L2, DMA,    1ce(   462),    1ce(   462),  100(  256),  1ce00( 118272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    aa152 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 2,  2], Required OUT : [ 2,  2],  To fill zero OUT: [ 2,  2]
------  145(TIDL_ConvolutionLayer) [138, 145] --[256 x 20 x  12] => [256 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 354, 354]**** [1], [1],[1] -[144 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),   0,    aa152 ||||  L2, DMA,    160(   352),    160(   352),  100(  256),  16080(  90240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    82080 
  WT:DDR_PERSIST, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,  1127a80 ||||  L2, DMA,     1a(    26),     1a(    26),  500( 1280),   8200(  33280),   0,    16080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  146(TIDL_BatchNormLayer) [139, 146] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[145 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    82080 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    c6180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  147(TIDL_ConcatLayer) [140, 147] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 264, 264]**** [2], [0],[2] -[144 146 ]---
  IN:MSMC, DMA,    1c0(   448),    162(   354),  100(  256),  1c02e( 114734),  2e,    aa152 ||||  L2, DMA,    1ce(   462),    1ce(   462),  200(  512),  39c00( 236544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    820ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 2,  2] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  148(TIDL_ConvolutionLayer) [141, 148] --[512 x 20 x  12] => [256 x 20 x  12] *** [512] ***[ROW_L] ***[0, 0, 0, 252, 252]**** [1], [1],[1] -[147 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    820ea ||||  L2, DMA,    140(   320),    140(   320),  200(  512),  28000( 163840),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    aa16a 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,  112fc80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    28000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  149(TIDL_BatchNormLayer) [142, 149] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[148 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    aa16a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    aa16a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  150(TIDL_ResizeLayer) [143, 150] --[256 x 20 x  12] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 295, 295]**** [1], [0],[1] -[149 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,    aa16a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  151(TIDL_ConcatLayer) [144, 151] --[512 x 40 x  24] => [512 x 40 x  24] *** [512] ***[ COL] ***[0, 0, 0, 984, 984]**** [4], [0],[4] -[150 87 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  154(TIDL_ConvolutionLayer) [145, 154] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[84, 128, 128, 64, 1067]**** [15], [120],[120] -[151 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),   0,    aa156 ||||  L2, DMA,    100(   256),    100(   256),  200(  512),  20380( 131968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4842a( 295978),  2a,   2685d6 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),  100(  256), 120100(1179904),   0,  114fd80 ||||  L2, DMA,   1240(  4672),   1201(  4609),   44(   68),  4d900( 317696),   0,    20380 
 STG:MSMC, DMA,   1364(  4964),   1201(  4609),  100(  256), 136400(1270784),   0,   132180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  157(TIDL_BatchNormLayer) [146, 157] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[154 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4842a( 295978),  2a,   2685d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  159(TIDL_ResizeLayer) [147, 159] --[256 x 40 x  24] => [256 x 80 x  48] *** [256] ***[ COL] ***[0, 0, 0, 1067, 1067]**** [1], [0],[1] -[157 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,   1321d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,   1b422e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  162(TIDL_ConvolutionLayer) [148, 162] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3888]**** [6], [1],[6] -[159 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,   1b422e ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64c00( 412672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,  126fe80 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  165(TIDL_BatchNormLayer) [149, 165] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[162 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  161(TIDL_ConvolutionLayer) [150, 161] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3888]**** [6], [1],[6] -[159 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),  100(  256), 104052(1065042),  52,   1b422e ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64c00( 412672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1b422e 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,  1277f00 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  164(TIDL_BatchNormLayer) [151, 164] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[161 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1b422e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1b422e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  167(TIDL_ConvolutionLayer) [152, 167] --[128 x 80 x  48] => [64 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1344, 4051]**** [3], [1],[3] -[164 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,   1b422e ||||  L2, DMA,    b40(  2880),    b40(  2880),   80(  128),  5a580( 370048),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2362ae 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   40(   64),  12080(  73856),   0,  127ff80 ||||  L2, DMA,    4c0(  1216),    481(  1153),   40(   64),  13000(  77824),   0,    5a580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  169(TIDL_BatchNormLayer) [153, 169] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[167 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2362ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2362ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  171(TIDL_ConvolutionLayer) [154, 171] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ROW_L] ***[164, 192, 192, 3072, 4051]**** [2], [1],[2] -[169 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   2362ae ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  63000( 405504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   27732e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,  1292000 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  173(TIDL_BatchNormLayer) [155, 173] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[171 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   27732e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   27732e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  175(TIDL_ConvolutionLayer) [156, 175] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ROW_L] ***[164, 192, 192, 3072, 4051]**** [2], [1],[2] -[173 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   27732e ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  63000( 405504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2b83ae 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,  129b080 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  177(TIDL_BatchNormLayer) [157, 177] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[175 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2b83ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2b83ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  179(TIDL_ConvolutionLayer) [158, 179] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ROW_L] ***[164, 192, 192, 3072, 4051]**** [2], [1],[2] -[177 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   2b83ae ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  63000( 405504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2f942e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,  12a4100 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  181(TIDL_BatchNormLayer) [159, 181] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[179 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2f942e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2f942e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  183(TIDL_ConcatLayer) [160, 183] --[512 x 80 x  48] => [512 x 80 x  48] *** [512] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [256], [0],[256] -[165 164 169 173 177 181 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae ||||  L2, DMA,   1074(  4212),   1074(  4212),    4(    4),   4200(  16896),   0,        0 
 OUT:MSMC, CPU,    f40(  3904),    f30(  3888),    4(    4),   3d00(  15616),   0,   33a480 |||| DDR, DMA,    fd3(  4051),    fd3(  4051),  200(  512), 1faa52(2075218),  52,   1ed62e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  185(TIDL_ConvolutionLayer) [161, 185] --[512 x 80 x  48] => [128 x 80 x  48] *** [512] ***[ROW_L] ***[0, 0, 0, 320, 3888]**** [13], [1],[13] -[183 ]---
  IN: DDR, DMA,    fd3(  4051),    fd3(  4051),  200(  512), 1faa52(2075218),  52,   1ed62e ||||  L2, DMA,    2c0(   704),    2c0(   704),  200(  512),  58d80( 363904),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),   80(  128),  10080(  65664),   0,  12ad180 ||||  L2, DMA,    240(   576),    201(   513),   80(  128),  12000(  73728),   0,    58d80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  187(TIDL_BatchNormLayer) [162, 187] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[185 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,   1321ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  189(TIDL_ConvolutionLayer) [163, 189] --[128 x 80 x  48] => [64 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1344, 4051]**** [3], [1],[3] -[187 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,   1321ae ||||  L2, DMA,    b40(  2880),    b40(  2880),   80(  128),  5a580( 370048),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1321ae 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   40(   64),  12080(  73856),   0,  12bd200 ||||  L2, DMA,    4c0(  1216),    481(  1153),   40(   64),  13000(  77824),   0,    5a580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  193(TIDL_BatchNormLayer) [164, 193] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[189 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1321ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1321ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  197(TIDL_ResizeLayer) [165, 197] --[64 x 80 x  48] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 4051, 4051]**** [1], [0],[1] -[193 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   1321ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   17325e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  200(TIDL_ConvolutionLayer) [166, 200] --[64 x 160 x  96] => [32 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 3072, 15779]**** [6], [1],[6] -[197 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,   17325e ||||  L2, DMA,   19c0(  6592),   19c0(  6592),   40(   64),  6a000( 434176),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   13565e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   20(   32),   4880(  18560),   0,  12cf280 ||||  L2, DMA,    2c0(   704),    241(   577),   20(   32),   5800(  22528),   0,    6a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  203(TIDL_BatchNormLayer) [167, 203] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[200 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   13565e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   1321de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  207(TIDL_ResizeLayer) [168, 207] --[32 x 160 x  96] => [32 x 320 x  192] *** [32] ***[ COL] ***[0, 0, 0, 15779, 15779]**** [4], [0],[4] -[203 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),   0,   1321de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866), 142,   1ada3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  211(TIDL_ConvolutionLayer) [169, 211] --[32 x 320 x  192] => [16 x 320 x  192] *** [32] ***[ROW_L] ***[644, 704, 704, 5824, 62275]**** [11], [1],[11] -[207 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866),   0,   1ada3e ||||  L2, DMA,   3040( 12352),   3040( 12352),   20(   32),  6d500( 447744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,   1ada3e 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   10(   16),   1280(   4736),   0,  12d3b00 ||||  L2, DMA,    140(   320),    121(   289),   10(   16),   1400(   5120),   0,    6d500 
 STG:MSMC, DMA_ONCE,    140(   320),    121(   289),   10(   16),   1400(   5120),   0,   7b8380 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  214(TIDL_BatchNormLayer) [170, 214] --[16 x 320 x  192] => [16 x 320 x  192] *** [16] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [8], [0],[8] -[211 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,   1ada3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,   1ac03e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  218(TIDL_ConvolutionLayer) [171, 218] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ROW_L] ***[0, 0, 0, 12992, 61632]**** [5], [1],[5] -[214 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,   1ac03e ||||  L2, DMA,   65c0( 26048),   65c0( 26048),   10(   16),  6f400( 455680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be 
  WT:DDR_PERSIST, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,  12d4d80 ||||  L2, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,    6f400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  222(TIDL_BatchNormLayer) [172, 222] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[218 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  217(TIDL_ConvolutionLayer) [173, 217] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ROW_L] ***[0, 0, 0, 12992, 61632]**** [5], [1],[5] -[214 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,   1ac03e ||||  L2, DMA,   65c0( 26048),   65c0( 26048),   10(   16),  6f400( 455680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1ac03e 
  WT:DDR_PERSIST, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,  12d4e80 ||||  L2, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,    6f400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  221(TIDL_BatchNormLayer) [174, 221] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[217 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1ac03e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1ac03e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  225(TIDL_ConvolutionLayer) [175, 225] --[8 x 320 x  192] => [4 x 320 x  192] *** [8] ***[ROW_L] ***[644, 704, 704, 26432, 62275]**** [3], [1],[3] -[221 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266),   0,   1ac03e ||||  L2, DMA,   d140( 53568),   d140( 53568),    8(    8),  6f180( 455040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   225ebe 
  WT:DDR_PERSIST, DMA,     49(    73),     49(    73),    4(    4),    180(    384),   0,  12d4f80 ||||  L2, DMA,     c0(   192),     49(    73),    4(    4),    300(    768),   0,    6f180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  228(TIDL_BatchNormLayer) [176, 228] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[225 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   225ebe ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   225ebe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  231(TIDL_ConvolutionLayer) [177, 231] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ROW_L] ***[644, 704, 704, 56704, 62275]**** [2], [1],[2] -[228 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666),   0,   225ebe ||||  L2, DMA,  1bdc0(114112),  1bdc0(114112),    4(    4),  6f700( 456448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   262e3e 
  WT:DDR_PERSIST, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,  12d5100 ||||  L2, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,    6f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  234(TIDL_BatchNormLayer) [178, 234] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[231 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   262e3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   262e3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  239(TIDL_ConvolutionLayer) [179, 239] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ROW_L] ***[644, 704, 704, 56704, 62275]**** [2], [1],[2] -[234 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666),   0,   262e3e ||||  L2, DMA,  1bdc0(114112),  1bdc0(114112),    4(    4),  6f700( 456448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   29fdbe 
  WT:DDR_PERSIST, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,  12d5200 ||||  L2, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,    6f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  244(TIDL_BatchNormLayer) [180, 244] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[239 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   29fdbe ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   29fdbe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  250(TIDL_ConvolutionLayer) [181, 250] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ROW_L] ***[644, 704, 704, 56704, 62275]**** [2], [1],[2] -[244 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666),   0,   29fdbe ||||  L2, DMA,  1bdc0(114112),  1bdc0(114112),    4(    4),  6f700( 456448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   2dcd3e 
  WT:DDR_PERSIST, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,  12d5300 ||||  L2, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,    6f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  255(TIDL_BatchNormLayer) [182, 255] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[250 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   2dcd3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   2dcd3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  263(TIDL_ConcatLayer) [183, 263] --[32 x 320 x  192] => [32 x 320 x  192] *** [32] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [16], [0],[16] -[222 221 228 234 244 255 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866), 142,   319cbe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  272(TIDL_ConvolutionLayer) [184, 272] --[32 x 320 x  192] => [8 x 320 x  192] *** [32] ***[ROW_L] ***[0, 0, 0, 6272, 61632]**** [10], [1],[10] -[263 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866), 142,   319cbe ||||  L2, DMA,   3140( 12608),   3140( 12608),   20(   32),  6ec00( 453632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be 
  WT:DDR_PERSIST, DMA,     21(    33),     21(    33),    8(    8),    180(    384),   0,  12d5400 ||||  L2, DMA,     21(    33),     21(    33),    8(    8),    180(    384),   0,    6ec00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  282(TIDL_BatchNormLayer) [185, 282] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[272 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,   1321be 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  288(TIDL_ResizeLayer) [186, 288] --[8 x 320 x  192] => [8 x 640 x  384] *** [8] ***[ COL] ***[0, 0, 0, 62275, 62275]**** [4], [0],[4] -[282 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266),   0,   1321be ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    8(    8), 1e3602(1979906), 282,   1ac07e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  293(TIDL_ConvolutionLayer) [187, 293] --[8 x 640 x  384] => [2 x 640 x  384] *** [8] ***[ROW_L] ***[1284, 1344, 1344, 13440, 247427]**** [19], [1],[19] -[288 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    8(    8), 1e3602(1979906),   0,   1ac07e ||||  L2, DMA,   6e40( 28224),   6e40( 28224),    8(    8),  6ee80( 454272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,   1321fe 
  WT:DDR_PERSIST, DMA,     49(    73),     49(    73),    2(    2),    100(    256),   0,  12d5580 ||||  L2, DMA,     c0(   192),     49(    73),    2(    2),    180(    384),   0,    6ee80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  299(TIDL_BatchNormLayer) [188, 299] --[2 x 640 x  384] => [2 x 640 x  384] *** [2] ***[ COL] ***[0, 0, 0, 123072, 246144]**** [4], [0],[4] -[293 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,   1321fe ||||  L2, DMA,  3c180(246144),  3c180(246144),    1(    1),  3c180( 246144),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,   1321fe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  304(TIDL_BatchNormLayer) [189, 304] --[2 x 640 x  384] => [2 x 640 x  384] *** [2] ***[ COL] ***[0, 0, 0, 123072, 246144]**** [4], [0],[4] -[299 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,   1321fe ||||  L2, DMA,  3c180(246144),  3c180(246144),    1(    1),  3c180( 246144),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,   1321fe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  308(TIDL_DataConvertLayer) [190, 308] --[2 x 640 x  384] => [2 x 640 x  384] *** [2] ***[ COL] ***[0, 0, 0, 61536, 246144]**** [8], [0],[8] -[304 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,   1321fe ||||  L2, DMA,  1e0c0(123072),  1e0c0(123072),    1(    1),  1e100( 123136),   0,        0 
 OUT:MSMC, CPU,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,   1aaf80 |||| DDR, DMA,  f0000(983040),  f0000(983040),    2(    2), 1e0400(1967104),   0,   1ed600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  153(TIDL_ConvolutionLayer) [192, 153] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 984]**** [4], [1],[4] -[151 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,    aa156 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,  12d5680 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  156(TIDL_BatchNormLayer) [193, 156] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[153 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  152(TIDL_ConvolutionLayer) [194, 152] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 984]**** [4], [1],[4] -[151 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,    aa156 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,  12f5780 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  155(TIDL_BatchNormLayer) [195, 155] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[152 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  158(TIDL_ConvolutionLayer) [196, 158] --[256 x 40 x  24] => [128 x 40 x  24] *** [256] ***[ROW_L] ***[84, 128, 128, 192, 1067]**** [5], [1],[5] -[155 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,    aa156 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    ee1d6 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),   80(  128),  48080( 295040),   0,  1315880 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  160(TIDL_BatchNormLayer) [197, 160] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[158 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    ee1d6 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    ee1d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  163(TIDL_ConvolutionLayer) [198, 163] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[84, 128, 128, 939, 1067]**** [1], [1],[1] -[160 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,    ee1d6 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   176256 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  135d900 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    22000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  166(TIDL_BatchNormLayer) [199, 166] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[163 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   176256 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   176256 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  168(TIDL_ConvolutionLayer) [200, 168] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[84, 128, 128, 939, 1067]**** [1], [1],[1] -[166 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,   176256 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   1982d6 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  1381980 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    22000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  170(TIDL_BatchNormLayer) [201, 170] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[168 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   1982d6 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   1982d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  172(TIDL_ConvolutionLayer) [202, 172] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[84, 128, 128, 939, 1067]**** [1], [1],[1] -[170 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,   1982d6 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   1ba356 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  13a5a00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    22000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  174(TIDL_BatchNormLayer) [203, 174] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[172 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   1ba356 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   1ba356 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  176(TIDL_ConcatLayer) [204, 176] --[1024 x 40 x  24] => [1024 x 40 x  24] *** [1024] ***[ COL] ***[0, 0, 0, 984, 984]**** [1024], [0],[1024] -[156 155 160 166 170 174 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,   1321d6 ||||  L2, DMA,    453(  1107),    453(  1107),    2(    2),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   1dc3d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  178(TIDL_ConvolutionLayer) [205, 178] --[1024 x 40 x  24] => [256 x 40 x  24] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 984]**** [16], [1],[16] -[176 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   1dc3d6 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20380( 131968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,  13c9a80 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20380 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  180(TIDL_BatchNormLayer) [206, 180] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[178 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  0],  To fill zero OUT: [ 0,  0]
------  182(TIDL_ConvolutionLayer) [207, 182] --[256 x 40 x  24] => [128 x 40 x  24] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 984]**** [2], [1],[2] -[180 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    ee1d6 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,  1409b80 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  184(TIDL_BatchNormLayer) [208, 184] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[182 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    ee1d6 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   170256 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  186(TIDL_ResizeLayer) [209, 186] --[128 x 40 x  24] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 1067, 1067]**** [1], [0],[1] -[184 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,   170256 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    ee1ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  188(TIDL_ConcatLayer) [210, 188] --[256 x 80 x  48] => [256 x 80 x  48] *** [256] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [8], [0],[8] -[186 62 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    ee1ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:MSMC, CPU,    f40(  3904),    f30(  3888),   40(   64),  3d000( 249856),   0,   170200 |||| DDR, DMA,    fd3(  4051),    fd3(  4051),  100(  256),  fd752(1038162),  52,   1ed62e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  191(TIDL_ConvolutionLayer) [211, 191] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3888]**** [6], [1],[6] -[188 ]---
  IN: DDR, DMA,    fd3(  4051),    fd3(  4051),  100(  256),  fd752(1038162),  52,   1ed62e ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64c00( 412672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,  1411c00 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  195(TIDL_BatchNormLayer) [212, 195] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[191 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  190(TIDL_ConvolutionLayer) [213, 190] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 3888]**** [6], [1],[6] -[188 ]---
  IN: DDR, DMA,    fd3(  4051),    fd3(  4051),  100(  256),  fd752(1038162),  52,   1ed62e ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64c00( 412672),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    ee1ae 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,  1419c80 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    64c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  194(TIDL_BatchNormLayer) [214, 194] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[190 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    ee1ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    ee1ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  198(TIDL_ConvolutionLayer) [215, 198] --[128 x 80 x  48] => [64 x 80 x  48] *** [128] ***[ROW_L] ***[164, 192, 192, 1344, 4051]**** [3], [1],[3] -[194 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,    ee1ae ||||  L2, DMA,    b40(  2880),    b40(  2880),   80(  128),  5a580( 370048),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   17022e 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   40(   64),  12080(  73856),   0,  1421d00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   40(   64),  13000(  77824),   0,    5a580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  201(TIDL_BatchNormLayer) [216, 201] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[198 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   17022e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   17022e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  204(TIDL_ConvolutionLayer) [217, 204] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ROW_L] ***[164, 192, 192, 3072, 4051]**** [2], [1],[2] -[201 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   17022e ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  63000( 405504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1b12ae 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,  1433d80 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  208(TIDL_BatchNormLayer) [218, 208] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[204 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1b12ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1b12ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  212(TIDL_ConvolutionLayer) [219, 212] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ROW_L] ***[164, 192, 192, 3072, 4051]**** [2], [1],[2] -[208 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   1b12ae ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  63000( 405504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1f232e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,  143ce00 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  215(TIDL_BatchNormLayer) [220, 215] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[212 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1f232e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   1f232e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  219(TIDL_ConvolutionLayer) [221, 219] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ROW_L] ***[164, 192, 192, 3072, 4051]**** [2], [1],[2] -[215 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),   0,   1f232e ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  63000( 405504),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2333ae 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,  1445e80 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    63000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  223(TIDL_BatchNormLayer) [222, 223] --[64 x 80 x  48] => [64 x 80 x  48] *** [64] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[219 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2333ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   40(   64),  41052( 266322),  52,   2333ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  226(TIDL_ConcatLayer) [223, 226] --[512 x 80 x  48] => [512 x 80 x  48] *** [512] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [256], [0],[256] -[195 194 201 208 215 223 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),    4(    4),   4200(  16896),   0,        0 
 OUT:MSMC, CPU,    f40(  3904),    f30(  3888),    4(    4),   3d00(  15616),   0,   274400 |||| DDR, DMA,    fd3(  4051),    fd3(  4051),  200(  512), 1faa52(2075218),  52,   2eadae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  229(TIDL_ConvolutionLayer) [224, 229] --[512 x 80 x  48] => [128 x 80 x  48] *** [512] ***[ROW_L] ***[0, 0, 0, 320, 3888]**** [13], [1],[13] -[226 ]---
  IN: DDR, DMA,    fd3(  4051),    fd3(  4051),  200(  512), 1faa52(2075218),  52,   2eadae ||||  L2, DMA,    2c0(   704),    2c0(   704),  200(  512),  58d80( 363904),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),   80(  128),  10080(  65664),   0,  144ef00 ||||  L2, DMA,    240(   576),    201(   513),   80(  128),  12000(  73728),   0,    58d80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  232(TIDL_BatchNormLayer) [225, 232] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[229 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  237(TIDL_ConvolutionLayer) [226, 237] --[128 x 80 x  48] => [192 x 80 x  48] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 3888]**** [3], [1],[3] -[232 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  66600( 419328),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   c0(  192),   6100(  24832),   0,  145ef80 ||||  L2, DMA,     c0(   192),     81(   129),   c0(  192),   9000(  36864),   0,    66600 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  242(TIDL_BatchNormLayer) [227, 242] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[237 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   60(   96),  62b80( 404352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  248(TIDL_ConvolutionLayer) [228, 248] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ROW_L] ***[164, 192, 192, 128, 4051]**** [31], [1],[31] -[242 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),   0,    ee1ae ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15e80(  89728),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1465080 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15e80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  253(TIDL_BatchNormLayer) [229, 253] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[248 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e ||||  L2, DMA,   1074(  4212),   1074(  4212),   60(   96),  62b80( 404352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  258(TIDL_ConvolutionLayer) [230, 258] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ROW_L] ***[164, 192, 192, 128, 4051]**** [31], [1],[31] -[253 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),   0,   1b122e ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15e80(  89728),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  14b6180 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15e80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  267(TIDL_BatchNormLayer) [231, 267] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[258 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e ||||  L2, DMA,   1074(  4212),   1074(  4212),   60(   96),  62b80( 404352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  277(TIDL_ConvolutionLayer) [232, 277] --[192 x 80 x  48] => [1 x 80 x  48] *** [192] ***[ROW_L] ***[0, 0, 0, 1088, 3888]**** [4], [1],[4] -[267 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,   1b122e ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   c0(  192),  69880( 432256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),    1(    1),   10d2(   4306),  52,   1b122e 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    1(    1),    100(    256),   0,  1507280 ||||  L2, DMA,    140(   320),     c1(   193),    1(    1),    180(    384),   0,    69880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  285(TIDL_BatchNormLayer) [233, 285] --[1 x 80 x  48] => [1 x 80 x  48] *** [1] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[277 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),    1(    1),   10d2(   4306),  52,   1b122e ||||  L2, DMA,   1074(  4212),   1074(  4212),    1(    1),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),    1(    1),   10d2(   4306),  52,   1b122e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  247(TIDL_ConvolutionLayer) [234, 247] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ROW_L] ***[164, 192, 192, 128, 4051]**** [31], [1],[31] -[242 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),   0,    ee1ae ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15e80(  89728),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1507380 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15e80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  252(TIDL_BatchNormLayer) [235, 252] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[247 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   60(   96),  62b80( 404352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  257(TIDL_ConvolutionLayer) [236, 257] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ROW_L] ***[164, 192, 192, 128, 4051]**** [31], [1],[31] -[252 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),   0,    ee1ae ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15e80(  89728),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1558480 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15e80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  266(TIDL_BatchNormLayer) [237, 266] --[192 x 80 x  48] => [192 x 80 x  48] *** [192] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[257 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae ||||  L2, DMA,   1074(  4212),   1074(  4212),   60(   96),  62b80( 404352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  275(TIDL_ConvolutionLayer) [238, 275] --[192 x 80 x  48] => [1 x 80 x  48] *** [192] ***[ROW_L] ***[0, 0, 0, 1088, 3888]**** [4], [1],[4] -[266 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   c0(  192),  69880( 432256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),    1(    1),   10d2(   4306),  52,   1b232e 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    1(    1),    100(    256),   0,  15a9580 ||||  L2, DMA,    140(   320),     c1(   193),    1(    1),    180(    384),   0,    69880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  284(TIDL_BatchNormLayer) [239, 284] --[1 x 80 x  48] => [1 x 80 x  48] *** [1] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [1], [0],[1] -[275 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),    1(    1),   10d2(   4306),  52,   1b232e ||||  L2, DMA,   1074(  4212),   1074(  4212),    1(    1),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),    1(    1),   10d2(   4306),  52,   1b232e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  276(TIDL_ConvolutionLayer) [240, 276] --[192 x 80 x  48] => [4 x 80 x  48] *** [192] ***[ROW_L] ***[0, 0, 0, 1088, 3888]**** [4], [1],[4] -[266 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   c0(  192),  c3052( 798802),  52,    ee1ae ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   c0(  192),  69880( 432256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),    4(    4),   4152(  16722),  52,    f432e 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    4(    4),    380(    896),   0,  15a9680 ||||  L2, DMA,    140(   320),     c1(   193),    4(    4),    500(   1280),   0,    69880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  290(TIDL_ConcatLayer) [241, 290] --[6 x 80 x  48] => [6 x 80 x  48] *** [6] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [6], [0],[6] -[276 284 285 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),    4(    4),   4152(  16722),  52,    f432e ||||  L2, DMA,   1023(  4131),   1023(  4131),    2(    2),   2080(   8320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    f00(  3840),    f00(  3840),    6(    6),   5a00(  23040),   0,    ee180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  296(TIDL_DataConvertLayer) [242, 296] --[6 x 80 x  48] => [6 x 80 x  48] *** [6] ***[ COL] ***[0, 0, 0, 3840, 3840]**** [1], [0],[1] -[290 ]---
  IN:MSMC, DMA,    f00(  3840),    f00(  3840),    6(    6),   5a00(  23040),   0,    ee180 ||||  L2, DMA,    f00(  3840),    f00(  3840),    6(    6),   5a00(  23040),   0,        0 
 OUT:MSMC, CPU,   3c00( 15360),   3c00( 15360),    6(    6),  16800(  92160),   0,    f3b80 |||| DDR, DMA,   3c00( 15360),   3c00( 15360),    6(    6),  16c00(  93184),   0,   2ead80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  295(TIDL_ReshapeLayer) [244, 295] --[6 x 80 x  48] => [1 x 3840 x  6] *** [6] ***[ COL] ***[0, 0, 0, 3840, 3840]**** [1], [0],[1] -[290 ]---
  IN:MSMC, DMA,    f00(  3840),    f00(  3840),    6(    6),   5a00(  23040),   0,    ee180 ||||  L2, DMA,    f00(  3840),    f00(  3840),    6(    6),   5a00(  23040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   5a00( 23040),   5a00( 23040),    1(    1),   5a00(  23040),   0,    ee180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  235(TIDL_ConvolutionLayer) [245, 235] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 3888]**** [3], [1],[3] -[232 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  66600( 419328),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    f3bae 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   80(  128),   4080(  16512),   0,  15a9a00 ||||  L2, DMA,     c0(   192),     81(   129),   80(  128),   6000(  24576),   0,    66600 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  240(TIDL_BatchNormLayer) [246, 240] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[235 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    f3bae ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,    f3bae 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  245(TIDL_ConvolutionLayer) [247, 245] --[128 x 80 x  48] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[82, 82, 82, 972, 3970]**** [4], [1],[4] -[240 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,    f3bae ||||  L2, DMA,    840(  2112),    840(  2112),   80(  128),  42780( 272256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    3c1(   961),   80(  128),  22000( 139264),   0,   175c00 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  15ada80 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    42780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  251(TIDL_BatchNormLayer) [248, 251] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 960, 960]**** [1], [0],[1] -[245 ]---
  IN:MSMC, DMA,    440(  1088),    3c1(   961),   80(  128),  22000( 139264),   0,   175c00 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,    f3b80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  236(TIDL_PoolingLayer) [249, 236] --[128 x 80 x  48] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[232 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,   111b80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  241(TIDL_ConvolutionLayer) [250, 241] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[0, 0, 0, 960, 960]**** [1], [1],[1] -[236 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,   111b80 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,       80 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   80(  128),   4080(  16512),   0,  15d1b00 ||||  L2, DMA,     c0(   192),     81(   129),   80(  128),   6000(  24576),   0,    1e000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  246(TIDL_BatchNormLayer) [251, 246] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 960, 960]**** [1], [0],[1] -[241 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,       80 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),   0,       80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  256(TIDL_ConcatLayer) [252, 256] --[512 x 40 x  24] => [512 x 40 x  24] *** [512] ***[ COL] ***[0, 0, 0, 984, 984]**** [512], [0],[512] -[246 251 180 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),   80(  128),  1e000( 122880),  2a,       80 ||||  L2, DMA,    453(  1107),    453(  1107),    2(    2),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,   111bd6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  265(TIDL_ConvolutionLayer) [253, 265] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 984]**** [4], [1],[4] -[256 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,   111bd6 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,       56 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,  15d5b80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  274(TIDL_BatchNormLayer) [254, 274] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[265 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,       56 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,       56 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  264(TIDL_ConvolutionLayer) [255, 264] --[512 x 40 x  24] => [256 x 40 x  24] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 984]**** [4], [1],[4] -[256 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  200(  512),  8802a( 557098),  2a,   111bd6 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48200( 295424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,  15f5c80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  273(TIDL_BatchNormLayer) [256, 273] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[264 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  283(TIDL_ConvolutionLayer) [257, 283] --[256 x 40 x  24] => [128 x 40 x  24] *** [256] ***[ROW_L] ***[84, 128, 128, 192, 1067]**** [5], [1],[5] -[273 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,    aa156 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    440d6 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),   80(  128),  48080( 295040),   0,  1615d80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  289(TIDL_BatchNormLayer) [258, 289] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[283 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    440d6 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    440d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  294(TIDL_ConvolutionLayer) [259, 294] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[84, 128, 128, 939, 1067]**** [1], [1],[1] -[289 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,    440d6 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    f3bd6 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  165de00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    22000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  300(TIDL_BatchNormLayer) [260, 300] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[294 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    f3bd6 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,    f3bd6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  305(TIDL_ConvolutionLayer) [261, 305] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[84, 128, 128, 939, 1067]**** [1], [1],[1] -[300 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,    f3bd6 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   115c56 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  1681e80 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    22000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  309(TIDL_BatchNormLayer) [262, 309] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[305 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   115c56 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   115c56 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  313(TIDL_ConvolutionLayer) [263, 313] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ROW_L] ***[84, 128, 128, 939, 1067]**** [1], [1],[1] -[309 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),   0,   115c56 ||||  L2, DMA,    440(  1088),    440(  1088),   80(  128),  22000( 139264),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   137cd6 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,  16a5f00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    22000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  316(TIDL_BatchNormLayer) [264, 316] --[128 x 40 x  24] => [128 x 40 x  24] *** [128] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[313 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   137cd6 ||||  L2, DMA,    453(  1107),    453(  1107),   80(  128),  22980( 141696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   80(  128),  2202a( 139306),  2a,   137cd6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  319(TIDL_ConcatLayer) [265, 319] --[1024 x 40 x  24] => [1024 x 40 x  24] *** [1024] ***[ COL] ***[0, 0, 0, 984, 984]**** [1024], [0],[1024] -[274 273 289 300 309 316 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,       56 ||||  L2, DMA,    453(  1107),    453(  1107),    2(    2),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   159d56 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  321(TIDL_ConvolutionLayer) [266, 321] --[1024 x 40 x  24] => [256 x 40 x  24] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 984]**** [16], [1],[16] -[319 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  400( 1024), 11002a(1114154),  2a,   159d56 ||||  L2, DMA,     80(   128),     80(   128),  400( 1024),  20380( 131968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,     16d6 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  100(  256),  40100( 262400),   0,  16c9f80 ||||  L2, DMA,    440(  1088),    401(  1025),  100(  256),  44000( 278528),   0,    20380 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  323(TIDL_BatchNormLayer) [267, 323] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[321 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,     16d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,     16d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  327(TIDL_ConvolutionLayer) [268, 327] --[256 x 40 x  24] => [192 x 40 x  24] *** [256] ***[ROW_L] ***[0, 0, 0, 704, 984]**** [2], [1],[2] -[323 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,     16d6 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),  100(  256),  5c000( 376832),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   c0(  192),   c100(  49408),   0,  170a080 ||||  L2, DMA,    140(   320),    101(   257),   c0(  192),   f000(  61440),   0,    5c000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  331(TIDL_BatchNormLayer) [269, 331] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[327 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 ||||  L2, DMA,    453(  1107),    453(  1107),   c0(  192),  33e80( 212608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  336(TIDL_ConvolutionLayer) [270, 336] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ROW_L] ***[84, 128, 128, 128, 1067]**** [8], [1],[8] -[331 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),   0,    45756 ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15300(  86784),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1716180 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  340(TIDL_BatchNormLayer) [271, 340] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[336 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 ||||  L2, DMA,    453(  1107),    453(  1107),   c0(  192),  33e80( 212608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  344(TIDL_ConvolutionLayer) [272, 344] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ROW_L] ***[84, 128, 128, 128, 1067]**** [8], [1],[8] -[340 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),   0,    aa156 ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15300(  86784),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1767280 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  349(TIDL_BatchNormLayer) [273, 349] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[344 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 ||||  L2, DMA,    453(  1107),    453(  1107),   c0(  192),  33e80( 212608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  0],  To fill zero OUT: [ 0,  0]
------  356(TIDL_ConvolutionLayer) [274, 356] --[192 x 40 x  24] => [1 x 40 x  24] *** [192] ***[ROW_L] ***[0, 0, 0, 984, 984]**** [1], [1],[1] -[349 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    aa156 ||||  L2, DMA,    440(  1088),    440(  1088),   c0(  192),  33000( 208896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),    1(    1),    4aa(   1194),  2a,       56 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    1(    1),    100(    256),   0,  17b8380 ||||  L2, DMA,    140(   320),     c1(   193),    1(    1),    180(    384),   0,    33000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  361(TIDL_BatchNormLayer) [275, 361] --[1 x 40 x  24] => [1 x 40 x  24] *** [1] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[356 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),    1(    1),    4aa(   1194),  2a,       56 ||||  L2, DMA,    453(  1107),    453(  1107),    1(    1),    480(   1152),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),    1(    1),    4aa(   1194),  2a,    787d6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  335(TIDL_ConvolutionLayer) [276, 335] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ROW_L] ***[84, 128, 128, 128, 1067]**** [8], [1],[8] -[331 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),   0,    45756 ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15300(  86784),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  17b8480 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  339(TIDL_BatchNormLayer) [277, 339] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[335 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 ||||  L2, DMA,    453(  1107),    453(  1107),   c0(  192),  33e80( 212608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  343(TIDL_ConvolutionLayer) [278, 343] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ROW_L] ***[84, 128, 128, 128, 1067]**** [8], [1],[8] -[339 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),   0,    45756 ||||  L2, DMA,    1c0(   448),    1c0(   448),   c0(  192),  15300(  86784),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1809580 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,    15300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  348(TIDL_BatchNormLayer) [279, 348] --[192 x 40 x  24] => [192 x 40 x  24] *** [192] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[343 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 ||||  L2, DMA,    453(  1107),    453(  1107),   c0(  192),  33e80( 212608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  354(TIDL_ConvolutionLayer) [280, 354] --[192 x 40 x  24] => [1 x 40 x  24] *** [192] ***[ROW_L] ***[0, 0, 0, 984, 984]**** [1], [1],[1] -[348 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 ||||  L2, DMA,    440(  1088),    440(  1088),   c0(  192),  33000( 208896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),    1(    1),    4aa(   1194),  2a,       56 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    1(    1),    100(    256),   0,  185a680 ||||  L2, DMA,    140(   320),     c1(   193),    1(    1),    180(    384),   0,    33000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  360(TIDL_BatchNormLayer) [281, 360] --[1 x 40 x  24] => [1 x 40 x  24] *** [1] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[354 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),    1(    1),    4aa(   1194),  2a,       56 ||||  L2, DMA,    453(  1107),    453(  1107),    1(    1),    480(   1152),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),    1(    1),    4aa(   1194),  2a,    78cd6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  355(TIDL_ConvolutionLayer) [282, 355] --[192 x 40 x  24] => [4 x 40 x  24] *** [192] ***[ROW_L] ***[0, 0, 0, 984, 984]**** [1], [1],[1] -[348 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),   c0(  192),  3302a( 208938),  2a,    45756 ||||  L2, DMA,    440(  1088),    440(  1088),   c0(  192),  33000( 208896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),    4(    4),   112a(   4394),  2a,    45756 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    4(    4),    380(    896),   0,  185a780 ||||  L2, DMA,    140(   320),     c1(   193),    4(    4),    500(   1280),   0,    33000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  364(TIDL_ConcatLayer) [283, 364] --[6 x 40 x  24] => [6 x 40 x  24] *** [6] ***[ COL] ***[0, 0, 0, 984, 984]**** [6], [0],[6] -[355 360 361 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),    4(    4),   112a(   4394),  2a,    45756 ||||  L2, DMA,    453(  1107),    453(  1107),    2(    2),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    3c0(   960),    3c0(   960),    6(    6),   1680(   5760),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  368(TIDL_DataConvertLayer) [284, 368] --[6 x 40 x  24] => [6 x 40 x  24] *** [6] ***[ COL] ***[0, 0, 0, 960, 960]**** [1], [0],[1] -[364 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),    6(    6),   1680(   5760),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),    6(    6),   1680(   5760),   0,        0 
 OUT:MSMC, CPU,    f00(  3840),    f00(  3840),    6(    6),   5a00(  23040),   0,    45700 |||| DDR, DMA,    f00(  3840),    f00(  3840),    6(    6),   5e00(  24064),   0,   2ead80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  367(TIDL_ReshapeLayer) [286, 367] --[6 x 40 x  24] => [1 x 960 x  6] *** [6] ***[ COL] ***[0, 0, 0, 960, 960]**** [1], [0],[1] -[364 ]---
  IN:MSMC, DMA,    3c0(   960),    3c0(   960),    6(    6),   1680(   5760),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),    6(    6),   1680(   5760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1680(  5760),   1680(  5760),    1(    1),   1680(   5760),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  325(TIDL_ConvolutionLayer) [287, 325] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ROW_L] ***[0, 0, 0, 640, 984]**** [2], [1],[2] -[323 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,     16d6 ||||  L2, DMA,    540(  1344),    540(  1344),  100(  256),  54000( 344064),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    f3bd6 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),  100(  256),  10100(  65792),   0,  185ab00 ||||  L2, DMA,    140(   320),    101(   257),  100(  256),  14000(  81920),   0,    54000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  329(TIDL_BatchNormLayer) [288, 329] --[256 x 40 x  24] => [256 x 40 x  24] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[325 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    f3bd6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,    aa156 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  333(TIDL_ConvolutionLayer) [289, 333] --[256 x 40 x  24] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[42, 42, 42, 246, 1026]**** [4], [16],[16] -[329 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),   0,    aa156 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24200( 147968),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f1(   241),  100(  256),  14000(  81920),   0,    45700 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,  186ac00 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24200 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  338(TIDL_BatchNormLayer) [290, 338] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[333 ]---
  IN:MSMC, DMA,    140(   320),     f1(   241),  100(  256),  14000(  81920),   0,    45700 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    f3b80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  326(TIDL_PoolingLayer) [291, 326] --[256 x 40 x  24] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 984, 984]**** [1], [0],[1] -[323 ]---
  IN:MSMC, DMA,    440(  1088),    42b(  1067),  100(  256),  4402a( 278570),  2a,     16d6 ||||  L2, DMA,    453(  1107),    453(  1107),  100(  256),  45300( 283392),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    45700 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  330(TIDL_ConvolutionLayer) [292, 330] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[0, 0, 0, 240, 240]**** [1], [1],[1] -[326 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,    45700 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,     1700 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),  100(  256),  10100(  65792),   0,  18fad00 ||||  L2, DMA,    140(   320),    101(   257),  100(  256),  14000(  81920),   0,    14000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  334(TIDL_BatchNormLayer) [293, 334] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[330 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,     1700 ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),     f0(   240),  100(  256),  14000(  81920),   0,     1680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  342(TIDL_ConcatLayer) [294, 342] --[1024 x 20 x  12] => [1024 x 20 x  12] *** [1024] ***[ COL] ***[0, 0, 0, 252, 252]**** [512], [0],[512] -[334 338 147 ]---
  IN:MSMC, DMA,    140(   320),     f0(   240),  100(  256),  14000(  81920),  16,     1680 ||||  L2, DMA,    150(   336),    150(   336),    4(    4),    580(   1408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  400( 1024),  50016( 327702),  16,    2976a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  347(TIDL_ConvolutionLayer) [295, 347] --[1024 x 20 x  12] => [512 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 252]**** [4], [32],[32] -[342 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  400( 1024),  50016( 327702),  16,    2976a ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  200(  512),  80200( 524800),   0,  190ae00 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30080 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  200(  512),  88000( 557056),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  353(TIDL_BatchNormLayer) [296, 353] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[347 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  346(TIDL_ConvolutionLayer) [297, 346] --[1024 x 20 x  12] => [512 x 20 x  12] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 252]**** [4], [32],[32] -[342 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  400( 1024),  50016( 327702),  16,    2976a ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30080( 196736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    2976a 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  200(  512),  80200( 524800),   0,  198b000 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30080 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  200(  512),  88000( 557056),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  352(TIDL_BatchNormLayer) [298, 352] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[346 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    2976a ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,    2976a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  359(TIDL_ConvolutionLayer) [299, 359] --[512 x 20 x  12] => [256 x 20 x  12] *** [512] ***[ROW_L] ***[44, 64, 64, 64, 295]**** [4], [28],[28] -[352 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),   0,    2976a ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18080(  98432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  17c16(  97302),  16,    517ea 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),  100(  256), 120100(1179904),   0,  1a0b200 ||||  L2, DMA,   1240(  4672),   1201(  4609),   4c(   76),  56b00( 355072),   0,    18080 
 STG:MSMC, DMA,   15ac(  5548),   1201(  4609),  100(  256), 15ac00(1420288),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  363(TIDL_BatchNormLayer) [300, 363] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[359 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  17c16(  97302),  16,    517ea ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    517ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  366(TIDL_ConvolutionLayer) [301, 366] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[363 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,    517ea ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    6586a 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,  1b2b300 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  370(TIDL_BatchNormLayer) [302, 370] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[366 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    6586a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    6586a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  373(TIDL_ConvolutionLayer) [303, 373] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[370 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,    6586a ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    798ea 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,  1bbb400 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  375(TIDL_BatchNormLayer) [304, 375] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[373 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    798ea ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    798ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  377(TIDL_ConvolutionLayer) [305, 377] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [4],[4] -[375 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),   0,    798ea ||||  L2, DMA,    140(   320),    140(   320),  100(  256),  14000(  81920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    8d96a 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,  1c4b500 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    14000 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    f3b80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  379(TIDL_BatchNormLayer) [306, 379] --[256 x 20 x  12] => [256 x 20 x  12] *** [256] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[377 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    8d96a ||||  L2, DMA,    150(   336),    150(   336),  100(  256),  15000(  86016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  100(  256),  14016(  81942),  16,    8d96a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  381(TIDL_ConcatLayer) [307, 381] --[2048 x 20 x  12] => [2048 x 20 x  12] *** [2048] ***[ COL] ***[0, 0, 0, 252, 252]**** [1024], [0],[1024] -[353 352 363 370 375 379 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea ||||  L2, DMA,    150(   336),    150(   336),    4(    4),    580(   1408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  800( 2048),  a0016( 655382),  16,    f3bea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  383(TIDL_ConvolutionLayer) [308, 383] --[2048 x 20 x  12] => [512 x 20 x  12] *** [2048] ***[ROW_L] ***[0, 0, 0, 64, 252]**** [4], [48],[48] -[381 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  800( 2048),  a0016( 655382),  16,    f3bea ||||  L2, DMA,     80(   128),     80(   128),  800( 2048),  40080( 262272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea 
  WT:DDR_PERSIST, DMA,    801(  2049),    801(  2049),  200(  512), 100200(1049088),   0,  1cdb600 ||||  L2, DMA,    840(  2112),    801(  2049),   5c(   92),  2f700( 194304),   0,    40080 
 STG:MSMC, DMA,    8e5(  2277),    801(  2049),  200(  512), 11ca00(1165824),   0,   193c00 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  385(TIDL_BatchNormLayer) [309, 385] --[512 x 20 x  12] => [512 x 20 x  12] *** [512] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[383 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea ||||  L2, DMA,    150(   336),    150(   336),  200(  512),  2a000( 172032),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  387(TIDL_ConvolutionLayer) [310, 387] --[512 x 20 x  12] => [192 x 20 x  12] *** [512] ***[ROW_L] ***[0, 0, 0, 252, 252]**** [1], [1],[1] -[385 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),  200(  512),  28016( 163862),  16,     16ea ||||  L2, DMA,    140(   320),    140(   320),  200(  512),  28000( 163840),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),   c0(  192),  18100(  98560),   0,  1ddb800 ||||  L2, DMA,    240(   576),    201(   513),   c0(  192),  1b000( 110592),   0,    28000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  392(TIDL_BatchNormLayer) [311, 392] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[387 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea ||||  L2, DMA,    150(   336),    150(   336),   c0(  192),   fc00(  64512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  398(TIDL_ConvolutionLayer) [312, 398] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [1],[1] -[392 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),   0,     16ea ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1df3900 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  404(TIDL_BatchNormLayer) [313, 404] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[398 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a ||||  L2, DMA,    150(   336),    150(   336),   c0(  192),   fc00(  64512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  408(TIDL_ConvolutionLayer) [314, 408] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [1],[1] -[404 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),   0,    1076a ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1e44a00 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  412(TIDL_BatchNormLayer) [315, 412] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[408 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a ||||  L2, DMA,    150(   336),    150(   336),   c0(  192),   fc00(  64512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  417(TIDL_ConvolutionLayer) [316, 417] --[192 x 20 x  12] => [1 x 20 x  12] *** [192] ***[ROW_L] ***[0, 0, 0, 252, 252]**** [1], [1],[1] -[412 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,    1076a ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),    1(    1),    196(    406),  16,    1076a 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    1(    1),    100(    256),   0,  1e95b00 ||||  L2, DMA,    140(   320),     c1(   193),    1(    1),    180(    384),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  421(TIDL_BatchNormLayer) [317, 421] --[1 x 20 x  12] => [1 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[417 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),    1(    1),    196(    406),  16,    1076a ||||  L2, DMA,    150(   336),    150(   336),    1(    1),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),    1(    1),    196(    406),  16,    1076a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  397(TIDL_ConvolutionLayer) [318, 397] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [1],[1] -[392 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),   0,     16ea ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1e95c00 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  403(TIDL_BatchNormLayer) [319, 403] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[397 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea ||||  L2, DMA,    150(   336),    150(   336),   c0(  192),   fc00(  64512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  407(TIDL_ConvolutionLayer) [320, 407] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ROW_L] ***[44, 64, 64, 231, 295]**** [1], [1],[1] -[403 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),   0,     16ea ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea 
  WT:DDR_PERSIST, DMA,    6c1(  1729),    6c1(  1729),   c0(  192),  51100( 332032),   0,  1ee6d00 ||||  L2, DMA,    740(  1856),    6c1(  1729),   c0(  192),  57000( 356352),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  411(TIDL_BatchNormLayer) [321, 411] --[192 x 20 x  12] => [192 x 20 x  12] *** [192] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[407 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea ||||  L2, DMA,    150(   336),    150(   336),   c0(  192),   fc00(  64512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  415(TIDL_ConvolutionLayer) [322, 415] --[192 x 20 x  12] => [1 x 20 x  12] *** [192] ***[ROW_L] ***[0, 0, 0, 252, 252]**** [1], [1],[1] -[411 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),    1(    1),    196(    406),  16,    1096a 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    1(    1),    100(    256),   0,  1f37e00 ||||  L2, DMA,    140(   320),     c1(   193),    1(    1),    180(    384),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  420(TIDL_BatchNormLayer) [323, 420] --[1 x 20 x  12] => [1 x 20 x  12] *** [1] ***[ COL] ***[0, 0, 0, 252, 252]**** [1], [0],[1] -[415 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),    1(    1),    196(    406),  16,    1096a ||||  L2, DMA,    150(   336),    150(   336),    1(    1),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),    1(    1),    196(    406),  16,    1096a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  416(TIDL_ConvolutionLayer) [324, 416] --[192 x 20 x  12] => [4 x 20 x  12] *** [192] ***[ROW_L] ***[0, 0, 0, 252, 252]**** [1], [1],[1] -[411 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),   c0(  192),   f016(  61462),  16,     16ea ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    127(   295),    4(    4),    516(   1302),  16,     1e6a 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),    4(    4),    380(    896),   0,  1f37f00 ||||  L2, DMA,    140(   320),     c1(   193),    4(    4),    500(   1280),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  424(TIDL_ConcatLayer) [325, 424] --[6 x 20 x  12] => [6 x 20 x  12] *** [6] ***[ COL] ***[0, 0, 0, 252, 252]**** [6], [0],[6] -[416 420 421 ]---
  IN:MSMC, DMA,    140(   320),    127(   295),    4(    4),    516(   1302),  16,     1e6a ||||  L2, DMA,    13b(   315),    13b(   315),    2(    2),    280(    640),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     f0(   240),     f0(   240),    6(    6),    600(   1536),   0,     1700 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  428(TIDL_DataConvertLayer) [326, 428] --[6 x 20 x  12] => [6 x 20 x  12] *** [6] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[424 ]---
  IN:MSMC, DMA,     f0(   240),     f0(   240),    6(    6),    600(   1536),   0,     1700 ||||  L2, DMA,     f0(   240),     f0(   240),    6(    6),    600(   1536),   0,        0 
 OUT:MSMC, CPU,    3c0(   960),    3c0(   960),    6(    6),   1680(   5760),   0,     1d00 |||| DDR, DMA,    3c0(   960),    3c0(   960),    6(    6),   1a80(   6784),   0,   2ead80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  427(TIDL_ReshapeLayer) [328, 427] --[6 x 20 x  12] => [1 x 240 x  6] *** [6] ***[ COL] ***[0, 0, 0, 240, 240]**** [1], [0],[1] -[424 ]---
  IN:MSMC, DMA,     f0(   240),     f0(   240),    6(    6),    600(   1536),   0,     1700 ||||  L2, DMA,     f0(   240),     f0(   240),    6(    6),    600(   1536),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5a0(  1440),    5a0(  1440),    1(    1),    600(   1536),   0,     1700 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  431(TIDL_ConcatLayer) [329, 431] --[1 x 3840 x  6] => [1 x 5040 x  6] *** [1] ***[ COL] ***[0, 0, 0, 23040, 23040]**** [1], [0],[1] -[295 367 427 ]---
  IN:MSMC, DMA,   5a00( 23040),   5a00( 23040),    1(    1),   5a00(  23040),   0,    ee180 ||||  L2, DMA,   5a00( 23040),   5a00( 23040),    2(    2),   b400(  46080),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   7620( 30240),   7620( 30240),    1(    1),   7680(  30336),   0,     7680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  435(TIDL_TransposeLayer) [330, 435] --[1 x 5040 x  6] => [1 x 6 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 30240, 30240]**** [1], [0],[1] -[431 ]---
  IN:MSMC, DMA,   7620( 30240),   7620( 30240),    1(    1),   7680(  30336),   0,     7680 ||||  L2, DMA,  6f800(456704),  6f800(456704),    1(    1),  6f800( 456704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   7620( 30240),   7620( 30240),    1(    1),   7680(  30336),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  437(TIDL_SliceLayer) [331, 437] --[1 x 6 x  5040] => [1 x 2 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 30240, 30240]**** [1], [0],[1] -[435 ]---
  IN:MSMC, DMA,   7620( 30240),   7620( 30240),    1(    1),   7680(  30336),   0,        0 ||||  L2, DMA,   7644( 30276),   7644( 30276),    1(    1),   7680(  30336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     7680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  1(TIDL_ConstDataLayer) [332, 1] --[3 x 640 x  384] => [1 x 2 x  5040] *** [3] ***[FRAME] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  3c000(245760),    1(    1), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,     9e80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   2760( 10080),   2760( 10080),    1(    1),   2780(  10112),   0,  1f9c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  440(TIDL_EltWiseLayer) [333, 440] --[2 x 2 x  5040] => [1 x 2 x  5040] *** [2] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[437 1 ]---
  IN:MSMC, DMA,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     7680 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    2(    2),   9f00(  40704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     7680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_ConstDataLayer) [334, 2] --[3 x 640 x  384] => [1 x 2 x  5040] *** [3] ***[FRAME] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  3c000(245760),    1(    1), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,     9e80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   2760( 10080),   2760( 10080),    1(    1),   2780(  10112),   0,  1f9eb80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  442(TIDL_EltWiseLayer) [335, 442] --[2 x 2 x  5040] => [1 x 2 x  5040] *** [2] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[440 2 ]---
  IN:MSMC, DMA,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     7680 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    2(    2),   9f00(  40704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     7680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  444(TIDL_DataConvertLayer) [336, 444] --[1 x 2 x  5040] => [1 x 2 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[442 ]---
  IN:MSMC, DMA,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     7680 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    1(    1),   2800(  10240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     ec80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  438(TIDL_DataConvertLayer) [337, 438] --[1 x 6 x  5040] => [1 x 6 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 30240, 30240]**** [1], [0],[1] -[435 ]---
  IN:MSMC, DMA,   7620( 30240),   7620( 30240),    1(    1),   7680(  30336),   0,        0 ||||  L2, DMA,   7644( 30276),   7644( 30276),    1(    1),   7680(  30336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   7640( 30272),   7620( 30240),    1(    1),   7680(  30336),   0,    11480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_ConstDataLayer) [338, 3] --[3 x 640 x  384] => [5040 x 3 x  2] *** [3] ***[FRAME] ***[0, 0, 0, 983040, 983040]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  f0000(983040), 13b0( 5040), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  f0000(983040),  f0000(983040),    2(    2), 1e0000(1966080),   0,    18b00 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     18(    24),     18(    24), 13b0( 5040),  1d880( 120960),   0,  1fa1300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  446(TIDL_ScatterElementsLayer) [339, 446] --[1 x 2 x  5040] => [1 x 6 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[438 3 444 ]---
  IN:MSMC, DMA,   7640( 30272),   7620( 30240),    1(    1),   7680(  30336),   0,    11480 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    2(    2),   4f80(  20352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   7640( 30272),   7620( 30240),    1(    1),   ec80(  60544),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  448(TIDL_SliceLayer) [340, 448] --[1 x 6 x  5040] => [1 x 2 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 30240, 30240]**** [1], [0],[1] -[446 ]---
  IN:MSMC, DMA,   7640( 30272),   7620( 30240),    1(    1),   ec80(  60544),   0,        0 ||||  L2, DMA,   7644( 30276),   7644( 30276),    1(    1),   7680(  30336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     ec80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  451(TIDL_BatchNormLayer) [341, 451] --[1 x 2 x  5040] => [1 x 2 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[448 ]---
  IN:MSMC, DMA,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     ec80 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    1(    1),   2800(  10240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     ec80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  4(TIDL_ConstDataLayer) [342, 4] --[3 x 640 x  384] => [1 x 2 x  5040] *** [3] ***[FRAME] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  3c000(245760),    1(    1), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,    11480 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   2760( 10080),   2760( 10080),    1(    1),   2780(  10112),   0,  1fbeb80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  453(TIDL_EltWiseLayer) [343, 453] --[2 x 2 x  5040] => [1 x 2 x  5040] *** [2] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[451 4 ]---
  IN:MSMC, DMA,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     ec80 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    2(    2),   9f00(  40704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,    11480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  455(TIDL_DataConvertLayer) [344, 455] --[1 x 2 x  5040] => [1 x 2 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[453 ]---
  IN:MSMC, DMA,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,    11480 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    1(    1),   2800(  10240),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   27c0( 10176),   2760( 10080),    1(    1),   2800(  10240),   0,     ec80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  449(TIDL_DataConvertLayer) [345, 449] --[1 x 6 x  5040] => [1 x 6 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 30240, 30240]**** [1], [0],[1] -[446 ]---
  IN:MSMC, DMA,   7640( 30272),   7620( 30240),    1(    1),   ec80(  60544),   0,        0 ||||  L2, DMA,   7644( 30276),   7644( 30276),    1(    1),   7680(  30336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   7640( 30272),   7620( 30240),    1(    1),   7680(  30336),   0,    11480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  5(TIDL_ConstDataLayer) [346, 5] --[3 x 640 x  384] => [5040 x 3 x  2] *** [3] ***[FRAME] ***[0, 0, 0, 983040, 983040]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  f0000(983040), 13b0( 5040), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  f0000(983040),  f0000(983040),    2(    2), 1e0000(1966080),   0,    18b00 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     18(    24),     18(    24), 13b0( 5040),  1d880( 120960),   0,  1fc1300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  456(TIDL_ScatterElementsLayer) [347, 456] --[1 x 2 x  5040] => [1 x 6 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 10080, 10080]**** [1], [0],[1] -[449 5 455 ]---
  IN:MSMC, DMA,   7640( 30272),   7620( 30240),    1(    1),   7680(  30336),   0,    11480 ||||  L2, DMA,   27c0( 10176),   27c0( 10176),    2(    2),   4f80(  20352),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   7640( 30272),   7620( 30240),    1(    1),   ec80(  60544),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  457(TIDL_DataConvertLayer) [348, 457] --[1 x 6 x  5040] => [1 x 6 x  5040] *** [1] ***[ COL] ***[0, 0, 0, 30240, 30240]**** [1], [0],[1] -[456 ]---
  IN:MSMC, DMA,   7640( 30272),   7620( 30240),    1(    1),   ec80(  60544),   0,        0 ||||  L2, DMA,   7620( 30240),   7620( 30240),    1(    1),   7680(  30336),   0,        0 
 OUT:MSMC, CPU,  1d880(120960),  1d880(120960),    2(    2),  3b100( 241920),   0,     ec80 |||| DDR, DMA,  1d880(120960),  1d880(120960),    1(    1),  1dc80( 121984),   0,   2ead80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  192(TIDL_ConvolutionLayer) [350, 192] --[256 x 80 x  48] => [128 x 80 x  48] *** [256] ***[ROW_L] ***[164, 192, 192, 192, 4051]**** [21], [1],[21] -[188 ]---
  IN: DDR, DMA,    fd3(  4051),    fd3(  4051),  100(  256),  fd752(1038162),   0,   1ed62e ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24e80( 151168),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),   80(  128),  48080( 295040),   0,  1f38280 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24e80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  196(TIDL_BatchNormLayer) [351, 196] --[128 x 80 x  48] => [128 x 80 x  48] *** [128] ***[ COL] ***[0, 0, 0, 3888, 3888]**** [4], [0],[4] -[192 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),  52,       2e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  199(TIDL_ResizeLayer) [352, 199] --[128 x 80 x  48] => [128 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 4051, 4051]**** [4], [0],[4] -[196 ]---
  IN:MSMC, DMA,   1040(  4160),    fd3(  4051),   80(  128),  82052( 532562),   0,       2e ||||  L2, DMA,   1074(  4212),   1074(  4212),   40(   64),  41d00( 269568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  202(TIDL_EltWiseLayer) [353, 202] --[256 x 160 x  96] => [128 x 160 x  96] *** [256] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [32], [0],[32] -[199 37 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    8(    8),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  206(TIDL_ConvolutionLayer) [354, 206] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 15456]**** [10], [1],[10] -[202 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  69200( 430592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   40(   64),   2080(   8320),   0,  1f80300 ||||  L2, DMA,     c0(   192),     81(   129),   40(   64),   3000(  12288),   0,    69200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  210(TIDL_BatchNormLayer) [355, 210] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[206 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  205(TIDL_ConvolutionLayer) [356, 205] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 15456]**** [10], [1],[10] -[202 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   80(  128), 1ee022(2023458),  a2,    f70de ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  69200( 430592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   40(   64),   2080(   8320),   0,  1f82380 ||||  L2, DMA,     c0(   192),     81(   129),   40(   64),   3000(  12288),   0,    69200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  209(TIDL_BatchNormLayer) [357, 209] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[205 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  213(TIDL_ConvolutionLayer) [358, 213] --[64 x 160 x  96] => [32 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 3072, 15779]**** [6], [1],[6] -[209 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,    f70de ||||  L2, DMA,   19c0(  6592),   19c0(  6592),   40(   64),  6a000( 434176),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   1ee15e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   20(   32),   4880(  18560),   0,  1f84400 ||||  L2, DMA,    2c0(   704),    241(   577),   20(   32),   5800(  22528),   0,    6a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  216(TIDL_BatchNormLayer) [359, 216] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[213 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   1ee15e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   1ee15e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  220(TIDL_ConvolutionLayer) [360, 220] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ROW_L] ***[324, 384, 384, 6592, 15779]**** [3], [1],[3] -[216 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),   0,   1ee15e ||||  L2, DMA,   3540( 13632),   3540( 13632),   20(   32),  6c180( 442752),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   2699de 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   20(   32),   2480(   9344),   0,  1f88c80 ||||  L2, DMA,    140(   320),    121(   289),   20(   32),   2800(  10240),   0,    6c180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  224(TIDL_BatchNormLayer) [361, 224] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[220 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   2699de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   2699de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  227(TIDL_ConvolutionLayer) [362, 227] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ROW_L] ***[324, 384, 384, 6592, 15779]**** [3], [1],[3] -[224 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),   0,   2699de ||||  L2, DMA,   3540( 13632),   3540( 13632),   20(   32),  6c180( 442752),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   2e525e 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   20(   32),   2480(   9344),   0,  1f8b100 ||||  L2, DMA,    140(   320),    121(   289),   20(   32),   2800(  10240),   0,    6c180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  230(TIDL_BatchNormLayer) [363, 230] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[227 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   2e525e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   2e525e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  233(TIDL_ConvolutionLayer) [364, 233] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ROW_L] ***[324, 384, 384, 6592, 15779]**** [3], [1],[3] -[230 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),   0,   2e525e ||||  L2, DMA,   3540( 13632),   3540( 13632),   20(   32),  6c180( 442752),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   360ade 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   20(   32),   2480(   9344),   0,  1f8d580 ||||  L2, DMA,    140(   320),    121(   289),   20(   32),   2800(  10240),   0,    6c180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  238(TIDL_BatchNormLayer) [365, 238] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[233 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   360ade ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   360ade 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  243(TIDL_ConcatLayer) [366, 243] --[256 x 160 x  96] => [256 x 160 x  96] *** [256] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [256], [0],[256] -[210 209 216 224 230 238 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    2(    2),   7d00(  32000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,   3dc35e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  249(TIDL_ConvolutionLayer) [367, 249] --[256 x 160 x  96] => [64 x 160 x  96] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 15456]**** [21], [1],[21] -[243 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),  100(  256), 3dc022(4046882),  a2,   3dc35e ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  67900( 424192),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   40(   64),   4080(  16512),   0,  1f8fa00 ||||  L2, DMA,    140(   320),    101(   257),   40(   64),   5000(  20480),   0,    67900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  254(TIDL_BatchNormLayer) [368, 254] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[249 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  259(TIDL_ConvolutionLayer) [369, 259] --[64 x 160 x  96] => [32 x 160 x  96] *** [64] ***[ROW_L] ***[0, 0, 0, 3392, 15456]**** [5], [1],[5] -[254 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   1ac0(  6848),   1ac0(  6848),   40(   64),  6d780( 448384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,    f70de 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,  1f93a80 ||||  L2, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,    6d780 
 STG:MSMC, DMA_ONCE,     40(    64),     40(    64),   20(   32),    880(   2176),   0,   7b9780 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  268(TIDL_DataConvertLayer) [370, 268] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[259 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,    f70de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),   20(   32),  78000( 491520),   0,   172900 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  278(TIDL_ReshapeLayer) [371, 278] --[32 x 160 x  96] => [1 x 15360 x  32] *** [32] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [4], [0],[4] -[268 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),   20(   32),  78000( 491520),   0,   172900 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),   10(   16),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  78000(491520),  78000(491520),    1(    1),  78000( 491520),   0,   172900 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  6(TIDL_ConstDataLayer) [372, 6] --[3 x 640 x  384] => [1 x 1 x  15360] *** [3] ***[FRAME] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  3c000(245760),    1(    1), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,   1ea900 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,  1fdeb80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  286(TIDL_InnerProductLayer) [373, 286] --[1 x 15360 x  32] => [1 x 1 x  32] *** [1] ***[ COL] ***[0, 0, 0, 168960, 491520]**** [3], [0],[3] -[278 6 ]---
  IN:MSMC, DMA,  78000(491520),  78000(491520),    1(    1),  78000( 491520),   0,   172900 ||||  L2, DMA,  56400(353280),  56400(353280),    1(    1),  52800( 337920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     20(    32),     20(    32),    1(    1),     80(    128),   0,    f7080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  291(TIDL_ReshapeLayer) [374, 291] --[1 x 1 x  32] => [1 x 32 x  1] *** [1] ***[ COL] ***[0, 0, 0, 32, 32]**** [1], [0],[1] -[286 ]---
  IN:MSMC, DMA,     20(    32),     20(    32),    1(    1),     80(    128),   0,    f7080 ||||  L2, DMA,     20(    32),     20(    32),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     20(    32),     20(    32),    1(    1),     80(    128),   0,    f7080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  260(TIDL_ConvolutionLayer) [375, 260] --[64 x 160 x  96] => [32 x 160 x  96] *** [64] ***[ROW_L] ***[0, 0, 0, 3392, 15456]**** [5], [1],[5] -[254 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   1ac0(  6848),   1ac0(  6848),   40(   64),  6d780( 448384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,    f715e 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,  1f94300 ||||  L2, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,    6d780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  269(TIDL_DataConvertLayer) [376, 269] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[260 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,    f715e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),   20(   32),  78000( 491520),   0,   172980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  279(TIDL_ReshapeLayer) [377, 279] --[32 x 160 x  96] => [1 x 15360 x  32] *** [32] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [4], [0],[4] -[269 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),   20(   32),  78000( 491520),   0,   172980 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),   10(   16),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  78000(491520),  78000(491520),    1(    1),  78000( 491520),   0,   172980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  297(TIDL_InnerProductLayer) [378, 297] --[1 x 32 x  1] => [1 x 15360 x  1] *** [1] ***[ COL] ***[0, 0, 0, 128, 32]**** [3], [0],[3] -[291 279 ]---
  IN:MSMC, DMA,     20(    32),     20(    32),    1(    1),     80(    128),   0,    f7080 ||||  L2, DMA,  50080(327808),  50080(327808),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c40( 15424),   3c00( 15360),    1(    1),   3c80(  15488),   0,    f7100 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  302(TIDL_SoftMaxLayer) [379, 302] --[1 x 15360 x  1] => [1 x 15360 x  1] *** [1] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [1], [0],[1] -[297 ]---
  IN:MSMC, DMA,   3c40( 15424),   3c00( 15360),    1(    1),   3c80(  15488),   0,    f7100 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,    fad80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  306(TIDL_ReshapeLayer) [380, 306] --[1 x 15360 x  1] => [1 x 160 x  96] *** [1] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [1], [0],[1] -[302 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,    fad80 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,    fad80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  310(TIDL_DataConvertLayer) [381, 310] --[1 x 160 x  96] => [1 x 160 x  96] *** [1] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [1], [0],[1] -[306 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,    fad80 ||||  L2, DMA,   3ca0( 15520),   3ca0( 15520),    1(    1),   3d00(  15616),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),    1(    1),   3e22(  15906),  a2,    fe9de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  314(TIDL_BatchNormLayer) [382, 314] --[1 x 160 x  96] => [1 x 160 x  96] *** [1] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [1], [0],[1] -[310 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),    1(    1),   3e22(  15906),  a2,    fe9de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    1(    1),   3e80(  16000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),    1(    1),   3e22(  15906),  a2,   1ee15e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  317(TIDL_EltWiseLayer) [383, 317] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [16], [0],[16] -[254 314 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    8(    8),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  261(TIDL_ConvolutionLayer) [384, 261] --[64 x 160 x  96] => [1 x 160 x  96] *** [64] ***[ROW_L] ***[0, 0, 0, 3392, 15456]**** [5], [1],[5] -[254 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   1ac0(  6848),   1ac0(  6848),   40(   64),  6d780( 448384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),    1(    1),   3e22(  15906),  a2,   1ee15e 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,  1f94b80 ||||  L2, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,    6d780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  270(TIDL_DataConvertLayer) [385, 270] --[1 x 160 x  96] => [1 x 160 x  96] *** [1] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [1], [0],[1] -[261 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),    1(    1),   3e22(  15906),  a2,   1ee15e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    1(    1),   3e80(  16000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1f1f80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  280(TIDL_ReshapeLayer) [386, 280] --[1 x 160 x  96] => [1 x 15360 x  1] *** [1] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [1], [0],[1] -[270 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1f1f80 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1f1f80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  287(TIDL_SoftMaxLayer) [387, 287] --[1 x 15360 x  1] => [1 x 15360 x  1] *** [1] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [1], [0],[1] -[280 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1f1f80 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1ee100 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  292(TIDL_ReshapeLayer) [388, 292] --[1 x 15360 x  1] => [1 x 1 x  15360] *** [1] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [1], [0],[1] -[287 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1ee100 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),    1(    1),   3c00(  15360),   0,   1ee100 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  262(TIDL_ConvolutionLayer) [389, 262] --[64 x 160 x  96] => [32 x 160 x  96] *** [64] ***[ROW_L] ***[0, 0, 0, 3392, 15456]**** [5], [1],[5] -[254 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   1ac0(  6848),   1ac0(  6848),   40(   64),  6d780( 448384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   1f1d5e 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,  1f94c00 ||||  L2, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,    6d780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  271(TIDL_DataConvertLayer) [390, 271] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[262 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,   1f1d5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3c00( 15360),   3c00( 15360),   20(   32),  78000( 491520),   0,   26d580 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  281(TIDL_ReshapeLayer) [391, 281] --[32 x 160 x  96] => [1 x 15360 x  32] *** [32] ***[ COL] ***[0, 0, 0, 15360, 15360]**** [4], [0],[4] -[271 ]---
  IN:MSMC, DMA,   3c00( 15360),   3c00( 15360),   20(   32),  78000( 491520),   0,   26d580 ||||  L2, DMA,   3c00( 15360),   3c00( 15360),   10(   16),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  78000(491520),  78000(491520),    1(    1),  78000( 491520),   0,   26d580 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  298(TIDL_InnerProductLayer) [392, 298] --[1 x 15360 x  32] => [1 x 1 x  32] *** [1] ***[ COL] ***[0, 0, 0, 168960, 491520]**** [3], [0],[3] -[281 292 ]---
  IN:MSMC, DMA,  78000(491520),  78000(491520),    1(    1),  78000( 491520),   0,   26d580 ||||  L2, DMA,  56400(353280),  56400(353280),    1(    1),  52800( 337920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     20(    32),     20(    32),    1(    1),     80(    128),   0,   1f1d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  303(TIDL_ReshapeLayer) [393, 303] --[1 x 1 x  32] => [32 x 1 x  1] *** [1] ***[ COL] ***[0, 0, 0, 32, 32]**** [1], [0],[1] -[298 ]---
  IN:MSMC, DMA,     20(    32),     20(    32),    1(    1),     80(    128),   0,   1f1d00 ||||  L2, DMA,     20(    32),     20(    32),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      1(     1),      1(     1),   20(   32),     80(    128),   0,   1f1d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  307(TIDL_DataConvertLayer) [394, 307] --[32 x 1 x  1] => [32 x 1 x  1] *** [32] ***[ COL] ***[0, 0, 0, 1, 1]**** [1], [0],[1] -[303 ]---
  IN:MSMC, DMA,      1(     1),      1(     1),   20(   32),     80(    128),   0,   1f1d00 ||||  L2, DMA,      1(     1),      1(     1),   20(   32),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      7(     7),      7(     7),   20(   32),    103(    259),   3,   1ee17d 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  311(TIDL_ConvolutionLayer) [395, 311] --[32 x 1 x  1] => [64 x 1 x  1] *** [32] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[307 ]---
  IN:MSMC, DMA,      7(     7),      7(     7),   20(   32),    103(    259),   3,   1ee17d ||||  L2, DMA,      2(     2),      2(     2),   20(   32),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      7(     7),      7(     7),   40(   64),    203(    515),   3,   1ee17d 
  WT:DDR_PERSIST, DMA,     20(    32),     20(    32),   40(   64),    900(   2304),   0,  1f95480 ||||  L2, DMA,     20(    32),     20(    32),   40(   64),    900(   2304),   0,       80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  315(TIDL_BatchNormLayer) [396, 315] --[64 x 1 x  1] => [64 x 1 x  1] *** [64] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[311 ]---
  IN:MSMC, DMA,      7(     7),      7(     7),   40(   64),    203(    515),   3,   1ee17d ||||  L2, DMA,      8(     8),      8(     8),   40(   64),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      7(     7),      7(     7),   40(   64),    203(    515),   3,   1ee17d 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  318(TIDL_EltWiseLayer) [397, 318] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [16], [0],[16] -[254 315 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    8(    8),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,   1ee3de 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  320(TIDL_EltWiseLayer) [398, 320] --[128 x 160 x  96] => [64 x 160 x  96] *** [128] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [16], [0],[16] -[317 318 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,    f70de ||||  L2, DMA,   3e43( 15939),   3e43( 15939),    8(    8),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  322(TIDL_BatchNormLayer) [399, 322] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[320 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  324(TIDL_BatchNormLayer) [400, 324] --[64 x 160 x  96] => [64 x 160 x  96] *** [64] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [8], [0],[8] -[322 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  328(TIDL_ConvolutionLayer) [401, 328] --[64 x 160 x  96] => [32 x 160 x  96] *** [64] ***[ROW_L] ***[324, 384, 384, 3072, 15779]**** [6], [1],[6] -[324 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   40(   64),  f7022(1011746),   0,       5e ||||  L2, DMA,   19c0(  6592),   19c0(  6592),   40(   64),  6a000( 434176),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,       5e 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   20(   32),   4880(  18560),   0,  1f95d80 ||||  L2, DMA,    2c0(   704),    241(   577),   20(   32),   5800(  22528),   0,    6a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  332(TIDL_BatchNormLayer) [402, 332] --[32 x 160 x  96] => [32 x 160 x  96] *** [32] ***[ COL] ***[0, 0, 0, 15456, 15456]**** [4], [0],[4] -[328 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),  a2,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  337(TIDL_ResizeLayer) [403, 337] --[32 x 160 x  96] => [32 x 320 x  192] *** [32] ***[ COL] ***[0, 0, 0, 15779, 15779]**** [4], [0],[4] -[332 ]---
  IN:MSMC, DMA,   3dc0( 15808),   3da3( 15779),   20(   32),  7b822( 505890),   0,       5e ||||  L2, DMA,   3e43( 15939),   3e43( 15939),   10(   16),  3e480( 255104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866), 142,    7b8be 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  341(TIDL_ConvolutionLayer) [404, 341] --[32 x 320 x  192] => [16 x 320 x  192] *** [32] ***[ROW_L] ***[644, 704, 704, 5824, 62275]**** [11], [1],[11] -[337 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866),   0,    7b8be ||||  L2, DMA,   3040( 12352),   3040( 12352),   20(   32),  6d500( 447744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,    7b8be 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   10(   16),   1280(   4736),   0,  1f9a600 ||||  L2, DMA,    140(   320),    121(   289),   10(   16),   1400(   5120),   0,    6d500 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 0,  0]
------  345(TIDL_BatchNormLayer) [405, 345] --[16 x 320 x  192] => [16 x 320 x  192] *** [16] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [8], [0],[8] -[341 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,    7b8be ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,    79ebe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  351(TIDL_ConvolutionLayer) [406, 351] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ROW_L] ***[0, 0, 0, 12992, 61632]**** [5], [1],[5] -[345 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,    79ebe ||||  L2, DMA,   65c0( 26048),   65c0( 26048),   10(   16),  6f400( 455680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:DDR_PERSIST, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,  1f9b880 ||||  L2, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,    6f400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  358(TIDL_BatchNormLayer) [407, 358] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[351 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  350(TIDL_ConvolutionLayer) [408, 350] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ROW_L] ***[0, 0, 0, 12992, 61632]**** [5], [1],[5] -[345 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   10(   16),  f3c42( 998466), 142,    79ebe ||||  L2, DMA,   65c0( 26048),   65c0( 26048),   10(   16),  6f400( 455680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,    79ebe 
  WT:DDR_PERSIST, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,  1f9b980 ||||  L2, DMA,     11(    17),     11(    17),    8(    8),    100(    256),   0,    6f400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  357(TIDL_BatchNormLayer) [409, 357] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[350 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,    79ebe ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,    79ebe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  362(TIDL_ConvolutionLayer) [410, 362] --[8 x 320 x  192] => [4 x 320 x  192] *** [8] ***[ROW_L] ***[644, 704, 704, 26432, 62275]**** [3], [1],[3] -[357 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266),   0,    79ebe ||||  L2, DMA,   d140( 53568),   d140( 53568),    8(    8),  6f180( 455040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    f3d3e 
  WT:DDR_PERSIST, DMA,     49(    73),     49(    73),    4(    4),    180(    384),   0,  1f9ba80 ||||  L2, DMA,     c0(   192),     49(    73),    4(    4),    300(    768),   0,    6f180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  365(TIDL_BatchNormLayer) [411, 365] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[362 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    f3d3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    f3d3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  369(TIDL_ConvolutionLayer) [412, 369] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ROW_L] ***[644, 704, 704, 56704, 62275]**** [2], [1],[2] -[365 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666),   0,    f3d3e ||||  L2, DMA,  1bdc0(114112),  1bdc0(114112),    4(    4),  6f700( 456448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   130cbe 
  WT:DDR_PERSIST, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,  1f9bc00 ||||  L2, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,    6f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  372(TIDL_BatchNormLayer) [413, 372] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[369 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   130cbe ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   130cbe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  374(TIDL_ConvolutionLayer) [414, 374] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ROW_L] ***[644, 704, 704, 56704, 62275]**** [2], [1],[2] -[372 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666),   0,   130cbe ||||  L2, DMA,  1bdc0(114112),  1bdc0(114112),    4(    4),  6f700( 456448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   16dc3e 
  WT:DDR_PERSIST, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,  1f9bd00 ||||  L2, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,    6f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  376(TIDL_BatchNormLayer) [415, 376] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[374 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   16dc3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   16dc3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  378(TIDL_ConvolutionLayer) [416, 378] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ROW_L] ***[644, 704, 704, 56704, 62275]**** [2], [1],[2] -[376 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666),   0,   16dc3e ||||  L2, DMA,  1bdc0(114112),  1bdc0(114112),    4(    4),  6f700( 456448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   1aabbe 
  WT:DDR_PERSIST, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,  1f9be00 ||||  L2, DMA,     29(    41),     29(    41),    4(    4),    100(    256),   0,    6f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  380(TIDL_BatchNormLayer) [417, 380] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[378 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   1aabbe ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   1aabbe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  382(TIDL_ConcatLayer) [418, 382] --[32 x 320 x  192] => [32 x 320 x  192] *** [32] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [16], [0],[16] -[358 357 365 372 376 380 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866), 142,   1e7b3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  384(TIDL_ConvolutionLayer) [419, 384] --[32 x 320 x  192] => [8 x 320 x  192] *** [32] ***[ROW_L] ***[0, 0, 0, 6272, 61632]**** [10], [1],[10] -[382 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),   20(   32), 1e7842(1996866), 142,   1e7b3e ||||  L2, DMA,   3140( 12608),   3140( 12608),   20(   32),  6ec00( 453632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:DDR_PERSIST, DMA,     21(    33),     21(    33),    8(    8),    180(    384),   0,  1f9bf00 ||||  L2, DMA,     21(    33),     21(    33),    8(    8),    180(    384),   0,    6ec00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  386(TIDL_BatchNormLayer) [420, 386] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[384 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  388(TIDL_ConvolutionLayer) [421, 388] --[8 x 320 x  192] => [4 x 320 x  192] *** [8] ***[ROW_L] ***[0, 0, 0, 26816, 61632]**** [3], [1],[3] -[386 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   d1c0( 53696),   d1c0( 53696),    8(    8),  6f680( 456320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    79ebe 
  WT:DDR_PERSIST, DMA,      8(     8),      8(     8),    4(    4),     80(    128),   0,  1f9c080 ||||  L2, DMA,      8(     8),      8(     8),    4(    4),     80(    128),   0,    6f680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  393(TIDL_DataConvertLayer) [422, 393] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[388 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    79ebe ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,    b6e00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  399(TIDL_ReshapeLayer) [423, 399] --[4 x 320 x  192] => [1 x 61440 x  4] *** [4] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[393 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,    b6e00 ||||  L2, DMA,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c000(245760),  3c000(245760),    1(    1),  3c000( 245760),   0,    b6e00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  7(TIDL_ConstDataLayer) [424, 7] --[3 x 640 x  384] => [1 x 1 x  61440] *** [3] ***[FRAME] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[]---
  IN: DDR, DMA,  f0000(983040),  3c000(245760),    1(    1), 2d0400(2950144),   0,        0 ||||MSMC, DMA,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,    f2e00 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,  1fe2780 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  405(TIDL_InnerProductLayer) [425, 405] --[1 x 61440 x  4] => [1 x 1 x  4] *** [1] ***[ COL] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[399 7 ]---
  IN:MSMC, DMA,  3c000(245760),  3c000(245760),    1(    1),  3c000( 245760),   0,    b6e00 ||||  L2, DMA,  5a000(368640),  5a000(368640),    1(    1),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),    1(    1),     80(    128),   0,    79e80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  409(TIDL_ReshapeLayer) [426, 409] --[1 x 1 x  4] => [1 x 4 x  1] *** [1] ***[ COL] ***[0, 0, 0, 4, 4]**** [1], [0],[1] -[405 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),    1(    1),     80(    128),   0,    79e80 ||||  L2, DMA,      4(     4),      4(     4),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),    1(    1),     80(    128),   0,    79e80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  389(TIDL_ConvolutionLayer) [427, 389] --[8 x 320 x  192] => [4 x 320 x  192] *** [8] ***[ROW_L] ***[0, 0, 0, 26816, 61632]**** [3], [1],[3] -[386 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   d1c0( 53696),   d1c0( 53696),    8(    8),  6f680( 456320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    79f3e 
  WT:DDR_PERSIST, DMA,      8(     8),      8(     8),    4(    4),     80(    128),   0,  1f9c100 ||||  L2, DMA,      8(     8),      8(     8),    4(    4),     80(    128),   0,    6f680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  394(TIDL_DataConvertLayer) [428, 394] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[389 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,    79f3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,    b6e80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  400(TIDL_ReshapeLayer) [429, 400] --[4 x 320 x  192] => [1 x 61440 x  4] *** [4] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[394 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,    b6e80 ||||  L2, DMA,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c000(245760),  3c000(245760),    1(    1),  3c000( 245760),   0,    b6e80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  413(TIDL_InnerProductLayer) [430, 413] --[1 x 4 x  1] => [1 x 61440 x  1] *** [1] ***[ COL] ***[0, 0, 0, 8, 4]**** [1], [0],[1] -[409 400 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),    1(    1),     80(    128),   0,    79e80 ||||  L2, DMA,  3c008(245768),  3c008(245768),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    79f00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  418(TIDL_SoftMaxLayer) [431, 418] --[1 x 61440 x  1] => [1 x 61440 x  1] *** [1] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[413 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    79f00 ||||  L2, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    88f00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  422(TIDL_ReshapeLayer) [432, 422] --[1 x 61440 x  1] => [1 x 320 x  192] *** [1] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[418 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    88f00 ||||  L2, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    88f00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  425(TIDL_DataConvertLayer) [433, 425] --[1 x 320 x  192] => [1 x 320 x  192] *** [1] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[422 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    88f00 ||||  L2, DMA,   f140( 61760),   f140( 61760),    1(    1),   f180(  61824),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    1(    1),   f442(  62530), 142,    97f3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  429(TIDL_BatchNormLayer) [434, 429] --[1 x 320 x  192] => [1 x 320 x  192] *** [1] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[425 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    1(    1),   f442(  62530), 142,    97f3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    1(    1),   f500(  62720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    1(    1),   f442(  62530), 142,    f3d3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  433(TIDL_EltWiseLayer) [435, 433] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [8], [0],[8] -[386 429 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    2(    2),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,    79ebe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  390(TIDL_ConvolutionLayer) [436, 390] --[8 x 320 x  192] => [1 x 320 x  192] *** [8] ***[ROW_L] ***[0, 0, 0, 26816, 61632]**** [3], [1],[3] -[386 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   d1c0( 53696),   d1c0( 53696),    8(    8),  6f680( 456320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    1(    1),   f442(  62530), 142,    f3d3e 
  WT:DDR_PERSIST, DMA,      8(     8),      8(     8),    1(    1),     80(    128),   0,  1f9c180 ||||  L2, DMA,      8(     8),      8(     8),    1(    1),     80(    128),   0,    6f680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  395(TIDL_DataConvertLayer) [437, 395] --[1 x 320 x  192] => [1 x 320 x  192] *** [1] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[390 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    1(    1),   f442(  62530), 142,    f3d3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    1(    1),   f500(  62720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,   103180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  401(TIDL_ReshapeLayer) [438, 401] --[1 x 320 x  192] => [1 x 61440 x  1] *** [1] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[395 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,   103180 ||||  L2, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,   103180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  406(TIDL_SoftMaxLayer) [439, 406] --[1 x 61440 x  1] => [1 x 61440 x  1] *** [1] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[401 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,   103180 ||||  L2, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    f3d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  410(TIDL_ReshapeLayer) [440, 410] --[1 x 61440 x  1] => [1 x 1 x  61440] *** [1] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[406 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    f3d00 ||||  L2, DMA,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    1(    1),   f000(  61440),   0,    f3d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  391(TIDL_ConvolutionLayer) [441, 391] --[8 x 320 x  192] => [4 x 320 x  192] *** [8] ***[ROW_L] ***[0, 0, 0, 26816, 61632]**** [3], [1],[3] -[386 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   d1c0( 53696),   d1c0( 53696),    8(    8),  6f680( 456320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   102d3e 
  WT:DDR_PERSIST, DMA,      8(     8),      8(     8),    4(    4),     80(    128),   0,  1f9c200 ||||  L2, DMA,      8(     8),      8(     8),    4(    4),     80(    128),   0,    6f680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  396(TIDL_DataConvertLayer) [442, 396] --[4 x 320 x  192] => [4 x 320 x  192] *** [4] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [1], [0],[1] -[391 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    4(    4),  3cf42( 249666), 142,   102d3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,   13fc80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  402(TIDL_ReshapeLayer) [443, 402] --[4 x 320 x  192] => [1 x 61440 x  4] *** [4] ***[ COL] ***[0, 0, 0, 61440, 61440]**** [1], [0],[1] -[396 ]---
  IN:MSMC, DMA,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,   13fc80 ||||  L2, DMA,   f000( 61440),   f000( 61440),    4(    4),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c000(245760),  3c000(245760),    1(    1),  3c000( 245760),   0,   13fc80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  414(TIDL_InnerProductLayer) [444, 414] --[1 x 61440 x  4] => [1 x 1 x  4] *** [1] ***[ COL] ***[0, 0, 0, 245760, 245760]**** [1], [0],[1] -[402 410 ]---
  IN:MSMC, DMA,  3c000(245760),  3c000(245760),    1(    1),  3c000( 245760),   0,   13fc80 ||||  L2, DMA,  5a000(368640),  5a000(368640),    1(    1),  3c000( 245760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),    1(    1),     80(    128),   0,   102d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  419(TIDL_ReshapeLayer) [445, 419] --[1 x 1 x  4] => [4 x 1 x  1] *** [1] ***[ COL] ***[0, 0, 0, 4, 4]**** [1], [0],[1] -[414 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),    1(    1),     80(    128),   0,   102d00 ||||  L2, DMA,      4(     4),      4(     4),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      1(     1),      1(     1),    4(    4),     80(    128),   0,   102d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  423(TIDL_DataConvertLayer) [446, 423] --[4 x 1 x  1] => [4 x 1 x  1] *** [4] ***[ COL] ***[0, 0, 0, 1, 1]**** [1], [0],[1] -[419 ]---
  IN:MSMC, DMA,      1(     1),      1(     1),    4(    4),     80(    128),   0,   102d00 ||||  L2, DMA,      1(     1),      1(     1),    4(    4),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      7(     7),      7(     7),    4(    4),     83(    131),   3,    f3d7d 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  426(TIDL_ConvolutionLayer) [447, 426] --[4 x 1 x  1] => [8 x 1 x  1] *** [4] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[423 ]---
  IN:MSMC, DMA,      7(     7),      7(     7),    4(    4),     83(    131),   3,    f3d7d ||||  L2, DMA,      2(     2),      2(     2),    4(    4),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      7(     7),      7(     7),    8(    8),     83(    131),   3,    f3d7d 
  WT:DDR_PERSIST, DMA,      8(     8),      8(     8),    8(    8),     80(    128),   0,  1f9c280 ||||  L2, DMA,      8(     8),      8(     8),    8(    8),     80(    128),   0,       80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  430(TIDL_BatchNormLayer) [448, 430] --[8 x 1 x  1] => [8 x 1 x  1] *** [8] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[426 ]---
  IN:MSMC, DMA,      7(     7),      7(     7),    8(    8),     83(    131),   3,    f3d7d ||||  L2, DMA,      8(     8),      8(     8),    8(    8),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      7(     7),      7(     7),    8(    8),     83(    131),   3,    f3d7d 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  434(TIDL_EltWiseLayer) [449, 434] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [8], [0],[8] -[386 430 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    2(    2),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,    f3e3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  436(TIDL_EltWiseLayer) [450, 436] --[16 x 320 x  192] => [8 x 320 x  192] *** [16] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [8], [0],[8] -[433 434 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,    79ebe ||||  L2, DMA,   f483( 62595),   f483( 62595),    2(    2),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  439(TIDL_BatchNormLayer) [451, 439] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[436 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  441(TIDL_BatchNormLayer) [452, 441] --[8 x 320 x  192] => [8 x 320 x  192] *** [8] ***[ COL] ***[0, 0, 0, 61632, 61632]**** [4], [0],[4] -[439 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266), 142,       3e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  443(TIDL_ResizeLayer) [453, 443] --[8 x 320 x  192] => [8 x 640 x  384] *** [8] ***[ COL] ***[0, 0, 0, 62275, 62275]**** [4], [0],[4] -[441 ]---
  IN:MSMC, DMA,   f3c0( 62400),   f343( 62275),    8(    8),  79e42( 499266),   0,       3e ||||  L2, DMA,   f483( 62595),   f483( 62595),    4(    4),  3d280( 250496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    8(    8), 1e3602(1979906), 282,    79efe 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  445(TIDL_ConvolutionLayer) [454, 445] --[8 x 640 x  384] => [2 x 640 x  384] *** [8] ***[ROW_L] ***[1284, 1344, 1344, 13440, 247427]**** [19], [1],[19] -[443 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    8(    8), 1e3602(1979906),   0,    79efe ||||  L2, DMA,   6e40( 28224),   6e40( 28224),    8(    8),  6ee80( 454272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,       7e 
  WT:DDR_PERSIST, DMA,     49(    73),     49(    73),    2(    2),    100(    256),   0,  1f9c300 ||||  L2, DMA,     c0(   192),     49(    73),    2(    2),    180(    384),   0,    6ee80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  447(TIDL_BatchNormLayer) [455, 447] --[2 x 640 x  384] => [2 x 640 x  384] *** [2] ***[ COL] ***[0, 0, 0, 123072, 246144]**** [4], [0],[4] -[445 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,       7e ||||  L2, DMA,  3c180(246144),  3c180(246144),    1(    1),  3c180( 246144),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,       7e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  450(TIDL_BatchNormLayer) [456, 450] --[2 x 640 x  384] => [2 x 640 x  384] *** [2] ***[ COL] ***[0, 0, 0, 123072, 246144]**** [4], [0],[4] -[447 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,       7e ||||  L2, DMA,  3c180(246144),  3c180(246144),    1(    1),  3c180( 246144),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,       7e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  452(TIDL_DataConvertLayer) [457, 452] --[2 x 640 x  384] => [2 x 640 x  384] *** [2] ***[ COL] ***[0, 0, 0, 61536, 246144]**** [8], [0],[8] -[450 ]---
  IN:MSMC, DMA,  3c6c0(247488),  3c683(247427),    2(    2),  78d82( 494978), 282,       7e ||||  L2, DMA,  1e0c0(123072),  1e0c0(123072),    1(    1),  1e100( 123136),   0,        0 
 OUT:MSMC, CPU,  3c000(245760),  3c000(245760),    2(    2),  78000( 491520),   0,    78e00 |||| DDR, DMA,  f0000(983040),  f0000(983040),    2(    2), 1e0400(1967104),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
