//############################################################################# // // FILE: driverlib.h // // TITLE: C28x Driverlib Header File // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //########################################################################### // // FILE: hw_memmap.h // // TITLE: Macros defining the memory map of the C28x. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the base address of the memories and // peripherals. // //***************************************************************************** //########################################################################### // // FILE: adc.h // // TITLE: C28x ADC driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup adc_api ADC //! @{ // //***************************************************************************** /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /*****************************************************************************/ /* STDINT.H */ /* */ /* Copyright (c) 2002 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /* 7.18.1.1 Exact-width integer types */ typedef int int16_t; typedef unsigned int uint16_t; typedef long int32_t; typedef unsigned long uint32_t; typedef long long int64_t; typedef unsigned long long uint64_t; /* 7.18.1.2 Minimum-width integer types */ typedef int16_t int_least8_t; typedef uint16_t uint_least8_t; typedef int16_t int_least16_t; typedef uint16_t uint_least16_t; typedef int32_t int_least32_t; typedef uint32_t uint_least32_t; typedef int64_t int_least64_t; typedef uint64_t uint_least64_t; /* 7.18.1.3 Fastest minimum-width integer types */ typedef int16_t int_fast8_t; typedef uint16_t uint_fast8_t; typedef int16_t int_fast16_t; typedef uint16_t uint_fast16_t; typedef int32_t int_fast32_t; typedef uint32_t uint_fast32_t; typedef int64_t int_fast64_t; typedef uint64_t uint_fast64_t; /* 7.18.1.4 Integer types capable of holding object pointers */ typedef long intptr_t; typedef unsigned long uintptr_t; /* 7.18.1.5 Greatest-width integer types */ typedef long long intmax_t; typedef unsigned long long uintmax_t; /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ /* 7.18.2 Limits of specified width integer types */ /* 7.18.3 Limits of other integer types */ /* 7.18.4.1 Macros for minimum-width integer constants */ /* There is a defect report filed against the C99 standard concerning how the (U)INTN_C macros should be implemented. Please refer to -- http://wwwold.dkuug.dk/JTC1/SC22/WG14/www/docs/dr_209.htm for more information. These macros are implemented according to the suggestion given at this web site. */ /* 7.18.4.2 Macros for greatest-width integer constants */ //########################################################################### // // FILE: hw_adc.h // // TITLE: Definitions for the ADC registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the ADC register offsets // //***************************************************************************** // Register // Register // Register // Selection Register // Selection Register // Register // Register // Register // Register // Register // Stamp Register // Register // Register // Time Stamp Register // Stamp Register // Register // Register // Time Stamp Register // Stamp Register // Register // Register // Time Stamp Register // Stamp Register // Register // Register // Time Stamp Register // generation cycle // Result Register // Result Register // Result Register // Result Register //***************************************************************************** // // The following are defines for the bit fields in the ADCCTL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCCTL2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCBURSTCTL register // //***************************************************************************** // Select //***************************************************************************** // // The following are defines for the bit fields in the ADCINTFLG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCINTFLGCLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCINTOVF register // //***************************************************************************** // Flags // Flags // Flags // Flags //***************************************************************************** // // The following are defines for the bit fields in the ADCINTOVFCLR register // //***************************************************************************** // Clear Bits // Clear Bits // Clear Bits // Clear Bits //***************************************************************************** // // The following are defines for the bit fields in the ADCINTSEL1N2 register // //***************************************************************************** // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCINTSEL3N4 register // //***************************************************************************** // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCPRICTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCINTSOCSEL1 register // //***************************************************************************** // Select // Select // Select // Select // Select // Select // Select // Select //***************************************************************************** // // The following are defines for the bit fields in the ADCINTSOCSEL2 register // //***************************************************************************** // Select // Select // Select // Select // Select // Select // Select // Select //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCFLG1 register // //***************************************************************************** // Flag // Flag // Flag // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCFRC1 register // //***************************************************************************** // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit // Conversion Bit //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCOVF1 register // //***************************************************************************** // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag // Overflow Flag //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCOVFCLR1 register // //***************************************************************************** // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit // Conversion Overflow Bit //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC0CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC1CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC2CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC3CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC4CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC5CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC6CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC7CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC8CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC9CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC10CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC11CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC12CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC13CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC14CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCSOC15CTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCEVTSTAT register // //***************************************************************************** // High Flag // Low Flag // Crossing Flag // High Flag // Low Flag // Crossing Flag // High Flag // Low Flag // Crossing Flag // High Flag // Low Flag // Crossing Flag //***************************************************************************** // // The following are defines for the bit fields in the ADCEVTCLR register // //***************************************************************************** // High Clear // Low Clear // Crossing Clear // High Clear // Low Clear // Crossing Clear // High Clear // Low Clear // Crossing Clear // High Clear // Low Clear // Crossing Clear //***************************************************************************** // // The following are defines for the bit fields in the ADCEVTSEL register // //***************************************************************************** // High Event Enable // Low Event Enable // Crossing Event Enable // High Event Enable // Low Event Enable // Crossing Event Enable // High Event Enable // Low Event Enable // Crossing Event Enable // High Event Enable // Low Event Enable // Crossing Event Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCEVTINTSEL register // //***************************************************************************** // High Interrupt Enable // Low Interrupt Enable // Crossing Interrupt Enable // High Interrupt Enable // Low Interrupt Enable // Crossing Interrupt Enable // High Interrupt Enable // Low Interrupt Enable // Crossing Interrupt Enable // High Interrupt Enable // Low Interrupt Enable // Crossing Interrupt Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCCOUNTER register // //***************************************************************************** // Value //***************************************************************************** // // The following are defines for the bit fields in the ADCREV register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCOFFTRIM register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB1CONFIG register // //***************************************************************************** // Configuration // Two's Complement Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB1STAMP register // //***************************************************************************** // Delay Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB1OFFCAL register // //***************************************************************************** // Offset Correction //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB1TRIPHI register // //***************************************************************************** // Trip High Limit //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB1TRIPLO register // //***************************************************************************** // Trip Low Limit // Request Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB2CONFIG register // //***************************************************************************** // Configuration // Two's Complement Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB2STAMP register // //***************************************************************************** // Delay Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB2OFFCAL register // //***************************************************************************** // Offset Correction //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB2TRIPHI register // //***************************************************************************** // Trip High Limit //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB2TRIPLO register // //***************************************************************************** // Trip Low Limit // Request Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB3CONFIG register // //***************************************************************************** // Configuration // Two's Complement Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB3STAMP register // //***************************************************************************** // Delay Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB3OFFCAL register // //***************************************************************************** // Offset Correction //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB3TRIPHI register // //***************************************************************************** // Trip High Limit //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB3TRIPLO register // //***************************************************************************** // Trip Low Limit // Request Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB4CONFIG register // //***************************************************************************** // Configuration // Two's Complement Enable //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB4STAMP register // //***************************************************************************** // Delay Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB4OFFCAL register // //***************************************************************************** // Offset Correction //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB4TRIPHI register // //***************************************************************************** // Trip High Limit //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB4TRIPLO register // //***************************************************************************** // Trip Low Limit // Request Time Stamp //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB1RESULT register // //***************************************************************************** // Result //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB2RESULT register // //***************************************************************************** // Result //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB3RESULT register // //***************************************************************************** // Result //***************************************************************************** // // The following are defines for the bit fields in the ADCPPB4RESULT register // //***************************************************************************** // Result //########################################################################### // // FILE: hw_asysctl.h // // TITLE: Definitions for the ASYSCTL registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the ASYSCTL register offsets // //***************************************************************************** // Peripheral Properties register // Register // Register // many sources on CopmHP inputs. // Refer to Pimux diagram for // details. // many sources on CopmLP inputs. // Refer to Pimux diagram for // details. // many sources on CopmHN inputs. // Refer to Pimux diagram for // details. // many sources on CopmLN inputs. // Refer to Pimux diagram for // details. //***************************************************************************** // // The following are defines for the bit fields in the ANAREFPP register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TSNSCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ANAREFCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCDCCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCDCSTS register // //***************************************************************************** // done. //***************************************************************************** // // The following are defines for the bit fields in the CMPHPMXSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPLPMXSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPHNMXSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPLNMXSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LOCK register // //***************************************************************************** //########################################################################### // // FILE: hw_types.h // // TITLE: Type definitions used in driverlib functions. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // Macros for hardware access // //***************************************************************************** //***************************************************************************** // // SUCCESS and FAILURE for API return value // //***************************************************************************** //***************************************************************************** // // 32-bit & 64-bit float type // //***************************************************************************** typedef float float32_t; typedef long double float64_t; //***************************************************************************** // // Extern compiler intrinsic prototypes. See compiler User's Guide for details. // These are provided to satisfy static analysis tools. The #ifndef is required // because the '&' is for a C++-style reference, and although it is the correct // prototype, it will not build in C code. // //***************************************************************************** //########################################################################### // // FILE: cpu.h // // TITLE: Useful C28x CPU defines. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** // // External reference to the interrupt flag register (IFR) register // extern __cregister volatile uint16_t IFR; // // External reference to the interrupt enable register (IER) register // extern __cregister volatile uint16_t IER; // // Define to enable interrupts // // // Define to disable interrupts // // // Define to enable debug events // // // Define to disable debug events // // // Define to allow writes to protected registers // // // Define to disable writes to protected registers // // // Define for emulation stop // // // Define for emulation stop // // // Define for no operation // // // Define for putting processor into a low-power mode // //***************************************************************************** // // Extern compiler intrinsic prototypes. See compiler User's Guide for details. // //***************************************************************************** extern void __eallow(void); extern void __edis(void); //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: debug.h // // TITLE: Assert definition macro for debug. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // Prototype for the function that is called when an invalid argument is passed // to an API. This is only used when doing a DEBUG build. It is the // application's responsibility to define the __error__ function. // //***************************************************************************** extern void __error__(char *filename, uint32_t line); //***************************************************************************** // // The ASSERT macro, which does the actual assertion checking. Typically, this // will be for procedure arguments. // //***************************************************************************** //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(), // ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and // ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also // make up the enumerated bit field returned by ADC_getPPBEventStatus(). // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to ADC_setPrescaler() as the \e clkPrescale //! parameter. // //***************************************************************************** typedef enum { ADC_CLK_DIV_1_0 = 0, //!< ADCCLK = (input clock) / 1.0 ADC_CLK_DIV_2_0 = 2, //!< ADCCLK = (input clock) / 2.0 ADC_CLK_DIV_2_5 = 3, //!< ADCCLK = (input clock) / 2.5 ADC_CLK_DIV_3_0 = 4, //!< ADCCLK = (input clock) / 3.0 ADC_CLK_DIV_3_5 = 5, //!< ADCCLK = (input clock) / 3.5 ADC_CLK_DIV_4_0 = 6, //!< ADCCLK = (input clock) / 4.0 ADC_CLK_DIV_4_5 = 7, //!< ADCCLK = (input clock) / 4.5 ADC_CLK_DIV_5_0 = 8, //!< ADCCLK = (input clock) / 5.0 ADC_CLK_DIV_5_5 = 9, //!< ADCCLK = (input clock) / 5.5 ADC_CLK_DIV_6_0 = 10, //!< ADCCLK = (input clock) / 6.0 ADC_CLK_DIV_6_5 = 11, //!< ADCCLK = (input clock) / 6.5 ADC_CLK_DIV_7_0 = 12, //!< ADCCLK = (input clock) / 7.0 ADC_CLK_DIV_7_5 = 13, //!< ADCCLK = (input clock) / 7.5 ADC_CLK_DIV_8_0 = 14, //!< ADCCLK = (input clock) / 8.0 ADC_CLK_DIV_8_5 = 15 //!< ADCCLK = (input clock) / 8.5 } ADC_ClkPrescale; //***************************************************************************** // //! Values that can be passed to ADC_setupSOC() as the \e trigger //! parameter to specify the event that will trigger a conversion to start. //! It is also used with ADC_setBurstModeConfig(). // //***************************************************************************** typedef enum { ADC_TRIGGER_SW_ONLY = 0, //!< Software only ADC_TRIGGER_CPU1_TINT0 = 1, //!< CPU1 Timer 0, TINT0 ADC_TRIGGER_CPU1_TINT1 = 2, //!< CPU1 Timer 1, TINT1 ADC_TRIGGER_CPU1_TINT2 = 3, //!< CPU1 Timer 2, TINT2 ADC_TRIGGER_GPIO = 4, //!< GPIO, ADCEXTSOC ADC_TRIGGER_EPWM1_SOCA = 5, //!< ePWM1, ADCSOCA ADC_TRIGGER_EPWM1_SOCB = 6, //!< ePWM1, ADCSOCB ADC_TRIGGER_EPWM2_SOCA = 7, //!< ePWM2, ADCSOCA ADC_TRIGGER_EPWM2_SOCB = 8, //!< ePWM2, ADCSOCB ADC_TRIGGER_EPWM3_SOCA = 9, //!< ePWM3, ADCSOCA ADC_TRIGGER_EPWM3_SOCB = 10, //!< ePWM3, ADCSOCB ADC_TRIGGER_EPWM4_SOCA = 11, //!< ePWM4, ADCSOCA ADC_TRIGGER_EPWM4_SOCB = 12, //!< ePWM4, ADCSOCB ADC_TRIGGER_EPWM5_SOCA = 13, //!< ePWM5, ADCSOCA ADC_TRIGGER_EPWM5_SOCB = 14, //!< ePWM5, ADCSOCB ADC_TRIGGER_EPWM6_SOCA = 15, //!< ePWM6, ADCSOCA ADC_TRIGGER_EPWM6_SOCB = 16, //!< ePWM6, ADCSOCB ADC_TRIGGER_EPWM7_SOCA = 17, //!< ePWM7, ADCSOCA ADC_TRIGGER_EPWM7_SOCB = 18, //!< ePWM7, ADCSOCB ADC_TRIGGER_EPWM8_SOCA = 19, //!< ePWM8, ADCSOCA ADC_TRIGGER_EPWM8_SOCB = 20 //!< ePWM8, ADCSOCB } ADC_Trigger; //***************************************************************************** // //! Values that can be passed to ADC_setupSOC() as the \e channel //! parameter. This is the input pin on which the signal to be converted is //! located. // //***************************************************************************** typedef enum { ADC_CH_ADCIN0, //!< ADCIN0 is converted ADC_CH_ADCIN1, //!< ADCIN1 is converted ADC_CH_ADCIN2, //!< ADCIN2 is converted ADC_CH_ADCIN3, //!< ADCIN3 is converted ADC_CH_ADCIN4, //!< ADCIN4 is converted ADC_CH_ADCIN5, //!< ADCIN5 is converted ADC_CH_ADCIN6, //!< ADCIN6 is converted ADC_CH_ADCIN7, //!< ADCIN7 is converted ADC_CH_ADCIN8, //!< ADCIN8 is converted ADC_CH_ADCIN9, //!< ADCIN9 is converted ADC_CH_ADCIN10, //!< ADCIN10 is converted ADC_CH_ADCIN11, //!< ADCIN11 is converted ADC_CH_ADCIN12, //!< ADCIN12 is converted ADC_CH_ADCIN13, //!< ADCIN13 is converted ADC_CH_ADCIN14, //!< ADCIN14 is converted ADC_CH_ADCIN15 //!< ADCIN15 is converted } ADC_Channel; //***************************************************************************** // //! Values that can be passed to ADC_setInterruptPulseMode() as the //! \e pulseMode parameter. // //***************************************************************************** typedef enum { //! Occurs at the end of the acquisition window ADC_PULSE_END_OF_ACQ_WIN = 0x00, //! Occurs at the end of the conversion ADC_PULSE_END_OF_CONV = 0x04 } ADC_PulseMode; //***************************************************************************** // //! Values that can be passed to ADC_enableInterrupt(), ADC_disableInterrupt(), //! and ADC_getInterruptStatus() as the \e adcIntNum parameter. // //***************************************************************************** typedef enum { ADC_INT_NUMBER1, //!< ADCINT1 Interrupt ADC_INT_NUMBER2, //!< ADCINT2 Interrupt ADC_INT_NUMBER3, //!< ADCINT3 Interrupt ADC_INT_NUMBER4 //!< ADCINT4 Interrupt } ADC_IntNumber; //***************************************************************************** // //! Values that can be passed in as the \e ppbNumber parameter for several //! functions. // //***************************************************************************** typedef enum { ADC_PPB_NUMBER1, //!< Post-processing block 1 ADC_PPB_NUMBER2, //!< Post-processing block 2 ADC_PPB_NUMBER3, //!< Post-processing block 3 ADC_PPB_NUMBER4 //!< Post-processing block 4 } ADC_PPBNumber; //***************************************************************************** // //! Values that can be passed in as the \e socNumber parameter for several //! functions. This value identifies the start-of-conversion (SOC) that a //! function is configuring or accessing. Note that in some cases (for example, //! ADC_setInterruptSource()) \e socNumber is used to refer to the //! corresponding end-of-conversion (EOC). // //***************************************************************************** typedef enum { ADC_SOC_NUMBER0, //!< SOC/EOC number 0 ADC_SOC_NUMBER1, //!< SOC/EOC number 1 ADC_SOC_NUMBER2, //!< SOC/EOC number 2 ADC_SOC_NUMBER3, //!< SOC/EOC number 3 ADC_SOC_NUMBER4, //!< SOC/EOC number 4 ADC_SOC_NUMBER5, //!< SOC/EOC number 5 ADC_SOC_NUMBER6, //!< SOC/EOC number 6 ADC_SOC_NUMBER7, //!< SOC/EOC number 7 ADC_SOC_NUMBER8, //!< SOC/EOC number 8 ADC_SOC_NUMBER9, //!< SOC/EOC number 9 ADC_SOC_NUMBER10, //!< SOC/EOC number 10 ADC_SOC_NUMBER11, //!< SOC/EOC number 11 ADC_SOC_NUMBER12, //!< SOC/EOC number 12 ADC_SOC_NUMBER13, //!< SOC/EOC number 13 ADC_SOC_NUMBER14, //!< SOC/EOC number 14 ADC_SOC_NUMBER15 //!< SOC/EOC number 15 } ADC_SOCNumber; //***************************************************************************** // //! Values that can be passed in as the \e trigger parameter for the //! ADC_setInterruptSOCTrigger() function. // //***************************************************************************** typedef enum { ADC_INT_SOC_TRIGGER_NONE, //!< No ADCINT will trigger the SOC ADC_INT_SOC_TRIGGER_ADCINT1, //!< ADCINT1 will trigger the SOC ADC_INT_SOC_TRIGGER_ADCINT2 //!< ADCINT2 will trigger the SOC } ADC_IntSOCTrigger; //***************************************************************************** // //! Values that can be passed to ADC_setSOCPriority() as the \e priMode //! parameter. // //***************************************************************************** typedef enum { ADC_PRI_ALL_ROUND_ROBIN, //!< Round robin mode is used for all ADC_PRI_SOC0_HIPRI, //!< SOC 0 hi pri, others in round robin ADC_PRI_THRU_SOC1_HIPRI, //!< SOC 0-1 hi pri, others in round robin ADC_PRI_THRU_SOC2_HIPRI, //!< SOC 0-2 hi pri, others in round robin ADC_PRI_THRU_SOC3_HIPRI, //!< SOC 0-3 hi pri, others in round robin ADC_PRI_THRU_SOC4_HIPRI, //!< SOC 0-4 hi pri, others in round robin ADC_PRI_THRU_SOC5_HIPRI, //!< SOC 0-5 hi pri, others in round robin ADC_PRI_THRU_SOC6_HIPRI, //!< SOC 0-6 hi pri, others in round robin ADC_PRI_THRU_SOC7_HIPRI, //!< SOC 0-7 hi pri, others in round robin ADC_PRI_THRU_SOC8_HIPRI, //!< SOC 0-8 hi pri, others in round robin ADC_PRI_THRU_SOC9_HIPRI, //!< SOC 0-9 hi pri, others in round robin ADC_PRI_THRU_SOC10_HIPRI, //!< SOC 0-10 hi pri, others in round robin ADC_PRI_THRU_SOC11_HIPRI, //!< SOC 0-11 hi pri, others in round robin ADC_PRI_THRU_SOC12_HIPRI, //!< SOC 0-12 hi pri, others in round robin ADC_PRI_THRU_SOC13_HIPRI, //!< SOC 0-13 hi pri, others in round robin ADC_PRI_THRU_SOC14_HIPRI, //!< SOC 0-14 hi pri, SOC15 in round robin ADC_PRI_ALL_HIPRI //!< All priorities based on SOC number } ADC_PriorityMode; //***************************************************************************** // //! Values that can be passed to ADC_getTemperatureC(), ADC_getTemperatureK(), //! and ADC_setVREF() as the \e refMode parameter. // //***************************************************************************** typedef enum { ADC_REFERENCE_INTERNAL, ADC_REFERENCE_EXTERNAL } ADC_ReferenceMode; //***************************************************************************** // //! Values that can be passed to ADC_setVREF() as the \e refVoltage parameter. // //***************************************************************************** typedef enum { ADC_REFERENCE_3_3V, ADC_REFERENCE_2_5V } ADC_ReferenceVoltage; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks an ADC base address. //! //! \param base specifies the ADC module base address. //! //! This function determines if a ADC module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Configures the analog-to-digital converter module prescaler. //! //! \param base is the base address of the ADC module. //! \param clkPrescale is the ADC clock prescaler. //! //! This function configures the ADC module's ADCCLK. //! //! The \e clkPrescale parameter specifies the value by which the input clock //! is divided to make the ADCCLK. The value can be specified with the value //! \b ADC_CLK_DIV_1_0, \b ADC_CLK_DIV_2_0, \b ADC_CLK_DIV_2_5, ..., //! \b ADC_CLK_DIV_7_5, \b ADC_CLK_DIV_8_0, or \b ADC_CLK_DIV_8_5. //! //! \return None. // //***************************************************************************** static inline void ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale) { // // Check the arguments. // ; // // Set the configuration of the ADC module prescaler. // __eallow(); (*((volatile uint16_t *)(base + 0x1U))) = ((*((volatile uint16_t *)(base + 0x1U))) & ~0xFU) | (uint16_t)clkPrescale; __edis(); } //***************************************************************************** // //! Configures a start-of-conversion (SOC) in the ADC. //! //! \param base is the base address of the ADC module. //! \param socNumber is the number of the start-of-conversion. //! \param trigger the source that will cause the SOC. //! \param channel is the number associated with the input signal. //! \param sampleWindow is the acquisition window duration. //! //! This function configures the a start-of-conversion (SOC) in the ADC module. //! //! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number //! from 0 to 15 specifying which SOC is to be configured on the ADC module //! specified by \e base. //! //! The \e trigger specifies the event that causes the SOC such as software, a //! timer interrupt, an ePWM event, or an ADC interrupt. It should be a value //! in the format of \b ADC_TRIGGER_XXXX where XXXX is the event such as //! \b ADC_TRIGGER_SW_ONLY, \b ADC_TRIGGER_CPU1_TINT0, \b ADC_TRIGGER_GPIO, //! \b ADC_TRIGGER_EPWM1_SOCA, and so on. //! //! The \e channel parameter specifies the channel to be converted. In //! single-ended mode this is a single pin given by \b ADC_CH_ADCINx where x is //! the number identifying the pin between 0 and 15 inclusive. //! //! The \e sampleWindow parameter is the acquisition window duration in SYSCLK //! cycles. It should be a value between 1 and 512 cycles inclusive. The //! selected duration must be at least as long as one ADCCLK cycle. Also, the //! datasheet will specify a minimum window duration requirement in //! nanoseconds. //! //! \return None. // //***************************************************************************** static inline void ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, ADC_Channel channel, uint32_t sampleWindow) { uint32_t ctlRegAddr; // // Check the arguments. // ; ; // // Calculate address for the SOC control register. // ctlRegAddr = base + 0x10U + ((uint32_t)socNumber * 2U); // // Set the configuration of the specified SOC. // __eallow(); (*((volatile uint32_t *)(ctlRegAddr))) = ((uint32_t)channel << 15U) | ((uint32_t)trigger << 20U) | (sampleWindow - 1U); __edis(); } //***************************************************************************** // //! Configures the interrupt SOC trigger of an SOC. //! //! \param base is the base address of the ADC module. //! \param socNumber is the number of the start-of-conversion. //! \param trigger the interrupt source that will cause the SOC. //! //! This function configures the an interrupt start-of-conversion trigger in //! the ADC module. //! //! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number //! from 0 to 15 specifying which SOC is to be configured on the ADC module //! specified by \e base. //! //! The \e trigger specifies the interrupt that causes a start of conversion or //! none. It should be one of the following values. //! //! - \b ADC_INT_SOC_TRIGGER_NONE //! - \b ADC_INT_SOC_TRIGGER_ADCINT1 //! - \b ADC_INT_SOC_TRIGGER_ADCINT2 //! //! This functionality is useful for creating continuous conversions. //! //! \return None. // //***************************************************************************** static inline void ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, ADC_IntSOCTrigger trigger) { uint16_t shiftVal; // // Check the arguments. // ; // // Each SOC has a 2-bit field in this register. // shiftVal = (uint16_t)socNumber << 1U; // // Set the configuration of the specified SOC. Not that we're treating // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here. // __eallow(); (*((volatile uint32_t *)(base + 0xAU))) = ((*((volatile uint32_t *)(base + 0xAU))) & ~((uint32_t)0x3U << shiftVal)) | ((uint32_t)trigger << shiftVal); __edis(); } //***************************************************************************** // //! Sets the timing of the end-of-conversion pulse //! //! \param base is the base address of the ADC module. //! \param pulseMode is the generation mode of the EOC pulse. //! //! This function configures the end-of-conversion (EOC) pulse generated by the //! ADC. This pulse will be generated either at the end of the acquisition //! window (pass \b ADC_PULSE_END_OF_ACQ_WIN into \e pulseMode) or at the end //! of the voltage conversion, one cycle prior to the ADC result latching into //! its result register (pass \b ADC_PULSE_END_OF_CONV into \e pulseMode). //! //! \return None. // //***************************************************************************** static inline void ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode) { // // Check the arguments. // ; // // Set the position of the pulse. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~0x4U) | (uint16_t)pulseMode; __edis(); } //***************************************************************************** // //! Sets the timing of early interrupt generation. //! //! \param base is the base address of the ADC module. //! \param cycleOffset is the cycles from an SOC falling edge to an early //! interrupt pulse. //! //! This function configures cycle offset between the negative edge of a sample //! pulse and an early interrupt pulse being generated. This number of cycles //! is specified with the \e cycleOffset parameter. //! //! This function only applies when early interrupt generation is enabled. That //! means the ADC_setInterruptPulseMode() function \e pulseMode parameter is //! configured as \b ADC_PULSE_END_OF_ACQ_WIN. //! //! \return None. // //***************************************************************************** static inline void ADC_setInterruptCycleOffset(uint32_t base, uint16_t cycleOffset) { // // Check the arguments. // ; // // Set the position of the pulse. // __eallow(); (*((volatile uint16_t *)(base + 0x6FU))) = cycleOffset; __edis(); } //***************************************************************************** // //! Powers up the analog-to-digital converter core. //! //! \param base is the base address of the ADC module. //! //! This function powers up the analog circuitry inside the analog core. //! //! \note Allow at least a 500us delay before sampling after calling this API. //! If you enable multiple ADCs, you can delay after they all have begun //! powering up. //! //! \return None. // //***************************************************************************** static inline void ADC_enableConverter(uint32_t base) { // // Check the arguments. // ; // // Set the bit that powers up the analog circuitry. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= 0x80U; __edis(); } //***************************************************************************** // //! Powers down the analog-to-digital converter module. //! //! \param base is the base address of the ADC module. //! //! This function powers down the analog circuitry inside the analog core. //! //! \return None. // //***************************************************************************** static inline void ADC_disableConverter(uint32_t base) { // // Check the arguments. // ; // // Clear the bit that powers down the analog circuitry. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) &= ~0x80U; __edis(); } //***************************************************************************** // //! Forces a SOC flag to a 1 in the analog-to-digital converter. //! //! \param base is the base address of the ADC module. //! \param socNumber is the number of the start-of-conversion. //! //! This function forces the SOC flag associated with the SOC specified by //! \e socNumber. This initiates a conversion once that SOC is given //! priority. This software trigger can be used whether or not the SOC has been //! configured to accept some other specific trigger. //! //! \return None. // //***************************************************************************** static inline void ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber) { // // Check the arguments. // ; // // Write to the register that will force a 1 to the corresponding SOC flag // (*((volatile uint16_t *)(base + 0xDU))) |= (1U << (uint16_t)socNumber); } //***************************************************************************** // //! Gets the current ADC interrupt status. //! //! \param base is the base address of the ADC module. //! \param adcIntNum is interrupt number within the ADC wrapper. //! //! This function returns the interrupt status for the analog-to-digital //! converter. //! //! \return \b true if the interrupt flag for the specified interrupt number is //! set and \b false if it is not. // //***************************************************************************** static inline _Bool ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) { // // Check the arguments. // ; // // Get the specified ADC interrupt status. // return(((*((volatile uint16_t *)(base + 0x3U))) & (1U << (uint16_t)adcIntNum)) != 0U); } //***************************************************************************** // //! Clears ADC interrupt sources. //! //! \param base is the base address of the ADC module. //! \param adcIntNum is interrupt number within the ADC wrapper. //! //! This function clears the specified ADC interrupt sources so that they no //! longer assert. If not in continuous mode, this function must be called //! before any further interrupt pulses may occur. //! //! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, //! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3, \b or ADC_INT_NUMBER4 to express //! which of the four interrupts of the ADC module should be cleared //! //! \return None. // //***************************************************************************** static inline void ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) { // // Check the arguments. // ; // // Clear the specified interrupt. // (*((volatile uint16_t *)(base + 0x4U))) |= 1U << (uint16_t)adcIntNum; } //***************************************************************************** // //! Reads the conversion result. //! //! \param resultBase is the base address of the ADC results. //! \param socNumber is the number of the start-of-conversion. //! //! This function returns the conversion result that corresponds to the base //! address passed into \e resultBase and the SOC passed into \e socNumber. //! //! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number //! from 0 to 15 specifying which SOC's result is to be read. //! //! \note Take care that you are using a base address for the result registers //! (ADCxRESULT_BASE) and not a base address for the control registers. //! //! \return Returns the conversion result. // //***************************************************************************** static inline uint16_t ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber) { uint16_t* resAddr; // // Check the arguments. // ; // // Get the address to the appropriate result. // resAddr = (uint16_t*)(resultBase + 0x0U); // // Return the result found at that address and offset. // return(resAddr[socNumber]); } //***************************************************************************** // //! Determines whether the ADC is busy or not. //! //! \param base is the base address of the ADC. //! //! This function allows the caller to determine whether or not the ADC is //! busy and can sample another channel. //! //! \return Returns \b true if the ADC is sampling or \b false if all //! samples are complete. // //***************************************************************************** static inline _Bool ADC_isBusy(uint32_t base) { // // Check the arguments. // ; // // Determine if the ADC is busy. // return(((*((volatile uint16_t *)(base + 0x0U))) & 0x2000U) != 0U); } //***************************************************************************** // //! Set SOC burst mode. //! //! \param base is the base address of the ADC. //! \param trigger the source that will cause the burst conversion sequence. //! \param burstSize is the number of SOCs converted during a burst sequence. //! //! This function configures the burst trigger and burstSize of an ADC module. //! Burst mode allows a single trigger to walk through the round-robin SOCs one //! or more at a time. When burst mode is enabled, the trigger selected by the //! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin //! mode. Instead, the source specified through the \e trigger parameter will //! cause a burst of \e burstSize conversions to occur. //! //! The \e trigger parameter takes the same values as the ADC_setupSOC() API //! The \e burstSize parameter should be a value between 1 and 16 inclusive. //! //! \return None. // //***************************************************************************** static inline void ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize) { uint16_t regValue; // // Check the arguments. // ; ; ; // // Write the burst mode configuration to the register. // __eallow(); regValue = (uint16_t)trigger | ((burstSize - 1U) << 8U); (*((volatile uint16_t *)(base + 0x2U))) = ((*((volatile uint16_t *)(base + 0x2U))) & ~((uint16_t)0x3FU | 0xF00U)) | regValue; __edis(); } //***************************************************************************** // //! Enables SOC burst mode. //! //! \param base is the base address of the ADC. //! //! This function enables SOC burst mode operation of the ADC. Burst mode //! allows a single trigger to walk through the round-robin SOCs one or more at //! a time. When burst mode is enabled, the trigger selected by the //! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin //! mode. Use ADC_setBurstMode() to configure the burst trigger and size. //! //! \return None. // //***************************************************************************** static inline void ADC_enableBurstMode(uint32_t base) { // // Check the arguments. // ; // // Enable burst mode. // __eallow(); (*((volatile uint16_t *)(base + 0x2U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Disables SOC burst mode. //! //! \param base is the base address of the ADC. //! //! This function disables SOC burst mode operation of the ADC. SOCs in //! round-robin mode will be triggered by the trigger configured using the //! ADC_setupSOC() API. //! //! \return None. // //***************************************************************************** static inline void ADC_disableBurstMode(uint32_t base) { // // Check the arguments. // ; // // Disable burst mode. // __eallow(); (*((volatile uint16_t *)(base + 0x2U))) &= ~0x8000U; __edis(); } //***************************************************************************** // //! Sets the priority mode of the SOCs. //! //! \param base is the base address of the ADC. //! \param priMode is the priority mode of the SOCs. //! //! This function sets the priority mode of the SOCs. There are three main //! modes that can be passed in the \e priMode parameter //! //! - All SOCs are in round-robin mode. This means no SOC has an inherent //! higher priority over another. This is selected by passing in the value //! \b ADC_PRI_ALL_ROUND_ROBIN. //! - All priorities are in high priority mode. This means that the priority of //! the SOC is determined by its SOC number. This option is selected by passing //! in the value \b ADC_PRI_ALL_HIPRI. //! - A range of SOCs are assigned high priority, with all others in round //! robin mode. High priority mode means that an SOC with high priority will //! interrupt the round robin wheel and insert itself as the next conversion. //! Passing in the value \b ADC_PRI_SOC0_HIPRI will make SOC0 highest priority, //! \b ADC_PRI_THRU_SOC1_HIPRI will put SOC0 and SOC 1 in high priority, and so //! on up to \b ADC_PRI_THRU_SOC14_HIPRI where SOCs 0 through 14 are in high //! priority. //! //! \return None. // //***************************************************************************** static inline void ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x1FU) | (uint16_t)priMode; __edis(); } //***************************************************************************** // //! Configures a post-processing block (PPB) in the ADC. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param socNumber is the number of the start-of-conversion. //! //! This function associates a post-processing block with a SOC. //! //! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to //! 4 inclusive that identifies a PPB to be configured. The \e socNumber //! number is a value \b ADC_SOC_NUMBERX where X is a number from 0 to 15 //! specifying which SOC is to be configured on the ADC module specified by //! \e base. //! //! \note You can have more that one PPB associated with the same SOC, but a //! PPB can only be configured to correspond to one SOC at a time. Also note //! that when you have multiple PPBs for the same SOC, the calibration offset //! that actually gets applied will be that of the PPB with the highest number. //! Since SOC0 is the default for all PPBs, look out for unintentional //! overwriting of a lower numbered PPB's offset. //! //! \return None. // //***************************************************************************** static inline void ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber) { uint32_t ppbOffset; // // Check the arguments. // ; // // Get the offset to the appropriate PPB configuration register. // ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U; // // Write the configuration to the register. // __eallow(); (*((volatile uint16_t *)(base + ppbOffset))) = ((*((volatile uint16_t *)(base + ppbOffset))) & ~0xFU) | ((uint16_t)socNumber & 0xFU); __edis(); } //***************************************************************************** // //! Enables individual ADC PPB event sources. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param evtFlags is a bit mask of the event sources to be enabled. //! //! This function enables the indicated ADC PPB event sources. This will allow //! the specified events to propagate through the X-BAR to a pin or to an ePWM //! module. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, //! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. //! //! \return None. // //***************************************************************************** static inline void ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) { // // Check the arguments. // ; ; // // Enable the specified event. // __eallow(); (*((volatile uint16_t *)(base + 0x34U))) |= evtFlags << ((uint16_t)ppbNumber * 4U); __edis(); } //***************************************************************************** // //! Disables individual ADC PPB event sources. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param evtFlags is a bit mask of the event sources to be enabled. //! //! This function disables the indicated ADC PPB event sources. This will stop //! the specified events from propagating through the X-BAR to other modules. //! The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, //! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. //! //! \return None. // //***************************************************************************** static inline void ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) { // // Check the arguments. // ; ; // // Disable the specified event. // __eallow(); (*((volatile uint16_t *)(base + 0x34U))) &= ~(evtFlags << ((uint16_t)ppbNumber * 4U)); __edis(); } //***************************************************************************** // //! Enables individual ADC PPB event interrupt sources. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param intFlags is a bit mask of the interrupt sources to be enabled. //! //! This function enables the indicated ADC PPB interrupt sources. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. The \e intFlags //! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, or //! \b ADC_EVT_ZERO values. //! //! \return None. // //***************************************************************************** static inline void ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t intFlags) { // // Check the arguments. // ; ; // // Enable the specified event interrupts. // __eallow(); (*((volatile uint16_t *)(base + 0x36U))) |= intFlags << ((uint16_t)ppbNumber * 4U); __edis(); } //***************************************************************************** // //! Disables individual ADC PPB event interrupt sources. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param intFlags is a bit mask of the interrupt source to be disabled. //! //! This function disables the indicated ADC PPB interrupt sources. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. The \e intFlags //! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, or //! \b ADC_EVT_ZERO values. //! //! \return None. // //***************************************************************************** static inline void ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t intFlags) { // // Check the arguments. // ; ; // // Disable the specified event interrupts. // __eallow(); (*((volatile uint16_t *)(base + 0x36U))) &= ~(intFlags << ((uint16_t)ppbNumber * 4U)); __edis(); } //***************************************************************************** // //! Gets the current ADC event status. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! //! This function returns the event status for the analog-to-digital converter. //! //! \return Returns the current event status, enumerated as a bit field of //! \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, and \b ADC_EVT_ZERO. // //***************************************************************************** static inline uint16_t ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber) { // // Check the arguments. // ; // // Get the event status for the specified post-processing block. // return(((*((volatile uint16_t *)(base + 0x30U))) >> ((uint16_t)ppbNumber * 4U)) & 0x7U); } //***************************************************************************** // //! Clears ADC event flags. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param evtFlags is a bit mask of the event source to be cleared. //! //! This function clears the indicated ADC PPB event flags. After an event //! occurs this function must be called to allow additional events to be //! produced. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, //! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. //! //! \return None. // //***************************************************************************** static inline void ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) { // // Check the arguments. // ; ; // // Clear the specified event interrupts. // (*((volatile uint16_t *)(base + 0x32U))) |= evtFlags << ((uint16_t)ppbNumber * 4U); } //***************************************************************************** // //! Reads the processed conversion result from the PPB. //! //! \param resultBase is the base address of the ADC results. //! \param ppbNumber is the number of the post-processing block. //! //! This function returns the processed conversion result that corresponds to //! the base address passed into \e resultBase and the PPB passed into //! \e ppbNumber. //! //! \note Take care that you are using a base address for the result registers //! (ADCxRESULT_BASE) and not a base address for the control registers. //! //! \return Returns the signed 32-bit conversion result. // //***************************************************************************** static inline int32_t ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber) { uint32_t *ppbRegAddr; // // Check the arguments. // ; // // Get the offset to the appropriate result. // ppbRegAddr = (uint32_t*)(resultBase + 0x10U); // // Return the result found at that address and offset. // return((int32_t)ppbRegAddr[ppbNumber]); } //***************************************************************************** // //! Reads sample delay time stamp from a PPB. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! //! This function returns the sample delay time stamp. This delay is the number //! of system clock cycles between the SOC being triggered and when it began //! converting. //! //! \return Returns the delay time stamp. // //***************************************************************************** static inline uint16_t ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber) { uint32_t ppbOffset; // // Check the arguments. // ; // // Get the offset to the appropriate delay. // ppbOffset = ((0x49U - 0x41U) * (uint32_t)ppbNumber) + 0x41U; // // Return the delay time stamp. // return((*((volatile uint16_t *)(base + ppbOffset))) & 0xFFFU); } //***************************************************************************** // //! Sets the post processing block offset correction. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param offset is the 10-bit signed value subtracted from ADC the output. //! //! This function sets the PPB offset correction value. This value can be used //! to digitally remove any system-level offset inherent in the ADCIN circuit //! before it is stored in the appropriate result register. The \e offset //! parameter is \b subtracted from the ADC output and is a signed value from //! -512 to 511 inclusive. For example, when \e offset = 1, ADCRESULT = ADC //! output - 1. When \e offset = -512, ADCRESULT = ADC output - (-512) or ADC //! output + 512. //! //! Passing a zero in to the \e offset parameter will effectively disable the //! calculation, allowing the raw ADC result to be passed unchanged into the //! result register. //! //! \note If multiple PPBs are applied to the same SOC, the offset that will be //! applied will be that of the PPB with the highest number. //! //! \return None // //***************************************************************************** static inline void ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, int16_t offset) { uint32_t ppbOffset; // // Check the arguments. // ; // // Get the offset to the appropriate offset register. // ppbOffset = ((0x4AU - 0x42U) * (uint32_t)ppbNumber) + 0x42U; // // Write the offset amount. // __eallow(); (*((volatile uint16_t *)(base + ppbOffset))) = ((*((volatile uint16_t *)(base + ppbOffset))) & ~0x3FFU) | ((uint16_t)offset & 0x3FFU); __edis(); } //***************************************************************************** // //! Sets the post processing block reference offset. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param offset is the 16-bit unsigned value subtracted from ADC the output. //! //! This function sets the PPB reference offset value. This can be used to //! either calculate the feedback error or convert a unipolar signal to bipolar //! by subtracting a reference value. The result will be stored in the //! appropriate PPB result register which can be read using ADC_readPPBResult(). //! //! Passing a zero in to the \e offset parameter will effectively disable the //! calculation and will pass the ADC result to the PPB result register //! unchanged. //! //! \note If in 12-bit mode, you may only pass a 12-bit value into the \e offset //! parameter. //! //! \return None // //***************************************************************************** static inline void ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t offset) { uint32_t ppbOffset; // // Check the arguments. // ; // // Get the offset to the appropriate offset register. // ppbOffset = ((0x4BU - 0x43U) * (uint32_t)ppbNumber) + 0x43U; // // Write the offset amount. // (*((volatile uint16_t *)(base + ppbOffset))) = offset; } //***************************************************************************** // //! Enables two's complement capability in the PPB. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! //! This function enables two's complement in the post-processing block //! specified by the \e ppbNumber parameter. When enabled, a two's complement //! will be performed on the output of the offset subtraction before it is //! stored in the appropriate PPB result register. In other words, the PPB //! result will be the reference offset value minus the the ADC result value //! (ADCPPBxRESULT = ADCSOCxOFFREF - ADCRESULTx). //! //! \return None // //***************************************************************************** static inline void ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) { uint32_t ppbOffset; // // Check the arguments. // ; // // Get the offset to the appropriate PPB configuration register. // ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U; // // Return the delay time stamp. // __eallow(); (*((volatile uint16_t *)(base + ppbOffset))) |= 0x10U; __edis(); } //***************************************************************************** // //! Disables two's complement capability in the PPB. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! //! This function disables two's complement in the post-processing block //! specified by the \e ppbNumber parameter. When disabled, a two's complement //! will \b NOT be performed on the output of the offset subtraction before it //! is stored in the appropriate PPB result register. In other words, the PPB //! result will be the ADC result value minus the reference offset value //! (ADCPPBxRESULT = ADCRESULTx - ADCSOCxOFFREF). //! //! \return None // //***************************************************************************** static inline void ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) { uint32_t ppbOffset; // // Check the arguments. // ; // // Get the offset to the appropriate PPB configuration register. // ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U; // // Return the delay time stamp. // __eallow(); (*((volatile uint16_t *)(base + ppbOffset))) &= ~0x10U; __edis(); } //***************************************************************************** // //! Enables an ADC interrupt source. //! //! \param base is the base address of the ADC module. //! \param adcIntNum is interrupt number within the ADC wrapper. //! //! This function enables the indicated ADC interrupt source. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2, //! \b ADC_INT_NUMBER3, \b or ADC_INT_NUMBER4 to express which of the four //! interrupts of the ADC module should be enabled. //! //! \return None. // //***************************************************************************** static inline void ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) { uint32_t intRegAddr; uint16_t shiftVal; // // Check the arguments. // ; // // Each INTSEL register manages two interrupts. If the interrupt number is // even, we'll be accessing the upper byte and will need to shift. // intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1); shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; // // Enable the specified ADC interrupt. // __eallow(); (*((volatile uint16_t *)(intRegAddr))) |= 0x20U << shiftVal; __edis(); } //***************************************************************************** // //! Disables an ADC interrupt source. //! //! \param base is the base address of the ADC module. //! \param adcIntNum is interrupt number within the ADC wrapper. //! //! This function disables the indicated ADC interrupt source. //! Only the sources that are enabled can be reflected to the processor //! interrupt. Disabled sources have no effect on the processor. //! //! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2, //! \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express which of the four //! interrupts of the ADC module should be disabled. //! //! \return None. // //***************************************************************************** static inline void ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) { uint32_t intRegAddr; uint16_t shiftVal; // // Check the arguments. // ; // // Each INTSEL register manages two interrupts. If the interrupt number is // even, we'll be accessing the upper byte and will need to shift. // intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1); shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; // // Disable the specified ADC interrupt. // __eallow(); (*((volatile uint16_t *)(intRegAddr))) &= ~(0x20U << shiftVal); __edis(); } //***************************************************************************** // //! Sets the source EOC for an analog-to-digital converter interrupt. //! //! \param base is the base address of the ADC module. //! \param adcIntNum is interrupt number within the ADC wrapper. //! \param socNumber is the number of the start-of-conversion. //! //! This function sets which conversion is the source of an ADC interrupt. //! //! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number //! from 0 to 15 specifying which EOC is to be configured on the ADC module //! specified by \e base. //! //! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2, //! \b ADC_INT_NUMBER3, \b or ADC_INT_NUMBER4 to express which of the four //! interrupts of the ADC module is being configured. //! //! \return None. // //***************************************************************************** static inline void ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, ADC_SOCNumber socNumber) { uint32_t intRegAddr; uint16_t shiftVal; // // Check the arguments. // ; // // Each INTSEL register manages two interrupts. If the interrupt number is // even, we'll be accessing the upper byte and will need to shift. // intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1); shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; // // Set the specified ADC interrupt source. // __eallow(); (*((volatile uint16_t *)(intRegAddr))) = ((*((volatile uint16_t *)(intRegAddr))) & ~(0xFU << shiftVal)) | ((uint16_t)socNumber << shiftVal); __edis(); } //***************************************************************************** // //! Enables continuous mode for an ADC interrupt. //! //! \param base is the base address of the ADC. //! \param adcIntNum is interrupt number within the ADC wrapper. //! //! This function enables continuous mode for the ADC interrupt passed into //! \e adcIntNum. This means that pulses will be generated for the specified //! ADC interrupt whenever an EOC pulse is generated irrespective of whether or //! not the flag bit is set. //! //! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2, //! \b ADC_INT_NUMBER3, \b or ADC_INT_NUMBER4 to express which of the four //! interrupts of the ADC module is being configured. //! //! \return None. // //***************************************************************************** static inline void ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) { uint32_t intRegAddr; uint16_t shiftVal; // // Check the arguments. // ; // // Each INTSEL register manages two interrupts. If the interrupt number is // even, we'll be accessing the upper byte and will need to shift. // intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1); shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; // // Enable continuous mode for the specified ADC interrupt. // __eallow(); (*((volatile uint16_t *)(intRegAddr))) |= 0x40U << shiftVal; __edis(); } //***************************************************************************** // //! Disables continuous mode for an ADC interrupt. //! //! \param base is the base address of the ADC. //! \param adcIntNum is interrupt number within the ADC wrapper. //! //! This function disables continuous mode for the ADC interrupt passed into //! \e adcIntNum. This means that pulses will not be generated for the //! specified ADC interrupt until the corresponding interrupt flag for the //! previous interrupt occurrence has been cleared using //! ADC_clearInterruptStatus(). //! //! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2, //! \b ADC_INT_NUMBER3, \b or ADC_INT_NUMBER4 to express which of the four //! interrupts of the ADC module is being configured. //! //! \return None. // //***************************************************************************** static inline void ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) { uint32_t intRegAddr; uint16_t shiftVal; // // Check the arguments. // ; // // Each INTSEL register manages two interrupts. If the interrupt number is // even, we'll be accessing the upper byte and will need to shift. // intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1); shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; // // Disable continuous mode for the specified ADC interrupt. // __eallow(); (*((volatile uint16_t *)(intRegAddr))) &= ~(0x40U << shiftVal); __edis(); } //***************************************************************************** // //! Converts temperature from sensor reading to degrees C //! //! \param tempResult is the raw ADC A conversion result from the temp sensor. //! \param vref is the reference voltage being used (for example 3.3 for 3.3V). //! //! This function converts temperature from temp sensor reading to degrees C. //! Temp sensor values in production test are derived with 2.5V reference. //! The \b vref argument in the function is used to scale the temp sensor //! reading accordingly if temp sensor value is read at a different VREF //! setting. //! //! \note Only external reference mode is supported for the temperature sensor. //! This function does not set the reference mode. Reference mode can be set //! using ADC_setVREF(). using ADC_setVREF(). //! //! \return Returns the temperature sensor reading converted to degrees C. // //***************************************************************************** static inline int16_t ADC_getTemperatureC(uint16_t tempResult, float32_t vref) { float32_t temp; // // Read temp sensor slope and offset locations from OTP and convert // temp = (float32_t)tempResult * (vref / 2.5F); return((int16_t)((((int32_t)temp - (*(int16_t *)0x705C0)) * 4096) / (*(int16_t *)0x705BF))); } //***************************************************************************** // //! Converts temperature from sensor reading to degrees K //! //! \param tempResult is the raw ADC A conversion result from the temp sensor. //! \param vref is the reference voltage being used (for example 3.3 for 3.3V). //! //! This function converts temperature from temp sensor reading to degrees K. //! Temp sensor values in production test are derived with 2.5V reference. //! The \b vref argument in the function is used to scale the temp sensor //! reading accordingly if temp sensor value is read at a different VREF //! setting. //! //! \note Only external reference mode is supported for the temperature sensor. //! This function does not set the reference mode. Reference mode can be set //! using ADC_setVREF(). using ADC_setVREF(). //! //! \return Returns the temperature sensor reading converted to degrees K. // //***************************************************************************** static inline int16_t ADC_getTemperatureK(uint16_t tempResult, float32_t vref) { float32_t temp; // // Read temp sensor slope and offset locations from OTP and convert // temp = (float32_t)tempResult * (vref / 2.5F); return((int16_t)(((((int32_t)temp - (*(int16_t *)0x705C0)) * 4096) / (*(int16_t *)0x705BF)) + 273)); } //***************************************************************************** // //! Configures the ADC module's reference mode and offset trim //! //! \param base is the base address of the ADC module. //! \param refMode is the reference mode being used (\b ADC_REFERENCE_INTERNAL //! or \b ADC_REFERENCE_EXTERNAL). //! \param refVoltage is the reference voltage being used //! (\b ADC_REFERENCE_2_5V or \b ADC_REFERENCE_3_3V). This is ignored //! when the reference mode is external. //! //! This function configures the ADC module's reference mode and loads the //! corresponding offset trims. //! //! \note When the \e refMode parameter is \b ADC_REFERENCE_EXTERNAL, the value //! of the \e refVoltage parameter has no effect on the operation of the ADC. //! //! \return None. // //***************************************************************************** extern void ADC_setVREF(uint32_t base, ADC_ReferenceMode refMode, ADC_ReferenceVoltage refVoltage); //***************************************************************************** // //! Sets the windowed trip limits for a PPB. //! //! \param base is the base address of the ADC module. //! \param ppbNumber is the number of the post-processing block. //! \param tripHiLimit is the value is the digital comparator trip high limit. //! \param tripLoLimit is the value is the digital comparator trip low limit. //! //! This function sets the windowed trip limits for a PPB. These values set //! the digital comparator so that when one of the values is exceeded, either a //! high or low trip event will occur. //! //! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to //! 4 inclusive that identifies a PPB to be configured. //! //! If using 16-bit mode, you may pass a 17-bit number into the \e tripHiLimit //! and \e tripLoLimit parameters where the 17th bit is the sign bit (that is //! a value from -65536 and 65535). In 12-bit mode, only bits 12:0 will be //! compared against bits 12:0 of the PPB result. //! //! //! \return None. // //***************************************************************************** extern void ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, int32_t tripHiLimit, int32_t tripLoLimit); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: asysctl.h // // TITLE: C28x driver for Analog System Control. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup asysctl_api ASysCtl //! @{ // //***************************************************************************** //***************************************************************************** // // Defines used for setting AnalogReference functions. // ASysCtl_setAnalogReferenceInternal() // ASysCtl_setAnalogReferenceExternal() // ASysCtl_setAnalogReference2P5() // ASysCtl_setAnalogReference1P65() // //***************************************************************************** //***************************************************************************** // // Values used for function ASysCtl_selectCMPHNMux(). These values can be // OR-ed together and passed to ASysCtl_selectCMPHNMux(). // //***************************************************************************** //***************************************************************************** // // Values used for function ASysCtl_selectCMPLNMux(). These values can be // OR-ed together and passed to ASysCtl_selectCMPLNMux(). // //***************************************************************************** //***************************************************************************** // //! ASysCtl_CMPHPMuxSelect used for function ASysCtl_selectCMPHPMux(). // //***************************************************************************** typedef enum { ASYSCTL_CMPHPMUX_SELECT_1 = 0x0U, //!< CMPHPMUX select 1 ASYSCTL_CMPHPMUX_SELECT_2 = 0x3U, //!< CMPHPMUX select 2 ASYSCTL_CMPHPMUX_SELECT_3 = 0x6U, //!< CMPHPMUX select 3 ASYSCTL_CMPHPMUX_SELECT_4 = 0x9U, //!< CMPHPMUX select 4 ASYSCTL_CMPHPMUX_SELECT_5 = 0xCU, //!< CMPHPMUX select 5 ASYSCTL_CMPHPMUX_SELECT_6 = 0x10U, //!< CMPHPMUX select 6 ASYSCTL_CMPHPMUX_SELECT_7 = 0x13U //!< CMPHPMUX select 7 } ASysCtl_CMPHPMuxSelect; //***************************************************************************** // //! ASysCtl_CMPLPMuxSelect used for function ASysCtl_selectCMPLPMux(). // //***************************************************************************** typedef enum { ASYSCTL_CMPLPMUX_SELECT_1 = 0x0U, //!< CMPLPMUX select 1 ASYSCTL_CMPLPMUX_SELECT_2 = 0x3U, //!< CMPLPMUX select 2 ASYSCTL_CMPLPMUX_SELECT_3 = 0x6U, //!< CMPLPMUX select 3 ASYSCTL_CMPLPMUX_SELECT_4 = 0x9U, //!< CMPLPMUX select 4 ASYSCTL_CMPLPMUX_SELECT_5 = 0xCU, //!< CMPLPMUX select 5 ASYSCTL_CMPLPMUX_SELECT_6 = 0x10U, //!< CMPLPMUX select 6 ASYSCTL_CMPLPMUX_SELECT_7 = 0x13U //!< CMPLPMUX select 7 } ASysCtl_CMPLPMuxSelect; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Enable temperature sensor. //! //! This function enables the temperature sensor output to the ADC. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_enableTemperatureSensor(void) { __eallow(); // // Set the temperature sensor enable bit. // (*((volatile uint16_t *)(0x0005D700U + 0x60U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disable temperature sensor. //! //! This function disables the temperature sensor output to the ADC. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_disableTemperatureSensor(void) { __eallow(); // // Clear the temperature sensor enable bit. // (*((volatile uint16_t *)(0x0005D700U + 0x60U))) &= ~(0x1U); __edis(); } //***************************************************************************** // //! Set the analog voltage reference selection to internal. //! //! \param reference is the analog reference. //! //! The parameter \e reference can be a combination of the following values: //! //! - \b ASYSCTL_VREFHIA //! - \b ASYSCTL_VREFHIB //! - \b ASYSCTL_VREFHIC //! //! \return None. // //***************************************************************************** static inline void ASysCtl_setAnalogReferenceInternal(uint16_t reference) { ; __eallow(); // // Write selection to the Analog Internal Reference Select bit. // (*((volatile uint16_t *)(0x0005D700U + 0x68U))) &= ~reference; __edis(); } //***************************************************************************** // //! Set the analog voltage reference selection to external. //! //! \param reference is the analog reference. //! //! The parameter \e reference can be a combination of the following values: //! //! - \b ASYSCTL_VREFHIA //! - \b ASYSCTL_VREFHIB //! - \b ASYSCTL_VREFHIC //! //! \return None. // //***************************************************************************** static inline void ASysCtl_setAnalogReferenceExternal(uint16_t reference) { ; __eallow(); // // Write selection to the Analog External Reference Select bit. // (*((volatile uint16_t *)(0x0005D700U + 0x68U))) |= reference; __edis(); } //***************************************************************************** // //! Set the external analog voltage reference selection to 2.5V. //! //! \param reference is the analog reference. //! //! The parameter \e reference can be a combination of the following values: //! //! - \b ASYSCTL_VREFHIA //! - \b ASYSCTL_VREFHIB //! - \b ASYSCTL_VREFHIC //! //! \return None. // //***************************************************************************** static inline void ASysCtl_setAnalogReference2P5(uint16_t reference) { ; __eallow(); // // Write selection to the Analog Voltage Reference Select bit. // (*((volatile uint16_t *)(0x0005D700U + 0x68U))) |= (reference << 8U); __edis(); } //***************************************************************************** // //! Set the external analog voltage reference selection to 1.65V. //! //! \param reference is the analog reference. //! //! The parameter \e reference can be a combination of the following values: //! //! - \b ASYSCTL_VREFHIA //! - \b ASYSCTL_VREFHIB //! - \b ASYSCTL_VREFHIC //! //! \return None. // //***************************************************************************** static inline void ASysCtl_setAnalogReference1P65(uint16_t reference) { ; __eallow(); // // Write selection to the Analog Voltage Reference Select bit. // (*((volatile uint16_t *)(0x0005D700U + 0x68U))) &= ~(reference << 8U); __edis(); } //***************************************************************************** // //! Enable DC-DC. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_enableDCDC(void) { __eallow(); // // Write 1 to enable bit. // (*((volatile uint32_t *)(0x0005D700U + 0x78U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disable DC-DC. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_disableDCDC(void) { __eallow(); // // Write 0 to enable bit. // (*((volatile uint32_t *)(0x0005D700U + 0x78U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Gets the inductor status. //! //! This function returns the inductor status. //! //! \return Return value \b true indicates that the external inductor connected //! to DC-DC is functional. Return value of \b false indicates it is faulty or //! not connected. // //***************************************************************************** static inline _Bool ASysCtl_getInductorFaultStatus(void) { // // Return the status the INDDETECT bit. // return(((*((volatile uint16_t *)(0x0005D700U + 0x7AU))) & 0x1U) == 0x1U); } //***************************************************************************** // //! Gets the Switch Sequence Status. //! //! This function returns the Switch Sequence Status. //! //! \return Return value \b false indicates that the switch to DC-DC is not //! complete. Return value of \b true indicates it is complete. // //***************************************************************************** static inline _Bool ASysCtl_getSwitchSequenceStatus(void) { // // Return the status the SWSEQDONE bit. // return(((*((volatile uint16_t *)(0x0005D700U + 0x7AU))) & 0x2U) == 0x2U); } //***************************************************************************** // //! Select the value for CMPHNMXSEL. //! //! \param select is a combination of CMPHNMXSEL values. //! //! The parameter \e select can be a bitwise OR of the below values: //! //! - \b ASYSCTL_CMPHNMUX_SELECT_1 //! - \b ASYSCTL_CMPHNMUX_SELECT_2 //! - \b ASYSCTL_CMPHNMUX_SELECT_3 //! - \b ASYSCTL_CMPHNMUX_SELECT_4 //! - \b ASYSCTL_CMPHNMUX_SELECT_5 //! - \b ASYSCTL_CMPHNMUX_SELECT_6 //! - \b ASYSCTL_CMPHNMUX_SELECT_7 //! //! \return None. // //***************************************************************************** static inline void ASysCtl_selectCMPHNMux(uint16_t select) { ; __eallow(); // // Write a select to the mux select bit. // (*((volatile uint16_t *)(0x0005D700U + 0x86U))) = select; __edis(); } //***************************************************************************** // //! Select the value for CMPLNMXSEL. //! //! \param select is a combination of CMPLNMXSEL values. //! //! The parameter \e select can be the bitwise OR of the below values: //! //! - \b ASYSCTL_CMPLNMUX_SELECT_1 //! - \b ASYSCTL_CMPLNMUX_SELECT_2 //! - \b ASYSCTL_CMPLNMUX_SELECT_3 //! - \b ASYSCTL_CMPLNMUX_SELECT_4 //! - \b ASYSCTL_CMPLNMUX_SELECT_5 //! - \b ASYSCTL_CMPLNMUX_SELECT_6 //! - \b ASYSCTL_CMPLNMUX_SELECT_7 //! //! \return None. // //***************************************************************************** static inline void ASysCtl_selectCMPLNMux(uint16_t select) { ; __eallow(); // // Write a select to the mux select bit. // (*((volatile uint16_t *)(0x0005D700U + 0x87U))) = select; __edis(); } //***************************************************************************** // //! Select the value for CMPHPMXSEL. //! //! \param select is of type ASysCtl_CMPHPMuxSelect. //! \param value is 0, 1, 2, 3, or 4. //! //! This function is used to write a value to one mux select at a time. //! The parameter \e select can be one of the following values: //! //! - \b ASYSCTL_CMPHPMUX_SELECT_1 //! - \b ASYSCTL_CMPHPMUX_SELECT_2 //! - \b ASYSCTL_CMPHPMUX_SELECT_3 //! - \b ASYSCTL_CMPHPMUX_SELECT_4 //! - \b ASYSCTL_CMPHPMUX_SELECT_5 //! - \b ASYSCTL_CMPHPMUX_SELECT_6 //! - \b ASYSCTL_CMPHPMUX_SELECT_7 //! //! \return None. // //***************************************************************************** static inline void ASysCtl_selectCMPHPMux(ASysCtl_CMPHPMuxSelect select, uint32_t value) { ; __eallow(); // // Set the value for the appropriate Mux Select. // (*((volatile uint32_t *)(0x0005D700U + 0x82U))) = ((*((volatile uint32_t *)(0x0005D700U + 0x82U))) & ~((uint32_t)0x7U << (uint32_t)select)) | (value << (uint32_t)select); __edis(); } //***************************************************************************** // //! Select the value for CMPLPMXSEL. //! //! \param select is of type ASysCtl_CMPLPMuxSelect. //! \param value is 0, 1, 2, 3, or 4. //! //! This function is used to write a value to one mux select at a time. //! The parameter \e select can be one of the following values: //! //! - \b ASYSCTL_CMPLPMUX_SELECT_1 //! - \b ASYSCTL_CMPLPMUX_SELECT_2 //! - \b ASYSCTL_CMPLPMUX_SELECT_3 //! - \b ASYSCTL_CMPLPMUX_SELECT_4 //! - \b ASYSCTL_CMPLPMUX_SELECT_5 //! - \b ASYSCTL_CMPLPMUX_SELECT_6 //! - \b ASYSCTL_CMPLPMUX_SELECT_7 //! //! \return None. // //***************************************************************************** static inline void ASysCtl_selectCMPLPMux(ASysCtl_CMPLPMuxSelect select, uint32_t value) { ; __eallow(); // // Set the value for the appropriate Mux Select. // (*((volatile uint32_t *)(0x0005D700U + 0x84U))) = ((*((volatile uint32_t *)(0x0005D700U + 0x84U))) & ~((uint32_t)0x7U << (uint32_t)select)) | (value << (uint32_t)select); __edis(); } //***************************************************************************** // //! Locks the temperature sensor control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockTemperatureSensor(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x1U; __edis(); } //***************************************************************************** // //! Locks the analog reference control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockANAREF(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x2U; __edis(); } //***************************************************************************** // //! Locks the voltage monitor control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockVMON(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x4U; __edis(); } //***************************************************************************** // //! Locks the DCDC control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockDCDC(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x8U; __edis(); } //***************************************************************************** // //! Locks the ADCIN control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockPGAADCINMux(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x10U; __edis(); } //***************************************************************************** // //! Locks the CMPHPMXSEL control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockCMPHPMux(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x20U; __edis(); } //***************************************************************************** // //! Locks the CMPLPMXSEL control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockCMPLPMux(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x40U; __edis(); } //***************************************************************************** // //! Locks the CMPHNMXSEL control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockCMPHNMux(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x80U; __edis(); } //***************************************************************************** // //! Locks the CMPLNMXSEL control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockCMPLNMux(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x100U; __edis(); } //***************************************************************************** // //! Locks the VREG control register. //! //! \return None. // //***************************************************************************** static inline void ASysCtl_lockVREG(void) { __eallow(); // // Write a 1 to the lock bit in the LOCK register. // (*((volatile uint16_t *)(0x0005D700U + 0x8EU))) |= 0x200U; __edis(); } //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: can.h // // TITLE: C28x CAN driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup can_api CAN //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_can.h // // TITLE: Definitions for the CAN registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the CAN register offsets // //***************************************************************************** // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the CAN_CTL register // //***************************************************************************** // Enable // Retransmission // Enable // Disabled //***************************************************************************** // // The following are defines for the bit fields in the CAN_ES register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_ERRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_BTR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_INT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_TEST register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_PERR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_RAM_INIT register // //***************************************************************************** // complete //***************************************************************************** // // The following are defines for the bit fields in the CAN_GLB_INT_EN register // //***************************************************************************** // CANINT0 // CANINT1 //***************************************************************************** // // The following are defines for the bit fields in the CAN_GLB_INT_FLG register // //***************************************************************************** // CANINT0 // CANINT1 //***************************************************************************** // // The following are defines for the bit fields in the CAN_GLB_INT_CLR register // //***************************************************************************** // for CANINT0 // for CANINT1 //***************************************************************************** // // The following are defines for the bit fields in the CAN_TXRQ_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_NDAT_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IPEN_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_MVAL_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1CMD register // //***************************************************************************** // Bit //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1MSK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1ARB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1DATB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2CMD register // //***************************************************************************** // Bit //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2MSK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2ARB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2DATB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3OBS register // //***************************************************************************** // observation // access // data read access // read access // access // access //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3MSK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3ARB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3DATB register // //***************************************************************************** //########################################################################### // // FILE: sysctl.h // // TITLE: C28x system control driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup sysctl_api SysCtl //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_nmi.h // // TITLE: Definitions for the NMI registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the NMI register offsets // //***************************************************************************** // Clear) //***************************************************************************** // // The following are defines for the bit fields in the NMICFG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the NMIFLG register // //***************************************************************************** // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the NMIFLGCLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the NMIFLGFRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the NMISHDFLG register // //***************************************************************************** //########################################################################### // // FILE: hw_sysctl.h // // TITLE: Definitions for the SYSCTL registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the SYSCTL register offsets // //***************************************************************************** // Identification Number // Identification Number // Reset register // register // register // register // register // register // register // register // register // register // register // register // register // register // register // & Debugger Connect // register-1 // register-2 // register-3 // register // register // Prescalar // Register // Address register // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // registers // registers // functionality control register // Register // Register // Select Lock Register // Select Lock Register // Select Register-1 // Select Register-2 // Select Register-1 // Select Register-2 // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Control Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // access to peripheral Access // register. // Register // Register // Lock register //***************************************************************************** // // The following are defines for the bit fields in the PARTIDL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PARTIDH register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the REVID register // //***************************************************************************** // specific to the Device //***************************************************************************** // // The following are defines for the bit fields in the FUSEERR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES10 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES13 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES14 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES15 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES16 register // //***************************************************************************** // bit // bit //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES19 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES20 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TAP_STATUS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CLKCFGLOCK1 register // //***************************************************************************** // register // register // register // register // register // register // register //***************************************************************************** // // The following are defines for the bit fields in the CLKSRCCTL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CLKSRCCTL2 register // //***************************************************************************** // Bit // Bit //***************************************************************************** // // The following are defines for the bit fields in the CLKSRCCTL3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SYSPLLCTL1 register // //***************************************************************************** // in the PLLSYSCLK path //***************************************************************************** // // The following are defines for the bit fields in the SYSPLLMULT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SYSPLLSTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SYSCLKDIVSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XCLKOUTDIVSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LOSPCP register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MCDCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the X1CNT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XTALCR register // //***************************************************************************** // Single-Ended mode // range //***************************************************************************** // // The following are defines for the bit fields in the CPUSYSLOCK1 register // //***************************************************************************** // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the PIEVERRADDR register // //***************************************************************************** // Handler Routine Address //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR10 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR13 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR14 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR15 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR16 register // //***************************************************************************** // Bit // Bit //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR19 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR20 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR21 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LPMCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPIOLPMSEL0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPIOLPMSEL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TMR2CLKCTL register // //***************************************************************************** // Select Bit // Value //***************************************************************************** // // The following are defines for the bit fields in the RESCCLR register // //***************************************************************************** // Bit // Bit // Bit // Indication Bit // Indication Bit //***************************************************************************** // // The following are defines for the bit fields in the RESC register // //***************************************************************************** // Bit // Bit // Bit // Indication Bit // Indication Bit // C28x //***************************************************************************** // // The following are defines for the bit fields in the SCSR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDCNTR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDKEY register // //***************************************************************************** // timer. //***************************************************************************** // // The following are defines for the bit fields in the WDCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDWCR register // //***************************************************************************** // Windowed Watchdog // functionality //***************************************************************************** // // The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register // //***************************************************************************** // bit // bit //***************************************************************************** // // The following are defines for the bit fields in the DMACHSRCSELLOCK register // //***************************************************************************** // bit // bit //***************************************************************************** // // The following are defines for the bit fields in the CLA1TASKSRCSEL1 register // //***************************************************************************** // for TASK1 of CLA1 // for TASK2 of CLA1 // for TASK3 of CLA1 // for TASK4 of CLA1 //***************************************************************************** // // The following are defines for the bit fields in the CLA1TASKSRCSEL2 register // //***************************************************************************** // for TASK5 of CLA1 // for TASK6 of CLA1 // for TASK7 of CLA1 // for TASK8 of CLA1 //***************************************************************************** // // The following are defines for the bit fields in the DMACHSRCSEL1 register // //***************************************************************************** // Source CH1 of DMA // Source CH2 of DMA // Source CH3 of DMA // Source CH4 of DMA //***************************************************************************** // // The following are defines for the bit fields in the DMACHSRCSEL2 register // //***************************************************************************** // Source CH5 of DMA // Source CH6 of DMA //***************************************************************************** // // The following are defines for the bit fields in the ADCA_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ADCB_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ADCC_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS1_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS2_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS3_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS4_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS5_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS6_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CMPSS7_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the DACA_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the DACB_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA1_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA2_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA3_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA4_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA5_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA6_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PGA7_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM1_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM2_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM3_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM4_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM5_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM6_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM7_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EPWM8_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EQEP1_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the EQEP2_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP1_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP2_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP3_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP4_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP5_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP6_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the ECAP7_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the SDFM1_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CLB1_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CLB2_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CLB3_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CLB4_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the CLA1PROMCRC_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the SPIA_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the SPIB_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PMBUS_A_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the LIN_A_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the DCANA_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the DCANB_AC register // //***************************************************************************** // peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the FSIATX_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the FSIARX_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the HRPWM_A_AC register // //***************************************************************************** // peripheral // Peripheral // Peripheral //***************************************************************************** // // The following are defines for the bit fields in the PERIPH_AC_LOCK register // //***************************************************************************** // control registers write. //***************************************************************************** // // The following are defines for the bit fields in the SYNCSELECT register // //***************************************************************************** // EPWM4 // EPWM7 // ECAP1 // ECAP4 // ECAP6 // EPWM1 //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCOUTSELECT register // //***************************************************************************** // ADCSOCAOn // ADCSOCAOn // ADCSOCAOn // ADCSOCAOn // ADCSOCAOn // ADCSOCAOn // ADCSOCAOn // ADCSOCAOn // ADCSOCBOn // ADCSOCBOn // ADCSOCBOn // ADCSOCBOn // ADCSOCBOn // ADCSOCBOn // ADCSOCBOn // ADCSOCBOn //***************************************************************************** // // The following are defines for the bit fields in the SYNCSOCLOCK register // //***************************************************************************** // bit //########################################################################### // // FILE: interrupt.h // // TITLE: C28x Interrupt (PIE) driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup interrupt_api Interrupt //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_ints.h // // TITLE: Definitions of interrupt numbers for use with interrupt.c. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ //########################################################################### //***************************************************************************** // // PIE Interrupt Numbers // // 0x00FF = PIE Table Row # // 0xFF00 = PIE Table Column # // 0xFFFF0000 = PIE Vector ID // //***************************************************************************** // Lower PIE Group 1 // Lower PIE Group 2 // Lower PIE Group 3 // Lower PIE Group 4 // Lower PIE Group 5 // Lower PIE Group 6 // Lower PIE Group 7 // Lower PIE Group 8 // Lower PIE Group 9 // Lower PIE Group 10 // Lower PIE Group 11 // Lower PIE Group 12 // Upper PIE Group 4 // Upper PIE Group 5 // Upper PIE Group 7 // Upper PIE Group 8 // Upper PIE Group 10 // Upper PIE Group 12 // Other interrupts //########################################################################### // // FILE: hw_pie.h // // TITLE: Definitions for the PIE registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the PIE register offsets // //***************************************************************************** // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the PIECTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEACK register // //***************************************************************************** // Group 1 // Group 2 // Group 3 // Group 4 // Group 5 // Group 6 // Group 7 // Group 8 // Group 9 // Group 10 // Group 11 // Group 12 //***************************************************************************** // // The following are defines for the bit fields in the PIEIER1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER5 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR5 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER10 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR10 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER11 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR11 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIER12 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEIFR12 register // //***************************************************************************** //***************************************************************************** // // The following are values that can be passed to the Interrupt_enableInCPU() // and Interrupt_disableInCPU() functions as the cpuInterrupt parameter. // //***************************************************************************** //***************************************************************************** // // The following are values that can be passed to the Interrupt_clearACKGroup() // function as the group parameter. // //***************************************************************************** //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! The default interrupt handler. //! //! This is the default interrupt handler. The Interrupt_initVectorTable() //! function sets all vectors to this function. Also, when an interrupt is //! unregistered using the Interrupt_unregister() function, this handler takes //! its place. This should never be called during normal operation. //! //! The ESTOP0 statement is for debug purposes only. Remove and replace with an //! appropriate error handling routine for your program. //! //! \return None. // //***************************************************************************** static void Interrupt_defaultHandler(void) { uint16_t pieVect; uint16_t vectID; // // Calculate the vector ID. If the vector is in the lower PIE, it's the // offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT) // divided by two. // pieVect = (*((volatile uint16_t *)(0x00000CE0U + 0x0U))); vectID = (pieVect & 0xFEU) >> 1U; // // If the vector is in the upper PIE, the vector ID is 128 or higher. // if(pieVect >= 0x0E00U) { vectID += 128U; } // // Something has gone wrong. An interrupt without a proper registered // handler function has occurred. To help you debug the issue, local // variable vectID contains the vector ID of the interrupt that occurred. // __asm(" ESTOP0"); for(;;) { ; } } //***************************************************************************** // //! \internal //! The default illegal instruction trap interrupt handler. //! //! This is the default interrupt handler for an illegal instruction trap //! (ITRAP). The Interrupt_initVectorTable() function sets the appropriate //! vector to this function. This should never be called during normal //! operation. //! //! The ESTOP0 statement is for debug purposes only. Remove and replace with //! an appropriate error handling routine for your program. //! //! \return None. // //***************************************************************************** static void Interrupt_illegalOperationHandler(void) { // // Something has gone wrong. The CPU has tried to execute an illegal // instruction, generating an illegal instruction trap (ITRAP). // __asm(" ESTOP0"); for(;;) { ; } } //***************************************************************************** // //! \internal //! The default non-maskable interrupt handler. //! //! This is the default interrupt handler for a non-maskable interrupt (NMI). //! The Interrupt_initVectorTable() function sets the appropriate vector to //! this function. This should never be called during normal operation. //! //! The ESTOP0 statement is for debug purposes only. Remove and replace with an //! appropriate error handling routine for your program. //! //! \return None. // //***************************************************************************** static void Interrupt_nmiHandler(void) { // // A non-maskable interrupt has occurred, indicating that a hardware error // has occurred in the system. You can use SysCtl_getNMIFlagStatus() to // to read the NMIFLG register and determine what caused the NMI. // __asm(" ESTOP0"); for(;;) { ; } } //***************************************************************************** // //! Allows the CPU to process interrupts. //! //! This function clears the global interrupt mask bit (INTM) in the CPU, //! allowing the processor to respond to interrupts. //! //! \return Returns \b true if interrupts were disabled when the function was //! called or \b false if they were initially enabled. // //***************************************************************************** static inline _Bool Interrupt_enableMaster(void) { // // Enable processor interrupts. // return(((__enable_interrupts() & 0x1U) != 0U) ? 1 : 0); } //***************************************************************************** // //! Stops the CPU from processing interrupts. //! //! This function sets the global interrupt mask bit (INTM) in the CPU, //! preventing the processor from receiving maskable interrupts. //! //! \return Returns \b true if interrupts were already disabled when the //! function was called or \b false if they were initially enabled. // //***************************************************************************** static inline _Bool Interrupt_disableMaster(void) { // // Disable processor interrupts. // return(((__disable_interrupts() & 0x1U) != 0U) ? 1 : 0); } //***************************************************************************** // //! Registers a function to be called when an interrupt occurs. //! //! \param interruptNumber specifies the interrupt in question. //! \param handler is a pointer to the function to be called. //! //! This function is used to specify the handler function to be called when the //! given interrupt is asserted to the processor. When the interrupt occurs, //! if it is enabled (via Interrupt_enable()), the handler function will be //! called in interrupt context. Since the handler function can preempt other //! code, care must be taken to protect memory or peripherals that are accessed //! by the handler and other non-handler code. //! //! The available \e interruptNumber values are supplied in //! inc/hw_ints.h. //! //! \note This function assumes that the PIE has been enabled. See //! Interrupt_initModule(). //! //! \return None. // //***************************************************************************** static inline void Interrupt_register(uint32_t interruptNumber, void (*handler)(void)) { uint32_t address; // // Calculate appropriate address for the interrupt number // address = (uint32_t)0x00000D00U + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); // // Copy ISR address into PIE table // __eallow(); (*((volatile uint32_t *)(address))) = (uint32_t)handler; __edis(); } //***************************************************************************** // //! Unregisters the function to be called when an interrupt occurs. //! //! \param interruptNumber specifies the interrupt in question. //! //! This function is used to indicate that a default handler //! Interrupt_defaultHandler() should be called when the given interrupt is //! asserted to the processor. Call Interrupt_disable() to disable //! the interrupt before calling this function. //! //! The available \e interruptNumber values are supplied in //! inc/hw_ints.h. //! //! \sa Interrupt_register() for important information about registering //! interrupt handlers. //! //! \return None. // //***************************************************************************** static inline void Interrupt_unregister(uint32_t interruptNumber) { uint32_t address; // // Calculate appropriate address for the interrupt number // address = (uint32_t)0x00000D00U + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); // // Copy default ISR address into PIE table // __eallow(); (*((volatile uint32_t *)(address))) = (uint32_t)Interrupt_defaultHandler; __edis(); } //***************************************************************************** // //! Enables CPU interrupt channels //! //! \param cpuInterrupt specifies the CPU interrupts to be enabled. //! //! This function enables the specified interrupts in the CPU. The //! \e cpuInterrupt parameter is a logical OR of the values //! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, //! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. //! //! \note Note that interrupts 1-12 correspond to the PIE groups with those //! same numbers. //! //! \return None. // //***************************************************************************** static inline void Interrupt_enableInCPU(uint16_t cpuInterrupt) { // // Set the interrupt bits in the CPU. // IER |= cpuInterrupt; } //***************************************************************************** // //! Disables CPU interrupt channels //! //! \param cpuInterrupt specifies the CPU interrupts to be disabled. //! //! This function disables the specified interrupts in the CPU. The //! \e cpuInterrupt parameter is a logical OR of the values //! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, //! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. //! //! \note Note that interrupts 1-12 correspond to the PIE groups with those //! same numbers. //! //! \return None. // //***************************************************************************** static inline void Interrupt_disableInCPU(uint16_t cpuInterrupt) { // // Clear the interrupt bits in the CPU. // IER &= ~cpuInterrupt; } //***************************************************************************** // //! Acknowledges PIE Interrupt Group //! //! \param group specifies the interrupt group to be acknowledged. //! //! The specified interrupt group is acknowledged and clears any interrupt //! flag within that respective group. //! //! The \e group parameter must be a logical OR of the following: //! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3 //! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6 //! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9 //! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11, //! \b INTERRUPT_ACK_GROUP12. //! //! \return None. // //***************************************************************************** static inline void Interrupt_clearACKGroup(uint16_t group) { // // Set interrupt group acknowledge bits // (*((volatile uint16_t *)(0x00000CE0U + 0x1U))) = group; } //***************************************************************************** // //! Initializes the PIE control registers by setting them to a known state. //! //! This function initializes the PIE control registers. After globally //! disabling interrupts and enabling the PIE, it clears all of the PIE //! interrupt enable bits and interrupt flags. //! //! \return None. // //***************************************************************************** extern void Interrupt_initModule(void); //***************************************************************************** // //! Initializes the PIE vector table by setting all vectors to a default //! handler function. //! //! \return None. // //***************************************************************************** extern void Interrupt_initVectorTable(void); //***************************************************************************** // //! Enables an interrupt. //! //! \param interruptNumber specifies the interrupt to be enabled. //! //! The specified interrupt is enabled in the interrupt controller. Other //! enables for the interrupt (such as at the peripheral level) are unaffected //! by this function. //! //! The available \e interruptNumber values are supplied in //! inc/hw_ints.h. //! //! \return None. // //***************************************************************************** extern void Interrupt_enable(uint32_t interruptNumber); //***************************************************************************** // //! Disables an interrupt. //! //! \param interruptNumber specifies the interrupt to be disabled. //! //! The specified interrupt is disabled in the interrupt controller. Other //! enables for the interrupt (such as at the peripheral level) are unaffected //! by this function. //! //! The available \e interruptNumber values are supplied in //! inc/hw_ints.h. //! //! \return None. // //***************************************************************************** extern void Interrupt_disable(uint32_t interruptNumber); //***************************************************************************** // // Extern compiler intrinsic prototypes. See compiler User's Guide for details. // //***************************************************************************** extern uint16_t __disable_interrupts(void); extern uint16_t __enable_interrupts(void); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //***************************************************************************** // // Defines for system control functions. Not intended for use by application // code. // //***************************************************************************** // Shifted pattern for WDCR register's WDCHK field. // Keys for WDKEY field. The first enables resets and the second resets. // Values to help decode peripheral parameter // LPM defines for LPMCR.LPM // Default internal oscillator frequency, 10 MHz // Mask for SYNCSELECT.SYNCIN // Boot ROM Booting and Reset Status //***************************************************************************** // // The following are values that can be passed to the SysCtl_setClock() API as // the config parameter. // //***************************************************************************** // // System clock divider (SYSDIV) // //! Macro to format system clock divider value. x must be 1 or even values up //! to 126. // // Integer multiplier (IMULT) // //! Macro to format integer multiplier value. x is a number from 1 to 127. //! // // Fractional multiplier (FMULT) // // // Oscillator source // // Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(), // and SysCtl_turnOffOsc() functions as the oscSource parameter. // //! Internal oscillator INTOSC2 //! External oscillator (XTAL) in crystal mode //! External oscillator (XTAL) in single-ended mode //! Internal oscillator INTOSC1 // // Enable/disable PLL // // // Number of PLL retries for SW work around // //***************************************************************************** // // Values that can be passed to SysCtl_clearNMIStatus(), // SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and // SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by // SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus(). // //***************************************************************************** //***************************************************************************** // // The following are values that can be passed to the SysCtl_clearResetCause() // API as rstCauses or returned by the SysCtl_getResetCause() API. // //***************************************************************************** //***************************************************************************** // // The following values define the adcsocSrc parameter for // SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource(). // //***************************************************************************** // ADCSOCAO // ADCSOCBO //***************************************************************************** // //! The following are values that can be passed to SysCtl_enablePeripheral() //! and SysCtl_disablePeripheral() as the \e peripheral parameter. // //***************************************************************************** typedef enum { // PCLKCR0 SYSCTL_PERIPH_CLK_CLA1 = 0x0000, //!< CLA1 clock SYSCTL_PERIPH_CLK_DMA = 0x0200, //!< DMA clock SYSCTL_PERIPH_CLK_TIMER0 = 0x0300, //!< CPUTIMER0 clock SYSCTL_PERIPH_CLK_TIMER1 = 0x0400, //!< CPUTIMER1 clock SYSCTL_PERIPH_CLK_TIMER2 = 0x0500, //!< CPUTIMER2 clock SYSCTL_PERIPH_CLK_HRPWM = 0x1000, //!< HRPWM clock SYSCTL_PERIPH_CLK_TBCLKSYNC = 0x1200, //!< ePWM time base clock sync // PCLKCR1 // Reserved // PCLKCR2 SYSCTL_PERIPH_CLK_EPWM1 = 0x0002, //!< ePWM1 clock SYSCTL_PERIPH_CLK_EPWM2 = 0x0102, //!< ePWM2 clock SYSCTL_PERIPH_CLK_EPWM3 = 0x0202, //!< ePWM3 clock SYSCTL_PERIPH_CLK_EPWM4 = 0x0302, //!< ePWM4 clock SYSCTL_PERIPH_CLK_EPWM5 = 0x0402, //!< ePWM5 clock SYSCTL_PERIPH_CLK_EPWM6 = 0x0502, //!< ePWM6 clock SYSCTL_PERIPH_CLK_EPWM7 = 0x0602, //!< ePWM7 clock SYSCTL_PERIPH_CLK_EPWM8 = 0x0702, //!< ePWM8 clock // PCLKCR3 SYSCTL_PERIPH_CLK_ECAP1 = 0x0003, //!< eCAP1 clock SYSCTL_PERIPH_CLK_ECAP2 = 0x0103, //!< eCAP2 clock SYSCTL_PERIPH_CLK_ECAP3 = 0x0203, //!< eCAP3 clock SYSCTL_PERIPH_CLK_ECAP4 = 0x0303, //!< eCAP4 clock SYSCTL_PERIPH_CLK_ECAP5 = 0x0403, //!< eCAP5 clock SYSCTL_PERIPH_CLK_ECAP6 = 0x0503, //!< eCAP6 clock SYSCTL_PERIPH_CLK_ECAP7 = 0x0603, //!< eCAP7 clock // PCLKCR4 SYSCTL_PERIPH_CLK_EQEP1 = 0x0004, //!< eQEP1 clock SYSCTL_PERIPH_CLK_EQEP2 = 0x0104, //!< eQEP2 clock // PCLKCR5 // Reserved // PCLKCR6 SYSCTL_PERIPH_CLK_SD1 = 0x0006, //!< SDFM1 clock // PCLKCR7 SYSCTL_PERIPH_CLK_SCIA = 0x0007, //!< SCIA clock SYSCTL_PERIPH_CLK_SCIB = 0x0107, //!< SCIB clock // PCLKCR8 SYSCTL_PERIPH_CLK_SPIA = 0x0008, //!< SPIA clock SYSCTL_PERIPH_CLK_SPIB = 0x0108, //!< SPIB clock // PCLKCR9 SYSCTL_PERIPH_CLK_I2CA = 0x0009, //!< I2CA clock // PCLKCR10 SYSCTL_PERIPH_CLK_CANA = 0x000A, //!< CANA clock SYSCTL_PERIPH_CLK_CANB = 0x010A, //!< CANB clock // PCLKCR11 // Reserved // PCLKCR12 // Reserved // PCLKCR13 SYSCTL_PERIPH_CLK_ADCA = 0x000D, //!< ADCA clock SYSCTL_PERIPH_CLK_ADCB = 0x010D, //!< ADCB clock SYSCTL_PERIPH_CLK_ADCC = 0x020D, //!< ADCC clock // PCLKCR14 SYSCTL_PERIPH_CLK_CMPSS1 = 0x000E, //!< CMPSS1 clock SYSCTL_PERIPH_CLK_CMPSS2 = 0x010E, //!< CMPSS2 clock SYSCTL_PERIPH_CLK_CMPSS3 = 0x020E, //!< CMPSS3 clock SYSCTL_PERIPH_CLK_CMPSS4 = 0x030E, //!< CMPSS4 clock SYSCTL_PERIPH_CLK_CMPSS5 = 0x040E, //!< CMPSS5 clock SYSCTL_PERIPH_CLK_CMPSS6 = 0x050E, //!< CMPSS6 clock SYSCTL_PERIPH_CLK_CMPSS7 = 0x060E, //!< CMPSS7 clock // PCLKCR15 SYSCTL_PERIPH_CLK_PGA1 = 0x000F, //!< PGA1 clock SYSCTL_PERIPH_CLK_PGA2 = 0x010F, //!< PGA2 clock SYSCTL_PERIPH_CLK_PGA3 = 0x020F, //!< PGA3 clock SYSCTL_PERIPH_CLK_PGA4 = 0x030F, //!< PGA4 clock SYSCTL_PERIPH_CLK_PGA5 = 0x040F, //!< PGA5 clock SYSCTL_PERIPH_CLK_PGA6 = 0x050F, //!< PGA6 clock SYSCTL_PERIPH_CLK_PGA7 = 0x060F, //!< PGA7 clock // PCLKCR16 SYSCTL_PERIPH_CLK_DACA = 0x1010, //!< DACA clock SYSCTL_PERIPH_CLK_DACB = 0x1110, //!< DACB clock // PCLKCR17 // Reserved // PCLKCR18 SYSCTL_PERIPH_CLK_FSITXA = 0x0012, //!< FSITXA clock SYSCTL_PERIPH_CLK_FSIRXA = 0x0112, //!< FSIRXA clock // PCLKCR19 SYSCTL_PERIPH_CLK_LINA = 0x0013, //!< LINA clock // PCLKCR20 SYSCTL_PERIPH_CLK_PMBUSA = 0x0014, //!< PMBusA clock // PCLKCR21 SYSCTL_PERIPH_CLK_DCC0 = 0x0015 //!< DCC0 clock } SysCtl_PeripheralPCLOCKCR; //***************************************************************************** // //! The following are values that can be passed to SysCtl_resetPeripheral() as //! the \e peripheral parameter. // //***************************************************************************** typedef enum { // SOFTPRES0 SYSCTL_PERIPH_RES_CLA1 = 0x0000, //!< Reset CLA1 // SOFTPRES1 // Reserved // SOFTPRES2 SYSCTL_PERIPH_RES_EPWM1 = 0x0002, //!< Reset ePWM1 SYSCTL_PERIPH_RES_EPWM2 = 0x0102, //!< Reset ePWM2 SYSCTL_PERIPH_RES_EPWM3 = 0x0202, //!< Reset ePWM3 SYSCTL_PERIPH_RES_EPWM4 = 0x0302, //!< Reset ePWM4 SYSCTL_PERIPH_RES_EPWM5 = 0x0402, //!< Reset ePWM5 SYSCTL_PERIPH_RES_EPWM6 = 0x0502, //!< Reset ePWM6 SYSCTL_PERIPH_RES_EPWM7 = 0x0602, //!< Reset ePWM7 SYSCTL_PERIPH_RES_EPWM8 = 0x0702, //!< Reset ePWM8 // SOFTPRES3 SYSCTL_PERIPH_RES_ECAP1 = 0x0003, //!< Reset eCAP1 SYSCTL_PERIPH_RES_ECAP2 = 0x0103, //!< Reset eCAP2 SYSCTL_PERIPH_RES_ECAP3 = 0x0203, //!< Reset eCAP3 SYSCTL_PERIPH_RES_ECAP4 = 0x0303, //!< Reset eCAP4 SYSCTL_PERIPH_RES_ECAP5 = 0x0403, //!< Reset eCAP5 SYSCTL_PERIPH_RES_ECAP6 = 0x0503, //!< Reset eCAP6 SYSCTL_PERIPH_RES_ECAP7 = 0x0603, //!< Reset eCAP7 // SOFTPRES4 SYSCTL_PERIPH_RES_EQEP1 = 0x0004, //!< Reset eQEP1 SYSCTL_PERIPH_RES_EQEP2 = 0x0104, //!< Reset eQEP2 // SOFTPRES5 // Reserved // SOFTPRES6 SYSCTL_PERIPH_RES_SD1 = 0x0006, //!< Reset SDFM1 // SOFTPRES7 SYSCTL_PERIPH_RES_SCIA = 0x0007, //!< Reset SCIA SYSCTL_PERIPH_RES_SCIB = 0x0107, //!< Reset SCIB // SOFTPRES8 SYSCTL_PERIPH_RES_SPIA = 0x0008, //!< Reset SPIA SYSCTL_PERIPH_RES_SPIB = 0x0108, //!< Reset SPIB // SOFTPRES9 SYSCTL_PERIPH_RES_I2CA = 0x0009, //!< Reset I2CA // SOFTPRES10 SYSCTL_PERIPH_RES_CANA = 0x000A, //!< Reset CANA SYSCTL_PERIPH_RES_CANB = 0x010A, //!< Reset CANB // SOFTPRES11 // Reserved // SOFTPRES12 // Reserved // SOFTPRES13 SYSCTL_PERIPH_RES_ADCA = 0x000D, //!< Reset ADCA SYSCTL_PERIPH_RES_ADCB = 0x010D, //!< Reset ADCB SYSCTL_PERIPH_RES_ADCC = 0x020D, //!< Reset ADCC // SOFTPRES14 SYSCTL_PERIPH_RES_CMPSS1 = 0x000E, //!< Reset CMPSS1 SYSCTL_PERIPH_RES_CMPSS2 = 0x010E, //!< Reset CMPSS2 SYSCTL_PERIPH_RES_CMPSS3 = 0x020E, //!< Reset CMPSS3 SYSCTL_PERIPH_RES_CMPSS4 = 0x030E, //!< Reset CMPSS4 SYSCTL_PERIPH_RES_CMPSS5 = 0x040E, //!< Reset CMPSS5 SYSCTL_PERIPH_RES_CMPSS6 = 0x050E, //!< Reset CMPSS6 SYSCTL_PERIPH_RES_CMPSS7 = 0x060E, //!< Reset CMPSS7 // SOFTPRES15 SYSCTL_PERIPH_RES_PGA1 = 0x000F, //!< Reset PGA1 SYSCTL_PERIPH_RES_PGA2 = 0x010F, //!< Reset PGA2 SYSCTL_PERIPH_RES_PGA3 = 0x020F, //!< Reset PGA3 SYSCTL_PERIPH_RES_PGA4 = 0x030F, //!< Reset PGA4 SYSCTL_PERIPH_RES_PGA5 = 0x040F, //!< Reset PGA5 SYSCTL_PERIPH_RES_PGA6 = 0x050F, //!< Reset PGA6 SYSCTL_PERIPH_RES_PGA7 = 0x060F, //!< Reset PGA7 // SOFTPRES16 SYSCTL_PERIPH_RES_DACA = 0x1010, //!< Reset DACA SYSCTL_PERIPH_RES_DACB = 0x1110, //!< Reset DACB // SOFTPRES17 // Reserved // SOFTPRES18 SYSCTL_PERIPH_RES_FSITXA = 0x0012, //!< Reset FSITXA SYSCTL_PERIPH_RES_FSIRXA = 0x0112, //!< Reset FSIRXA // SOFTPRES19 SYSCTL_PERIPH_RES_LINA = 0x0013, //!< Reset LINA // SOFTPRES20 SYSCTL_PERIPH_RES_PMBUSA = 0x0014, //!< Reset PMBusA // SOFTPRES21 SYSCTL_PERIPH_RES_DCC0 = 0x0015 } SysCtl_PeripheralSOFTPRES; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setWatchdogPredivider() as the \e predivider parameter. // //***************************************************************************** typedef enum { SYSCTL_WD_PREDIV_2 = 0x800, //!< PREDIVCLK = INTOSC1 / 2 SYSCTL_WD_PREDIV_4 = 0x900, //!< PREDIVCLK = INTOSC1 / 4 SYSCTL_WD_PREDIV_8 = 0xA00, //!< PREDIVCLK = INTOSC1 / 8 SYSCTL_WD_PREDIV_16 = 0xB00, //!< PREDIVCLK = INTOSC1 / 16 SYSCTL_WD_PREDIV_32 = 0xC00, //!< PREDIVCLK = INTOSC1 / 32 SYSCTL_WD_PREDIV_64 = 0xD00, //!< PREDIVCLK = INTOSC1 / 64 SYSCTL_WD_PREDIV_128 = 0xE00, //!< PREDIVCLK = INTOSC1 / 128 SYSCTL_WD_PREDIV_256 = 0xF00, //!< PREDIVCLK = INTOSC1 / 256 SYSCTL_WD_PREDIV_512 = 0x000, //!< PREDIVCLK = INTOSC1 / 512 SYSCTL_WD_PREDIV_1024 = 0x100, //!< PREDIVCLK = INTOSC1 / 1024 SYSCTL_WD_PREDIV_2048 = 0x200, //!< PREDIVCLK = INTOSC1 / 2048 SYSCTL_WD_PREDIV_4096 = 0x300 //!< PREDIVCLK = INTOSC1 / 4096 } SysCtl_WDPredivider; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setWatchdogPrescaler() as the \e prescaler parameter. // //***************************************************************************** typedef enum { SYSCTL_WD_PRESCALE_1 = 1, //!< WDCLK = PREDIVCLK / 1 SYSCTL_WD_PRESCALE_2 = 2, //!< WDCLK = PREDIVCLK / 2 SYSCTL_WD_PRESCALE_4 = 3, //!< WDCLK = PREDIVCLK / 4 SYSCTL_WD_PRESCALE_8 = 4, //!< WDCLK = PREDIVCLK / 8 SYSCTL_WD_PRESCALE_16 = 5, //!< WDCLK = PREDIVCLK / 16 SYSCTL_WD_PRESCALE_32 = 6, //!< WDCLK = PREDIVCLK / 32 SYSCTL_WD_PRESCALE_64 = 7 //!< WDCLK = PREDIVCLK / 64 } SysCtl_WDPrescaler; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setWatchdogMode() as the \e prescaler parameter. // //***************************************************************************** typedef enum { //! Watchdog can generate a reset signal SYSCTL_WD_MODE_RESET, //! Watchdog can generate an interrupt signal; reset signal is disabled SYSCTL_WD_MODE_INTERRUPT } SysCtl_WDMode; //***************************************************************************** // //! The following are values that can be passed to SysCtl_setLowSpeedClock() as //! the \e prescaler parameter. // //***************************************************************************** typedef enum { SYSCTL_LSPCLK_PRESCALE_1 = 0, //!< LSPCLK = SYSCLK / 1 SYSCTL_LSPCLK_PRESCALE_2 = 1, //!< LSPCLK = SYSCLK / 2 SYSCTL_LSPCLK_PRESCALE_4 = 2, //!< LSPCLK = SYSCLK / 4 (default) SYSCTL_LSPCLK_PRESCALE_6 = 3, //!< LSPCLK = SYSCLK / 6 SYSCTL_LSPCLK_PRESCALE_8 = 4, //!< LSPCLK = SYSCLK / 8 SYSCTL_LSPCLK_PRESCALE_10 = 5, //!< LSPCLK = SYSCLK / 10 SYSCTL_LSPCLK_PRESCALE_12 = 6, //!< LSPCLK = SYSCLK / 12 SYSCTL_LSPCLK_PRESCALE_14 = 7 //!< LSPCLK = SYSCLK / 14 } SysCtl_LSPCLKPrescaler; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setPeripheralAccessControl() and SysCtl_getPeripheralAccessControl() //! as the \e peripheral parameter. // //***************************************************************************** typedef enum { // ADC SYSCTL_ACCESS_ADCA = 0x0, //!< ADCA access SYSCTL_ACCESS_ADCB = 0x2, //!< ADCB access SYSCTL_ACCESS_ADCC = 0x4, //!< ADCC access // CMPSS SYSCTL_ACCESS_CMPSS1 = 0x10, //!< CMPSS1 access SYSCTL_ACCESS_CMPSS2 = 0x12, //!< CMPSS2 access SYSCTL_ACCESS_CMPSS3 = 0x14, //!< CMPSS3 access SYSCTL_ACCESS_CMPSS4 = 0x16, //!< CMPSS4 access SYSCTL_ACCESS_CMPSS5 = 0x18, //!< CMPSS5 access SYSCTL_ACCESS_CMPSS6 = 0x1A, //!< CMPSS6 access SYSCTL_ACCESS_CMPSS7 = 0x1C, //!< CMPSS7 access // DAC SYSCTL_ACCESS_DACA = 0x28, //!< DACA access SYSCTL_ACCESS_DACB = 0x2A, //!< DACB access // PGA SYSCTL_ACCESS_PGA1 = 0x38, //!< PGA1 access SYSCTL_ACCESS_PGA2 = 0x3A, //!< PGA2 access SYSCTL_ACCESS_PGA3 = 0x3C, //!< PGA3 access SYSCTL_ACCESS_PGA4 = 0x3E, //!< PGA4 access SYSCTL_ACCESS_PGA5 = 0x40, //!< PGA5 access SYSCTL_ACCESS_PGA6 = 0x42, //!< PGA6 access SYSCTL_ACCESS_PGA7 = 0x44, //!< PGA7 access // EPWM SYSCTL_ACCESS_EPWM1 = 0x48, //!< ePWM1 access SYSCTL_ACCESS_EPWM2 = 0x4A, //!< ePWM2 access SYSCTL_ACCESS_EPWM3 = 0x4C, //!< ePWM3 access SYSCTL_ACCESS_EPWM4 = 0x4E, //!< ePWM4 access SYSCTL_ACCESS_EPWM5 = 0x50, //!< ePWM5 access SYSCTL_ACCESS_EPWM6 = 0x52, //!< ePWM6 access SYSCTL_ACCESS_EPWM7 = 0x54, //!< ePWM7 access SYSCTL_ACCESS_EPWM8 = 0x56, //!< ePWM8 access // EQEP SYSCTL_ACCESS_EQEP1 = 0x70, //!< eQEP1 access SYSCTL_ACCESS_EQEP2 = 0x72, //!< eQEP2 access // ECAP SYSCTL_ACCESS_ECAP1 = 0x80, //!< eCAP1 access SYSCTL_ACCESS_ECAP2 = 0x82, //!< eCAP2 access SYSCTL_ACCESS_ECAP3 = 0x84, //!< eCAP3 access SYSCTL_ACCESS_ECAP4 = 0x86, //!< eCAP4 access SYSCTL_ACCESS_ECAP5 = 0x88, //!< eCAP5 access SYSCTL_ACCESS_ECAP6 = 0x8A, //!< eCAP6 access SYSCTL_ACCESS_ECAP7 = 0x8C, //!< eCAP7 access // SDFM SYSCTL_ACCESS_SDFM1 = 0xA8, //!< SDFM1 access // CLAPROMCRC SYSCTL_ACCESS_CLA1PROMCRC = 0xC0, //!< CLA1PROMCRC access // SPI SYSCTL_ACCESS_SPIA = 0x110, //!< SPIA access SYSCTL_ACCESS_SPIB = 0x112, //!< SPIB access // PMBUS SYSCTL_ACCESS_PMBUS_A = 0x130, //!< PMBusA access // LIN SYSCTL_ACCESS_LIN_A = 0x138, //!< LIN access // CAN SYSCTL_ACCESS_CANA = 0x140, //!< CANA access SYSCTL_ACCESS_CANB = 0x142, //!< CANB access // FSI SYSCTL_ACCESS_FSIATX = 0x158, //!< FSITXA access SYSCTL_ACCESS_FSIARX = 0x15A, //!< FSIRXA access // HRPWM SYSCTL_ACCESS_HRPWM_A = 0x1AA //!< HRPWM access } SysCtl_AccessPeripheral; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setPeripheralAccessControl() and SysCtl_getPeripheralAccessControl() //! as the \e master parameter. // //***************************************************************************** typedef enum { SYSCTL_ACCESS_CPU1 = 0U, //!< CPU access to the peripheral SYSCTL_ACCESS_CLA1 = 2U, //!< CLA1 access to the peripheral SYSCTL_ACCESS_DMA1 = 4U //!< DMA access to the peripheral } SysCtl_AccessMaster; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setPeripheralAccessControl() as the \e permission parameter. // //***************************************************************************** typedef enum { //! Full Access for both read and write. SYSCTL_ACCESS_FULL = 3U, //! Protected RD access such that FIFOs. Clear on read, registers are not //! changed and no write access. SYSCTL_ACCESS_PROTECTED = 2U, //! No read or write access. SYSCTL_ACCESS_NONE = 0U } SysCtl_AccessPermission; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_selectClockOutSource() as the \e source parameter. // //***************************************************************************** typedef enum { SYSCTL_CLOCKOUT_PLLSYS = 0U, //!< PLL System Clock SYSCTL_CLOCKOUT_PLLRAW = 1U, //!< PLL Raw Clock SYSCTL_CLOCKOUT_SYSCLK = 2U, //!< CPU System Clock SYSCTL_CLOCKOUT_INTOSC1 = 5U, //!< Internal Oscillator 1 SYSCTL_CLOCKOUT_INTOSC2 = 6U, //!< Internal Oscillator 2 SYSCTL_CLOCKOUT_XTALOSC = 7U //!< External Oscillator } SysCtl_ClockOut; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setExternalOscMode() as the \e mode parameter. // //***************************************************************************** typedef enum { SYSCTL_XTALMODE_CRYSTAL = 1U, //!< XTAL Oscillator Crystal Mode SYSCTL_XTALMODE_SINGLE = 2U //!< XTAL Oscillator Single-Ended Mode } SysCtl_ExternalOscMode; //***************************************************************************** // //! The following values define the \e syncInput parameter for //! SysCtl_setSyncInputConfig(). // //***************************************************************************** typedef enum { SYSCTL_SYNC_IN_EPWM1 = 29, //!< Sync input to ePWM 1 SYSCTL_SYNC_IN_EPWM4 = 0, //!< Sync input to ePWM 4 SYSCTL_SYNC_IN_EPWM7 = 3, //!< Sync input to ePWM 7 SYSCTL_SYNC_IN_ECAP1 = 9, //!< Sync input to eCAP 1 SYSCTL_SYNC_IN_ECAP4 = 12, //!< Sync input to eCAP 4 SYSCTL_SYNC_IN_ECAP6 = 15 //!< Sync input to eCAP 6 } SysCtl_SyncInput; //***************************************************************************** // //! The following values define the \e syncSrc parameter for //! SysCtl_setSyncInputConfig(). Note that some of these are only valid for //! certain values of \e syncInput. See device technical reference manual for //! info on time-base counter synchronization for details. // //***************************************************************************** typedef enum { //! EPWM1SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT = 0, //! EPWM4SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM4SYNCOUT = 1, //! EPWM7SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM7SYNCOUT = 2, //! ECAP1SYNCOUT SYSCTL_SYNC_IN_SRC_ECAP1SYNCOUT = 4, //! EXTSYNCIN1--Valid for all values of syncInput SYSCTL_SYNC_IN_SRC_EXTSYNCIN1 = 5, //! EXTSYNCIN2--Valid for all values of syncInput except EPWM1 SYSCTL_SYNC_IN_SRC_EXTSYNCIN2 = 6, //! ECAP4SYNCOUT SYSCTL_SYNC_IN_SRC_ECAP4SYNCOUT = 7 } SysCtl_SyncInputSource; //***************************************************************************** // //! The following values define the \e syncSrc parameter for //! SysCtl_setSyncOutputConfig(). // //***************************************************************************** typedef enum { SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT, //!< EPWM1SYNCOUT --> EXTSYNCOUT SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT, //!< EPWM4SYNCOUT --> EXTSYNCOUT SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT //!< EPWM7SYNCOUT --> EXTSYNCOUT } SysCtl_SyncOutputSource; //***************************************************************************** // //! The following values define the \e parametric parameter for //! SysCtl_getDeviceParametric(). // //***************************************************************************** typedef enum { SYSCTL_DEVICE_QUAL, //!< Device Qualification Status SYSCTL_DEVICE_PINCOUNT, //!< Device Pin Count SYSCTL_DEVICE_INSTASPIN, //!< Device InstaSPIN Feature Set SYSCTL_DEVICE_FLASH, //!< Device Flash size (KB) SYSCTL_DEVICE_FAMILY, //!< Device Family SYSCTL_DEVICE_PARTNO, //!< Device Part Number SYSCTL_DEVICE_CLASSID //!< Device Class ID } SysCtl_DeviceParametric; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Resets a peripheral //! //! \param peripheral is the peripheral to reset. //! //! This function uses the SOFTPRESx registers to reset a specified peripheral. //! Module registers will be returned to their reset states. //! //! \note This includes registers containing trim values. //! //! \return None. // //***************************************************************************** static inline void SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral) { uint16_t regIndex; uint16_t bitIndex; // // Decode the peripheral variable. // regIndex = (uint16_t)2U * ((uint16_t)peripheral & (uint16_t)0x001FU); bitIndex = ((uint16_t)peripheral & 0x1F00U) >> 0x0008U; __eallow(); // // Sets the appropriate reset bit and then clears it. // (*((volatile uint32_t *)(0x0005D000U + 0x82U + regIndex))) |= ((uint32_t)1U << bitIndex); (*((volatile uint32_t *)(0x0005D000U + 0x82U + regIndex))) &= ~((uint32_t)1U << bitIndex); __edis(); } //***************************************************************************** // //! Enables a peripheral. //! //! \param peripheral is the peripheral to enable. //! //! Peripherals are enabled with this function. At power-up, all peripherals //! are disabled; they must be enabled in order to operate or respond to //! register reads/writes. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) { uint16_t regIndex; uint16_t bitIndex; // // Decode the peripheral variable. // regIndex = (uint16_t)2U * ((uint16_t)peripheral & (uint16_t)0x001FU); bitIndex = ((uint16_t)peripheral & 0x1F00U) >> 0x0008U; __eallow(); // // Turn on the module clock. // (*((volatile uint32_t *)(0x0005D300U + 0x22U + regIndex))) |= ((uint32_t)1U << bitIndex); __edis(); } //***************************************************************************** // //! Disables a peripheral. //! //! \param peripheral is the peripheral to disable. //! //! Peripherals are disabled with this function. Once disabled, they will not //! operate or respond to register reads/writes. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) { uint16_t regIndex; uint16_t bitIndex; // // Decode the peripheral variable. // regIndex = (uint16_t)2U * ((uint16_t)peripheral & (uint16_t)0x001FU); bitIndex = ((uint16_t)peripheral & 0x1F00U) >> 0x0008U; __eallow(); // // Turn off the module clock. // (*((volatile uint32_t *)(0x0005D300U + 0x22U + regIndex))) &= ~((uint32_t)1U << bitIndex); __edis(); } //***************************************************************************** // //! Resets the device. //! //! This function performs a watchdog reset of the device. //! //! \return This function does not return. // //***************************************************************************** static inline void SysCtl_resetDevice(void) { // // Write an incorrect check value to the watchdog control register // This will cause a device reset // __eallow(); // Enable the watchdog (*((volatile uint16_t *)(0x00007000U + 0x29U))) = 0x0028U; // Write a bad check value (*((volatile uint16_t *)(0x00007000U + 0x29U))) = 0U; __edis(); // // The device should have reset, so this should never be reached. Just in // case, loop forever. // while(1) { } } //***************************************************************************** // //! Gets the reason for a reset. //! //! This function will return the reason(s) for a reset. Since the reset //! reasons are sticky until either cleared by software or an external reset, //! multiple reset reasons may be returned if multiple resets have occurred. //! The reset reason will be a logical OR of //! - \b SYSCTL_CAUSE_POR - Power-on reset //! - \b SYSCTL_CAUSE_XRS - External reset pin //! - \b SYSCTL_CAUSE_WDRS - Watchdog reset //! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset //! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM //! //! \note If you re-purpose the reserved boot ROM RAM, the POR and XRS reset //! statuses won't be accurate. //! //! \return Returns the reason(s) for a reset. // //***************************************************************************** static inline uint32_t SysCtl_getResetCause(void) { uint32_t resetCauses; // // Read CPU reset register // resetCauses = (*((volatile uint32_t *)(0x0005D300U + 0x80U))) & ((uint32_t)0x1U | (uint32_t)0x2U | (uint32_t)0x4U | (uint32_t)0x8U | (uint32_t)0x100U); // // Set POR and XRS Causes from boot ROM Status // if(((*((volatile uint32_t *)(0x0002U))) & (uint32_t)0x2000U) == (uint32_t)0x2000U) { resetCauses |= 0x1U; } if(((*((volatile uint32_t *)(0x0002U))) & (uint32_t)0x1000U) == (uint32_t)0x1000U) { resetCauses |= 0x2U; } // // Return the reset reasons. // return(resetCauses); } //***************************************************************************** // //! Clears reset reasons. //! //! \param rstCauses are the reset causes to be cleared; must be a logical //! OR of \b SYSCTL_CAUSE_POR, \b SYSCTL_CAUSE_XRS, \b SYSCTL_CAUSE_WDRS, //! \b SYSCTL_CAUSE_NMIWDRS, and/or \b SYSCTL_CAUSE_SCCRESET. //! //! This function clears the specified sticky reset reasons. Once cleared, //! another reset for the same reason can be detected, and a reset for a //! different reason can be distinguished (instead of having two reset causes //! set). If the reset reason is used by an application, all reset causes //! should be cleared after they are retrieved with SysCtl_getResetCause(). //! //! \note Some reset causes are cleared by the boot ROM. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearResetCause(uint32_t rstCauses) { // // Clear the given reset reasons. // (*((volatile uint32_t *)(0x0005D300U + 0x7EU))) = rstCauses; } //***************************************************************************** // //! Sets the low speed peripheral clock rate prescaler. //! //! \param prescaler is the LSPCLK rate relative to SYSCLK //! //! This function configures the clock rate of the low speed peripherals. The //! \e prescaler parameter is the value by which the SYSCLK rate is divided to //! get the LSPCLK rate. For example, a \e prescaler of //! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter //! of the SYSCLK rate. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler) { // // Write the divider selection to the appropriate register. // __eallow(); (*((volatile uint32_t *)(0x0005D200U + 0x2CU))) = ((*((volatile uint32_t *)(0x0005D200U + 0x2CU))) & ~0x7U) | (uint32_t)prescaler; __edis(); } //***************************************************************************** // //! Selects a clock source to mux to an external GPIO pin (XCLKOUT). //! //! \param source is the internal clock source to be configured. //! //! This function configures the specified clock source to be muxed to an //! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a //! value of one of the following values: //! - \b SYSCTL_CLOCKOUT_PLLSYS //! - \b SYSCTL_CLOCKOUT_PLLRAW //! - \b SYSCTL_CLOCKOUT_SYSCLK //! - \b SYSCTL_CLOCKOUT_INTOSC1 //! - \b SYSCTL_CLOCKOUT_INTOSC2 //! - \b SYSCTL_CLOCKOUT_XTALOSC //! //! \return None. // //***************************************************************************** static inline void SysCtl_selectClockOutSource(SysCtl_ClockOut source) { __eallow(); // // Clear clock out source // (*((volatile uint16_t *)(0x0005D200U + 0xCU))) &= ~0x7U; // // Set clock out source // (*((volatile uint16_t *)(0x0005D200U + 0xCU))) |= (uint16_t)source; __edis(); } //***************************************************************************** // //! Set the external oscillator mode. //! //! \param mode is the external oscillator mode to be configured. //! //! This function sets the external oscillator mode specified by the \e mode //! parameter which may take one of two values: //! - \b SYSCTL_XTALMODE_CRYSTAL - Crystal Mode //! - \b SYSCTL_XTALMODE_SINGLE - Single-Ended Mode //! //! \note The external oscillator must be powered off before this configuration //! can be performed. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setExternalOscMode(SysCtl_ExternalOscMode mode) { __eallow(); switch(mode) { case SYSCTL_XTALMODE_CRYSTAL: // Set mode to Crystal (*((volatile uint32_t *)(0x0005D200U + 0x32U))) &= ~0x2U; break; case SYSCTL_XTALMODE_SINGLE: // Set mode to Single-Ended (*((volatile uint32_t *)(0x0005D200U + 0x32U))) |= 0x2U; break; default: // Do nothing. Not a valid mode value. break; } __edis(); } //***************************************************************************** // //! Gets the external oscillator counter value. //! //! This function returns the X1 clock counter value. When the return value //! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external //! oscillator (XTAL), an application should call this function to make sure the //! counter is saturated. //! //! \return Returns the value of the 10-bit X1 clock counter. // //***************************************************************************** static inline uint16_t SysCtl_getExternalOscCounterValue(void) { return((*((volatile uint16_t *)(0x0005D200U + 0x30U))) & 0x3FFU); } //***************************************************************************** // //! Clears the external oscillator counter value. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearExternalOscCounterValue(void) { (*((volatile uint32_t *)(0x0005D200U + 0x30U))) |= 0x10000U; } //***************************************************************************** // //! Turns on the specified oscillator sources. //! //! \param oscSource is the oscillator source to be configured. //! //! This function turns on the oscillator specified by the \e oscSource //! parameter which may take a value of \b SYSCTL_OSCSRC_OSC2 or //! \b SYSCTL_OSCSRC_XTAL. //! //! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. //! //! \return None. // //***************************************************************************** static inline void SysCtl_turnOnOsc(uint32_t oscSource) { ; __eallow(); switch(oscSource) { case 0x00000000U: // Turn on INTOSC2 (*((volatile uint16_t *)(0x0005D200U + 0x8U))) &= ~0x8U; break; case 0x00010000U: // Turn on XTALOSC (*((volatile uint16_t *)(0x0005D200U + 0x32U))) &= ~0x1U; break; default: // Do nothing. Not a valid oscSource value. break; } __edis(); } //***************************************************************************** // //! Turns off the specified oscillator sources. //! //! \param oscSource is the oscillator source to be configured. //! //! This function turns off the oscillator specified by the \e oscSource //! parameter which may take a value of \b SYSCTL_OSCSRC_OSC2 or //! \b SYSCTL_OSCSRC_XTAL. //! //! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. //! //! \return None. // //***************************************************************************** static inline void SysCtl_turnOffOsc(uint32_t oscSource) { ; __eallow(); switch(oscSource) { case 0x00000000U: // Turn off INTOSC2 (*((volatile uint16_t *)(0x0005D200U + 0x8U))) |= 0x8U; break; case 0x00010000U: // Turn off XTALOSC (*((volatile uint16_t *)(0x0005D200U + 0x32U))) |= 0x1U; break; default: // Do nothing. Not a valid oscSource value. break; } __edis(); } //***************************************************************************** // //! Enters IDLE mode. //! //! This function puts the device into IDLE mode. The CPU clock is gated while //! all peripheral clocks are left running. Any enabled interrupt will wake the //! CPU up from IDLE mode. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enterIdleMode(void) { __eallow(); // // Configure the device to go into IDLE mode when IDLE is executed. // (*((volatile uint32_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint32_t *)(0x0005D300U + 0x76U))) & ~0x3U) | 0x0000U; __edis(); __asm(" IDLE"); } //***************************************************************************** // //! Enters HALT mode. //! //! This function puts the device into HALT mode. This will gate almost all //! systems and clocks and allows for the power-down of oscillators and analog //! blocks. The watchdog may be left clocked to produce a reset. See //! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be //! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin(). //! //! //! The CPU will receive an interrupt (WAKEINT) on wakeup. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enterHaltMode(void) { __eallow(); // // Configure the device to go into HALT mode when IDLE is executed. // (*((volatile uint32_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint32_t *)(0x0005D300U + 0x76U))) & ~0x3U) | 0x0002U; (*((volatile uint16_t *)(0x0005D200U + 0xEU))) &= ~(0x2U | 0x1U); __edis(); __asm(" IDLE"); } //***************************************************************************** // //! Enables a pin to wake up the device from HALT. //! //! \param pin is the identifying number of the pin. //! //! This function connects a pin to the LPM circuit, allowing an event on the //! pin to wake up the device when when it is in HALT mode. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of //! being connected to the LPM circuit. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableLPMWakeupPin(uint32_t pin) { uint32_t pinMask; // // Check the arguments. // ; pinMask = (uint32_t)1U << (uint32_t)(pin % 32U); __eallow(); if(pin < 32U) { (*((volatile uint32_t *)(0x0005D300U + 0x78U))) |= pinMask; } else { (*((volatile uint32_t *)(0x0005D300U + 0x7AU))) |= pinMask; } __edis(); } //***************************************************************************** // //! Disables a pin to wake up the device from HALT. //! //! \param pin is the identifying number of the pin. //! //! This function disconnects a pin to the LPM circuit, disallowing an event on //! the pin to wake up the device when when it is in HALT mode. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableLPMWakeupPin(uint32_t pin) { uint32_t pinMask; // // Check the arguments. // ; pinMask = (uint32_t)1U << (uint32_t)(pin % 32U); __eallow(); if(pin < 32U) { (*((volatile uint32_t *)(0x0005D300U + 0x78U))) &= ~pinMask; } else { (*((volatile uint32_t *)(0x0005D300U + 0x7AU))) &= ~pinMask; } __edis(); } //***************************************************************************** // //! Enable the watchdog to run while in HALT mode. //! //! This function configures the watchdog to continue to run while in HALT //! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the //! system enters HALT mode. By default the watchdog is gated when the system //! enters HALT. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableWatchdogInHalt(void) { __eallow(); // // Set the watchdog HALT mode ignore bit. // (*((volatile uint16_t *)(0x0005D200U + 0x8U))) |= 0x20U; __edis(); } //***************************************************************************** // //! Disable the watchdog from running while in HALT mode. //! //! This function gates the watchdog when the system enters HALT mode. INTOSC1 //! and INTOSC2 will be powered down. This is the default behavior of the //! device. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableWatchdogInHalt(void) { __eallow(); // // Clear the watchdog HALT mode ignore bit. // (*((volatile uint16_t *)(0x0005D200U + 0x8U))) &= ~0x20U; __edis(); } //***************************************************************************** // //! Configures whether the watchdog generates a reset or an interrupt signal. //! //! \param mode is a flag to select the watchdog mode. //! //! This function configures the action taken when the watchdog counter reaches //! its maximum value. When the \e mode parameter is //! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog //! interrupt signal and disables the generation of a reset signal. This will //! allow the watchdog module to wake up the device from IDLE. //! //! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will //! be put into reset mode and generation of a watchdog interrupt signal will //! be disabled. This is how the watchdog is configured by default. //! //! \note Check the status of the watchdog interrupt using //! SysCtl_isWatchdogInterruptActive() before calling this function. If the //! interrupt is still active, switching from interrupt mode to reset mode will //! immediately reset the device. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogMode(SysCtl_WDMode mode) { __eallow(); // // Either set or clear the WDENINT bit to that will determine whether the // watchdog will generate a reset signal or an interrupt signal. Take care // not to write a 1 to WDOVERRIDE. // if(mode == SYSCTL_WD_MODE_INTERRUPT) { (*((volatile uint16_t *)(0x00007000U + 0x22U))) = ((*((volatile uint16_t *)(0x00007000U + 0x22U))) & ~0x1U) | 0x2U; } else { (*((volatile uint16_t *)(0x00007000U + 0x22U))) &= ~(0x2U | 0x1U); } __edis(); } //***************************************************************************** // //! Gets the status of the watchdog interrupt signal. //! //! This function returns the status of the watchdog interrupt signal. If the //! interrupt is active, this function will return \b true. If \b false, the //! interrupt is NOT active. //! //! \note Make sure to call this function to ensure that the interrupt is not //! active before making any changes to the configuration of the watchdog to //! prevent any unexpected behavior. For instance, switching from interrupt //! mode to reset mode while the interrupt is active will immediately reset the //! device. //! //! \return \b true if the interrupt is active and \b false if it is not. // //***************************************************************************** static inline _Bool SysCtl_isWatchdogInterruptActive(void) { // // If the status bit is cleared, the WDINTn signal is active. // return(((*((volatile uint16_t *)(0x00007000U + 0x22U))) & 0x4U) == 0U); } //***************************************************************************** // //! Disables the watchdog. //! //! This function disables the watchdog timer. Note that the watchdog timer is //! enabled on reset. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableWatchdog(void) { __eallow(); // // Set the disable bit. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) |= 0x0028U | 0x40U; __edis(); } //***************************************************************************** // //! Enables the watchdog. //! //! This function enables the watchdog timer. Note that the watchdog timer is //! enabled on reset. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableWatchdog(void) { __eallow(); // // Clear the disable bit. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) = ((*((volatile uint16_t *)(0x00007000U + 0x29U))) & ~0x40U) | 0x0028U; __edis(); } //***************************************************************************** // //! Services the watchdog. //! //! This function resets the watchdog. //! //! \return None. // //***************************************************************************** static inline void SysCtl_serviceWatchdog(void) { __eallow(); // // Enable the counter to be reset and then reset it. // (*((volatile uint16_t *)(0x00007000U + 0x25U))) = 0x0055U; (*((volatile uint16_t *)(0x00007000U + 0x25U))) = 0x00AAU; __edis(); } //***************************************************************************** // //! Sets up watchdog clock (WDCLK) pre-divider. //! //! \param predivider is the value that configures the pre-divider. //! //! This function sets up the watchdog clock (WDCLK) pre-divider. There are two //! dividers that scale INTOSC1 to WDCLK. The \e predivider parameter divides //! INTOSC1 down to PREDIVCLK and the prescaler (set by the //! SysCtl_setWatchdogPrescaler() function) divides PREDIVCLK down to WDCLK. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogPredivider(SysCtl_WDPredivider predivider) { uint16_t regVal; regVal = (uint16_t)predivider | (uint16_t)0x0028U; __eallow(); // // Write the predivider to the appropriate register. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) = ((*((volatile uint16_t *)(0x00007000U + 0x29U))) & ~(0xF00U)) | regVal; __edis(); } //***************************************************************************** // //! Sets up watchdog clock (WDCLK) prescaler. //! //! \param prescaler is the value that configures the watchdog clock relative //! to the value from the pre-divider. //! //! This function sets up the watchdog clock (WDCLK) prescaler. There are two //! dividers that scale INTOSC1 to WDCLK. The predivider (set with the //! SysCtl_setWatchdogPredivider() function) divides INTOSC1 down to PREDIVCLK //! and the \e prescaler parameter divides PREDIVCLK down to WDCLK. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler) { uint16_t regVal; regVal = (uint16_t)prescaler | (uint16_t)0x0028U; __eallow(); // // Write the prescaler to the appropriate register. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) = ((*((volatile uint16_t *)(0x00007000U + 0x29U))) & ~(0x7U)) | regVal; __edis(); } //***************************************************************************** // //! Gets the watchdog counter value. //! //! \return Returns the current value of the 8-bit watchdog counter. If this //! count value overflows, a watchdog output pulse is generated. // //***************************************************************************** static inline uint16_t SysCtl_getWatchdogCounterValue(void) { // // Read and return the value of the watchdog counter. // return((*((volatile uint16_t *)(0x00007000U + 0x23U)))); } //***************************************************************************** // //! Gets the watchdog reset status. //! //! This function returns the watchdog reset status. If this function returns //! \b true, that indicates that a watchdog reset generated the last reset //! condition. Otherwise, it was an external device or power-up reset //! condition. //! //! \return Returns \b true if the watchdog generated the last reset condition. // //***************************************************************************** static inline _Bool SysCtl_getWatchdogResetStatus(void) { // // Read and return the status of the watchdog reset status flag. // return(((*((volatile uint16_t *)(0x0005D300U + 0x80U))) & 0x4U) != 0U); } //***************************************************************************** // //! Clears the watchdog reset status. //! //! This function clears the watchdog reset status. To check if it was set //! first, see SysCtl_getWatchdogResetStatus(). //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearWatchdogResetStatus(void) { __eallow(); // // Read and return the status of the watchdog reset status flag. // (*((volatile uint16_t *)(0x0005D300U + 0x7EU))) = 0x4U; __edis(); } //***************************************************************************** // //! Set the minimum threshold value for windowed watchdog //! //! \param value is the value to set the window threshold //! //! This function sets the minimum threshold value used to define the lower //! limit of the windowed watchdog functionality. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogWindowValue(uint16_t value) { __eallow(); // // Clear the windowed value // (*((volatile uint16_t *)(0x00007000U + 0x2AU))) &= ~0xFFU; // // Set the windowed value // (*((volatile uint16_t *)(0x00007000U + 0x2AU))) |= (value & 0xFFU); __edis(); } //***************************************************************************** // //! Read NMI interrupts. //! //! Read the current state of NMI interrupt. //! //! \return \b true if NMI interrupt is triggered, \b false if not. // //***************************************************************************** static inline _Bool SysCtl_getNMIStatus(void) { // // Read and return the current value of the NMI flag register, masking out // all but the NMI bit. // return(((*((volatile uint16_t *)(0x00007060U + 0x1U))) & 0x1U) != 0U); } //***************************************************************************** // //! Read NMI Flags. //! //! Read the current state of individual NMI interrupts //! //! \return Value of NMIFLG register. These defines are provided to decode //! the value: //! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt //! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure //! - \b SYSCTL_NMI_RAMUNCERR - Uncorrectable RAM error //! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error //! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error //! - \b SYSCTL_NMI_SWERR - SW Error Force NMI Flag // //***************************************************************************** static inline uint32_t SysCtl_getNMIFlagStatus(void) { // // Read and return the current value of the NMI flag register. // return((*((volatile uint16_t *)(0x00007060U + 0x1U)))); } //***************************************************************************** // //! Check if the individual NMI interrupts are set. //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt //! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure //! - \b SYSCTL_NMI_RAMUNCERR - Uncorrectable RAM error //! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error //! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error //! - \b SYSCTL_NMI_SWERR - SW Error Force NMI Flag //! //! Check if interrupt flags corresponding to the passed in bit mask are //! asserted. //! //! \return \b true if any of the NMI asked for in the parameter bit mask //! is set. \b false if none of the NMI requested in the parameter bit mask are //! set. // //***************************************************************************** static inline _Bool SysCtl_isNMIFlagSet(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // ; // // Read the flag register and return true if any of them are set. // return(((*((volatile uint16_t *)(0x00007060U + 0x1U))) & nmiFlags) != 0U); } //***************************************************************************** // //! Function to clear individual NMI interrupts. //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_CLOCKFAIL //! - \b SYSCTL_NMI_RAMUNCERR //! - \b SYSCTL_NMI_FLUNCERR //! - \b SYSCTL_NMI_PIEVECTERR //! - \b SYSCTL_NMI_SWERR //! //! Clear NMI interrupt flags that correspond with the passed in bit mask. //! //! \b Note: The NMI Interrupt flag is always cleared by default and //! therefore doesn't have to be included in the bit mask. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearNMIStatus(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // ; __eallow(); // // Clear the individual flags as well as NMI Interrupt flag // (*((volatile uint16_t *)(0x00007060U + 0x2U))) = nmiFlags; (*((volatile uint16_t *)(0x00007060U + 0x2U))) = 0x1U; __edis(); } //***************************************************************************** // //! Clear all the NMI Flags that are currently set. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearAllNMIFlags(void) { uint32_t nmiFlags; // // Read the flag status register and then write to the clear register, // clearing all the flags that were returned plus the NMI flag. // __eallow(); nmiFlags = SysCtl_getNMIFlagStatus(); (*((volatile uint16_t *)(0x00007060U + 0x2U))) = nmiFlags; (*((volatile uint16_t *)(0x00007060U + 0x2U))) = 0x1U; __edis(); } //***************************************************************************** // //! Function to force individual NMI interrupt fail flags //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_CLOCKFAIL //! - \b SYSCTL_NMI_RAMUNCERR //! - \b SYSCTL_NMI_FLUNCERR //! - \b SYSCTL_NMI_PIEVECTERR //! - \b SYSCTL_NMI_SWERR //! //! \return None. // //***************************************************************************** static inline void SysCtl_forceNMIFlags(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // ; __eallow(); // // Set the Flags for the individual interrupts in the NMI flag // force register // (*((volatile uint16_t *)(0x00007060U + 0x3U))) |= nmiFlags; __edis(); } //***************************************************************************** // //! Gets the NMI watchdog counter value. //! //! \b Note: The counter is clocked at the SYSCLKOUT rate. //! //! \return Returns the NMI watchdog counter register's current value. // //***************************************************************************** static inline uint16_t SysCtl_getNMIWatchdogCounter(void) { // // Read and return the NMI watchdog counter register's value. // return((*((volatile uint16_t *)(0x00007060U + 0x4U)))); } //***************************************************************************** // //! Sets the NMI watchdog period value. //! //! \param wdPeriod is the 16-bit value at which a reset is generated. //! //! This function writes to the NMI watchdog period register that holds the //! value to which the NMI watchdog counter is compared. When the two registers //! match, a reset is generated. By default, the period is 0xFFFF. //! //! \note If a value smaller than the current counter value is passed into the //! \e wdPeriod parameter, a NMIRSn will be forced. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod) { __eallow(); // // Write to the period register. // (*((volatile uint16_t *)(0x00007060U + 0x5U))) = wdPeriod; __edis(); } //***************************************************************************** // //! Gets the NMI watchdog period value. //! //! \return Returns the NMI watchdog period register's current value. // //***************************************************************************** static inline uint16_t SysCtl_getNMIWatchdogPeriod(void) { // // Read and return the NMI watchdog period register's value. // return((*((volatile uint16_t *)(0x00007060U + 0x5U)))); } //***************************************************************************** // //! Read NMI Shadow Flags. //! //! Read the current state of individual NMI interrupts //! //! \return Value of NMISHDFLG register. These defines are provided to decode //! the value: //! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt //! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure //! - \b SYSCTL_NMI_RAMUNCERR - Uncorrectable RAM error //! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error //! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error //! - \b SYSCTL_NMI_SWERR - SW Error Force NMI Flag // //***************************************************************************** static inline uint32_t SysCtl_getNMIShadowFlagStatus(void) { // // Read and return the current value of the NMI shadow flag register. // return((*((volatile uint16_t *)(0x00007060U + 0x6U)))); } //***************************************************************************** // //! Check if the individual NMI shadow flags are set. //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_NMIINT //! - \b SYSCTL_NMI_CLOCKFAIL //! - \b SYSCTL_NMI_RAMUNCERR //! - \b SYSCTL_NMI_FLUNCERR //! - \b SYSCTL_NMI_PIEVECTERR //! - \b SYSCTL_NMI_SWERR //! //! Check if interrupt flags corresponding to the passed in bit mask are //! asserted. //! //! \return \b true if any of the NMI asked for in the parameter bit mask //! is set. \b false if none of the NMI requested in the parameter bit mask are //! set. // //***************************************************************************** static inline _Bool SysCtl_isNMIShadowFlagSet(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // ; // // Read the flag register and return true if any of them are set. // return(((*((volatile uint16_t *)(0x00007060U + 0x6U))) & nmiFlags) != 0U); } //***************************************************************************** // //! Enable the missing clock detection (MCD) Logic //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableMCD(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) &= ~(0x4U); __edis(); } //***************************************************************************** // //! Disable the missing clock detection (MCD) Logic //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableMCD(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) |= 0x4U; __edis(); } //***************************************************************************** // //! Get the missing clock detection Failure Status //! //! \note A failure means the oscillator clock is missing //! //! \return Returns \b true if a failure is detected or \b false if a //! failure isn't detected // //***************************************************************************** static inline _Bool SysCtl_isMCDClockFailureDetected(void) { // // Check the status bit to determine failure // return(((*((volatile uint16_t *)(0x0005D200U + 0x2EU))) & 0x1U) != 0U); } //***************************************************************************** // //! Reset the missing clock detection logic after clock failure //! //! \return None. // //***************************************************************************** static inline void SysCtl_resetMCD(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) |= 0x2U; __edis(); } //***************************************************************************** // //! Re-connect missing clock detection clock source to stop simulating clock //! failure //! //! \return None. // //***************************************************************************** static inline void SysCtl_connectMCDClockSource(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) &= ~(0x8U); __edis(); } //***************************************************************************** // //! Disconnect missing clock detection clock source to simulate clock failure. //! This is for testing the MCD functionality. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disconnectMCDClockSource(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) |= 0x8U; __edis(); } //***************************************************************************** // //! Lock the Access Control Registers //! //! This function locks the access control registers and puts them in a //! read-only state. //! //! \note Only a reset can unlock the access control registers. //! //! \return None. // //***************************************************************************** static inline void SysCtl_lockAccessControlRegs(void) { __eallow(); (*((volatile uint16_t *)(0x0005D500U + 0x1FEU))) |= 0x1U; __edis(); } //***************************************************************************** // //! Set the peripheral access control permissions //! //! \param peripheral is the selected peripheral //! \param master is the selected master (CPU1, CLA1, or DMA1) //! \param permission is the selected access permissions //! //! This function sets the specified peripheral access control permissions for //! the the specified master (CPU1, CLA1, or DMA1) //! //! The \e peripheral parameter can have one enumerated value in the format of //! \b SYSCTL_ACCESS_X where X is the name of the peripheral instance to be //! configured such as \b SYSCTL_ACCESS_ADCA. //! //! The \e master parameter can have one the following enumerated values: //! - \b SYSCTL_ACCESS_CPU1 - CPU1 Master //! - \b SYSCTL_ACCESS_CLA1 - CLA1 Master //! - \b SYSCTL_ACCESS_DMA1 - DMA1 Master //! //! The \e permission parameter can have one the following enumerated values: //! - \b SYSCTL_ACCESS_FULL - Full Access for both read and write //! - \b SYSCTL_ACCESS_PROTECTED - Protected read access such that FIFOs, clear //! on read registers are not changed, and no //! write access //! - \b SYSCTL_ACCESS_NONE - No read or write access //! //! \return None. // //***************************************************************************** static inline void SysCtl_setPeripheralAccessControl(SysCtl_AccessPeripheral peripheral, SysCtl_AccessMaster master, SysCtl_AccessPermission permission) { // // Set master permissions for specified peripheral. Each master has // two bits dedicated to its permission setting. // __eallow(); (*((volatile uint16_t *)(0x0005D500U + (uint16_t)peripheral))) = ((*((volatile uint16_t *)(0x0005D500U + (uint16_t)peripheral))) & ~(0x3U << (uint16_t)master)) | ((uint32_t)permission << (uint16_t)master); __edis(); } //***************************************************************************** // //! Get the peripheral access control permissions //! //! \param peripheral is the selected peripheral //! \param master is the selected master (CPU1, CLA1, or DMA1) //! //! This function gets the specified peripheral access control permissions for //! the the specified master (CPU1, CLA1, or DMA1) //! //! The \e peripheral parameter can have one enumerated value in the format of //! \b SYSCTL_ACCESS_X where X is the name of the peripheral instance to be //! configured such as \b SYSCTL_ACCESS_ADCA. //! //! The \e master parameter can have one the following enumerated values: //! - \b SYSCTL_ACCESS_CPU1 - CPU1 Master //! - \b SYSCTL_ACCESS_CLA1 - CLA1 Master //! - \b SYSCTL_ACCESS_DMA1 - DMA1 Master //! //! \return Returns one of the following enumerated permission values: //! - \b SYSCTL_ACCESS_FULL - Full Access for both read and write //! - \b SYSCTL_ACCESS_PROTECTED - Protected read access such that FIFOs, clear //! on read registers are not changed, and no //! write access //! - \b SYSCTL_ACCESS_NONE - No read or write access // //***************************************************************************** static inline uint32_t SysCtl_getPeripheralAccessControl(SysCtl_AccessPeripheral peripheral, SysCtl_AccessMaster master) { // // Read master permissions for specified peripheral. Each master has // two bits dedicated to its permission setting. // return(((*((volatile uint16_t *)(0x0005D500U + (uint16_t)peripheral))) >> (uint16_t)master) & 0x3U); } //***************************************************************************** // //! Configures the sync input source for the ePWM and eCAP signals. //! //! \param syncInput is the sync input being configured //! \param syncSrc is sync input source selection. //! //! This function configures the sync input source for the ePWM and eCAP //! modules. The \e syncInput parameter is the sync input being configured. It //! should be passed a value of \b SYSCTL_SYNC_IN_XXXX, where XXXX is the ePWM //! or eCAP instance the sync signal is entering. //! //! The \e syncSrc parameter is the sync signal selected as the source of the //! sync input. It should be passed a value of \b SYSCTL_SYNC_IN_SRC_XXXX, //! XXXX is a sync signal coming from an ePWM, eCAP or external sync output. //! where For example, a \e syncInput value of \b SYSCTL_SYNC_IN_ECAP1 and a //! \e syncSrc value of \b SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT will make the //! EPWM1SYNCOUT signal drive eCAP1's SYNCIN signal. //! //! Note that some \e syncSrc values are only valid for certain values of //! \e syncInput. See device technical reference manual for details on //! time-base counter synchronization. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setSyncInputConfig(SysCtl_SyncInput syncInput, SysCtl_SyncInputSource syncSrc) { uint32_t clearMask; // // Write the input sync source selection to the appropriate register. // __eallow(); if(syncInput == SYSCTL_SYNC_IN_EPWM1) { // Note that EXTSYNCIN1 is the only valid option for ePWM1 (*((volatile uint32_t *)(0x00007940U + 0x0U))) &= ~0xE0000000U; } else { clearMask = (uint32_t)0x7U << (uint32_t)syncInput; (*((volatile uint32_t *)(0x00007940U + 0x0U))) = ((*((volatile uint32_t *)(0x00007940U + 0x0U))) & ~clearMask) | ((uint32_t)syncSrc << (uint32_t)syncInput); } __edis(); } //***************************************************************************** // //! Configures the sync output source. //! //! \param syncSrc is sync output source selection. //! //! This function configures the sync output source from the ePWM modules. The //! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is //! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT //! //! \return None. // //***************************************************************************** static inline void SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc) { // // Write the sync output source selection to the appropriate register. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x0U))) = ((*((volatile uint32_t *)(0x00007940U + 0x0U))) & ~((uint32_t)0x18000000U)) | ((uint32_t)syncSrc << 27U); __edis(); } //***************************************************************************** // //! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal. //! //! \param adcsocSrc is a bit field of the selected signals to be enabled //! //! This function configures which ePWM SOC signals are enabled as a source for //! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR //! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different //! signals. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc) { // // Set the bits that correspond to signal to be enabled. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x2U))) |= adcsocSrc; __edis(); } //***************************************************************************** // //! Disables ePWM SOC signals from driving an external ADCSOC signal. //! //! \param adcsocSrc is a bit field of the selected signals to be disabled //! //! This function configures which ePWM SOC signals are disabled as a source //! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical //! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different //! signals. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc) { // // Clear the bits that correspond to signal to be disabled. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x2U))) &= ~adcsocSrc; __edis(); } //***************************************************************************** // //! Locks the SOC Select of the Trig X-BAR. //! //! This function locks the external ADC SOC select of the Trig X-BAR. //! //! \return None. // //***************************************************************************** static inline void SysCtl_lockExtADCSOCSelect(void) { // // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x4U))) = 0x2U; __edis(); } //***************************************************************************** // //! Locks the Sync Select of the Trig X-BAR. //! //! This function locks Sync Input and Output Select of the Trig X-BAR. //! //! \return None. // //***************************************************************************** static inline void SysCtl_lockSyncSelect(void) { // // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x4U))) = 0x1U; __edis(); } //***************************************************************************** // //! Get the Device Silicon Revision ID //! //! This function returns the silicon revision ID for the device. //! //! \return Returns the silicon revision ID value. // //***************************************************************************** static inline uint32_t SysCtl_getDeviceRevision(void) { // // Returns the device silicon revision ID // return((*((volatile uint32_t *)(0x0005D000U + 0xCU)))); } //***************************************************************************** // //! Delays for a fixed number of cycles. //! //! \param count is the number of delay loop iterations to perform. //! //! This function generates a constant length delay using assembly code. The //! loop takes 5 cycles per iteration plus 9 cycles of overhead. //! //! \note If count is equal to zero, the loop will underflow and run for a //! very long time. //! //! \return None. // //***************************************************************************** extern void SysCtl_delay(uint32_t count); //***************************************************************************** // //! Calculates the system clock frequency (SYSCLK). //! //! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). //! //! This function determines the frequency of the system clock based on the //! frequency of the oscillator clock source (from \e clockInHz) and the PLL //! and clock divider configuration registers. //! //! \return Returns the system clock frequency. If a missing clock is detected, //! the function will return the INTOSC1 frequency. This needs to be //! corrected and cleared (see SysCtl_resetMCD()) before trying to call this //! function again. // //***************************************************************************** extern uint32_t SysCtl_getClock(uint32_t clockInHz); //***************************************************************************** // //! Configures the clocking of the device. //! //! \param config is the required configuration of the device clocking. //! //! This function configures the clocking of the device. The input crystal //! frequency, oscillator to be used, use of the PLL, and the system clock //! divider are all configured with this function. //! //! The \e config parameter is the OR of several different values, many of //! which are grouped into sets where only one can be chosen. //! //! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x) //! where x is either 1 or an even value up to 126. //! //! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or //! \b SYSCTL_PLL_DISABLE. //! //! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value //! from 1 to 127. //! //! - The fractional multiplier is chosen with either \b SYSCTL_FMULT_0, //! \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or \b SYSCTL_FMULT_3_4. //! //! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2, //! \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_XTAL_SE or \b SYSCTL_OSCSRC_OSC1. //! //! This function uses the DCC to check that the PLLRAWCLK is running at the //! expected rate. If you are using the DCC, you must back up its configuration //! before calling this function and restore it afterward. //! //! \note See your device errata for more details about locking the PLL. //! //! \return Returns \b false if a missing clock error is detected. This needs //! to be cleared (see SysCtl_resetMCD()) before trying to call this function //! again. Also, returns \b false if the PLLRAWCLK is not running and its //! expected rate after \b SYSCTL_PLL_RETRIES retries. Otherwise, returns //! \b true. // //***************************************************************************** extern _Bool SysCtl_setClock(uint32_t config); //***************************************************************************** // //! Validates PLL Raw Clock Frequency (PLLRAWCLK) //! //! \param oscSource is the Clock Source for the PLL that is also used for DCC //! \param pllMult has the PLL Multiplier Register configuration which include //! integer and fractional multiplier used to configure the DCC Counter1 clock //! //! This function uses DCC module to validate the PLL clock frequency. //! It uses oscSource as a reference clock for DCC, and PLL is used as clock //! under test. As long as the Counter0 (running of oscSource) & Counter1 //! (running of PLL) expire at the same time, DCC will not generate an Error. //! This function gives 100 attempts for PLL to lock and make sure frequency //! is as expected. //! //! \note This function does not validate if PLL output frequency (PLLRAWCLK) //! is within the operating range as per the datasheet. //! //! - The \e oscSource parameter is the oscillator source chosen with //! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_XTAL_SE or //! \b SYSCTL_OSCSRC_OSC1. //! //! - The \e pllMult parameter is a bitwise OR of \b SYSCTL_IMULT(x) where x is //! a value from 1 to 127 and one of the following fractional values: //! \b SYSCTL_FMULT_0, \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or //! \b SYSCTL_FMULT_3_4. //! //! \return Returns \b true if the DCCSTATUS error flag is not set. //! Otherwise, returns \b false. // //***************************************************************************** extern _Bool SysCtl_isPLLValid(uint32_t oscSource,uint32_t pllMult); //***************************************************************************** // //! Configures the external oscillator for the clocking of the device. //! //! This function configures the external oscillator (XTAL) to be used for the //! clocking of the device in crystal mode. It follows the procedure to turn on //! the oscillator, wait for it to power up, and select it as the source of the //! system clock. //! //! Please note that this function blocks while it waits for the XTAL to power //! up. If the XTAL does not manage to power up properly, the function will //! loop for a long time. It is recommended that you modify this function to //! add an appropriate timeout and error-handling procedure. //! //! \return None. // //***************************************************************************** extern void SysCtl_selectXTAL(void); //***************************************************************************** // //! Configures the external oscillator for the clocking of the device in //! single-ended mode. //! //! This function configures the external oscillator (XTAL) to be used for the //! clocking of the device in single-ended mode. It follows the procedure to //! turn on the oscillator, wait for it to power up, and select it as the //! source of the system clock. //! //! Please note that this function blocks while it waits for the XTAL to power //! up. If the XTAL does not manage to power up properly, the function will //! loop for a long time. It is recommended that you modify this function to //! add an appropriate timeout and error-handling procedure. //! //! \return None. // //***************************************************************************** extern void SysCtl_selectXTALSingleEnded(void); //***************************************************************************** // //! Selects the oscillator to be used for the clocking of the device. //! //! \param oscSource is the oscillator source to be configured. //! //! This function configures the oscillator to be used in the clocking of the //! device. The \e oscSource parameter may take a value of //! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_XTAL_SE, or //! \b SYSCTL_OSCSRC_OSC1. //! //! \sa SysCtl_turnOnOsc() //! //! \return None. // //***************************************************************************** extern void SysCtl_selectOscSource(uint32_t oscSource); //***************************************************************************** // //! Calculates the low-speed peripheral clock frequency (LSPCLK). //! //! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). //! //! This function determines the frequency of the low-speed peripheral clock //! based on the frequency of the oscillator clock source (from \e clockInHz) //! and the PLL and clock divider configuration registers. //! //! \return Returns the low-speed peripheral clock frequency. // //***************************************************************************** extern uint32_t SysCtl_getLowSpeedClock(uint32_t clockInHz); //***************************************************************************** // //! Get the device part parametric value //! //! \param parametric is the requested device parametric value //! //! This function gets the device part parametric value. //! //! The \e parametric parameter can have one the following enumerated values: //! - \b SYSCTL_DEVICE_QUAL - Device Qualification Status //! - \b SYSCTL_DEVICE_PINCOUNT - Device Pin Count //! - \b SYSCTL_DEVICE_INSTASPIN - Device InstaSPIN Feature Set //! - \b SYSCTL_DEVICE_FLASH - Device Flash size (KB) //! - \b SYSCTL_DEVICE_FAMILY - Device Family //! - \b SYSCTL_DEVICE_PARTNO - Device Part Number //! - \b SYSCTL_DEVICE_CLASSID - Device Class ID //! //! \return Returns the specified parametric value. // //***************************************************************************** extern uint16_t SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric); //***************************************************************************** // // Close the Doxygen group. //! @} // //**************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** // // The key value for RAM initialization // // // RAM Initialization Register Mask // // // The Parity disable key value // //***************************************************************************** // // Miscellaneous defines for Message ID Types // //***************************************************************************** //***************************************************************************** // // These are the flags used by the flags parameter when calling // the CAN_setupMessageObject() function. // //***************************************************************************** //! This indicates that transmit interrupts should be enabled, or are enabled. //! This indicates that receive interrupts should be enabled, or are //! enabled. //! This indicates that a message object will use or is using filtering //! based on the object's message identifier. //! This indicates that a message object will use or is using filtering //! based on the direction of the transfer. //! This indicates that a message object will use or is using message //! identifier filtering based on the extended identifier. //! This indicates that this message object is part of a FIFO structure and //! not the final message object in a FIFO. //! This indicates that a message object has no flags set. //***************************************************************************** // // These definitions are used to specify interrupt sources to // CAN_enableInterrupt() and CAN_disableInterrupt(). // //***************************************************************************** //! This flag is used to allow a CAN controller to generate error //! interrupts. //! This flag is used to allow a CAN controller to generate status //! interrupts. //! This flag is used to allow a CAN controller to generate interrupts //! on interrupt line 0 //! This flag is used to allow a CAN controller to generate interrupts //! on interrupt line 1 //***************************************************************************** // // The following definitions contain all error or status indicators that can // be returned when calling the CAN_getStatus() function. // //***************************************************************************** //! CAN controller has detected a parity error. //! CAN controller has entered a Bus Off state. //! CAN controller error level has reached warning level. //! CAN controller error level has reached error passive level. //! A message was received successfully since the last read of this status. //! A message was transmitted successfully since the last read of this //! status. //! This is the mask for the last error code field. //! There was no error. //! A bit stuffing error has occurred. //! A formatting error has occurred. //! An acknowledge error has occurred. //! The bus remained a bit level of 1 for longer than is allowed. //! The bus remained a bit level of 0 for longer than is allowed. //! A CRC error has occurred. //***************************************************************************** // // The following macros are added for the Global Interrupt EN/FLG/CLR // register // //***************************************************************************** //! CANINT0 global interrupt bit //! CANINT1 global interrupt bit //***************************************************************************** // // The following macros are added for accessing the interrupt register and // the standard arbitration ID in the interface registers. // //***************************************************************************** //! Status of INT0ID //! IF1 Arbitration Standard ID Shift Offset //! IF1 Arbitration Standard ID Mask //! IF2 Arbitration Standard ID Shift Offset //! IF2 Arbitration Standard ID Mask //***************************************************************************** // //! This data type is used to identify the interrupt status register. This is //! used when calling the CAN_setupMessageObject() function. // //***************************************************************************** typedef enum { //! Set the message ID frame to standard. CAN_MSG_FRAME_STD, //! Set the message ID frame to extended. CAN_MSG_FRAME_EXT } CAN_MsgFrameType; //***************************************************************************** // //! This definition is used to determine the type of message object that will //! be set up via a call to the CAN_setupMessageObject() API. // //***************************************************************************** typedef enum { //! Transmit message object. CAN_MSG_OBJ_TYPE_TX, //! Transmit remote request message object CAN_MSG_OBJ_TYPE_TX_REMOTE, //! Receive message object. CAN_MSG_OBJ_TYPE_RX, //! Remote frame receive remote, with auto-transmit message object. CAN_MSG_OBJ_TYPE_RXTX_REMOTE } CAN_MsgObjType; //***************************************************************************** // //! This definition is used to determine the clock source that will //! be set up via a call to the CAN_selectClockSource() API. // //***************************************************************************** typedef enum { //! Peripheral System Clock Source CAN_CLOCK_SOURCE_SYS = 0x0, //! External Oscillator Clock Source CAN_CLOCK_SOURCE_XTAL = 0x1, //! Auxiliary Clock Input Source CAN_CLOCK_SOURCE_AUX = 0x2 } CAN_ClockSource; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! //! Checks a CAN base address. //! //! \param base is the base address of the CAN controller. //! //! This function determines if a CAN controller base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! \internal //! //! Copies data from a buffer to the CAN Data registers. //! //! \param data is a pointer to the data to be written out to the CAN //! controller's data registers. //! \param address is an int16_t pointer to the first register of the //! CAN controller's data registers. For example, in order to use the IF1 //! register set on CAN controller 0, the value would be: \b CANA_BASE \b + //! \b CAN_O_IF1DATA. //! \param size is the number of bytes to copy into the CAN controller. //! //! This function takes the steps necessary to copy data from a contiguous //! buffer in memory into the non-contiguous data registers used by the CAN //! controller. //! //! \return None. // //***************************************************************************** static void CAN_writeDataReg(const uint16_t *const data, int16_t *address, uint32_t size) { uint32_t idx; int16_t *dataReg = address; // // Loop always copies 1 byte per iteration. // for(idx = 0U; idx < size; idx++) { // // Write out the data 8 bits at a time. // if(dataReg != 0U) { __byte((int16_t *)(dataReg),0) = data[idx]; dataReg++; } } } //***************************************************************************** // //! \internal //! //! Copies data from a buffer to the CAN Data registers. //! //! \param data is a pointer to the location to store the data read from the //! CAN controller's data registers. //! \param address is an int16_t pointer to the first register of the //! CAN controller's data registers. For example, in order to use the IF1 //! register set on CAN controller 1, the value would be: \b CANA_BASE \b + //! \b CAN_O_IF1DATA. //! \param size is the number of bytes to copy from the CAN controller. //! //! This function takes the steps necessary to copy data to a contiguous buffer //! in memory from the non-contiguous data registers used by the CAN //! controller. //! //! \return None. // //***************************************************************************** static void CAN_readDataReg(uint16_t *data, int16_t *address, uint32_t size) { uint32_t idx; int16_t *dataReg = address; // // Loop always copies 1 byte per iteration. // for(idx = 0U; idx < size; idx++) { // // Read out the data // data[idx] = __byte((int16_t *)(dataReg),0); dataReg++; } } //***************************************************************************** // //! Initializes the CAN controller's RAM. //! //! \param base is the base address of the CAN controller. //! //! Performs the initialization of the RAM used for the CAN message objects. //! //! \return None. // //***************************************************************************** static inline void CAN_initRAM(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x40U))) = 0x10U | (0xAU); while(!(((*((volatile uint16_t *)(base + 0x40U))) & (0x003FU)) == (0x20U | 0x4U | 0x1U))) { // // Wait until RAM Init is complete // } } //***************************************************************************** // //! Select CAN Clock Source //! //! \param base is the base address of the CAN controller. //! \param source is the clock source to use for the CAN controller. //! //! This function selects the specified clock source for the CAN controller. //! //! The \e source parameter can be any one of the following: //! - \b CAN_CLOCK_SOURCE_SYS - Peripheral System Clock //! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator //! - \b CAN_CLOCK_SOURCE_AUX - Auxiliary Clock Input from GPIO //! //! \return None. // //***************************************************************************** static inline void CAN_selectClockSource(uint32_t base, CAN_ClockSource source) { // // Check the arguments. // ; // // Determine the CAN controller and set specified clock source // __eallow(); switch(base) { case 0x00048000U: (*((volatile uint16_t *)(0x0005D200U + 0xAU))) &= ~0xCU; (*((volatile uint16_t *)(0x0005D200U + 0xAU))) |= ((uint16_t)source << 2U); break; case 0x0004A000U: (*((volatile uint16_t *)(0x0005D200U + 0xAU))) &= ~0x30U; (*((volatile uint16_t *)(0x0005D200U + 0xAU))) |= ((uint16_t)source << 4U); break; default: // Do nothing. Not a valid mode value. break; } __edis(); } //***************************************************************************** // //! Starts the CAN Module's Operations //! //! \param base is the base address of the CAN controller. //! //! This function starts the CAN module's operations after initialization, //! which includes the CAN protocol controller state machine of the CAN core //! and the message handler state machine to begin controlling the CAN's //! internal data flow. //! //! \return None. // //***************************************************************************** static inline void CAN_startModule(uint32_t base) { // // Check the arguments. // ; // // Clear Init and CCE bits // (*((volatile uint16_t *)(base + 0x0U))) &= ~(0x1U | 0x40U); } //***************************************************************************** // //! Enables the CAN controller. //! //! \param base is the base address of the CAN controller to enable. //! //! Enables the CAN controller for message processing. Once enabled, the //! controller will automatically transmit any pending frames, and process any //! received frames. The controller can be stopped by calling //! CAN_disableController(). //! //! \return None. // //***************************************************************************** static inline void CAN_enableController(uint32_t base) { // // Check the arguments. // ; // // Clear the init bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x1U; } //***************************************************************************** // //! Disables the CAN controller. //! //! \param base is the base address of the CAN controller to disable. //! //! Disables the CAN controller for message processing. When disabled, the //! controller will no longer automatically process data on the CAN bus. The //! controller can be restarted by calling CAN_enableController(). The state //! of the CAN controller and the message objects in the controller are left as //! they were before this call was made. //! //! \return None. // //***************************************************************************** static inline void CAN_disableController(uint32_t base) { // // Check the arguments. // ; // // Set the init bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x1U; } //***************************************************************************** // //! Enables the test modes of the CAN controller. //! //! \param base is the base address of the CAN controller. //! \param mode are the the test modes to enable. //! //! Enables test modes within the controller. The following valid options for //! \e mode can be OR'ed together: //! - \b CAN_TEST_SILENT - Silent Mode //! - \b CAN_TEST_LBACK - Loopback Mode //! - \b CAN_TEST_EXL - External Loopback Mode //! //! \note Loopback mode and external loopback mode \b can \b not be //! enabled at the same time. //! //! \return None. // //***************************************************************************** static inline void CAN_enableTestMode(uint32_t base, uint16_t mode) { // // Check the arguments. // ; ; // // Clear the bits in the test register. // (*((volatile uint16_t *)(base + 0x14U))) &= ~((uint16_t)0x8U | (uint16_t)0x10U | (uint16_t)0x100U); // // Enable test mode and set the bits in the test register. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x80U; (*((volatile uint16_t *)(base + 0x14U))) |= mode; } //***************************************************************************** // //! Disables the test modes of the CAN controller. //! //! \param base is the base address of the CAN controller. //! //! Disables test modes within the controller and clears the test bits. //! //! \return None. // //***************************************************************************** static inline void CAN_disableTestMode(uint32_t base) { // // Check the arguments. // ; // // Clear the bits in the test register. // (*((volatile uint16_t *)(base + 0x14U))) &= ~((uint16_t)0x8U | (uint16_t)0x10U | (uint16_t)0x100U); // // Clear the test mode enable bit // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x80U; } //***************************************************************************** // //! Get the current settings for the CAN controller bit timing. //! //! \param base is the base address of the CAN controller. //! //! This function reads the current configuration of the CAN controller bit //! clock timing. //! //! \return Returns the value of the bit timing register. // //***************************************************************************** static inline uint32_t CAN_getBitTiming(uint32_t base) { // // Check the arguments. // ; // // Read and return BTR register // return(__byte_peripheral_32((uint32_t *)(base + 0xCU))); } //***************************************************************************** // //! Enables direct access to the RAM. //! //! \param base is the base address of the CAN controller. //! //! Enables direct access to the RAM while in Test mode. //! //! \note Test Mode must first be enabled to use this function. //! //! \return None. // //***************************************************************************** static inline void CAN_enableMemoryAccessMode(uint32_t base) { // // Check the arguments. // ; // // Set the RAM direct access bit // (*((volatile uint16_t *)(base + 0x14U))) |= 0x200U; } //***************************************************************************** // //! Disables direct access to the RAM. //! //! \param base is the base address of the CAN controller. //! //! Disables direct access to the RAM while in Test mode. //! //! \return None. // //***************************************************************************** static inline void CAN_disableMemoryAccessMode(uint32_t base) { // // Check the arguments. // ; // // Clear the RAM direct access bit // (*((volatile uint16_t *)(base + 0x14U))) &= ~0x200U; } //***************************************************************************** // //! Sets the interruption debug mode of the CAN controller. //! //! \param base is the base address of the CAN controller. //! \param enable is a flag to enable or disable the interruption debug mode. //! //! This function sets the interruption debug mode of the CAN controller. When //! the \e enable parameter is \b true, CAN will be configured to interrupt any //! transmission or reception and enter debug mode immediately after it is //! requested. When \b false, CAN will wait for a started transmission or //! reception to be completed before entering debug mode. //! //! \return None. // //***************************************************************************** static inline void CAN_setInterruptionDebugMode(uint32_t base, _Bool enable) { // // Check the arguments. // ; if(enable) { // // Enable interrupt debug support // (*((volatile uint16_t *)(base + 0x0U))) |= 0x100U; } else { // // Disable interrupt debug support // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x100U; } } //***************************************************************************** // //! Enables DMA Requests from the CAN controller. //! //! \param base is the base address of the CAN controller to enable. //! //! Enables the CAN controller DMA request lines for each of the 3 interface //! register sets. To actually assert the request line, the DMA Active bit //! must be set in the corresponding interface CMD register. //! //! \return None. // //***************************************************************************** static inline void CAN_enableDMARequests(uint32_t base) { // // Check the arguments. // ; // // Set the DMA enable bits in the control register. // __byte_peripheral_32((uint32_t *)(base + 0x0U)) |= (0x40000U | 0x80000U | 0x100000U); } //***************************************************************************** // //! Disables DMA Requests from the CAN controller. //! //! \param base is the base address of the CAN controller to enable. //! //! Disables the CAN controller DMA request lines for each of the 3 interface //! register sets. //! //! \return None. // //***************************************************************************** static inline void CAN_disableDMARequests(uint32_t base) { // // Check the arguments. // ; // // Clear the DMA enable bits in the control register. // __byte_peripheral_32((uint32_t *)(base + 0x0U)) &= ~(0x40000U | 0x80000U | 0x100000U); } //***************************************************************************** // //! Disables Auto-Bus-On. //! //! \param base is the base address of the CAN controller. //! //! Disables the Auto-Bus-On feature of the CAN controller. //! //! \return None. // //***************************************************************************** static inline void CAN_disableAutoBusOn(uint32_t base) { // // Check the arguments. // ; // // Clear the ABO bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x200U; } //***************************************************************************** // //! Enables Auto-Bus-On. //! //! \param base is the base address of the CAN controller. //! //! Enables the Auto-Bus-On feature of the CAN controller. Be sure to also //! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function. //! //! \return None. // //***************************************************************************** static inline void CAN_enableAutoBusOn(uint32_t base) { // // Check the arguments. // ; // // Set the ABO bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x200U; } //***************************************************************************** // //! Sets the time before a Bus-Off recovery sequence is started. //! //! \param base is the base address of the CAN controller. //! \param time is number of clock cycles before a Bus-Off recovery sequence //! is started. //! //! This function sets the number of clock cycles before a Bus-Off recovery //! sequence is started by clearing the Init bit. //! //! \note To enable this functionality, use CAN_enableAutoBusOn(). //! //! \return None. // //***************************************************************************** static inline void CAN_setAutoBusOnTime(uint32_t base, uint32_t time) { // // Check the arguments. // ; // // Set bus-off timer value // __byte_peripheral_32((uint32_t *)(base + 0x80U)) = time; } //***************************************************************************** // //! Enables individual CAN controller interrupt sources. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Enables specific interrupt sources of the CAN controller. Only enabled //! sources will cause a processor interrupt. //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_INT_ERROR - a controller error condition has occurred //! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has //! been detected //! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt //! line 0 //! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt //! line 1 //! //! \return None. // //***************************************************************************** static inline void CAN_enableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Enable the specified interrupts. // __byte_peripheral_32((uint32_t *)(base + 0x0U)) |= intFlags; } //***************************************************************************** // //! Disables individual CAN controller interrupt sources. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! Disables the specified CAN controller interrupt sources. Only enabled //! interrupt sources can cause a processor interrupt. //! //! The \e intFlags parameter has the same definition as in the //! CAN_enableInterrupt() function. //! //! \return None. // //***************************************************************************** static inline void CAN_disableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Disable the specified interrupts. // __byte_peripheral_32((uint32_t *)(base + 0x0U)) &= ~(intFlags); } //***************************************************************************** // //! Get the CAN controller Interrupt Line set for each mailbox //! //! \param base is the base address of the CAN controller. //! //! Gets which interrupt line each message object should assert when an //! interrupt occurs. Bit 0 corresponds to message object 32 and then bits //! 1 to 31 correspond to message object 1 through 31 respectively. Bits that //! are asserted indicate the message object should generate an interrupt on //! interrupt line 1, while bits that are not asserted indicate the message //! object should generate an interrupt on line 0. //! //! \return Returns the value of the interrupt muxing register. // //***************************************************************************** static inline uint32_t CAN_getInterruptMux(uint32_t base) { // // Check the arguments. // ; // // Get the interrupt muxing for the CAN peripheral // return(__byte_peripheral_32((uint32_t *)(base + 0xD8U))); } //***************************************************************************** // //! Set the CAN controller Interrupt Line for each mailbox //! //! \param base is the base address of the CAN controller. //! \param mux bit packed representation of which message objects should //! generate an interrupt on a given interrupt line. //! //! Selects which interrupt line each message object should assert when an //! interrupt occurs. Bit 0 corresponds to message object 32 and then bits //! 1 to 31 correspond to message object 1 through 31 respectively. Bits that //! are asserted indicate the message object should generate an interrupt on //! interrupt line 1, while bits that are not asserted indicate the message //! object should generate an interrupt on line 0. //! //! \return None. // //***************************************************************************** static inline void CAN_setInterruptMux(uint32_t base, uint32_t mux) { // // Check the arguments. // ; // // Set the interrupt muxing for the CAN peripheral // __byte_peripheral_32((uint32_t *)(base + 0xD8U)) = mux; } //***************************************************************************** // //! Enables the CAN controller automatic retransmission behavior. //! //! \param base is the base address of the CAN controller. //! //! Enables the automatic retransmission of messages with detected errors. //! //! \return None. // //***************************************************************************** static inline void CAN_enableRetry(uint32_t base) { // // Check the arguments. // ; // // Clearing the DAR bit tells the controller to not disable the // auto-retry of messages which were not transmitted or received // correctly. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x20U; } //***************************************************************************** // //! Disables the CAN controller automatic retransmission behavior. //! //! \param base is the base address of the CAN controller. //! //! Disables the automatic retransmission of messages with detected errors. //! //! \return None. // //***************************************************************************** static inline void CAN_disableRetry(uint32_t base) { // // Check the arguments. // ; // // Setting the DAR bit tells the controller to disable the auto-retry // of messages which were not transmitted or received correctly. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x20U; } //***************************************************************************** // //! Returns the current setting for automatic retransmission. //! //! \param base is the base address of the CAN controller. //! //! Reads the current setting for the automatic retransmission in the CAN //! controller and returns it to the caller. //! //! \return Returns \b true if automatic retransmission is enabled, \b false //! otherwise. // //***************************************************************************** static inline _Bool CAN_isRetryEnabled(uint32_t base) { // // Check the arguments. // ; // // Read the disable automatic retry setting from the CAN controller. // return((_Bool)(((*((volatile uint16_t *)(base + 0x0U))) & 0x20U) != 0x20U)); } //***************************************************************************** // //! Reads the CAN controller error counter register. //! //! \param base is the base address of the CAN controller. //! \param rxCount is a pointer to storage for the receive error counter. //! \param txCount is a pointer to storage for the transmit error counter. //! //! Reads the error counter register and returns the transmit and receive error //! counts to the caller along with a flag indicating if the controller receive //! counter has reached the error passive limit. The values of the receive and //! transmit error counters are returned through the pointers provided as //! parameters. //! //! After this call, \e rxCount will hold the current receive error count //! and \e txCount will hold the current transmit error count. //! //! \return Returns \b true if the receive error count has reached the error //! passive limit, and \b false if the error count is below the error passive //! limit. // //***************************************************************************** static inline _Bool CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount) { uint32_t canError = 0U; // // Check the arguments. // ; // // Read the current count of transmit/receive errors. // canError = __byte_peripheral_32((uint32_t *)(base + 0x8U)); // // Extract the error numbers from the register value. // *rxCount = (canError & 0x7F00U) >> 8U; *txCount = (canError & 0xFFU) >> 0U; return((_Bool)((canError & 0x8000U) != 0U)); } //***************************************************************************** // //! Reads the CAN controller error and status register. //! //! \param base is the base address of the CAN controller. //! //! Reads the error and status register of the CAN controller. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint16_t CAN_getStatus(uint32_t base) { // // Check the arguments. // ; // // Return error and status register value // return((*((volatile uint16_t *)(base + 0x4U)))); } //***************************************************************************** // //! Reads the CAN controller TX request register. //! //! \param base is the base address of the CAN controller. //! //! Reads the TX request register of the CAN controller. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint32_t CAN_getTxRequests(uint32_t base) { // // Check the arguments. // ; // // Return Tx requests register value // return(__byte_peripheral_32((uint32_t *)(base + 0x88U))); } //***************************************************************************** // //! Reads the CAN controller new data status register. //! //! \param base is the base address of the CAN controller. //! //! Reads the new data status register of the CAN controller for all message //! objects. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint32_t CAN_getNewDataFlags(uint32_t base) { // // Check the arguments. // ; // // Return new data register value // return(__byte_peripheral_32((uint32_t *)(base + 0x9CU))); } //***************************************************************************** // //! Reads the CAN controller valid message object register. //! //! \param base is the base address of the CAN controller. //! //! Reads the valid message object register of the CAN controller. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint32_t CAN_getValidMessageObjects(uint32_t base) { // // Check the arguments. // ; // // Return the valid message register value // return(__byte_peripheral_32((uint32_t *)(base + 0xC4U))); } //***************************************************************************** // //! Get the CAN controller interrupt cause. //! //! \param base is the base address of the CAN controller. //! //! This function returns the value of the interrupt register that indicates //! the cause of the interrupt. //! //! \return Returns the value of the interrupt register. // //***************************************************************************** static inline uint32_t CAN_getInterruptCause(uint32_t base) { // // Check the arguments. // ; // // Read interrupt identifier status // return(__byte_peripheral_32((uint32_t *)(base + 0x10U))); } //***************************************************************************** // //! Get the CAN controller pending interrupt message source. //! //! \param base is the base address of the CAN controller. //! //! Returns the value of the pending interrupts register that indicates //! which messages are the source of pending interrupts. //! //! \return Returns the value of the pending interrupts register. // //***************************************************************************** static inline uint32_t CAN_getInterruptMessageSource(uint32_t base) { // // Check the arguments. // ; // // Read message object interrupt status // return(__byte_peripheral_32((uint32_t *)(base + 0xB0U))); } //***************************************************************************** // //! CAN Global interrupt Enable function. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Enables specific CAN interrupt in the global interrupt enable register //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt Enable bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt Enable bit for CAN INT1 //! //! \return None. // //***************************************************************************** static inline void CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; ; // // Enable the requested interrupts // (*((volatile uint16_t *)(base + 0x50U))) |= intFlags; } //***************************************************************************** // //! CAN Global interrupt Disable function. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! Disables the specific CAN interrupt in the global interrupt enable register //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 //! //! \return None. // //***************************************************************************** static inline void CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; ; // // Disable the requested interrupts // (*((volatile uint16_t *)(base + 0x50U))) &= ~intFlags; } //***************************************************************************** // //! CAN Global interrupt Clear function. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be cleared. //! //! Clear the specific CAN interrupt bit in the global interrupt flag register. //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 //! //! \return None. // //***************************************************************************** static inline void CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; ; // // Clear the requested interrupts // (*((volatile uint16_t *)(base + 0x58U))) |= intFlags; } //***************************************************************************** // //! Get the CAN Global Interrupt status. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Check if any interrupt bit is set in the global interrupt flag register. //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 //! //! \return True if any of the requested interrupt bits are set. False, if //! none of the requested bits are set. // //***************************************************************************** static inline _Bool CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; ; // // Read and return the global interrupt flag register // return((_Bool)(((*((volatile uint16_t *)(base + 0x54U))) & intFlags) != 0U)); } //***************************************************************************** // //! Initializes the CAN controller //! //! \param base is the base address of the CAN controller. //! //! This function initializes the message RAM, which also clears all the //! message objects, and places the CAN controller in an init state. Write //! access to the configuration registers is available as a result, allowing //! the bit timing and message objects to be setup. //! //! \note To exit the initialization mode and start the CAN module, use the //! CAN_startModule() function. //! //! \return None. // //***************************************************************************** extern void CAN_initModule(uint32_t base); //***************************************************************************** // //! Sets the CAN Bit Timing based on requested Bit Rate. //! //! \param base is the base address of the CAN controller. //! \param clock is the CAN module clock frequency before the bit rate //! prescaler (Hertz) //! \param bitRate is the desired bit rate (bits/sec) //! \param bitTime is the number of time quanta per bit required for desired //! bit time (Tq) and must be in the range from 8 to 25 //! //! This function sets the CAN bit timing values for the bit rate passed in the //! \e bitRate and \e bitTime parameters based on the \e clock parameter. The //! CAN bit clock is calculated to be an average timing value that should work //! for most systems. If tighter timing requirements are needed, then the //! CAN_setBitTiming() function is available for full customization of all of //! the CAN bit timing values. //! //! \return None. // //***************************************************************************** extern void CAN_setBitRate(uint32_t base, uint32_t clock, uint32_t bitRate, uint16_t bitTime); //***************************************************************************** // //! Manually set the CAN controller bit timing. //! //! \param base is the base address of the CAN controller. //! \param prescaler is the baud rate prescaler //! \param prescalerExtension is the baud rate prescaler extension //! \param tSeg1 is the time segment 1 //! \param tSeg2 is the time segment 2 //! \param sjw is the synchronization jump width //! //! This function sets the various timing parameters for the CAN bus bit //! timing: baud rate prescaler, prescaler extension, time segment 1, //! time segment 2, and the Synchronization Jump Width. //! //! \return None. // //***************************************************************************** extern void CAN_setBitTiming(uint32_t base, uint16_t prescaler, uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, uint16_t sjw); //***************************************************************************** // //! Clears a CAN interrupt source. //! //! \param base is the base address of the CAN controller. //! \param intClr is a value indicating which interrupt source to clear. //! //! This function can be used to clear a specific interrupt source. The //! \e intClr parameter should be either a number from 1 to 32 to clear a //! specific message object interrupt or can be the following: //! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt. //! //! It is not necessary to use this function to clear an interrupt. This //! should only be used if the application wants to clear an interrupt source //! without taking the normal interrupt action. //! //! \return None. // //***************************************************************************** extern void CAN_clearInterruptStatus(uint32_t base, uint32_t intClr); //***************************************************************************** // //! Setup a Message Object //! //! \param base is the base address of the CAN controller. //! \param objID is the message object number to configure (1-32). //! \param msgID is the CAN message identifier used for the 11 or 29 bit //! identifiers //! \param frame is the CAN ID frame type //! \param msgType is the message object type //! \param msgIDMask is the CAN message identifier mask used when identifier //! filtering is enabled //! \param flags is the various flags and settings to be set for the message //! object //! \param msgLen is the number of bytes of data in the message object (0-8) //! //! This function sets the various values required for a message object. //! //! The \e frame parameter can be one of the following values: //! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier //! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier //! //! The \e msgType parameter can be one of the following values: //! - \b CAN_MSG_OBJ_TYPE_TX - Transmit Message //! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE - Transmit Remote Message //! - \b CAN_MSG_OBJ_TYPE_RX - Receive Message //! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with //! auto-transmit //! //! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags //! are required or the parameter can be a logical OR of any of the following //! values: //! - \b CAN_MSG_OBJ_TX_INT_ENABLE - Enable Transmit Interrupts //! - \b CAN_MSG_OBJ_RX_INT_ENABLE - Enable Receive Interrupts //! - \b CAN_MSG_OBJ_USE_ID_FILTER - Use filtering based on the Message ID //! - \b CAN_MSG_OBJ_USE_EXT_FILTER - Use filtering based on the Extended //! Message ID //! - \b CAN_MSG_OBJ_USE_DIR_FILTER - Use filtering based on the direction of //! the transfer //! - \b CAN_MSG_OBJ_FIFO - Message object is part of a FIFO //! structure and isn't the final message //! object in FIFO //! //! \return None. // //***************************************************************************** extern void CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, CAN_MsgFrameType frame, CAN_MsgObjType msgType, uint32_t msgIDMask, uint32_t flags, uint16_t msgLen); //***************************************************************************** // //! Sends a Message Object //! //! \param base is the base address of the CAN controller. //! \param objID is the object number to configure (1-32). //! \param msgLen is the number of bytes of data in the message object (0-8) //! \param msgData is a pointer to the message object's data //! //! This function is used to transmit a message object and the message data, //! if applicable. //! //! \note The message object requested by the \e objID must first be setup //! using the CAN_setupMessageObject() function. //! //! \return None. // //***************************************************************************** extern void CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, const uint16_t *msgData); //***************************************************************************** // //! Reads the data in a Message Object //! //! \param base is the base address of the CAN controller. //! \param objID is the object number to read (1-32). //! \param msgData is a pointer to the array to store the message data //! //! This function is used to read the data contents of the specified message //! object in the CAN controller. The data returned is stored in the //! \e msgData parameter. //! //! \note //! -# The message object requested by the \e objID must first be setup //! using the CAN_setupMessageObject() function. //! -# If the DLC of the received message is larger than the \e msgData //! buffer provided, then it is possible for a buffer overflow to occur. //! //! \return Returns \b true if new data was retrieved, else returns //! \b false to indicate no new data was retrieved. // //***************************************************************************** extern _Bool CAN_readMessage(uint32_t base, uint32_t objID, uint16_t *msgData); //***************************************************************************** // //! Transfers a CAN message between the IF registers and Message RAM. //! //! \param base is the base address of the CAN controller. //! \param interface is the interface to use for the transfer. Valid value are //! 1 or 2. //! \param objID is the object number to transfer (1-32). //! \param direction is the of the transfer. False is Message RAM to IF, True //! is IF to Message RAM. //! \param dmaRequest asserts the DMA request line after a transfer if //! set to True. //! //! This function transfers the contents of the interface registers to message //! RAM or vice versa depending on the value passed to direction. This //! function is designed to be used with DMA transfers. //! //! \return None. // //***************************************************************************** extern void CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, _Bool direction, _Bool dmaRequest); //***************************************************************************** // //! Clears a message object so that it is no longer used. //! //! \param base is the base address of the CAN controller. //! \param objID is the message object number to disable (1-32). //! //! This function frees the specified message object from use. Once a message //! object has been cleared, it will no longer automatically send or //! receive messages, or generate interrupts. //! //! \return None. // //***************************************************************************** extern void CAN_clearMessage(uint32_t base, uint32_t objID); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: cla.h // // TITLE: CLA Driver Implementation File // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup cla_api CLA //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_cla.h // // TITLE: Definitions for the CLA registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the CLA register offsets // //***************************************************************************** // MVECTBGRND. // Register // ground task. // ground task. // task. // Register // Register // Register // Register 0 // Register 1 // Register 2 // Register 3 //***************************************************************************** // // The following are defines for the bit fields in the MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTINTEN register // //***************************************************************************** // or End of Task interrupt. // or End of Task interrupt. // or End of Task interrupt. // or End of Task interrupt. // or End of Task interrupt. // or End of Task interrupt. // or End of Task interrupt. // or End of Task interrupt. //***************************************************************************** // // The following are defines for the bit fields in the _MSTSBGRND register // //***************************************************************************** // bit. // task can be interrupted. // trigger overflow. //***************************************************************************** // // The following are defines for the bit fields in the _MCTLBGRND register // //***************************************************************************** // trigger enable //***************************************************************************** // // The following are defines for the bit fields in the MIFR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MIOVF register // //***************************************************************************** // Flag // Flag // Flag // Flag // Flag // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the MIFRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MICLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MICLROVF register // //***************************************************************************** // Flag Clear // Flag Clear // Flag Clear // Flag Clear // Flag Clear // Flag Clear // Flag Clear // Flag Clear //***************************************************************************** // // The following are defines for the bit fields in the MIER register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MIRUN register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the _MSTF register // //***************************************************************************** // Mode //***************************************************************************** // // The following are defines for the bit fields in the _MPSACTL register // //***************************************************************************** // every cycle or when PAB // changes. // every cycle. //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to CLA_getBackgroundTaskStatus() as the //! \e stsFlag parameter. // //***************************************************************************** typedef enum { //! Run status CLA_BGSTS_RUNNING = 0x1U, //! Can BG task be interrupted? CLA_BGSTS_CANNOT_INTERRUPT = 0x2U, //! BG task hardware trigger overflow - if a second trigger occurs //! while the BG is already running, the overflow is set CLA_BGSTS_OVERFLOW = 0x4U } CLA_BGTaskStatus; //***************************************************************************** // // Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(), // and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt() // as the taskFlags parameter. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to CLA_getPendingTaskFlag(), // CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(), // CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt() // as the taskNumber parameter. // //***************************************************************************** typedef enum { CLA_TASK_1, //!< CLA Task 1 CLA_TASK_2, //!< CLA Task 2 CLA_TASK_3, //!< CLA Task 3 CLA_TASK_4, //!< CLA Task 4 CLA_TASK_5, //!< CLA Task 5 CLA_TASK_6, //!< CLA Task 6 CLA_TASK_7, //!< CLA Task 7 CLA_TASK_8 //!< CLA Task 8 } CLA_TaskNumber; //***************************************************************************** // //! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect //! parameter. // //***************************************************************************** typedef enum { CLA_MVECT_1 = 0x0U, //!< Task Interrupt Vector 1 CLA_MVECT_2 = 0x1U, //!< Task Interrupt Vector 2 CLA_MVECT_3 = 0x2U, //!< Task Interrupt Vector 3 CLA_MVECT_4 = 0x3U, //!< Task Interrupt Vector 4 CLA_MVECT_5 = 0x4U, //!< Task Interrupt Vector 5 CLA_MVECT_6 = 0x5U, //!< Task Interrupt Vector 6 CLA_MVECT_7 = 0x6U, //!< Task Interrupt Vector 7 CLA_MVECT_8 = 0x7U //!< Task Interrupt Vector 8 } CLA_MVECTNumber; //***************************************************************************** // //! Values that can be passed to CLA_setTriggerSource() as the \e trigger //! parameter. // //***************************************************************************** typedef enum { CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1 CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2 CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3 CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4 CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1 CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2 CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3 CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4 CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1 CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2 CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3 CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4 CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1 CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2 CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3 CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4 CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5 CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0 CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1 CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2 CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT CLA_TRIGGER_ECAP7INT = 81U, //!< CLA Task Trigger Source is ECAP7INT CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT CLA_TRIGGER_ECAP6INT2 = 92U, //!< CLA Task Trigger Source is ECAP6INT2 CLA_TRIGGER_ECAP7INT2 = 93U, //!< CLA Task Trigger Source is ECAP7INT2 CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT CLA_TRIGGER_SDFM1DRINT1 = 96U, //!< CLA Task Trigger Source is SDFM1DRINT1 CLA_TRIGGER_SDFM1DRINT2 = 97U, //!< CLA Task Trigger Source is SDFM1DRINT2 CLA_TRIGGER_SDFM1DRINT3 = 98U, //!< CLA Task Trigger Source is SDFM1DRINT3 CLA_TRIGGER_SDFM1DRINT4 = 99U, //!< CLA Task Trigger Source is SDFM1DRINT4 CLA_TRIGGER_PMBUSAINT = 105U, //!< CLA Task Trigger Source is PMBUSAINT CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT CLA_TRIGGER_LINAINT1 = 117U, //!< CLA Task Trigger Source is LINAINT1 CLA_TRIGGER_LINAINT0 = 118U, //!< CLA Task Trigger Source is LINAINT0 CLA_TRIGGER_CLA1PROMCRC = 121U, //!< CLA Task Trigger Source is CLA1PROMCRC CLA_TRIGGER_FSITXAINT1 = 123U, //!< CLA Task Trigger Source is FSITXAINT1 CLA_TRIGGER_FSITXAINT2 = 124U, //!< CLA Task Trigger Source is FSITXAINT2 CLA_TRIGGER_FSIRXAINT1 = 125U, //!< CLA Task Trigger Source is FSIRXAINT1 CLA_TRIGGER_FSIRXAINT2 = 126U, //!< CLA Task Trigger Source is FSIRXAINT2 } CLA_Trigger; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks a CLA base address. //! //! \param base is the base address of the CLA controller. //! //! This function determines if a CLA controller base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Map CLA Task Interrupt Vector //! //! \param base is the base address of the CLA controller. //! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8) //! the value of claIntVect can be any of the following: //! - \b CLA_MVECT_1 - Task Interrupt Vector 1 //! - \b CLA_MVECT_2 - Task Interrupt Vector 2 //! - \b CLA_MVECT_3 - Task Interrupt Vector 3 //! - \b CLA_MVECT_4 - Task Interrupt Vector 4 //! - \b CLA_MVECT_5 - Task Interrupt Vector 5 //! - \b CLA_MVECT_6 - Task Interrupt Vector 6 //! - \b CLA_MVECT_7 - Task Interrupt Vector 7 //! - \b CLA_MVECT_8 - Task Interrupt Vector 8 //! \param claTaskAddr is the start address of the code for task //! //! Each CLA Task (1 to 8) has its own MVECTx register. When a task is //! triggered, the CLA loads the MVECTx register of the task in question //! to the MPC (CLA program counter) and begins execution from that point. //! The CLA has a 16-bit address bus, and can therefore, access the lower //! 64 KW space. The MVECTx registers take an address anywhere in this space. //! //! \return None. // //***************************************************************************** static inline void CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect, uint16_t claTaskAddr) { // // Check the arguments. // ; // // Modify protected register // __eallow(); (*((volatile uint16_t *)(base + (uint16_t)claIntVect))) = claTaskAddr; __edis(); } //***************************************************************************** // //! Hard Reset //! //! \param base is the base address of the CLA controller. //! //! This function will cause a hard reset of the CLA and set all CLA registers //! to their default state. //! //! \return None. // //***************************************************************************** static inline void CLA_performHardReset(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Hard reset of the CLA // (*((volatile uint16_t *)(base + 0x10U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Soft Reset //! //! \param base is the base address of the CLA controller. //! //! This function will cause a soft reset of the CLA. This will stop the //! current task, clear the MIRUN flag and clear all bits in the MIER register. //! //! \return None. // //***************************************************************************** static inline void CLA_performSoftReset(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Soft reset of the CLA // (*((volatile uint16_t *)(base + 0x10U))) |= 0x2U; __edis(); } //***************************************************************************** // //! IACK enable //! //! \param base is the base address of the CLA controller. //! //! This function enables the main CPU to use the IACK #16bit instruction to //! set MIFR bits in the same manner as writing to the MIFRC register. //! //! \return None. // //***************************************************************************** static inline void CLA_enableIACK(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Enable the main CPU to use the IACK #16bit instruction // (*((volatile uint16_t *)(base + 0x10U))) |= 0x4U; __edis(); } //***************************************************************************** // //! IACK disable //! //! \param base is the base address of the CLA controller. //! //! This function disables the main CPU to use the IACK #16bit instruction to //! set MIFR bits in the same manner as writing to the MIFRC register. //! //! \return None. // //***************************************************************************** static inline void CLA_disableIACK(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Enable the main CPU to use the IACK #16bit instruction // (*((volatile uint16_t *)(base + 0x10U))) &= ~0x4U; __edis(); } //***************************************************************************** // //! Query task N to see if it is flagged and pending execution //! //! \param base is the base address of the CLA controller. //! \param taskNumber is the number of the task CLA_TASK_N where N is a number //! from 1 to 8. Do not use CLA_TASKFLAG_ALL. //! //! This function gets the status of each bit in the interrupt flag register //! corresponds to a CLA task. The corresponding bit is automatically set //! when the task is triggered (either from a peripheral, through software, or //! through the MIFRC register). The bit gets cleared when the CLA starts to //! execute the flagged task. //! //! \return \b True if the queried task has been triggered but pending //! execution. // //***************************************************************************** static inline _Bool CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber) { // // Check the arguments. // ; // // Read the run status register and return the appropriate value. // return((((*((volatile uint16_t *)(base + 0x20U))) >> (uint16_t)taskNumber) & 1U) != 0U); } //***************************************************************************** // //! Get status of All Task Interrupt Flag //! //! \param base is the base address of the CLA controller. //! //! This function gets the value of the interrupt flag register (MIFR) //! //! \return the value of Interrupt Flag Register (MIFR) // //***************************************************************************** static inline uint16_t CLA_getAllPendingTaskFlags(uint32_t base) { uint16_t status; // // Check the arguments. // ; // // Just return the Interrupt Flag Register (MIFR) since that is what was // requested. // status = (*((volatile uint16_t *)(base + 0x20U))); // // Return the Interrupt Flag Register value // return(status); } //***************************************************************************** // //! Get status of Task n Interrupt Overflow Flag //! //! \param base is the base address of the CLA controller. //! \param taskNumber is the number of the task CLA_TASK_N where N is a number //! from 1 to 8. Do not use CLA_TASKFLAG_ALL. //! //! This function gets the status of each bit in the overflow flag register //! corresponds to a CLA task, This bit is set when an interrupt overflow event //! has occurred for the specific task. //! //! \return True if any of task interrupt overflow has occurred. // //***************************************************************************** static inline _Bool CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber) { // // Check the arguments. // ; // // Read the run status register and return the appropriate value. // return((((*((volatile uint16_t *)(base + 0x21U))) >> (uint16_t)taskNumber) & 1U) != 0U); } //***************************************************************************** // //! Get status of All Task Interrupt Overflow Flag //! //! \param base is the base address of the CLA controller. //! //! This function gets the value of the Interrupt Overflow Flag Register //! //! \return the value of Interrupt Overflow Flag Register(MIOVF) // //***************************************************************************** static inline uint16_t CLA_getAllTaskOverflowFlags(uint32_t base) { uint16_t status; // // Check the arguments. // ; // // Just return Interrupt Overflow Flag Register(MIOVF) since that is what // was requested. // status = (*((volatile uint16_t *)(base + 0x21U))); // // Return the Interrupt Overflow Flag Register // return(status); } //***************************************************************************** // //! Clear the task interrupt flag //! //! \param base is the base address of the CLA controller. //! \param taskFlags is the bitwise OR of the tasks' flags to be cleared //! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL //! to clear all flags. //! //! This function is used to manually clear bits in the interrupt //! flag (MIFR) register //! //! \return None. // //***************************************************************************** static inline void CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags) { // // Check the arguments. // ; // //Modify protected register // __eallow(); // // Clear the task interrupt flag // (*((volatile uint16_t *)(base + 0x23U))) |= taskFlags; __edis(); } //***************************************************************************** // //! Force a CLA Task //! //! \param base is the base address of the CLA controller. //! \param taskFlags is the bitwise OR of the tasks' flags to be forced //! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL //! to force all tasks. //! //! This function forces a task through software. //! //! \return None. // //***************************************************************************** static inline void CLA_forceTasks(uint32_t base, uint16_t taskFlags) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Force the task interrupt. // (*((volatile uint16_t *)(base + 0x22U))) |= taskFlags; __edis(); } //***************************************************************************** // //! Enable CLA task(s) //! //! \param base is the base address of the CLA controller. //! \param taskFlags is the bitwise OR of the tasks' flags to be enabled //! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL //! to enable all tasks //! //! This function allows an incoming interrupt or main CPU software to //! start the corresponding CLA task. //! //! \return None. // //***************************************************************************** static inline void CLA_enableTasks(uint32_t base, uint16_t taskFlags) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Enable CLA task // (*((volatile uint16_t *)(base + 0x25U))) |= taskFlags; __edis(); } //***************************************************************************** // //! Disable CLA task interrupt //! //! \param base is the base address of the CLA controller. //! \param taskFlags is the bitwise OR of the tasks' flags to be disabled //! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL //! to disable all tasks //! //! This function disables CLA task interrupt by setting the MIER register bit //! to 0, while the corresponding task is executing this will have no effect //! on the task. The task will continue to run until it hits the MSTOP //! instruction. //! //! \return None. // //***************************************************************************** static inline void CLA_disableTasks(uint32_t base, uint16_t taskFlags) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Disable CLA task interrupt // (*((volatile uint16_t *)(base + 0x25U))) &= ~taskFlags; __edis(); } //***************************************************************************** // //! Get the value of a task run status //! //! \param base is the base address of the CLA controller. //! \param taskNumber is the number of the task CLA_TASK_N where N is a number //! from 1 to 8. Do not use CLA_TASKFLAG_ALL. //! //! This function gets the status of each bit in the Interrupt Run Status //! Register which indicates whether the task is currently executing //! //! \return True if the task is executing. // //***************************************************************************** static inline _Bool CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber) { // // Check the arguments. // ; // // Read the run status register and return the appropriate value. // return((((*((volatile uint16_t *)(base + 0x26U))) >> (uint16_t)taskNumber) & 1U) != 0U); } //***************************************************************************** // //! Get the value of all task run status //! //! \param base is the base address of the CLA controller. //! //! This function indicates which task is currently executing. //! //! \return the value of Interrupt Run Status Register (MIRUN) // //***************************************************************************** static inline uint16_t CLA_getAllTaskRunStatus(uint32_t base) { uint16_t status; // // Check the arguments. // ; // // Just return the Interrupt Run Status Register since that is what was // requested. // status = (*((volatile uint16_t *)(base + 0x26U))); // // Return the Interrupt Run Status Register (MIRUN) // return(status); } //***************************************************************************** // //! Get the value of Active register for MVECTBGRNDACTIVE //! //! \param base is the base address of the CLA controller. //! //! This function gives the current interrupted MPC value of the background //! task. //! //! \return the value of Active register for the Background Task Vector // //***************************************************************************** static inline uint16_t CLA_getBackgroundActiveVector(uint32_t base) { uint16_t status; // // Check the arguments. // ; // // Just return the Active register for the Background Task Vector since // that is what was requested. // status = (*((volatile uint16_t *)(base + 0x1BU))); // // Return the value of Active register for the Background Task Vector // return(status); } //***************************************************************************** // //! Enable the background task //! //! \param base is the base address of the CLA controller. //! //! This function enables the background task //! //! \return None. // //***************************************************************************** static inline void CLA_enableBackgroundTask(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Enable background task // (*((volatile uint16_t *)(base + 0x1EU))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Disable background task //! //! \param base is the base address of the CLA controller. //! //! This function disables the background task //! //! \return None. // //***************************************************************************** static inline void CLA_disableBackgroundTask(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Disables background task // (*((volatile uint16_t *)(base + 0x1EU))) &= ~0x8000U; __edis(); } //***************************************************************************** // //! Start background task //! //! \param base is the base address of the CLA controller. //! //! This function will start the background task, provided there are no other //! pending tasks. //! //! \return None. // //***************************************************************************** static inline void CLA_startBackgroundTask(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Start background task // (*((volatile uint16_t *)(base + 0x1EU))) |= 0x1U; __edis(); } //***************************************************************************** // //! Enable background task hardware trigger //! //! \param base is the base address of the CLA controller. //! //! This function enables hardware trigger for background task //! \note Trigger source for the background task will be MPERINT8.1. //! //! \return None. // //***************************************************************************** static inline void CLA_enableHardwareTrigger(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Enable background task hardware trigger // (*((volatile uint16_t *)(base + 0x1EU))) |= 0x2U; __edis(); } //***************************************************************************** // //! Disable background task hardware trigger //! //! \param base is the base address of the CLA controller. //! //! This function disables hardware trigger for background task //! //! \return None. // //***************************************************************************** static inline void CLA_disableHardwareTrigger(uint32_t base) { // // Check the arguments. // ; // // Modify protected register // __eallow(); // // Disables hardware trigger for background task // (*((volatile uint16_t *)(base + 0x1EU))) &= ~0x2U; __edis(); } //***************************************************************************** // //! Map background task vector //! //! \param base is the base address of the CLA controller. //! \param claTaskAddr is the start address of the code for task //! //! This function specifies the start address for the background task //! //! \return None. // //***************************************************************************** static inline void CLA_mapBackgroundTaskVector(uint32_t base, uint16_t claTaskAddr) { // // Check the arguments. // ; // // Modify protected register // __eallow(); (*((volatile uint16_t *)(base + 0x1FU))) = (uint16_t)claTaskAddr; __edis(); } //***************************************************************************** // //! Get Status register for the back ground task. //! //! \param base is the base address of the CLA controller. //! \param stsFlag is status item to be returned. //! //! The value of \e stsFlag can be any of the following: //! - \b CLA_BGSTS_RUNNING //! - \b CLA_BGSTS_CANNOT_INTERRUPT //! - \b CLA_BGSTS_OVERFLOW //! //! This function gets the status of background task //! //! \return Based on the value of \e stsFlag, the function will return: //! - \b CLA_BGSTS_RUNNING - The function will return \b true if the background //! task is running. //! - \b CLA_BGSTS_CANNOT_INTERRUPT - The function will return \b true if the //! background task will not be interrupted (when MSETC BGINTM is executed). //! - \b CLA_BGSTS_OVERFLOW - This function will return \b true if an enabled //! hardware trigger occurred while _MCTLBGRND.BGSTART is set. // //***************************************************************************** static inline _Bool CLA_getBackgroundTaskStatus(uint32_t base, CLA_BGTaskStatus stsFlag) { // // Check the arguments. // ; ; // // Return the background task status value // return(((*((volatile uint16_t *)(base + 0x1DU))) & (uint16_t)stsFlag) != 0U); } // // These functions are accessible only from the CLA (Type - 1/2) // // // These functions can only be called from the C28x // //***************************************************************************** // //! Configures CLA task triggers. //! //! \param taskNumber is the number of the task CLA_TASK_N where N is a number //! from 1 to 8. //! \param trigger is the trigger source to be assigned to the selected task. //! //! This function configures the trigger source of a CLA task. The //! \e taskNumber parameter indicates which task is being configured, and the //! \e trigger parameter is the interrupt source from a specific peripheral //! interrupt (or software) that will trigger the task. //! //! \return None. // //***************************************************************************** extern void CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: clapromcrc.h // // TITLE: C28x and CLA CLAPROMCRC driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup clapromcrc_api CLAPROMCRC //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_clapromcrc.h // // TITLE: Definitions for the CLAPROMCRC registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the CLAPROMCRC register offsets // //***************************************************************************** // register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the CRC32_CONTROLREG register // //***************************************************************************** // CRC is to be calculated //***************************************************************************** // // The following are defines for the bit fields in the CRC32_STATUSREG register // //***************************************************************************** // current address //***************************************************************************** // // The following are defines for the bit fields in the CRC32_INTEN register // //***************************************************************************** // register //***************************************************************************** // // The following are defines for the bit fields in the CRC32_FLG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CRC32_CLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CRC32_FRC register // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to CLAPROMCRC_setEmulationMode(). // //***************************************************************************** typedef enum { CLAPROMCRC_MODE_SOFT = 0x00, //!< Soft Mode CLAPROMCRC_MODE_FREE = 0x10 //!< Free Mode } CLAPROMCRC_EmulationMode; //***************************************************************************** // //! Values that can be passed to CLAPROMCRC_getInterruptStatus() and //! CLAPROMCRC_clearInterruptFlag(). // //***************************************************************************** typedef enum { CLAPROMCRC_INT_FLG = 0x01, //!< Global Interrupt Flag CLAPROMCRC_CRCDONE_FLG = 0x02 //!< CRCDONE Interrupt Flag } CLAPROMCRC_IntFlag; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks an CLAPROMCRC base address. //! //! \param base specifies the CLAPROMCRC module base address. //! //! This function determines if the CLAPROMCRC module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Sets the Emulation Mode. //! //! \param base is the base address of the CLAPROMCRC module. //! \param emulationMode is soft mode or free mode. It can take values //! CLAPROMCRC_MODE_SOFT or CLAPROMCRC_MODE_FREE. //! //! This function sets the emulation mode which controls the behaviour of the //! CRC32 calculation during emulation. CLAPROMCRC_MODE_SOFT mode will stop the //! CLAPROMCRC module on CLA debug suspend. CLAPROMCRC_MODE_FREE mode sets the //! CLAPROMCRC module so that the CRC32 calculation is not affected by debug //! halt of the CLA. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_setEmulationMode(uint32_t base, CLAPROMCRC_EmulationMode emulationMode) { ; __eallow(); // // Clear the FREE_SOFT bit. // (*((volatile uint16_t *)(base + 0x0U))) &= ~(0x10U); // // Write the emulation mode to the FREE_SOFT bit. // (*((volatile uint16_t *)(base + 0x0U))) = (*((volatile uint16_t *)(base + 0x0U))) | (uint16_t)emulationMode; __edis(); } //***************************************************************************** // //! Starts the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function starts CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_start(uint32_t base) { ; __eallow(); // // Write to the START bit. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Halts the CRC32 calculations. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function halts the CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_halt(uint32_t base) { ; __eallow(); // // Write to the HALT bit. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x100U; __edis(); } //***************************************************************************** // //! Resumes the CRC32 calculations. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function resumes the CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_resume(uint32_t base) { ; __eallow(); // // Clear the HALT bit. // (*((volatile uint16_t *)(base + 0x0U))) &= ~(0x100U); __edis(); } //***************************************************************************** // //! Sets the Block Size of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! \param blockSize is the number of KB. The maximum value is 128 KB //! //! This function sets the block size for the CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_setBlockSize(uint32_t base, uint16_t blockSize) { ; ; ; __eallow(); // // Clear the BLOCKSIZE field. // (*((volatile uint32_t *)(base + 0x0U))) &= ~((uint32_t)0x7F0000U); // // Subtract 1 from blockSize and write it to the BLOCKSIZE field. // (*((volatile uint32_t *)(base + 0x0U))) |= (((uint32_t)blockSize - 1UL) << 16U) & 0x7F0000U; __edis(); } //***************************************************************************** // //! Sets the Start Address of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! \param startAddress defines the starting point for the CRC32 calculation. //! A startAddress corresponding to the CLA memory map is to be used. //! startAddress has to be a 1KB aligned address. If it is not aligned, then //! the LSB bits are ignored to get a 1KB aligned address. //! //! This function sets the start address with \e startAddress for the CRC32 //! calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_setStartAddress(uint32_t base, uint32_t startAddress) { ; __eallow(); // // Write the STARTADDRESS register. // (*((volatile uint32_t *)(base + 0x2U))) = startAddress; __edis(); } //***************************************************************************** // //! Sets the Seed of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! \param seed is the initial value of the CRC32 calculation. //! //! This function sets the seed with \e Seed for CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_setSeed(uint32_t base, uint32_t seed) { ; __eallow(); // // Write to the SEED register. // (*((volatile uint32_t *)(base + 0x4U))) = seed; __edis(); } //***************************************************************************** // //! Gets the Current Address of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function returns the current CLA memory map address of the data fetch //! unit of the CLAPROMCRC. //! //! \return Returns the current address. // //***************************************************************************** static inline uint16_t CLAPROMCRC_getCurrentAddress(uint32_t base) { ; // // Returns the lower 16 bits of STATUSREG which corresponds to the // CURRENTADDR field. // return((*((volatile uint16_t *)(base + 0x6U)))); } //***************************************************************************** // //! Check the status of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function returns the status for the CLAPROMCRC. Return value of true //! means PASS. Return value of false means FAIL. The comparison is enabled //! after CRC calculation is completed. //! //! \return Returns true (PASS) or false (FAIL) as the status of the CRC32 //! calculation. // //***************************************************************************** static inline _Bool CLAPROMCRC_checkStatus(uint32_t base) { ; // // If the CRCCHECKSTATUS bit is set, then return false corresponding to // FAIL. // return(!(((*((volatile uint32_t *)(base + 0x6U))) & 0x800000U) == 0x800000U)); } //***************************************************************************** // //! Gets the Run Status of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function returns the run status for the CLAPROMCRC with the base //! address passed in the \e base parameter. Return value of false means IDLE. //! Return value of true means ACTIVE. //! //! \return Returns true (Active) or false (Idle) as the run status of the //! CRC32 calculation. // //***************************************************************************** static inline _Bool CLAPROMCRC_getRunStatus(uint32_t base) { ; // // If the RUNSTATUS bit is set, then return true corresponding to Active. // return(((*((volatile uint32_t *)(base + 0x6U))) & 0x80000000U) == 0x80000000U); } //***************************************************************************** // //! Gets the Result of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function returns the result of the CRC32 calculation. //! //! \return Returns the result of the CRC32 calculation. // //***************************************************************************** static inline uint32_t CLAPROMCRC_getResult(uint32_t base) { ; // // Return the 32-bit CRCRESULT register. // return((*((volatile uint32_t *)(base + 0x8U)))); } //***************************************************************************** // //! Sets the Golden CRC of the CRC32 calculation. //! //! \param base is the base address of the CLAPROMCRC module. //! \param goldenCRC is value which will be compared with CRCRESULT. //! //! This function sets the GOLDENCRC register with \e goldenCRC for the //! CLAPROMCRC module. The value of GOLDENCRC is compared with CRCRESULT to //! determine a PASS or FAIL. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_setGoldenCRC(uint32_t base, uint32_t goldenCRC) { ; // // Write goldenCRC to the GOLDENCRC register. // (*((volatile uint32_t *)(base + 0xAU))) = goldenCRC; } //***************************************************************************** // //! Disables Interrupts the CRC32 calculations. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function disables interrupts for the CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_disableDoneInterrupt(uint32_t base) { ; __eallow(); // // Disable the CRCDONE interrupt. // (*((volatile uint16_t *)(base + 0x18U))) &= ~0x2U; __edis(); } //***************************************************************************** // //! Enables Interrupts the CRC32 calculations. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function enables interrupts for the CRC32 calculation. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_enableDoneInterrupt(uint32_t base) { ; __eallow(); // // Enable the CRCDONE interrupt. // (*((volatile uint16_t *)(base + 0x18U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Gets the Interrupt Status of of flag. //! //! \param base is the base address of the CLAPROMCRC module. //! \param intFlag is a CLAPROMCRC_IntFlag type and is either //! CLAPROMCRC_INT_FLG or CLAPROMCRC_CRCDONE_FLG. //! //! This function returns the interrupt status for \e intFlag. Return value of //! false means no interrupt generated. Return value of true means interrupt //! was generated. //! //! \return Returns the interrupt status. True means interrupt was generated //! and false means no interrupt was generated. // //***************************************************************************** static inline _Bool CLAPROMCRC_getInterruptStatus(uint32_t base, CLAPROMCRC_IntFlag intFlag) { ; // // Return the status of the interrupt flag. // return(((*((volatile uint16_t *)(base + 0x1AU))) & (uint16_t)intFlag ) == (uint16_t)intFlag); } //***************************************************************************** // //! Clears the Global Interrupt Flag of the CLAPROMCRC. //! //! \param base is the base address of the CLAPROMCRC module. //! \param intFlag is either CLAPROMCRC_INT_FLG or CLAPROMCRC_CRCDONE_FLG. //! //! This function clears the interrupt flag for the CLAPROMCRC with the base //! address passed in the \e base parameter. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_clearInterruptFlag(uint32_t base, CLAPROMCRC_IntFlag intFlag) { ; // // Clear the interrupt flag. // (*((volatile uint16_t *)(base + 0x1CU))) = (*((volatile uint16_t *)(base + 0x1CU))) | (uint16_t)intFlag; } //***************************************************************************** // //! Force the CRCDONE Interrupt Flag of the CLAPROMCRC. //! //! \param base is the base address of the CLAPROMCRC module. //! //! This function forces the CRCDONE interrupt flag for the CLAPROMCRC with the //! base address passed in the \e base parameter. //! //! \return None. // //***************************************************************************** static inline void CLAPROMCRC_forceDoneFlag(uint32_t base) { ; // // Force the CRCDONE interrupt flag. // (*((volatile uint16_t *)(base + 0x1EU))) |= 0x2U; } //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: cmpss.h // // TITLE: C28x CMPSS driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup cmpss_api CMPSS //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_cmpss.h // // TITLE: Definitions for the CMPSS registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the CMPSS register offsets // //***************************************************************************** // Register // Control Register // Register // Register // Register // Register // Active Register // Shadow Register // Active Register // Shadow Register // Register // Register // Register // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the COMPCTL register // //***************************************************************************** // Select // Path Enable // Select // Path Enable //***************************************************************************** // // The following are defines for the bit fields in the COMPHYSCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the COMPSTS register // //***************************************************************************** // Status //***************************************************************************** // // The following are defines for the bit fields in the COMPSTSCLR register // //***************************************************************************** // Status Clear // Enable // Clear // Enable //***************************************************************************** // // The following are defines for the bit fields in the COMPDACCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACHVALS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACHVALA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACLVALS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACLVALA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RAMPDLYA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RAMPDLYS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CTRIPLFILCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CTRIPLFILCLKCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CTRIPHFILCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CTRIPHFILCLKCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the COMPLOCK register // //***************************************************************************** //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to CMPSS_configLowComparator() and // CMPSS_configHighComparator() as the config parameter. // //***************************************************************************** // Comparator negative input source //! Input driven by internal DAC //! Input driven by external pin // Extra options //! Comparator output is inverted //! Asynch comparator output feeds into OR with latched digital filter output //***************************************************************************** // // Values that can be passed to CMPSS_configOutputsLow() and // CMPSS_configOutputsHigh() as the config parameter. // //***************************************************************************** // Signal driving CTRIPOUT //! Asynchronous comparator output drives CTRIPOUT //! Synchronous comparator output drives CTRIPOUT //! Filter output drives CTRIPOUT //! Latched filter output drives CTRIPOUT // Signal driving CTRIP //! Asynchronous comparator output drives CTRIP //! Synchronous comparator output drives CTRIP //! Filter output drives CTRIP //! Latched filter output drives CTRIP //***************************************************************************** // // Values that can be returned by CMPSS_getStatus(). // //***************************************************************************** //! High digital filter output //! Latched value of high digital filter output //! Low digital filter output //! Latched value of low digital filter output //***************************************************************************** // // Values that can be passed to CMPSS_configDAC() the config parameter. // //***************************************************************************** // When is DAC value loaded from shadow register //! DAC value updated from SYSCLK //! DAC value updated from PWMSYNC // DAC reference voltage //! VDDA is the voltage reference //! VDAC is the voltage reference // DAC value source //! DAC value updated from shadow register //! DAC value is updated from the ramp register //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks a CMPSS base address. //! //! \param base is the base address of the CMPSS module. //! //! This function determines if a CMPSS base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enables the CMPSS module. //! //! \param base is the base address of the CMPSS module. //! //! This function enables the CMPSS module passed into the \e base parameter. //! //! \return None. // //***************************************************************************** static inline void CMPSS_enableModule(uint32_t base) { // // Check the arguments. // ; // // Set the bit that enables the CMPSS module. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Disables the CMPSS module. //! //! \param base is the base address of the CMPSS module. //! //! This function disables the CMPSS module passed into the \e base parameter. //! //! \return None. // //***************************************************************************** static inline void CMPSS_disableModule(uint32_t base) { // // Check the arguments. // ; // // Clear the bit that enables the CMPSS module. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) &= ~0x8000U; __edis(); } //***************************************************************************** // //! Sets the configuration for the high comparator. //! //! \param base is the base address of the CMPSS module. //! \param config is the configuration of the high comparator. //! //! This function configures a comparator. The \e config parameter is the //! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if //! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. //! //! The \b CMPSS_INSRC_xxx term can take on the following values to specify //! the high comparator negative input source: //! - \b CMPSS_INSRC_DAC - The internal DAC. //! - \b CMPSS_INSRC_PIN - An external pin. //! //! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output //! should be inverted. //! //! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the //! asynchronous comparator output should be fed into an OR gate with the //! latched digital filter output before it is made available for CTRIPH or //! CTRIPOUTH. //! //! \return None. // //***************************************************************************** static inline void CMPSS_configHighComparator(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the high comparator configuration to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0x1U | 0x2U | 0x40U)) | config; __edis(); } //***************************************************************************** // //! Sets the configuration for the low comparator. //! //! \param base is the base address of the CMPSS module. //! \param config is the configuration of the low comparator. //! //! This function configures a comparator. The \e config parameter is the //! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if //! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. //! //! The \b CMPSS_INSRC_xxx term can take on the following values to specify //! the low comparator negative input source: //! - \b CMPSS_INSRC_DAC - The internal DAC. //! - \b CMPSS_INSRC_PIN - An external pin. //! //! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output //! should be inverted. //! //! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the //! asynchronous comparator output should be fed into an OR gate with the //! latched digital filter output before it is made available for CTRIPL or //! CTRIPOUTL. //! //! \return None. // //***************************************************************************** static inline void CMPSS_configLowComparator(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the low comparator configuration to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0x100U | 0x200U | 0x4000U)) | (config << 8U); __edis(); } //***************************************************************************** // //! Sets the output signal configuration for the high comparator. //! //! \param base is the base address of the CMPSS module. //! \param config is the configuration of the high comparator output signals. //! //! This function configures a comparator's output signals CTRIP and CTRIPOUT. //! The \e config parameter is the result of a logical OR operation between the //! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. //! //! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify //! which signal drives CTRIPOUTH: //! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. //! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. //! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. //! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. //! //! The \b CMPSS_TRIP_xxx term can take on the following values to specify //! which signal drives CTRIPH: //! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. //! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. //! - \b CMPSS_TRIP_FILTER - The output of the digital filter. //! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. //! //! \return None. // //***************************************************************************** static inline void CMPSS_configOutputsHigh(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the high comparator output settings to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0x30U | 0xCU)) | config; __edis(); } //***************************************************************************** // //! Sets the output signal configuration for the low comparator. //! //! \param base is the base address of the CMPSS module. //! \param config is the configuration of the low comparator output signals. //! //! This function configures a comparator's output signals CTRIP and CTRIPOUT. //! The \e config parameter is the result of a logical OR operation between the //! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. //! //! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify //! which signal drives CTRIPOUTL: //! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. //! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. //! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. //! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. //! //! The \b CMPSS_TRIP_xxx term can take on the following values to specify //! which signal drives CTRIPL: //! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. //! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. //! - \b CMPSS_TRIP_FILTER - The output of the digital filter. //! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. //! //! \return None. // //***************************************************************************** static inline void CMPSS_configOutputsLow(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the low comparator output settings to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0x3000U | 0xC00U)) | (config << 8U); __edis(); } //***************************************************************************** // //! Gets the current comparator status. //! //! \param base is the base address of the comparator module. //! //! This function returns the current status for the comparator, specifically //! the digital filter output and latched digital filter output. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! the following values: //! - \b CMPSS_STS_HI_FILTOUT - High digital filter output //! - \b CMPSS_STS_HI_LATCHFILTOUT - Latched value of high digital filter //! output //! - \b CMPSS_STS_LO_FILTOUT - Low digital filter output //! - \b CMPSS_STS_LO_LATCHFILTOUT - Latched value of low digital filter output // //***************************************************************************** static inline uint16_t CMPSS_getStatus(uint32_t base) { // // Check the arguments. // ; // // Return contents of the status register. // return((*((volatile uint16_t *)(base + 0x2U)))); } //***************************************************************************** // //! Sets the configuration for the internal comparator DACs. //! //! \param base is the base address of the CMPSS module. //! \param config is the configuration of the internal DAC. //! //! This function configures the comparator's internal DAC. The \e config //! parameter is the result of a logical OR operation between the //! \b CMPSS_DACVAL_xxx, \b CMPSS_DACREF_xxx, and \b CMPSS_DACSRC_xxx. //! //! The \b CMPSS_DACVAL_xxx term can take on the following values to specify //! when the DAC value is loaded from its shadow register: //! - \b CMPSS_DACVAL_SYSCLK - Value register updated on system clock. //! - \b CMPSS_DACVAL_PWMSYNC - Value register updated on PWM sync. //! //! The \b CMPSS_DACREF_xxx term can take on the following values to specify //! which voltage supply is used as reference for the DACs: //! - \b CMPSS_DACREF_VDDA - VDDA is the voltage reference for the DAC. //! - \b CMPSS_DACREF_VDAC - VDAC is the voltage reference for the DAC. //! //! The \b CMPSS_DACSRC_xxx term can take on the following values to specify //! the DAC value source for the high comparator's internal DAC: //! - \b CMPSS_DACSRC_SHDW - The user-programmed DACVALS register. //! - \b CMPSS_DACSRC_RAMP - The ramp generator RAMPSTS register //! //! \note The \b CMPSS_DACVAL_xxx and \b CMPSS_DACREF_xxx terms apply to //! both the high and low comparators. \b CMPSS_DACSRC_xxx will only affect //! the high comparator's internal DAC. //! //! \return None. // //***************************************************************************** static inline void CMPSS_configDAC(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the DAC configuration to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & ~(0x80U | 0x20U | 0x1U)) | config; __edis(); } //***************************************************************************** // //! Sets the value of the internal DAC of the high comparator. //! //! \param base is the base address of the comparator module. //! \param value is the value actively driven by the DAC. //! //! This function sets the 12-bit value driven by the internal DAC of the high //! comparator. This function will load the value into the shadow register from //! which the actual DAC value register will be loaded. To configure which //! event causes this shadow load to take place, use CMPSS_configDAC(). //! //! \return None. // //***************************************************************************** static inline void CMPSS_setDACValueHigh(uint32_t base, uint16_t value) { // // Check the arguments. // ; ; // // Write the DAC value to the DAC value shadow register. // (*((volatile uint16_t *)(base + 0x6U))) = value; } //***************************************************************************** // //! Sets the value of the internal DAC of the low comparator. //! //! \param base is the base address of the comparator module. //! \param value is the value actively driven by the DAC. //! //! This function sets the 12-bit value driven by the internal DAC of the low //! comparator. This function will load the value into the shadow register from //! which the actual DAC value register will be loaded. To configure which //! event causes this shadow load to take place, use CMPSS_configDAC(). //! //! \return None. // //***************************************************************************** static inline void CMPSS_setDACValueLow(uint32_t base, uint16_t value) { // // Check the arguments. // ; ; // // Write the DAC value to the DAC value shadow register. // (*((volatile uint16_t *)(base + 0x12U))) = value; } //***************************************************************************** // //! Initializes the digital filter of the high comparator. //! //! \param base is the base address of the comparator module. //! //! This function initializes all the samples in the high comparator digital //! filter to the filter input value. //! //! \note See CMPSS_configFilterHigh() for the proper initialization sequence //! to avoid glitches. //! //! \return None. // //***************************************************************************** static inline void CMPSS_initFilterHigh(uint32_t base) { // // Check the arguments. // ; // // Set the high comparator filter initialization bit. // __eallow(); (*((volatile uint16_t *)(base + 0x18U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Initializes the digital filter of the low comparator. //! //! \param base is the base address of the comparator module. //! //! This function initializes all the samples in the low comparator digital //! filter to the filter input value. //! //! \note See CMPSS_configFilterLow() for the proper initialization sequence //! to avoid glitches. //! //! \return None. // //***************************************************************************** static inline void CMPSS_initFilterLow(uint32_t base) { // // Check the arguments. // ; // // Set the low comparator filter initialization bit. // __eallow(); (*((volatile uint16_t *)(base + 0x16U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Gets the value of the internal DAC of the high comparator. //! //! \param base is the base address of the comparator module. //! //! This function gets the value of the internal DAC of the high comparator. //! The value is read from the \e active register--not the shadow register to //! which CMPSS_setDACValueHigh() writes. //! //! \return Returns the value driven by the internal DAC of the high comparator. // //***************************************************************************** static inline uint16_t CMPSS_getDACValueHigh(uint32_t base) { // // Check the arguments. // ; // // Write the DAC value to the DAC value shadow register. // return((*((volatile uint16_t *)(base + 0x7U)))); } //***************************************************************************** // //! Gets the value of the internal DAC of the low comparator. //! //! \param base is the base address of the comparator module. //! //! This function gets the value of the internal DAC of the low comparator. //! The value is read from the \e active register--not the shadow register to //! which CMPSS_setDACValueLow() writes. //! //! \return Returns the value driven by the internal DAC of the low comparator. // //***************************************************************************** static inline uint16_t CMPSS_getDACValueLow(uint32_t base) { // // Check the arguments. // ; // // Write the DAC value to the DAC value shadow register. // return((*((volatile uint16_t *)(base + 0x13U)))); } //***************************************************************************** // //! Causes a software reset of the high comparator digital filter output latch. //! //! \param base is the base address of the comparator module. //! //! This function causes a software reset of the high comparator digital filter //! output latch. It will generate a single pulse of the latch reset signal. //! //! \return None. // //***************************************************************************** static inline void CMPSS_clearFilterLatchHigh(uint32_t base) { // // Check the arguments. // ; // // Set the bit that generates a reset pulse to the digital filter latch. // __eallow(); (*((volatile uint16_t *)(base + 0x3U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Causes a software reset of the low comparator digital filter output latch. //! //! \param base is the base address of the comparator module. //! //! This function causes a software reset of the low comparator digital filter //! output latch. It will generate a single pulse of the latch reset signal. //! //! \return None. // //***************************************************************************** static inline void CMPSS_clearFilterLatchLow(uint32_t base) { // // Check the arguments. // ; // // Set the bit that generates a reset pulse to the digital filter latch. // __eallow(); (*((volatile uint16_t *)(base + 0x3U))) |= 0x200U; __edis(); } //***************************************************************************** // //! Sets the ramp generator maximum reference value. //! //! \param base is the base address of the comparator module. //! \param value the ramp maximum reference value. //! //! This function sets the ramp maximum reference value that will be loaded //! into the ramp generator. //! //! \return None. // //***************************************************************************** static inline void CMPSS_setMaxRampValue(uint32_t base, uint16_t value) { // // Check the arguments. // ; // // Write the maximum ramp value to the shadow register. // (*((volatile uint16_t *)(base + 0xAU))) = value; } //***************************************************************************** // //! Gets the ramp generator maximum reference value. //! //! \param base is the base address of the comparator module. //! //! \return Returns the latched ramp maximum reference value that will be //! loaded into the ramp generator. // //***************************************************************************** static inline uint16_t CMPSS_getMaxRampValue(uint32_t base) { // // Check the arguments. // ; // // Read the maximum ramp value from the register. // return((*((volatile uint16_t *)(base + 0x8U)))); } //***************************************************************************** // //! Sets the ramp generator decrement value. //! //! \param base is the base address of the comparator module. //! \param value is the ramp decrement value. //! //! This function sets the value that is subtracted from the ramp value on //! every system clock cycle. //! //! \return None. // //***************************************************************************** static inline void CMPSS_setRampDecValue(uint32_t base, uint16_t value) { // // Check the arguments. // ; // // Write the ramp decrement value to the shadow register. // (*((volatile uint16_t *)(base + 0xEU))) = value; } //***************************************************************************** // //! Gets the ramp generator decrement value. //! //! \param base is the base address of the comparator module. //! //! \return Returns the latched ramp decrement value that is subtracted from //! the ramp value on every system clock cycle. // //***************************************************************************** static inline uint16_t CMPSS_getRampDecValue(uint32_t base) { // // Check the arguments. // ; // // Read the ramp decrement value from the register. // return((*((volatile uint16_t *)(base + 0xCU)))); } //***************************************************************************** // //! Sets the ramp generator delay value. //! //! \param base is the base address of the comparator module. //! \param value is the 13-bit ramp delay value. //! //! This function sets the value that configures the number of system clock //! cycles to delay the start of the ramp generator decrementer after a PWMSYNC //! event is received. Delay value can be no greater than 8191. //! //! \return None. // //***************************************************************************** static inline void CMPSS_setRampDelayValue(uint32_t base, uint16_t value) { // // Check the arguments. // ; ; // // Write the ramp delay value to the shadow register. // (*((volatile uint16_t *)(base + 0x15U))) = value; } //***************************************************************************** // //! Gets the ramp generator delay value. //! //! \param base is the base address of the comparator module. //! //! \return Returns the latched ramp delay value that is subtracted from //! the ramp value on every system clock cycle. // //***************************************************************************** static inline uint16_t CMPSS_getRampDelayValue(uint32_t base) { // // Check the arguments. // ; // // Read the ramp delay value from the register. // return((*((volatile uint16_t *)(base + 0x14U)))); } //***************************************************************************** // //! Sets the comparator hysteresis settings. //! //! \param base is the base address of the comparator module. //! \param value is the amount of hysteresis on the comparator inputs. //! //! This function sets the amount of hysteresis on the comparator inputs. The //! \e value parameter indicates the amount of hysteresis desired. Passing in 0 //! results in none, passing in 1 results in typical hysteresis, passing in 2 //! results in 2x of typical hysteresis, and so on where \e value x of typical //! hysteresis is the amount configured. //! //! \return None. // //***************************************************************************** static inline void CMPSS_setHysteresis(uint32_t base, uint16_t value) { // // Check the arguments. // ; ; // // Read the ramp delay value from the register. // __eallow(); (*((volatile uint16_t *)(base + 0x1U))) = value; __edis(); } //***************************************************************************** // //! Sets the ePWM module blanking signal that holds trip in reset. //! //! \param base is the base address of the comparator module. //! \param pwmBlankSrc is the number of the PWMBLANK source. //! //! This function configures which PWMBLANK signal from the ePWM module will //! hold trip in reset when blanking is enabled. //! //! The number of the PWMBLANK signal to be used to reset the ramp generator //! should be specified by passing it into the \e pwmBlankSrc parameter. For //! instance, passing a 2 into \e pwmBlankSrc will select PWMBLANK2. //! //! \return None. // //***************************************************************************** static inline void CMPSS_configBlanking(uint32_t base, uint16_t pwmBlankSrc) { // // Check the arguments. // ; ; // // Write the blank source number to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & ~0xF00U) | ((pwmBlankSrc - 1U) << 8U); __edis(); } //***************************************************************************** // //! Enables an ePWM blanking signal to hold trip in reset. //! //! \param base is the base address of the comparator module. //! //! This function enables a selected ePWM blanking signal to hold trip in //! reset. //! //! \return None. // //***************************************************************************** static inline void CMPSS_enableBlanking(uint32_t base) { // // Check the arguments. // ; // // Set the bit that enables the PWMBLANK signal. // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x1000U; __edis(); } //***************************************************************************** // //! Disables an ePWM blanking signal from holding trip in reset. //! //! \param base is the base address of the comparator module. //! //! This function disables a selected ePWM blanking signal from holding trip in //! reset. //! //! \return None. // //***************************************************************************** static inline void CMPSS_disableBlanking(uint32_t base) { // // Check the arguments. // ; // // Clear the bit that enables the PWMBLANK signal. // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x1000U; __edis(); } //***************************************************************************** // //! Configures the digital filter of the high comparator. //! //! \param base is the base address of the comparator module. //! \param samplePrescale is the number of system clock cycles between samples. //! \param sampleWindow is the number of FIFO samples to monitor. //! \param threshold is the majority threshold of samples to change state. //! //! This function configures the operation of the digital filter of the high //! comparator. //! //! The \e samplePrescale parameter specifies the number of system clock cycles //! between samples. It is a 10-bit value so a number higher than 1023 should //! not be passed as this parameter. //! //! The \e sampleWindow parameter configures the size of the window of FIFO //! samples taken from the input that will be monitored to determine when to //! change the filter output. This sample window may be no larger than 32 //! samples. //! //! The filter output resolves to the majority value of the sample window where //! majority is defined by the value passed into the \e threshold parameter. //! For proper operation, the value of \e threshold must be greater than //! sampleWindow / 2. //! //! To ensure proper operation of the filter, the following is the recommended //! function call sequence for initialization: //! //! -# Configure and enable the comparator using CMPSS_configHighComparator() //! and CMPSS_enableModule() //! -# Configure the digital filter using CMPSS_configFilterHigh() //! -# Initialize the sample values using CMPSS_initFilterHigh() //! -# Configure the module output signals CTRIP and CTRIPOUT using //! CMPSS_configOutputsHigh() //! //! \return None. // //***************************************************************************** extern void CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, uint16_t sampleWindow, uint16_t threshold); //***************************************************************************** // //! Configures the digital filter of the low comparator. //! //! \param base is the base address of the comparator module. //! \param samplePrescale is the number of system clock cycles between samples. //! \param sampleWindow is the number of FIFO samples to monitor. //! \param threshold is the majority threshold of samples to change state. //! //! This function configures the operation of the digital filter of the low //! comparator. //! //! The \e samplePrescale parameter specifies the number of system clock cycles //! between samples. It is a 10-bit value so a number higher than 1023 should //! not be passed as this parameter. //! //! The \e sampleWindow parameter configures the size of the window of FIFO //! samples taken from the input that will be monitored to determine when to //! change the filter output. This sample window may be no larger than 32 //! samples. //! //! The filter output resolves to the majority value of the sample window where //! majority is defined by the value passed into the \e threshold parameter. //! For proper operation, the value of \e threshold must be greater than //! sampleWindow / 2. //! //! To ensure proper operation of the filter, the following is the recommended //! function call sequence for initialization: //! //! -# Configure and enable the comparator using CMPSS_configLowComparator() //! and CMPSS_enableModule() //! -# Configure the digital filter using CMPSS_configFilterLow() //! -# Initialize the sample values using CMPSS_initFilterLow() //! -# Configure the module output signals CTRIP and CTRIPOUT using //! CMPSS_configOutputsLow() //! //! \return None. // //***************************************************************************** extern void CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, uint16_t sampleWindow, uint16_t threshold); //***************************************************************************** // //! Configures whether or not the digital filter latches are reset by PWMSYNC //! //! \param base is the base address of the comparator module. //! \param highEnable indicates filter latch settings in the high comparator. //! \param lowEnable indicates filter latch settings in the low comparator. //! //! This function configures whether or not the digital filter latches in both //! the high and low comparators should be reset by PWMSYNC. If the //! \e highEnable parameter is \b true, the PWMSYNC will be allowed to reset //! the high comparator's digital filter latch. If it is false, the ability of //! the PWMSYNC to reset the latch will be disabled. The \e lowEnable parameter //! has the same effect on the low comparator's digital filter latch. //! //! \return None. // //***************************************************************************** extern void CMPSS_configLatchOnPWMSYNC(uint32_t base, _Bool highEnable, _Bool lowEnable); //***************************************************************************** // //! Configures the comparator subsystem's ramp generator. //! //! \param base is the base address of the comparator module. //! \param maxRampVal is the ramp maximum reference value. //! \param decrementVal value is the ramp decrement value. //! \param delayVal is the ramp delay value. //! \param pwmSyncSrc is the number of the PWMSYNC source. //! \param useRampValShdw indicates if the max ramp shadow should be used. //! //! This function configures many of the main settings of the comparator //! subsystem's ramp generator. The \e maxRampVal parameter should be passed //! the ramp maximum reference value that will be loaded into the ramp //! generator. The \e decrementVal parameter should be passed the decrement //! value that will be subtracted from the ramp generator on each system clock //! cycle. The \e delayVal parameter should be passed the 13-bit number of //! system clock cycles the ramp generator should delay before beginning to //! decrement the ramp generator after a PWMSYNC signal is received. //! //! These three values may be be set individually using the //! CMPSS_setMaxRampValue(), CMPSS_setRampDecValue(), and //! CMPSS_setRampDelayValue() APIs. //! //! The number of the PWMSYNC signal to be used to reset the ramp generator //! should be specified by passing it into the \e pwmSyncSrc parameter. For //! instance, passing a 2 into \e pwmSyncSrc will select PWMSYNC2. //! //! To indicate whether the ramp generator should reset with the value from the //! ramp max reference value shadow register or with the latched ramp max //! reference value, use the \e useRampValShdw parameter. Passing it \b true //! will result in the latched value being bypassed. The ramp generator will be //! loaded right from the shadow register. A value of \b false will load the //! ramp generator from the latched value. //! //! \return None. // //***************************************************************************** extern void CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, uint16_t delayVal, uint16_t pwmSyncSrc, _Bool useRampValShdw); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //############################################################################# // // FILE: cputimer.h // // TITLE: C28x CPU timer Driver // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup cputimer_api CPUTimer //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_cputimer.h // // TITLE: Definitions for the CPUTIMER registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the CPUTIMER register offsets // //***************************************************************************** // High //***************************************************************************** // // The following are defines for the bit fields in the TIM register // //***************************************************************************** // High //***************************************************************************** // // The following are defines for the bit fields in the PRD register // //***************************************************************************** // High //***************************************************************************** // // The following are defines for the bit fields in the TCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TPR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TPRH register // //***************************************************************************** //***************************************************************************** // // Defines for the API. // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to CPUTimer_setEmulationMode() as the //! \e mode parameter. // //**************************************************************************** typedef enum { //! Denotes that the timer will stop after the next decrement CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000, //! Denotes that the timer will stop when it reaches zero CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400, //! Denotes that the timer will run free CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800 }CPUTimer_EmulationMode; //***************************************************************************** // //! The following are values that can be passed to //! CPUTimer_selectClockSource() as the \e source parameter. // //***************************************************************************** typedef enum { //! System Clock Source CPUTIMER_CLOCK_SOURCE_SYS = 0x0, //! Internal Oscillator 1 Clock Source CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1, //! Internal Oscillator 2 Clock Source CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2, //! External Clock Source CPUTIMER_CLOCK_SOURCE_XTAL = 0x3, //! Auxiliary PLL Clock Source CPUTIMER_CLOCK_SOURCE_AUX = 0x6 } CPUTimer_ClockSource; //***************************************************************************** // //! The following are values that can be passed to //! CPUTimer_selectClockSource() as the \e prescaler parameter. // //***************************************************************************** typedef enum { CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1 CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2 CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4 CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8 CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16 } CPUTimer_Prescaler; //***************************************************************************** // //! \internal //! Checks CPU timer base address. //! //! \param base specifies the Timer module base address. //! //! This function determines if a CPU timer module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Clears CPU timer overflow flag. //! //! \param base is the base address of the timer module. //! //! This function clears the CPU timer overflow flag. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_clearOverflowFlag(uint32_t base) { ; // // Set TIF bit of TCR register // (*((volatile uint16_t *)(base + 0x4U))) |= 0x8000U; } //***************************************************************************** // //! Disables CPU timer interrupt. //! //! \param base is the base address of the timer module. //! //! This function disables the CPU timer interrupt. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_disableInterrupt(uint32_t base) { ; // // Clear TIE bit of TCR register // (*((volatile uint16_t *)(base + 0x4U))) &= ~0x4000U; } //***************************************************************************** // //! Enables CPU timer interrupt. //! //! \param base is the base address of the timer module. //! //! This function enables the CPU timer interrupt. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_enableInterrupt(uint32_t base) { ; // // Set TIE bit of TCR register // (*((volatile uint16_t *)(base + 0x4U))) |= 0x4000U; } //***************************************************************************** // //! Reloads CPU timer counter. //! //! \param base is the base address of the timer module. //! //! This function reloads the CPU timer counter with the values contained in //! the CPU timer period register. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_reloadTimerCounter(uint32_t base) { ; // // Set TRB bit of register TCR // (*((volatile uint16_t *)(base + 0x4U))) |= 0x20U; } //***************************************************************************** // //! Stops CPU timer. //! //! \param base is the base address of the timer module. //! //! This function stops the CPU timer. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_stopTimer(uint32_t base) { ; // // Set TSS bit of register TCR // (*((volatile uint16_t *)(base + 0x4U))) |= 0x10U; } //***************************************************************************** // //! Starts(restarts) CPU timer. //! //! \param base is the base address of the timer module. //! //! This function starts (restarts) the CPU timer. //! //! \b Note: This function doesn't reset the timer counter. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_resumeTimer(uint32_t base) { ; // // Clear TSS bit of register TCR // (*((volatile uint16_t *)(base + 0x4U))) &= ~0x10U; } //***************************************************************************** // //! Starts(restarts) CPU timer. //! //! \param base is the base address of the timer module. //! //! This function starts (restarts) the CPU timer. //! //! \b Note: This function reloads the timer counter. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_startTimer(uint32_t base) { ; // // Reload the timer counter // (*((volatile uint16_t *)(base + 0x4U))) |= 0x20U; // // Clear TSS bit of register TCR // (*((volatile uint16_t *)(base + 0x4U))) &= ~0x10U; } //***************************************************************************** // //! Sets CPU timer period. //! //! \param base is the base address of the timer module. //! \param periodCount is the CPU timer period count. //! //! This function sets the CPU timer period count. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount) { ; // // Load the MSB period Count // (*((volatile uint32_t *)(base + 0x2U))) = periodCount; } //***************************************************************************** // //! Returns the current CPU timer counter value. //! //! \param base is the base address of the timer module. //! //! This function returns the current CPU timer counter value. //! //! \return Returns the current CPU timer count value. // //***************************************************************************** static inline uint32_t CPUTimer_getTimerCount(uint32_t base) { ; // // Get the TIMH:TIM registers value // return((*((volatile uint32_t *)(base + 0x0U)))); } //***************************************************************************** // //! Set CPU timer pre-scaler value. //! //! \param base is the base address of the timer module. //! \param prescaler is the CPU timer pre-scaler value. //! //! This function sets the pre-scaler value for the CPU timer. For every value //! of (prescaler + 1), the CPU timer counter decrements by 1. //! //! \return None. // //***************************************************************************** static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler) { ; // // Writes to TPR.TDDR and TPRH.TDDRH bits // (*((volatile uint16_t *)(base + 0x7U))) = prescaler >> 8U; (*((volatile uint16_t *)(base + 0x6U))) = (prescaler & 0xFFU) ; } //***************************************************************************** // //! Return the CPU timer overflow status. //! //! \param base is the base address of the timer module. //! //! This function returns the CPU timer overflow status. //! //! \return Returns true if the CPU timer has overflowed, false if not. // //***************************************************************************** static inline _Bool CPUTimer_getTimerOverflowStatus(uint32_t base) { ; // // Check if TIF bits of register TCR are set // return((((*((volatile uint16_t *)(base + 0x4U))) & 0x8000U) == 0x8000U) ? 1 : 0); } //***************************************************************************** // //! Select CPU Timer 2 Clock Source and Prescaler //! //! \param base is the base address of the timer module. //! \param source is the clock source to use for CPU Timer 2 //! \param prescaler is the value that configures the selected clock source //! relative to the system clock //! //! This function selects the specified clock source and prescaler value //! for the CPU timer (CPU timer 2 only). //! //! The \e source parameter can be any one of the following: //! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock //! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock //! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock //! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock //! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock //! //! The \e prescaler parameter can be any one of the following: //! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1 //! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2 //! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4 //! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8 //! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16 //! //! \return None. // //***************************************************************************** static inline void CPUTimer_selectClockSource(uint32_t base, CPUTimer_ClockSource source, CPUTimer_Prescaler prescaler) { ; // // Set source and prescaler for CPU Timer 2 // if(base == 0x00000C10U) { __eallow(); // // Set Clock Source // (*((volatile uint16_t *)(0x0005D300U + 0x7CU))) &= ~0x7U; (*((volatile uint16_t *)(0x0005D300U + 0x7CU))) |= (uint16_t)source; // // Set Clock Prescaler // (*((volatile uint16_t *)(0x0005D300U + 0x7CU))) &= ~0x38U; (*((volatile uint16_t *)(0x0005D300U + 0x7CU))) |= ((uint16_t)prescaler << 3U); __edis(); } } //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Sets Emulation mode for CPU timer. //! //! \param base is the base address of the timer module. //! \param mode is the emulation mode of the timer. //! //! This function sets the behaviour of CPU timer during emulation. Valid //! values mode are: CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT, //! CPUTIMER_EMULATIONMODE_STOPATZERO and CPUTIMER_EMULATIONMODE_RUNFREE. //! //! \return None. // //***************************************************************************** extern void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: dac.h // // TITLE: C28x DAC driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup dac_api DAC //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_dac.h // // TITLE: Definitions for the DAC registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the DAC register offsets // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACREV register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACVALA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACVALS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACOUTEN register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DACLOCK register // //***************************************************************************** // Lock //***************************************************************************** // // The following are defines for the bit fields in the DACTRIM register // //***************************************************************************** // // A 8-bit register mask // // // Lock Key // //***************************************************************************** // // The following are defines for the reg parameter of the // DAC_lockRegister() and DAC_isRegisterLocked() functions. // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to DAC_setReferenceVoltage() as the \e source //! parameter. // //***************************************************************************** typedef enum { DAC_REF_VDAC = 0, //!< VDAC reference voltage DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage }DAC_ReferenceVoltage; //***************************************************************************** // //! Values that can be passed to DAC_setGainMode() as the \e mode parameter. // //***************************************************************************** typedef enum { DAC_GAIN_ONE = 0, //!< Gain set to 1 DAC_GAIN_TWO = 2 //!< Gain set to 2 }DAC_GainMode; //***************************************************************************** // //! Values that can be passed to DAC_setLoadMode() as the \e mode parameter. // //***************************************************************************** typedef enum { DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL }DAC_LoadMode; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks DAC base address. //! //! \param base specifies the DAC module base address. //! //! This function determines if an DAC module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Get the DAC Revision value //! //! \param base is the DAC module base address //! //! This function gets the DAC revision value. //! //! \return Returns the DAC revision value. // //***************************************************************************** static inline uint16_t DAC_getRevision(uint32_t base) { // // Check the arguments. // ; // // Get the revision value. // return((*((volatile uint16_t *)(base + 0x0U))) & 0xFFU); } //***************************************************************************** // //! Sets the DAC Reference Voltage //! //! \param base is the DAC module base address //! \param source is the selected reference voltage //! //! This function sets the DAC reference voltage. //! //! The \e source parameter can have one of two values: //! - \b DAC_REF_VDAC - The VDAC reference voltage //! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage //! //! \return None. // //***************************************************************************** static inline void DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source) { // // Check the arguments. // ; // // Set the reference voltage // __eallow(); (*((volatile uint16_t *)(base + 0x1U))) = ((*((volatile uint16_t *)(base + 0x1U))) & ~0x1U) | (uint16_t)source; __edis(); } //***************************************************************************** // //! Sets the DAC Gain Mode //! //! \param base is the DAC module base address //! \param mode is the selected gain mode //! //! This function sets the DAC gain mode for the buffered output. //! //! The \e mode parameter can have one of two values: //! - \b DAC_GAIN_ONE - Gain is set to 1 //! - \b DAC_GAIN_TWO - Gain is set to 2 //! //! \note This value is only used when \e DAC_REF_ADC_VREFHI is set using //! DAC_setReferenceVoltage() and internal ADC reference mode is selected. //! //! \return None. // //***************************************************************************** static inline void DAC_setGainMode(uint32_t base, DAC_GainMode mode) { // // Check the arguments. // ; // // Set the gain mode // __eallow(); (*((volatile uint16_t *)(base + 0x1U))) = ((*((volatile uint16_t *)(base + 0x1U))) & ~0x2U) | (uint16_t)mode; __edis(); } //***************************************************************************** // //! Sets the DAC Load Mode //! //! \param base is the DAC module base address //! \param mode is the selected load mode //! //! This function sets the DAC load mode. //! //! The \e mode parameter can have one of two values: //! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK //! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL //! //! \return None. // //***************************************************************************** static inline void DAC_setLoadMode(uint32_t base, DAC_LoadMode mode) { // // Check the arguments. // ; // // Set the load mode // __eallow(); (*((volatile uint16_t *)(base + 0x1U))) = ((*((volatile uint16_t *)(base + 0x1U))) & ~0x4U) | (uint16_t)mode; __edis(); } //***************************************************************************** // //! Sets the DAC PWMSYNC Signal //! //! \param base is the DAC module base address //! \param signal is the selected PWM signal //! //! This function sets the DAC PWMSYNC signal. //! //! The \e signal parameter must be set to a number that represents the PWM //! signal that will be set. For instance, passing 2 into \e signal will //! select PWM sync signal 2. //! //! \return None. // //***************************************************************************** static inline void DAC_setPWMSyncSignal(uint32_t base, uint16_t signal) { // // Check the arguments. // ; ; // // Set the PWM sync signal // __eallow(); (*((volatile uint16_t *)(base + 0x1U))) = ((*((volatile uint16_t *)(base + 0x1U))) & ~0xF0U) | ((uint16_t)(signal - 1U) << 4U); __edis(); } //***************************************************************************** // //! Get the DAC Active Output Value //! //! \param base is the DAC module base address //! //! This function gets the DAC active output value. //! //! \return Returns the DAC active output value. // //***************************************************************************** static inline uint16_t DAC_getActiveValue(uint32_t base) { // // Check the arguments. // ; // // Get the active value // return((*((volatile uint16_t *)(base + 0x2U))) & 0xFFFU); } //***************************************************************************** // //! Set the DAC Shadow Output Value //! //! \param base is the DAC module base address //! \param value is the 12-bit code to be loaded into the active value register //! //! This function sets the DAC shadow output value. //! //! \return None. // //***************************************************************************** static inline void DAC_setShadowValue(uint32_t base, uint16_t value) { // // Check the arguments. // ; ; // // Set the shadow value // (*((volatile uint16_t *)(base + 0x3U))) = ((*((volatile uint16_t *)(base + 0x3U))) & ~0xFFFU) | (uint16_t)(value & 0xFFFU); } //***************************************************************************** // //! Get the DAC Shadow Output Value //! //! \param base is the DAC module base address //! //! This function gets the DAC shadow output value. //! //! \return Returns the DAC shadow output value. // //***************************************************************************** static inline uint16_t DAC_getShadowValue(uint32_t base) { // // Check the arguments. // ; // // Get the shadow value // return((*((volatile uint16_t *)(base + 0x3U))) & 0xFFFU); } //***************************************************************************** // //! Enable the DAC Output //! //! \param base is the DAC module base address //! //! This function enables the DAC output. //! //! \note A delay is required after enabling the DAC. Further details //! regarding the exact delay time length can be found in the device datasheet. //! //! \return None. // //***************************************************************************** static inline void DAC_enableOutput(uint32_t base) { // // Check the arguments. // ; // // Enable the output // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disable the DAC Output //! //! \param base is the DAC module base address //! //! This function disables the DAC output. //! //! \return None. // //***************************************************************************** static inline void DAC_disableOutput(uint32_t base) { // // Check the arguments. // ; // // Disable the output // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Set DAC Offset Trim //! //! \param base is the DAC module base address //! \param offset is the specified value for the offset trim //! //! This function sets the DAC offset trim. The \e offset value should be a //! signed number in the range of -128 to 127. //! //! \note The offset should not be modified unless specifically indicated by //! TI Errata or other documentation. Modifying the offset value could cause //! this module to operate outside of the datasheet specifications. //! //! \return None. // //***************************************************************************** static inline void DAC_setOffsetTrim(uint32_t base, int16_t offset) { // // Check the arguments. // ; ; // // Set the offset trim value // __eallow(); (*((volatile uint16_t *)(base + 0x6U))) = ((*((volatile uint16_t *)(base + 0x6U))) & ~0xFFU) | (int16_t)offset; __edis(); } //***************************************************************************** // //! Get DAC Offset Trim //! //! \param base is the DAC module base address //! //! This function gets the DAC offset trim value. //! //! \return None. // //***************************************************************************** static inline int16_t DAC_getOffsetTrim(uint32_t base) { uint16_t value; // // Check the arguments. // ; // // Get the sign-extended offset trim value // value = ((*((volatile uint16_t *)(base + 0x6U))) & 0xFFU); value = ((value & (uint16_t)(0xFFU)) ^ (uint16_t)0x80) - (uint16_t)0x80; return ((int16_t)value); } //***************************************************************************** // //! Lock write-access to DAC Register //! //! \param base is the DAC module base address //! \param reg is the selected DAC registers //! //! This function locks the write-access to the specified DAC register. Only a //! system reset can unlock the register once locked. //! //! The \e reg parameter can be an ORed combination of any of the following //! values: //! - \b DAC_LOCK_CONTROL - Lock the DAC control register //! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register //! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register //! //! \return None. // //***************************************************************************** static inline void DAC_lockRegister(uint32_t base, uint16_t reg) { // // Check the arguments. // ; ; // // Lock the specified registers // __eallow(); (*((volatile uint16_t *)(base + 0x5U))) |= ((0xA000U) | reg); __edis(); } //***************************************************************************** // //! Check if DAC Register is locked //! //! \param base is the DAC module base address //! \param reg is the selected DAC register locks to check //! //! This function checks if write-access has been locked on the specified DAC //! register. //! //! The \e reg parameter can be an ORed combination of any of the following //! values: //! - \b DAC_LOCK_CONTROL - Lock the DAC control register //! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register //! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register //! //! \return Returns \b true if any of the registers specified are locked, and //! \b false if all specified registers aren't locked. // //***************************************************************************** static inline _Bool DAC_isRegisterLocked(uint32_t base, uint16_t reg) { // // Check the arguments. // ; ; // // Return the lock status on the specified registers // return((_Bool)(((*((volatile uint16_t *)(base + 0x5U))) & reg) != 0U)); } //***************************************************************************** // //! Tune DAC Offset Trim //! //! \param base is the DAC module base address //! \param referenceVoltage is the reference voltage the DAC //! module is operating at. //! //! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage //! value should be a floating point number in the range specified in the //! device data manual. //! //! \note Use this function to adjust the DAC offset trim if operating //! at a reference voltage other than 2.5v. Since this function modifies //! the DAC offset trim register, it should only be called once after //! Device_cal. If it is called multiple times after Device_cal, the offset //! value scaled would be the wrong value. //! //! \return None. // //***************************************************************************** extern void DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: dcc.h // // TITLE: C28x DCC driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup dcc_api DCC //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_dcc.h // // TITLE: Definitions for the DCC registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the DCC register offsets // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCGCTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCREV register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCCNTSEED0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCVALIDSEED0 register // //***************************************************************************** // Counter 0 //***************************************************************************** // // The following are defines for the bit fields in the DCCCNTSEED1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCSTATUS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCCNT0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCVALID0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCCNT1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCCCLKSRC1 register // //***************************************************************************** // Counter 1 // Source Selection for COUNT1 //***************************************************************************** // // The following are defines for the bit fields in the DCCCLKSRC0 register // //***************************************************************************** // Counter 0 // // The reset value required to start or enable specific DCC operations // // // The reset value required to stop or disable specific DCC operations // // // A 16-bit register mask // // // A 8-bit register mask // // // A mask for the DCC counter seed registers // // // A mask for the DCC counter seed value // //***************************************************************************** // //! The following are defines for the mode parameter of the //! DCC_enableSingleShotMode() function. // //***************************************************************************** typedef enum { //! Use to stop counting when counter0 and valid0 both reach zero DCC_MODE_COUNTER_ZERO = 0xA00U, //! Use to stop counting when counter1 reaches zero DCC_MODE_COUNTER_ONE = 0xB00U } DCC_SingleShotMode; //***************************************************************************** // //! The following are defines for the identifier parameter of the //! DCC_getRevisionNumber() function. // //***************************************************************************** typedef enum { DCC_REVISION_MINOR = 0x0U, //!< The module minor revision number DCC_REVISION_CUSTOM = 0x1U, //!< The custom module revision number DCC_REVISION_MAJOR = 0x2U, //!< The module major revision number DCC_REVISION_DESIGN = 0x3U, //!< The module design release number DCC_REVISION_FUNCTIONAL = 0x4U, //!< The module functional release number DCC_REVISION_SCHEME = 0x5U //!< The scheme of the module } DCC_RevisionNumber; //***************************************************************************** // //! The following are defines for the source parameter of the //! DCC_setCounter1ClkSource() function. // //***************************************************************************** typedef enum { DCC_COUNT1SRC_PLL = 0x0U, //!< PLL021SSP Clock Out Source DCC_COUNT1SRC_INTOSC1 = 0x2U, //!< Internal Oscillator 1 Clock Source DCC_COUNT1SRC_INTOSC2 = 0x3U, //!< Internal Oscillator 2 Clock Source DCC_COUNT1SRC_PUMOSC = 0x4U, //!< PUMOSC Clock Source DCC_COUNT1SRC_DCDC = 0x5U, //!< DCDC Clock Source DCC_COUNT1SRC_SYSCLK = 0x6U, //!< System Clock Source DCC_COUNT1SRC_FOSCLK = 0x7U, //!< FOS Clock Source DCC_COUNT1SRC_ODPOSC = 0x8U, //!< ODP Oscillator Clock Source DCC_COUNT1SRC_CROSSBAR = 0x9U, //!< Input Crossbar Clock Source DCC_COUNT1SRC_AUXCLK = 0xAU, //!< AUX Clock Source DCC_COUNT1SRC_ETPWM = 0xBU, //!< ETPWM Clock Source DCC_COUNT1SRC_LSPCLK = 0xCU, //!< LSP Clock Source DCC_COUNT1SRC_ADCCLK = 0xDU, //!< ADC Clock Source DCC_COUNT1SRC_WDCLK = 0xEU, //!< Watch Dog Clock Source DCC_COUNT1SRC_CANX = 0xFU //!< CANxBIT Clock Source } DCC_Count1ClockSource; //***************************************************************************** // //! The following are defines for the source parameter of the //! DCC_setCounter0ClkSource() function. // //***************************************************************************** typedef enum { DCC_COUNT0SRC_XTAL = 0x0U, //!< Accurate Clock Source DCC_COUNT0SRC_INTOSC1 = 0x1U, //!< Internal Oscillator 1 Clock Source DCC_COUNT0SRC_INTOSC2 = 0x2U, //!< Internal Oscillator 2 Clock Source DCC_COUNT0SRC_TCK = 0x4U, //!< Preliminary Clock Source DCC_COUNT0SRC_AUXCLK = 0x8U, //!< AUX Clock Source DCC_COUNT0SRC_XBAR = 0xDU //!< Input XBAR Clock Source } DCC_Count0ClockSource; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks DCC base address. //! //! \param base specifies the DCC module base address. //! //! This function determines if an DCC module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enables the DCC module. //! //! \param base is the DCC module base address //! //! This function starts the DCC counter operation. //! //! \return None. // //***************************************************************************** static inline void DCC_enableModule(uint32_t base) { // // Check the arguments. // ; // // Set DCC enable bit field. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xFU)) | (0xAU); __edis(); } //***************************************************************************** // //! Disable the DCC module. //! //! \param base is the DCC module base address //! //! This function stops the DCC counter operation. //! //! \return None. // //***************************************************************************** static inline void DCC_disableModule(uint32_t base) { // // Check the arguments. // ; // // Reset DCC enable bit field. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xFU)) | (0x5U); __edis(); } //***************************************************************************** // //! Enable DCC Error Signal //! //! \param base is the DCC module base address //! //! This function enables the error signal interrupt. //! //! \return None. // //***************************************************************************** static inline void DCC_enableErrorSignal(uint32_t base) { // // Check the arguments. // ; // // Enable the error signal // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF0U)) | ((0xAU) << 4U); __edis(); } //***************************************************************************** // //! Enable DCC Done Signal //! //! \param base is the DCC module base address //! //! This function enables the done signal interrupt. //! //! \return None. // //***************************************************************************** static inline void DCC_enableDoneSignal(uint32_t base) { // // Check the arguments. // ; // // Enable the done interrupt signal // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF000U)) | ((0xAU) << 12U); __edis(); } //***************************************************************************** // //! Disable DCC Error Signal //! //! \param base is the DCC module base address //! //! This function disables the error signal interrupt. //! //! \return None. // //***************************************************************************** static inline void DCC_disableErrorSignal(uint32_t base) { // // Check the arguments. // ; // // Disable the error signal // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF0U)) | ((0x5U) << 4U); __edis(); } //***************************************************************************** // //! Disable DCC Done Signal //! //! \param base is the DCC module base address //! //! This function disables the done signal interrupt. //! //! \return None. // //***************************************************************************** static inline void DCC_disableDoneSignal(uint32_t base) { // // Check the arguments. // ; // // Disable the done interrupt signal // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF000U)) | ((0x5U) << 12U); __edis(); } //***************************************************************************** // //! Enable DCC Single-Shot Mode //! //! \param base is the DCC module base address //! \param mode is the selected Single-Shot operation mode //! //! This function enables the single-shot mode and sets the operation mode. //! //! The \e mode parameter can have one of two values: //! - \b DCC_MODE_COUNTER_ZERO - Stops counting when counter0 and valid0 both //! reach zero //! - \b DCC_MODE_COUNTER_ONE - Stops counting when counter1 reaches zero //! //! \return None. // //***************************************************************************** static inline void DCC_enableSingleShotMode(uint32_t base, DCC_SingleShotMode mode) { // // Check the arguments. // ; // // Set Single-Shot mode value to the appropriate register // if(mode == DCC_MODE_COUNTER_ZERO) { __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF00U)) | (uint16_t)DCC_MODE_COUNTER_ZERO; __edis(); } else { __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF00U)) | (uint16_t)DCC_MODE_COUNTER_ONE; __edis(); } } //***************************************************************************** // //! Disable DCC Single-Shot Mode //! //! \param base is the DCC module base address //! //! This function disables the DCC Single-Shot operation mode //! //! \return None. // //***************************************************************************** static inline void DCC_disableSingleShotMode(uint32_t base) { // // Check the arguments. // ; // // Reset Single-Shot enable bit field. // __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~(0xF00U)) | ((0x5U) << 8U); __edis(); } //***************************************************************************** // //! Get Error Flag Status //! //! \param base is the DCC module base address //! //! This function gets the error flag status. //! //! \return Returns \b true if an error has occurred, \b false if no errors //! have occurred. // //***************************************************************************** static inline _Bool DCC_getErrorStatus(uint32_t base) { // // Check the arguments. // ; // // Get the error flag // return((_Bool)(((*((volatile uint16_t *)(base + 0x14U))) & 0x1U) == 0x1U)); } //***************************************************************************** // //! Get Single-Shot Done Flag Status //! //! \param base is the DCC module base address //! //! This function gets the single-shot done flag status. //! //! \return Returns \b true if single-shot mode has completed, \b false if //! single-shot mode has not completed. // //***************************************************************************** static inline _Bool DCC_getSingleShotStatus(uint32_t base) { // // Check the arguments. // ; // // Read the done flag // return((_Bool)(((*((volatile uint16_t *)(base + 0x14U))) & 0x2U) == 0x2U)); } //***************************************************************************** // //! Clear Error Status Flag //! //! \param base is the DCC module base address //! //! This function clears the DCC error status flag. //! //! \return None. // //***************************************************************************** static inline void DCC_clearErrorFlag(uint32_t base) { // // Check the arguments. // ; // // Clear error status flag // __eallow(); (*((volatile uint16_t *)(base + 0x14U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Clear Single-Shot Done Status Flag //! //! \param base is the DCC module base address //! //! This function clears the DCC single-shot done status flag. //! //! \return None. // //***************************************************************************** static inline void DCC_clearDoneFlag(uint32_t base) { // // Check the arguments. // ; // // Clear done status flag // __eallow(); (*((volatile uint16_t *)(base + 0x14U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Get Current Value of Counter 0 //! //! \param base is the DCC module base address //! //! This function gets current value of counter 0. //! //! \note Reads of the counter value may not be exact since the read operation //! is synchronized to the vbus clock. //! //! \return Returns the current value of counter 0. // //***************************************************************************** static inline uint32_t DCC_getCounter0Value(uint32_t base) { uint32_t value; // // Check the arguments. // ; // // Get the current counter 0 value // value = (*((volatile uint16_t *)(base + 0x18U))) & (0xFFFFU); value |= ((uint32_t)((*((volatile uint16_t *)(base + 0x18U + 2U))) & (0xFFFFFU >> 16U)) << 16U); return(value); } //***************************************************************************** // //! Get Current Value of the Valid Duration Counter for Counter 0 //! //! \param base is the DCC module base address //! //! This function gets current value of the valid duration counter for //! counter 0. //! //! \note Reads of the counter value may not be exact since the read operation //! is synchronized to the vbus clock. //! //! \return Returns the current value of the valid duration counter. // //***************************************************************************** static inline uint16_t DCC_getValidCounter0Value(uint32_t base) { // // Check the arguments. // ; // // Get the current valid duration counter value // return((*((volatile uint16_t *)(base + 0x1CU)))); } //***************************************************************************** // //! Get Current Value of Counter 1 //! //! \param base is the DCC module base address //! //! This function gets current value of counter 1. //! //! \note Reads of the counter value may not be exact since the read operation //! is synchronized to the vbus clock. //! //! \return Returns the current value of counter 1. // //***************************************************************************** static inline uint32_t DCC_getCounter1Value(uint32_t base) { uint32_t value; // // Check the arguments. // ; // // Get the current counter 1 value // value = (*((volatile uint16_t *)(base + 0x20U))) & (0xFFFFU); value |= ((uint32_t)((*((volatile uint16_t *)(base + 0x20U + 2U))) & (0xFFFFFU >> 16U)) << 16U); return(value); } //***************************************************************************** // //! Set Counter 1 Clock Source //! //! \param base is the DCC module base address //! \param source is the selected clock source for counter 1 //! //! This function sets the counter 1 clock source. //! //! The \e source parameter can have one of fifteen values: //! - \b DCC_COUNT1SRC_PLL - PLL021SSP Clock Out Source //! - \b DCC_COUNT1SRC_INTOSC1 - Internal Oscillator 1 Clock Source //! - \b DCC_COUNT1SRC_INTOSC2 - Internal Oscillator 2 Clock Source //! - \b DCC_COUNT1SRC_PUMOSC - PUMOSC Clock Source //! - \b DCC_COUNT1SRC_DCDC - DCDC Clock Source //! - \b DCC_COUNT1SRC_SYSCLK - System Clock Source //! - \b DCC_COUNT1SRC_FOSCLK - FOS Clock Source //! - \b DCC_COUNT1SRC_ODPOSC - ODP Oscillator Clock Source //! - \b DCC_COUNT1SRC_CROSSBAR - Input Crossbar Clock Source //! - \b DCC_COUNT1SRC_AUXCLK - AUX Clock Source //! - \b DCC_COUNT1SRC_ETPWM - ETPWM Clock Source //! - \b DCC_COUNT1SRC_LSPCLK - LSP Clock Source //! - \b DCC_COUNT1SRC_ADCCLK - ADC Clock Source //! - \b DCC_COUNT1SRC_WDCLK - Watch Dog Clock Source //! - \b DCC_COUNT1SRC_CANX - CANxBIT Clock Source //! //! \return None. // //***************************************************************************** static inline void DCC_setCounter1ClkSource(uint32_t base, DCC_Count1ClockSource source) { // // Check the arguments. // ; // // Set the specified clock source // __eallow(); (*((volatile uint16_t *)(base + 0x24U))) = ((*((volatile uint16_t *)(base + 0x24U))) & ((0xFFU) << 4U)) | (((0xAU) << 12U) | (uint16_t)source); __edis(); } //***************************************************************************** // //! Set Counter 0 Clock Source //! //! \param base is the DCC module base address //! \param source is the selected clock source for counter 0 //! //! This function sets the counter 0 clock source. //! //! The \e source parameter can have one of six values: //! - \b DCC_COUNT0SRC_XTAL - Accurate Clock Source //! - \b DCC_COUNT0SRC_INTOSC1 - Internal Oscillator 1 Clock Source //! - \b DCC_COUNT0SRC_INTOSC2 - Internal Oscillator 2 Clock Source //! - \b DCC_COUNT0SRC_TCK - Preliminary Clock Source //! - \b DCC_COUNT0SRC_AUXCLK - AUX Clock Source //! - \b DCC_COUNT0SRC_XBAR - Input XBAR Clock Source //! //! \return None. // //***************************************************************************** static inline void DCC_setCounter0ClkSource(uint32_t base, DCC_Count0ClockSource source) { // // Check the arguments. // ; // // Set the specified clock source // __eallow(); (*((volatile uint16_t *)(base + 0x28U))) = ((*((volatile uint16_t *)(base + 0x28U))) & ~(0xFU)) | (uint16_t)source; __edis(); } //***************************************************************************** // //! Get Counter 1 Clock Source //! //! \param base is the DCC module base address //! //! This function gets the counter 1 clock source. //! //! \return Returns one of the following enumerated source values: //! - \b DCC_COUNT1SRC_PLL - PLL021SSP Clock Out Source //! - \b DCC_COUNT1SRC_INTOSC1 - Internal Oscillator 1 Clock Source //! - \b DCC_COUNT1SRC_INTOSC2 - Internal Oscillator 2 Clock Source //! - \b DCC_COUNT1SRC_PUMOSC - PUMOSC Clock Source //! - \b DCC_COUNT1SRC_DCDC - DCDC Clock Source //! - \b DCC_COUNT1SRC_SYSCLK - System Clock Source //! - \b DCC_COUNT1SRC_FOSCLK - FOS Clock Source //! - \b DCC_COUNT1SRC_ODPOSC - ODP Oscillator Clock Source //! - \b DCC_COUNT1SRC_CROSSBAR - Input Crossbar Clock Source //! - \b DCC_COUNT1SRC_AUXCLK - AUX Clock Source //! - \b DCC_COUNT1SRC_ETPWM - ETPWM Clock Source //! - \b DCC_COUNT1SRC_LSPCLK - LSP Clock Source //! - \b DCC_COUNT1SRC_ADCCLK - ADC Clock Source //! - \b DCC_COUNT1SRC_WDCLK - Watch Dog Clock Source //! - \b DCC_COUNT1SRC_CANX - CANxBIT Clock Source // //***************************************************************************** static inline uint16_t DCC_getCounter1ClkSource(uint32_t base) { // // Check the arguments. // ; // // Get the specified clock source // return((*((volatile uint16_t *)(base + 0x24U))) & 0xFU); } //***************************************************************************** // //! Get Counter 0 Clock Source //! //! \param base is the DCC module base address //! //! This function gets the counter 0 clock source. //! //! \return Returns one of the following enumerated source values: //! - \b DCC_COUNT0SRC_XTAL - Accurate Clock Source //! - \b DCC_COUNT0SRC_INTOSC1 - Internal Oscillator 1 Clock Source //! - \b DCC_COUNT0SRC_INTOSC2 - Internal Oscillator 2 Clock Source //! - \b DCC_COUNT0SRC_TCK - Preliminary Clock Source //! - \b DCC_COUNT0SRC_AUXCLK - AUX Clock Source //! - \b DCC_COUNT0SRC_XBAR - Input XBAR Clock Source // //***************************************************************************** static inline uint16_t DCC_getCounter0ClkSource(uint32_t base) { // // Check the arguments. // ; // // Get the specified clock source // return((*((volatile uint16_t *)(base + 0x28U))) & 0xFU); } //***************************************************************************** // //! Set the seed values //! //! \param base is the DCC module base address //! \param counter0 sets the seed value that gets loaded into Counter 0 //! \param validCounter0 sets the seed value that gets loaded into the valid //! duration counter for Counter 0 //! \param counter1 sets the seed value that gets loaded into Counter 1 //! //! This function sets the seed values for Counter 0, Valid Duration Counter 0, //! and Counter 1. //! //! \note //! -# Operating DCC with '0' set as the seed value for Counter 0, Valid //! Duration Counter 0, and/or Counter 1 will result in undefined operation. //! -# The Valid Duration Counter 0 is designed to be at least four cycles //! wide and shouldn't be programmed with a value less than '4'. //! //! \return None. // //***************************************************************************** static inline void DCC_setCounterSeeds(uint32_t base, uint32_t counter0, uint32_t validCounter0, uint32_t counter1) { // // Check the arguments. // ; ; ; ; __eallow(); // // Set Counter 0 Seed // (*((volatile uint16_t *)(base + 0x8U))) = counter0 & (0xFFFFU); (*((volatile uint16_t *)(base + 0x8U + 2U))) = ((*((volatile uint16_t *)(base + 0x8U + 2U))) & (0xFFF0U)) | ((uint32_t)(counter0 & (0xF0000U)) >> 16U); // // Set Valid Duration Counter 0 Seed // (*((volatile uint16_t *)(base + 0xCU))) = validCounter0; // // Set Counter 1 Seed // (*((volatile uint16_t *)(base + 0x10U))) = counter1 & (0xFFFFU); (*((volatile uint16_t *)(base + 0x10U + 2U))) = ((*((volatile uint16_t *)(base + 0x10U + 2U))) & (0xFFF0U)) | ((uint32_t)(counter1 & (0xF0000U)) >> 16U); __edis(); } //***************************************************************************** // //! Get DCC Version Number //! //! \param base is the DCC module base address //! \param identifier is the selected revision number identifier //! //! This function gets the specific version number. //! //! The \e identifier parameter can have one of six values: //! - \b DCC_REVISION_MINOR - The minor revision number //! - \b DCC_REVISION_CUSTOM - The custom module number //! - \b DCC_REVISION_MAJOR - The major revision number //! - \b DCC_REVISION_DESIGN - The design release number //! - \b DCC_REVISION_FUNCTIONAL - The functional release number //! - \b DCC_REVISION_SCHEME - The scheme of the module //! //! \return Specified revision number // //***************************************************************************** extern uint16_t DCC_getRevisionNumber(uint32_t base, DCC_RevisionNumber identifier); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //############################################################################# // // FILE: dcsm.h // // TITLE: C28x Driver for the DCSM security module. // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup dcsm_api DCSM //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_dcsm.h // // TITLE: Definitions for the DCSM registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the DCSM register offsets // //***************************************************************************** // OTP for flash BANK0 // OTP for flash BANK0 // OTP for flash BANK0 // Register-2 content // OTP // for flash BANK0 // OTP for flash BANK0 // OTP for flash BANK0 // OTP // BANK0 // BANK0 // Register-2 // Sectors Register // Register // Execute_Only Sector Register // Register // BANK0 // BANK0 // Sectors Register // Register // Execute_Only Sector Register // Register // Register // Register // Register // Register // OTP for flash BANK1 // OTP for flash BANK1 // OTP for flash BANK1 // OTP for flash BANK1 // OTP for flash BANK1 // OTP for flash BANK1 // BANK1 // BANK1 // Sectors Register // Execute_Only Sector Register // BANK1 // BANK1 // Sectors Register // Execute_Only Sector Register //***************************************************************************** // // The following are defines for the bit fields in the B0_Z1_LINKPOINTER register // //***************************************************************************** // Flash BANK0 //***************************************************************************** // // The following are defines for the bit fields in the Z1_OTPSECLOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z1_LINKPOINTERERR register // //***************************************************************************** // pointer from OTP loaded values //***************************************************************************** // // The following are defines for the bit fields in the Z1_CR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z1_GRABSECTR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the Z1_GRABRAMR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z1_EXEONLYSECTR register // //***************************************************************************** // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 //***************************************************************************** // // The following are defines for the bit fields in the Z1_EXEONLYRAMR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z2_LINKPOINTER register // //***************************************************************************** // BANK0 //***************************************************************************** // // The following are defines for the bit fields in the Z2_OTPSECLOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z2_LINKPOINTERERR register // //***************************************************************************** // pointer from OTP loaded values //***************************************************************************** // // The following are defines for the bit fields in the Z2_CR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z2_GRABSECTR register // //***************************************************************************** // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 // BANK0 //***************************************************************************** // // The following are defines for the bit fields in the Z2_GRABRAMR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_Z2_EXEONLYSECTR register // //***************************************************************************** // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 // in Flash BANK0 //***************************************************************************** // // The following are defines for the bit fields in the Z2_EXEONLYRAMR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FLSEM register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B0_SECTSTAT register // //***************************************************************************** // Sector 0 // sector 1 // Sector 2 // Sector 3 // Sector 4 // Sector 5 // Sector 6 // Sector 7 // sector 8 // Sector 9 // Sector 10 // Sector 11 // Sector 12 // Sector 13 // Sector 14 // Sector 15 //***************************************************************************** // // The following are defines for the bit fields in the RAMSTAT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B1_SECTSTAT register // //***************************************************************************** // Sector 0 // sector 1 // Sector 2 // Sector 3 // Sector 4 // Sector 5 // Sector 6 // Sector 7 // sector 8 // Sector 9 // Sector 10 // Sector 11 // Sector 12 // Sector 13 // Sector 14 // Sector 15 //***************************************************************************** // // The following are defines for the bit fields in the SECERRSTAT register // //***************************************************************************** // Error Status //***************************************************************************** // // The following are defines for the bit fields in the SECERRCLR register // //***************************************************************************** // Load Error Status Bit //***************************************************************************** // // The following are defines for the bit fields in the SECERRFRC register // //***************************************************************************** // Load Error Status Bit //***************************************************************************** // // The following are defines for the bit fields in the B1_Z1_LINKPOINTER register // //***************************************************************************** // BANK1 //***************************************************************************** // // The following are defines for the bit fields in the B1_Z1_LINKPOINTERERR register // //***************************************************************************** // pointer from OTP loaded values //***************************************************************************** // // The following are defines for the bit fields in the B1_Z1_GRABSECTR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the B1_Z1_EXEONLYSECTR register // //***************************************************************************** // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 //***************************************************************************** // // The following are defines for the bit fields in the B1_Z2_LINKPOINTER register // //***************************************************************************** // BANK1 //***************************************************************************** // // The following are defines for the bit fields in the B1_Z2_LINKPOINTERERR register // //***************************************************************************** // pointer from OTP loaded values //***************************************************************************** // // The following are defines for the bit fields in the B1_Z2_GRABSECTR register // //***************************************************************************** // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 // BANK1 //***************************************************************************** // // The following are defines for the bit fields in the B1_Z2_EXEONLYSECTR register // //***************************************************************************** // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 // in Flash BANK1 //***************************************************************************** // // Defines for the unlockZone1CSM() and unlockZone2CSM(). // These are not parameters for any function. // These are not intended for application code. // //***************************************************************************** //***************************************************************************** // // Register key defines. // //***************************************************************************** //***************************************************************************** // //! Data structures to hold password keys. // //***************************************************************************** typedef struct { uint32_t csmKey0; uint32_t csmKey1; uint32_t csmKey2; uint32_t csmKey3; } DCSM_CSMPasswordKey; //***************************************************************************** // //! Values to distinguish which bank. //! These values can be passed to DCSM_getZone1FlashEXEStatus(), //! DCSM_getZone2FlashEXEStatus(), DCSM_getFlashSectorZone(), //! DCSM_getZone1LinkPointerError(), DCSM_getZone2LinkPointerError(). // //***************************************************************************** typedef enum { DCSM_BANK0, //!< Bank 0 DCSM_BANK1 //!< Bank 1 } DCSM_Bank; //***************************************************************************** // //! Values to distinguish the status of RAM or FLASH sectors. These values //! describe which zone the memory location belongs too. //! These values can be returned from DCSM_getRAMZone(), //! DCSM_getFlashSectorZone(). // //***************************************************************************** typedef enum { DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible DCSM_MEMORY_ZONE1, //!< Zone 1 DCSM_MEMORY_ZONE2, //!< Zone 2 DCSM_MEMORY_FULL_ACCESS //!< Full access } DCSM_MemoryStatus; //***************************************************************************** // //! Values to pass to DCSM_claimZoneSemaphore(). These values are used //! to describe the zone that can write to Flash Wrapper registers. // //***************************************************************************** typedef enum { DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1 DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2 } DCSM_SemaphoreZone; //***************************************************************************** // //! Values to distinguish the security status of the zones. //! These values can be returned from DCSM_getZone1CSMSecurityStatus(), //! DCSM_getZone2CSMSecurityStatus(). // //***************************************************************************** typedef enum { DCSM_STATUS_SECURE, //!< Secure DCSM_STATUS_UNSECURE, //!< Unsecure DCSM_STATUS_LOCKED, //!< Locked DCSM_STATUS_BLOCKED //!< Blocked } DCSM_SecurityStatus; //***************************************************************************** // // Values to distinguish the status of the Control Registers. These values // describe can be used with the return values of // DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus(). // //***************************************************************************** //***************************************************************************** // //! Values to decribe the EXEONLY Status. //! These values are returned from to DCSM_getZone1RAMEXEStatus(), //! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(), //! DCSM_getZone2FlashEXEStatus(). // //***************************************************************************** typedef enum { DCSM_PROTECTED, //!< Protected DCSM_UNPROTECTED, //!< Unprotected DCSM_INCORRECT_ZONE //!< Incorrect Zone }DCSM_EXEOnlyStatus; //***************************************************************************** // //! Values to distinguish RAM Module. //! These values can be passed to DCSM_getZone1RAMEXEStatus() //! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone(). // //***************************************************************************** typedef enum { DCSM_RAMLS0, //!< RAMLS0 DCSM_RAMLS1, //!< RAMLS1 DCSM_RAMLS2, //!< RAMLS2 DCSM_RAMLS3, //!< RAMLS3 DCSM_RAMLS4, //!< RAMLS4 DCSM_RAMLS5, //!< RAMLS5 DCSM_RAMLS6, //!< RAMLS6 DCSM_RAMLS7 //!< RAMLS7 } DCSM_RAMModule; //***************************************************************************** // //! Values to distinguish Flash Sector. //! These values can be passed to DCSM_getZone1FlashEXEStatus() //! DCSM_getZone2FlashEXEStatus(), DCSM_getFlashSectorZone(). // //***************************************************************************** typedef enum { DCSM_BANK0_SECTOR0, //!< Bank 0 - Sector 0 DCSM_BANK0_SECTOR1, //!< Bank 0 - Sector 1 DCSM_BANK0_SECTOR2, //!< Bank 0 - Sector 2 DCSM_BANK0_SECTOR3, //!< Bank 0 - Sector 3 DCSM_BANK0_SECTOR4, //!< Bank 0 - Sector 4 DCSM_BANK0_SECTOR5, //!< Bank 0 - Sector 5 DCSM_BANK0_SECTOR6, //!< Bank 0 - Sector 6 DCSM_BANK0_SECTOR7, //!< Bank 0 - Sector 7 DCSM_BANK0_SECTOR8, //!< Bank 0 - Sector 8 DCSM_BANK0_SECTOR9, //!< Bank 0 - Sector 9 DCSM_BANK0_SECTOR10, //!< Bank 0 - Sector 10 DCSM_BANK0_SECTOR11, //!< Bank 0 - Sector 11 DCSM_BANK0_SECTOR12, //!< Bank 0 - Sector 12 DCSM_BANK0_SECTOR13, //!< Bank 0 - Sector 13 DCSM_BANK0_SECTOR14, //!< Bank 0 - Sector 14 DCSM_BANK0_SECTOR15, //!< Bank 0 - Sector 15 DCSM_BANK1_SECTOR0, //!< Bank 1 - Sector 0 DCSM_BANK1_SECTOR1, //!< Bank 1 - Sector 1 DCSM_BANK1_SECTOR2, //!< Bank 1 - Sector 2 DCSM_BANK1_SECTOR3, //!< Bank 1 - Sector 3 DCSM_BANK1_SECTOR4, //!< Bank 1 - Sector 4 DCSM_BANK1_SECTOR5, //!< Bank 1 - Sector 5 DCSM_BANK1_SECTOR6, //!< Bank 1 - Sector 6 DCSM_BANK1_SECTOR7, //!< Bank 1 - Sector 7 DCSM_BANK1_SECTOR8, //!< Bank 1 - Sector 8 DCSM_BANK1_SECTOR9, //!< Bank 1 - Sector 9 DCSM_BANK1_SECTOR10, //!< Bank 1 - Sector 10 DCSM_BANK1_SECTOR11, //!< Bank 1 - Sector 11 DCSM_BANK1_SECTOR12, //!< Bank 1 - Sector 12 DCSM_BANK1_SECTOR13, //!< Bank 1 - Sector 13 DCSM_BANK1_SECTOR14, //!< Bank 1 - Sector 14 DCSM_BANK1_SECTOR15 //!< Bank 1 - Sector 15 } DCSM_Sector; //***************************************************************************** // // Defines for the FLSEM register. // These values can be passed to the DCSM_setFlashSemaphore(). // //***************************************************************************** //***************************************************************************** // // DCSM functions // //***************************************************************************** //***************************************************************************** // //! Secures zone 1 by setting the FORCESEC bit of Z1_CR register //! //! This function resets the state of the zone. If the zone is unlocked, //! it will lock (secure) the zone and also reset all the bits in the //! Control Register. //! //! \return None. // //***************************************************************************** static inline void DCSM_secureZone1(void) { // // Write to the FORCESEC bit. // (*((volatile uint16_t *)(0x0005F000U + 0x19U)))|= 0x8000U; } //***************************************************************************** // //! Secures zone 2 by setting the FORCESEC bit of Z2_CR register //! //! This function resets the state of the zone. If the zone is unlocked, //! it will lock (secure) the zone and also reset all the bits in the //! Control Register. //! //! \return None. // //***************************************************************************** static inline void DCSM_secureZone2(void) { // // Write to the FORCESEC bit. // (*((volatile uint16_t *)(0x0005F040U + 0x19U)))|= 0x8000U; } //***************************************************************************** // //! Returns the CSM security status of zone 1 //! //! This function returns the security status of zone 1 CSM //! //! \return Returns security status as an enumerated type DCSM_SecurityStatus. // //***************************************************************************** static inline DCSM_SecurityStatus DCSM_getZone1CSMSecurityStatus(void) { uint16_t status; DCSM_SecurityStatus returnStatus; status = (*((volatile uint16_t *)(0x0005F000U + 0x19U))); // // if ARMED bit is set and UNSECURED bit is set then CSM is unsecured. // Else it is secure. // if(((status & 0x40U) != 0U) && ((status & 0x20U) != 0U)) { returnStatus = DCSM_STATUS_UNSECURE; } else if((status & 0x10U) == 0x10U) { returnStatus = DCSM_STATUS_BLOCKED; } else if((status & 0x8U) == 0x8U) { returnStatus = DCSM_STATUS_LOCKED; } else { returnStatus = DCSM_STATUS_SECURE; } return(returnStatus); } //***************************************************************************** // //! Returns the CSM security status of zone 2 //! //! This function returns the security status of zone 2 CSM //! //! \return Returns security status as an enumerated type DCSM_SecurityStatus. // //***************************************************************************** static inline DCSM_SecurityStatus DCSM_getZone2CSMSecurityStatus(void) { uint16_t status; DCSM_SecurityStatus returnStatus; status = (*((volatile uint16_t *)(0x0005F040U + 0x19U))); // // if ARMED bit is set and UNSECURED bit is set then CSM is unsecured. // Else it is secure. // if(((status & 0x40U) != 0U) && ((status & 0x20U) != 0U)) { returnStatus = DCSM_STATUS_UNSECURE; } else if((status & 0x10U) == 0x10U) { returnStatus = DCSM_STATUS_BLOCKED; } else if((status & 0x8U) == 0x8U) { returnStatus = DCSM_STATUS_LOCKED; } else { returnStatus = DCSM_STATUS_SECURE; } return(returnStatus); } //***************************************************************************** // //! Returns the Control Status of zone 1 //! //! This function returns the Control Status of zone 1 CSM //! //! \return Returns the contents of the Control Register which can be //! used with provided defines. // //***************************************************************************** static inline uint16_t DCSM_getZone1ControlStatus(void) { // // Return the contents of the CR register. // return((*((volatile uint16_t *)(0x0005F000U + 0x19U)))); } //***************************************************************************** // //! Returns the Control Status of zone 2 //! //! This function returns the Control Status of zone 2 CSM //! //! \return Returns the contents of the Control Register which can be //! used with the provided defines. // //***************************************************************************** static inline uint16_t DCSM_getZone2ControlStatus(void) { // // Return the contents of the CR register. // return((*((volatile uint16_t *)(0x0005F040U + 0x19U)))); } //***************************************************************************** // //! Returns the security zone a RAM section belongs to //! //! \param module is the RAM module value. Valid values are type DCSM_RAMModule //! - \b DCSM_RAMLS0 //! - \b DCSM_RAMLS1 //! - \b DCSM_RAMLS2 //! - \b DCSM_RAMLS3 //! - \b DCSM_RAMLS4 //! - \b DCSM_RAMLS5 //! - \b DCSM_RAMLS6 //! - \b DCSM_RAMLS7 //! //! This function returns the security zone a RAM section belongs to. //! //! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible, //! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if //! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section //! doesn't belong to any zone (or if the section is unsecure). // //***************************************************************************** static inline DCSM_MemoryStatus DCSM_getRAMZone(DCSM_RAMModule module) { uint16_t shift = (uint16_t)module * 2U; // //Read the RAMSTAT register for the specific RAM Module. // return((DCSM_MemoryStatus)(((*((volatile uint32_t *)(0x0005F070U + 0x4U))) >> shift) & 0x03U)); } //***************************************************************************** // //! Returns the security zone a flash sector belongs to //! //! \param sector is the flash sector value. Use DCSM_Sector type. //! //! This function returns the security zone a flash sector belongs to. //! //! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible , //! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if //! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section //! doesn't belong to any zone (or if the section is unsecure).. // //***************************************************************************** static inline DCSM_MemoryStatus DCSM_getFlashSectorZone(DCSM_Sector sector) { uint32_t sectStat; uint16_t shift; // // Get the Sector status register for the specific bank // if(sector <= DCSM_BANK0_SECTOR15) { sectStat = (*((volatile uint32_t *)(0x0005F070U + 0x2U))); shift = (uint16_t)sector * 2U; } else { sectStat = (*((volatile uint32_t *)(0x0005F070U + 0x8U))); shift = ((uint16_t)sector & 0xFU) * (uint16_t)2U; } // //Read the SECTSTAT register for the specific Flash Sector. // return((DCSM_MemoryStatus)((sectStat >> shift) & 0x3U)); } //***************************************************************************** // //! Read Zone 1 Link Pointer Error //! //! \param bank is the DCSM_Bank to operate on. //! //! A non-zero value indicates an error on the bit position that is set to 1. //! //! \return Returns the value of the Zone 1 Link Pointer error. // //***************************************************************************** static inline uint32_t DCSM_getZone1LinkPointerError(DCSM_Bank bank) { uint32_t tempReturn; // // Return the LinkPointer Error for specific bank // if(bank == DCSM_BANK0) { tempReturn = (*((volatile uint32_t *)(0x0005F000U + 0x6U))); } else { tempReturn = (*((volatile uint32_t *)(0x0005F100U + 0x6U))); } return(tempReturn); } //***************************************************************************** // //! Read Zone 2 Link Pointer Error //! //! \param bank is the DCSM_Bank to operate on. //! //! A non-zero value indicates an error on the bit position that is set to 1. //! //! \return Returns the value of the Zone 2 Link Pointer error. // //***************************************************************************** static inline uint32_t DCSM_getZone2LinkPointerError(DCSM_Bank bank) { uint32_t tempReturn; // // Return the LinkPointer Error for specific bank // if(bank == DCSM_BANK0) { tempReturn = (*((volatile uint32_t *)(0x0005F040U + 0x6U))); } else { tempReturn = (*((volatile uint32_t *)(0x0005F140U + 0x6U))); } return(tempReturn); } //***************************************************************************** // //! Get the status of the security configuration load from USER-OTP or sector //! error status //! //! \return Returns 0 if no error in loading security information from //! USER-OTP, 1 if an error has occurred in the load from USER-OTP. // //***************************************************************************** static inline _Bool DCSM_getFlashErrorStatus(void) { return((_Bool)((*((volatile uint32_t *)(0x0005F070U + 0xAU))) & 0x1U)); } //***************************************************************************** // //! Clear the Flash Error Status bit //! //! Write a '1' to the clear bit to clear the sector error status bit. //! //! \return None. // //***************************************************************************** static inline void DCSM_clearFlashErrorStatus(void) { (*((volatile uint32_t *)(0x0005F070U + 0xCU))) |= 0x1U; } //***************************************************************************** // //! Set the force Flash Error Status bit //! //! Write a '1' to force bit to set the sector error status bit. //! //! \return None. // //***************************************************************************** static inline void DCSM_forceFlashErrorStatus(void) { (*((volatile uint32_t *)(0x0005F070U + 0xEU))) |= 0x1U; } //***************************************************************************** // //! Unlocks Zone 1 CSM. //! //! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the //! CSM password for zone 1. //! //! This function unlocks the CSM password. It first reads the //! four password locations in the User OTP. If any of the password values is //! different from 0xFFFFFFFF, it unlocks the device by writing the provided //! passwords into CSM Key registers //! //! \return None. // //***************************************************************************** extern void DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey); //***************************************************************************** // //! Unlocks Zone 2 CSM. //! //! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM //! password for zone 2. //! //! This function unlocks the CSM password. It first reads //! the four password locations in the User OTP. If any of the password values //! is different from 0xFFFFFFFF, it unlocks the device by writing the //! provided passwords into CSM Key registers //! //! \return None. // //***************************************************************************** extern void DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey); //***************************************************************************** // //! Returns the EXE-ONLY status of zone 1 for a flash sector //! //! \param sector is the flash sector value. Use DCSM_Sector type. //! //! This function takes in a valid sector value and returns the status of EXE //! ONLY security protection for the sector. //! //! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, //! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, //! DCSM_INCORRECT_ZONE if sector does not belong to this zone. // //***************************************************************************** extern DCSM_EXEOnlyStatus DCSM_getZone1FlashEXEStatus(DCSM_Sector sector); //***************************************************************************** // //! Returns the EXE-ONLY status of zone 1 for a RAM module //! //! \param module is the RAM module value. Valid values are type DCSM_RAMModule //! - \b DCSM_RAMLS0 //! - \b DCSM_RAMLS1 //! - \b DCSM_RAMLS2 //! - \b DCSM_RAMLS3 //! - \b DCSM_RAMLS4 //! - \b DCSM_RAMLS5 //! - \b DCSM_RAMLS6 //! - \b DCSM_RAMLS7 //! //! This function takes in a valid module value and returns the status of EXE //! ONLY security protection for that module. //! //! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, //! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, //! DCSM_INCORRECT_ZONE if module does not belong to this zone. // //***************************************************************************** extern DCSM_EXEOnlyStatus DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module); //***************************************************************************** // //! Returns the EXE-ONLY status of zone 2 for a flash sector //! //! \param sector is the flash sector value. Use DCSM_Sector type. //! //! This function takes in a valid sector value and returns the status of EXE //! ONLY security protection for the sector. //! //! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, //! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, //! DCSM_INCORRECT_ZONE if sector does not belong to this zone. // //***************************************************************************** extern DCSM_EXEOnlyStatus DCSM_getZone2FlashEXEStatus(DCSM_Sector sector); //***************************************************************************** // //! Returns the EXE-ONLY status of zone 2 for a RAM module //! //! \param module is the RAM module value. Valid values are type DCSM_RAMModule //! - \b DCSM_RAMLS0 //! - \b DCSM_RAMLS1 //! - \b DCSM_RAMLS2 //! - \b DCSM_RAMLS3 //! - \b DCSM_RAMLS4 //! - \b DCSM_RAMLS5 //! - \b DCSM_RAMLS6 //! - \b DCSM_RAMLS7 //! //! This function takes in a valid module value and returns the status of EXE //! ONLY security protection for that module. //! //! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, //! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, //! DCSM_INCORRECT_ZONE if module does not belong to this zone. // //***************************************************************************** extern DCSM_EXEOnlyStatus DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module); //***************************************************************************** // //! Claims the zone semaphore which allows access to the Flash Wrapper register //! for that zone. //! //! \param zone is the zone which is trying to claim the semaphore which allows //! access to the Flash Wrapper registers. //! //! \return Returns true for a successful semaphore capture, false if it was //! unable to capture the semaphore. // //***************************************************************************** extern _Bool DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone); //***************************************************************************** // //! Releases the zone semaphore. //! //! \return Returns true if was successful in releasing the zone semaphore and //! false if it was unsuccessful in releasing the zone semaphore. //! //! \note If the calling function is not in the right zone to be able //! to access this register, it will return a false. // //***************************************************************************** extern _Bool DCSM_releaseZoneSemaphore(void); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: dma.h // // TITLE: C28x DMA driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup dma_api DMA //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_dma.h // // TITLE: Definitions for the DMA registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the DMA register offsets // //***************************************************************************** // Register // Register // Register // Register // Register // Register // Register // Register // Register // Shadow Register // Register // Active Register // Register //***************************************************************************** // // The following are defines for the bit fields in the DMACTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DEBUGCTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PRIORITYCTRL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PRIORITYSTAT register // //***************************************************************************** // Bits //***************************************************************************** // // The following are defines for the bit fields in the MODE register // //***************************************************************************** // Select //***************************************************************************** // // The following are defines for the bit fields in the CONTROL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the BURST_SIZE register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the BURST_COUNT register // //***************************************************************************** //***************************************************************************** // // Values that can be passed to DMA_configMode() as the config parameter. // //***************************************************************************** //! Only one burst transfer performed per trigger. //! Burst transfers occur without additional event triggers after the first. //! DMA channel will be disabled at the end of a transfer. //! DMA reinitializes when the transfer count is zero and waits for a trigger. //! DMA transfers 16 bits at a time. //! DMA transfers 32 bits at a time. //***************************************************************************** // //! Values that can be passed to DMA_configMode() as the \e trigger parameter. // //***************************************************************************** typedef enum { DMA_TRIGGER_SOFTWARE = 0, DMA_TRIGGER_ADCA1 = 1, DMA_TRIGGER_ADCA2 = 2, DMA_TRIGGER_ADCA3 = 3, DMA_TRIGGER_ADCA4 = 4, DMA_TRIGGER_ADCAEVT = 5, DMA_TRIGGER_ADCB1 = 6, DMA_TRIGGER_ADCB2 = 7, DMA_TRIGGER_ADCB3 = 8, DMA_TRIGGER_ADCB4 = 9, DMA_TRIGGER_ADCBEVT = 10, DMA_TRIGGER_ADCC1 = 11, DMA_TRIGGER_ADCC2 = 12, DMA_TRIGGER_ADCC3 = 13, DMA_TRIGGER_ADCC4 = 14, DMA_TRIGGER_ADCCEVT = 15, DMA_TRIGGER_XINT1 = 29, DMA_TRIGGER_XINT2 = 30, DMA_TRIGGER_XINT3 = 31, DMA_TRIGGER_XINT4 = 32, DMA_TRIGGER_XINT5 = 33, DMA_TRIGGER_EPWM1SOCA = 36, DMA_TRIGGER_EPWM1SOCB = 37, DMA_TRIGGER_EPWM2SOCA = 38, DMA_TRIGGER_EPWM2SOCB = 39, DMA_TRIGGER_EPWM3SOCA = 40, DMA_TRIGGER_EPWM3SOCB = 41, DMA_TRIGGER_EPWM4SOCA = 42, DMA_TRIGGER_EPWM4SOCB = 43, DMA_TRIGGER_EPWM5SOCA = 44, DMA_TRIGGER_EPWM5SOCB = 45, DMA_TRIGGER_EPWM6SOCA = 46, DMA_TRIGGER_EPWM6SOCB = 47, DMA_TRIGGER_EPWM7SOCA = 48, DMA_TRIGGER_EPWM7SOCB = 49, DMA_TRIGGER_EPWM8SOCA = 50, DMA_TRIGGER_EPWM8SOCB = 51, DMA_TRIGGER_TINT0 = 68, DMA_TRIGGER_TINT1 = 69, DMA_TRIGGER_TINT2 = 70, DMA_TRIGGER_ECAP1 = 75, DMA_TRIGGER_ECAP2 = 76, DMA_TRIGGER_ECAP3 = 77, DMA_TRIGGER_ECAP4 = 78, DMA_TRIGGER_ECAP5 = 79, DMA_TRIGGER_ECAP6 = 80, DMA_TRIGGER_ECAP7 = 81, DMA_TRIGGER_SDFM1FLT1 = 96, DMA_TRIGGER_SDFM1FLT2 = 97, DMA_TRIGGER_SDFM1FLT3 = 98, DMA_TRIGGER_SDFM1FLT4 = 99, DMA_TRIGGER_SPIATX = 109, DMA_TRIGGER_SPIARX = 110, DMA_TRIGGER_SPIBTX = 111, DMA_TRIGGER_SPIBRX = 112, DMA_TRIGGER_LINATX = 117, DMA_TRIGGER_LINARX = 118, DMA_TRIGGER_FSITXA = 123, DMA_TRIGGER_FSIRXA = 125, DMA_TRIGGER_CANAIF1 = 167, DMA_TRIGGER_CANAIF2 = 168, DMA_TRIGGER_CANAIF3 = 169, DMA_TRIGGER_CANBIF1 = 170, DMA_TRIGGER_CANBIF2 = 171, DMA_TRIGGER_CANBIF3 = 172 } DMA_Trigger; //***************************************************************************** // //! Values that can be passed to DMA_setInterruptMode() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! DMA interrupt is generated at the beginning of a transfer DMA_INT_AT_BEGINNING, //! DMA interrupt is generated at the end of a transfer DMA_INT_AT_END } DMA_InterruptMode; //***************************************************************************** // //! Values that can be passed to DMA_setEmulationMode() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! Transmission stops after current read-write access is completed DMA_EMULATION_STOP, //! Continue DMA operation regardless of emulation suspend DMA_EMULATION_FREE_RUN } DMA_EmulationMode; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks an DMA channel base address. //! //! \param base specifies the DMA channel base address. //! //! This function determines if a DMA channel base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Initializes the DMA controller to a known state. //! //! This function configures does a hard reset of the DMA controller in order //! to put it into a known state. The function also sets the DMA to run free //! during an emulation suspend (see the field DEBUGCTRL.FREE for more info). //! //! \return None. // //***************************************************************************** static inline void DMA_initController(void) { __eallow(); // Set the hard reset bit. One NOP is required after HARDRESET. (*((volatile uint16_t *)(0x00001000U + 0x0U))) |= 0x1U; __asm(" NOP"); __edis(); } //***************************************************************************** // //! Sets DMA emulation mode. //! //! \param mode is the emulation mode to be selected. //! //! This function sets the behavior of the DMA operation when an emulation //! suspend occurs. The \e mode parameter can be one of the following: //! //! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is //! completed. //! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a //! the suspend. //! //! \return None. // //***************************************************************************** static inline void DMA_setEmulationMode(DMA_EmulationMode mode) { __eallow(); // Set emulation mode if(mode == DMA_EMULATION_STOP) { (*((volatile uint16_t *)(0x00001000U + 0x1U))) &= ~0x8000U; } else { (*((volatile uint16_t *)(0x00001000U + 0x1U))) |= 0x8000U; } __edis(); } //***************************************************************************** // //! Enables peripherals to trigger a DMA transfer. //! //! \param base is the base address of the DMA channel control registers. //! //! This function enables the selected peripheral trigger to start a DMA //! transfer on the specified channel. //! //! \return None. // //***************************************************************************** static inline void DMA_enableTrigger(uint32_t base) { // Check the arguments. ; // Set the peripheral interrupt trigger enable bit. __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= 0x100U; __edis(); } //***************************************************************************** // //! Disables peripherals from triggering a DMA transfer. //! //! \param base is the base address of the DMA channel control registers. //! //! This function disables the selected peripheral trigger from starting a DMA //! transfer on the specified channel. This also disables the use of the //! software force using the DMA_forceTrigger() API. //! //! \return None. // //***************************************************************************** static inline void DMA_disableTrigger(uint32_t base) { // Check the arguments. ; // Clear the peripheral interrupt trigger enable bit. __eallow(); (*((volatile uint16_t *)(base + 0x0U))) &= ~0x100U; __edis(); } //***************************************************************************** // //! Force a peripheral trigger to a DMA channel. //! //! \param base is the base address of the DMA channel control registers. //! //! This function sets the peripheral trigger flag and if triggering a DMA //! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be //! forced. //! //! \return None. // //***************************************************************************** static inline void DMA_forceTrigger(uint32_t base) { // Check the arguments. ; // Set the peripheral interrupt trigger force bit. __eallow(); (*((volatile uint16_t *)(base + 0x1U))) |= 0x8U; __edis(); } //***************************************************************************** // //! Clears a DMA channel's peripheral trigger flag. //! //! \param base is the base address of the DMA channel control registers. //! //! This function clears the peripheral trigger flag. Normally, you would use //! this function when initializing the DMA for the first time. The flag is //! cleared automatically when the DMA starts the first burst of a transfer. //! //! \return None. // //***************************************************************************** static inline void DMA_clearTriggerFlag(uint32_t base) { // Check the arguments. ; // Write a one to the clear bit to clear the peripheral trigger flag. __eallow(); (*((volatile uint16_t *)(base + 0x1U))) |= 0x10U; __edis(); } //***************************************************************************** // //! Gets the status of a DMA channel's peripheral trigger flag. //! //! \param base is the base address of the DMA channel control registers. //! //! This function returns \b true if a peripheral trigger event has occurred //! The flag is automatically cleared when the first burst transfer begins, but //! if needed, it can be cleared using DMA_clearTriggerFlag(). //! //! \return Returns \b true if a peripheral trigger event has occurred and its //! flag is set. Returns \b false otherwise. // //***************************************************************************** static inline _Bool DMA_getTriggerFlagStatus(uint32_t base) { // Check the arguments. ; // Read the peripheral trigger flag and return appropriately. return(((*((volatile uint16_t *)(base + 0x1U))) & 0x100U) != 0U); } //***************************************************************************** // //! Starts a DMA channel. //! //! \param base is the base address of the DMA channel control registers. //! //! This function starts the DMA running, typically after you have configured //! it. It will wait for the first trigger event to start operation. To halt //! the channel use DMA_stopChannel(). //! //! \return None. // //***************************************************************************** static inline void DMA_startChannel(uint32_t base) { // Check the arguments. ; // Set the run bit. __eallow(); (*((volatile uint16_t *)(base + 0x1U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Halts a DMA channel. //! //! \param base is the base address of the DMA channel control registers. //! //! This function halts the DMA at its current state and any current read-write //! access is completed. To start the channel again use DMA_startChannel(). //! //! \return None. // //***************************************************************************** static inline void DMA_stopChannel(uint32_t base) { // Check the arguments. ; // Set the halt bit. __eallow(); (*((volatile uint16_t *)(base + 0x1U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Enables a DMA channel interrupt source. //! //! \param base is the base address of the DMA channel control registers. //! //! This function enables the indicated DMA channel interrupt source. //! //! \return None. // //***************************************************************************** static inline void DMA_enableInterrupt(uint32_t base) { // Check the arguments. ; // Enable the specified DMA channel interrupt. __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Disables a DMA channel interrupt source. //! //! \param base is the base address of the DMA channel control registers. //! //! This function disables the indicated DMA channel interrupt source. //! //! \return None. // //***************************************************************************** static inline void DMA_disableInterrupt(uint32_t base) { // Check the arguments. ; // Disable the specified DMA channel interrupt. __eallow(); (*((volatile uint16_t *)(base + 0x0U))) &= ~0x8000U; __edis(); } //***************************************************************************** // //! Enables the DMA channel overrun interrupt. //! //! \param base is the base address of the DMA channel control registers. //! //! This function enables the indicated DMA channel's ability to generate an //! interrupt upon the detection of an overrun. An overrun is when a peripheral //! event trigger is received by the DMA before a previous trigger on that //! channel had been serviced and its flag had been cleared. //! //! Note that this is the same interrupt signal as the interrupt that gets //! generated at the beginning/end of a transfer. That interrupt must first be //! enabled using DMA_enableInterrupt() in order for the overrun interrupt to //! be generated. //! //! \return None. // //***************************************************************************** static inline void DMA_enableOverrunInterrupt(uint32_t base) { // Check the arguments. ; // Enable the specified DMA channel interrupt. __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= 0x80U; __edis(); } //***************************************************************************** // //! Disables the DMA channel overrun interrupt. //! //! \param base is the base address of the DMA channel control registers. //! //! This function disables the indicated DMA channel's ability to generate an //! interrupt upon the detection of an overrun. //! //! \return None. // //***************************************************************************** static inline void DMA_disableOverrunInterrupt(uint32_t base) { // Check the arguments. ; // Disable the specified DMA channel interrupt. __eallow(); (*((volatile uint16_t *)(base + 0x0U))) &= ~0x80U; __edis(); } //***************************************************************************** // //! Clears the DMA channel error flags. //! //! \param base is the base address of the DMA channel control registers. //! //! This function clears both the DMA channel's sync error flag and its //! overrun error flag. //! //! \return None. // //***************************************************************************** static inline void DMA_clearErrorFlag(uint32_t base) { // Check the arguments. ; // Write to the error clear bit. __eallow(); (*((volatile uint16_t *)(base + 0x1U))) |= 0x80U; __edis(); } //***************************************************************************** // //! Sets the interrupt generation mode of a DMA channel interrupt. //! //! \param base is the base address of the DMA channel control registers. //! \param mode is a flag to indicate the channel interrupt mode. //! //! This function sets the channel interrupt mode. When the \e mode parameter //! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the //! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be //! generated at the beginning of a new transfer. Generating at the beginning //! of a new transfer is the default behavior. //! //! \return None. // //***************************************************************************** static inline void DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode) { // Check the arguments. ; __eallow(); // Write the selected interrupt generation mode to the register. if(mode == DMA_INT_AT_END) { (*((volatile uint16_t *)(base + 0x0U))) |= 0x200U; } else { (*((volatile uint16_t *)(base + 0x0U))) &= ~0x200U; } __edis(); } //***************************************************************************** // //! Sets the DMA channel priority mode. //! //! \param ch1IsHighPri is a flag to indicate the channel interrupt mode. //! //! This function sets the channel interrupt mode. When the \e ch1IsHighPri //! parameter is \b false, the DMA channels are serviced in round-robin mode. //! This is the default behavior. //! //! If \b true, channel 1 will be given higher priority than the other //! channels. This means that if a channel 1 trigger occurs, the current word //! transfer on any other channel is completed and channel 1 is serviced for //! the complete burst count. The lower-priority channel's interrupted transfer //! will then resume. //! //! \return None. // //***************************************************************************** static inline void DMA_setPriorityMode(_Bool ch1IsHighPri) { __eallow(); // Write the selected priority mode to the register. if(ch1IsHighPri) { (*((volatile uint16_t *)(0x00001000U + 0x4U))) |= 0x1U; } else { (*((volatile uint16_t *)(0x00001000U + 0x4U))) &= ~0x1U; } __edis(); } //***************************************************************************** // //! Configures the DMA channel //! //! \param base is the base address of the DMA channel control registers. //! \param *destAddr is the interrupt source that triggers a DMA transfer. //! \param *srcAddr is a bit field of several configuration selections. //! //! This function configures the source and destination addresses of a DMA //! channel. The parameters are pointers to the data to be transferred. //! //! \return None. // //***************************************************************************** extern void DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr); //***************************************************************************** // //! Configures the DMA channel's burst settings. //! //! \param base is the base address of the DMA channel control registers. //! \param size is the number of words transferred per burst. //! \param srcStep is the amount to increment or decrement the source address //! after each word of a burst. //! \param destStep is the amount to increment or decrement the destination //! address after each word of a burst. //! //! This function configures the size of each burst and the address step size. //! //! The \e size parameter is the number of words that will be transferred //! during a single burst. Possible amounts range from 1 word to 32 words. //! //! The \e srcStep and \e destStep parameters specify the address step that //! should be added to the source and destination addresses after each //! transferred word of a burst. Only signed values from -4096 to 4095 are //! valid. //! //! \note Note that regardless of what data size (configured by //! DMA_configMode()) is used, parameters are in terms of 16-bits words. //! //! \return None. // //***************************************************************************** extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, int16_t destStep); //***************************************************************************** // //! Configures the DMA channel's transfer settings. //! //! \param base is the base address of the DMA channel control registers. //! \param transferSize is the number of bursts per transfer. //! \param srcStep is the amount to increment or decrement the source address //! after each burst of a transfer unless a wrap occurs. //! \param destStep is the amount to increment or decrement the destination //! address after each burst of a transfer unless a wrap occurs. //! //! This function configures the transfer size and the address step that is //! made after each burst. //! //! The \e transferSize parameter is the number of bursts per transfer. If DMA //! channel interrupts are enabled, they will occur after this number of bursts //! have completed. The maximum number of bursts is 65536. //! //! The \e srcStep and \e destStep parameters specify the address step that //! should be added to the source and destination addresses after each //! transferred burst of a transfer. Only signed values from -4096 to 4095 are //! valid. If a wrap occurs, these step values will be ignored. Wrapping is //! configured with DMA_configWrap(). //! //! \note Note that regardless of what data size (configured by //! DMA_configMode()) is used, parameters are in terms of 16-bits words. //! //! \return None. // //***************************************************************************** extern void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, int16_t destStep); //***************************************************************************** // //! Configures the DMA channel's wrap settings. //! //! \param base is the base address of the DMA channel control registers. //! \param srcWrapSize is the number of bursts to be transferred before a wrap //! of the source address occurs. //! \param srcStep is the amount to increment or decrement the source address //! after each burst of a transfer unless a wrap occurs. //! \param destWrapSize is the number of bursts to be transferred before a wrap //! of the destination address occurs. //! \param destStep is the amount to increment or decrement the destination //! address after each burst of a transfer unless a wrap occurs. //! //! This function configures the DMA channel's wrap settings. //! //! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts //! that are to be transferred before their respective addresses are wrapped. //! The maximum wrap size is 65536 bursts. //! //! The \e srcStep and \e destStep parameters specify the address step that //! should be added to the source and destination addresses when the wrap //! occurs. Only signed values from -4096 to 4095 are valid. //! //! \note Note that regardless of what data size (configured by //! DMA_configMode()) is used, parameters are in terms of 16-bits words. //! //! \return None. // //***************************************************************************** extern void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, uint32_t destWrapSize, int16_t destStep); //***************************************************************************** // //! Configures the DMA channel trigger and mode. //! //! \param base is the base address of the DMA channel control registers. //! \param trigger is the interrupt source that triggers a DMA transfer. //! \param config is a bit field of several configuration selections. //! //! This function configures the DMA channel's trigger and mode. //! //! The \e trigger parameter is the interrupt source that will trigger the //! start of a DMA transfer. //! //! The \e config parameter is the logical OR of the following values: //! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled, //! the subsequent burst transfers occur without additional event triggers //! after the first event trigger. If disabled, only one burst transfer is //! performed per event trigger. //! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled //! the DMA reinitializes when the transfer count is zero and waits for the //! next interrupt event trigger. If disabled, the DMA stops and clears the //! run status bit. //! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects //! whether the databus width is 16 or 32 bits. //! //! \return None. // //***************************************************************************** extern void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: ecap.h // // TITLE: C28x ECAP driver // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup ecap_api eCAP //! @{ // //***************************************************************************** // **************************************************************************** // the includes // **************************************************************************** //########################################################################### // // FILE: hw_ecap.h // // TITLE: Definitions for the ECAP registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the ECAP register offsets // //***************************************************************************** // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the ECCTL0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ECCTL1 register // //***************************************************************************** // select // Event 1 // select // Event 2 // select // Event 3 // select // Event 4 // a Cap Event //***************************************************************************** // // The following are defines for the bit fields in the ECCTL2 register // //***************************************************************************** // for continuous // select // counter, and interrupt flags. //***************************************************************************** // // The following are defines for the bit fields in the ECEINT register // //***************************************************************************** // Enable // Enable // Enable // Enable // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the ECFLG register // //***************************************************************************** // Flag // Flag // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the ECCLR register // //***************************************************************************** // Clear //***************************************************************************** // // The following are defines for the bit fields in the ECFRC register // //***************************************************************************** // Interrupt // Interrupt // Interrupt // Interrupt // Interrupt //***************************************************************************** // // The following are defines for the bit fields in the ECAPSYNCINSEL register // //***************************************************************************** //***************************************************************************** // // eCAP minimum and maximum values // //***************************************************************************** //***************************************************************************** // // Values that can be passed to ECAP_enableInterrupt(), // ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as // the intFlags parameter and returned by ECAP_getInterruptSource(). // //***************************************************************************** //! Event 1 ISR source //! //! Event 2 ISR source //! //! Event 3 ISR source //! //! Event 4 ISR source //! //! Counter overflow ISR source //! //! Counter equals period ISR source //! //! Counter equals compare ISR source //! //***************************************************************************** // //! Values that can be passed to ECAP_setEmulationMode() as the //! \e mode parameter. // //***************************************************************************** typedef enum { //! TSCTR is stopped on emulation suspension ECAP_EMULATION_STOP = 0x0U, //! TSCTR runs until 0 before stopping on emulation suspension ECAP_EMULATION_RUN_TO_ZERO = 0x1U, //! TSCTR is not affected by emulation suspension ECAP_EMULATION_FREE_RUN = 0x2U }ECAP_EmulationMode; //***************************************************************************** // //! Values that can be passed to ECAP_setCaptureMode() as the //! \e mode parameter. // //***************************************************************************** typedef enum { //! eCAP operates in continuous capture mode ECAP_CONTINUOUS_CAPTURE_MODE = 0U, //! eCAP operates in one shot capture mode ECAP_ONE_SHOT_CAPTURE_MODE = 1U }ECAP_CaptureMode; //***************************************************************************** // //! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(), //! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(), //! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter. // //***************************************************************************** typedef enum { ECAP_EVENT_1 = 0U, //!< eCAP event 1 ECAP_EVENT_2 = 1U, //!< eCAP event 2 ECAP_EVENT_3 = 2U, //!< eCAP event 3 ECAP_EVENT_4 = 3U //!< eCAP event 4 }ECAP_Events; //***************************************************************************** // //! Values that can be passed to ECAP_setSyncOutMode() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! sync out on the sync in signal and software force ECAP_SYNC_OUT_SYNCI = 0x00, //! sync out on counter equals period ECAP_SYNC_OUT_COUNTER_PRD = 0x40, //! Disable sync out signal ECAP_SYNC_OUT_DISABLED = 0x80 }ECAP_SyncOutMode; //***************************************************************************** // //! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity //! parameter. // //***************************************************************************** typedef enum { ECAP_APWM_ACTIVE_HIGH = 0x000, //!< APWM is active high ECAP_APWM_ACTIVE_LOW = 0x400 //!< APWM is active low }ECAP_APWMPolarity; //***************************************************************************** // //! Values that can be passed to ECAP_setEventPolarity() as the \e polarity //! parameter. // //***************************************************************************** typedef enum { ECAP_EVNT_RISING_EDGE = 0U, //!< Rising edge polarity ECAP_EVNT_FALLING_EDGE = 1U //!< Falling edge polarity }ECAP_EventPolarity; //***************************************************************************** // //! Values that can be passed to ECAP_selectECAPInput() as the \e input //! parameter. // //***************************************************************************** typedef enum { //! GPIO Input Crossbar output signal-1 ECAP_INPUT_INPUTXBAR1 = 0, //! GPIO Input Crossbar output signal-2 ECAP_INPUT_INPUTXBAR2 = 1, //! GPIO Input Crossbar output signal-3 ECAP_INPUT_INPUTXBAR3 = 2, //! GPIO Input Crossbar output signal-4 ECAP_INPUT_INPUTXBAR4 = 3, //! GPIO Input Crossbar output signal-5 ECAP_INPUT_INPUTXBAR5 = 4, //! GPIO Input Crossbar output signal-6 ECAP_INPUT_INPUTXBAR6 = 5, //! GPIO Input Crossbar output signal-7 ECAP_INPUT_INPUTXBAR7 = 6, //! GPIO Input Crossbar output signal-8 ECAP_INPUT_INPUTXBAR8 = 7, //! GPIO Input Crossbar output signal-9 ECAP_INPUT_INPUTXBAR9 = 8, //! GPIO Input Crossbar output signal-10 ECAP_INPUT_INPUTXBAR10 = 9, //! GPIO Input Crossbar output signal-11 ECAP_INPUT_INPUTXBAR11 = 10, //! GPIO Input Crossbar output signal-12 ECAP_INPUT_INPUTXBAR12 = 11, //! GPIO Input Crossbar output signal-13 ECAP_INPUT_INPUTXBAR13 = 12, //! GPIO Input Crossbar output signal-14 ECAP_INPUT_INPUTXBAR14 = 13, //! GPIO Input Crossbar output signal-15 ECAP_INPUT_INPUTXBAR15 = 14, //! GPIO Input Crossbar output signal-16 ECAP_INPUT_INPUTXBAR16 = 15, //! CANA INT0 Input ECAP_INPUT_CANA_INT0 = 20, //! CANB INT0 Input ECAP_INPUT_CANB_INT0 = 21, //! Delay clock for measurement ECAP_INPUT_ECAP_DELAY_CLOCK = 23, //! Output Xbar Output-1 ECAP_INPUT_OUTPUTXBAR1 = 24, //! Output Xbar Output-2 ECAP_INPUT_OUTPUTXBAR2 = 25, //! Output Xbar Output-3 ECAP_INPUT_OUTPUTXBAR3 = 26, //! Output Xbar Output-4 ECAP_INPUT_OUTPUTXBAR4 = 27, //! Output Xbar Output-5 ECAP_INPUT_OUTPUTXBAR5 = 28, //! Output Xbar Output-6 ECAP_INPUT_OUTPUTXBAR6 = 29, //! Output Xbar Output-7 ECAP_INPUT_OUTPUTXBAR7 = 30, //! Output Xbar Output-8 ECAP_INPUT_OUTPUTXBAR8 = 31, //! ADCC Event4 ECAP_INPUT_ADC_C_EVENT4 = 36, //! ADCC Event3 ECAP_INPUT_ADC_C_EVENT3 = 37, //! ADCC Event2 ECAP_INPUT_ADC_C_EVENT2 = 38, //! ADCC Event1 ECAP_INPUT_ADC_C_EVENT1 = 39, //! ADCB Event4 ECAP_INPUT_ADC_B_EVENT4 = 40, //! ADCB Event3 ECAP_INPUT_ADC_B_EVENT3 = 41, //! ADCB Event2 ECAP_INPUT_ADC_B_EVENT2 = 42, //! ADCB Event1 ECAP_INPUT_ADC_B_EVENT1 = 43, //! ADCA Event4 ECAP_INPUT_ADC_A_EVENT4 = 44, //! ADCA Event3 ECAP_INPUT_ADC_A_EVENT3 = 45, //! ADCA Event2 ECAP_INPUT_ADC_A_EVENT2 = 46, //! ADCA Event1 ECAP_INPUT_ADC_A_EVENT1 = 47, //! SDFM-1 Filter-1 Compare Low Trip ECAP_INPUT_SDFM1_FLT1_COMPARE_LOW = 64, //! SDFM-1 Filter-2 Compare Low Trip ECAP_INPUT_SDFM1_FLT2_COMPARE_LOW = 65, //! SDFM-1 Filter-3 Compare Low Trip ECAP_INPUT_SDFM1_FLT3_COMPARE_LOW = 66, //! SDFM-1 Filter-4 Compare Low Trip ECAP_INPUT_SDFM1_FLT4_COMPARE_LOW = 67, //! SDFM-1 Filter-1 Compare High Trip ECAP_INPUT_SDFM1_FLT1_COMPARE_HIGH = 80, //! SDFM-1 Filter-2 Compare High Trip ECAP_INPUT_SDFM1_FLT2_COMPARE_HIGH = 81, //! SDFM-1 Filter-3 Compare High Trip ECAP_INPUT_SDFM1_FLT3_COMPARE_HIGH = 82, //! SDFM-1 Filter-4 Compare High Trip ECAP_INPUT_SDFM1_FLT4_COMPARE_HIGH = 83, //! SDFM-1 Filter-1 Compare High Trip or Low Trip ECAP_INPUT_SDFM1_FLT1_COMPARE_HIGH_OR_LOW = 88, //! SDFM-1 Filter-2 Compare High Trip or Low Trip ECAP_INPUT_SDFM1_FLT2_COMPARE_HIGH_OR_LOW = 89, //! SDFM-1 Filter-3 Compare High Trip or Low Trip ECAP_INPUT_SDFM1_FLT3_COMPARE_HIGH_OR_LOW = 90, //! SDFM-1 Filter-4 Compare High Trip or Low Trip ECAP_INPUT_SDFM1_FLT4_COMPARE_HIGH_OR_LOW = 91, //! Compare Subsystem-1 Low Trip ECAP_INPUT_CMPSS1_CTRIP_LOW = 96, //! Compare Subsystem-2 Low Trip ECAP_INPUT_CMPSS2_CTRIP_LOW = 97, //! Compare Subsystem-3 Low Trip ECAP_INPUT_CMPSS3_CTRIP_LOW = 98, //! Compare Subsystem-4 Low Trip ECAP_INPUT_CMPSS4_CTRIP_LOW = 99, //! Compare Subsystem-5 Low Trip ECAP_INPUT_CMPSS5_CTRIP_LOW = 100, //! Compare Subsystem-6 Low Trip ECAP_INPUT_CMPSS6_CTRIP_LOW = 101, //! Compare Subsystem-7 Low Trip ECAP_INPUT_CMPSS7_CTRIP_LOW = 102, //! Compare Subsystem-1 High Trip ECAP_INPUT_CMPSS1_CTRIP_HIGH = 108, //! Compare Subsystem-2 High Trip ECAP_INPUT_CMPSS2_CTRIP_HIGH = 109, //! Compare Subsystem-3 High Trip ECAP_INPUT_CMPSS3_CTRIP_HIGH = 110, //! Compare Subsystem-4 High Trip ECAP_INPUT_CMPSS4_CTRIP_HIGH = 111, //! Compare Subsystem-5 High Trip ECAP_INPUT_CMPSS5_CTRIP_HIGH = 112, //! Compare Subsystem-6 High Trip ECAP_INPUT_CMPSS6_CTRIP_HIGH = 113, //! Compare Subsystem-7 High Trip ECAP_INPUT_CMPSS7_CTRIP_HIGH = 114, //! Compare Subsystem-1 High Trip or Low Trip ECAP_INPUT_CMPSS1_CTRIP_HIGH_OR_LOW = 120, //! Compare Subsystem-2 High Trip or Low Trip ECAP_INPUT_CMPSS2_CTRIP_HIGH_OR_LOW = 121, //! Compare Subsystem-3 High Trip or Low Trip ECAP_INPUT_CMPSS3_CTRIP_HIGH_OR_LOW = 122, //! Compare Subsystem-4 High Trip or Low Trip ECAP_INPUT_CMPSS4_CTRIP_HIGH_OR_LOW = 123, //! Compare Subsystem-5 High Trip or Low Trip ECAP_INPUT_CMPSS5_CTRIP_HIGH_OR_LOW = 124, //! Compare Subsystem-6 High Trip or Low Trip ECAP_INPUT_CMPSS6_CTRIP_HIGH_OR_LOW = 125, //! Compare Subsystem-7 High Trip or Low Trip ECAP_INPUT_CMPSS7_CTRIP_HIGH_OR_LOW = 126 }ECAP_InputCaptureSignals; //***************************************************************************** // //! \internal //! Checks eCAP base address. //! //! \param base specifies the eCAP module base address. //! //! This function determines if an eCAP module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Sets the input prescaler. //! //! \param base is the base address of the ECAP module. //! \param preScalerValue is the pre scaler value for ECAP input //! //! This function divides the ECAP input scaler. The pre scale value is //! doubled inside the module. For example a preScalerValue of 5 will divide //! the scaler by 10. Use a value of 1 to divide the pre scaler by 1. //! The value of preScalerValue should be less than //! \b ECAP_MAX_PRESCALER_VALUE. //! //! \return None. // //***************************************************************************** static inline void ECAP_setEventPrescaler(uint32_t base, uint16_t preScalerValue) { ; ; __eallow(); // write to PRESCALE bit (*((volatile uint16_t *)(base + 0x14U))) = (((*((volatile uint16_t *)(base + 0x14U))) & (~0x3E00U)) | (preScalerValue << 9U)); __edis(); } //***************************************************************************** // //! Sets the Capture event polarity. //! //! \param base is the base address of the ECAP module. //! \param event is the event number. //! \param polarity is the polarity of the event. //! //! This function sets the polarity of a given event. The value of event //! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to //! the four available events.For each event the polarity value determines the //! edge on which the capture is activated. For a rising edge use a polarity //! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of //! \b ECAP_EVNT_FALLING_EDGE. //! //! \return None. // //***************************************************************************** static inline void ECAP_setEventPolarity(uint32_t base, ECAP_Events event, ECAP_EventPolarity polarity) { uint16_t shift; ; shift = ((uint16_t)event) << 1U; __eallow(); // write to CAP1POL, CAP2POL, CAP3POL or CAP4POL (*((volatile uint16_t *)(base + 0x14U))) = ((*((volatile uint16_t *)(base + 0x14U))) & ~(1U << shift)) | ((uint16_t)polarity << shift); __edis(); } //***************************************************************************** // //! Sets the capture mode. //! //! \param base is the base address of the ECAP module. //! \param mode is the capture mode. //! \param event is the event number at which the counter stops or wraps. //! //! This function sets the eCAP module to a continuous or one-shot mode. //! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or //! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode //! respectively. //! //! The value of event determines the event number at which the counter stops //! (in one-shot mode) or the counter wraps (in continuous mode). The value of //! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding //! to the valid event numbers. //! //! \return None. // //***************************************************************************** static inline void ECAP_setCaptureMode(uint32_t base, ECAP_CaptureMode mode, ECAP_Events event) { ; __eallow(); // write to CONT/ONESHT (*((volatile uint16_t *)(base + 0x15U))) = (((*((volatile uint16_t *)(base + 0x15U))) & (~0x1U)) | (uint16_t)mode); // write to STOP_WRAP (*((volatile uint16_t *)(base + 0x15U))) = (((*((volatile uint16_t *)(base + 0x15U))) & (~0x6U)) | (((uint16_t)event) << 1U )); __edis(); } //***************************************************************************** // //! Re-arms the eCAP module. //! //! \param base is the base address of the ECAP module. //! //! This function re-arms the eCAP module. //! //! \return None. // //***************************************************************************** static inline void ECAP_reArm(uint32_t base) { ; __eallow(); // write to RE-ARM bit (*((volatile uint16_t *)(base + 0x15U))) |= 0x8U; __edis(); } //***************************************************************************** // //! Enables interrupt source. //! //! \param base is the base address of the ECAP module. //! \param intFlags is the interrupt source to be enabled. //! //! This function sets and enables eCAP interrupt source. The following are //! valid interrupt sources. //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates //! interrupt //! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates //! interrupt //! //! \return None. // //***************************************************************************** static inline void ECAP_enableInterrupt(uint32_t base, uint16_t intFlags) { ; ; __eallow(); // set bits in ECEINT register (*((volatile uint16_t *)(base + 0x16U))) |= intFlags; __edis(); } //***************************************************************************** // //! Disables interrupt source. //! //! \param base is the base address of the ECAP module. //! \param intFlags is the interrupt source to be disabled. //! //! This function clears and disables eCAP interrupt source. The following are //! valid interrupt sources. //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates //! interrupt //! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates //! interrupt //! //! \return None. // //***************************************************************************** static inline void ECAP_disableInterrupt(uint32_t base, uint16_t intFlags) { ; ; __eallow(); // clear bits in ECEINT register (*((volatile uint16_t *)(base + 0x16U))) &= ~intFlags; __edis(); } //***************************************************************************** // //! Returns the interrupt flag. //! //! \param base is the base address of the ECAP module. //! //! This function returns the eCAP interrupt flag. The following are valid //! interrupt sources corresponding to the eCAP interrupt flag. //! //! \return Returns the eCAP interrupt that has occurred. The following are //! valid return values. //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates //! interrupt //! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates //! interrupt //! //! \note - User can check if a combination of various interrupts have occurred //! by ORing the above return values. // //***************************************************************************** static inline uint16_t ECAP_getInterruptSource(uint32_t base) { ; // return contents of ECFLG register return((*((volatile uint16_t *)(base + 0x17U))) & 0xFEU); } //***************************************************************************** // //! Returns the Global interrupt flag. //! //! \param base is the base address of the ECAP module. //! //! This function returns the eCAP Global interrupt flag. //! //! \return Returns true if there is a global eCAP interrupt, false otherwise. // //***************************************************************************** static inline _Bool ECAP_getGlobalInterruptStatus(uint32_t base) { ; // return contents of Global interrupt bit return(((*((volatile uint16_t *)(base + 0x17U))) & 0x1U) == 0x1U); } //***************************************************************************** // //! Clears interrupt flag. //! //! \param base is the base address of the ECAP module. //! \param intFlags is the interrupt source. //! //! This function clears eCAP interrupt flags. The following are valid //! interrupt sources. //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates //! interrupt //! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates //! interrupt //! //! \return None. // //***************************************************************************** static inline void ECAP_clearInterrupt(uint32_t base, uint16_t intFlags) { ; ; // write to ECCLR register (*((volatile uint16_t *)(base + 0x18U))) |= intFlags; } //***************************************************************************** // //! Clears global interrupt flag //! //! \param base is the base address of the ECAP module. //! //! This function clears the global interrupt bit. //! //! \return None. // //***************************************************************************** static inline void ECAP_clearGlobalInterrupt(uint32_t base) { ; // write to INT bit (*((volatile uint16_t *)(base + 0x18U))) |= 0x1U; } //***************************************************************************** // //! Forces interrupt source. //! //! \param base is the base address of the ECAP module. //! \param intFlags is the interrupt source. //! //! This function forces and enables eCAP interrupt source. The following are //! valid interrupt sources. //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt //! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt //! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates //! interrupt //! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates //! interrupt //! //! \return None. // //***************************************************************************** static inline void ECAP_forceInterrupt(uint32_t base, uint16_t intFlags) { ; ; __eallow(); // write to ECFRC register (*((volatile uint16_t *)(base + 0x19U))) |= intFlags; __edis(); } //***************************************************************************** // //! Sets eCAP in Capture mode. //! //! \param base is the base address of the ECAP module. //! //! This function sets the eCAP module to operate in Capture mode. //! //! \return None. // //***************************************************************************** static inline void ECAP_enableCaptureMode(uint32_t base) { ; __eallow(); // clear CAP/APWM bit (*((volatile uint16_t *)(base + 0x15U))) &= ~0x200U; __edis(); } //***************************************************************************** // //! Sets eCAP in APWM mode. //! //! \param base is the base address of the ECAP module. //! //! This function sets the eCAP module to operate in APWM mode. //! //! \return None. // //***************************************************************************** static inline void ECAP_enableAPWMMode(uint32_t base) { ; __eallow(); // set CAP/APWM bit (*((volatile uint16_t *)(base + 0x15U))) |= 0x200U; __edis(); } //***************************************************************************** // //! Enables counter reset on an event. //! //! \param base is the base address of the ECAP module. //! \param event is the event number the time base gets reset. //! //! This function enables the base timer, TSCTR, to be reset on capture //! event provided by the variable event. Valid inputs for event are //! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. //! //! \return None. // //***************************************************************************** static inline void ECAP_enableCounterResetOnEvent(uint32_t base, ECAP_Events event) { ; __eallow(); // set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits (*((volatile uint16_t *)(base + 0x14U))) |= 1U << ((2U * (uint16_t)event) + 1U); __edis(); } //***************************************************************************** // //! Disables counter reset on events. //! //! \param base is the base address of the ECAP module. //! \param event is the event number the time base gets reset. //! //! This function disables the base timer, TSCTR, from being reset on capture //! event provided by the variable event. Valid inputs for event are 1 to 4. //! //! \return None. // //***************************************************************************** static inline void ECAP_disableCounterResetOnEvent(uint32_t base, ECAP_Events event) { ; ; __eallow(); // clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits (*((volatile uint16_t *)(base + 0x14U))) &= ~(1U << ((2U * (uint16_t)event) + 1U)); __edis(); } //***************************************************************************** // //! Enables time stamp capture. //! //! \param base is the base address of the ECAP module. //! //! This function enables time stamp count to be captured //! //! \return None. // //***************************************************************************** static inline void ECAP_enableTimeStampCapture(uint32_t base) { ; __eallow(); // set CAPLDEN bit (*((volatile uint16_t *)(base + 0x14U))) |= 0x100U; __edis(); } //***************************************************************************** // //! Disables time stamp capture. //! //! \param base is the base address of the ECAP module. //! //! This function disables time stamp count to be captured //! //! \return None. // //***************************************************************************** static inline void ECAP_disableTimeStampCapture(uint32_t base) { ; __eallow(); // clear CAPLDEN bit (*((volatile uint16_t *)(base + 0x14U))) &= ~0x100U; __edis(); } //***************************************************************************** // //! Sets a phase shift value count. //! //! \param base is the base address of the ECAP module. //! \param shiftCount is the phase shift value. //! //! This function writes a phase shift value to be loaded into the main time //! stamp counter. //! //! \return None. // //***************************************************************************** static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount) { ; // write to CTRPHS (*((volatile uint32_t *)(base + 0x2U))) = shiftCount; } //***************************************************************************** // //! Enable counter loading with phase shift value. //! //! \param base is the base address of the ECAP module. //! //! This function enables loading of the counter with the value present in the //! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. //! //! \return None. // //***************************************************************************** static inline void ECAP_enableLoadCounter(uint32_t base) { ; __eallow(); // write to SYNCI_EN (*((volatile uint16_t *)(base + 0x15U))) |= 0x20U; __edis(); } //***************************************************************************** // //! Disable counter loading with phase shift value. //! //! \param base is the base address of the ECAP module. //! //! This function disables loading of the counter with the value present in the //! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. //! //! \return None. // //***************************************************************************** static inline void ECAP_disableLoadCounter(uint32_t base) { ; __eallow(); // write to SYNCI_EN (*((volatile uint16_t *)(base + 0x15U))) &= ~0x20U; __edis(); } //***************************************************************************** // //! Load time stamp counter //! //! \param base is the base address of the ECAP module. //! //! This function forces the value in the phase shift counter register to be //! loaded into Time stamp counter register. //! Make sure to enable loading of Time stamp counter by calling //! ECAP_enableLoadCounter() function before calling this function. //! //! \return None. // //***************************************************************************** static inline void ECAP_loadCounter(uint32_t base) { ; __eallow(); // write to SWSYNC (*((volatile uint16_t *)(base + 0x15U))) |= 0x100U; __edis(); } //***************************************************************************** // //! Configures Sync out signal mode. //! //! \param base is the base address of the ECAP module. //! \param mode is the sync out mode. //! //! This function sets the sync out mode. Valid parameters for mode are: //! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event. //! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period. //! - ECAP_SYNC_OUT_DISABLED - Disable sync out. //! //! \return None. // //***************************************************************************** static inline void ECAP_setSyncOutMode(uint32_t base, ECAP_SyncOutMode mode) { ; __eallow(); // write to SYNCO_SEL (*((volatile uint16_t *)(base + 0x15U))) = (((*((volatile uint16_t *)(base + 0x15U))) & (~0xC0U)) | (uint16_t)mode); __edis(); } //***************************************************************************** // //! Stops Time stamp counter. //! //! \param base is the base address of the ECAP module. //! //! This function stops the time stamp counter. //! //! \return None. // //***************************************************************************** static inline void ECAP_stopCounter(uint32_t base) { ; __eallow(); // clear TSCTR (*((volatile uint16_t *)(base + 0x15U))) &= ~0x10U; __edis(); } //***************************************************************************** // //! Starts Time stamp counter. //! //! \param base is the base address of the ECAP module. //! //! This function starts the time stamp counter. //! //! \return None. // //***************************************************************************** static inline void ECAP_startCounter(uint32_t base) { ; __eallow(); // set TSCTR (*((volatile uint16_t *)(base + 0x15U))) |= 0x10U; __edis(); } //***************************************************************************** // //! Set eCAP APWM polarity. //! //! \param base is the base address of the ECAP module. //! \param polarity is the polarity of APWM //! //! This function sets the polarity of the eCAP in APWM mode. Valid inputs for //! polarity are: //! - ECAP_APWM_ACTIVE_HIGH - For active high. //! - ECAP_APWM_ACTIVE_LOW - For active low. //! //! \return None. // //***************************************************************************** static inline void ECAP_setAPWMPolarity(uint32_t base, ECAP_APWMPolarity polarity) { ; __eallow(); (*((volatile uint16_t *)(base + 0x15U))) = (((*((volatile uint16_t *)(base + 0x15U))) & ~0x400U) | (uint16_t)polarity); __edis(); } //***************************************************************************** // //! Set eCAP APWM period. //! //! \param base is the base address of the ECAP module. //! \param periodCount is the period count for APWM. //! //! This function sets the period count of the APWM waveform. //! periodCount takes the actual count which is written to the register. The //! user is responsible for converting the desired frequency or time into //! the period count. //! //! \return None. // //***************************************************************************** static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount) { ; // write to CAP1 (*((volatile uint32_t *)(base + 0x4U))) = periodCount; } //***************************************************************************** // //! Set eCAP APWM on or off time count. //! //! \param base is the base address of the ECAP module. //! \param compareCount is the on or off count for APWM. //! //! This function sets the on or off time count of the APWM waveform depending //! on the polarity of the output. If the output , as set by //! ECAP_setAPWMPolarity(), is active high then compareCount determines the on //! time. If the output is active low then compareCount determines the off //! time. compareCount takes the actual count which is written to the register. //! The user is responsible for converting the desired frequency or time into //! the appropriate count value. //! //! \return None. // //***************************************************************************** static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount) { ; // write to CAP2 (*((volatile uint32_t *)(base + 0x6U))) = compareCount; } //***************************************************************************** // //! Load eCAP APWM shadow period. //! //! \param base is the base address of the ECAP module. //! \param periodCount is the shadow period count for APWM. //! //! This function sets the shadow period count of the APWM waveform. //! periodCount takes the actual count which is written to the register. The //! user is responsible for converting the desired frequency or time into //! the period count. //! //! \return None. // //***************************************************************************** static inline void ECAP_setAPWMShadowPeriod(uint32_t base, uint32_t periodCount) { ; // write to CAP3 (*((volatile uint32_t *)(base + 0x8U))) = periodCount; } //***************************************************************************** // //! Set eCAP APWM shadow on or off time count. //! //! \param base is the base address of the ECAP module. //! \param compareCount is the on or off count for APWM. //! //! This function sets the shadow on or off time count of the APWM waveform //! depending on the polarity of the output. If the output , as set by //! ECAP_setAPWMPolarity() , is active high then compareCount determines the //! on time. If the output is active low then compareCount determines the off //! time. compareCount takes the actual count which is written to the register. //! The user is responsible for converting the desired frequency or time into //! the appropriate count value. //! //! \return None. // //***************************************************************************** static inline void ECAP_setAPWMShadowCompare(uint32_t base, uint32_t compareCount) { ; // write to CAP4 (*((volatile uint32_t *)(base + 0xAU))) = compareCount; } //***************************************************************************** // //! Returns the time base counter value. //! //! \param base is the base address of the ECAP module. //! //! This function returns the time base counter value. //! //! \return Returns the time base counter value. // //***************************************************************************** static uint32_t ECAP_getTimeBaseCounter(uint32_t base) { ; // Read the Time base counter value return((*((volatile uint32_t *)(base + 0x0U)))); } //***************************************************************************** // //! Returns event time stamp. //! //! \param base is the base address of the ECAP module. //! \param event is the event number. //! //! This function returns the current time stamp count of the given event. //! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4. //! //! \return Event time stamp value or 0 if \e event is invalid. // //***************************************************************************** static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event) { uint32_t count; ; switch(event) { case ECAP_EVENT_1: // read CAP1 register count = (*((volatile uint32_t *)(base + 0x4U))); break; case ECAP_EVENT_2: // read CAP2 register count = (*((volatile uint32_t *)(base + 0x6U))); break; case ECAP_EVENT_3: // read CAP3 register count = (*((volatile uint32_t *)(base + 0x8U))); break; case ECAP_EVENT_4: // read CAP4 register count = (*((volatile uint32_t *)(base + 0xAU))); break; default: // invalid event parameter count = 0U; break; } return(count); } //***************************************************************************** // //! Select eCAP input. //! //! \param base is the base address of the ECAP module. //! \param input is the eCAP input signal. //! //! This function selects the eCAP input signal. //! //! //! \return None. // //***************************************************************************** static inline void ECAP_selectECAPInput(uint32_t base, ECAP_InputCaptureSignals input) { ; __eallow(); // write to ECCTL0 (*((volatile uint16_t *)(base + 0x12U))) = (((*((volatile uint16_t *)(base + 0x12U))) & ~0x7FU) | (uint16_t)input); __edis(); } //***************************************************************************** // //! Resets eCAP counters and flags. //! //! \param base is the base address of the ECAP module. //! //! This function resets the main counter (TSCTR register), event filter, //! modulo counter, capture events and counter overflow flags //! //! \return None. // //***************************************************************************** static inline void ECAP_resetCounters(uint32_t base) { ; __eallow(); // write to ECCTL2 (*((volatile uint16_t *)(base + 0x15U))) |= 0x800U; __edis(); } //***************************************************************************** // //! Sets the eCAP DMA source. //! //! \param base is the base address of the ECAP module. //! \param event is the eCAP event for the DMA //! //! This function sets the eCAP event source for the DMA trigger. //! //! \return None. // //***************************************************************************** static inline void ECAP_setDMASource(uint32_t base, ECAP_Events event) { ; __eallow(); // write to ECCTL2 (*((volatile uint16_t *)(base + 0x15U))) = (((*((volatile uint16_t *)(base + 0x15U))) & ~0x3000U) | ((uint16_t)event << 12U)); __edis(); } //***************************************************************************** // //! Return the Modulo counter status. //! //! \param base is the base address of the ECAP module. //! //! This function returns the modulo counter status, indicating which register //! gets loaded on the next capture event. //! //! \return Returns an \b ECAP_EVENT_n value indicating that CAPn is the //! register to be loaded on the next event. // //***************************************************************************** static inline ECAP_Events ECAP_getModuloCounterStatus(uint32_t base) { ; // Read MODCNTRSTS bit return((ECAP_Events)(((*((volatile uint16_t *)(base + 0x15U))) & 0xC000U) >> 14U)); } //***************************************************************************** // //! Configures emulation mode. //! //! \param base is the base address of the ECAP module. //! \param mode is the emulation mode. //! //! This function configures the eCAP counter, TSCTR, to the desired emulation //! mode when emulation suspension occurs. Valid inputs for mode are: //! - ECAP_EMULATION_STOP - Counter is stopped immediately. //! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0. //! - ECAP_EMULATION_FREE_RUN - Counter is not affected. //! //! \return None. // //***************************************************************************** extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //############################################################################# // // FILE: epwm.h // // TITLE: C28x EPWM Driver // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup epwm_api ePWM //! @{ // //***************************************************************************** //***************************************************************************** // the includes //***************************************************************************** //########################################################################### // // FILE: hw_epwm.h // // TITLE: Definitions for the EPWM registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the EPWM register offsets // //***************************************************************************** // Register // Register 2 // Register // Register 2 // Register // Event Source Select Register // Register // Register // Register // Register // Register For Output A // Control Register For Output A // Register For Output B // Control Register For Output B // Force Register // S/W Force Register // Edge Delay High Resolution // Mirror Register // Edge Delay Count Register // Register 2 // Register // Select Register // Register // Digital Compare A // Digital Compare B // Register // Register // Register // Pre-Scale Register // Register // Initialization Control Register // Initialization Register // Register // Register // Register // Control Register // Control Register // Register // Counter Register // Register // Counter Register // Capture Register // Select // Select // Select // Select // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the TBCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TBCTL2 register // //***************************************************************************** // SYNC Event //***************************************************************************** // // The following are defines for the bit fields in the TBSTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPCTL register // //***************************************************************************** // Operating Mode // Operating Mode // Full Status // Full Status //***************************************************************************** // // The following are defines for the bit fields in the CMPCTL2 register // //***************************************************************************** // Mode // Mode //***************************************************************************** // // The following are defines for the bit fields in the DBCTL register // //***************************************************************************** // Control // Control //***************************************************************************** // // The following are defines for the bit fields in the DBCTL2 register // //***************************************************************************** // Select //***************************************************************************** // // The following are defines for the bit fields in the AQCTL register // //***************************************************************************** // Select // Select // Mode // Mode //***************************************************************************** // // The following are defines for the bit fields in the AQTSRCSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the VCAPCTL register // //***************************************************************************** // Enable // Select //***************************************************************************** // // The following are defines for the bit fields in the VCNTCFG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GLDCTL register // //***************************************************************************** // event control // Pulse Selection // bit // Select Register // Register //***************************************************************************** // // The following are defines for the bit fields in the GLDCFG register // //***************************************************************************** // configuration for TBPRD:TBPRDHR // configuration for CMPA:CMPAHR // configuration for CMPB:CMPBHR // configuration for CMPC // configuration for CMPD // configuration for DBRED:DBREDHR // configuration for DBFED:DBFEDHR // configuration for DBCTL // configuration for AQCTLA/A2 // configuration for AQCTLB/B2 // configuration for AQCSFRC //***************************************************************************** // // The following are defines for the bit fields in the EPWMXLINK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the EPWMREV register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the AQCTLA register // //***************************************************************************** // Down // Down //***************************************************************************** // // The following are defines for the bit fields in the AQCTLA2 register // //***************************************************************************** // T1 in UP-Count // T1 in DOWN-Count // T2 in UP-Count // T2 in DOWN-Count //***************************************************************************** // // The following are defines for the bit fields in the AQCTLB register // //***************************************************************************** // Down // Down //***************************************************************************** // // The following are defines for the bit fields in the AQCTLB2 register // //***************************************************************************** // T1 in UP-Count // T1 in DOWN-Count // T2 in UP-Count // T2 in DOWN-Count //***************************************************************************** // // The following are defines for the bit fields in the AQSFRC register // //***************************************************************************** // A Invoked // B Invoked //***************************************************************************** // // The following are defines for the bit fields in the AQCSFRC register // //***************************************************************************** // output A // output B //***************************************************************************** // // The following are defines for the bit fields in the DBRED register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DBFED register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TBPHS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GLDCTL2 register // //***************************************************************************** // shot mode // shot mode //***************************************************************************** // // The following are defines for the bit fields in the TZSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TZDCSEL register // //***************************************************************************** // Event 1 // Event 2 // Event 1 // Event 2 //***************************************************************************** // // The following are defines for the bit fields in the TZCTL register // //***************************************************************************** // EPWMxA // EPWMxB //***************************************************************************** // // The following are defines for the bit fields in the TZCTL2 register // //***************************************************************************** // Count direction is UP // Count direction is DOWN // Count direction is UP // Count direction is DOWN //***************************************************************************** // // The following are defines for the bit fields in the TZCTLDCA register // //***************************************************************************** // while Count direction is UP // while Count direction is DOWN // while Count direction is UP // while Count direction is DOWN //***************************************************************************** // // The following are defines for the bit fields in the TZCTLDCB register // //***************************************************************************** // while Count direction is UP // while Count direction is DOWN // while Count direction is UP // while Count direction is DOWN //***************************************************************************** // // The following are defines for the bit fields in the TZEINT register // //***************************************************************************** // Enable // Enable // Enable // Enable // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the TZFLG register // //***************************************************************************** // Flag // Flag // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the TZCBCFLG register // //***************************************************************************** // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Digital Compare Output A Event 2 // Digital Compare Output B Event 2 //***************************************************************************** // // The following are defines for the bit fields in the TZOSTFLG register // //***************************************************************************** // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Digital Compare Output A Event 1 // Digital Compare Output B Event 1 //***************************************************************************** // // The following are defines for the bit fields in the TZCLR register // //***************************************************************************** // Latch //***************************************************************************** // // The following are defines for the bit fields in the TZCBCCLR register // //***************************************************************************** // (CBC1) Trip Latch // (CBC2) Trip Latch // (CBC3) Trip Latch // (CBC4) Trip Latch // (CBC5) Trip Latch // (CBC6) Trip Latch // selected for CBC // selected for CBC //***************************************************************************** // // The following are defines for the bit fields in the TZOSTCLR register // //***************************************************************************** // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // selected for OST // selected for OST //***************************************************************************** // // The following are defines for the bit fields in the TZFRC register // //***************************************************************************** // Cycle Event // Event // 1 // 2 // 1 // 2 //***************************************************************************** // // The following are defines for the bit fields in the ETSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETPS register // //***************************************************************************** // Bits // Selection Bits //***************************************************************************** // // The following are defines for the bit fields in the ETFLG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETCLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETFRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETINTPS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETSOCPS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETCNTINITCTL register // //***************************************************************************** // Initialization Force // Initialization Force // Initialization Force // Initialization Enable // Initialization Enable // Initialization Enable //***************************************************************************** // // The following are defines for the bit fields in the ETCNTINIT register // //***************************************************************************** // Initialization Bits // Initialization Bits // Initialization Bits //***************************************************************************** // // The following are defines for the bit fields in the DCTRIPSEL register // //***************************************************************************** // Input Select // Input Select // Input Select // Input Select //***************************************************************************** // // The following are defines for the bit fields in the DCACTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCBCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCFCTL register // //***************************************************************************** // Select // Capture Alignment //***************************************************************************** // // The following are defines for the bit fields in the DCCAPCTL register // //***************************************************************************** // Capture Event // Clear Flag //***************************************************************************** // // The following are defines for the bit fields in the DCAHTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the DCALTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the DCBHTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the DCBLTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the EPWMLOCK register // //***************************************************************************** // Lock // Lock // Time Base Module //***************************************************************************** // //! Values that can be passed to EPWM_setEmulationMode() as the //! \e emulationMode parameter. // //***************************************************************************** typedef enum { //! Stop after next Time Base counter increment or decrement. EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0, //! Stop when counter completes whole cycle EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1, //! Free run EPWM_EMULATION_FREE_RUN = 2 }EPWM_EmulationMode; //***************************************************************************** // //! Values that can be passed to EPWM_setCountModeAfterSync() as the //! \e mode parameter. // //***************************************************************************** typedef enum { EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0, //!< Count down after sync event EPWM_COUNT_MODE_UP_AFTER_SYNC = 1 //!< Count up after sync event }EPWM_SyncCountMode; //***************************************************************************** // //! Values that can be passed to EPWM_setClockPrescaler() as the //! \e prescaler parameter. // //***************************************************************************** typedef enum { EPWM_CLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 EPWM_CLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 EPWM_CLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 EPWM_CLOCK_DIVIDER_8 = 3, //!< Divide clock by 8 EPWM_CLOCK_DIVIDER_16 = 4, //!< Divide clock by 16 EPWM_CLOCK_DIVIDER_32 = 5, //!< Divide clock by 32 EPWM_CLOCK_DIVIDER_64 = 6, //!< Divide clock by 64 EPWM_CLOCK_DIVIDER_128 = 7 //!< Divide clock by 128 }EPWM_ClockDivider; //***************************************************************************** // //! Values that can be passed to EPWM_setClockPrescaler() as the //! \e highSpeedPrescaler parameter. // //***************************************************************************** typedef enum { EPWM_HSCLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 EPWM_HSCLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 EPWM_HSCLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 EPWM_HSCLOCK_DIVIDER_6 = 3, //!< Divide clock by 6 EPWM_HSCLOCK_DIVIDER_8 = 4, //!< Divide clock by 8 EPWM_HSCLOCK_DIVIDER_10 = 5, //!< Divide clock by 10 EPWM_HSCLOCK_DIVIDER_12 = 6, //!< Divide clock by 12 EPWM_HSCLOCK_DIVIDER_14 = 7 //!< Divide clock by 14 }EPWM_HSClockDivider; //***************************************************************************** // //! Values that can be passed to EPWM_setSyncOutPulseMode() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! sync pulse is generated by software EPWM_SYNC_OUT_PULSE_ON_SOFTWARE = 0, //! sync pulse is passed from EPWMxSYNCIN EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN = 0, //! sync pulse is generated when time base counter equals zero EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO = 1, //! sync pulse is generated when time base counter equals compare B value. EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B = 2, //! sync pulse is disabled EPWM_SYNC_OUT_PULSE_DISABLED = 4, //! sync pulse is generated when time base counter equals compare D value. EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C = 5, //! sync pulse is disabled. EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D = 6 }EPWM_SyncOutPulseMode; //***************************************************************************** // //! Values that can be passed to EPWM_setPeriodLoadMode() as the //! \e loadMode parameter. // //***************************************************************************** typedef enum { //! PWM Period register access is through shadow register EPWM_PERIOD_SHADOW_LOAD = 0, //! PWM Period register access is directly EPWM_PERIOD_DIRECT_LOAD = 1 }EPWM_PeriodLoadMode; //***************************************************************************** // //! Values that can be passed to EPWM_setTimeBaseCounterMode() as the //! \e counterMode parameter. // //***************************************************************************** typedef enum { EPWM_COUNTER_MODE_UP = 0, //!< Up - count mode. EPWM_COUNTER_MODE_DOWN = 1, //!< Down - count mode. EPWM_COUNTER_MODE_UP_DOWN = 2, //!< Up - down - count mode. EPWM_COUNTER_MODE_STOP_FREEZE = 3 //!< Stop - Freeze counter. }EPWM_TimeBaseCountMode; //***************************************************************************** // //! Values that can be passed to EPWM_selectPeriodLoadEvent() as the //! \e shadowLoadMode parameter. // //***************************************************************************** typedef enum { //! shadow to active load occurs when time base counter reaches 0. EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0, //! shadow to active load occurs when time base counter reaches 0 and a //! SYNC occurs EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1, //! shadow to active load occurs only when a SYNC occurs EPWM_SHADOW_LOAD_MODE_SYNC = 2 }EPWM_PeriodShadowLoadMode; //***************************************************************************** // // Values that can be returned by the EPWM_getTimeBaseCounterDirection() // //***************************************************************************** //! Time base counter is counting up //! //! Time base counter is counting down //! //***************************************************************************** // //! Values that can be passed to EPWM_setupEPWMLinks() as the \e epwmLink //! parameter. // //***************************************************************************** typedef enum { EPWM_LINK_WITH_EPWM_1 = 0, //!< link current ePWM with ePWM1 EPWM_LINK_WITH_EPWM_2 = 1, //!< link current ePWM with ePWM2 EPWM_LINK_WITH_EPWM_3 = 2, //!< link current ePWM with ePWM3 EPWM_LINK_WITH_EPWM_4 = 3, //!< link current ePWM with ePWM4 EPWM_LINK_WITH_EPWM_5 = 4, //!< link current ePWM with ePWM5 EPWM_LINK_WITH_EPWM_6 = 5, //!< link current ePWM with ePWM6 EPWM_LINK_WITH_EPWM_7 = 6, //!< link current ePWM with ePWM7 EPWM_LINK_WITH_EPWM_8 = 7 //!< link current ePWM with ePWM8 }EPWM_CurrentLink; //***************************************************************************** // //! Values that can be passed to EPWM_setupEPWMLinks() as the \e linkComp //! parameter. // //***************************************************************************** typedef enum { EPWM_LINK_TBPRD = 0, //!< link TBPRD:TBPRDHR registers EPWM_LINK_COMP_A = 4, //!< link COMPA registers EPWM_LINK_COMP_B = 8, //!< link COMPB registers EPWM_LINK_COMP_C = 12, //!< link COMPC registers EPWM_LINK_COMP_D = 16, //!< link COMPD registers EPWM_LINK_GLDCTL2 = 28 //!< link GLDCTL2 registers }EPWM_LinkComponent; // Counter Compare Module //***************************************************************************** // //! Values that can be passed to the EPWM_getCounterCompareShadowStatus(), //! EPWM_setCounterCompareValue(), EPWM_setCounterCompareShadowLoadMode(), //! EPWM_disableCounterCompareShadowLoadMode() //! as the \e compModule parameter. // //***************************************************************************** typedef enum { EPWM_COUNTER_COMPARE_A = 0, //!< counter compare A EPWM_COUNTER_COMPARE_B = 2, //!< counter compare B EPWM_COUNTER_COMPARE_C = 5, //!< counter compare C EPWM_COUNTER_COMPARE_D = 7 //!< counter compare D }EPWM_CounterCompareModule; //***************************************************************************** // //! Values that can be passed to EPWM_setCounterCompareShadowLoadMode() as the //! \e loadMode parameter. // //***************************************************************************** typedef enum { //! load when counter equals zero EPWM_COMP_LOAD_ON_CNTR_ZERO = 0, //! load when counter equals period EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1, //! load when counter equals zero or period EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2, //! Freeze shadow to active load EPWM_COMP_LOAD_FREEZE = 3, //! load when counter equals zero EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4, //! load when counter equals period EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5, //! load when counter equals zero or period EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, //! load on sync only EPWM_COMP_LOAD_ON_SYNC_ONLY = 8 }EPWM_CounterCompareLoadMode; // Action Qualifier Module //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() and //! EPWM_disableActionQualifierShadowLoadMode() as the \e aqModule parameter. // //***************************************************************************** typedef enum { EPWM_ACTION_QUALIFIER_A = 0, //!< Action Qualifier A EPWM_ACTION_QUALIFIER_B = 2 //!< Action Qualifier B }EPWM_ActionQualifierModule; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() as the //! \e loadMode parameter. // //***************************************************************************** typedef enum { //! load when counter equals zero EPWM_AQ_LOAD_ON_CNTR_ZERO = 0, //! load when counter equals period EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1, //! load when counter equals zero or period EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2, //! Freeze shadow to active load EPWM_AQ_LOAD_FREEZE = 3, //! load on sync or when counter equals zero EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4, //! load on sync or when counter equals period EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5, //! load on sync or when counter equals zero or period EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, //! load on sync only EPWM_AQ_LOAD_ON_SYNC_ONLY = 8 }EPWM_ActionQualifierLoadMode; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierT1TriggerSource() and //! EPWM_setActionQualifierT2TriggerSource() as the \e trigger parameter. // //***************************************************************************** typedef enum { EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0, //!< Digital compare event A 1 EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1, //!< Digital compare event A 2 EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2, //!< Digital compare event B 1 EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3, //!< Digital compare event B 2 EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4, //!< Trip zone 1 EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5, //!< Trip zone 2 EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6, //!< Trip zone 3 EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7 //!< ePWM sync }EPWM_ActionQualifierTriggerSource; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierAction() as the \e //! event parameter. // //***************************************************************************** typedef enum { //! Time base counter equals zero EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0, //! Time base counter equals period EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2, //! Time base counter up equals COMPA EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4, //! Time base counter down equals COMPA EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6, //! Time base counter up equals COMPB EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8, //! Time base counter down equals COMPB EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10, //! T1 event on count up EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1, //! T1 event on count down EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3, //! T2 event on count up EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5, //! T2 event on count down EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7 }EPWM_ActionQualifierOutputEvent; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierSWAction(), //! EPWM_setActionQualifierAction() as the \e outPut parameter. // //***************************************************************************** typedef enum { EPWM_AQ_OUTPUT_NO_CHANGE = 0, //!< No change in the output pins EPWM_AQ_OUTPUT_LOW = 1, //!< Set output pins to low EPWM_AQ_OUTPUT_HIGH = 2, //!< Set output pins to High EPWM_AQ_OUTPUT_TOGGLE = 3 //!< Toggle the output pins }EPWM_ActionQualifierOutput; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierContSWForceAction() //! as the \e outPut parameter. // //***************************************************************************** typedef enum { EPWM_AQ_SW_DISABLED = 0, //!< Software forcing disabled EPWM_AQ_SW_OUTPUT_LOW = 1, //!< Set output pins to low EPWM_AQ_SW_OUTPUT_HIGH = 2 //!< Set output pins to High }EPWM_ActionQualifierSWOutput; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierActionComplete() //! as the \e action parameter. // //***************************************************************************** typedef enum { //! Time base counter equals zero and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0, //! Time base counter equals zero and set output pins to low EPWM_AQ_OUTPUT_LOW_ZERO = 0x1, //! Time base counter equals zero and set output pins to high EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2, //! Time base counter equals zero and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3, //! Time base counter equals period and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0, //! Time base counter equals period and set output pins to low EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4, //! Time base counter equals period and set output pins to high EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8, //! Time base counter equals period and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC, //! Time base counter up equals COMPA and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00, //! Time base counter up equals COMPA and set output pins to low EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10, //! Time base counter up equals COMPA and set output pins to high EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20, //! Time base counter up equals COMPA and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30, //! Time base counter down equals COMPA and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00, //! Time base counter down equals COMPA and set output pins to low EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40, //! Time base counter down equals COMPA and set output pins to high EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80, //! Time base counter down equals COMPA and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0, //! Time base counter up equals COMPB and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000, //! Time base counter up equals COMPB and set output pins to low EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100, //! Time base counter up equals COMPB and set output pins to high EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200, //! Time base counter up equals COMPB and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300, //! Time base counter down equals COMPB and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000, //! Time base counter down equals COMPB and set output pins to low EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400, //! Time base counter down equals COMPB and set output pins to high EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800, //! Time base counter down equals COMPB and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00 } EPWM_ActionQualifierEventAction; //***************************************************************************** // //! Values that can be passed to //! EPWM_setAdditionalActionQualifierActionComplete() as the \e action //! parameter. // //***************************************************************************** typedef enum { //! T1 event on count up and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0, //! T1 event on count up and set output pins to low EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1, //! T1 event on count up and set output pins to high EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2, //! T1 event on count up and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3, //! T1 event on count down and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0, //! T1 event on count down and set output pins to low EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4, //! T1 event on count down and set output pins to high EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8, //! T1 event on count down and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC, //! T2 event on count up and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00, //! T2 event on count up and set output pins to low EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10, //! T2 event on count up and set output pins to high EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20, //! T2 event on count up and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30, //! T2 event on count down and no change in the output pins EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00, //! T2 event on count down and set output pins to low EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40, //! T2 event on count down and set output pins to high EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80, //! T2 event on count down and toggle the output pins EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0 } EPWM_AdditionalActionQualifierEventAction; //***************************************************************************** // //! Values that can be passed to EPWM_forceActionQualifierSWAction(), //! EPWM_setActionQualifierSWAction(), EPWM_setActionQualifierAction() //! EPWM_setActionQualifierContSWForceAction() as the \e epwmOutput parameter. // //***************************************************************************** typedef enum { EPWM_AQ_OUTPUT_A = 0, //!< ePWMxA output EPWM_AQ_OUTPUT_B = 2 //!< ePWMxB output }EPWM_ActionQualifierOutputModule; //***************************************************************************** // //! Values that can be passed to EPWM_setActionQualifierContSWForceShadowMode() //! as the \e mode parameter. // //***************************************************************************** typedef enum { //! shadow mode load when counter equals zero EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0, //! shadow mode load when counter equals period EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1, //! shadow mode load when counter equals zero or period EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2, //! No shadow load mode. Immediate mode only. EPWM_AQ_SW_IMMEDIATE_LOAD = 3 }EPWM_ActionQualifierContForce; //***************************************************************************** // //! Values that can be passed to EPWM_setDeadBandOutputSwapMode() //! as the \e output parameter. // //***************************************************************************** typedef enum { EPWM_DB_OUTPUT_A = 0, //!< DB output is ePWMA EPWM_DB_OUTPUT_B = 1 //!< DB output is ePWMB }EPWM_DeadBandOutput; //***************************************************************************** // //! Values that can be passed to EPWM_setDeadBandDelayPolarity(), //! EPWM_setDeadBandDelayMode() as the \e delayMode parameter. // //***************************************************************************** typedef enum { EPWM_DB_RED = 1, //!< DB RED (Rising Edge Delay) mode EPWM_DB_FED = 0 //!< DB FED (Falling Edge Delay) mode }EPWM_DeadBandDelayMode; //***************************************************************************** // //! Values that can be passed to EPWM_setDeadBandDelayPolarity as the //! \e polarity parameter. // //***************************************************************************** typedef enum { EPWM_DB_POLARITY_ACTIVE_HIGH = 0, //!< DB polarity is not inverted EPWM_DB_POLARITY_ACTIVE_LOW = 1 //!< DB polarity is inverted }EPWM_DeadBandPolarity; //***************************************************************************** // // Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(), // EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter. // //***************************************************************************** //! Input signal is ePWMA //! //! Input signal is ePWMA //! //! Input signal is the output of Rising Edge delay //! //***************************************************************************** // //! Values that can be passed to EPWM_setDeadBandControlShadowLoadMode() as //! the \e loadMode parameter. // //***************************************************************************** typedef enum { //! load when counter equals zero EPWM_DB_LOAD_ON_CNTR_ZERO = 0, //! load when counter equals period EPWM_DB_LOAD_ON_CNTR_PERIOD = 1, //! load when counter equals zero or period EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2, //! Freeze shadow to active load EPWM_DB_LOAD_FREEZE = 3 }EPWM_DeadBandControlLoadMode; //***************************************************************************** // //! Values that can be passed to EPWM_setRisingEdgeDelayCountShadowLoadMode() //! as the \e loadMode parameter. // //***************************************************************************** typedef enum { //! load when counter equals zero EPWM_RED_LOAD_ON_CNTR_ZERO = 0, //! load when counter equals period EPWM_RED_LOAD_ON_CNTR_PERIOD = 1, //! load when counter equals zero or period EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2, //! Freeze shadow to active load EPWM_RED_LOAD_FREEZE = 3 }EPWM_RisingEdgeDelayLoadMode; //***************************************************************************** // //! Values that can be passed to EPWM_setFallingEdgeDelayCountShadowLoadMode() //! as the \e loadMode parameter. // //***************************************************************************** typedef enum { //! load when counter equals zero EPWM_FED_LOAD_ON_CNTR_ZERO = 0, //! load when counter equals period EPWM_FED_LOAD_ON_CNTR_PERIOD = 1, //! load when counter equals zero or period EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2, //! Freeze shadow to active load EPWM_FED_LOAD_FREEZE = 3 }EPWM_FallingEdgeDelayLoadMode; //***************************************************************************** // //! Values that can be passed to EPWM_setDeadBandCounterClock() as the //! \e clockMode parameter. // //***************************************************************************** typedef enum { //! Dead band counter runs at TBCLK rate EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0, //! Dead band counter runs at 2*TBCLK rate EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1 }EPWM_DeadBandClockMode; // Trip Zone //***************************************************************************** // // Values that can be passed to EPWM_enableTripZoneSignals() and // EPWM_disableTripZoneSignals() as the tzSignal parameter. // //***************************************************************************** //! TZ1 Cycle By Cycle //! //! TZ2 Cycle By Cycle //! //! TZ3 Cycle By Cycle //! //! TZ4 Cycle By Cycle //! //! TZ5 Cycle By Cycle //! //! TZ6 Cycle By Cycle //! //! DCAEVT2 Cycle By Cycle //! //! DCBEVT2 Cycle By Cycle //! //! One-shot TZ1 //! //! One-shot TZ2 //! //! One-shot TZ3 //! //! One-shot TZ4 //! //! One-shot TZ5 //! //! One-shot TZ6 //! //! One-shot DCAEVT1 //! //! One-shot DCBEVT1 //! //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() //! as the \e dcType parameter. // //***************************************************************************** typedef enum { EPWM_TZ_DC_OUTPUT_A1 = 0, //!< Digital Compare output 1 A EPWM_TZ_DC_OUTPUT_A2 = 3, //!< Digital Compare output 2 A EPWM_TZ_DC_OUTPUT_B1 = 6, //!< Digital Compare output 1 B EPWM_TZ_DC_OUTPUT_B2 = 9 //!< Digital Compare output 2 B }EPWM_TripZoneDigitalCompareOutput; //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() //! as the \e dcEvent parameter. // //***************************************************************************** typedef enum { EPWM_TZ_EVENT_DC_DISABLED = 0, //!< Event is disabled EPWM_TZ_EVENT_DCXH_LOW = 1, //!< Event when DCxH low EPWM_TZ_EVENT_DCXH_HIGH = 2, //!< Event when DCxH high EPWM_TZ_EVENT_DCXL_LOW = 3, //!< Event when DCxL low EPWM_TZ_EVENT_DCXL_HIGH = 4, //!< Event when DCxL high EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5 //!< Event when DCxL high DCxH low }EPWM_TripZoneDigitalCompareOutputEvent; //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneAction() as the \e tzEvent //! parameter. // //***************************************************************************** typedef enum { EPWM_TZ_ACTION_EVENT_TZA = 0, //!< TZ1 - TZ6, DCAEVT2, DCAEVT1 EPWM_TZ_ACTION_EVENT_TZB = 2, //!< TZ1 - TZ6, DCBEVT2, DCBEVT1 EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, //!< DCAEVT1 (Digital Compare A event 1) EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, //!< DCAEVT2 (Digital Compare A event 2) EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, //!< DCBEVT1 (Digital Compare B event 1) EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 //!< DCBEVT2 (Digital Compare B event 2) }EPWM_TripZoneEvent; //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneAction() as the //! \e tzAction parameter. // //***************************************************************************** typedef enum { EPWM_TZ_ACTION_HIGH_Z = 0, //!< high impedance output EPWM_TZ_ACTION_HIGH = 1, //!< high voltage state EPWM_TZ_ACTION_LOW = 2, //!< low voltage state EPWM_TZ_ACTION_DISABLE = 3 //!< disable action }EPWM_TripZoneAction; //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneAdvAction() as the //! \e tzAdvEvent parameter. // //***************************************************************************** typedef enum { //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9, //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6, //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3, //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0 }EPWM_TripZoneAdvancedEvent; //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA(), //! EPWM_setTripZoneAdvDigitalCompareActionB(),EPWM_setTripZoneAdvAction() //! as the \e tzAdvDCAction parameter. // //***************************************************************************** typedef enum { EPWM_TZ_ADV_ACTION_HIGH_Z = 0, //!< high impedance output EPWM_TZ_ADV_ACTION_HIGH = 1, //!< high voltage state EPWM_TZ_ADV_ACTION_LOW = 2, //!< low voltage state EPWM_TZ_ADV_ACTION_TOGGLE = 3, //!< toggle the output EPWM_TZ_ADV_ACTION_DISABLE = 7 //!< disable action }EPWM_TripZoneAdvancedAction; //***************************************************************************** // //! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA() and //! EPWM_setTripZoneAdvDigitalCompareActionB() as the \e tzAdvDCEvent //! parameter. // //***************************************************************************** typedef enum { //! Digital Compare event A/B 1 while counting up EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0, //! Digital Compare event A/B 1 while counting down EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3, //! Digital Compare event A/B 2 while counting up EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6, //! Digital Compare event A/B 2 while counting down EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9 }EPWM_TripZoneAdvDigitalCompareEvent; //***************************************************************************** // // Values that can be passed to EPWM_enableTripZoneInterrupt()and // EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter . // //***************************************************************************** //! Trip Zones Cycle By Cycle interrupt //! //! Trip Zones One Shot interrupt //! //! Digital Compare A Event 1 interrupt //! //! Digital Compare A Event 2 interrupt //! //! Digital Compare B Event 1 interrupt //! //! Digital Compare B Event 2 interrupt //! //***************************************************************************** // // Values that can be returned by EPWM_getTripZoneFlagStatus() . // //***************************************************************************** //! Trip Zones Cycle By Cycle flag //! //! Trip Zones One Shot flag //! //! Digital Compare A Event 1 flag //! //! Digital Compare A Event 2 flag //! //! Digital Compare B Event 1 flag //! //! Digital Compare B Event 2 flag //! //***************************************************************************** // // Value can be passed to EPWM_clearTripZoneFlag() as the // tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus(). // //***************************************************************************** //! Trip Zone interrupt //! //***************************************************************************** // // Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag() // as the tzCbcFlag parameter and returned by // EPWM_getCycleByCycleTripZoneFlagStatus(). // //***************************************************************************** //! CBC flag 1 //! //! CBC flag 2 //! //! CBC flag 3 //! //! CBC flag 4 //! //! CBC flag 5 //! //! CBC flag 6 //! //! CBC flag Digital compare event A2 //! //! CBC flag Digital compare event B2 //! //***************************************************************************** // // Values that can be passed to EPWM_clearOneShotTripZoneFlag() as // the tzCbcFlag parameter and returned by the // EPWM_getOneShotTripZoneFlagStatus() . // //***************************************************************************** //! OST flag OST1 //! //! OST flag OST2 //! //! OST flag OST3 //! //! OST flag OST4 //! //! OST flag OST5 //! //! OST flag OST6 //! //! OST flag Digital compare event A1 //! //! OST flag Digital compare event B1 //! //***************************************************************************** // //! Values that can be passed to EPWM_selectCycleByCycleTripZoneClearEvent() as //! the \e clearMode parameter. // //***************************************************************************** typedef enum { //! Clear CBC pulse when counter equals zero EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0, //! Clear CBC pulse when counter equals period EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1, //! Clear CBC pulse when counter equals zero or period EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2 }EPWM_CycleByCycleTripZoneClearMode; //***************************************************************************** // // Values that can be passed to EPWM_forceTripZoneEvent() as the // tzForceEvent parameter. // //***************************************************************************** //! Force Cycle By Cycle trip event //! //! Force a One-Shot Trip Event //! //! ForceDigital Compare Output A Event 1 //! //! ForceDigital Compare Output A Event 2 //! //! ForceDigital Compare Output B Event 1 //! //! ForceDigital Compare Output B Event 2 //! //***************************************************************************** // // Values that can be passed to EPWM_setInterruptSource() as the // interruptSource parameter. // //***************************************************************************** //! Time-base counter equal to zero //! //! Time-base counter equal to period //! //! Time-base counter equal to zero or period //! //! time-base counter equal to CMPA when the timer is incrementing //! //! time-base counter equal to CMPC when the timer is incrementing //! //! time-base counter equal to CMPA when the timer is decrementing //! //! time-base counter equal to CMPC when the timer is decrementing //! //! time-base counter equal to CMPB when the timer is incrementing //! //! time-base counter equal to CMPD when the timer is incrementing //! //! time-base counter equal to CMPB when the timer is decrementing //! //! time-base counter equal to CMPD when the timer is decrementing //! //***************************************************************************** // //! Values that can be passed to EPWM_enableADCTrigger(), //! EPWM_disableADCTrigger(),EPWM_setADCTriggerSource(), //! EPWM_setADCTriggerEventPrescale(),EPWM_getADCTriggerFlagStatus(), //! EPWM_clearADCTriggerFlag(),EPWM_enableADCTriggerEventCountInit(), //! EPWM_disableADCTriggerEventCountInit(),EPWM_forceADCTriggerEventCountInit(), //! EPWM_setADCTriggerEventCountInitValue(),EPWM_getADCTriggerEventCount(), //! EPWM_forceADCTrigger() as the \e adcSOCType parameter // //***************************************************************************** typedef enum { EPWM_SOC_A = 0, //!< SOC A EPWM_SOC_B = 1 //!< SOC B }EPWM_ADCStartOfConversionType; //***************************************************************************** // //! Values that can be passed to EPWM_setADCTriggerSource() as the //! \e socSource parameter. // //***************************************************************************** typedef enum { //! Event is based on DCxEVT1 EPWM_SOC_DCxEVT1 = 0, //! Time-base counter equal to zero EPWM_SOC_TBCTR_ZERO = 1, //! Time-base counter equal to period EPWM_SOC_TBCTR_PERIOD = 2, //! Time-base counter equal to zero or period EPWM_SOC_TBCTR_ZERO_OR_PERIOD = 3, //! time-base counter equal to CMPA when the timer is incrementing EPWM_SOC_TBCTR_U_CMPA = 4, //! time-base counter equal to CMPC when the timer is incrementing EPWM_SOC_TBCTR_U_CMPC = 8, //! time-base counter equal to CMPA when the timer is decrementing EPWM_SOC_TBCTR_D_CMPA = 5, //! time-base counter equal to CMPC when the timer is decrementing EPWM_SOC_TBCTR_D_CMPC = 10, //! time-base counter equal to CMPB when the timer is incrementing EPWM_SOC_TBCTR_U_CMPB = 6, //! time-base counter equal to CMPD when the timer is incrementing EPWM_SOC_TBCTR_U_CMPD = 12, //! time-base counter equal to CMPB when the timer is decrementing EPWM_SOC_TBCTR_D_CMPB = 7, //! time-base counter equal to CMPD when the timer is decrementing EPWM_SOC_TBCTR_D_CMPD = 14 }EPWM_ADCStartOfConversionSource; // Digital Compare Module //***************************************************************************** // //! Values that can be passed to EPWM_selectDigitalCompareTripInput(), //! EPWM_enableDigitalCompareTripCombinationInput(), //! EPWM_disableDigitalCompareTripCombinationInput() as the \e dcType //! parameter. // //***************************************************************************** typedef enum { EPWM_DC_TYPE_DCAH = 0, //!< Digital Compare A High EPWM_DC_TYPE_DCAL = 1, //!< Digital Compare A Low EPWM_DC_TYPE_DCBH = 2, //!< Digital Compare B High EPWM_DC_TYPE_DCBL = 3 //!< Digital Compare B Low }EPWM_DigitalCompareType; //***************************************************************************** // //! Values that can be passed to EPWM_selectDigitalCompareTripInput() as the //! \e tripSource parameter. // //***************************************************************************** typedef enum { EPWM_DC_TRIP_TRIPIN1 = 0, //!< Trip 1 EPWM_DC_TRIP_TRIPIN2 = 1, //!< Trip 2 EPWM_DC_TRIP_TRIPIN3 = 2, //!< Trip 3 EPWM_DC_TRIP_TRIPIN4 = 3, //!< Trip 4 EPWM_DC_TRIP_TRIPIN5 = 4, //!< Trip 5 EPWM_DC_TRIP_TRIPIN6 = 5, //!< Trip 6 EPWM_DC_TRIP_TRIPIN7 = 6, //!< Trip 7 EPWM_DC_TRIP_TRIPIN8 = 7, //!< Trip 8 EPWM_DC_TRIP_TRIPIN9 = 8, //!< Trip 9 EPWM_DC_TRIP_TRIPIN10 = 9, //!< Trip 10 EPWM_DC_TRIP_TRIPIN11 = 10, //!< Trip 11 EPWM_DC_TRIP_TRIPIN12 = 11, //!< Trip 12 EPWM_DC_TRIP_TRIPIN14 = 13, //!< Trip 14 EPWM_DC_TRIP_TRIPIN15 = 14, //!< Trip 15 EPWM_DC_TRIP_COMBINATION = 15 //!< All Trips (Trip1 - Trip 15) are selected }EPWM_DigitalCompareTripInput; //***************************************************************************** // // Values that can be passed to // EPWM_enableDigitalCompareTripCombinationInput(), // EPWM_disableDigitalCompareTripCombinationInput() as the tripInput // parameter. // //***************************************************************************** //! Combinational Trip 1 input //! //! Combinational Trip 2 input //! //! Combinational Trip 3 input //! //! Combinational Trip 4 input //! //! Combinational Trip 5 input //! //! Combinational Trip 6 input //! //! Combinational Trip 7 input //! //! Combinational Trip 8 input //! //! Combinational Trip 9 input //! //! Combinational Trip 10 input //! //! Combinational Trip 11 input //! //! Combinational Trip 12 input //! //! Combinational Trip 14 input //! //! Combinational Trip 15 input //! //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareBlankingEvent() as the //! the \e blankingPulse parameter. // //***************************************************************************** typedef enum { //! Time base counter equals period EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0, //! Time base counter equals zero EPWM_DC_WINDOW_START_TBCTR_ZERO = 1, //! Time base counter equals zero EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2 }EPWM_DigitalCompareBlankingPulse; //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareFilterInput() //! as the \e filterInput parameter. // //***************************************************************************** typedef enum { EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, //!< DC filter signal source is DCAEVT1 EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, //!< DC filter signal source is DCAEVT2 EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, //!< DC filter signal source is DCBEVT1 EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3 //!< DC filter signal source is DCBEVT2 }EPWM_DigitalCompareFilterInput; //***************************************************************************** // //! Values that can be assigned to EPWM_setDigitalCompareEventSource(), //! EPWM_setDigitalCompareEventSyncMode(),EPWM_enableDigitalCompareSyncEvent() //! EPWM_enableDigitalCompareADCTrigger(),EPWM_disableDigitalCompareSyncEvent() //! EPWM_disableDigitalCompareADCTrigger() as the \e dcModule parameter. // //***************************************************************************** typedef enum { EPWM_DC_MODULE_A = 0, //!< Digital Compare Module A EPWM_DC_MODULE_B = 1 //!< Digital Compare Module B }EPWM_DigitalCompareModule; //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareEventSource(), //! EPWM_setDigitalCompareEventSyncMode as the \e dcEvent parameter. // //***************************************************************************** typedef enum { EPWM_DC_EVENT_1 = 0, //!< Digital Compare Event number 1 EPWM_DC_EVENT_2 = 1 //!< Digital Compare Event number 2 }EPWM_DigitalCompareEvent; //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareEventSource() as the //! \e dcEventSource parameter. // //***************************************************************************** typedef enum { //! signal source is unfiltered (DCAEVT1/2) EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0, //! signal source is filtered (DCEVTFILT) EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1 }EPWM_DigitalCompareEventSource; //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareEventSyncMode() as the //! \e syncMode parameter. // //***************************************************************************** typedef enum { //! DC input signal is synced with TBCLK EPWM_DC_EVENT_INPUT_SYNCED = 0, //! DC input signal is not synced with TBCLK EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1 }EPWM_DigitalCompareSyncMode; //***************************************************************************** // //! Values that can be passed to EPWM_setGlobalLoadTrigger() as the //! \e loadTrigger parameter. // //***************************************************************************** typedef enum { //! load when counter is equal to zero EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0, //! load when counter is equal to period EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1, //! load when counter is equal to zero or period EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2, //! load on sync event EPWM_GL_LOAD_PULSE_SYNC = 0x3, //! load on sync event or when counter is equal to zero EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4, //! load on sync event or when counter is equal to period EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5, //! load on sync event or when counter is equal to period or zero EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6, //! load on global force EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF }EPWM_GlobalLoadTrigger; //***************************************************************************** // // Values that can be passed to EPWM_enableGlobalLoadRegisters(), // EPWM_disableGlobalLoadRegisters() as theloadRegister parameter. // //***************************************************************************** //! Global load TBPRD:TBPRDHR //! //! Global load CMPA:CMPAHR //! //! Global load CMPB:CMPBHR //! //! Global load CMPC //! //! Global load CMPD //! //! Global load DBRED:DBREDHR //! //! Global load DBFED:DBFEDHR //! //! Global load DBCTL //! //! Global load AQCTLA/A2 //! //! Global load AQCTLB/B2 //! //! Global load AQCSFRC //! //***************************************************************************** // //! Values that can be passed to EPWM_setValleyTriggerSource() as the \e //! trigger parameter. // //***************************************************************************** typedef enum { //! Valley capture trigged by software. EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U, //! Valley capture trigged by when counter is equal to zero. EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U, //! Valley capture trigged by when counter is equal period. EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U, //! Valley capture trigged when counter is equal to zero or period. EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U, //! Valley capture trigged by DCAEVT1 (Digital Compare A event 1) EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U, //! Valley capture trigged by DCAEVT2 (Digital Compare A event 2) EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U, //! Valley capture trigged by DCBEVT1 (Digital Compare B event 1) EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U, //! Valley capture trigged by DCBEVT2 (Digital Compare B event 2) EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U }EPWM_ValleyTriggerSource; //***************************************************************************** // //! Values that can be passed to EPWM_getValleyCountEdgeStatus() as the \e edge //! parameter. // //***************************************************************************** typedef enum { EPWM_VALLEY_COUNT_START_EDGE = 0, //!< Valley count start edge EPWM_VALLEY_COUNT_STOP_EDGE = 1 //!< Valley count stop edge }EPWM_ValleyCounterEdge; //***************************************************************************** // //! Values that can be passed to EPWM_setValleyDelayValue() as the \e delayMode //! parameter. // //***************************************************************************** typedef enum { //! Delay value equals the offset value defines by software EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U, //! Delay value equals the sum of the Hardware counter value and the offset //! value defines by software EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U, //! Delay value equals the the Hardware counter shifted by //! (1 + the offset value defines by software) EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U, //! Delay value equals the the Hardware counter shifted by //! (2 + the offset value defines by software) EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U, //! Delay value equals the the Hardware counter shifted by //! (4 + the offset value defines by software) EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U }EPWM_ValleyDelayMode; // DC Edge Filter //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareEdgeFilterMode() //! as the \e edgeMode parameter. // //***************************************************************************** typedef enum { EPWM_DC_EDGEFILT_MODE_RISING = 0, //!< Digital Compare Edge filter low //!< to high edge mode EPWM_DC_EDGEFILT_MODE_FALLING = 1, //!< Digital Compare Edge filter high //!< to low edge mode EPWM_DC_EDGEFILT_MODE_BOTH = 2 //!< Digital Compare Edge filter both //!< edges mode } EPWM_DigitalCompareEdgeFilterMode; //***************************************************************************** // //! Values that can be passed to EPWM_setDigitalCompareEdgeFilterEdgeCount() //! as the \e edgeCount parameter. // //***************************************************************************** typedef enum { EPWM_DC_EDGEFILT_EDGECNT_0 = 0, //!< Digital Compare Edge filter edge //!< count = 0 EPWM_DC_EDGEFILT_EDGECNT_1 = 1, //!< Digital Compare Edge filter edge //!< count = 1 EPWM_DC_EDGEFILT_EDGECNT_2 = 2, //!< Digital Compare Edge filter edge //!< count = 2 EPWM_DC_EDGEFILT_EDGECNT_3 = 3, //!< Digital Compare Edge filter edge //!< count = 3 EPWM_DC_EDGEFILT_EDGECNT_4 = 4, //!< Digital Compare Edge filter edge //!< count = 4 EPWM_DC_EDGEFILT_EDGECNT_5 = 5, //!< Digital Compare Edge filter edge //!< count = 5 EPWM_DC_EDGEFILT_EDGECNT_6 = 6, //!< Digital Compare Edge filter edge //!< count = 6 EPWM_DC_EDGEFILT_EDGECNT_7 = 7 //!< Digital Compare Edge filter edge //!< count = 7 } EPWM_DigitalCompareEdgeFilterEdgeCount; //***************************************************************************** // //! Values that can be passed to EPWM_lockRegisters() as the \e registerGroup //! parameter. // //***************************************************************************** typedef enum { EPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group EPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group EPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group }EPWM_LockRegisterGroup; //***************************************************************************** // // Prototypes for the API. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks ePWM base address. //! //! \param base specifies the ePWM module base address. //! //! This function determines if an ePWM module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** // Time Base Sub Module //***************************************************************************** // //! Set the time base count //! //! \param base is the base address of the EPWM module. //! \param count is the time base count value. //! //! This function sets the 16 bit counter value of the time base counter. //! //! \return None. // //***************************************************************************** static inline void EPWM_setTimeBaseCounter(uint32_t base, uint16_t count) { ; // write to TBCTR register (*((volatile uint16_t *)(base + 0x4U))) = count; } //***************************************************************************** // //! Set count mode after phase shift sync //! //! \param base is the base address of the EPWM module. //! \param mode is the count mode. //! //! This function sets the time base count to count up or down after a new //! phase value set by the EPWM_setPhaseShift(). The count direction is //! determined by the variable mode. Valid inputs for mode are: //! - EPWM_COUNT_MODE_UP_AFTER_SYNC - Count up after sync //! - EPWM_COUNT_MODE_DOWN_AFTER_SYNC - Count down after sync //! //! \return None. // //***************************************************************************** static inline void EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode) { ; if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC) { // set PHSDIR bit (*((volatile uint16_t *)(base + 0x0U))) |= 0x2000U; } else { // clear PHSDIR bit (*((volatile uint16_t *)(base + 0x0U))) &= ~0x2000U; } } //***************************************************************************** // //! Set the time base clock and the high speed time base clock count pre-scaler //! //! \param base is the base address of the EPWM module. //! \param prescaler is the time base count pre scale value. //! \param highSpeedPrescaler is the high speed time base count pre scale //! value. //! //! This function sets the pre scaler(divider)value for the time base clock //! counter and the high speed time base clock counter. //! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X, //! where X is 1,2,4,8,16, 32,64 or 128. //! The actual numerical values for these macros represent values 0,1...7. //! The equation for the output clock is: //! TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler) //! //! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half //! SYSCLK. //! //! \return None. // //***************************************************************************** static inline void EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, EPWM_HSClockDivider highSpeedPrescaler) { ; // write to CLKDIV and HSPCLKDIV bit (*((volatile uint16_t *)(base + 0x0U))) = (((*((volatile uint16_t *)(base + 0x0U))) & ~(0x1C00U | 0x380U))| (((uint16_t)prescaler << 10U) | ((uint16_t)highSpeedPrescaler << 7U))); } //***************************************************************************** // //! Force a software sync pulse //! //! \param base is the base address of the EPWM module. //! //! This function causes a single software initiated sync pulse. Make sure the //! appropriate mode is selected using EPWM_setupSyncOutputMode() before using //! this function. //! //! \return None. // //***************************************************************************** static inline void EPWM_forceSyncPulse(uint32_t base) { ; // set SWFSYNC bit (*((volatile uint16_t *)(base + 0x0U))) |= 0x40U; } //***************************************************************************** // //! Set up the sync out pulse event //! //! \param base is the base address of the EPWM module. //! \param mode is the sync out mode. //! //! This function set the sync out pulse mode. //! Valid values for mode are: //! - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - sync pulse is generated by software //! when EPWM_forceSyncPulse() //! function is called or by EPWMxSYNCI //! signal. //! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO - sync pulse is generated when //! time base counter equals zero. //! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B - sync pulse is generated when //! time base counter equals compare //! B value. //! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C - sync pulse is generated when //! time base counter equals compare //! C value. //! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D - sync pulse is generated when //! time base counter equals compare //! D value. //! - EPWM_SYNC_OUT_PULSE_DISABLED - sync pulse is disabled. //! //! \return None. // //***************************************************************************** static inline void EPWM_setSyncOutPulseMode(uint32_t base, EPWM_SyncOutPulseMode mode) { ; // No extended mode support if(mode < EPWM_SYNC_OUT_PULSE_DISABLED) { // write to SYNCOSEL bits (*((volatile uint16_t *)(base + 0x0U))) = (((*((volatile uint16_t *)(base + 0x0U))) & ~(0x30U)) | ((uint16_t)mode << 4U)); } else // Extended modes and sync out disable mode { // Write 0x3 to SYNCOSEL to enable selection from SYNCOSELX (*((volatile uint16_t *)(base + 0x0U))) = (*((volatile uint16_t *)(base + 0x0U))) | 0x30U; // write to SYNCOSELX bit (*((volatile uint16_t *)(base + 0x1U))) = (((*((volatile uint16_t *)(base + 0x1U))) & ~(0x3000U)) | (((uint16_t)mode & 0x3U) << 12U)); } } //***************************************************************************** // //! Set PWM period load mode. //! //! \param base is the base address of the EPWM module. //! \param loadMode is the PWM period load mode. //! //! This function sets the load mode for the PWM period. If loadMode is set to //! EPWM_PERIOD_SHADOW_LOAD, a write or read to the TBPRD (PWM Period count //! register) accesses the shadow register. If loadMode is set to //! EPWM_PERIOD_DIRECT_LOAD, a write or read to the TBPRD register accesses the //! register directly. //! //! \return None. // //***************************************************************************** static inline void EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode) { ; if(loadMode == EPWM_PERIOD_SHADOW_LOAD) { // clear PRDLD (*((volatile uint16_t *)(base + 0x0U))) &= ~0x8U; } else { // set PRDLD (*((volatile uint16_t *)(base + 0x0U))) |= 0x8U; } } //***************************************************************************** // //! Enable phase shift load //! //! \param base is the base address of the EPWM module. //! //! This function enables loading of phase shift when the appropriate sync //! event occurs. //! //! \return None. // //***************************************************************************** static inline void EPWM_enablePhaseShiftLoad(uint32_t base) { ; // set PHSEN bit (*((volatile uint16_t *)(base + 0x0U))) |= 0x4U; } //***************************************************************************** // //! Disable phase shift load //! //! \param base is the base address of the EPWM module. //! //! This function disables loading of phase shift. //! occurs. //! //! \return None. // //***************************************************************************** static inline void EPWM_disablePhaseShiftLoad(uint32_t base) { ; // clear PHSEN bit (*((volatile uint16_t *)(base + 0x0U))) &= ~0x4U; } //***************************************************************************** // //! Set time base counter mode //! //! \param base is the base address of the EPWM module. //! \param counterMode is the time base counter mode. //! //! This function sets up the time base counter mode. //! Valid values for counterMode are: //! - EPWM_COUNTER_MODE_UP - Up - count mode. //! - EPWM_COUNTER_MODE_DOWN - Down - count mode. //! - EPWM_COUNTER_MODE_UP_DOWN - Up - down - count mode. //! - EPWM_COUNTER_MODE_STOP_FREEZE - Stop - Freeze counter. //! //! \return None. // //***************************************************************************** static inline void EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode) { ; // write to CTRMODE bit (*((volatile uint16_t *)(base + 0x0U))) = (((*((volatile uint16_t *)(base + 0x0U))) & ~(0x3U)) | ((uint16_t)counterMode)); } //***************************************************************************** // //! Set shadow to active period load on sync mode //! //! \param base is the base address of the EPWM module. //! \param shadowLoadMode is the shadow to active load mode. //! //! This function sets up the shadow to active Period register load mode with //! respect to a sync event. Valid values for shadowLoadMode are: //! - EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO - shadow to active load occurs when //! time base counter reaches 0. //! - EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC - shadow to active load occurs when //! time base counter reaches 0 and a //! SYNC occurs. //! - EPWM_SHADOW_LOAD_MODE_SYNC - shadow to active load occurs only //! when a SYNC occurs. //! //! \return None. // //***************************************************************************** static inline void EPWM_selectPeriodLoadEvent(uint32_t base, EPWM_PeriodShadowLoadMode shadowLoadMode) { ; // write to PRDLDSYNC bit (*((volatile uint16_t *)(base + 0x1U))) = (((*((volatile uint16_t *)(base + 0x1U))) & ~(0xC000U)) | ((uint16_t)shadowLoadMode << 14U)); } //***************************************************************************** // //! Enable one shot sync mode //! //! \param base is the base address of the EPWM module. //! //! This function enables one shot sync mode. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableOneShotSync(uint32_t base) { ; // Set OSHTSYNCMODE bit (*((volatile uint16_t *)(base + 0x1U))) |= 0x40U; } //***************************************************************************** // //! Disable one shot sync mode //! //! \param base is the base address of the EPWM module. //! //! This function disables one shot sync mode. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableOneShotSync(uint32_t base) { ; // Clear OSHTSYNCMODE bit (*((volatile uint16_t *)(base + 0x1U))) &= ~0x40U; } //***************************************************************************** // //! Start one shot sync mode //! //! \param base is the base address of the EPWM module. //! //! This function propagates a one shot sync pulse. //! //! \return None. // //***************************************************************************** static inline void EPWM_startOneShotSync(uint32_t base) { ; // set OSHTSYNC bit (*((volatile uint16_t *)(base + 0x1U))) |= 0x80U; } //***************************************************************************** // //! Return time base counter maximum status. //! //! \param base is the base address of the EPWM module. //! //! This function returns the status of the time base max counter. //! //! \return Returns true if the counter has reached 0xFFFF. //! Returns false if the counter hasn't reached 0xFFFF. // //***************************************************************************** static inline _Bool EPWM_getTimeBaseCounterOverflowStatus(uint32_t base) { ; // Return true if CTRMAX bit is set, false otherwise return((((*((volatile uint16_t *)(base + 0x5U))) & 0x4U) == 0x4U) ? 1 : 0); } //***************************************************************************** // //! Clear max time base counter event. //! //! \param base is the base address of the EPWM module. //! //! This function clears the max time base counter latch event. The latch event //! occurs when the time base counter reaches its maximum value of 0xFFFF. //! //! \return None. // //***************************************************************************** static inline void EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base) { ; // set CTRMAX bit (*((volatile uint16_t *)(base + 0x5U))) |= 0x4U; } //***************************************************************************** // //! Return external sync signal status. //! //! \param base is the base address of the EPWM module. //! //! This function returns the external sync signal status. //! //! \return Returns true if if an external sync signal event //! Returns false if there is no event. // //***************************************************************************** static inline _Bool EPWM_getSyncStatus(uint32_t base) { ; // Return true if SYNCI bit is set, false otherwise return((((*((volatile uint16_t *)(base + 0x5U))) & 0x2U) == 0x2U) ? 1 : 0); } //***************************************************************************** // //! Clear external sync signal event. //! //! \param base is the base address of the EPWM module. //! //! This function clears the external sync signal latch event. //! //! \return None. // //***************************************************************************** static inline void EPWM_clearSyncEvent(uint32_t base) { ; // Set SYNCI bit (*((volatile uint16_t *)(base + 0x5U))) |= 0x2U; } //***************************************************************************** // //! Return time base counter direction. //! //! \param base is the base address of the EPWM module. //! //! This function returns the direction of the time base counter. //! //! \return returns EPWM_TIME_BASE_STATUS_COUNT_UP if the counter is counting //! up or EPWM_TIME_BASE_STATUS_COUNT_DOWN if the counter is //! counting down. // //***************************************************************************** static inline uint16_t EPWM_getTimeBaseCounterDirection(uint32_t base) { ; // Return CTRDIR bit return((*((volatile uint16_t *)(base + 0x5U))) & 0x1U); } //***************************************************************************** // //! Sets the phase shift offset counter value. //! //! \param base is the base address of the EPWM module. //! \param phaseCount is the phase shift count value. //! //! This function sets the 16 bit time-base counter phase of the ePWM relative //! to the time-base that is supplying the synchronization input signal. Call //! the EPWM_enablePhaseShiftLoad() function to enable loading of the //! phaseCount phase shift value when a sync event occurs. //! //! \return None. // //***************************************************************************** static inline void EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount) { ; // write to TBPHS bit (*((volatile uint32_t *)(base + 0x60U))) = (((*((volatile uint32_t *)(base + 0x60U))) & ~((uint32_t)0xFFFF0000U)) | ((uint32_t)phaseCount << 16U)); } //***************************************************************************** // //! Sets the PWM period count. //! //! \param base is the base address of the EPWM module. //! \param periodCount is period count value. //! //! This function sets the period of the PWM count. The value of periodCount is //! the value written to the register. User should map the desired period or //! frequency of the waveform into the correct periodCount. //! Invoke the function EPWM_selectPeriodLoadEvent() with the appropriate //! parameter to set the load mode of the Period count. periodCount has a //! maximum valid value of 0xFFFF //! //! \return None. // //***************************************************************************** static inline void EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount) { ; // write to TBPRD bit (*((volatile uint16_t *)(base + 0x63U))) = periodCount; } //***************************************************************************** // //! Gets the PWM period count. //! //! \param base is the base address of the EPWM module. //! //! This function gets the period of the PWM count. //! //! \return The period count value. // //***************************************************************************** static inline uint16_t EPWM_getTimeBasePeriod(uint32_t base) { ; // read from TBPRD bit return((*((volatile uint16_t *)(base + 0x63U)))); } //***************************************************************************** // //! Sets the EPWM links. //! //! \param base is the base address of the EPWM module. //! \param epwmLink is the ePWM instance to link with. //! \param linkComp is the ePWM component to link. //! //! This function links the component defined in linkComp in the current ePWM //! instance with the linkComp component of the ePWM instance defined by //! epwmLink. A change (a write) in the value of linkComp component of epwmLink //! instance, causes a change in the current ePWM linkComp component. //! For example if the current ePWM is ePWM3 and the values of epwmLink and //! linkComp are EPWM_LINK_WITH_EPWM_1 and EPWM_LINK_COMP_C respectively, //! then a write to COMPC register in ePWM1, will result in a simultaneous //! write to COMPC register in ePWM3. //! Valid values for epwmLink are: //! - EPWM_LINK_WITH_EPWM_1 - link current ePWM with ePWM1 //! - EPWM_LINK_WITH_EPWM_2 - link current ePWM with ePWM2 //! - EPWM_LINK_WITH_EPWM_3 - link current ePWM with ePWM3 //! - EPWM_LINK_WITH_EPWM_4 - link current ePWM with ePWM4 //! - EPWM_LINK_WITH_EPWM_5 - link current ePWM with ePWM5 //! - EPWM_LINK_WITH_EPWM_6 - link current ePWM with ePWM6 //! - EPWM_LINK_WITH_EPWM_7 - link current ePWM with ePWM7 //! - EPWM_LINK_WITH_EPWM_8 - link current ePWM with ePWM8 //! //! Valid values for linkComp are: //! - EPWM_LINK_TBPRD - link TBPRD:TBPRDHR registers //! - EPWM_LINK_COMP_A - link COMPA registers //! - EPWM_LINK_COMP_B - link COMPB registers //! - EPWM_LINK_COMP_C - link COMPC registers //! - EPWM_LINK_COMP_D - link COMPD registers //! - EPWM_LINK_GLDCTL2 - link GLDCTL2 registers //! //! \return None. // //***************************************************************************** static inline void EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, EPWM_LinkComponent linkComp) { ; // Configure EPWM links (*((volatile uint32_t *)(base + 0x38U))) = (((*((volatile uint32_t *)(base + 0x38U))) & ~((uint32_t)0xFU << linkComp)) | ((uint32_t)epwmLink << linkComp)); } //***************************************************************************** // //! Sets up the Counter Compare shadow load mode //! //! \param base is the base address of the EPWM module. //! \param compModule is the counter compare module. //! \param loadMode is the shadow to active load mode. //! //! This function enables and sets up the counter compare shadow load mode. //! Valid values for the variables are: //! - compModule //! - EPWM_COUNTER_COMPARE_A - counter compare A. //! - EPWM_COUNTER_COMPARE_B - counter compare B. //! - EPWM_COUNTER_COMPARE_C - counter compare C. //! - EPWM_COUNTER_COMPARE_D - counter compare D. //! - loadMode //! - EPWM_COMP_LOAD_ON_CNTR_ZERO - load when counter equals zero //! - EPWM_COMP_LOAD_ON_CNTR_PERIOD - load when counter equals period //! - EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals //! zero or period //! - EPWM_COMP_LOAD_FREEZE - Freeze shadow to active load //! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO - load when counter equals zero //! - EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD -load when counter equals period //! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load when counter equals //! zero or period //! - EPWM_COMP_LOAD_ON_SYNC_ONLY - load on sync only //! //! \return None. // //***************************************************************************** static inline void EPWM_setCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule, EPWM_CounterCompareLoadMode loadMode) { uint16_t syncModeOffset; uint16_t loadModeOffset; uint16_t shadowModeOffset; uint32_t registerOffset; ; if((compModule == EPWM_COUNTER_COMPARE_A) || (compModule == EPWM_COUNTER_COMPARE_C)) { syncModeOffset = 10U; loadModeOffset = 0U; shadowModeOffset = 4U; } else { syncModeOffset = 12U; loadModeOffset = 2U; shadowModeOffset = 6U; } // Get the register offset. EPWM_O_CMPCTL for A&B or // EPWM_O_CMPCTL2 for C&D registerOffset = base + 0x8U + ((uint32_t)compModule & 0x1U); // Set the appropriate sync and load mode bits and also enable shadow // load mode. Shadow to active load can also be frozen. (*((volatile uint16_t *)(registerOffset))) = (((*((volatile uint16_t *)(registerOffset))) & ~((0x3U << syncModeOffset) | // Clear sync mode (0x3U << loadModeOffset) | // Clear load mode (0x1U << shadowModeOffset))) | // shadow mode ((((uint16_t)loadMode >> 2U) << syncModeOffset) | (((uint16_t)loadMode & 0x3U) << loadModeOffset))); } //***************************************************************************** // //! Disable Counter Compare shadow load mode //! //! \param base is the base address of the EPWM module. //! \param compModule is the counter compare module. //! //! This function disables counter compare shadow load mode. //! Valid values for the variables are: //! - compModule //! - EPWM_COUNTER_COMPARE_A - counter compare A. //! - EPWM_COUNTER_COMPARE_B - counter compare B. //! - EPWM_COUNTER_COMPARE_C - counter compare C. //! - EPWM_COUNTER_COMPARE_D - counter compare D. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule) { uint16_t shadowModeOffset; uint32_t registerOffset; ; if((compModule == EPWM_COUNTER_COMPARE_A) || (compModule == EPWM_COUNTER_COMPARE_C)) { shadowModeOffset = 4U; } else { shadowModeOffset = 6U; } // Get the register offset. EPWM_O_CMPCTL for A&B or // EPWM_O_CMPCTL2 for C&D registerOffset = base + 0x8U + ((uint32_t)compModule & 0x1U); // Disable shadow load mode. (*((volatile uint16_t *)(registerOffset))) = ((*((volatile uint16_t *)(registerOffset))) | (0x1U << shadowModeOffset)); } //***************************************************************************** // //! Set counter compare values. //! //! \param base is the base address of the EPWM module. //! \param compModule is the Counter Compare value module. //! \param compCount is the counter compare count value. //! //! This function sets the counter compare value for counter compare registers. //! The maximum value for compCount is 0xFFFF. //! Valid values for compModule are: //! - EPWM_COUNTER_COMPARE_A - counter compare A. //! - EPWM_COUNTER_COMPARE_B - counter compare B. //! - EPWM_COUNTER_COMPARE_C - counter compare C. //! - EPWM_COUNTER_COMPARE_D - counter compare D. //! //! \return None. // //***************************************************************************** static inline void EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, uint16_t compCount) { uint32_t registerOffset; ; // Get the register offset for the Counter compare registerOffset = 0x6AU + (uint16_t)compModule; // Write to the counter compare registers. if((compModule == EPWM_COUNTER_COMPARE_A) || (compModule == EPWM_COUNTER_COMPARE_B)) { // write to COMPA or COMPB bits (*((volatile uint16_t *)(base + registerOffset + 0x1U))) = compCount; } else { // write to COMPC or COMPD bits (*((volatile uint16_t *)(base + registerOffset))) = compCount; } } //***************************************************************************** // //! Get counter compare values. //! //! \param base is the base address of the EPWM module. //! \param compModule is the Counter Compare value module. //! //! This function gets the counter compare value for counter compare registers. //! Valid values for compModule are: //! - EPWM_COUNTER_COMPARE_A - counter compare A. //! - EPWM_COUNTER_COMPARE_B - counter compare B. //! - EPWM_COUNTER_COMPARE_C - counter compare C. //! - EPWM_COUNTER_COMPARE_D - counter compare D. //! //! \return The counter compare count value. // //***************************************************************************** static inline uint16_t EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule) { uint32_t registerOffset; uint16_t compCount; ; // Get the register offset for the Counter compare registerOffset = 0x6AU + (uint16_t)compModule; // Read from the counter compare registers. if((compModule == EPWM_COUNTER_COMPARE_A) || (compModule == EPWM_COUNTER_COMPARE_B)) { // read COMPA or COMPB bits compCount = (uint16_t)(((*((volatile uint32_t *)(base + registerOffset))) & (uint32_t)0xFFFF0000U) >> 16U); } else { // read COMPC or COMPD bits compCount = (*((volatile uint16_t *)(base + registerOffset))); } return(compCount); } //***************************************************************************** // //! Return the counter compare shadow register full status. //! //! \param base is the base address of the EPWM module. //! \param compModule is the Counter Compare value module. //! //! This function returns the counter Compare shadow register full status flag. //! Valid values for compModule are: //! - EPWM_COUNTER_COMPARE_A - counter compare A. //! - EPWM_COUNTER_COMPARE_B - counter compare B. //! //! \return Returns true if the shadow register is full. //! Returns false if the shadow register is not full. // //***************************************************************************** static inline _Bool EPWM_getCounterCompareShadowStatus(uint32_t base, EPWM_CounterCompareModule compModule) { ; // Read the value of SHDWAFULL or SHDWBFULL bit return(((((*((volatile uint32_t *)(base + 0x8U))) >> ((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) & 0x1U) == 0x1U) ? 1:0); } // Action Qualifier functions //***************************************************************************** // //! Sets the Action Qualifier shadow load mode //! //! \param base is the base address of the EPWM module. //! \param aqModule is the Action Qualifier module value. //! \param loadMode is the shadow to active load mode. //! //! This function enables and sets the Action Qualifier shadow load mode. //! Valid values for the variables are: //! - aqModule //! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. //! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. //! - loadMode //! - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero //! - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period //! - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals //! zero or period //! - EPWM_AQ_LOAD_FREEZE - Freeze shadow to active load //! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter //! equals zero //! - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter //! equals period //! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when //! counter equals zero or period //! - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule, EPWM_ActionQualifierLoadMode loadMode) { uint16_t syncModeOffset; uint16_t shadowModeOffset; syncModeOffset = 8U + (uint16_t)aqModule; shadowModeOffset = 4U + (uint16_t)aqModule; // Set the appropriate sync and load mode bits and also enable shadow // load mode. Shadow to active load can also be frozen. (*((volatile uint16_t *)(base + 0x10U))) = (((*((volatile uint16_t *)(base + 0x10U))) & (~((0x3U << (uint16_t)aqModule) | // Clear AQ mode selection (0x3U << (uint16_t)syncModeOffset))) | // Clear Sync mode (0x1U << shadowModeOffset)) | // Enable Shadow mode ((((uint16_t)loadMode >> 2U) << syncModeOffset) | // sync mode (((uint16_t)loadMode & 0x3U) << (uint16_t)aqModule))); // AQ mode } //***************************************************************************** // //! Disable Action Qualifier shadow load mode //! //! \param base is the base address of the EPWM module. //! \param aqModule is the Action Qualifier module value. //! //! This function disables the Action Qualifier shadow load mode. //! Valid values for the variables are: //! - aqModule //! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. //! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule) { uint16_t shadowModeOffset; ; shadowModeOffset = 4U + (uint16_t)aqModule; // Disable shadow load mode. Action qualifier is loaded on // immediate mode only. (*((volatile uint16_t *)(base + 0x10U))) &= ~(1U << shadowModeOffset); } //***************************************************************************** // //! Set up Action qualifier trigger source for event T1 //! //! \param base is the base address of the EPWM module. //! \param trigger sources for Action Qualifier triggers. //! //! This function sets up the sources for Action Qualifier event T1. //! Valid values for trigger are: //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierT1TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger) { ; // Set T1 trigger source (*((volatile uint16_t *)(base + 0x11U))) = (((*((volatile uint16_t *)(base + 0x11U))) & (~0xFU)) | ((uint16_t)trigger)); } //***************************************************************************** // //! Set up Action qualifier trigger source for event T2 //! //! \param base is the base address of the EPWM module. //! \param trigger sources for Action Qualifier triggers. //! //! This function sets up the sources for Action Qualifier event T2. //! Valid values for trigger are: //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 //! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierT2TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger) { ; // Set T2 trigger source (*((volatile uint16_t *)(base + 0x11U))) = (((*((volatile uint16_t *)(base + 0x11U))) & (~0xF0U)) | ((uint16_t)trigger << 4U)); } //***************************************************************************** // //! Set up Action qualifier outputs //! //! \param base is the base address of the EPWM module. //! \param epwmOutput is the ePWM pin type. //! \param output is the Action Qualifier output. //! \param event is the event that causes a change in output. //! //! This function sets up the Action Qualifier output on ePWM A or ePWMB, //! depending on the value of epwmOutput, to a value specified by outPut based //! on the input events - specified by event. //! The following are valid values for the parameters. //! - epwmOutput //! - EPWM_AQ_OUTPUT_A - ePWMxA output //! - EPWM_AQ_OUTPUT_B - ePWMxB output //! - output //! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins //! - EPWM_AQ_OUTPUT_LOW - Set output pins to low //! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High //! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins //! - event //! - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO - Time base counter equals //! zero //! - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD - Time base counter equals //! period //! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA - Time base counter up equals //! COMPA //! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA - Time base counter down //! equals COMPA //! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB - Time base counter up equals //! COMPB //! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB - Time base counter down //! equals COMPB //! - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP - T1 event on count up //! - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN - T1 event on count down //! - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP - T2 event on count up //! - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN - T2 event on count down //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_ActionQualifierOutputEvent event) { uint32_t registerOffset; uint32_t registerTOffset; ; // Get the register offset registerOffset = 0x40U + (uint16_t)epwmOutput; registerTOffset = 0x41U + (uint16_t)epwmOutput; // If the event occurs on T1 or T2 events if(((uint16_t)event & 0x1U) == 1U) { // Write to T1U,T1D,T2U or T2D of AQCTLA2 register (*((volatile uint16_t *)(base + registerTOffset))) = (((*((volatile uint16_t *)(base + registerTOffset))) & ~(3U << ((uint16_t)event - 1U))) | ((uint16_t)output << ((uint16_t)event - 1U))); } else { // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register (*((volatile uint16_t *)(base + registerOffset))) = (((*((volatile uint16_t *)(base + registerOffset))) & ~(3U << (uint16_t)event)) | ((uint16_t)output << (uint16_t)event)); } } //***************************************************************************** // //! Set up Action qualifier event outputs //! //! \param base is the base address of the EPWM module. //! \param epwmOutput is the ePWM pin type. //! \param action is the desired action when the specified event occurs //! //! This function sets up the Action Qualifier output on ePWMA or ePWMB, //! depending on the value of epwmOutput, to a value specified by action //! The following are valid values for the parameters. //! - epwmOutput //! - EPWM_AQ_OUTPUT_A - ePWMxA output //! - EPWM_AQ_OUTPUT_B - ePWMxB output //! - action //! - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO - Time base counter equals zero //! and no change in output pins //! - EPWM_AQ_OUTPUT_LOW_ZERO - Time base counter equals zero //! and set output pins to low //! - EPWM_AQ_OUTPUT_HIGH_ZERO - Time base counter equals zero //! and set output pins to high //! - EPWM_AQ_OUTPUT_TOGGLE_ZERO - Time base counter equals zero //! and toggle the output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period //! and no change in output pins //! - EPWM_AQ_OUTPUT_LOW_PERIOD - Time base counter equals period //! and set output pins to low //! - EPWM_AQ_OUTPUT_HIGH_PERIOD - Time base counter equals period //! and set output pins to high //! - EPWM_AQ_OUTPUT_TOGGLE_PERIOD - Time base counter equals period //! and toggle the output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA - Time base counter up equals //! COMPA and no change in the //! output pins //! - EPWM_AQ_OUTPUT_LOW_UP_CMPA - Time base counter up equals //! COMPA and set output pins low //! - EPWM_AQ_OUTPUT_HIGH_UP_CMPA - Time base counter up equals //! COMPA and set output pins high //! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA - Time base counter up equals //! COMPA and toggle output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA- Time base counter down equals //! COMPA and no change in the //! output pins //! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA - Time base counter down equals //! COMPA and set output pins low //! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA - Time base counter down equals //! COMPA and set output pins high //! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA - Time base counter down equals //! COMPA and toggle output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB - Time base counter up equals //! COMPB and no change in the //! output pins //! - EPWM_AQ_OUTPUT_LOW_UP_CMPB - Time base counter up equals //! COMPB and set output pins low //! - EPWM_AQ_OUTPUT_HIGH_UP_CMPB - Time base counter up equals //! COMPB and set output pins high //! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB - Time base counter up equals //! COMPB and toggle output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals //! COMPB and no change in the //! output pins //! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB - Time base counter down equals //! COMPB and set output pins low //! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB - Time base counter down equals //! COMPB and set output pins high //! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB - Time base counter down equals //! COMPB and toggle output pins //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierEventAction action) { uint32_t registerOffset; ; // Get the register offset registerOffset = 0x40U + (uint16_t)epwmOutput; // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register (*((volatile uint16_t *)(base + registerOffset))) = (uint16_t)action; } //***************************************************************************** // //! Set up Additional action qualifier event outputs //! //! \param base is the base address of the EPWM module. //! \param epwmOutput is the ePWM pin type. //! \param action is the desired action when the specified event occurs //! //! This function sets up the Additional Action Qualifier output on ePWMA or //! ePWMB depending on the value of epwmOutput, to a value specified by action //! The following are valid values for the parameters. //! - epwmOutput //! - EPWM_AQ_OUTPUT_A - ePWMxA output //! - EPWM_AQ_OUTPUT_B - ePWMxB output //! - action //! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_TI - T1 event on count up //! and no change in output pins //! - EPWM_AQ_OUTPUT_LOW_UP_TI - T1 event on count up //! and set output pins to low //! - EPWM_AQ_OUTPUT_HIGH_UP_TI - T1 event on count up //! and set output pins to high //! - EPWM_AQ_OUTPUT_TOGGLE_UP_TI - T1 event on count up //! and toggle the output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_TI- T1 event on count down //! and no change in output pins //! - EPWM_AQ_OUTPUT_LOW_DOWN_TI - T1 event on count down //! and set output pins to low //! - EPWM_AQ_OUTPUT_HIGH_DOWN_TI - T1 event on count down //! and set output pins to high //! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_TI - T1 event on count down //! and toggle the output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 - T2 event on count up //! and no change in output pins //! - EPWM_AQ_OUTPUT_LOW_UP_T2 - T2 event on count up //! and set output pins to low //! - EPWM_AQ_OUTPUT_HIGH_UP_T2 - T2 event on count up //! and set output pins to high //! - EPWM_AQ_OUTPUT_TOGGLE_UP_T2 - T2 event on count up //! and toggle the output pins //! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2- T2 event on count down //! and no change in output pins //! - EPWM_AQ_OUTPUT_LOW_DOWN_T2 - T2 event on count down //! and set output pins to low //! - EPWM_AQ_OUTPUT_HIGH_DOWN_T2 - T2 event on count down //! and set output pins to high //! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 - T2 event on count down //! and toggle the output pins //! //! \return None. // //***************************************************************************** static inline void EPWM_setAdditionalActionQualifierActionComplete (uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_AdditionalActionQualifierEventAction action) { uint32_t registerTOffset; ; // Get the register offset registerTOffset = 0x41U + (uint16_t)epwmOutput; // Write to T1U, T1D, T2U or T2D of AQCTLA2 register (*((volatile uint16_t *)(base + registerTOffset))) = (uint16_t)action; } //***************************************************************************** // //! Sets up Action qualifier continuous software load mode. //! //! \param base is the base address of the EPWM module. //! \param mode is the mode for shadow to active load mode. //! //! This function sets up the AQCFRSC register load mode for continuous //! software force reload mode. The software force actions are determined by //! the EPWM_setActionQualifierContSWForceAction() function. //! Valid values for mode are: //! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO - shadow mode load when counter //! equals zero //! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD - shadow mode load when counter //! equals period //! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter //! equals zero or period //! - EPWM_AQ_SW_IMMEDIATE_LOAD - immediate mode load only //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, EPWM_ActionQualifierContForce mode) { ; // Set the Action qualifier software action reload mode. // write to RLDCSF bit (*((volatile uint16_t *)(base + 0x47U))) = (((*((volatile uint16_t *)(base + 0x47U))) & ~0xC0U) | ((uint16_t)mode << 6U)); } //***************************************************************************** // //! Triggers a continuous software forced event. //! //! \param base is the base address of the EPWM module. //! \param epwmOutput is the ePWM pin type. //! \param output is the Action Qualifier output. //! //! This function triggers a continuous software forced Action Qualifier output //! on ePWM A or B based on the value of epwmOutput. //! Valid values for the parameters are: //! - epwmOutput //! - EPWM_AQ_OUTPUT_A - ePWMxA output //! - EPWM_AQ_OUTPUT_B - ePWMxB output //! - output //! - EPWM_AQ_SW_DISABLED - Software forcing disabled. //! - EPWM_AQ_OUTPUT_LOW - Set output pins to low //! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierContSWForceAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierSWOutput output) { ; // Initiate a Continuous software forced output if(epwmOutput == EPWM_AQ_OUTPUT_A) { (*((volatile uint16_t *)(base + 0x49U))) = (((*((volatile uint16_t *)(base + 0x49U))) & ~0x3U) | ((uint16_t)output)); } else { (*((volatile uint16_t *)(base + 0x49U))) = (((*((volatile uint16_t *)(base + 0x49U))) & ~0xCU) | ((uint16_t)output << 2U)) ; } } //***************************************************************************** // //! Set up one time software forced Action qualifier outputs //! //! \param base is the base address of the EPWM module. //! \param epwmOutput is the ePWM pin type. //! \param output is the Action Qualifier output. //! //! This function sets up the one time software forced Action Qualifier output //! on ePWM A or ePWMB, depending on the value of epwmOutput to a value //! specified by outPut. //! The following are valid values for the parameters. //! - epwmOutput //! - EPWM_AQ_OUTPUT_A - ePWMxA output //! - EPWM_AQ_OUTPUT_B - ePWMxB output //! - output //! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins //! - EPWM_AQ_OUTPUT_LOW - Set output pins to low //! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High //! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins //! //! \return None. // //***************************************************************************** static inline void EPWM_setActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output) { ; // Set the one time software forced action if(epwmOutput == EPWM_AQ_OUTPUT_A) { (*((volatile uint16_t *)(base + 0x47U))) = (((*((volatile uint16_t *)(base + 0x47U))) & ~0x3U) | ((uint16_t)output)); } else { (*((volatile uint16_t *)(base + 0x47U))) = (((*((volatile uint16_t *)(base + 0x47U))) & ~0x18U) | ((uint16_t)output << 3U)); } } //***************************************************************************** // //! Triggers a one time software forced event on Action qualifier //! //! \param base is the base address of the EPWM module. //! \param epwmOutput is the ePWM pin type. //! //! This function triggers a one time software forced Action Qualifier event //! on ePWM A or B based on the value of epwmOutput. //! Valid values for epwmOutput are: //! - EPWM_AQ_OUTPUT_A - ePWMxA output //! - EPWM_AQ_OUTPUT_B - ePWMxB output //! //! \return None. // //***************************************************************************** static inline void EPWM_forceActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput) { ; // Initiate a software forced event if(epwmOutput == EPWM_AQ_OUTPUT_A) { (*((volatile uint16_t *)(base + 0x47U))) |= 0x4U; } else { (*((volatile uint16_t *)(base + 0x47U))) |= 0x20U; } } // Dead Band //***************************************************************************** // //! Sets Dead Band signal output swap mode. //! //! \param base is the base address of the EPWM module. //! \param output is the ePWM Dead Band output. //! \param enableSwapMode is the output swap mode. //! //! This function sets up the output signal swap mode. For example if the //! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then //! the ePWM A output gets its signal from the ePWM B signal path. Valid values //! for the input variables are: //! output //! - EPWM_DB_OUTPUT_A - ePWM output A //! - EPWM_DB_OUTPUT_B - ePWM output B //! enableSwapMode //! - true - the output is swapped //! - false - the output and the signal path are the same. //! //! \return None. // //***************************************************************************** static inline void EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, _Bool enableSwapMode) { uint16_t mask; ; mask = (uint16_t)1U << ((uint16_t)output + 12U); if(enableSwapMode) { // Set the appropriate outswap bit to swap output (*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) | mask); } else { // Clear the appropriate outswap bit to disable output swap (*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) & ~mask); } } //***************************************************************************** // //! Sets Dead Band signal output mode. //! //! \param base is the base address of the EPWM module. //! \param delayMode is the Dead Band delay type. //! \param enableDelayMode is the dead band delay mode. //! //! This function sets up the dead band delay mode. The delayMode variable //! determines if the applied delay is Rising Edge or Falling Edge. The //! enableDelayMode determines if a dead band delay should be applied. //! Valid values for the variables are: //! delayMode //! - EPWM_DB_RED - Rising Edge delay //! - EPWM_DB_FED - Falling Edge delay //! enableDelayMode //! - true - Falling edge or Rising edge delay is applied. //! - false - Dead Band delay is bypassed. //! //! \return None. // //***************************************************************************** static inline void EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, _Bool enableDelayMode) { uint16_t mask; ; mask = 1U << ((uint16_t)(delayMode + 0U)); if(enableDelayMode) { // Set the appropriate outmode bit to enable Dead Band delay (*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) | mask); } else { // Clear the appropriate outswap bit to disable output swap (*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) & ~ mask); } } //***************************************************************************** // //! Sets Dead Band delay polarity. //! //! \param base is the base address of the EPWM module. //! \param delayMode is the Dead Band delay type. //! \param polarity is the polarity of the delayed signal. //! //! This function sets up the polarity as determined by the variable polarity //! of the Falling Edge or Rising Edge delay depending on the value of //! delayMode. Valid values for the variables are: //! delayMode //! - EPWM_DB_RED - Rising Edge delay //! - EPWM_DB_FED - Falling Edge delay //! polarity //! - EPWM_DB_POLARITY_ACTIVE_HIGH - polarity is not inverted. //! - EPWM_DB_POLARITY_ACTIVE_LOW - polarity is inverted. //! //! \return None. // //***************************************************************************** static inline void EPWM_setDeadBandDelayPolarity(uint32_t base, EPWM_DeadBandDelayMode delayMode, EPWM_DeadBandPolarity polarity) { uint16_t shift; ; shift = (((uint16_t)delayMode ^ 0x1U) + 2U); // Set the appropriate polsel bits for dead band polarity (*((volatile uint16_t *)(base + 0xCU))) = (((*((volatile uint16_t *)(base + 0xCU))) & ~ (1U << shift)) | ((uint16_t)polarity << shift)); } //***************************************************************************** // //! Sets Rising Edge Dead Band delay input. //! //! \param base is the base address of the EPWM module. //! \param input is the input signal to the dead band. //! //! This function sets up the rising Edge delay input signal. //! Valid values for input are: //! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA( Valid for both Falling //! Edge and Rising Edge) //! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMA( Valid for both Falling //! Edge and Rising Edge) //! //! \return None. // //***************************************************************************** static inline void EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) { ; ; // Set the Rising Edge Delay input (*((volatile uint16_t *)(base + 0xCU))) = (((*((volatile uint16_t *)(base + 0xCU))) & ~(1U << (4U))) | (input << 4U)); } //***************************************************************************** // //! Sets Dead Band delay input. //! //! \param base is the base address of the EPWM module. //! \param input is the input signal to the dead band. //! //! This function sets up the rising Edge delay input signal. //! Valid values for input are: //! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA(Valid for both Falling //! Edge and Rising Edge) //! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMA(Valid for both Falling //! Edge and Rising Edge) //! - EPWM_DB_INPUT_DB_RED - Input signal is the output of Rising //! Edge delay. //! (Valid only for Falling Edge delay) //! //! \return None. // //***************************************************************************** static inline void EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) { ; ; if(input == 2U) { // Set the Falling Edge Delay input (*((volatile uint16_t *)(base + 0xCU))) |= 0x4000U; } else { // Set the Falling Edge Delay input (*((volatile uint16_t *)(base + 0xCU))) &= ~0x4000U; // Set the Rising Edge Delay input (*((volatile uint16_t *)(base + 0xCU))) = (((*((volatile uint16_t *)(base + 0xCU))) & ~(1U << (4U + 1U))) | (input << (4U + 1U))); } } //***************************************************************************** // //! Set the Dead Band control shadow load mode. //! //! \param base is the base address of the EPWM module. //! \param loadMode is the shadow to active load mode. //! //! This function enables and sets the Dead Band control register shadow //! load mode. //! Valid values for the parameters are: //! loadMode //! - EPWM_DB_LOAD_ON_CNTR_ZERO - load when counter equals zero. //! - EPWM_DB_LOAD_ON_CNTR_PERIOD - load when counter equals period. //! - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or //! period. //! - EPWM_DB_LOAD_FREEZE - Freeze shadow to active load. //! //! \return None. // //***************************************************************************** static inline void EPWM_setDeadBandControlShadowLoadMode(uint32_t base, EPWM_DeadBandControlLoadMode loadMode) { ; // Check if shadow mode is enabled // Enable the shadow mode and setup the load event (*((volatile uint16_t *)(base + 0xDU))) = (((*((volatile uint16_t *)(base + 0xDU))) & ~0x3U) | (0x4U | (uint16_t)loadMode)); } //***************************************************************************** // //! Disable Dead Band control shadow load mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables the Dead Band control register shadow //! load mode. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableDeadBandControlShadowLoadMode(uint32_t base) { ; // Disable the shadow load mode. Only immediate load mode only. (*((volatile uint16_t *)(base + 0xDU))) = ((*((volatile uint16_t *)(base + 0xDU))) & ~0x4U); } //***************************************************************************** // //! Set the RED (Rising Edge Delay) shadow load mode. //! //! \param base is the base address of the EPWM module. //! \param loadMode is the shadow to active load event. //! //! This function sets the Rising Edge Delay register shadow load mode. //! Valid values for the parameters are: //! loadMode //! - EPWM_RED_LOAD_ON_CNTR_ZERO - load when counter equals zero. //! - EPWM_RED_LOAD_ON_CNTR_PERIOD - load when counter equals period. //! - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or //! period. //! - EPWM_RED_LOAD_FREEZE - Freeze shadow to active load. //! //! \return None. // //***************************************************************************** static inline void EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_RisingEdgeDelayLoadMode loadMode) { ; // Enable the shadow mode. Set-up the load mode (*((volatile uint16_t *)(base + 0xCU))) = (((*((volatile uint16_t *)(base + 0xCU))) & ~0xC0U) | ((uint16_t)0x400U | ((uint16_t)loadMode << 6U))); } //***************************************************************************** // //! Disable the RED (Rising Edge Delay) shadow load mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables the Rising Edge Delay register shadow load mode. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableRisingEdgeDelayCountShadowLoadMode (uint32_t base) { ; // Disable the shadow mode. (*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) & ~0x400U); } //***************************************************************************** // //! Set the FED (Falling Edge Delay) shadow load mode. //! //! \param base is the base address of the EPWM module. //! \param loadMode is the shadow to active load event. //! //! This function enables and sets the Falling Edge Delay register shadow load //! mode. Valid values for the parameters are: //! loadMode //! - EPWM_FED_LOAD_ON_CNTR_ZERO - load when counter equals zero. //! - EPWM_FED_LOAD_ON_CNTR_PERIOD - load when counter equals period. //! - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or //! period. //! - EPWM_FED_LOAD_FREEZE - Freeze shadow to active load. //! //! \return None. // //***************************************************************************** static inline void EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_FallingEdgeDelayLoadMode loadMode) { ; // Enable the shadow mode. Setup the load mode (*((volatile uint16_t *)(base + 0xCU))) = (((*((volatile uint16_t *)(base + 0xCU))) & ~0x300U) | (0x800U | ((uint16_t)loadMode << 8U))); } //***************************************************************************** // //! Disables the FED (Falling Edge Delay) shadow load mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables the Falling Edge Delay register shadow load mode. //! Valid values for the parameters are: //! //! \return None. // //***************************************************************************** static inline void EPWM_disableFallingEdgeDelayCountShadowLoadMode (uint32_t base) { ; // Disable the shadow mode. (*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) & ~0x800U); } //***************************************************************************** // //! Sets Dead Band Counter clock rate. //! //! \param base is the base address of the EPWM module. //! \param clockMode is the Dead Band counter clock mode. //! //! This function sets up the Dead Band counter clock rate with respect to //! TBCLK (ePWM time base counter). //! Valid values for clockMode are: //! - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE -Dead band counter runs at TBCLK //! (ePWM Time Base Counter) rate. //! - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE -Dead band counter runs at 2*TBCLK //! (twice ePWM Time Base Counter)rate. //! //! \return None. // //***************************************************************************** static inline void EPWM_setDeadBandCounterClock(uint32_t base, EPWM_DeadBandClockMode clockMode) { ; // Set the DB clock mode (*((volatile uint16_t *)(base + 0xCU))) = (((*((volatile uint16_t *)(base + 0xCU))) & ~0x8000U) | ((uint16_t)clockMode << 15U)); } //***************************************************************************** // //! Set ePWM RED count //! //! \param base is the base address of the EPWM module. //! \param redCount is the RED(Rising Edge Delay) count. //! //! This function sets the RED (Rising Edge Delay) count value. //! The value of redCount should be less than 0x4000U. //! //! \return None. // //***************************************************************************** static inline void EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount) { ; ; // Set the RED (Rising Edge Delay) count (*((volatile uint16_t *)(base + 0x51U))) = redCount; } //***************************************************************************** // //! Set ePWM FED count //! //! \param base is the base address of the EPWM module. //! \param fedCount is the FED(Falling Edge Delay) count. //! //! This function sets the FED (Falling Edge Delay) count value. //! The value of fedCount should be less than 0x4000U. //! //! \return None. // //***************************************************************************** static inline void EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount) { ; ; // Set the RED (Rising Edge Delay) count (*((volatile uint16_t *)(base + 0x53U))) = fedCount; } // Chopper //***************************************************************************** // //! Enable chopper mode //! //! \param base is the base address of the EPWM module. //! //! This function enables ePWM chopper module. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableChopper(uint32_t base) { ; // Set CHPEN bit. Enable Chopper (*((volatile uint16_t *)(base + 0x14U))) |= 0x1U; } //***************************************************************************** // //! Disable chopper mode //! //! \param base is the base address of the EPWM module. //! //! This function disables ePWM chopper module. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableChopper(uint32_t base) { ; // Clear CHPEN bit. Disable Chopper (*((volatile uint16_t *)(base + 0x14U))) &= ~0x1U; } //***************************************************************************** // //! Set chopper duty cycle. //! //! \param base is the base address of the EPWM module. //! \param dutyCycleCount is the chopping clock duty cycle count. //! //! This function sets the chopping clock duty cycle. The value of //! dutyCycleCount should be less than 7. The dutyCycleCount value is converted //! to the actual chopper duty cycle value base on the following equation: //! chopper duty cycle = (dutyCycleCount + 1) / 8 //! //! \return None. // //***************************************************************************** static inline void EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount) { ; ; // Set the chopper duty cycle (*((volatile uint16_t *)(base + 0x14U))) = (((*((volatile uint16_t *)(base + 0x14U))) & ~0x700U) | (dutyCycleCount << 8U)); } //***************************************************************************** // //! Set chopper clock frequency scaler. //! //! \param base is the base address of the EPWM module. //! \param freqDiv is the chopping clock frequency divider. //! //! This function sets the scaler for the chopping clock frequency. The value //! of freqDiv should be less than 8. The chopping clock frequency is altered //! based on the following equation. //! chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv) //! //! \return None. // //***************************************************************************** static inline void EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv) { ; ; // Set the chopper clock (*((volatile uint16_t *)(base + 0x14U))) = (((*((volatile uint16_t *)(base + 0x14U))) & ~(uint16_t)0xE0U) | (freqDiv << 5U)); } //***************************************************************************** // //! Set chopper clock frequency scaler. //! //! \param base is the base address of the EPWM module. //! \param firstPulseWidth is the width of the first pulse. //! //! This function sets the first pulse width of chopper output waveform. The //! value of firstPulseWidth should be less than 0x10. The value of the first //! pulse width in seconds is given using the following equation: //! first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8) //! //! \return None. // //***************************************************************************** static inline void EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth) { ; ; // Set the chopper clock (*((volatile uint16_t *)(base + 0x14U))) = (((*((volatile uint16_t *)(base + 0x14U))) & ~(uint16_t)0x1EU) | (firstPulseWidth << 1U)); } // Trip Zone functions //***************************************************************************** // //! Enables Trip Zone signal. //! //! \param base is the base address of the EPWM module. //! \param tzSignal is the Trip Zone signal. //! //! This function enables the Trip Zone signals specified by tzSignal as a //! source for the Trip Zone module. //! Valid values for tzSignal are: //! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle //! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle //! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle //! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 //! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 //! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 //! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 //! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 //! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 //! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 //! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 //! //! \b note: A logical OR of the valid values can be passed as the tzSignal //! parameter. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal) { ; __eallow(); // Set the trip zone bits (*((volatile uint16_t *)(base + 0x80U))) |= tzSignal; __edis(); } //***************************************************************************** // //! Disables Trip Zone signal. //! //! \param base is the base address of the EPWM module. //! \param tzSignal is the Trip Zone signal. //! //! This function disables the Trip Zone signal specified by tzSignal as a //! source for the Trip Zone module. //! Valid values for tzSignal are: //! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle //! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle //! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle //! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle //! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 //! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 //! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 //! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 //! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 //! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 //! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 //! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 //! //! \b note: A logical OR of the valid values can be passed as the tzSignal //! parameter. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal) { ; __eallow(); // Clear the trip zone bits (*((volatile uint16_t *)(base + 0x80U))) &= ~tzSignal; __edis(); } //***************************************************************************** // //! Set Digital compare conditions that cause Trip Zone event. //! //! \param base is the base address of the EPWM module. //! \param dcType is the Digital compare output type. //! \param dcEvent is the Digital Compare output event. //! //! This function sets up the Digital Compare output Trip Zone event sources. //! The dcType variable specifies the event source to be whether Digital //! Compare output A or Digital Compare output B. The dcEvent parameter //! specifies the event that causes Trip Zone. //! Valid values for the parameters are: //! dcType //! - EPWM_TZ_DC_OUTPUT_A1 - Digital Compare output 1 A //! - EPWM_TZ_DC_OUTPUT_A2 - Digital Compare output 2 A //! - EPWM_TZ_DC_OUTPUT_B1 - Digital Compare output 1 B //! - EPWM_TZ_DC_OUTPUT_B2 - Digital Compare output 2 B //! dcEvent //! - EPWM_TZ_EVENT_DC_DISABLED - Event Trigger is disabled //! - EPWM_TZ_EVENT_DCXH_LOW - Trigger event when DCxH low //! - EPWM_TZ_EVENT_DCXH_HIGH - Trigger event when DCxH high //! - EPWM_TZ_EVENT_DCXL_LOW - Trigger event when DCxL low //! - EPWM_TZ_EVENT_DCXL_HIGH - Trigger event when DCxL high //! - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW - Trigger event when DCxL high //! DCxH low //! //! \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL //! //! \return None. // //***************************************************************************** static inline void EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, EPWM_TripZoneDigitalCompareOutput dcType, EPWM_TripZoneDigitalCompareOutputEvent dcEvent) { ; __eallow(); // Set Digital Compare Events conditions that cause a Digital Compare trip (*((volatile uint16_t *)(base + 0x82U))) = (((*((volatile uint16_t *)(base + 0x82U))) & ~(0x7U << (uint16_t)dcType)) | ((uint16_t)dcEvent << (uint16_t)dcType)); __edis(); } //***************************************************************************** // //! Enable advanced Trip Zone event Action. //! //! \param base is the base address of the EPWM module. //! //! This function enables the advanced actions of the Trip Zone events. The //! advanced features combine the trip zone events with the direction of the //! counter. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableTripZoneAdvAction(uint32_t base) { ; __eallow(); // Enable Advanced feature. Set ETZE bit (*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Disable advanced Trip Zone event Action. //! //! \param base is the base address of the EPWM module. //! //! This function disables the advanced actions of the Trip Zone events. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableTripZoneAdvAction(uint32_t base) { ; __eallow(); // Disable Advanced feature. clear ETZE bit (*((volatile uint16_t *)(base + 0x85U))) &= ~0x8000U; __edis(); } //***************************************************************************** // //! Set Trip Zone Action. //! //! \param base is the base address of the EPWM module. //! \param tzEvent is the Trip Zone event type. //! \param tzAction is the Trip zone Action. //! //! This function sets the Trip Zone Action to be taken when a Trip Zone event //! occurs. //! Valid values for the parameters are: //! tzEvent //! - EPWM_TZ_ACTION_EVENT_DCBEVT2 - DCBEVT2 (Digital Compare B event 2) //! - EPWM_TZ_ACTION_EVENT_DCBEVT1 - DCBEVT1 (Digital Compare B event 1) //! - EPWM_TZ_ACTION_EVENT_DCAEVT2 - DCAEVT2 (Digital Compare A event 2) //! - EPWM_TZ_ACTION_EVENT_DCAEVT1 - DCAEVT1 (Digital Compare A event 1) //! - EPWM_TZ_ACTION_EVENT_TZB - TZ1 - TZ6, DCBEVT2, DCBEVT1 //! - EPWM_TZ_ACTION_EVENT_TZA - TZ1 - TZ6, DCAEVT2, DCAEVT1 //! tzAction //! - EPWM_TZ_ACTION_HIGH_Z - high impedance output //! - EPWM_TZ_ACTION_HIGH - high output //! - EPWM_TZ_ACTION_LOW - low low //! - EPWM_TZ_ACTION_DISABLE - disable action //! //! \note Disable the advanced Trip Zone event using //! EPWM_disableTripZoneAdvAction() before calling this function. //! \note This function operates on both ePWMA and ePWMB depending on the //! tzEvent parameter. //! //! \return None. // //***************************************************************************** static inline void EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, EPWM_TripZoneAction tzAction) { ; __eallow(); // Set the Action for Trip Zone events (*((volatile uint16_t *)(base + 0x84U))) = (((*((volatile uint16_t *)(base + 0x84U))) & ~(0x3U << (uint16_t)tzEvent)) | ((uint16_t)tzAction << (uint16_t)tzEvent)) ; __edis(); } //***************************************************************************** // //! Set Advanced Trip Zone Action. //! //! \param base is the base address of the EPWM module. //! \param tzAdvEvent is the Trip Zone event type. //! \param tzAdvAction is the Trip zone Action. //! //! This function sets the Advanced Trip Zone Action to be taken when an //! advanced Trip Zone event occurs. //! //! Valid values for the parameters are: //! tzAdvEvent //! - EPWM_TZ_ADV_ACTION_EVENT_TZB_D - TZ1 - TZ6, DCBEVT2, DCBEVT1 while //! counting down //! - EPWM_TZ_ADV_ACTION_EVENT_TZB_U - TZ1 - TZ6, DCBEVT2, DCBEVT1 while //! counting up //! - EPWM_TZ_ADV_ACTION_EVENT_TZA_D - TZ1 - TZ6, DCAEVT2, DCAEVT1 while //! counting down //! - EPWM_TZ_ADV_ACTION_EVENT_TZA_U - TZ1 - TZ6, DCAEVT2, DCAEVT1 while //! counting up //! tzAdvAction //! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output //! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state //! - EPWM_TZ_ADV_ACTION_LOW - low voltage state //! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output //! - EPWM_TZ_ADV_ACTION_DISABLE - disable action //! //! \note This function enables the advanced Trip Zone event. //! //! \note This function operates on both ePWMA and ePWMB depending on the //! tzAdvEvent parameter. //! \note Advanced Trip Zone events take into consideration the direction of //! the counter in addition to Trip Zone events. //! //! \return None. // //***************************************************************************** static inline void EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, EPWM_TripZoneAdvancedAction tzAdvAction) { ; __eallow(); // Set the Advanced Action for Trip Zone events (*((volatile uint16_t *)(base + 0x85U))) = (((*((volatile uint16_t *)(base + 0x85U))) & ~(0x7U << (uint16_t)tzAdvEvent)) | ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)); (*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Set Advanced Digital Compare Trip Zone Action on ePWMA. //! //! \param base is the base address of the EPWM module. //! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. //! \param tzAdvDCAction is the Digital Compare Trip zone Action. //! //! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be //! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs. //! Valid values for the parameters are: //! tzAdvDCEvent //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event A2 while //! counting down //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event A2 while //! counting up //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event A1 while //! counting down //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event A1 while //! counting up //! tzAdvDCAction //! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output //! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state //! - EPWM_TZ_ADV_ACTION_LOW - low voltage state //! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output //! - EPWM_TZ_ADV_ACTION_DISABLE - disable action //! //! \note This function enables the advanced Trip Zone event. //! //! \note Advanced Trip Zone events take into consideration the direction of //! the counter in addition to Digital Compare Trip Zone events. //! //! \return None. // //***************************************************************************** static inline void EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction) { ; __eallow(); // Set the Advanced Action for Trip Zone events (*((volatile uint16_t *)(base + 0x86U))) = (((*((volatile uint16_t *)(base + 0x86U))) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); (*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Set Advanced Digital Compare Trip Zone Action on ePWMB. //! //! \param base is the base address of the EPWM module. //! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. //! \param tzAdvDCAction is the Digital Compare Trip zone Action. //! //! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be //! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs. //! Valid values for the parameters are: //! tzAdvDCEvent //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event B2 while //! counting down //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event B2 while //! counting up //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event B1 while //! counting down //! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event B1 while //! counting up //! tzAdvDCAction //! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output //! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state //! - EPWM_TZ_ADV_ACTION_LOW - low voltage state //! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output //! - EPWM_TZ_ADV_ACTION_DISABLE - disable action //! //! \note This function enables the advanced Trip Zone event. //! //! \note Advanced Trip Zone events take into consideration the direction of //! the counter in addition to Digital Compare Trip Zone events. //! //! \return None. // //***************************************************************************** static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction) { ; __eallow(); // Set the Advanced Action for Trip Zone events (*((volatile uint16_t *)(base + 0x87U))) = (((*((volatile uint16_t *)(base + 0x87U))) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); (*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Enable Trip Zone interrupts. //! //! \param base is the base address of the EPWM module. //! \param tzInterrupt is the Trip Zone interrupt. //! //! This function enables the Trip Zone interrupts. //! Valid values for tzInterrupt are: //! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt //! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt //! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt //! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt //! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt //! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt //! //! \b note: A logical OR of the valid values can be passed as the tzInterrupt //! parameter. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) { ; ; __eallow(); // Enable Trip zone interrupts (*((volatile uint16_t *)(base + 0x8DU))) |= tzInterrupt; __edis(); } //***************************************************************************** // //! Disable Trip Zone interrupts. //! //! \param base is the base address of the EPWM module. //! \param tzInterrupt is the Trip Zone interrupt. //! //! This function disables the Trip Zone interrupts. //! Valid values for tzInterrupt are: //! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt //! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt //! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt //! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt //! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt //! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt //! //! \b note: A logical OR of the valid values can be passed as the tzInterrupt //! parameter. //! //! \return None. // //*************************************************************************** static inline void EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) { ; ; __eallow(); // Disable Trip zone interrupts (*((volatile uint16_t *)(base + 0x8DU))) &= ~tzInterrupt; __edis(); } //***************************************************************************** // //! Gets the Trip Zone status flag //! //! \param base is the base address of the EPWM module. //! //! This function returns the Trip Zone status flag. //! //! \return The function returns the following or the bitwise OR value //! of the following values. //! - EPWM_TZ_INTERRUPT - Trip Zone interrupt was generated //! due to the following TZ events. //! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle event status flag //! - EPWM_TZ_FLAG_OST - Trip Zones One Shot event status flag //! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag //! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag //! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag //! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag // //*************************************************************************** static inline uint16_t EPWM_getTripZoneFlagStatus(uint32_t base) { ; // Return the Trip zone flag status return((*((volatile uint16_t *)(base + 0x93U))) & 0x7FU); } //***************************************************************************** // //! Gets the Trip Zone Cycle by Cycle flag status //! //! \param base is the base address of the EPWM module. //! //! This function returns the specific Cycle by Cycle Trip Zone flag //! status. //! //! \return The function returns the following values. //! - EPWM_TZ_CBC_FLAG_1 - CBC 1 status flag //! - EPWM_TZ_CBC_FLAG_2 - CBC 2 status flag //! - EPWM_TZ_CBC_FLAG_3 - CBC 3 status flag //! - EPWM_TZ_CBC_FLAG_4 - CBC 4 status flag //! - EPWM_TZ_CBC_FLAG_5 - CBC 5 status flag //! - EPWM_TZ_CBC_FLAG_6 - CBC 6 status flag //! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC status flag for Digital compare //! event A2 //! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC status flag for Digital compare //! event B2 // //*************************************************************************** static inline uint16_t EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base) { ; // Return the Cycle By Cycle Trip zone flag status return((*((volatile uint16_t *)(base + 0x94U))) & 0xFFU); } //***************************************************************************** // //! Gets the Trip Zone One Shot flag status //! //! \param base is the base address of the EPWM module. //! //! This function returns the specific One Shot Trip Zone flag status. //! //! \return The function returns the bitwise OR of the following flags. //! - EPWM_TZ_OST_FLAG_OST1 - OST status flag for OST1 //! - EPWM_TZ_OST_FLAG_OST2 - OST status flag for OST2 //! - EPWM_TZ_OST_FLAG_OST3 - OST status flag for OST3 //! - EPWM_TZ_OST_FLAG_OST4 - OST status flag for OST4 //! - EPWM_TZ_OST_FLAG_OST5 - OST status flag for OST5 //! - EPWM_TZ_OST_FLAG_OST6 - OST status flag for OST6 //! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST status flag for Digital //! compare event A1 //! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST status flag for Digital //! compare event B1 // //*************************************************************************** static inline uint16_t EPWM_getOneShotTripZoneFlagStatus(uint32_t base) { ; // Return the One Shot Trip zone flag status return((*((volatile uint16_t *)(base + 0x95U))) & 0xFFU); } //***************************************************************************** // //! Set the Trip Zone CBC pulse clear event. //! //! \param base is the base address of the EPWM module. //! \param clearEvent is the CBC trip zone clear event. //! //! This function set the event which automatically clears the //! CBC (Cycle by Cycle) latch. //! Valid values for clearEvent are: //! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO - Clear CBC pulse when counter //! equals zero //! - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD - Clear CBC pulse when counter //! equals period //! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD - Clear CBC pulse when counter //! equals zero or period //! //! \return None. // //************************************************************************** static inline void EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, EPWM_CycleByCycleTripZoneClearMode clearEvent) { ; __eallow(); // Set the Cycle by Cycle Trip Latch mode (*((volatile uint16_t *)(base + 0x97U))) = (((*((volatile uint16_t *)(base + 0x97U))) & ~0xC000U) | ((uint16_t)clearEvent << 14U)); __edis(); } //***************************************************************************** // //! Clear Trip Zone flag //! //! \param base is the base address of the EPWM module. //! \param tzFlags is the Trip Zone flags. //! //! This function clears the Trip Zone flags //! Valid values for tzFlags are: //! - EPWM_TZ_INTERRUPT - Global Trip Zone interrupt flag //! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle flag //! - EPWM_TZ_FLAG_OST - Trip Zones One Shot flag //! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag //! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag //! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag //! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag //! //! \b note: A bitwise OR of the valid values can be passed as the tzFlags //! parameter. //! //! //! \return None. // //*************************************************************************** static inline void EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags) { ; ; __eallow(); // Clear Trip zone event flag (*((volatile uint16_t *)(base + 0x97U))) |= tzFlags; __edis(); } //***************************************************************************** // //! Clear the Trip Zone Cycle by Cycle flag. //! //! \param base is the base address of the EPWM module. //! \param tzCBCFlags is the CBC flag to be cleared. //! //! This function clears the specific Cycle by Cycle Trip Zone flag. //! The following are valid values for tzCBCFlags. //! - EPWM_TZ_CBC_FLAG_1 - CBC 1 flag //! - EPWM_TZ_CBC_FLAG_2 - CBC 2 flag //! - EPWM_TZ_CBC_FLAG_3 - CBC 3 flag //! - EPWM_TZ_CBC_FLAG_4 - CBC 4 flag //! - EPWM_TZ_CBC_FLAG_5 - CBC 5 flag //! - EPWM_TZ_CBC_FLAG_6 - CBC 6 flag //! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC flag Digital compare //! event A2 //! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC flag Digital compare //! event B2 //! //! \return None. // //*************************************************************************** static inline void EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags) { ; ; __eallow(); // Clear the Cycle By Cycle Trip zone flag (*((volatile uint16_t *)(base + 0x98U))) |= tzCBCFlags; __edis(); } //***************************************************************************** // //! Clear the Trip Zone One Shot flag. //! //! \param base is the base address of the EPWM module. //! \param tzOSTFlags is the OST flags to be cleared. //! //! This function clears the specific One Shot (OST) Trip Zone flag. //! The following are valid values for tzOSTFlags. //! - EPWM_TZ_OST_FLAG_OST1 - OST flag for OST1 //! - EPWM_TZ_OST_FLAG_OST2 - OST flag for OST2 //! - EPWM_TZ_OST_FLAG_OST3 - OST flag for OST3 //! - EPWM_TZ_OST_FLAG_OST4 - OST flag for OST4 //! - EPWM_TZ_OST_FLAG_OST5 - OST flag for OST5 //! - EPWM_TZ_OST_FLAG_OST6 - OST flag for OST6 //! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST flag for Digital compare event A1 //! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST flag for Digital compare event B1 //! //! \return None. // //*************************************************************************** static inline void EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags) { ; ; __eallow(); // Clear the Cycle By Cycle Trip zone flag (*((volatile uint16_t *)(base + 0x99U))) |= tzOSTFlags; __edis(); } //***************************************************************************** // //! Force Trip Zone events. //! //! \param base is the base address of the EPWM module. //! \param tzForceEvent is the forced Trip Zone event. //! //! This function forces a Trip Zone event. //! Valid values for tzForceEvent are: //! - EPWM_TZ_FORCE_EVENT_CBC - Force Trip Zones Cycle By Cycle event //! - EPWM_TZ_FORCE_EVENT_OST - Force Trip Zones One Shot Event //! - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1 //! - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2 //! - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1 //! - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2 //! //! \return None. // //*************************************************************************** static inline void EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent) { ; ; __eallow(); // Force a Trip Zone event (*((volatile uint16_t *)(base + 0x9BU))) |= tzForceEvent; __edis(); } // Event Trigger //***************************************************************************** // //! Enable ePWM interrupt. //! //! \param base is the base address of the EPWM module. //! //! This function enables the ePWM interrupt. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableInterrupt(uint32_t base) { ; // enable ePWM interrupt (*((volatile uint16_t *)(base + 0xA4U))) |= 0x8U; } //***************************************************************************** // //! disable ePWM interrupt. //! //! \param base is the base address of the EPWM module. //! //! This function disables the ePWM interrupt. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableInterrupt(uint32_t base) { ; // disable ePWM interrupt (*((volatile uint16_t *)(base + 0xA4U))) &= ~0x8U; } //***************************************************************************** // //! Sets the ePWM interrupt source. //! //! \param base is the base address of the EPWM module. //! \param interruptSource is the ePWM interrupt source. //! //! This function sets the ePWM interrupt source. //! Valid values for interruptSource are: //! - EPWM_INT_TBCTR_ZERO - Time-base counter equal to zero //! - EPWM_INT_TBCTR_PERIOD - Time-base counter equal to period //! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or //! period //! - EPWM_INT_TBCTR_U_CMPx - Where x is A,B,C or D //! Time-base counter equal to CMPA, CMPB, //! CMPC or CMPD (depending the value of x) //! when the timer is incrementing //! - EPWM_INT_TBCTR_D_CMPx - Where x is A,B,C or D //! Time-base counter equal to CMPA, CMPB, //! CMPC or CMPD (depending the value of x) //! when the timer is decrementing //! //! \return None. // //***************************************************************************** static inline void EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource) { uint16_t intSource; ; ; if((interruptSource == 8U) || (interruptSource == 12U) || (interruptSource == 10U) || (interruptSource == 14U)) { // Shift the interrupt source by 1 intSource = interruptSource >> 1U; // Enable events based on comp C or comp D (*((volatile uint16_t *)(base + 0xA4U))) |= 0x40U; } else if((interruptSource == 4U) || (interruptSource == 6U) || (interruptSource == 5U) || (interruptSource == 7U)) { intSource = interruptSource; // Enable events based on comp A or comp B (*((volatile uint16_t *)(base + 0xA4U))) &= ~0x40U; } else { intSource = interruptSource; } // Set the interrupt source (*((volatile uint16_t *)(base + 0xA4U))) = (((*((volatile uint16_t *)(base + 0xA4U))) & ~0x7U) | intSource); } //***************************************************************************** // //! Sets the ePWM interrupt event counts. //! //! \param base is the base address of the EPWM module. //! \param eventCount is the event count for interrupt scale //! //! This function sets the interrupt event count that determines the number of //! events that have to occur before an interrupt is issued. //! Maximum value for eventCount is 15. //! //! \return None. // //***************************************************************************** static inline void EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount) { ; ; // Enable advanced feature of interrupt every up to 15 events (*((volatile uint16_t *)(base + 0xA6U))) |= 0x10U; (*((volatile uint16_t *)(base + 0xAEU))) = (((*((volatile uint16_t *)(base + 0xAEU))) & ~0xFU) | eventCount); } //***************************************************************************** // //! Return the interrupt status. //! //! \param base is the base address of the EPWM module. //! //! This function returns the ePWM interrupt status. //! \b Note This function doesn't return the Trip Zone status. //! //! \return Returns true if ePWM interrupt was generated. //! Returns false if no interrupt was generated // //***************************************************************************** static inline _Bool EPWM_getEventTriggerInterruptStatus(uint32_t base) { ; // Return INT bit of ETFLG register return((((*((volatile uint16_t *)(base + 0xA8U))) & 0x1U) == 0x1U) ? 1 : 0); } //***************************************************************************** // //! Clear interrupt flag. //! //! \param base is the base address of the EPWM module. //! //! This function clears the ePWM interrupt flag. //! //! \return None // //***************************************************************************** static inline void EPWM_clearEventTriggerInterruptFlag(uint32_t base) { ; // clear INT bit of ETCLR register (*((volatile uint16_t *)(base + 0xAAU))) |= 0x1U; } //***************************************************************************** // //! Enable Pre-interrupt count load. //! //! \param base is the base address of the EPWM module. //! //! This function enables the ePWM interrupt counter to be pre-interrupt loaded //! with a count value. //! //! \note This is valid only for advanced/expanded interrupt mode //! //! \return None. // //***************************************************************************** static inline void EPWM_enableInterruptEventCountInit(uint32_t base) { ; // Enable interrupt event count initializing/loading (*((volatile uint16_t *)(base + 0xB2U))) |= 0x2000U; } //***************************************************************************** // //! Disable interrupt count load. //! //! \param base is the base address of the EPWM module. //! //! This function disables the ePWM interrupt counter from being loaded with //! pre-interrupt count value. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableInterruptEventCountInit(uint32_t base) { ; // disable interrupt event count initializing/loading (*((volatile uint16_t *)(base + 0xB2U))) &= ~0x2000U; } //***************************************************************************** // //! Force a software pre interrupt event counter load. //! //! \param base is the base address of the EPWM module. //! //! This function forces the ePWM interrupt counter to be loaded with the //! contents set by EPWM_setPreInterruptEventCount(). //! //! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is //! is called before invoking this function. //! //! \return None. // //***************************************************************************** static inline void EPWM_forceInterruptEventCountInit(uint32_t base) { ; // Load the Interrupt Event counter value (*((volatile uint16_t *)(base + 0xB2U))) |= 0x400U; } //***************************************************************************** // //! Set interrupt count. //! //! \param base is the base address of the EPWM module. //! \param eventCount is the ePWM interrupt count value. //! //! This function sets the ePWM interrupt count. eventCount is the value of the //! pre-interrupt value that is to be loaded. The maximum value of eventCount //! is 15. //! //! \return None. // //***************************************************************************** static inline void EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount) { ; ; // Set the Pre-interrupt event count (*((volatile uint16_t *)(base + 0xB4U))) = (((*((volatile uint16_t *)(base + 0xB4U))) & ~0xFU) | (uint16_t)(eventCount & 0xFU)); } //***************************************************************************** // //! Get the interrupt count. //! //! \param base is the base address of the EPWM module. //! //! This function returns the ePWM interrupt event count. //! //! \return The interrupt event counts that have occurred. // //***************************************************************************** static inline uint16_t EPWM_getInterruptEventCount(uint32_t base) { ; // Return the interrupt event count return((((*((volatile uint16_t *)(base + 0xAEU))) & 0xF0U) >> 4U)); } //***************************************************************************** // //! Force ePWM interrupt. //! //! \param base is the base address of the EPWM module. //! //! This function forces an ePWM interrupt. //! //! \return None // //***************************************************************************** static inline void EPWM_forceEventTriggerInterrupt(uint32_t base) { ; // Set INT bit of ETFRC register (*((volatile uint16_t *)(base + 0xACU))) |= 0x1U; } // SOC //***************************************************************************** // //! Enable ADC SOC event. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function enables the ePWM module to trigger an ADC SOC event. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \return None. // //***************************************************************************** static inline void EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // enable an SOC if(adcSOCType == EPWM_SOC_A) { (*((volatile uint16_t *)(base + 0xA4U))) |= 0x800U; } else { (*((volatile uint16_t *)(base + 0xA4U))) |= 0x8000U; } } //***************************************************************************** // //! Disable ADC SOC event. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function disables the ePWM module from triggering an ADC SOC event. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \return None. // //***************************************************************************** static inline void EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // disable an SOC if(adcSOCType == EPWM_SOC_A) { (*((volatile uint16_t *)(base + 0xA4U))) &= ~0x800U; } else { (*((volatile uint16_t *)(base + 0xA4U))) &= ~0x8000U; } } //***************************************************************************** // //! Sets the ePWM SOC source. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! \param socSource is the SOC source. //! //! This function sets the ePWM ADC SOC source. //! Valid values for socSource are: //! adcSOCType //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! socSource //! - EPWM_SOC_DCxEVT1 - Event is based on DCxEVT1 //! - EPWM_SOC_TBCTR_ZERO - Time-base counter equal to zero //! - EPWM_SOC_TBCTR_PERIOD - Time-base counter equal to period //! - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or //! period //! - EPWM_SOC_TBCTR_U_CMPx - Where x is A,B,C or D //! Time-base counter equal to CMPA, CMPB, //! CMPC or CMPD(depending the value of x) //! when the timer is incrementing //! - EPWM_SOC_TBCTR_D_CMPx - Where x is A,B,C or D //! Time-base counter equal to CMPA, CMPB, //! CMPC or CMPD(depending the value of x) //! when the timer is decrementing //! //! \return None. // //***************************************************************************** static inline void EPWM_setADCTriggerSource(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, EPWM_ADCStartOfConversionSource socSource) { uint16_t source; ; if((socSource == EPWM_SOC_TBCTR_U_CMPC) || (socSource == EPWM_SOC_TBCTR_U_CMPD) || (socSource == EPWM_SOC_TBCTR_D_CMPC) || (socSource == EPWM_SOC_TBCTR_D_CMPD)) { source = (uint16_t)socSource >> 1U; } else { source = (uint16_t)socSource; } if(adcSOCType == EPWM_SOC_A) { // Set the SOC source (*((volatile uint16_t *)(base + 0xA4U))) = (((*((volatile uint16_t *)(base + 0xA4U))) & ~0x700U) | (source << 8U)); // Enable the comparator selection if((socSource == EPWM_SOC_TBCTR_U_CMPA) || (socSource == EPWM_SOC_TBCTR_U_CMPB) || (socSource == EPWM_SOC_TBCTR_D_CMPA) || (socSource == EPWM_SOC_TBCTR_D_CMPB)) { // Enable events based on comp A or comp B (*((volatile uint16_t *)(base + 0xA4U))) &= ~0x10U; } else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || (socSource == EPWM_SOC_TBCTR_U_CMPD) || (socSource == EPWM_SOC_TBCTR_D_CMPC) || (socSource == EPWM_SOC_TBCTR_D_CMPD)) { // Enable events based on comp C or comp D (*((volatile uint16_t *)(base + 0xA4U))) |= 0x10U; } else { ; // No action required for the other socSource options } } else { // Enable the comparator selection (*((volatile uint16_t *)(base + 0xA4U))) = (((*((volatile uint16_t *)(base + 0xA4U))) & ~0x7000U) | (source << 12U)); // Enable the comparator selection if((socSource == EPWM_SOC_TBCTR_U_CMPA) || (socSource == EPWM_SOC_TBCTR_U_CMPB) || (socSource == EPWM_SOC_TBCTR_D_CMPA) || (socSource == EPWM_SOC_TBCTR_D_CMPB)) { // Enable events based on comp A or comp B (*((volatile uint16_t *)(base + 0xA4U))) &= ~0x20U; } else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || (socSource == EPWM_SOC_TBCTR_U_CMPD) || (socSource == EPWM_SOC_TBCTR_D_CMPC) || (socSource == EPWM_SOC_TBCTR_D_CMPD)) { // Enable events based on comp C or comp D (*((volatile uint16_t *)(base + 0xA4U))) |= 0x20U; } else { ; // No action required for the other socSource options } } } //***************************************************************************** // //! Sets the ePWM SOC event counts. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! \param preScaleCount is the event count number. //! //! This function sets the SOC event count that determines the number of //! events that have to occur before an SOC is issued. //! Valid values for the parameters are: //! adcSOCType //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! preScaleCount //! - [1 - 15] - Generate SOC pulse every preScaleCount //! upto 15 events. //! \b Note. A preScaleCount value of 0 disables the presale. //! //! \return None. // //***************************************************************************** static inline void EPWM_setADCTriggerEventPrescale(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t preScaleCount) { ; ; // Enable advanced feature of SOC every up to 15 events (*((volatile uint16_t *)(base + 0xA6U))) |= 0x20U; if(adcSOCType == EPWM_SOC_A) { // set the count for SOC A (*((volatile uint16_t *)(base + 0xB0U))) = (((*((volatile uint16_t *)(base + 0xB0U))) & ~0xFU) | preScaleCount); } else { // set the count for SOC B (*((volatile uint16_t *)(base + 0xB0U))) = (((*((volatile uint16_t *)(base + 0xB0U))) & ~0xF00U) | (preScaleCount << 8U)); } } //***************************************************************************** // //! Return the SOC event status. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function returns the ePWM SOC status. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \return Returns true if the selected adcSOCType SOC was generated. //! Returns false if the selected adcSOCType SOC was not generated. // //***************************************************************************** static inline _Bool EPWM_getADCTriggerFlagStatus(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // Return the SOC A/ B status return(((((*((volatile uint16_t *)(base + 0xA8U))) >> ((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? 1 : 0); } //***************************************************************************** // //! Clear SOC flag. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function clears the ePWM SOC flag. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \return None // //***************************************************************************** static inline void EPWM_clearADCTriggerFlag(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // clear SOC A/B bit of ETCLR register (*((volatile uint16_t *)(base + 0xAAU))) |= 1U << ((uint16_t)adcSOCType + 2U); } //***************************************************************************** // //! Enable Pre-SOC event count load. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function enables the ePWM SOC event counter which is set by the //! EPWM_setADCTriggerEventCountInitValue() function to be loaded before //! an SOC event. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \note This is valid only for advanced/expanded SOC mode //! //! \return None. // //***************************************************************************** static inline void EPWM_enableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // Enable SOC event count initializing/loading (*((volatile uint16_t *)(base + 0xB2U))) |= 1U << ((uint16_t)adcSOCType + 14U); } //***************************************************************************** // //! Disable Pre-SOC event count load. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function disables the ePWM SOC event counter from being loaded before //! an SOC event (only an SOC event causes an increment of the counter value). //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \note This is valid only for advanced/expanded SOC mode //! //! \return None. // //***************************************************************************** static inline void EPWM_disableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // disable SOC event count initializing/loading (*((volatile uint16_t *)(base + 0xB2U))) &= ~(1U << ((uint16_t)adcSOCType + 14U)); } //***************************************************************************** // //! Force a software pre SOC event counter load. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type //! //! This function forces the ePWM SOC counter to be loaded with the //! contents set by EPWM_setPreADCStartOfConversionEventCount(). //! //! \note make sure the EPWM_enableADCTriggerEventCountInit() //! function is called before invoking this function. //! //! \return None. // //***************************************************************************** static inline void EPWM_forceADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // Load the Interrupt Event counter value (*((volatile uint16_t *)(base + 0xB2U))) |= 1U << ((uint16_t)adcSOCType + 11U); } //***************************************************************************** // //! Set ADC Trigger count values. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! \param eventCount is the ePWM interrupt count value. //! //! This function sets the ePWM ADC Trigger count values. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! The eventCount has a maximum value of 15. //! //! \return None. // //***************************************************************************** static inline void EPWM_setADCTriggerEventCountInitValue(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t eventCount) { ; ; // Set the ADC Trigger event count if(adcSOCType == EPWM_SOC_A) { (*((volatile uint16_t *)(base + 0xB4U))) = (((*((volatile uint16_t *)(base + 0xB4U))) & ~0xF0U) | (uint16_t)(eventCount << 4U)); } else { (*((volatile uint16_t *)(base + 0xB4U))) = (((*((volatile uint16_t *)(base + 0xB4U))) & ~0xF00U) | (eventCount << 8U)); } } //***************************************************************************** // //! Get the SOC event count. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function returns the ePWM SOC event count. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \return The SOC event counts that have occurred. // //***************************************************************************** static inline uint16_t EPWM_getADCTriggerEventCount(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { uint16_t eventCount; ; // Return the SOC event count if(adcSOCType == EPWM_SOC_A) { eventCount = ((*((volatile uint16_t *)(base + 0xB0U))) >> 4U) & 0xFU; } else { eventCount = ((*((volatile uint16_t *)(base + 0xB0U))) >> 12U) & 0xFU; } return(eventCount); } //***************************************************************************** // //! Force SOC event. //! //! \param base is the base address of the EPWM module. //! \param adcSOCType is the ADC SOC type. //! //! This function forces an ePWM SOC event. //! Valid values for adcSOCType are: //! - EPWM_SOC_A - SOC A //! - EPWM_SOC_B - SOC B //! //! \return None // //***************************************************************************** static inline void EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) { ; // Set SOC A/B bit of ETFRC register (*((volatile uint16_t *)(base + 0xACU))) |= 1U << ((uint16_t)adcSOCType + 2U); } // Digital Compare //***************************************************************************** // //! Set the DC trip input. //! //! \param base is the base address of the EPWM module. //! \param tripSource is the tripSource. //! \param dcType is the Digital Compare type. //! //! This function sets the trip input to the Digital Compare (DC). For a given //! dcType the function sets the tripSource to be the input to the DC. //! Valid values for the parameter are: //! dcType //! - EPWM_DC_TYPE_DCAH - Digital Compare A High //! - EPWM_DC_TYPE_DCAL - Digital Compare A Low //! - EPWM_DC_TYPE_DCBH - Digital Compare B High //! - EPWM_DC_TYPE_DCBL - Digital Compare B Low //! tripSource //! - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13. //! - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input is //! enabled by the EPWM_enableDCTripCombInput() //! function. //! //! \return None // //***************************************************************************** static inline void EPWM_selectDigitalCompareTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, EPWM_DigitalCompareType dcType) { ; // set the DC trip input __eallow(); (*((volatile uint16_t *)(base + 0xC0U))) = (((*((volatile uint16_t *)(base + 0xC0U))) & ~(0xFU << ((uint16_t)dcType << 2U))) | ((uint16_t)tripSource << ((uint16_t)dcType << 2U))); __edis(); } // DCFILT //***************************************************************************** // //! Enable DC filter blanking window. //! //! \param base is the base address of the EPWM module. //! //! This function enables the DC filter blanking window. //! //! \return None // //***************************************************************************** static inline void EPWM_enableDigitalCompareBlankingWindow(uint32_t base) { ; // Enable DC filter blanking window __eallow(); (*((volatile uint16_t *)(base + 0xC7U))) |= 0x4U; __edis(); } //***************************************************************************** // //! Disable DC filter blanking window. //! //! \param base is the base address of the EPWM module. //! //! This function disables the DC filter blanking window. //! //! \return None // //***************************************************************************** static inline void EPWM_disableDigitalCompareBlankingWindow(uint32_t base) { ; // Disable DC filter blanking window __eallow(); (*((volatile uint16_t *)(base + 0xC7U))) &= ~0x4U; __edis(); } //***************************************************************************** // //! Enable Digital Compare Window inverse mode. //! //! \param base is the base address of the EPWM module. //! //! This function enables the Digital Compare Window inverse mode. This will //! invert the blanking window. //! //! \return None // //***************************************************************************** static inline void EPWM_enableDigitalCompareWindowInverseMode(uint32_t base) { ; __eallow(); (*((volatile uint16_t *)(base + 0xC7U))) |= 0x8U; __edis(); } //***************************************************************************** // //! Disable Digital Compare Window inverse mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables the Digital Compare Window inverse mode. //! //! \return None // //***************************************************************************** static inline void EPWM_disableDigitalCompareWindowInverseMode(uint32_t base) { ; __eallow(); (*((volatile uint16_t *)(base + 0xC7U))) &= ~0x8U; __edis(); } //***************************************************************************** // //! Set the Digital Compare filter blanking pulse. //! //! \param base is the base address of the EPWM module. //! \param blankingPulse is Pulse that starts blanking window. //! //! This function sets the input pulse that starts the Digital Compare blanking //! window. //! Valid values for blankingPulse are: //! - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period //! - EPWM_DC_WINDOW_START_TBCTR_ZERO - Time base counter equals zero //! - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero //! or period. //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareBlankingEvent(uint32_t base, EPWM_DigitalCompareBlankingPulse blankingPulse) { ; __eallow(); (*((volatile uint16_t *)(base + 0xC7U))) = (((*((volatile uint16_t *)(base + 0xC7U))) & ~0x30U) | ((uint16_t)((uint32_t)blankingPulse << 4U))); __edis(); } //***************************************************************************** // //! Set up the Digital Compare filter input. //! //! \param base is the base address of the EPWM module. //! \param filterInput is Digital Compare signal source. //! //! This function sets the signal input source that will be filtered by the //! Digital Compare module. //! Valid values for filterInput are: //! - EPWM_DC_WINDOW_SOURCE_DCAEVT1 - DC filter signal source is DCAEVT1 //! - EPWM_DC_WINDOW_SOURCE_DCAEVT2 - DC filter signal source is DCAEVT2 //! - EPWM_DC_WINDOW_SOURCE_DCBEVT1 - DC filter signal source is DCBEVT1 //! - EPWM_DC_WINDOW_SOURCE_DCBEVT2 - DC filter signal source is DCBEVT2 //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareFilterInput(uint32_t base, EPWM_DigitalCompareFilterInput filterInput) { ; __eallow(); // Set the signal source that will be filtered. (*((volatile uint16_t *)(base + 0xC7U))) = (((*((volatile uint16_t *)(base + 0xC7U))) & ~0x3U) | ((uint16_t)filterInput)); __edis(); } // DC Edge Filter //***************************************************************************** // //! Enable Digital Compare Edge Filter. //! //! \param base is the base address of the EPWM module. //! //! This function enables the Digital Compare Edge filter to generate event //! after configured number of edges. //! //! \return None // //***************************************************************************** static inline void EPWM_enableDigitalCompareEdgeFilter(uint32_t base) { ; __eallow(); // Enable DC Edge Filter. (*((volatile uint16_t *)(base + 0xC7U))) |= 0x40U; __edis(); } //***************************************************************************** // //! Disable Digital Compare Edge Filter. //! //! \param base is the base address of the EPWM module. //! //! This function disables the Digital Compare Edge filter. //! //! \return None // //***************************************************************************** static inline void EPWM_disableDigitalCompareEdgeFilter(uint32_t base) { ; __eallow(); // Disable DC Edge Filter. (*((volatile uint16_t *)(base + 0xC7U))) &= ~0x40U; __edis(); } //***************************************************************************** // //! Set the Digital Compare Edge Filter Mode. //! //! \param base is the base address of the EPWM module. //! \param edgeMode is Digital Compare Edge filter mode. //! //! This function sets the Digital Compare Event filter mode. Valid values //! for edgeMode are: //! - EPWM_DC_EDGEFILT_MODE_RISING - DC edge filter mode is rising edge //! - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge //! - EPWM_DC_EDGEFILT_MODE_BOTH - DC edge filter mode is both edges //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, EPWM_DigitalCompareEdgeFilterMode edgeMode) { ; __eallow(); // Set DC Edge filter mode. (*((volatile uint16_t *)(base + 0xC7U))) = ((*((volatile uint16_t *)(base + 0xC7U))) & ~0x300U) | (edgeMode << 8U); __edis(); } //***************************************************************************** // //! Set the Digital Compare Edge Filter Edge Count. //! //! \param base is the base address of the EPWM module. //! \param edgeMode is Digital Compare Edge filter mode. //! //! This function sets the Digital Compare Event filter Edge Count to genrate //! events. Valid values for edgeCount can be: //! - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event //! - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation //! - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation //! - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation //! - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation //! - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation //! - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation //! - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount) { ; __eallow(); // Set DC Edge filter edge count. (*((volatile uint16_t *)(base + 0xC7U))) = ((*((volatile uint16_t *)(base + 0xC7U))) & ~0x1C00U) | (edgeCount << 10U); __edis(); } //***************************************************************************** // //! Returns the Digital Compare Edge Filter Edge Count. //! //! \param base is the base address of the EPWM module. //! //! This function returns the configured Digital Compare Edge filter edge //! count required to generate events. It can return values from 0-7. //! //! \return Returns the configured DigitalCompare Edge filter edge count. // //***************************************************************************** static inline uint16_t EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base) { ; // Return configured DC edge filter edge count. return(((*((volatile uint16_t *)(base + 0xC7U))) & 0x1C00U) >> 10U); } //***************************************************************************** // //! Returns the Digital Compare Edge filter captured edge count status. //! //! \param base is the base address of the EPWM module. //! //! This function returns the count of edges captured by Digital Compare Edge //! filter. It can return values from 0-7. //! //! \return Returns the count of captured edges // //***************************************************************************** static inline uint16_t EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base) { ; // Return captured edge count by DC Edge filter. return(((*((volatile uint16_t *)(base + 0xC7U))) & 0xE000U) >> 13U); } //***************************************************************************** // //! Set up the Digital Compare filter window offset //! //! \param base is the base address of the EPWM module. //! \param windowOffsetCount is blanking window offset length. //! //! This function sets the offset between window start pulse and blanking //! window in TBCLK count. //! The function take a 16bit count value for the offset value. //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount) { ; // Set the blanking window offset in TBCLK counts (*((volatile uint16_t *)(base + 0xC9U))) = windowOffsetCount; } //***************************************************************************** // //! Set up the Digital Compare filter window length //! //! \param base is the base address of the EPWM module. //! \param windowLengthCount is blanking window length. //! //! This function sets up the Digital Compare filter blanking window length in //! TBCLK count.The function takes a 16bit count value for the window length. //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount) { ; // Set the blanking window length in TBCLK counts (*((volatile uint16_t *)(base + 0xCBU))) = windowLengthCount; } //***************************************************************************** // //! Return DC filter blanking window offset count. //! //! \param base is the base address of the EPWM module. //! //! This function returns DC filter blanking window offset count. //! //! \return None // //***************************************************************************** static inline uint16_t EPWM_getDigitalCompareBlankingWindowOffsetCount( uint32_t base) { ; // Return the Blanking Window Offset count return((*((volatile uint16_t *)(base + 0xCAU)))); } //***************************************************************************** // //! Return DC filter blanking window length count. //! //! \param base is the base address of the EPWM module. //! //! This function returns DC filter blanking window length count. //! //! \return None // //***************************************************************************** static inline uint16_t EPWM_getDigitalCompareBlankingWindowLengthCount( uint32_t base) { ; // Return the Blanking Window Length count return((*((volatile uint16_t *)(base + 0xCCU)))); } //***************************************************************************** // //! Set up the Digital Compare Event source. //! //! \param base is the base address of the EPWM module. //! \param dcModule is the Digital Compare module. //! \param dcEvent is the Digital Compare Event number. //! \param dcEventSource is the - Digital Compare Event source. //! //! This function sets up the Digital Compare module Event sources. //! The following are valid values for the parameters. //! dcModule //! - EPWM_DC_MODULE_A - Digital Compare Module A //! - EPWM_DC_MODULE_B - Digital Compare Module B //! dcEvent //! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 //! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 //! dcEventSource //! - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL - signal source is filtered //! \note The signal source for this option is DCxEVTy, where the //! value of x is dependent on dcModule and the value of y is //! dependent on dcEvent. Possible signal sources are DCAEVT1, //! DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both //! dcModule and dcEvent. //! - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL - signal source is unfiltered //! The signal source for this option is DCEVTFILT. //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareEventSource(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareEventSource dcEventSource) { uint32_t registerOffset; ; registerOffset = 0xC3U + (uint16_t)dcModule; // Set the DC event 1 source source __eallow(); if(dcEvent == EPWM_DC_EVENT_1) { (*((volatile uint16_t *)(base + registerOffset))) = (((*((volatile uint16_t *)(base + registerOffset))) & ~0x1U) | (uint16_t)dcEventSource); } else { (*((volatile uint16_t *)(base + registerOffset))) = (((*((volatile uint16_t *)(base + registerOffset))) & ~0x100U) | ((uint16_t)dcEventSource << 8U)); } __edis(); } //***************************************************************************** // //! Set up the Digital Compare input sync mode. //! //! \param base is the base address of the EPWM module. //! \param dcModule is the Digital Compare module. //! \param dcEvent is the Digital Compare Event number. //! \param syncMode is the Digital Compare Event sync mode. //! //! This function sets up the Digital Compare module Event sources. //! The following are valid values for the parameters. //! dcModule //! - EPWM_DC_MODULE_A - Digital Compare Module A //! - EPWM_DC_MODULE_B - Digital Compare Module B //! dcEvent //! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 //! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 //! syncMode //! - EPWM_DC_EVENT_INPUT_SYNCED - DC input signal is synced with //! TBCLK //! - EPWM_DC_EVENT_INPUT_NOT SYNCED - DC input signal is not synced with //! TBCLK //! //! \return None // //***************************************************************************** static inline void EPWM_setDigitalCompareEventSyncMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareSyncMode syncMode) { uint32_t registerOffset; ; registerOffset = 0xC3U + (uint16_t)dcModule; // Set the DC event sync mode __eallow(); if(dcEvent == EPWM_DC_EVENT_1) { (*((volatile uint16_t *)(base + registerOffset))) = (((*((volatile uint16_t *)(base + registerOffset))) & ~0x2U) | ((uint16_t)syncMode << 1U)); } else { (*((volatile uint16_t *)(base + registerOffset))) = (((*((volatile uint16_t *)(base + registerOffset))) & ~0x200U) | ((uint16_t)syncMode << 9U)); } __edis(); } //***************************************************************************** // //! Enable Digital Compare to generate Start of Conversion. //! //! \param base is the base address of the EPWM module. //! \param dcModule is the Digital Compare module. //! //! This function enables the Digital Compare Event 1 to generate Start of //! Conversion. //! The following are valid values for the parameters. //! dcModule //! - EPWM_DC_MODULE_A - Digital Compare Module A //! - EPWM_DC_MODULE_B - Digital Compare Module B //! //! \return None // //***************************************************************************** static inline void EPWM_enableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule) { uint32_t registerOffset; ; registerOffset = 0xC3U + (uint16_t)dcModule; // Enable digital Compare to generate Start of conversion __eallow(); (*((volatile uint16_t *)(base + registerOffset))) = ((*((volatile uint16_t *)(base + registerOffset))) | 0x4U); __edis(); } //***************************************************************************** // //! Disable Digital Compare from generating Start of Conversion. //! //! \param base is the base address of the EPWM module. //! \param dcModule is the Digital Compare module. //! //! This function disables the Digital Compare Event 1 from generating Start of //! Conversion. //! The following are valid values for the parameters. //! dcModule //! - EPWM_DC_MODULE_A - Digital Compare Module A //! - EPWM_DC_MODULE_B - Digital Compare Module B //! //! \return None // //***************************************************************************** static inline void EPWM_disableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule) { uint32_t registerOffset; ; registerOffset = 0xC3U + (uint16_t)dcModule; // Disable digital Compare to generate Start of conversion __eallow(); (*((volatile uint16_t *)(base + registerOffset))) = ((*((volatile uint16_t *)(base + registerOffset))) & ~0x4U); __edis(); } //***************************************************************************** // //! Enable Digital Compare to generate sync out pulse. //! //! \param base is the base address of the EPWM module. //! \param dcModule is the Digital Compare module. //! //! This function enables the Digital Compare Event 1 to generate sync out //! pulse //! The following are valid values for the parameters. //! dcModule //! - EPWM_DC_MODULE_A - Digital Compare Module A //! - EPWM_DC_MODULE_B - Digital Compare Module B //! //! \return None // //***************************************************************************** static inline void EPWM_enableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule) { uint32_t registerOffset; ; registerOffset = 0xC3U + (uint16_t)dcModule; // Enable digital Compare to generate Start of conversion __eallow(); (*((volatile uint16_t *)(base + registerOffset))) = ((*((volatile uint16_t *)(base + registerOffset))) | 0x8U); __edis(); } //***************************************************************************** // //! Disable Digital Compare from generating Start of Conversion. //! //! \param base is the base address of the EPWM module. //! \param dcModule is the Digital Compare module. //! //! This function disables the Digital Compare Event 1 from generating synch //! out pulse. //! The following are valid values for the parameters. //! dcModule //! - EPWM_DC_MODULE_A - Digital Compare Module A //! - EPWM_DC_MODULE_B - Digital Compare Module B //! //! \return None // //***************************************************************************** static inline void EPWM_disableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule) { uint32_t registerOffset; ; registerOffset = 0xC3U + (uint16_t)dcModule; // Disable digital Compare to generate Start of conversion __eallow(); (*((volatile uint16_t *)(base + registerOffset))) = ((*((volatile uint16_t *)(base + registerOffset))) & ~0x8U); __edis(); } // DC capture mode //***************************************************************************** // //! Enables the Time Base Counter Capture controller. //! //! \param base is the base address of the EPWM module. //! //! This function enables the time Base Counter Capture. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableDigitalCompareCounterCapture(uint32_t base) { ; // Enable Time base counter capture __eallow(); (*((volatile uint16_t *)(base + 0xC8U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disables the Time Base Counter Capture controller. //! //! \param base is the base address of the EPWM module. //! //! This function disable the time Base Counter Capture. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableDigitalCompareCounterCapture(uint32_t base) { ; // Disable Time base counter capture __eallow(); (*((volatile uint16_t *)(base + 0xC8U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Set the Time Base Counter Capture mode. //! //! \param base is the base address of the EPWM module. //! \param enableShadowMode is the shadow read mode flag. //! //! This function sets the mode the Time Base Counter value is read from. If //! enableShadowMode is true, CPU reads of the DCCAP register will return the //! shadow register contents.If enableShadowMode is false, CPU reads of the //! DCCAP register will return the active register contents. //! //! \return None. // //***************************************************************************** static inline void EPWM_setDigitalCompareCounterShadowMode(uint32_t base, _Bool enableShadowMode) { ; __eallow(); if(enableShadowMode) { (*((volatile uint16_t *)(base + 0xC8U))) &= ~0x2U; } else { (*((volatile uint16_t *)(base + 0xC8U))) |= 0x2U; } __edis(); } //***************************************************************************** // //! Return the DC Capture event status. //! //! \param base is the base address of the EPWM module. //! //! This function returns the DC capture event status. //! //! \return Returns true if a DC capture event has occurs. //! Returns false if no DC Capture event has occurred. //! //! \return None. // //***************************************************************************** static inline _Bool EPWM_getDigitalCompareCaptureStatus(uint32_t base) { ; // Return the DC compare status return(((*((volatile uint16_t *)(base + 0xC8U))) & 0x2000U) == 0x2000U); } //***************************************************************************** // //! Return the DC Time Base Counter capture value. //! //! \param base is the base address of the EPWM module. //! //! This function returns the DC Time Base Counter capture value. The value //! read is determined by the mode as set in the //! EPWM_setTimeBaseCounterReadMode() function. //! //! \return Returns the DC Time Base Counter Capture count value. // //***************************************************************************** static inline uint16_t EPWM_getDigitalCompareCaptureCount(uint32_t base) { ; // Return the DC Time Base Counter Capture count value return((*((volatile uint16_t *)(base + 0xCFU)))); } //***************************************************************************** // //! Enable DC TRIP combinational input. //! //! \param base is the base address of the EPWM module. //! \param tripInput is the Trip number. //! \param dcType is the Digital Compare module. //! //! This function enables the specified Trip input. //! Valid values for the parameters are: //! tripInput //! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 //! dcType //! - EPWM_DC_TYPE_DCAH - Digital Compare A High //! - EPWM_DC_TYPE_DCAL - Digital Compare A Low //! - EPWM_DC_TYPE_DCBH - Digital Compare B High //! - EPWM_DC_TYPE_DCBL - Digital Compare B Low //! //! \return None. // //***************************************************************************** static inline void EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType) { uint32_t registerOffset; ; // get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register // offset with respect to DCAHTRIPSEL registerOffset = 0xD2U + (uint16_t)dcType; // set the DC trip input __eallow(); (*((volatile uint16_t *)(base + registerOffset))) = ((*((volatile uint16_t *)(base + registerOffset))) | tripInput); // Enable the combinational (*((volatile uint16_t *)(base + 0xC0U))) = ((*((volatile uint16_t *)(base + 0xC0U))) | (0xFU << ((uint16_t)dcType << 2U))); __edis(); } //***************************************************************************** // //! Disable DC TRIP combinational input. //! //! \param base is the base address of the EPWM module. //! \param tripInput is the Trip number. //! \param dcType is the Digital Compare module. //! //! This function disables the specified Trip input. //! Valid values for the parameters are: //! tripInput //! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 //! dcType //! - EPWM_DC_TYPE_DCAH - Digital Compare A High //! - EPWM_DC_TYPE_DCAL - Digital Compare A Low //! - EPWM_DC_TYPE_DCBH - Digital Compare B High //! - EPWM_DC_TYPE_DCBL - Digital Compare B Low //! //! \return None. // //***************************************************************************** static inline void EPWM_disableDigitalCompareTripCombinationInput( uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType) { uint32_t registerOffset; ; // get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register // offset with respect to DCAHTRIPSEL registerOffset = 0xD2U + (uint16_t)dcType; // set the DC trip input __eallow(); (*((volatile uint16_t *)(base + registerOffset))) = ((*((volatile uint16_t *)(base + registerOffset))) & ~tripInput); __edis(); } // Valley switching //***************************************************************************** // //! Enable valley capture mode. //! //! \param base is the base address of the EPWM module. //! //! This function enables Valley Capture mode. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableValleyCapture(uint32_t base) { ; // Set VCAPE bit __eallow(); (*((volatile uint16_t *)(base + 0x18U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disable valley capture mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables Valley Capture mode. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableValleyCapture(uint32_t base) { ; // Clear VCAPE bit __eallow(); (*((volatile uint16_t *)(base + 0x18U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Start valley capture mode. //! //! \param base is the base address of the EPWM module. //! //! This function starts Valley Capture sequence. //! //! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger //! variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this //! function. //! //! \return None. // //***************************************************************************** static inline void EPWM_startValleyCapture(uint32_t base) { ; // Set VCAPSTART bit __eallow(); (*((volatile uint16_t *)(base + 0x18U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Set valley capture trigger. //! //! \param base is the base address of the EPWM module. //! \param trigger is the Valley counter trigger. //! //! This function sets the trigger value that initiates Valley Capture sequence //! //! \b Set the number of Trigger source events for starting and stopping the //! valley capture using EPWM_setValleyTriggerEdgeCounts(). //! //! \return None. // //***************************************************************************** static inline void EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger) { ; // write to TRIGSEL bits __eallow(); (*((volatile uint16_t *)(base + 0x18U))) = (((*((volatile uint16_t *)(base + 0x18U))) & ~0x1CU) | ((uint16_t)trigger << 2U)); __edis(); } //***************************************************************************** // //! Set valley capture trigger source count. //! //! \param base is the base address of the EPWM module. //! \param startCount //! \param stopCount //! //! This function sets the number of trigger events required to start and stop //! the valley capture count. //! Maximum values for both startCount and stopCount is 15 corresponding to the //! 15th edge of the trigger event. //! //! \b Note: //! A startCount value of 0 prevents starting the valley counter. //! A stopCount value of 0 prevents the valley counter from stopping. //! //! \return None. // //***************************************************************************** static inline void EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, uint16_t stopCount) { ; ; // write to STARTEDGE and STOPEDGE bits __eallow(); (*((volatile uint16_t *)(base + 0x19U))) = (((*((volatile uint16_t *)(base + 0x19U))) & ~(0xFU | 0xF00U)) | (startCount | (stopCount << 8U))); __edis(); } //***************************************************************************** // //! Enable valley switching delay. //! //! \param base is the base address of the EPWM module. //! //! This function enables Valley switching delay. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableValleyHWDelay(uint32_t base) { ; // Set EDGEFILTDLYSEL bit __eallow(); (*((volatile uint16_t *)(base + 0x18U))) |= 0x400U; __edis(); } //***************************************************************************** // //! Disable valley switching delay. //! //! \param base is the base address of the EPWM module. //! //! This function disables Valley switching delay. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableValleyHWDelay(uint32_t base) { ; // Clear EDGEFILTDLYSEL bit __eallow(); (*((volatile uint16_t *)(base + 0x18U))) &= ~0x400U; __edis(); } //***************************************************************************** // //! Set Valley delay values. //! //! \param base is the base address of the EPWM module. //! \param delayOffsetValue is the software defined delay offset value. //! //! This function sets the Valley delay value. //! //! \return None. // //***************************************************************************** static inline void EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue) { ; // Write to SWVDELVAL bits (*((volatile uint16_t *)(base + 0x77U))) = delayOffsetValue; } //***************************************************************************** // //! Set Valley delay mode. //! //! \param base is the base address of the EPWM module. //! \param delayMode is the Valley delay mode. //! //! This function sets the Valley delay mode values. //! //! \return None. // //***************************************************************************** static inline void EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode) { ; __eallow(); // Write to VDELAYDIV bits (*((volatile uint16_t *)(base + 0x18U))) = (((*((volatile uint16_t *)(base + 0x18U))) & ~0x380U) | ((uint16_t)delayMode << 7U)); __edis(); } //***************************************************************************** // //! Get the valley edge status bit. //! //! \param base is the base address of the EPWM module. //! \param edge is the start or stop edge. //! //! This function returns the status of the start or stop valley status //! depending on the value of edge. //! If a start or stop edge has occurred, the function returns true, if not it //! returns false. //! //! \return Returns true if the specified edge has occurred, //! Returns false if the specified edge has not occurred. // //***************************************************************************** static inline _Bool EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge) { ; if(edge == EPWM_VALLEY_COUNT_START_EDGE) { // returns STARTEDGESTS status return((((*((volatile uint16_t *)(base + 0x19U))) & 0x80U) == 0x80U ) ? 1 : 0); } else { // returns STOPEDGESTS status return((((*((volatile uint16_t *)(base + 0x19U))) & 0x8000U) == 0x8000U) ? 1 : 0); } } //***************************************************************************** // //! Get the Valley Counter value. //! //! \param base is the base address of the EPWM module. //! //! This function returns the valley time base count value which is captured //! upon occurrence of the stop edge condition selected by //! EPWM_setValleyTriggerSource() and by the stopCount variable of the //! EPWM_setValleyTriggerEdgeCounts() function. //! //! \return Returns the valley base time count. // //***************************************************************************** static inline uint16_t EPWM_getValleyCount(uint32_t base) { ; // Read VCNTVAL register return((*((volatile uint16_t *)(base + 0xFEU)))); } //***************************************************************************** // //! Get the Valley delay value. //! //! \param base is the base address of the EPWM module. //! //! This function returns the hardware valley delay count. //! //! \return Returns the valley delay count. // //***************************************************************************** static inline uint16_t EPWM_getValleyHWDelay(uint32_t base) { ; // Read HWVDELVAL register return((*((volatile uint16_t *)(base + 0xFDU)))); } //***************************************************************************** // //! Enable Global shadow load mode. //! //! \param base is the base address of the EPWM module. //! //! This function enables Global shadow to active load mode of registers. //! The trigger source for loading shadow to active is determined by //! EPWM_setGlobalLoadTrigger() function. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableGlobalLoad(uint32_t base) { ; __eallow(); // shadow to active load is controlled globally (*((volatile uint16_t *)(base + 0x34U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disable Global shadow load mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables Global shadow to active load mode of registers. //! Loading shadow to active is determined individually. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableGlobalLoad(uint32_t base) { ; __eallow(); // shadow to active load is controlled individually (*((volatile uint16_t *)(base + 0x34U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Set the Global shadow load pulse. //! //! \param base is the base address of the EPWM module. //! \param loadTrigger is the pulse that causes global shadow load. //! //! This function sets the pulse that causes Global shadow to active load. //! Valid values for the loadTrigger parameter are: //! //! - EPWM_GL_LOAD_PULSE_CNTR_ZERO - load when counter is equal //! to zero //! - EPWM_GL_LOAD_PULSE_CNTR_PERIOD - load when counter is equal //! to period //! - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD - load when counter is equal //! to zero or period //! - EPWM_GL_LOAD_PULSE_SYNC - load on sync event //! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO - load on sync event or when //! counter is equal to zero //! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD - load on sync event or when //! counter is equal to period //! - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD - load on sync event or when //! counter is equal to period //! or zero //! - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE - load on global force //! //! \return None. // //***************************************************************************** static inline void EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger) { ; // set the Global shadow to active load pulse. __eallow(); (*((volatile uint16_t *)(base + 0x34U))) = (((*((volatile uint16_t *)(base + 0x34U))) & ~0x1EU) | ((uint16_t)loadTrigger << 1U)); __edis(); } //***************************************************************************** // //! Set the number of Global load pulse event counts //! //! \param base is the base address of the EPWM module. //! \param prescalePulseCount is the pulse event counts. //! //! This function sets the number of Global Load pulse events that have to //! occurred before a global load pulse is issued. Valid values for //! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7 //! representing 7 events. //! //! \return None. // //***************************************************************************** static inline void EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount) { ; ; // Set the number of counts that have to occur before // a load strobe is issued. __eallow(); (*((volatile uint16_t *)(base + 0x34U))) = (((*((volatile uint16_t *)(base + 0x34U))) & ~0x380U) | (prescalePulseCount << 7U)); __edis(); } //***************************************************************************** // //! Return the number of Global load pulse event counts //! //! \param base is the base address of the EPWM module. //! //! This function returns the number of Global Load pulse events that have //! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger() //! function. //! //! \return None. // //***************************************************************************** static inline uint16_t EPWM_getGlobalLoadEventCount(uint32_t base) { ; // Return the number of events that have occurred. return(((*((volatile uint16_t *)(base + 0x34U))) >> 10U) & 0x7U); } //***************************************************************************** // //! Enable continuous global shadow to active load. //! //! \param base is the base address of the EPWM module. //! //! This function enables global continuous shadow to active load. Register //! load happens every time the event set by the //! EPWM_setGlobalLoadTrigger() occurs. //! //! \return None. // //***************************************************************************** static inline void EPWM_disableGlobalLoadOneShotMode(uint32_t base) { ; // Enable global continuous shadow to active load __eallow(); (*((volatile uint16_t *)(base + 0x34U))) &= ~0x20U; __edis(); } //***************************************************************************** // //! Enable One shot global shadow to active load. //! //! \param base is the base address of the EPWM module. //! //! This function enables a one time global shadow to active load. Register //! load happens every time the event set by the //! EPWM_setGlobalLoadTrigger() occurs. //! //! \return None. // //***************************************************************************** static inline void EPWM_enableGlobalLoadOneShotMode(uint32_t base) { ; // Enable global continuous shadow to active load __eallow(); (*((volatile uint16_t *)(base + 0x34U))) |= 0x20U; __edis(); } //***************************************************************************** // //! Set One shot global shadow to active load pulse. //! //! \param base is the base address of the EPWM module. //! //! This function sets a one time global shadow to active load pulse. The pulse //! propagates to generate a load signal if any of the events set by //! EPWM_setGlobalLoadTrigger() occur. //! //! \return None. // //***************************************************************************** static inline void EPWM_setGlobalLoadOneShotLatch(uint32_t base) { ; // Set a one shot Global shadow load pulse. (*((volatile uint16_t *)(base + 0x74U))) |= 0x1U; } //***************************************************************************** // //! Force a software One shot global shadow to active load pulse. //! //! \param base is the base address of the EPWM module. //! //! This function forces a software a one time global shadow to active load //! pulse. //! //! \return None. // //***************************************************************************** static inline void EPWM_forceGlobalLoadOneShotEvent(uint32_t base) { ; // Force a Software Global shadow load pulse. (*((volatile uint16_t *)(base + 0x74U))) |= 0x2U; } //***************************************************************************** // //! Enable a register to be loaded Globally. //! //! \param base is the base address of the EPWM module. //! \param loadRegister is the register. //! //! This function enables the register specified by loadRegister to be globally //! loaded. //! Valid values for loadRegister are: //! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR //! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR //! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR //! - EPWM_GL_REGISTER_CMPC - Register CMPC //! - EPWM_GL_REGISTER_CMPD - Register CMPD //! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR //! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR //! - EPWM_GL_REGISTER_DBCTL - Register DBCTL //! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 //! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 //! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC //! //! \return None. // //***************************************************************************** static inline void EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) { ; ; // the register specified by loadRegister is loaded globally __eallow(); (*((volatile uint16_t *)(base + 0x35U))) |= loadRegister; __edis(); } //***************************************************************************** // //! Disable a register to be loaded Globally. //! //! \param base is the base address of the EPWM module. //! \param loadRegister is the register. //! //! This function disables the register specified by loadRegister from being //! loaded globally. The shadow to active load happens as specified by the //! register control //! Valid values for loadRegister are: //! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR //! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR //! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR //! - EPWM_GL_REGISTER_CMPC - Register CMPC //! - EPWM_GL_REGISTER_CMPD - Register CMPD //! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR //! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR //! - EPWM_GL_REGISTER_DBCTL - Register DBCTL //! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 //! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 //! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC //! //! \return None. // //***************************************************************************** static inline void EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) { ; ; // the register specified by loadRegister is loaded by individual // register configuration setting __eallow(); (*((volatile uint16_t *)(base + 0x35U))) &= ~loadRegister; __edis(); } //***************************************************************************** // //! Lock EALLOW protected register groups //! //! \param base is the base address of the EPWM module. //! \param registerGroup is the EALLOW register groups. //! //! This functions locks the EALLOW protected register groups specified by //! the registerGroup variable. //! //! \return None. // //***************************************************************************** static inline void EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup) { ; // write the Key to EPWMLOCK register (*((volatile uint32_t *)(base + 0xFAU))) = ((uint32_t)0xA5A50000U | ((uint32_t)registerGroup)); } //***************************************************************************** // //! Set emulation mode //! //! \param base is the base address of the EPWM module. //! \param emulationMode is the emulation mode. //! //! This function sets the emulation behaviours of the time base counter. Valid //! values for emulationMode are: //! - EPWM_EMULATION_STOP_AFTER_NEXT_TB - Stop after next Time Base counter //! increment or decrement. //! - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole //! cycle. //! - EPWM_EMULATION_FREE_RUN - Free run. //! //! \return None. // //***************************************************************************** extern void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: eqep.h // // TITLE: C28x eQEP driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup eqep_api eQEP //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_eqep.h // // TITLE: Definitions for the EQEP registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the EQEP register offsets // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the QDECCTL register // //***************************************************************************** // Position Counter // selection //***************************************************************************** // // The following are defines for the bit fields in the QEPCTL register // //***************************************************************************** // enable // counter // count //***************************************************************************** // // The following are defines for the bit fields in the QCAPCTL register // //***************************************************************************** // prescaler //***************************************************************************** // // The following are defines for the bit fields in the QPOSCTL register // //***************************************************************************** // width // enable/disable // load // enable //***************************************************************************** // // The following are defines for the bit fields in the QEINT register // //***************************************************************************** // interrupt enable // interrupt enable // interrupt enable // enable // interrupt enable // interrupt enable // interrupt enable // interrupt enable // enable // enable // enable //***************************************************************************** // // The following are defines for the bit fields in the QFLG register // //***************************************************************************** // interrupt flag // interrupt flag // interrupt flag // flag // interrupt flag // interrupt flag // interrupt flag // interrupt flag // flag // flag //***************************************************************************** // // The following are defines for the bit fields in the QCLR register // //***************************************************************************** // interrupt flag // interrupt flag // change interrupt flag // interrupt flag // underflow interrupt flag // overflow interrupt flag // interrupt flag // event interrupt flag // interrupt flag // interrupt flag // flag // flag //***************************************************************************** // // The following are defines for the bit fields in the QFRC register // //***************************************************************************** // interrupt // interrupt // change interrupt // interrupt // underflow interrupt // overflow interrupt // interrupt // interrupt // interrupt // interrupt //***************************************************************************** // // The following are defines for the bit fields in the QEPSTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the REV register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the QEPSTROBESEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the QMACTRL register // //***************************************************************************** //***************************************************************************** // // Values that can be passed to EQEP_setDecoderConfig() as the config // parameter. // //***************************************************************************** // Operation Mode // Resolution // Swap QEPA and QEPB //***************************************************************************** // // Values that can be passed to EQEP_setCompareConfig() as the config // parameter. // //***************************************************************************** // Sync pulse pin // Shadow register use //***************************************************************************** // // Values that can be passed to EQEP_enableInterrupt(), // EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the // intFlags parameter and returned by EQEP_clearInterruptStatus(). // //***************************************************************************** //***************************************************************************** // // Values that can be returned by EQEP_getStatus(). // //***************************************************************************** //! Unit position event detected //! Direction was clockwise on first index event //! Direction is CW (forward) //! Direction was CW on index //! Capture timer overflow //! Direction changed between position capture events //! First index pulse occurred //! Position counter error //***************************************************************************** // // Values that can be passed to EQEP_setLatchMode() as the latchMode parameter. // //***************************************************************************** // Position counter latch event // Strobe position counter latch event //! On rising edge of strobe //! On rising edge when clockwise, on falling when counter clockwise // Index position counter latch event //***************************************************************************** // // Values that can be passed to EQEP_setPositionInitMode() as the initMode // parameter. // //***************************************************************************** // Strobe events //! On rising edge of strobe //! On rising edge when clockwise, on falling when counter clockwise // Index events //***************************************************************************** // //! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! Reset position on index pulse EQEP_POSITION_RESET_IDX = 0x0000, //! Reset position on maximum position EQEP_POSITION_RESET_MAX_POS = 0x1000, //! Reset position on the first index pulse EQEP_POSITION_RESET_1ST_IDX = 0x2000, //! Reset position on a unit time event EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000 } EQEP_PositionResetMode; //***************************************************************************** // //! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale //! parameter. CAPCLK is the capture timer clock frequency. // //***************************************************************************** typedef enum { EQEP_CAPTURE_CLK_DIV_1 = 0x00, //!< CAPCLK = SYSCLKOUT/1 EQEP_CAPTURE_CLK_DIV_2 = 0x10, //!< CAPCLK = SYSCLKOUT/2 EQEP_CAPTURE_CLK_DIV_4 = 0x20, //!< CAPCLK = SYSCLKOUT/4 EQEP_CAPTURE_CLK_DIV_8 = 0x30, //!< CAPCLK = SYSCLKOUT/8 EQEP_CAPTURE_CLK_DIV_16 = 0x40, //!< CAPCLK = SYSCLKOUT/16 EQEP_CAPTURE_CLK_DIV_32 = 0x50, //!< CAPCLK = SYSCLKOUT/32 EQEP_CAPTURE_CLK_DIV_64 = 0x60, //!< CAPCLK = SYSCLKOUT/64 EQEP_CAPTURE_CLK_DIV_128 = 0x70 //!< CAPCLK = SYSCLKOUT/128 } EQEP_CAPCLKPrescale; //***************************************************************************** // //! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale //! parameter. UPEVNT is the unit position event frequency. // //***************************************************************************** typedef enum { EQEP_UNIT_POS_EVNT_DIV_1, //!< UPEVNT = QCLK/1 EQEP_UNIT_POS_EVNT_DIV_2, //!< UPEVNT = QCLK/2 EQEP_UNIT_POS_EVNT_DIV_4, //!< UPEVNT = QCLK/4 EQEP_UNIT_POS_EVNT_DIV_8, //!< UPEVNT = QCLK/8 EQEP_UNIT_POS_EVNT_DIV_16, //!< UPEVNT = QCLK/16 EQEP_UNIT_POS_EVNT_DIV_32, //!< UPEVNT = QCLK/32 EQEP_UNIT_POS_EVNT_DIV_64, //!< UPEVNT = QCLK/64 EQEP_UNIT_POS_EVNT_DIV_128, //!< UPEVNT = QCLK/128 EQEP_UNIT_POS_EVNT_DIV_256, //!< UPEVNT = QCLK/256 EQEP_UNIT_POS_EVNT_DIV_512, //!< UPEVNT = QCLK/512 EQEP_UNIT_POS_EVNT_DIV_1024, //!< UPEVNT = QCLK/1024 EQEP_UNIT_POS_EVNT_DIV_2048 //!< UPEVNT = QCLK/2048 } EQEP_UPEVNTPrescale; //***************************************************************************** // //! Values that can be passed to EQEP_setStrobeSource() as the \e strobeSrc //! parameter. // //***************************************************************************** typedef enum { EQEP_STROBE_FROM_GPIO = 0, //!< Strobe signal comes from GPIO EQEP_STROBE_OR_ADCSOCA = 2, //!< Strobe signal is OR'd with ADCSOCA EQEP_STROBE_OR_ADCSOCB = 3 //!< Strobe signal is OR'd with ADCSOCB } EQEP_StrobeSource; //***************************************************************************** // //! Values that can be passed to EQEP_setQMAModuleMode() as the \e qmaMode //! parameter. // //***************************************************************************** typedef enum { EQEP_QMA_MODE_BYPASS, //!< QMA module is bypassed EQEP_QMA_MODE_1, //!< QMA mode-1 operation is selected EQEP_QMA_MODE_2 //!< QMA mode-2 operation is selected } EQEP_QMAMode; //***************************************************************************** // //! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode //! parameter. // //***************************************************************************** typedef enum { EQEP_EMULATIONMODE_STOPIMMEDIATELY, //!< Counters stop immediately EQEP_EMULATIONMODE_STOPATROLLOVER, //!< Counters stop at period rollover EQEP_EMULATIONMODE_RUNFREE //!< Counter unaffected by suspend }EQEP_EmulationMode; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks an eQEP base address. //! //! \param base specifies the eQEP module base address. //! //! This function determines if a eQEP module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enables the eQEP module. //! //! \param base is the base address of the eQEP module. //! //! This function enables operation of the enhanced quadrature encoder pulse //! (eQEP) module. The module must be configured before it is enabled. //! //! \sa EQEP_setConfig() //! //! \return None. // //***************************************************************************** static inline void EQEP_enableModule(uint32_t base) { // // Check the arguments. // ; // // Enable the eQEP module. // (*((volatile uint16_t *)(base + 0x15U))) |= 0x8U; } //***************************************************************************** // //! Disables the eQEP module. //! //! \param base is the base address of the enhanced quadrature encoder pulse //! (eQEP) module //! //! This function disables operation of the eQEP module. //! //! \return None. // //***************************************************************************** static inline void EQEP_disableModule(uint32_t base) { // // Check the arguments. // ; // // Disable the eQEP module. // (*((volatile uint16_t *)(base + 0x15U))) &= ~(0x8U); } //***************************************************************************** // //! Configures eQEP module's quadrature decoder unit. //! //! \param base is the base address of the eQEP module. //! \param config is the configuration for the eQEP module decoder unit. //! //! This function configures the operation of the eQEP module's quadrature decoder //! unit. The \e config parameter provides the configuration of the decoder //! and is the logical OR of several values: //! //! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify //! if both rising and falling edges should be counted or just rising edges. //! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR, //! \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if //! quadrature signals are being provided on QEPA and QEPB, if a direction //! signal and a clock are being provided, or if the direction should be //! hard-wired for a single direction with QEPA used for input. //! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the //! signals provided on QEPA and QEPB should be swapped before being //! processed. //! //! \return None. // //***************************************************************************** static inline void EQEP_setDecoderConfig(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the new decoder configuration to the hardware. // (*((volatile uint16_t *)(base + 0x14U))) = ((*((volatile uint16_t *)(base + 0x14U))) & ~(0x400U | 0x800U | 0xC000U)) | config; } //***************************************************************************** // //! Configures eQEP module position counter unit. //! //! \param base is the base address of the eQEP module. //! \param mode is the configuration for the eQEP module position counter. //! \param maxPosition specifies the maximum position value. //! //! This function configures the operation of the eQEP module position //! counter. The \e mode parameter determines the event on which the position //! counter gets reset. It should be passed one of the following values: //! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS, //! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT. //! //! \e maxPosition is the maximum value of the position counter and is //! the value used to reset the position capture when moving in the reverse //! (negative) direction. //! //! \return None. // //***************************************************************************** static inline void EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode, uint32_t maxPosition) { // // Check the arguments. // ; // // Write the position counter reset configuration to the hardware. // (*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) & ~0x3000U) | (uint16_t)mode; // // Set the maximum position. // (*((volatile uint32_t *)(base + 0x4U))) = maxPosition; } //***************************************************************************** // //! Gets the current encoder position. //! //! \param base is the base address of the eQEP module. //! //! This function returns the current position of the encoder. Depending upon //! the configuration of the encoder, and the incident of an index pulse, this //! value may or may not contain the expected data (that is, if in reset on //! index mode, if an index pulse has not been encountered, the position //! counter is not yet aligned with the index pulse). //! //! \return The current position of the encoder. // //***************************************************************************** static inline uint32_t EQEP_getPosition(uint32_t base) { // // Check the arguments. // ; // // Return the current position counter. // return((*((volatile uint32_t *)(base + 0x0U)))); } //***************************************************************************** // //! Sets the current encoder position. //! //! \param base is the base address of the eQEP module. //! \param position is the new position for the encoder. //! //! This function sets the current position of the encoder; the encoder //! position is then measured relative to this value. //! //! \return None. // //***************************************************************************** static inline void EQEP_setPosition(uint32_t base, uint32_t position) { // // Check the arguments. // ; // // Set the position counter. // (*((volatile uint32_t *)(base + 0x0U))) = position; } //***************************************************************************** // //! Gets the current direction of rotation. //! //! \param base is the base address of the eQEP module. //! //! This function returns the current direction of rotation. In this case, //! current means the most recently detected direction of the encoder; it may //! not be presently moving but this is the direction it last moved before it //! stopped. //! //! \return Returns 1 if moving in the forward direction or -1 if moving in the //! reverse direction. // //***************************************************************************** static inline int16_t EQEP_getDirection(uint32_t base) { int16_t direction; // // Check the arguments. // ; // // Return the direction of rotation. // if(((*((volatile uint16_t *)(base + 0x1CU))) & 0x20U) != 0U) { direction = 1; } else { direction = -1; } return(direction); } //***************************************************************************** // //! Enables individual eQEP module interrupt sources. //! //! \param base is the base address of the eQEP module. //! \param intFlags is a bit mask of the interrupt sources to be enabled. //! //! This function enables eQEP module interrupt sources. The \e intFlags //! parameter can be any of the following values OR'd together: //! - \b EQEP_INT_POS_CNT_ERROR - Position counter error //! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error //! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change //! - \b EQEP_INT_WATCHDOG - Watchdog time-out //! - \b EQEP_INT_UNDERFLOW - Position counter underflow //! - \b EQEP_INT_OVERFLOW - Position counter overflow //! - \b EQEP_INT_POS_COMP_READY - Position-compare ready //! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match //! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch //! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch //! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out //! - \b EQEP_INT_QMA_ERROR - QMA error //! //! \return None. // //***************************************************************************** static inline void EQEP_enableInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; // // Enable the specified interrupts. // (*((volatile uint16_t *)(base + 0x18U))) |= intFlags; } //***************************************************************************** // //! Disables individual eQEP module interrupt sources. //! //! \param base is the base address of the eQEP module. //! \param intFlags is a bit mask of the interrupt sources to be disabled. //! //! This function disables eQEP module interrupt sources. The \e intFlags //! parameter can be any of the following values OR'd together: //! - \b EQEP_INT_POS_CNT_ERROR - Position counter error //! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error //! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change //! - \b EQEP_INT_WATCHDOG - Watchdog time-out //! - \b EQEP_INT_UNDERFLOW - Position counter underflow //! - \b EQEP_INT_OVERFLOW - Position counter overflow //! - \b EQEP_INT_POS_COMP_READY - Position-compare ready //! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match //! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch //! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch //! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out //! - \b EQEP_INT_QMA_ERROR - QMA error //! //! \return None. // //***************************************************************************** static inline void EQEP_disableInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; // // Disable the specified interrupts. // (*((volatile uint16_t *)(base + 0x18U))) &= ~(intFlags); } //***************************************************************************** // //! Gets the current interrupt status. //! //! \param base is the base address of the eQEP module. //! //! This function returns the interrupt status for the eQEP module //! module. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! the following values: //! - \b EQEP_INT_GLOBAL - Global interrupt flag //! - \b EQEP_INT_POS_CNT_ERROR - Position counter error //! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error //! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change //! - \b EQEP_INT_WATCHDOG - Watchdog time-out //! - \b EQEP_INT_UNDERFLOW - Position counter underflow //! - \b EQEP_INT_OVERFLOW - Position counter overflow //! - \b EQEP_INT_POS_COMP_READY - Position-compare ready //! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match //! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch //! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch //! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out //! - \b EQEP_INT_QMA_ERROR - QMA error // //***************************************************************************** static inline uint16_t EQEP_getInterruptStatus(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0x19U)))); } //***************************************************************************** // //! Clears eQEP module interrupt sources. //! //! \param base is the base address of the eQEP module. //! \param intFlags is a bit mask of the interrupt sources to be cleared. //! //! This function clears eQEP module interrupt flags. The \e intFlags //! parameter can be any of the following values OR'd together: //! - \b EQEP_INT_GLOBAL - Global interrupt flag //! - \b EQEP_INT_POS_CNT_ERROR - Position counter error //! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error //! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change //! - \b EQEP_INT_WATCHDOG - Watchdog time-out //! - \b EQEP_INT_UNDERFLOW - Position counter underflow //! - \b EQEP_INT_OVERFLOW - Position counter overflow //! - \b EQEP_INT_POS_COMP_READY - Position-compare ready //! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match //! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch //! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch //! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out //! - \b EQEP_INT_QMA_ERROR - QMA error //! //! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In //! order to get any further eQEP interrupts, this flag must be cleared. //! //! \return None. // //***************************************************************************** static inline void EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; // // Clear the requested interrupt sources. // (*((volatile uint16_t *)(base + 0x1AU))) = intFlags; } //***************************************************************************** // //! Forces individual eQEP module interrupts. //! //! \param base is the base address of the eQEP module. //! \param intFlags is a bit mask of the interrupt sources to be forced. //! //! This function forces eQEP module interrupt flags. The \e intFlags //! parameter can be any of the following values OR'd together: //! - \b EQEP_INT_POS_CNT_ERROR //! - \b EQEP_INT_PHASE_ERROR //! - \b EQEP_INT_DIR_CHANGE //! - \b EQEP_INT_WATCHDOG //! - \b EQEP_INT_UNDERFLOW //! - \b EQEP_INT_OVERFLOW //! - \b EQEP_INT_POS_COMP_READY //! - \b EQEP_INT_POS_COMP_MATCH //! - \b EQEP_INT_STROBE_EVNT_LATCH //! - \b EQEP_INT_INDEX_EVNT_LATCH //! - \b EQEP_INT_UNIT_TIME_OUT //! - \b EQEP_INT_QMA_ERROR //! //! \return None. // //***************************************************************************** static inline void EQEP_forceInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // ; // // Force the specified interrupts. // (*((volatile uint16_t *)(base + 0x1BU))) |= intFlags; } //***************************************************************************** // //! Gets the encoder error indicator. //! //! \param base is the base address of the eQEP module. //! //! This function returns the error indicator for the eQEP module. It is an //! error for both of the signals of the quadrature input to change at the same //! time. //! //! \return Returns \b true if an error has occurred and \b false otherwise. // //***************************************************************************** static inline _Bool EQEP_getError(uint32_t base) { // // Check the arguments. // ; // // Return the error indicator. // return(((*((volatile uint16_t *)(base + 0x19U))) & 0x4U) != 0U); } //***************************************************************************** // //! Returns content of the eQEP module status register //! //! \param base is the base address of the eQEP module. //! //! This function returns the contents of the status register. The value it //! returns is an OR of the following values: //! //! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected //! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward //! movement) occurred on the first index event //! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation //! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last //! index event marker //! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer //! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position //! capture events //! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index //! pulse //! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred //! //! \return Returns the value of the QEP status register. // //***************************************************************************** static inline uint16_t EQEP_getStatus(uint32_t base) { // // Check the arguments. // ; // // Return the status register. // return((*((volatile uint16_t *)(base + 0x1CU))) & 0x00FFU); } //***************************************************************************** // //! Clears selected fields of the eQEP module status register //! //! \param base is the base address of the eQEP module. //! \param statusFlags is the bit mask of the status flags to be cleared. //! //! This function clears the status register fields indicated by //! \e statusFlags. The \e statusFlags parameter is the logical OR of any of //! the following: //! //! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected //! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer //! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position //! capture events //! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index //! pulse //! //! \note Only the above status fields can be cleared. All others are //! read-only, non-sticky fields. //! //! \return None. // //***************************************************************************** static inline void EQEP_clearStatus(uint32_t base, uint16_t statusFlags) { // // Check the arguments. // ; // // Clear the requested interrupt sources. // (*((volatile uint16_t *)(base + 0x1CU))) = statusFlags; } //***************************************************************************** // //! Configures eQEP module edge-capture unit. //! //! \param base is the base address of the eQEP module. //! \param capPrescale is the prescaler setting of the eQEP capture timer clk. //! \param evntPrescale is the prescaler setting of the unit position event //! frequency. //! //! This function configures the operation of the eQEP module edge-capture //! unit. The \e capPrescale parameter provides the configuration of the eQEP //! capture timer clock rate. It determines by which power of 2 between 1 and //! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in //! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For //! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock //! frequency that is SYSCLKOUT/32. //! //! The \e evntPrescale parameter determines how frequently a unit position //! event occurs. The macro that can be passed this parameter is in the format //! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock //! periods between unit position events. For example, //! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event //! frequency of QCLK/16. //! //! \return None. // //***************************************************************************** static inline void EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale, EQEP_UPEVNTPrescale evntPrescale) { // // Check the arguments. // ; // // Write new prescaler configurations to the appropriate registers. // (*((volatile uint16_t *)(base + 0x16U))) = ((*((volatile uint16_t *)(base + 0x16U))) & ~(0xFU | 0x70U)) | ((uint16_t)evntPrescale | (uint16_t)capPrescale); } //***************************************************************************** // //! Enables the eQEP module edge-capture unit. //! //! \param base is the base address of the eQEP module. //! //! This function enables operation of the eQEP module's edge-capture unit. //! //! \return None. // //***************************************************************************** static inline void EQEP_enableCapture(uint32_t base) { // // Check the arguments. // ; // // Enable edge capture. // (*((volatile uint16_t *)(base + 0x16U))) |= 0x8000U; } //***************************************************************************** // //! Disables the eQEP module edge-capture unit. //! //! \param base is the base address of the eQEP module. //! //! This function disables operation of the eQEP module's edge-capture unit. //! //! \return None. // //***************************************************************************** static inline void EQEP_disableCapture(uint32_t base) { // // Check the arguments. // ; // // Disable edge capture. // (*((volatile uint16_t *)(base + 0x16U))) &= ~(0x8000U); } //***************************************************************************** // //! Gets the encoder capture period. //! //! \param base is the base address of the eQEP module. //! //! This function returns the period count value between the last successive //! eQEP position events. //! //! \return The period count value between the last successive position events. // //***************************************************************************** static inline uint16_t EQEP_getCapturePeriod(uint32_t base) { // // Check the arguments. // ; // // Return the capture period. // return((*((volatile uint16_t *)(base + 0x1EU)))); } //***************************************************************************** // //! Gets the encoder capture timer value. //! //! \param base is the base address of the eQEP module. //! //! This function returns the time base for the edge capture unit. //! //! \return The capture timer value. // //***************************************************************************** static inline uint16_t EQEP_getCaptureTimer(uint32_t base) { // // Check the arguments. // ; // // Return the capture timer value. // return((*((volatile uint16_t *)(base + 0x1DU)))); } //***************************************************************************** // //! Enables the eQEP module position-compare unit. //! //! \param base is the base address of the eQEP module. //! //! This function enables operation of the eQEP module's position-compare unit. //! //! \return None. // //***************************************************************************** static inline void EQEP_enableCompare(uint32_t base) { // // Check the arguments. // ; // // Enable position compare. // (*((volatile uint16_t *)(base + 0x17U))) |= 0x1000U; } //***************************************************************************** // //! Disables the eQEP module position-compare unit. //! //! \param base is the base address of the eQEP module. //! //! This function disables operation of the eQEP module's position-compare //! unit. //! //! \return None. // //***************************************************************************** static inline void EQEP_disableCompare(uint32_t base) { // // Check the arguments. // ; // // Disable position compare. // (*((volatile uint16_t *)(base + 0x17U))) &= ~(0x1000U); } //***************************************************************************** // //! Configures the position-compare unit's sync output pulse width. //! //! \param base is the base address of the eQEP module. //! \param cycles is the width of the pulse that can be generated on a //! position-compare event. It is in units of 4 SYSCLKOUT cycles. //! //! This function configures the width of the sync output pulse. The width of //! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle. The //! maximum width is 4096 * 4 * SYSCLKOUT cycles. //! //! \return None. // //***************************************************************************** static inline void EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles) { // // Check the arguments. // ; ; // // Set the pulse width. // (*((volatile uint16_t *)(base + 0x17U))) = ((*((volatile uint16_t *)(base + 0x17U))) & ~0xFFFU) | (cycles - 1U); } //***************************************************************************** // //! Enables the eQEP module unit timer. //! //! \param base is the base address of the eQEP module. //! \param period is period value at which a unit time-out interrupt is set. //! //! This function enables operation of the eQEP module's peripheral unit timer. //! The unit timer is clocked by SYSCLKOUT and will set the unit time-out //! interrupt when it matches the value specified by \e period. //! //! \return None. // //***************************************************************************** static inline void EQEP_enableUnitTimer(uint32_t base, uint32_t period) { // // Check the arguments. // ; // // Set the period of the unit timer. // (*((volatile uint32_t *)(base + 0x10U))) = period; // // Enable peripheral unit timer. // (*((volatile uint16_t *)(base + 0x15U))) |= 0x2U; } //***************************************************************************** // //! Disables the eQEP module unit timer. //! //! \param base is the base address of the eQEP module. //! //! This function disables operation of the eQEP module's peripheral //! unit timer. //! //! \return None. // //***************************************************************************** static inline void EQEP_disableUnitTimer(uint32_t base) { // // Check the arguments. // ; // // Disable peripheral unit timer. // (*((volatile uint16_t *)(base + 0x15U))) &= ~(0x2U); } //***************************************************************************** // //! Enables the eQEP module watchdog timer. //! //! \param base is the base address of the eQEP module. //! \param period is watchdog period value at which a time-out will occur if //! no quadrature-clock event is detected. //! //! This function enables operation of the eQEP module's peripheral watchdog //! timer. //! //! \note When selecting \e period, note that the watchdog timer is clocked //! from SYSCLKOUT/64. //! //! \return None. // //***************************************************************************** static inline void EQEP_enableWatchdog(uint32_t base, uint16_t period) { // // Check the arguments. // ; // // Set the timeout count for the eQEP peripheral watchdog timer. // (*((volatile uint16_t *)(base + 0x13U))) = period; // // Enable peripheral watchdog. // (*((volatile uint16_t *)(base + 0x15U))) |= 0x1U; } //***************************************************************************** // //! Disables the eQEP module watchdog timer. //! //! \param base is the base address of the eQEP module. //! //! This function disables operation of the eQEP module's peripheral watchdog //! timer. //! //! \return None. // //***************************************************************************** static inline void EQEP_disableWatchdog(uint32_t base) { // // Check the arguments. // ; // // Disable peripheral watchdog. // (*((volatile uint16_t *)(base + 0x15U))) &= ~(0x1U); } //***************************************************************************** // //! Sets the eQEP module watchdog timer value. //! //! \param base is the base address of the eQEP module. //! \param value is the value to be written to the watchdog timer. //! //! This function sets the eQEP module's watchdog timer value. //! //! \return None. // //***************************************************************************** static inline void EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value) { // // Check the arguments. // ; // // Write the value to the watchdog timer register. // (*((volatile uint16_t *)(base + 0x12U))) = value; } //***************************************************************************** // //! Gets the eQEP module watchdog timer value. //! //! \param base is the base address of the eQEP module. //! //! \return Returns the current watchdog timer value. // //***************************************************************************** static inline uint16_t EQEP_getWatchdogTimerValue(uint32_t base) { // // Check the arguments. // ; // // Read the value from the watchdog timer register. // return((*((volatile uint16_t *)(base + 0x12U)))); } //***************************************************************************** // //! Configures the mode in which the position counter is initialized. //! //! \param base is the base address of the eQEP module. //! \param initMode is the configuration for initializing the position count. //! See below for a description of this parameter. //! //! This function configures the events on which the position count can be //! initialized. The \e initMode parameter provides the mode as either //! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following //! strobe events, index events, or a logical OR of both a strobe event and an //! index event. //! //! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify //! which strobe event will initialize the position counter. //! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify //! which index event will initialize the position counter. //! //! Use EQEP_setSWPositionInit() to cause a software initialization and //! EQEP_setInitialPosition() to set the value that gets loaded into the //! position counter upon initialization. //! //! \return None. // //***************************************************************************** static inline void EQEP_setPositionInitMode(uint32_t base, uint16_t initMode) { // // Check the arguments. // ; // // Set the init mode in the QEP Control register. // (*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) & ~(0x300U | 0xC00U)) | initMode; } //***************************************************************************** // //! Sets the software initialization of the encoder position counter. //! //! \param base is the base address of the eQEP module. //! \param initialize is a flag to specify if software initialization of the //! position counter is enabled. //! //! This function does a software initialization of the position counter when //! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit //! is cleared and no action is taken. //! //! The init value to be loaded into the position counter can be set with //! EQEP_setInitialPosition(). Additional initialization causes can be //! configured with EQEP_setPositionInitMode(). //! //! \return None. // //***************************************************************************** static inline void EQEP_setSWPositionInit(uint32_t base, _Bool initialize) { // // Check the arguments. // ; // // Set or clear the software initialization bit. // if(initialize) { (*((volatile uint16_t *)(base + 0x15U))) |= 0x80U; } else { (*((volatile uint16_t *)(base + 0x15U))) &= ~0x80U; } } //***************************************************************************** // //! Sets the init value for the encoder position counter. //! //! \param base is the base address of the eQEP module. //! \param position is the value to be written to the position counter upon. //! initialization. //! //! This function sets the init value for position of the encoder. See //! EQEP_setPositionInitMode() to set the initialization cause or //! EQEP_setSWPositionInit() to cause a software initialization. //! //! \return None. // //***************************************************************************** static inline void EQEP_setInitialPosition(uint32_t base, uint32_t position) { // // Check the arguments. // ; // // Write position to position counter init register // (*((volatile uint32_t *)(base + 0x2U))) = position; } //***************************************************************************** // //! Configures the quadrature modes in which the position count can be latched. //! //! \param base is the base address of the eQEP module. //! \param latchMode is the configuration for latching of the position count //! and several other registers. See below for a description of this //! parameter. //! //! This function configures the events on which the position count and several //! other registers can be latched. The \e latchMode parameter provides the //! mode as the logical OR of several values. //! //! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify //! the event that latches the position counter. This latch register can be //! read using EQEP_getPositionLatch(). The capture timer and capture //! period are also latched based on this setting, and can be read using //! EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch(). //! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE //! specify which strobe event will latch the position counter into the //! strobe position latch register. This register can be read with //! EQEP_getStrobePositionLatch(). //! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or //! \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the //! position counter into the index position latch register. This register //! can be read with EQEP_getIndexPositionLatch(). //! //! \return None. // //***************************************************************************** static inline void EQEP_setLatchMode(uint32_t base, uint32_t latchMode) { // // Check the arguments. // ; // // Set the latch mode in the QEP Control register. // (*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) & ~(0x4U | 0x30U | 0x40U)) | latchMode; } //***************************************************************************** // //! Gets the encoder position that was latched on an index event. //! //! \param base is the base address of the eQEP module. //! //! This function returns the value in the index position latch register. The //! position counter is latched into this register on either a rising index //! edge, a falling index edge, or a software index marker. This is configured //! using EQEP_setLatchMode(). //! //! \return The position count latched on an index event. // //***************************************************************************** static inline uint32_t EQEP_getIndexPositionLatch(uint32_t base) { // // Check the arguments. // ; // // Return the current position counter. // return((*((volatile uint32_t *)(base + 0x8U)))); } //***************************************************************************** // //! Gets the encoder position that was latched on a strobe event. //! //! \param base is the base address of the eQEP module. //! //! This function returns the value in the strobe position latch register. The //! position counter can be configured to be latched into this register on //! rising strobe edges only or on rising strobe edges while moving clockwise //! and falling strobe edges while moving counter-clockwise. This is configured //! using EQEP_setLatchMode(). //! //! \return The position count latched on a strobe event. // //***************************************************************************** static inline uint32_t EQEP_getStrobePositionLatch(uint32_t base) { // // Check the arguments. // ; // // Return the current position counter. // return((*((volatile uint32_t *)(base + 0xAU)))); } //***************************************************************************** // //! Gets the encoder position that was latched on a unit time-out event. //! //! \param base is the base address of the eQEP module. //! //! This function returns the value in the position latch register. The //! position counter is latched into this register either on a unit time-out //! event. //! //! \return The position count latch register value. // //***************************************************************************** static inline uint32_t EQEP_getPositionLatch(uint32_t base) { // // Check the arguments. // ; // // Return the current position counter. // return((*((volatile uint32_t *)(base + 0xCU)))); } //***************************************************************************** // //! Gets the encoder capture timer latch. //! //! \param base is the base address of the eQEP module. //! //! This function returns the value in the capture timer latch register. The //! capture timer value is latched into this register either on a unit time-out //! event or upon the CPU reading the eQEP position counter. This is configured //! using EQEP_setLatchMode(). //! //! \return The edge-capture timer latch value. // //***************************************************************************** static inline uint16_t EQEP_getCaptureTimerLatch(uint32_t base) { // // Check the arguments. // ; // // Return the current position counter. // return((*((volatile uint16_t *)(base + 0x1FU)))); } //***************************************************************************** // //! Gets the encoder capture period latch. //! //! \param base is the base address of the eQEP module. //! //! This function returns the value in the capture period latch register. The //! capture period value is latched into this register either on a unit //! time-out event or upon the CPU reading the eQEP position counter. This is //! configured using EQEP_setLatchMode(). //! //! \return The edge-capture period latch value. // //***************************************************************************** static inline uint16_t EQEP_getCapturePeriodLatch(uint32_t base) { // // Check the arguments. // ; // // Return the current position counter. // return((*((volatile uint16_t *)(base + 0x20U)))); } //***************************************************************************** // //! Set the quadrature mode adapter (QMA) module mode //! //! \param base is the base address of the eQEP module. //! \param qmaMode is the mode in which the QMA module will operate. //! //! This function sets the quadrature mode adapter module mode. The possible //! modes are passed to the function through the \e qmaMode parameter which //! can take the values EQEP_QMA_MODE_BYPASS, EQEP_QMA_MODE_1, or //! EQEP_QMA_MODE_2. //! //! To use the QMA module, you must first put the eQEP module into //! direction-count mode (\b EQEP_CONFIG_CLOCK_DIR) using EQEP_setConfig(). //! //! \return None. // //***************************************************************************** static inline void EQEP_setQMAModuleMode(uint32_t base, EQEP_QMAMode qmaMode) { // // Check the arguments. // ; // // Write the QMA module mode into the appropriate register. // (*((volatile uint16_t *)(base + 0x34U))) = ((*((volatile uint16_t *)(base + 0x34U))) & ~0x7U) | (uint16_t)qmaMode; } //***************************************************************************** // //! Set the strobe input source of the eQEP module. //! //! \param base is the base address of the eQEP module. //! \param strobeSrc is the source of the strobe signal. //! //! This function sets the source of the eQEP module's strobe signal. The //! possible values of the \e strobeSrc parameter are //! - \b EQEP_STROBE_FROM_GPIO - The strobe is used as-is after passing through //! the polarity select logic. //! - \b EQEP_STROBE_OR_ADCSOCA - The strobe is OR'd with the ADCSOCA signal //! after passing through the polarity select logic. //! - \b EQEP_STROBE_OR_ADCSOCB - The strobe is OR'd with the ADCSOCB signal //! after passing through the polarity select logic. //! //! \return None. // //***************************************************************************** static inline void EQEP_setStrobeSource(uint32_t base, EQEP_StrobeSource strobeSrc) { // // Check the arguments. // ; // // Write the strobe source selection into the appropriate register. // (*((volatile uint16_t *)(base + 0x32U))) = ((*((volatile uint16_t *)(base + 0x32U))) & ~0x3U) | (uint16_t)strobeSrc; } //***************************************************************************** // //! Set the emulation mode of the eQEP module. //! //! \param base is the base address of the eQEP module. //! \param emuMode is the mode operation upon an emulation suspend. //! //! This function sets the eQEP module's emulation mode. This mode determines //! how the timers are affected by an emulation suspend. Valid values for the //! \e emuMode parameter are the following: //! //! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog //! counter, unit timer, and capture timer all stop immediately. //! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog //! counter, unit timer all count until period rollover. The capture timer //! counts until the next unit period event. //! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter, //! unit timer, and capture timer are all unaffected by an emulation suspend. //! //! \return None. // //***************************************************************************** static inline void EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode) { // // Check the arguments. // ; // // Write the emulation mode to the FREE_SOFT bits. // (*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) & ~0xC000U) | ((uint16_t)emuMode << 14U); } //***************************************************************************** // //! Configures eQEP module position-compare unit. //! //! \param base is the base address of the eQEP module. //! \param config is the configuration for the eQEP module //! position-compare unit. See below for a description of this parameter. //! \param compareValue is the value to which the position count value is //! compared for a position-compare event. //! \param cycles is the width of the pulse that can be generated on a //! position-compare event. It is in units of 4 SYSCLKOUT cycles. //! //! This function configures the operation of the eQEP module position-compare //! unit. The \e config parameter provides the configuration of the //! position-compare unit and is the logical OR of several values: //! //! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or //! \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse //! and which pin should be used. //! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or //! \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when //! should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP. //! //! The \e cycles is used to select the width of the sync output pulse. The //! width of the resulting pulse will be \e cycles * 4 * the width of a //! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles. //! //! \note You can set the sync pulse width independently using the //! EQEP_setComparePulseWidth() function. //! //! \return None. // //***************************************************************************** extern void EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, uint16_t cycles); //***************************************************************************** // //! Sets the polarity of the eQEP module's input signals. //! //! \param base is the base address of the eQEP module. //! \param invertQEPA is the flag to negate the QEPA input. //! \param invertQEPB is the flag to negate the QEPA input. //! \param invertIndex is the flag to negate the index input. //! \param invertStrobe is the flag to negate the strobe input. //! //! This function configures the polarity of the inputs to the eQEP module. To //! negate the polarity of any of the input signals, pass \b true into its //! corresponding parameter in this function. Pass \b false to leave it as-is. //! //! \return None. // //***************************************************************************** extern void EQEP_setInputPolarity(uint32_t base, _Bool invertQEPA, _Bool invertQEPB, _Bool invertIndex, _Bool invertStrobe); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: flash.h // // TITLE: C28x Flash driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup flash_api Flash //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_flash.h // // TITLE: Definitions for the FLASH registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the FLASH register offsets // //***************************************************************************** // Register // Register // Register // Register 1 // Register 2 // Register // Low // High //***************************************************************************** // // The following are defines for the bit fields in the FRDCNTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FBAC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FBFALLBACK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FBPRDY register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FPAC1 register // //***************************************************************************** // Mode //***************************************************************************** // // The following are defines for the bit fields in the FPAC2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FMSTAT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FRD_INTF_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ECC_ENABLE register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ERR_STATUS register // //***************************************************************************** // Corrected Value 0 // Corrected Value 1 // error occurred // Corrected Value 0 // Corrected Value 1 // error occurred //***************************************************************************** // // The following are defines for the bit fields in the ERR_POS register // //***************************************************************************** // Error in lower 64 bits // Error in upper 64 bits //***************************************************************************** // // The following are defines for the bit fields in the ERR_STATUS_CLR register // //***************************************************************************** // Corrected Value 0 Clear // Corrected Value 1 Clear // error occurred Clear // Corrected Value 0 Clear // Corrected Value 1 Clear // error occurred Clear //***************************************************************************** // // The following are defines for the bit fields in the ERR_CNT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ERR_THRESHOLD register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ERR_INTFLG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ERR_INTCLR register // //***************************************************************************** // Clear // Clear //***************************************************************************** // // The following are defines for the bit fields in the FADDR_TEST register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FECC_TEST register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FECC_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FECC_STATUS register // //***************************************************************************** // Error // Error // Bits of Error #pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc"); #pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc"); //***************************************************************************** // //! Values that can be passed to Flash_setBankPowerMode() as the bank parameter. // //***************************************************************************** typedef enum { FLASH_BANK0 = 0x0, //!< Bank 0 FLASH_BANK1 = 0x1 //!< Bank 1 } Flash_BankNumber; //***************************************************************************** // //! Values that can be passed to Flash_setBankPowerMode() as the powerMode //! parameter. // //***************************************************************************** typedef enum { FLASH_BANK_PWR_SLEEP = 0x0, //!< Sleep fallback mode FLASH_BANK_PWR_STANDBY = 0x1, //!< Standby fallback mode FLASH_BANK_PWR_ACTIVE = 0x3 //!< Active fallback mode } Flash_BankPowerMode; //***************************************************************************** // //! Values that can be passed to Flash_setPumpPowerMode() as the powerMode //! parameter. // //***************************************************************************** typedef enum { FLASH_PUMP_PWR_SLEEP = 0x0, //!< Sleep fallback mode FLASH_PUMP_PWR_ACTIVE = 0x1 //!< Active fallback mode } Flash_PumpPowerMode; //***************************************************************************** // //! Type that correspond to values returned from Flash_getLowErrorStatus() and //! Flash_getHighErrorStatus() determining the error status code. // //***************************************************************************** typedef enum { FLASH_NO_ERR = 0x0, //!< No error FLASH_FAIL_0 = 0x1, //!< Fail on 0 FLASH_FAIL_1 = 0x2, //!< Fail on 1 FLASH_UNC_ERR = 0x4 //!< Uncorrectable error } Flash_ErrorStatus; //***************************************************************************** // //! Values that can be returned from Flash_getLowErrorType() and //! Flash_getHighErrorType() determining the error type. // //***************************************************************************** typedef enum { FLASH_DATA_ERR = 0x0, //!< Data error FLASH_ECC_ERR = 0x1 //!< ECC error } Flash_ErrorType; //***************************************************************************** // //! Values that can be returned from Flash_getECCTestSingleBitErrorType(). // //***************************************************************************** typedef enum { FLASH_DATA_BITS = 0x0, //!< Data bits FLASH_CHECK_BITS = 0x1 //!< ECC bits } Flash_SingleBitErrorIndicator; //***************************************************************************** // // Values that can be passed to Flash_clearLowErrorStatus and // Flash_clearHighErrorStatus. // //***************************************************************************** //***************************************************************************** // // Values that can be returned from Flash_getInterruptFlag and // Flash_getECCTestStatus. // //***************************************************************************** //***************************************************************************** // // Delay instruction that allows for register configuration to complete. // //***************************************************************************** //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks a flash wrapper base address for the control registers. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! This function determines if a flash wrapper control base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks a flash wrapper base address for the ECC registers. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function determines if a flash wrapper ECC base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Sets the random read wait state amount. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param waitstates is the wait-state value. //! //! This function sets the number of wait states for a flash read access. The //! \e waitstates parameter is a number between 0 and 15. It is \b important //! to look at your device's datasheet for information about what the required //! minimum flash wait-state is for your selected SYSCLK frequency. //! //! By default the wait state amount is configured to the maximum 15. //! //! \return None. // //***************************************************************************** static inline void Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates) { // // Check the arguments. // ; ; __eallow(); // // Write flash read wait-state amount to appropriate register. // (*((volatile uint32_t *)(ctrlBase + 0x0U))) = ((*((volatile uint32_t *)(ctrlBase + 0x0U))) & ~(uint32_t)0xF00U) | ((uint32_t)waitstates << 8U); __edis(); } //***************************************************************************** // //! Sets the fallback power mode of a flash bank. //! //! \param ctrlBase is the base address of the flash wrapper registers. //! \param bank is the flash bank that is being configured. //! \param powerMode is the power mode to be entered. //! //! This function sets the fallback power mode of the flash bank specified by //! them \e bank parameter. The power mode is specified by the \e powerMode //! parameter with one of the following values: //! //! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled. //! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference //! enabled. //! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled. //! //! \return None. // //***************************************************************************** static inline void Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank, Flash_BankPowerMode powerMode) { // // Check the arguments. // ; __eallow(); // // Write the power mode to the appropriate register. // (*((volatile uint32_t *)(ctrlBase + 0x20U))) = ((*((volatile uint32_t *)(ctrlBase + 0x20U))) & ~((0x3U) << ((uint32_t)bank * 2U))) | ((uint32_t)powerMode << ((uint32_t)bank * 2U)); __edis(); } //***************************************************************************** // //! Sets the fallback power mode of the charge pump. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param powerMode is the power mode to be entered. //! //! This function sets the fallback power mode flash charge pump. //! //! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled. //! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active. //! //! \return None. // //***************************************************************************** static inline void Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode) { // // Check the arguments. // ; __eallow(); // // Write the power mode to the appropriate register. // (*((volatile uint32_t *)(ctrlBase + 0x24U))) = ((*((volatile uint32_t *)(ctrlBase + 0x24U))) & ~(uint32_t)0x1U) | (uint32_t)powerMode; __edis(); } //***************************************************************************** // //! Enables prefetch mechanism. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! \return None. // //***************************************************************************** static inline void Flash_enablePrefetch(uint32_t ctrlBase) { // // Check the arguments. // ; __eallow(); // // Set the prefetch enable bit. // (*((volatile uint32_t *)(ctrlBase + 0x180U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disables prefetch mechanism. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! \return None. // //***************************************************************************** static inline void Flash_disablePrefetch(uint32_t ctrlBase) { // // Check the arguments. // ; __eallow(); // // Clear the prefetch enable bit. // (*((volatile uint32_t *)(ctrlBase + 0x180U))) &= ~(uint32_t)0x1U; __edis(); } //***************************************************************************** // //! Enables data cache. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! \return None. // //***************************************************************************** static inline void Flash_enableCache(uint32_t ctrlBase) { // // Check the arguments. // ; __eallow(); // // Set the data cache enable bit. // (*((volatile uint32_t *)(ctrlBase + 0x180U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Disables data cache. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! \return None. // //***************************************************************************** static inline void Flash_disableCache(uint32_t ctrlBase) { // // Check the arguments. // ; __eallow(); // // Clear the data cache enable bit. // (*((volatile uint32_t *)(ctrlBase + 0x180U))) &= ~(uint32_t)0x2U; __edis(); } //***************************************************************************** // //! Enables flash error correction code (ECC) protection. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_enableECC(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); // // Write the key value 0xA to ECC_ENABLE register. // (*((volatile uint32_t *)(eccBase + 0x0U))) = ((*((volatile uint32_t *)(eccBase + 0x0U))) & ~(uint32_t)0xFU) | 0xAU; __edis(); } //***************************************************************************** // //! Disables flash error correction code (ECC) protection. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_disableECC(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); // // Clear ECC enable field with the one's complement of the key. // (*((volatile uint32_t *)(eccBase + 0x0U))) = ((*((volatile uint32_t *)(eccBase + 0x0U))) & ~(uint32_t)0xFU) | 0x5U; __edis(); } //***************************************************************************** // //! Sets the bank active grace period. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param period is the starting count value for the BAGP down counter. //! //! This function sets the bank active grace period specified by the //! \e period parameter. The \e period is a value between 0 and 255. This //! value must be greater than 1 when the fallback mode is not Active. //! //! \return None. // //***************************************************************************** static inline void Flash_setBankActiveGracePeriod(uint32_t ctrlBase, uint32_t period) { // // Check the arguments. // ; ; __eallow(); // // Write period to the BAGP of the FBAC register. // (*((volatile uint32_t *)(ctrlBase + 0x1EU))) = ((*((volatile uint32_t *)(ctrlBase + 0x1EU))) & ~(uint32_t)0xFF00U) | (period << 8U); __edis(); } //***************************************************************************** // //! Sets the pump active grace period. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param period is the starting count value for the PAGP down counter. //! //! This function sets the pump active grace period specified by the //! \e period parameter. The \e period is a value between 0 and 65535. The //! counter is reloaded after any flash access. After the counter expires, the //! charge pump falls back to the power mode determined by FPAC1, bit PMPPWR. //! //! \return None. // //***************************************************************************** static inline void Flash_setPumpActiveGracePeriod(uint32_t ctrlBase, uint16_t period) { // // Check the arguments. // ; __eallow(); // // Write period to the PAGP of the FPAC2 register. // (*((volatile uint32_t *)(ctrlBase + 0x26U))) = ((*((volatile uint32_t *)(ctrlBase + 0x26U))) & ~(uint32_t)0xFFFFU) | ((uint32_t)period << 0U); __edis(); } //***************************************************************************** // //! Sets the pump wake up time. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump //! to wakeup. //! //! This function sets the wakeup time with \e sysclkCycles parameter. //! The \e sysclkCycles is a value between 0 and 8190. When the charge pump //! exits sleep power mode, it will take sysclkCycles to wakeup. //! //! \return None. // //***************************************************************************** static inline void Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles) { // // Check the arguments. // ; ; __eallow(); // // Write sysclkCycles/2 to PSLEEP of the FPAC1 register. // (*((volatile uint32_t *)(ctrlBase + 0x24U))) = ((*((volatile uint32_t *)(ctrlBase + 0x24U))) & ~(uint32_t)0xFFF0000U) | (((uint32_t)sysclkCycles/(uint32_t)2) << (uint32_t)16U); __edis(); } //***************************************************************************** // //! Reads the bank active power state. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param bank is the flash bank that is being used. //! //! \return Returns \b true if the Bank is in Active power state and \b false //! otherwise. // //***************************************************************************** static inline _Bool Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank) { // // Check the arguments. // ; _Bool ready; uint32_t bitMask = (uint32_t)0x1U << (uint32_t)bank; // // Return the BANKXRDY bit in FBPRDY. // if(((*((volatile uint32_t *)(ctrlBase + 0x22U))) & bitMask) == bitMask) { ready = 1; } else { ready = 0; } return(ready); } //***************************************************************************** // //! Reads the pump active power state. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! \return Returns \b true if the Pump is in Active power state and \b false //! otherwise. // //***************************************************************************** static inline _Bool Flash_isPumpReady(uint32_t ctrlBase) { // // Check the arguments. // ; _Bool ready; // // Return the PUMPRDY bit in FBPRDY. // if(((*((volatile uint32_t *)(ctrlBase + 0x22U))) & (uint32_t)0x8000U) == 0x8000U) { ready = 1; } else { ready = 0; } return(ready); } //***************************************************************************** // //! Gets the single error address low. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the 32-bit address of the single bit error that //! occurred in the lower 64-bits of a 128-bit memory-aligned data. The //! returned address is to that 64-bit aligned data. //! //! \return Returns the 32 bits of a 64-bit aligned address where a single bit //! error occurred. // //***************************************************************************** static inline uint32_t Flash_getSingleBitErrorAddressLow(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x2U)))); } //***************************************************************************** // //! Gets the single error address high. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the 32-bit address of the single bit error that //! occurred in the upper 64-bits of a 128-bit memory-aligned data. The //! returned address is to that 64-bit aligned data. //! //! \return Returns the 32 bits of a 64-bit aligned address where a single bit //! error occurred. // //***************************************************************************** static inline uint32_t Flash_getSingleBitErrorAddressHigh(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x4U)))); } //***************************************************************************** // //! Gets the uncorrectable error address low. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the 32-bit address of the uncorrectable error that //! occurred in the lower 64-bits of a 128-bit memory-aligned data. The //! returned address is to that 64-bit aligned data. //! //! \return Returns the 32 bits of a 64-bit aligned address where an //! uncorrectable error occurred. // //***************************************************************************** static inline uint32_t Flash_getUncorrectableErrorAddressLow(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x6U)))); } //***************************************************************************** // //! Gets the uncorrectable error address high. //! //! \param eccBase is the base address of the flash wrapper ECC base. //! //! This function returns the 32-bit address of the uncorrectable error that //! occurred in the upper 64-bits of a 128-bit memory-aligned data. The //! returned address is to that 64-bit aligned data. //! //! \return Returns the 32 bits of a 64-bit aligned address where an //! uncorrectable error occurred. // //***************************************************************************** static inline uint32_t Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x8U)))); } //***************************************************************************** // //! Gets the error status of the Lower 64-bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the error status of the lower 64-bits of a 128-bit //! aligned address. //! //! \return Returns value of the low error status bits which can be used with //! Flash_ErrorStatus type. // //***************************************************************************** static inline Flash_ErrorStatus Flash_getLowErrorStatus(uint32_t eccBase) { // // Check the arguments. // ; // // Get the Low Error Status bits // return((Flash_ErrorStatus)((*((volatile uint32_t *)(eccBase + 0xAU))) & (uint32_t)0x7U)); } //***************************************************************************** // //! Gets the error status of the Upper 64-bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the error status of the upper 64-bits of a 128-bit //! aligned address. //! //! \return Returns value of the high error status bits which can be used with //! Flash_ErrorStatus type. // //***************************************************************************** static inline Flash_ErrorStatus Flash_getHighErrorStatus(uint32_t eccBase) { // // Check the arguments. // ; // // Get the High Error Status bits // return((Flash_ErrorStatus)(((*((volatile uint32_t *)(eccBase + 0xAU))) >> 16U) & (uint32_t)0x7U)); } //***************************************************************************** // //! Gets the error position of the lower 64-bits for a single bit error. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the error position of the lower 64-bits. If the //! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges //! from 0-63 for FLASH_DATA_ERR. //! //! \return Returns the position of the lower error bit. // //***************************************************************************** static inline uint32_t Flash_getLowErrorPosition(uint32_t eccBase) { // // Check the arguments. // ; return(((*((volatile uint32_t *)(eccBase + 0xCU))) & (uint32_t)0x3FU) >> 0U); } //***************************************************************************** // //! Gets the error position of the upper 64-bits for a single bit error. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the error position of the upper 64-bits. If the //! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges //! from 0-63 for FLASH_DATA_ERR. //! //! \return Returns the position of the upper error bit. // //***************************************************************************** static inline uint32_t Flash_getHighErrorPosition(uint32_t eccBase) { // // Check the arguments. // ; return(((*((volatile uint32_t *)(eccBase + 0xCU))) & (uint32_t)0x3F0000U) >> 16U); } //***************************************************************************** // //! Clears the error position bit of the lower 64-bits for a single bit error. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function clears the error position bit of the lower 64-bits. //! //! \return None // //***************************************************************************** static inline void Flash_clearLowErrorPosition(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0xCU))) &= ~(uint32_t)0x3FU; __edis(); } //***************************************************************************** // //! Clears the error position of the upper 64-bits for a single bit error. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function clears the error position bit of the upper 64-bits. //! //! \return None. // //***************************************************************************** static inline void Flash_clearHighErrorPosition(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0xCU))) &= ~(uint32_t)0x3F0000U; __edis(); } //***************************************************************************** // //! Gets the error type of the lower 64-bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the error type of the lower 64-bits. The error type //! can be FLASH_ECC_ERR or FLASH_DATA_ERR. //! //! \return Returns the type of the lower 64-bit error. // //***************************************************************************** static inline Flash_ErrorType Flash_getLowErrorType(uint32_t eccBase) { // // Check the arguments. // ; // // Check which error type. // If bit is 1 then ECC error, else it is a Data error. // return((Flash_ErrorType)(((*((volatile uint32_t *)(eccBase + 0xCU))) & (uint32_t)0x100U) >> 8U)); } //***************************************************************************** // //! Gets the error type of the upper 64-bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the error type of the upper 64-bits. The error type //! can be FLASH_ECC_ERR or FLASH_DATA_ERR. //! //! \return Returns the type of the upper 64-bit error. // //***************************************************************************** static inline Flash_ErrorType Flash_getHighErrorType(uint32_t eccBase) { // // Check the arguments. // ; // // Check which error type. // If bit is 1 then ECC error, else it is a Data error. // return((Flash_ErrorType)(((*((volatile uint32_t *)(eccBase + 0xCU))) & (uint32_t)0x1000000U) >> 24U)); } //***************************************************************************** // //! Clears the errors status of the lower 64-bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param errorStatus is the error status to clear. errorStatus is a uint16_t. //! errorStatus is a bitwise OR of the following value: //! //! - \b FLASH_FAIL_0_CLR //! - \b FLASH_FAIL_1_CLR //! - \b FLASH_UNC_ERR_CLR //! //! \return None. // //***************************************************************************** static inline void Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus) { // // Check the arguments. // ; ; __eallow(); (*((volatile uint32_t *)(eccBase + 0xEU))) |= ((uint32_t)errorStatus); __edis(); } //***************************************************************************** // //! Clears the errors status of the upper 64-bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param errorStatus is the error status to clear. errorStatus is a uint16_t. //! errorStatus is a bitwise OR of the following value: //! //! - \b FLASH_FAIL_0_CLR //! - \b FLASH_FAIL_1_CLR //! - \b FLASH_UNC_ERR_CLR //! //! \return None. // //***************************************************************************** static inline void Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus) { // // Check the arguments. // ; ; __eallow(); (*((volatile uint32_t *)(eccBase + 0xEU))) |= ((uint32_t)errorStatus << 16U); __edis(); } //***************************************************************************** // //! Gets the single bit error count. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return Returns the single bit error count. // //***************************************************************************** static inline uint32_t Flash_getErrorCount(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x10U))) & (uint32_t)0xFFFFU); } //***************************************************************************** // //! Sets the single bit error threshold. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param threshold is the single bit error threshold. Valid ranges are from //! 0-65535. //! //! \return None. // //***************************************************************************** static inline void Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x12U))) = ((uint32_t)threshold & (uint32_t)0xFFFFU); __edis(); } //***************************************************************************** // //! Gets the error interrupt. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the type of error interrupt that occurred. The //! values can be used with //! - \b FLASH_NO_ERROR //! - \b FLASH_SINGLE_ERROR //! - \b FLASH_UNC_ERROR //! //! \return Returns the interrupt flag. // //***************************************************************************** static inline uint32_t Flash_getInterruptFlag(uint32_t eccBase) { // // Check the arguments. // ; // // Read which type of error occurred. // return(((*((volatile uint32_t *)(eccBase + 0x14U))) & (uint32_t)0x3U)); } //***************************************************************************** // //! Clears the single error interrupt flag. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_clearSingleErrorInterruptFlag(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x16U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Clears the uncorrectable error interrupt flag. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_clearUncorrectableInterruptFlag(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x16U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Sets the Data Low Test register for ECC testing. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param data is a 32-bit value that is the low double word of selected //! 64-bit data //! //! \return None. // //***************************************************************************** static inline void Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x1AU))) = data; __edis(); } //***************************************************************************** // //! Sets the Data High Test register for ECC testing. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param data is a 32-bit value that is the high double word of selected //! 64-bit data //! //! \return None. // //***************************************************************************** static inline void Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x18U))) = data; __edis(); } //***************************************************************************** // //! Sets the test address register for ECC testing. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param address is a 32-bit value containing an address. Bits 21-3 will be //! used as the flash word (128-bit) address. //! //! This function left shifts the address 1 bit to convert it to a byte address. //! //! \return None. // //***************************************************************************** static inline void Flash_setECCTestAddress(uint32_t eccBase, uint32_t address) { // // Check the arguments. // ; // // Left shift the address 1 bit to make it byte-addressable // uint32_t byteAddress = address << 1; __eallow(); // // Write bits 21-3 to the register. // (*((volatile uint32_t *)(eccBase + 0x1CU))) = byteAddress; __edis(); } //***************************************************************************** // //! Sets the ECC test bits for ECC testing. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param ecc is a 32-bit value. The least significant 8 bits are used as //! the ECC Control Bits in the ECC Test. //! //! \return None. // //***************************************************************************** static inline void Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc) { // // Check the arguments. // ; ; __eallow(); // // Write the 8 ECC Control Bits. // (*((volatile uint32_t *)(eccBase + 0x1EU))) = ((uint32_t)ecc & (uint32_t)0xFFU); __edis(); } //***************************************************************************** // //! Enables ECC Test mode. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_enableECCTestMode(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x20U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disables ECC Test mode. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_disableECCTestMode(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x20U))) &= ~(uint32_t)0x1U; __edis(); } //***************************************************************************** // //! Selects the ECC block on bits [63:0] of bank data. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_selectLowECCBlock(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x20U))) &= ~(uint32_t)0x2U; __edis(); } //***************************************************************************** // //! Selects the ECC block on bits [127:64] of bank data. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_selectHighECCBlock(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x20U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Performs the ECC calculation on the test block. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return None. // //***************************************************************************** static inline void Flash_performECCCalculation(uint32_t eccBase) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(eccBase + 0x20U))) |= 0x4U; __edis(); } //***************************************************************************** // //! Gets the ECC Test data out high 63:32 bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return Returns the ECC TEst data out High. // //***************************************************************************** static inline uint32_t Flash_getTestDataOutHigh(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x22U)))); } //***************************************************************************** // //! Gets the ECC Test data out low 31:0 bits. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return Returns the ECC Test data out Low. // //***************************************************************************** static inline uint32_t Flash_getTestDataOutLow(uint32_t eccBase) { // // Check the arguments. // ; return((*((volatile uint32_t *)(eccBase + 0x24U)))); } //***************************************************************************** // //! Gets the ECC Test status. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! This function returns the ECC test status. The values can be used with //! - \b FLASH_NO_ERROR //! - \b FLASH_SINGLE_ERROR //! - \b FLASH_UNC_ERROR //! //! \return Returns the ECC test status. // //***************************************************************************** static inline uint32_t Flash_getECCTestStatus(uint32_t eccBase) { // // Check the arguments. // ; // // Read which type of error occurred. // return(((*((volatile uint32_t *)(eccBase + 0x26U))) & (uint32_t)0x3U)); } //***************************************************************************** // //! Gets the ECC Test single bit error position. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return Returns the ECC Test single bit error position. If the error type //! is check bits than the position can range from 0 to 7. If the error type //! is data bits than the position can range from 0 to 63. // //***************************************************************************** static inline uint32_t Flash_getECCTestErrorPosition(uint32_t eccBase) { // // Check the arguments. // ; // // Read the position bits and shift it to the right. // return(((*((volatile uint32_t *)(eccBase + 0x26U))) & (uint32_t)0xFCU) >> 2U); } //***************************************************************************** // //! Gets the single bit error type. //! //! \param eccBase is the base address of the flash wrapper ECC registers. //! //! \return Returns the single bit error type as a //! Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS //! indicate where the single bit error occurred. // //***************************************************************************** static inline Flash_SingleBitErrorIndicator Flash_getECCTestSingleBitErrorType(uint32_t eccBase) { // // Check the arguments. // ; // // Read the ERR_TYPE bit to see where the single bit error was. // return((Flash_SingleBitErrorIndicator) (((*((volatile uint32_t *)(eccBase + 0x26U))) & (uint32_t)0x100U) >> 8U)); } //***************************************************************************** // //! Initializes the flash control registers. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! \param eccBase is the base address of the flash wrapper ECC registers. //! \param waitstates is the wait-state value. //! //! This function initializes the flash control registers. At reset bank and //! pump are in sleep. A flash access will power up the bank and pump //! automatically. After a flash access, bank and pump go to low power mode //! (configurable in FBFALLBACK/FPAC1 registers) if there is no further access //! to flash. This function will power up Flash bank and pump and set the //! fallback mode of flash and pump as active. //! //! This function also sets the number of wait-states for a flash access //! (see Flash_setWaitstates() for more details), and enables cache, the //! prefetch mechanism, and ECC. //! //! \return None. // //***************************************************************************** extern void Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates); //***************************************************************************** // //! Powers down the flash. //! //! \param ctrlBase is the base address of the flash wrapper control registers. //! //! This function powers down the flash bank(s) and the flash pump. //! //! \return None. // //***************************************************************************** void Flash_powerDown(uint32_t ctrlBase); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: fsi.h // // TITLE: C28x FSI Driver API header file // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup fsi_api FSI //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_fsi.h // // TITLE: Definitions for the FSI registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the FSI register offsets // //***************************************************************************** // register // register // register low // register high // register // data register // control load register // control status register // register // reference // count // control register // register // register // status flag register // clear register // force register // register // buffer // register // register // register // data register // register // status flag register // and computed CRC // register // force register // register // register // control register // counter reference // current count // register // reference // count // register for RX_INT1 // register for RX_INT2 // register // register // register // register 1 // buffer //***************************************************************************** // // The following are defines for the bit fields in the TX_MASTER_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_CLK_CTRL register // //***************************************************************************** // Divider //***************************************************************************** // // The following are defines for the bit fields in the TX_OPER_CTRL_LO register // //***************************************************************************** // Select // Select //***************************************************************************** // // The following are defines for the bit fields in the TX_OPER_CTRL_HI register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_FRAME_CTRL register // //***************************************************************************** // Transmitted //***************************************************************************** // // The following are defines for the bit fields in the TX_FRAME_TAG_UDATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_BUF_PTR_LOAD register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_BUF_PTR_STS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_PING_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_PING_TAG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_INT_CTRL register // //***************************************************************************** // to INT1 // Interrupt to INT1 // Interrupt to INT1 // to INT1 // to INT2 // Interrupt to INT2 // Interrupt to INT2 // to INT2 //***************************************************************************** // // The following are defines for the bit fields in the TX_DMA_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_LOCK_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_EVT_STS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_EVT_CLR register // //***************************************************************************** // Clear //***************************************************************************** // // The following are defines for the bit fields in the TX_EVT_FRC register // //***************************************************************************** // Force //***************************************************************************** // // The following are defines for the bit fields in the TX_USER_CRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_ECC_DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TX_ECC_VAL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_MASTER_CTRL register // //***************************************************************************** // Behaviour //***************************************************************************** // // The following are defines for the bit fields in the RX_OPER_CTRL register // //***************************************************************************** // Received // Select //***************************************************************************** // // The following are defines for the bit fields in the RX_FRAME_INFO register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_FRAME_TAG_UDATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_DMA_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_EVT_STS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_CRC_INFO register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_EVT_CLR register // //***************************************************************************** // Clear // Clear // Clear // Clear // Clear // Clear // Clear //***************************************************************************** // // The following are defines for the bit fields in the RX_EVT_FRC register // //***************************************************************************** // Force // Force // Force // Force // Force // Force // Force //***************************************************************************** // // The following are defines for the bit fields in the RX_BUF_PTR_LOAD register // //***************************************************************************** // pointer //***************************************************************************** // // The following are defines for the bit fields in the RX_BUF_PTR_STS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_FRAME_WD_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_PING_WD_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_PING_TAG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_INT1_CTRL register // //***************************************************************************** // Interrupt to INT1 // Interrupt to INT1 // INT1 // Interrupt to INT1 // Interrupt to INT1 // Interrupt to INT1 // to INT1 // Interrupt to INT1 // Interrupt to INT1 // Interrupt to INT1 // Interrupt to INT1 // Interrupt to INT1 //***************************************************************************** // // The following are defines for the bit fields in the RX_INT2_CTRL register // //***************************************************************************** // Interrupt to INT2 // Interrupt to INT2 // to INT2 // Interrupt to INT2 // Interrupt to INT2 // Interrupt to INT2 // to INT2 // Interrupt to INT2 // Interrupt to INT2 // Interrupt to INT2 // Interrupt to INT2 // Interrupt to INT2 //***************************************************************************** // // The following are defines for the bit fields in the RX_LOCK_CTRL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_ECC_DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_ECC_VAL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_ECC_LOG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the RX_DLYLINE_CTRL register // //***************************************************************************** // RXCLK // RXD0 // RXD1 //***************************************************************************** // // The following are defines for the bit fields in the RX_VIS_1 register // //***************************************************************************** //***************************************************************************** // FSI Tx defines //***************************************************************************** //! \brief FSI Tx events defines //! //! \details Values that can be passed to APIs to enable/disable interrupts and //! also to set/get/clear event status on FSI Tx operation. //! //! There are 4 supported interrupts related to Tx events- //! All are available as event status as well excecpt 4th one. //! 1) frame transmission done //! 2) transmit buffer is underrun //! 3) transmit buffer is overrun //! 4) ping counter timeout //! //! Ping frame transmission upon hardware trigger(ping watchdog or //! external trigger) is shown as event status. //! //! \brief Mask of all Tx Events, ORing all event defines //! //! \brief Maximum number of external input for triggering frame-transmission //! //! \brief Shifts needed to control FSI Tx interrupt generation on INT2 //! //***************************************************************************** // FSI Rx Defines //***************************************************************************** //! \brief FSI Rx event defines //! //! \details Values that can be passed to APIs to enable/disable interrupts and //! also to set/get/clear event status on FSI Rx operation. //! //! There are 12 supported interrupts related to Rx events- //! All are available as event status as well. //! 1) ping watchdog times out //! 2) frame watchdog times out //! 3) mismatch between hardware computed CRC and received CRC.This //! status should be ignored if user chooses SW CRC computation //! 4) invalid Frame type detected //! 5) invalid EndofFrame bit-pattern //! 6) buffer Overrun in Rx buffer //! 7) received frame without errors //! 8) software reads empty Rx buffer //! 9) received error frame //! 10) received ping frame //! 11) software didn't clear FRAME_DONE flag after receiving new //! frame //! 12) received data frame //! //! \brief Mask of all Rx Events, ORing all event defines //! //! \brief Maximum value in Rx delay line tap control //! //***************************************************************************** // Common defines for both FSI Tx and Rx //***************************************************************************** //! \brief Maximum data length(16 words) for user/software defined data frame //! //! \brief Maximum value for user data field(8 bits) //! //! \brief Maximum value of Buffer pointer offset(4 bits) //! //! \brief Key value for writing some FSI Tx/Rx registers //! //***************************************************************************** // typedefs //***************************************************************************** //! \brief Data lines used for transmit/receive operation //! //! \details Supported number of data lines is only 2 - 1 lane or 2 lanes //! typedef enum { FSI_DATA_WIDTH_1_LANE = 0x0000U, FSI_DATA_WIDTH_2_LANE = 0x0001U } FSI_DataWidth; //! \brief List of TX submodules that can be reset, can be used with reset APIs //! //! \details Three kind of resets can be made- //! 1) reset entire Tx Module //! 2) reset only TX clock //! 3) reset ping timeout counter //! typedef enum { FSI_TX_MASTER_CORE_RESET = 0x0000U, FSI_TX_CLOCK_RESET = 0x0001U, FSI_TX_PING_TIMEOUT_CNT_RESET = 0x0002U } FSI_TxSubmoduleInReset; //! \brief Start Mode for Tx frame transmission //! //! \details Three start modes(i.e. how transmission will start) are supported- //! 1. SW write of START bit in \b TX_PKT_CTRL register //! 2. Rising edge on external trigger //! 3. Either SW write of START bit or Frame completion //! typedef enum { FSI_TX_START_FRAME_CTRL = 0x0000U, FSI_TX_START_EXT_TRIG = 0x0001U, FSI_TX_START_FRAME_CTRL_OR_UDATA_TAG = 0x0002U } FSI_TxStartMode; //! \brief Various FSI frame types //! //! \details Three frame types exist- //! - \b Ping: Used for checking line integrity, can be sent by //! software or automatically by hardware. //! - \b Error: Used typically during error conditions or when one //! side wants to signal the other side for attention. //! - \b Data: Two subtypes exist based on data-length- //! a) \b Fixed (1/2/4/6 words) //! b) \b Nwords Software programs number of data words //! //! \note 4 bit code for frame types- 0x1, 0x2 and 0x8 to 0xE are reserved //! typedef enum { FSI_FRAME_TYPE_PING = 0x0000U, FSI_FRAME_TYPE_ERROR = 0x000FU, FSI_FRAME_TYPE_1WORD_DATA = 0x0004U, FSI_FRAME_TYPE_2WORD_DATA = 0x0005U, FSI_FRAME_TYPE_4WORD_DATA = 0x0006U, FSI_FRAME_TYPE_6WORD_DATA = 0x0007U, FSI_FRAME_TYPE_NWORD_DATA = 0x0003U } FSI_FrameType; //! \brief Possible values of a FSI frame //! //! \details 4 bit field inside FSI frame is available to set tag value(0-15) //! typedef enum { FSI_FRAME_TAG0 = 0x0000U, FSI_FRAME_TAG1 = 0x0001U, FSI_FRAME_TAG2 = 0x0002U, FSI_FRAME_TAG3 = 0x0003U, FSI_FRAME_TAG4 = 0x0004U, FSI_FRAME_TAG5 = 0x0005U, FSI_FRAME_TAG6 = 0x0006U, FSI_FRAME_TAG7 = 0x0007U, FSI_FRAME_TAG8 = 0x0008U, FSI_FRAME_TAG9 = 0x0009U, FSI_FRAME_TAG10 = 0x000AU, FSI_FRAME_TAG11 = 0x000BU, FSI_FRAME_TAG12 = 0x000CU, FSI_FRAME_TAG13 = 0x000DU, FSI_FRAME_TAG14 = 0x000EU, FSI_FRAME_TAG15 = 0x000FU } FSI_FrameTag; //! \brief Ping timeout mode //! //! \details Ping timeout can reset and restart only on hardware initiated PING //! frames (PING Watchdog timeout) //! OR //! on any software initiated frame being sent out also based on //! which mode is selected //! typedef enum { FSI_PINGTIMEOUT_ON_HWINIT_PING_FRAME = 0x0000U, FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME = 0x0001U } FSI_PingTimeoutMode; //! \brief ECC Computation width- 16 bit or 32 bit //! typedef enum { FSI_32BIT_ECC_COMPUTE = 0x0000U, FSI_16BIT_ECC_COMPUTE = 0x0001U } FSI_ECCComputeWidth; //! \brief Interrupt lines supported in FSI //! //! \details Any event on FSI Tx or Rx can be enabled to trigger interrupt on 2 //! interrupt lines to CPU/CLA- \b INT1 and \b INT2 //! typedef enum { FSI_INT1 = 0x0000U, FSI_INT2 = 0x0001U } FSI_InterruptNum; //! \brief List of RX modules that can be reset, can be used with reset APIs //! //! \details Three submodules can be reset- //! 1) RX master core //! 2) frame watchdog counter //! 3) ping watchdog counter //! typedef enum { FSI_RX_MASTER_CORE_RESET = 0x0000U, FSI_RX_FRAME_WD_CNT_RESET = 0x0001U, FSI_RX_PING_WD_CNT_RESET = 0x0002U } FSI_RxSubmoduleInReset; //! \brief Available Rx lines for delay tap selection //! //! \details Delay tapping can be done on 3 lines- 1)RXCLK 2)RXD0 and 3)RXD1 //! typedef enum { FSI_RX_DELAY_CLK = 0x0000U, FSI_RX_DELAY_D0 = 0x0001U, FSI_RX_DELAY_D1 = 0x0002U } FSI_RxDelayTapType; //! \brief Indexes of available EPWM SOC triggers //! //! \details There are 16 ePWM SOC events as external triggers for FSI frame //! transfers. Indexes 0:7 and 24:31 are reserved out of total 32 //! muxed external triggers. //! typedef enum { FSI_EXT_TRIGSRC_EPWM1_SOCA = 8, FSI_EXT_TRIGSRC_EPWM1_SOCB, FSI_EXT_TRIGSRC_EPWM2_SOCA, FSI_EXT_TRIGSRC_EPWM2_SOCB, FSI_EXT_TRIGSRC_EPWM3_SOCA, FSI_EXT_TRIGSRC_EPWM3_SOCB, FSI_EXT_TRIGSRC_EPWM4_SOCA, FSI_EXT_TRIGSRC_EPWM4_SOCB, FSI_EXT_TRIGSRC_EPWM5_SOCA, FSI_EXT_TRIGSRC_EPWM5_SOCB, FSI_EXT_TRIGSRC_EPWM6_SOCA, FSI_EXT_TRIGSRC_EPWM6_SOCB, FSI_EXT_TRIGSRC_EPWM7_SOCA, FSI_EXT_TRIGSRC_EPWM7_SOCB, FSI_EXT_TRIGSRC_EPWM8_SOCA, FSI_EXT_TRIGSRC_EPWM8_SOCB } FSI_ExtFrameTriggerSrc; //***************************************************************************** // FSI Tx function prototypes/defintion //***************************************************************************** //***************************************************************************** // //! \brief Validates if FSI-Tx base address is correct //! //! \param[in] base is the base address of the FSI-Tx module //! //! \return returns \b true if the base address is valid and \b false otherwise // //***************************************************************************** //***************************************************************************** // //! \brief Sends FLUSH pattern //! //! \details FLUSH pattern (toggle data lines followed by toggle on clocks) //! should be sent only when FSI Tx is not under \b SOFT_RESET and the //! clock to the transmit core has been turned ON. //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_sendTxFlush(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= ((uint16_t)0x2U | ((0x00A5U) << 8U)); __edis(); } //***************************************************************************** // //! \brief Stops FLUSH pattern transmission //! //! \details Transmission of FLUSH pattern should be stopped before starting //! sending frames. Generally during initilization a pair of send/stop //! APIs for FLUSH pattern is called to clear data/clock lines. //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_stopTxFlush(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = (((~0x2U) & (*((volatile uint16_t *)(base + 0x0U)))) | ((0x00A5U) << 8U)); __edis(); } //***************************************************************************** // //! \brief Selects PLL clock as source for clock dividers //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_selectTxPLLClock(uint32_t base) { // // Check the arguments. // ; __eallow(); // // Set PLLCLK as source for clock divider // (*((volatile uint16_t *)(base + 0x4U))) |= 0x100U; __edis(); } //***************************************************************************** // //! \brief sets clock division prescalar and enables the transmit clock //! //! \param[in] base is the FSI Tx module base address //! \param[in] preScaleValue used to generate transmit clock, it defines the //! division value of /2,/3,/4,etc. of \b PLLcLK //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxClock(uint32_t base, uint16_t preScaleValue) { // // Check the arguments. // ; ; __eallow(); // // Set prescalar value // (*((volatile uint16_t *)(base + 0x2U))) = ((*((volatile uint16_t *)(base + 0x2U))) & (~0x3FCU)) | (preScaleValue << 2U); // // Enable Tx clock // (*((volatile uint16_t *)(base + 0x2U))) |= 0x2U; __edis(); } //***************************************************************************** // //! \brief Disables transmit clock //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxClock(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x2U))) &= ~0x2U; __edis(); } //***************************************************************************** // //! \brief Sets Data width for transmission //! //! \param[in] base is the FSI Tx module base address //! \param[in] dataWidth selection between 1 or 2 lane transmission //! //! \return None. // //***************************************************************************** static inline void FSI_setTxDataWidth(uint32_t base, FSI_DataWidth dataWidth) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & (~0x3U)) | (uint16_t)dataWidth; __edis(); } //***************************************************************************** // //! \brief Enables SPI compatible mode //! //! \details FSI supports a \b compatibility mode in order to communicate with //! \b legacy peripherals like \b SPI. Only the 16-bit mode of SPI will //! be supported. All the frame structures, CRC checks and will be //! identical to the normal FSI frames. //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxSPIMode(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x4U; __edis(); } //***************************************************************************** // //! \brief Disables SPI compatible mode //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxSPIMode(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x4U; __edis(); } //***************************************************************************** // //! \brief Sets start mode for any frame transmission //! //! \param[in] base is the FSI Tx module base address //! \param[in] txStartMode is one of supported 3 start modes in transmission //! //! \return None. // //***************************************************************************** static inline void FSI_setTxStartMode(uint32_t base, FSI_TxStartMode txStartMode) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & (~0x38U)) | ((uint16_t)txStartMode << 3U); __edis(); } //***************************************************************************** // //! \brief Setting for when Ping timeout can reset and restart //! //! \param[in] base is the FSI Tx module base address //! \param[in] pingTimeoutMode can be HW or both HW/SW initiated //! //! \return None. // //***************************************************************************** static inline void FSI_setTxPingTimeoutMode(uint32_t base, FSI_PingTimeoutMode pingTimeoutMode) { // // Check the arguments. // ; __eallow(); if(pingTimeoutMode == FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME) { (*((volatile uint16_t *)(base + 0x4U))) |= 0x80U; } else { (*((volatile uint16_t *)(base + 0x4U))) &= ~0x80U; } __edis(); } //***************************************************************************** // //! \brief Sets a particular external input to trigger transmission //! //! \param[in] base is the FSI Tx module base address //! \param[in] extInputNum can be one of ports from 0 to 31 //! //! \return None. // //***************************************************************************** static inline void FSI_setTxExtFrameTrigger(uint32_t base, uint16_t extInputNum) { // // Check the arguments. // ; ; __eallow(); (*((volatile uint16_t *)(base + 0x5U))) = ((*((volatile uint16_t *)(base + 0x5U))) & (~0x1FU)) | extInputNum; __edis(); } //***************************************************************************** // //! \brief Enables CRC value of a data frame to be forced to zero //! //! \details CRC value of the data frame will be forced to 0 whenever there is //! a transmission and buffer over-run or under-run condition happens. //! The idea is to force a corruption of the CRC since the data is not //! guaranteed to be reliable //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxCRCForceError(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x5U))) |= 0x20U; __edis(); } //***************************************************************************** // //! \brief Disables forcing of CRC value of a data frame to zero //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxCRCForceError(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x5U))) &= ~0x20U; __edis(); } //***************************************************************************** // //! \brief Select between 16-bit and 32-bit ECC computation //! //! \param[in] base is the FSI Tx module base address //! \param[in] eccComputeWidth is ECC Computation width //! //! \return None. // //***************************************************************************** static inline void FSI_setTxECCComputeWidth(uint32_t base, FSI_ECCComputeWidth eccComputeWidth) { // // Check the arguments. // ; __eallow(); if(eccComputeWidth == FSI_16BIT_ECC_COMPUTE) { (*((volatile uint16_t *)(base + 0x5U))) |= 0x40U; } else { (*((volatile uint16_t *)(base + 0x5U))) &= ~0x40U; } __edis(); } //***************************************************************************** // //! \brief Sets frame type for transmission //! //! \param[in] base is the FSI Tx module base address //! \param[in] frameType value of frame type //! //! \return None. // //***************************************************************************** static inline void FSI_setTxFrameType(uint32_t base, FSI_FrameType frameType) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x6U))) = ((*((volatile uint16_t *)(base + 0x6U))) & (~0xFU)) | (uint16_t)frameType; } //***************************************************************************** // //! \brief Sets the frame size if frame type is user/software defined frame //! //! \param[in] base is the FSI Tx module base address //! \param[in] nWords is number of data words in a software defined frame //! //! \return None. // //***************************************************************************** static inline void FSI_setTxSoftwareFrameSize(uint32_t base, uint16_t nWords) { // // Check the arguments. // ; ; (*((volatile uint16_t *)(base + 0x6U))) = ((*((volatile uint16_t *)(base + 0x6U))) & (~0xF0U)) | ((nWords - 1) << 4U); } //***************************************************************************** // //! \brief Starts transmitting frames //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_startTxTransmit(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x6U))) |= 0x8000U; } //***************************************************************************** // //! \brief Sets frame tag for transmission //! //! \param[in] base is the FSI Tx module base address //! \param[in] frameTag value of frame tag, 4 bit value (0 to 15) //! //! \return None. // //***************************************************************************** static inline void FSI_setTxFrameTag(uint32_t base, FSI_FrameTag frameTag) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x7U))) = ((*((volatile uint16_t *)(base + 0x7U))) & (~0xFU)) | (uint16_t)frameTag; } //***************************************************************************** // //! \brief Sets user defined data for transmission //! It is an extra data field(8 bit) apart from regular data //! //! \param[in] base is the FSI Tx module base address //! \param[in] userDefData 8 bit user defined data value //! //! \return None. // //***************************************************************************** static inline void FSI_setTxUserDefinedData(uint32_t base, uint16_t userDefData) { // // Check the arguments. // ; ; (*((volatile uint16_t *)(base + 0x7U))) = ((*((volatile uint16_t *)(base + 0x7U))) & (~0xFF00U)) | (userDefData << 8U); } //***************************************************************************** // //! \brief Sets the value for transmit buffer pointer at desired location //! //! \param[in] base is the FSI Tx module base address //! \param[in] bufPtrOff 4 bit offset pointer in Tx buffer where transmitter //! will pick the data //! //! \return None. // //***************************************************************************** static inline void FSI_setTxBufferPtr(uint32_t base, uint16_t bufPtrOff) { // // Check the arguments. // ; ; __eallow(); (*((volatile uint16_t *)(base + 0x8U))) = bufPtrOff; __edis(); } //***************************************************************************** // //! \brief Returns current buffer pointer location //! //! \param[in] base is the FSI Tx module base address //! //! \return current buffer pointer location //! //! \note there could be lag due to synchronization hence value is accurate //! only when no current transmission is happening // //***************************************************************************** static inline uint16_t FSI_getTxBufferPtr(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0x9U))) & 0xFU); } //***************************************************************************** // //! \brief Returns valid number of data words present in buffer which have not //! been transmitted yet //! //! \param[in] base is the FSI Tx module base address //! //! \return number of data words present in buffer which have not been //! transmitted yet //! \note there could be lag due to synchronization hence value is accurate //! only when no current transmission is happening // //***************************************************************************** static inline uint16_t FSI_getTxWordCount(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0x9U))) & 0x1F00U) >> 8U); } //***************************************************************************** // //! \brief Enables ping timer logic and once set time elapses it sends signal //! to transmitter to send ping frame //! //! \param[in] base is the FSI Tx module base address //! \param[in] refValue 32 bit reference value for ping time-out counter //! \param[in] pingFrameTag 4 bit tag value for ping time-out counter //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxPingTimer(uint32_t base, uint32_t refValue, FSI_FrameTag pingFrameTag) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0xBU))) = (uint16_t)pingFrameTag; __eallow(); (*((volatile uint32_t *)(base + 0xCU))) = refValue; (*((volatile uint16_t *)(base + 0xAU))) |= 0x2U; __edis(); } //***************************************************************************** // //! \brief Sets the ping tag value, used by either timeout counter initiated //! PING frame transfer or by external ping trigger input. //! //! \param[in] base is the FSI Tx module base address //! \param[in] frameTag 4 bit tag value for ping time-out counter //! //! \return None. // //***************************************************************************** static inline void FSI_setTxPingTag(uint32_t base, FSI_FrameTag frameTag) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0xBU))) = (uint16_t)frameTag; } //***************************************************************************** // //! \brief Disables ping timer logic //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxPingTimer(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0xAU))) &= ~0x2U; __edis(); } //***************************************************************************** // //! \brief Enables external trigger to transmit a ping frame //! //! \param[in] base is the FSI Tx module base address //! \param[in] extTrigSel 5 bit value which selects among 32 external inputs //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxExtPingTrigger(uint32_t base, uint16_t extTrigSel) { // // Check the arguments. // ; ; __eallow(); // // Select external input trigger // (*((volatile uint16_t *)(base + 0xAU))) = ((*((volatile uint16_t *)(base + 0xAU))) & (~0xF8U)) | (extTrigSel << 3U); // // Enable ping frame transmission through external trigger // (*((volatile uint16_t *)(base + 0xAU))) |= 0x4U; __edis(); } //***************************************************************************** // //! \brief Disables external trigger logic //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxExtPingTrigger(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0xAU))) &= ~0x4U; __edis(); } //***************************************************************************** // //! \brief Gives Current value of Ping Timeout Logic Counter //! //! \param[in] base is the FSI Tx module base address //! //! \return Current value of counter is returned // //***************************************************************************** static inline uint32_t FSI_getTxCurrentPingTimeoutCounter(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint32_t *)(base + 0xEU)))); } //***************************************************************************** // //! \brief Enables to generate DMA event on completion of a frame transfer //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxDMAEvent(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x11U))) |= 0x1U; __edis(); } //***************************************************************************** // //! \brief Disable to generate DMA event on completion of a frame transfer //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxDMAEvent(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x11U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! \brief Locks the control of all transmit control registers,once locked //! further writes will not take effect until system reset occurs //! //! \param[in] base is the FSI Tx module base address //! //! \note System reset only can unlock registers once locked. //! //! \return None. // //***************************************************************************** static inline void FSI_lockTxCtrl(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x12U))) = ((uint16_t)0x1U | ((0x00A5U) << 8U)); __edis(); } //***************************************************************************** // //! \brief Returns current status of all the error flags //! //! \param[in] base is the FSI Tx module base address //! //! \return the status of error flags,each bit of integer is associated with //! one error flag. //! //! Example Usage - function will set the bits corresponding to respective //! error flag in return value //! evtStatus = FSI_getTxEventStatus(FSI_base) //! if bit value of evtStatus is 12(01100) means //! FSI_TX_EVT_OVERRUN and FSI_TX_EVT_PING_HW_TRIG flags are set // //***************************************************************************** static inline uint16_t FSI_getTxEventStatus(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0x14U))) & (0x000FU)); } //***************************************************************************** // //! \brief Enables user to set TX error flags //! //! \param[in] base is the FSI Tx module base address //! \param[in] evtFlags contains list of event and error flags that are //! supposed to be set. //! //! \details Writing a 1 to this bit position will cause the corresponding bit //! in \b TX_EVT_ERR_STATUS register to get set. The purpose of this //! register is to allow software to simulate the effect of the event //! and test the associated software/ISR. //! //! Example Usage //! evtFlags = FSI_TX_EVT_FRAME_DONE & FSI_TX_EVT_OVERRUN //! FSI_forceTxEvents(FSI_base,evtFlags) //! Above call sets error flag to frameDone and overRun events //! //! \return None. // //***************************************************************************** static inline void FSI_forceTxEvents(uint32_t base, uint16_t evtFlags) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x17U))) = (evtFlags & (0x000FU)); __edis(); } //***************************************************************************** // //! \brief Enables user to clear TX error flags //! //! \param[in] base is the FSI Tx module base address //! \param[in] evtFlags contains list of event and error flags that are //! supposed to be cleared. //! //! \details Writing a 1 to this bit position will cause the corresponding bit //! in the TX_EVT_ERR_STATUS register to get cleared to 0 //! //! \return None. // //***************************************************************************** static inline void FSI_clearTxEvents(uint32_t base, uint16_t evtFlags) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x16U))) = (evtFlags & (0x000FU)); __edis(); } //***************************************************************************** // //! \brief Sets the CRC value to be picked transmission if transmission is //! configured to use user defined SW CRC //! //! \param[in] base is the FSI Tx module base address //! \param[in] userCRCValue is user defined CRC //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxUserCRC(uint32_t base, uint16_t userCRCValue) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x40U; __edis(); (*((volatile uint16_t *)(base + 0x18U))) = userCRCValue; } //***************************************************************************** // //! \brief Sets the CRC value to be picked transmission if transmission is //! configured to use user defined SW CRC //! //! \param[in] base is the FSI Tx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxUserCRC(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x40U; __edis(); } //***************************************************************************** // //! \brief Sets data for ECC logic computaion //! //! \param[in] base is the FSI Tx module base address //! \param[in] data data value for which ECC needs to be computed //! //! \return None. // //***************************************************************************** static inline void FSI_setTxECCdata(uint32_t base, uint32_t data) { // // Check the arguments. // ; (*((volatile uint32_t *)(base + 0x20U))) = data; } //***************************************************************************** // //! \brief Returns ECC value evaluated for 16/32 bit data //! //! \param[in] base is the FSI Tx module base address //! //! \return ECC value for input data // //***************************************************************************** static inline uint16_t FSI_getTxECCValue(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0x22U))) & 0xFFU); } //***************************************************************************** // //! \brief Enables user to generate interrupt on occurrence of FSI_TxEventList //! events //! //! \param[in] base is the FSI Tx module base address //! \param[in] intNum is the type of interrupt to be generated //! interrupt1 or interrupt2 //! \param[in] intFlags contains list of events on which interrupt //! should be generated. //! //! Example Usage //! intFlags = FSI_TX_EVT_FRAME_DONE && FSI_TX_EVT_BUF_OVERRUN //! && FSI_TX_EVT_PING_TIMEOUT //! FSI_enableTxInterrupt(FSI_base, FSI_INT1, intFlags) //! above configuration will generate signal on interrupt line 1 upon //! frameDone, BufOverRun and PingTimeOut event //! //! \return None. // //***************************************************************************** static inline void FSI_enableTxInterrupt(uint32_t base, FSI_InterruptNum intNum, uint16_t intFlags) { // // Check the arguments. // ; __eallow(); if(intNum == FSI_INT1) { (*((volatile uint16_t *)(base + 0x10U))) |= (intFlags & (0x000FU)); } else { (*((volatile uint16_t *)(base + 0x10U))) |= ((intFlags & (0x000FU)) << (0x8U)); } __edis(); } //***************************************************************************** // //! \brief Enables user to disable generation interrupt on occurrence of //! FSI_TxEventList events //! //! \param[in] base is the FSI Tx module base address //! \param[in] intNum is the type of interrupt to be generated //! interrupt1 or interrupt2 //! \param[in] intFlags contains list of events on which interrupt //! generation has to be disabled. //! //! \return None. // //***************************************************************************** static inline void FSI_disableTxInterrupt(uint32_t base, FSI_InterruptNum intNum, uint16_t intFlags) { // // Check the arguments. // ; __eallow(); if(intNum == FSI_INT1) { (*((volatile uint16_t *)(base + 0x10U))) &= ~(intFlags & (0x000FU)); } else { (*((volatile uint16_t *)(base + 0x10U))) &= ((~(intFlags & (0x000FU)) << (0x8U)) | 0xFFU); } __edis(); } //***************************************************************************** // //! \brief Returns address of Tx data buffer //! //! \details Data buffer is consisting of 16 words from offset- 0x40 to 0x4e //! //! \param[in] base is the FSI Tx module base address //! //! \return Tx data buffer address // //***************************************************************************** static inline uint32_t FSI_getTxBufferAddress(uint32_t base) { // // Check the arguments. // ; return(base + 0x40U); } //***************************************************************************** // //! \brief Resets clock or ping timeout counter or entire TX module //! //! \param[in] base is the FSI Tx module base address //! \param[in] moduleName the name of submodule which is supposed to be reset //! //! \return None. // //***************************************************************************** extern void FSI_resetTxModule(uint32_t base, FSI_TxSubmoduleInReset submodule); //***************************************************************************** // //! \brief Clears reset on clock or ping timeout counter or entire TX module //! //! \param[in] base is the FSI Tx module base address //! \param[in] moduleName the name of submodule, to be brought out of reset //! //! \return None. // //***************************************************************************** extern void FSI_clearTxModuleReset(uint32_t base, FSI_TxSubmoduleInReset submodule); //***************************************************************************** // //! \brief Writes data in FSI Tx buffer //! //! \param[in] base is the FSI Tx module base address //! \param[in] array is the address of the array of words to be transmitted. //! \param[in] length is the number of words in the array to be transmitted. //! \param[in] bufOffset is the offset in Tx buffer where data will be written //! //! \note Data Overwrite protection is implemented in this function by ensuring //! not more than 16 words are written and also wrap around case is taken //! care when more words need to be written if last write happens at //! maximum offset in Tx buffer //! //! \return None. // //***************************************************************************** extern void FSI_writeTxBuffer(uint32_t base, const uint16_t array[], uint16_t length, uint16_t bufOffset); //***************************************************************************** //***************************************************************************** // FSI Rx function prototypes/definitions //***************************************************************************** //***************************************************************************** // //! \brief Checks the FSI-Rx base address //! //! \param base is the base address of the FSI-Rx module //! //! \return returns \b true if the base address is valid and \b false otherwise // //***************************************************************************** //***************************************************************************** // //! \brief Enables internal loopback where mux will select //! internal pins coming from TX module instead of what comes from pins //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableRxInternalLoopback(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= ((uint16_t)0x2U | ((0x00A5U) << 8U)); __edis(); } //***************************************************************************** // //! \brief Disables internal loopback where mux will not use internal pins //! coming from TX module //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxInternalLoopback(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & (~0x2U)) | ((0x00A5U) << 8U); __edis(); } //***************************************************************************** // //! \brief Receive clock is selected from the internal port coming //! from TX module //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableRxSPIPairing(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x0U))) |= ((uint16_t)0x4U | ((0x00A5U) << 8U)); __edis(); } //***************************************************************************** // //! \brief Selects regular receive clock coming from the pins //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxSPIPairing(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & (~0x4U)) | ((0x00A5U) << 8U); __edis(); } //***************************************************************************** // //! \brief Selects number of data lines used for receiving //! //! \param[in] base is the FSI Rx module base address //! \param[in] dataWidth selection between 1 or 2 lane receive operation //! //! \return None. // //***************************************************************************** static inline void FSI_setRxDataWidth(uint32_t base, FSI_DataWidth dataWidth) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & (~0x3U)) | (uint16_t)dataWidth; __edis(); } //***************************************************************************** // //! \brief Enables SPI compatible mode in FSI Rx //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableRxSPIMode(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x4U; __edis(); } //***************************************************************************** // //! \brief Disables SPI compatible mode in FSI Rx //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxSPIMode(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x4U; __edis(); } //***************************************************************************** // //! \brief Sets the frame size if frame type is user/software defined frame //! //! \param[in] base is the FSI Rx module base address //! \param[in] nWords is number of data words in a software defined frame //! //! \return None. // //***************************************************************************** static inline void FSI_setRxSoftwareFrameSize(uint32_t base, uint16_t nWords) { // // Check the arguments. // ; ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & (~0x78U)) | ((nWords - 1) << 3U); __edis(); } //***************************************************************************** // //! \brief Select between 16-bit and 32-bit ECC computation //! //! \param[in] base is the FSI Rx module base address //! \param[in] eccComputeWidth is ECC Computation width //! //! \return None. // //***************************************************************************** static inline void FSI_setRxECCComputeWidth(uint32_t base, FSI_ECCComputeWidth eccComputeWidth) { // // Check the arguments. // ; __eallow(); if(eccComputeWidth == FSI_16BIT_ECC_COMPUTE) { (*((volatile uint16_t *)(base + 0x4U))) |= 0x80U; } else { (*((volatile uint16_t *)(base + 0x4U))) &= ~0x80U; } __edis(); } //***************************************************************************** // //! \brief Setting for when Ping timeout can reset and restart //! //! \param[in] base is the FSI Rx module base address //! \param[in] pingTimeoutMode can be HW or both HW/SW initiated //! //! \return None. // //***************************************************************************** static inline void FSI_setRxPingTimeoutMode(uint32_t base, FSI_PingTimeoutMode pingTimeoutMode) { // // Check the arguments. // ; __eallow(); if(pingTimeoutMode == FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME) { (*((volatile uint16_t *)(base + 0x4U))) |= 0x100U; } else { (*((volatile uint16_t *)(base + 0x4U))) &= ~0x100U; } __edis(); } //***************************************************************************** // //! \brief Gets frame type received in the last successful frame //! //! \param[in] base is the FSI Rx module base address //! //! \return value of Frame type received on last successful frame // //***************************************************************************** static inline FSI_FrameType FSI_getRxFrameType(uint32_t base) { // // Check the arguments. // ; return((FSI_FrameType)((*((volatile uint16_t *)(base + 0x6U))) & 0xFU)); } //***************************************************************************** // //! \brief Enables to generate DMA event on completion of a successful //! frame reception //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_enableRxDMAEvent(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x8U))) |= 0x1U; __edis(); } //***************************************************************************** // //! \brief Disables the DMA event generation on completion of a successful //! frame reception //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxDMAEvent(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x8U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! \brief Returns Frame tag received for the last successful frame //! //! \param[in] base is the FSI Rx module base address //! //! \return frame tag value. // //***************************************************************************** static inline uint16_t FSI_getRxFrameTag(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0x7U))) & 0x1EU) >> 1U); } //***************************************************************************** // //! \brief Returns User-Data(8-bit) field for received data frame. //! //! \param[in] base is the FSI Rx module base address //! //! \return user data field value. // //***************************************************************************** static inline uint16_t FSI_getRxUserDefinedData(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0x7U))) & 0xFF00U) >> 8U); } //***************************************************************************** // //! \brief Returns current status of all the evetn/error flags //! //! \param[in] base is the FSI Rx module base address //! //! \return the status of error flags,each bit of integer is associated //! with one error flag. //! //! Example Usage - function will set the bits corresponding to respective //! error flag in return value //! evtFlags = FSI_getRxEventStatus(FSI_base) //! if value of evtFlags is 1036(0100000001100) means //! FSI_RX_EVT_FRAME_OVERRUN,FSI_RX_EVT_TYPE_ERR and //! FSI_RX_EVT_CRC_ERR flags are set // //***************************************************************************** static inline uint16_t FSI_getRxEventStatus(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0xAU))) & (0x0FFFU)); } //***************************************************************************** // //! \brief Enables user to set RX event/error flags //! //! \param[in] base is the FSI Rx module base address //! \param[in] evtFlags contains list of error flags to be set //! //! \return None. //! //! Example Usage //! evtFlags = FSI_RX_EVT_EOF_ERR && FSI_RX_EVT_TYPE_ERR //! FSI_forceRxEvents(FSI_base,evtFlags) //! Above call sets error flag to FSI_RX_ERR_EOF_ERR and //! FSI_RX_ERR_TYPE_ERR events // //***************************************************************************** static inline void FSI_forceRxEvents(uint32_t base, uint16_t evtFlags) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0xDU))) = (evtFlags & (0x0FFFU)); __edis(); } //***************************************************************************** // //! \brief Enables user to clear RX event/error flags //! //! \param[in] base is the FSI Rx module base address //! \param[in] evtFlags contains list of error flags to be cleared //! //! \return None. // //***************************************************************************** static inline void FSI_clearRxEvents(uint32_t base, uint16_t evtFlags) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0xCU))) = (evtFlags & (0x0FFFU)); __edis(); } //***************************************************************************** // //! \brief Returns CRC value received in data frame/frame //! //! \param[in] base is the FSI Rx module base address //! //! \return CRC value received in data frame // //***************************************************************************** static inline uint16_t FSI_getRxReceivedCRC(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0xBU))) & 0xFFU); } //***************************************************************************** // //! \brief Computes and returns CRC value for data received //! //! \param[in] base is the FSI Rx module base address //! //! \return CRC value computed on received data // //***************************************************************************** static inline uint16_t FSI_getRxComputedCRC(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0xBU))) & 0xFF00U) >> 8U); } //***************************************************************************** // //! \brief Sets the value for receive buffer pointer at desired location //! //! \param[in] base is the FSI Rx module base address //! \param[in] bufPtrOff 4 bit offset pointer in Rx buffer from where received //! data will be read //! //! \return None. // //***************************************************************************** static inline void FSI_setRxBufferPtr(uint32_t base, uint16_t bufPtrOff) { // // Check the arguments. // ; ; __eallow(); (*((volatile uint16_t *)(base + 0xEU))) = bufPtrOff; __edis(); } //***************************************************************************** // //! \brief Returns current buffer pointer location //! //! \param[in] base is the FSI Rx module base address //! //! \return current buffer pointer location //! //! \note there could be lag due to synchronization, hence value is accurate //! only when no current reception is happening // //***************************************************************************** static inline uint16_t FSI_getRxBufferPtr(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0xFU))) & 0xFU); } //***************************************************************************** // //! \brief Returns valid number of data words present in buffer which have //! not been read out yet //! //! \param[in] base is the FSI Rx module base address //! //! \return number of data words present in buffer which have not been read //! out yet //! //! \note there could be lag due to synchronization, hence value is accurate //! only when no current reception is happening // //***************************************************************************** static inline uint16_t FSI_getRxWordCount(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0xFU))) & 0x1F00U) >> 8U); } //***************************************************************************** // //! \brief Enables the frame watchdog counter logic to count every time it //! start to receive a frame //! //! \param[in] base is the FSI Rx module base address //! \param[in] wdRef reference value for ping watchdog time-out counter //! //! \return None. // //***************************************************************************** static inline void FSI_enableRxFrameWatchdog(uint32_t base,uint32_t wdRef) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(base + 0x12U))) = wdRef; (*((volatile uint16_t *)(base + 0x10U))) |= 0x2U; __edis(); } //***************************************************************************** // //! \brief Disables the frame watchdog counter logic //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxFrameWatchdog(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x10U))) &= ~0x2U; __edis(); } //***************************************************************************** // //! \brief Returns current value of frame watchdog counter //! //! \param[in] base is the FSI Rx module base address //! //! \return current value of frame watchdog counter // //***************************************************************************** static inline uint32_t FSI_getRxFrameWatchdogCounter(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint32_t *)(base + 0x14U)))); } //***************************************************************************** // //! \brief Enables the ping watchdog counter logic and once the set time //! elapses it will indicate ping watchdog time-out has occurred //! //! \param[in] base is the FSI Rx module base address //! \param[in] wdRef reference value for ping watchdog time-out counter //! //! \return None. // //***************************************************************************** static inline void FSI_enableRxPingWatchdog(uint32_t base, uint32_t wdRef) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(base + 0x18U))) = wdRef; (*((volatile uint16_t *)(base + 0x16U))) |= 0x2U; __edis(); } //***************************************************************************** // //! \brief Enables the ping watchdog counter logic and once the set time //! elapses it will indicate ping watchdog time-out has occurred //! //! \param[in] base is the FSI Rx module base address //! \param[in] wdRef reference value for ping watchdog time-out counter //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxPingWatchdog(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x16U))) &= ~0x2U; __edis(); } //***************************************************************************** // //! \brief Returns current value of ping watchdog counter //! //! \param[in] base is the FSI Rx module base address //! //! \return current value(32 bit) of ping watchdog counter // //***************************************************************************** static inline uint32_t FSI_getRxPingWatchdogCounter(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint32_t *)(base + 0x1AU)))); } //***************************************************************************** // //! \brief Returns the value of tag received for last ping frame //! //! \param[in] base is the FSI Rx module base address //! //! \return the tagValue received for last ping frame // //***************************************************************************** static inline uint16_t FSI_getRxPingTag(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0x17U))) & 0x1EU) >> 1U); } //***************************************************************************** // //! \brief Locks the control of all receive control registers, //! once locked further writes will not take effect until system //! reset occurs //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** static inline void FSI_lockRxCtrl(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x1EU))) = ((uint16_t)0x1U | ((0x00A5U) << 8U)); __edis(); } //***************************************************************************** // //! \brief Sets Rx ECC data on which ECC (SEC-DED) computaion logic runs //! //! \param[in] base is the FSI Rx module base address //! \param[in] rxECCdata Data for ECC logic //! //! \return None. // //***************************************************************************** static inline void FSI_setRxECCData(uint32_t base, uint32_t rxECCdata) { // // Check the arguments. // ; (*((volatile uint32_t *)(base + 0x20U))) = rxECCdata; } //***************************************************************************** // //! \brief Sets received ECC value on which ECC (SEC-DED) computaion logic runs //! //! \param[in] base is the FSI Rx module base address //! \param[in] rxECCvalue Received ECC value in a data frame //! //! \return None. // //***************************************************************************** static inline void FSI_setRxReceivedECCValue(uint32_t base, uint16_t rxECCvalue) { // // Check the arguments. // ; // // ECC value can be passed as 8 bit value in USERDATA field in a frame // ; (*((volatile uint16_t *)(base + 0x22U))) = rxECCvalue; } //***************************************************************************** // //! \brief Returns ECC Corrected data //! //! \param[in] base is the FSI Rx module base address //! //! \return 32 bit ECC corrected data // //***************************************************************************** static inline uint32_t FSI_getRxECCCorrectedData(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint32_t *)(base + 0x24U)))); } //***************************************************************************** // //! \brief Returns ECC Log details //! //! \param[in] base is the FSI Rx module base address //! //! \return ECC Log value(8 bit) // //***************************************************************************** static inline uint16_t FSI_getRxECCLog(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0x26U))) & (0x1U | 0x2U)); } //***************************************************************************** // //! \brief Let user generate interrupt on occurrence of Rx events //! //! \param[in] base is the FSI Rx module base address //! \param[in] intNum the type of interrupt to be generated interrupt1 //! or interrupt2 //! \param[in] intFlags contains list of events on which interrupt //! should be generated. Each bit will represent one event,bits for //! the events on which user want to generate interrupt will be set //! others remain clear //! //! \return None. //! //! Example Usage //! evtFlags = FSI_RX_EVT_PING_WD_TIMEOUT & FSI_RX_INT_TYPE_ERR //! FSI_enableRxInterrupt(FSI_base,FSI_INT1,evtFlags) //! Above call will generate interrupt1 on events //! FSI_RX_INT_PING_WD_TIMEOUT and FSI_RX_INT_TYPE_ERR // //***************************************************************************** static inline void FSI_enableRxInterrupt(uint32_t base, FSI_InterruptNum intNum, uint16_t intFlags) { // // Check the arguments. // ; __eallow(); if(intNum == FSI_INT1) { (*((volatile uint16_t *)(base + 0x1CU))) |= (intFlags & (0x0FFFU)); } else { (*((volatile uint16_t *)(base + 0x1DU))) |= (intFlags & (0x0FFFU)); } __edis(); } //***************************************************************************** // //! \brief Let user disable interrupt generation on Rx events //! //! \param[in] base is the FSI Rx module base address //! \param[in] intNum the type of interrupt to be generated interrupt1 //! or interrupt2 //! \param[in] intFlags contains list of events on which interrupt //! generation has to be disabled. //! //! \return None. // //***************************************************************************** static inline void FSI_disableRxInterrupt(uint32_t base, FSI_InterruptNum intNum, uint16_t intFlags) { // // Check the arguments. // ; __eallow(); if(intNum == FSI_INT1) { (*((volatile uint16_t *)(base + 0x1CU))) &= ~(intFlags & (0x0FFFU)); } else { (*((volatile uint16_t *)(base + 0x1DU))) &= ~(intFlags & (0x0FFFU)); } __edis(); } //***************************************************************************** // //! \brief Returns address of Rx data buffer //! //! \details Data buffer is consisting of 16 words from offset- 0x40 to 0x4e //! //! \param[in] base is the FSI Rx module base address //! //! \return Rx data buffer address // //***************************************************************************** static inline uint32_t FSI_getRxBufferAddress(uint32_t base) { // // Check the arguments. // ; return(base + 0x40U); } //***************************************************************************** // //! \brief Resets frame watchdog,ping watchdog or entire RX module //! //! \param[in] base is the FSI Rx module base address //! \param[in] moduleName the name of module which is supposed to be reset //! //! \return None. // //***************************************************************************** extern void FSI_resetRxModule(uint32_t base, FSI_RxSubmoduleInReset submodule); //***************************************************************************** // //! \brief Clears resets on frame watchdog,ping watchdog or entire RX module //! //! \param[in] base is the FSI Rx module base address //! \param[in] moduleName module which is to be brought out of reset //! //! \return None. // //***************************************************************************** extern void FSI_clearRxModuleReset(uint32_t base, FSI_RxSubmoduleInReset submodule); //***************************************************************************** // //! \brief Reads data from FSI Rx buffer //! //! \param[in] base is the FSI Rx module base address //! \param[out] array is the address of the array of words to be transmitted. //! \param[in] length is the number of words in the array to be transmitted. //! \param[in] bufOffset is the offset in Tx buffer where data will be read //! //! \note This function ensures that not more than 16 words are written and //! also wrap around case is taken care when more words need to be read //! if last read happens at maximum offset in Tx buffer //! //! \return None. // //***************************************************************************** extern void FSI_readRxBuffer(uint32_t base, uint16_t array[], uint16_t length, uint16_t bufOffset); //***************************************************************************** // //! \brief Adds delay for selected tap line //! //! \param[in] base is the FSI Rx module base address //! \param[in] delayTapType the line for which delay needs to be added //! it can be either RXCLK,RXD0 or RXD1 //! \param[in] tapValue 5 bit value of the amount of delay to be added //! //! \return None. // //***************************************************************************** extern void FSI_configRxDelayLine(uint32_t base, FSI_RxDelayTapType delayTapType, uint16_t tapValue); //***************************************************************************** // //! \brief Initializes FSI Tx module //! //! \details Software based initialization of the FSI transmitter IP. This is //! typically needed only once during initialization or if the module //! needs to be reset due to an underrun condition that occurred during //! operation. //! //! \param[in] base is the FSI Tx module base address //! \param[in] prescalar is the user configurable clock divider for PLL input //! clock //! //! \return None. // //***************************************************************************** extern void FSI_performTxInitialization(uint32_t base, uint16_t prescalar); //***************************************************************************** // //! \brief Initializes FSI Rx module //! //! \details Software based initialization of the FSI receiver module.This is //! typically needed only once during initialization. However, if there //! are framing errors in the received frames, then the receive module //! needs to be reset so that subsequent frames/packets can be handled //! fresh. //! //! \param[in] base is the FSI Rx module base address //! //! \return None. // //***************************************************************************** extern void FSI_performRxInitialization(uint32_t base); //***************************************************************************** // //! \brief Sends Flush pattern sequence //! //! \details Flush pattern sequence sent by a FSI transmit module will bring the //! FSI receive module out of reset so that it will then be ready to //! receive subsequent frames. //! //! \param[in] base is the FSI Tx module base address //! \param[in] prescalar is the user configurable clock divider for PLL input //! clock //! //! \return None. // //***************************************************************************** extern void FSI_executeTxFlushSequence(uint32_t base, uint16_t prescalar); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: gpio.h // // TITLE: C28x GPIO driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup gpio_api GPIO //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_gpio.h // // TITLE: Definitions for the GPIO registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the GPIO register offsets // //***************************************************************************** // Period (GPIO0 to GPIO31) // (GPIO0 to GPIO15) // (GPIO16 to GPIO31) // to GPIO15) // to GPIO31) // GPIO31) // to GPIO31) // to GPIO31) // (GPIO0 to GPIO31) // (GPIO0 to GPIO31) // (GPIO0 to GPIO15) // (GPIO16 to GPIO31) // (GPIO0 to GPIO7) // (GPIO8 to GPIO15) // (GPIO16 to GPIO23) // (GPIO24 to GPIO31) // to GPIO31) // (GPIO0 to GPIO31) // Period (GPIO32 to GPIO63) // (GPIO32 to GPIO47) // (GPIO48 to GPIO63) // to GPIO47) // to GPIO63) // GPIO63) // (GPIO32 to GPIO63) // (GPIO32 to GPIO63) // (GPIO32 to GPIO63) // (GPIO32 to GPIO47) // (GPIO48 to GPIO63) // (GPIO32 to GPIO39) // (GPIO40 to GPIO47) // (GPIO48 to GPIO55) // (GPIO56 to GPIO63) // to GPIO63) // (GPIO32 to GPIO63) // Period (GPIO224 to GPIO255) // (GPIO224 to GPIO239) // (GPIO240 to GPIO255) // (GPIO224 to GPIO255) // (GPIO224 to GPIO255) // to GPIO255) // (GPIO224 to GPIO255) // to GPIO31) // GPIO31) // GPIO31) // to GPIO31) // to GPIO64) // GPIO64) // to GPIO64) // to GPIO64) // to GPIO255) //***************************************************************************** // // The following are defines for the bit fields in the GPACTRL register // //***************************************************************************** // for GPIO0 to GPIO7 // for GPIO8 to GPIO15 // for GPIO16 to GPIO23 // for GPIO24 to GPIO31 //***************************************************************************** // // The following are defines for the bit fields in the GPAQSEL1 register // //***************************************************************************** // type for GPIO0 // type for GPIO1 // type for GPIO2 // type for GPIO3 // type for GPIO4 // type for GPIO5 // type for GPIO6 // type for GPIO7 // type for GPIO8 // type for GPIO9 // type for GPIO10 // type for GPIO11 // type for GPIO12 // type for GPIO13 // type for GPIO14 // type for GPIO15 //***************************************************************************** // // The following are defines for the bit fields in the GPAQSEL2 register // //***************************************************************************** // type for GPIO16 // type for GPIO17 // type for GPIO18 // type for GPIO19 // type for GPIO20 // type for GPIO21 // type for GPIO22 // type for GPIO23 // type for GPIO24 // type for GPIO25 // type for GPIO26 // type for GPIO27 // type for GPIO28 // type for GPIO29 // type for GPIO30 // type for GPIO31 //***************************************************************************** // // The following are defines for the bit fields in the GPAMUX1 register // //***************************************************************************** // for GPIO0 // for GPIO1 // for GPIO2 // for GPIO3 // for GPIO4 // for GPIO5 // for GPIO6 // for GPIO7 // for GPIO8 // for GPIO9 // for GPIO10 // for GPIO11 // for GPIO12 // for GPIO13 // for GPIO14 // for GPIO15 //***************************************************************************** // // The following are defines for the bit fields in the GPAMUX2 register // //***************************************************************************** // for GPIO16 // for GPIO17 // for GPIO18 // for GPIO19 // for GPIO20 // for GPIO21 // for GPIO22 // for GPIO23 // for GPIO24 // for GPIO25 // for GPIO26 // for GPIO27 // for GPIO28 // for GPIO29 // for GPIO30 // for GPIO31 //***************************************************************************** // // The following are defines for the bit fields in the GPADIR register // //***************************************************************************** // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode //***************************************************************************** // // The following are defines for the bit fields in the GPAPUD register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPAINV register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPAODR register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPAAMSEL register // //***************************************************************************** // pin // pin //***************************************************************************** // // The following are defines for the bit fields in the GPAGMUX1 register // //***************************************************************************** // for GPIO0 // for GPIO1 // for GPIO2 // for GPIO3 // for GPIO4 // for GPIO5 // for GPIO6 // for GPIO7 // for GPIO8 // for GPIO9 // for GPIO10 // for GPIO11 // for GPIO12 // for GPIO13 // for GPIO14 // for GPIO15 //***************************************************************************** // // The following are defines for the bit fields in the GPAGMUX2 register // //***************************************************************************** // for GPIO16 // for GPIO17 // for GPIO18 // for GPIO19 // for GPIO20 // for GPIO21 // for GPIO22 // for GPIO23 // for GPIO24 // for GPIO25 // for GPIO26 // for GPIO27 // for GPIO28 // for GPIO29 // for GPIO30 // for GPIO31 //***************************************************************************** // // The following are defines for the bit fields in the GPACSEL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPACSEL2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPACSEL3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPACSEL4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPALOCK register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPACR register // //***************************************************************************** // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin //***************************************************************************** // // The following are defines for the bit fields in the GPBCTRL register // //***************************************************************************** // for GPIO32 to GPIO39 // for GPIO40 to GPIO47 // for GPIO48 to GPIO55 // for GPIO56 to GPIO63 //***************************************************************************** // // The following are defines for the bit fields in the GPBQSEL1 register // //***************************************************************************** // type for GPIO32 // type for GPIO33 // type for GPIO34 // type for GPIO35 // type for GPIO37 // type for GPIO39 // type for GPIO40 // type for GPIO41 // type for GPIO42 // type for GPIO43 // type for GPIO44 // type for GPIO45 // type for GPIO46 // type for GPIO47 //***************************************************************************** // // The following are defines for the bit fields in the GPBQSEL2 register // //***************************************************************************** // type for GPIO48 // type for GPIO49 // type for GPIO50 // type for GPIO51 // type for GPIO52 // type for GPIO53 // type for GPIO54 // type for GPIO55 // type for GPIO56 // type for GPIO57 // type for GPIO58 // type for GPIO59 //***************************************************************************** // // The following are defines for the bit fields in the GPBMUX1 register // //***************************************************************************** // for GPIO32 // for GPIO33 // for GPIO34 // for GPIO35 // for GPIO37 // for GPIO39 // for GPIO40 // for GPIO41 // for GPIO42 // for GPIO43 // for GPIO44 // for GPIO45 // for GPIO46 // for GPIO47 //***************************************************************************** // // The following are defines for the bit fields in the GPBMUX2 register // //***************************************************************************** // for GPIO48 // for GPIO49 // for GPIO50 // for GPIO51 // for GPIO52 // for GPIO53 // for GPIO54 // for GPIO55 // for GPIO56 // for GPIO57 // for GPIO58 // for GPIO59 //***************************************************************************** // // The following are defines for the bit fields in the GPBDIR register // //***************************************************************************** // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode // pin in GPIO mode //***************************************************************************** // // The following are defines for the bit fields in the GPBPUD register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPBINV register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPBODR register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPBGMUX1 register // //***************************************************************************** // for GPIO32 // for GPIO33 // for GPIO34 // for GPIO35 // for GPIO37 // for GPIO39 // for GPIO40 // for GPIO41 // for GPIO42 // for GPIO43 // for GPIO44 // for GPIO45 // for GPIO46 // for GPIO47 //***************************************************************************** // // The following are defines for the bit fields in the GPBGMUX2 register // //***************************************************************************** // for GPIO48 // for GPIO49 // for GPIO50 // for GPIO51 // for GPIO52 // for GPIO53 // for GPIO54 // for GPIO55 // for GPIO56 // for GPIO57 // for GPIO58 // for GPIO59 //***************************************************************************** // // The following are defines for the bit fields in the GPBCSEL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBCSEL2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBCSEL3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBCSEL4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBLOCK register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPBCR register // //***************************************************************************** // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin //***************************************************************************** // // The following are defines for the bit fields in the GPHCTRL register // //***************************************************************************** // for GPIO224 to GPIO231 // for GPIO232 to GPIO239 // for GPIO240 to GPIO247 //***************************************************************************** // // The following are defines for the bit fields in the GPHQSEL1 register // //***************************************************************************** // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin //***************************************************************************** // // The following are defines for the bit fields in the GPHQSEL2 register // //***************************************************************************** // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin // type for this GPIO Pin //***************************************************************************** // // The following are defines for the bit fields in the GPHINV register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPHAMSEL register // //***************************************************************************** // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin //***************************************************************************** // // The following are defines for the bit fields in the GPHLOCK register // //***************************************************************************** // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin // this pin //***************************************************************************** // // The following are defines for the bit fields in the GPHCR register // //***************************************************************************** // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin // for this pin //***************************************************************************** // // The following are defines for the bit fields in the GPADAT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPASET register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPACLEAR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPATOGGLE register // //***************************************************************************** // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin //***************************************************************************** // // The following are defines for the bit fields in the GPBDAT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBSET register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBCLEAR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPBTOGGLE register // //***************************************************************************** // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin // pin //***************************************************************************** // // The following are defines for the bit fields in the GPHDAT register // //***************************************************************************** //########################################################################### // // FILE: hw_xint.h // // TITLE: Definitions for the XINT registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the XINT register offsets // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XINT1CR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XINT2CR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XINT3CR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XINT4CR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XINT5CR register // //***************************************************************************** //########################################################################### // // FILE: xbar.h // // TITLE: C28x X-BAR driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup xbar_api XBAR //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_epwmxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the XBAR register offsets // //***************************************************************************** // for TRIP4 // for TRIP4 // for TRIP5 // for TRIP5 // for TRIP7 // for TRIP7 // for TRIP8 // for TRIP8 // for TRIP9 // for TRIP9 // for TRIP10 // for TRIP10 // for TRIP11 // for TRIP11 // for TRIP12 // for TRIP12 // TRIP4 // TRIP5 // TRIP7 // TRIP8 // TRIP9 // TRIP10 // TRIP11 // TRIP12 // Register // register //***************************************************************************** // // The following are defines for the bit fields in the TRIP4MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP4MUX16TO31CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP5MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP5MUX16TO31CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP7MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP7MUX16TO31CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP8MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP8MUX16TO31CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP9MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP9MUX16TO31CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP10MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP10MUX16TO31CFG register // //***************************************************************************** // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR // TRIP10 of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP11MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP11MUX16TO31CFG register // //***************************************************************************** // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR // TRIP11 of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP12MUX0TO15CFG register // //***************************************************************************** // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP12MUX16TO31CFG register // //***************************************************************************** // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR // TRIP12 of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP4MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP5MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP7MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP8MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP9MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP10MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP11MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIP12MUXENABLE register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIPOUTINV register // //***************************************************************************** // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR // of EPWM-XBAR //***************************************************************************** // // The following are defines for the bit fields in the TRIPLOCK register // //***************************************************************************** // EPWM-XBAR //########################################################################### // // FILE: hw_inputxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the XBAR register offsets // //***************************************************************************** // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) // (GPIO0 to x) //***************************************************************************** // // The following are defines for the bit fields in the INPUTSELECTLOCK register // //***************************************************************************** // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register //########################################################################### // // FILE: hw_outputxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the XBAR register offsets // //***************************************************************************** // Configuration for Output 1 // Configuration for Output 1 // Configuration for Output 2 // Configuration for Output 2 // Configuration for Output 3 // Configuration for Output 3 // Configuration for Output 4 // Configuration for Output 4 // Configuration for Output 5 // Configuration for Output 5 // Configuration for Output 6 // Configuration for Output 6 // Configuration for Output 7 // Configuration for Output 7 // Configuration for Output 8 // Configuration for Output 8 // Output 1 // Output 2 // Output 3 // Output 4 // Output 5 // Output 6 // Output 7 // Output 8 // Clear // Clear // Enable // Lock register //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register // //***************************************************************************** // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register // //***************************************************************************** // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR // OUTPUT1 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register // //***************************************************************************** // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register // //***************************************************************************** // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register // //***************************************************************************** // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register // //***************************************************************************** // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register // //***************************************************************************** // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register // //***************************************************************************** // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register // //***************************************************************************** // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register // //***************************************************************************** // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register // //***************************************************************************** // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register // //***************************************************************************** // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register // //***************************************************************************** // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register // //***************************************************************************** // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register // //***************************************************************************** // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register // //***************************************************************************** // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT1MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT2MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT3MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT4MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT5MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT6MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT7MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUT8MUXENABLE register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUTLATCH register // //***************************************************************************** // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR // OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUTLATCHCLR register // //***************************************************************************** // OUTPUT1 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUTLATCHFRC register // //***************************************************************************** // OUTPUT1 of OUTPUT-XBAR // OUTPUT2 of OUTPUT-XBAR // OUTPUT3 of OUTPUT-XBAR // OUTPUT4 of OUTPUT-XBAR // OUTPUT5 of OUTPUT-XBAR // OUTPUT6 of OUTPUT-XBAR // OUTPUT7 of OUTPUT-XBAR // OUTPUT8 of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUTLATCHENABLE register // //***************************************************************************** // drive OUTPUT1 for OUTPUT-XBAR // drive OUTPUT2 for OUTPUT-XBAR // drive OUTPUT3 for OUTPUT-XBAR // drive OUTPUT4 for OUTPUT-XBAR // drive OUTPUT5 for OUTPUT-XBAR // drive OUTPUT6 for OUTPUT-XBAR // drive OUTPUT7 for OUTPUT-XBAR // drive OUTPUT8 for OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUTINV register // //***************************************************************************** // of OUTPUT-XBAR // of OUTPUT-XBAR // of OUTPUT-XBAR // of OUTPUT-XBAR // of OUTPUT-XBAR // of OUTPUT-XBAR // of OUTPUT-XBAR // of OUTPUT-XBAR //***************************************************************************** // // The following are defines for the bit fields in the OUTPUTLOCK register // //***************************************************************************** // OUTPUT-XBAR //########################################################################### // // FILE: hw_xbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the XBAR register offsets // //***************************************************************************** // Register 1 // Register 2 // Register 3 // Register 4 //***************************************************************************** // // The following are defines for the bit fields in the XBARFLG1 register // //***************************************************************************** // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // CMPSS1.CTRIPOUTL Signal // CMPSS1.CTRIPOUTH Signal // CMPSS2.CTRIPOUTL Signal // CMPSS2.CTRIPOUTH Signal // CMPSS3.CTRIPOUTL Signal // CMPSS3.CTRIPOUTH Signal // CMPSS4.CTRIPOUTL Signal // CMPSS4.CTRIPOUTH Signal // CMPSS5.CTRIPOUTL Signal // CMPSS5.CTRIPOUTH Signal // CMPSS6.CTRIPOUTL Signal // CMPSS6.CTRIPOUTH Signal // CMPSS7.CTRIPOUTL Signal // CMPSS7.CTRIPOUTH Signal // CMPSS8.CTRIPOUTL Signal // CMPSS8.CTRIPOUTH Signal //***************************************************************************** // // The following are defines for the bit fields in the XBARFLG2 register // //***************************************************************************** // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal //***************************************************************************** // // The following are defines for the bit fields in the XBARFLG3 register // //***************************************************************************** // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal //***************************************************************************** // // The following are defines for the bit fields in the XBARFLG4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XBARCLR1 register // //***************************************************************************** // CMPSS1.CTRIPL Signal // CMPSS1.CTRIPH Signal // CMPSS2.CTRIPL Signal // CMPSS2.CTRIPH Signal // CMPSS3.CTRIPL Signal // CMPSS3.CTRIPH Signal // CMPSS4.CTRIPL Signal // CMPSS4.CTRIPH Signal // CMPSS5.CTRIPL Signal // CMPSS5.CTRIPH Signal // CMPSS6.CTRIPL Signal // CMPSS6.CTRIPH Signal // CMPSS7.CTRIPL Signal // CMPSS7.CTRIPH Signal // CMPSS8.CTRIPL Signal // CMPSS8.CTRIPH Signal // CMPSS1.CTRIPOUTL Signal // CMPSS1.CTRIPOUTH Signal // CMPSS2.CTRIPOUTL Signal // CMPSS2.CTRIPOUTH Signal // CMPSS3.CTRIPOUTL Signal // CMPSS3.CTRIPOUTH Signal // CMPSS4.CTRIPOUTL Signal // CMPSS4.CTRIPOUTH Signal // CMPSS5.CTRIPOUTL Signal // CMPSS5.CTRIPOUTH Signal // CMPSS6.CTRIPOUTL Signal // CMPSS6.CTRIPOUTH Signal // CMPSS7.CTRIPOUTL Signal // CMPSS7.CTRIPOUTH Signal // CMPSS8.CTRIPOUTL Signal // CMPSS8.CTRIPOUTH Signal //***************************************************************************** // // The following are defines for the bit fields in the XBARCLR2 register // //***************************************************************************** // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // ECAP1.OUT Signal // ECAP2.OUT Signal // ECAP3.OUT Signal // ECAP4.OUT Signal // ECAP5.OUT Signal // ECAP6.OUT Signal // EXTSYNCOUT Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal // Signal //***************************************************************************** // // The following are defines for the bit fields in the XBARCLR3 register // //***************************************************************************** // Signal // Signal // Signal // SD1FLT1.COMPL Signal // SD1FLT1.COMPH Signal // SD1FLT2.COMPL Signal // SD1FLT2.COMPH Signal // SD1FLT3.COMPL Signal // SD1FLT3.COMPH Signal // SD1FLT4.COMPL Signal // SD1FLT4.COMPH Signal // ECAP7.OUT Signal // SD1FLT1.COMPZ Signal // SD1FLT1.DRINT Signal // SD1FLT2.COMPZ Signal // SD1FLT2.DRINT Signal // SD1FLT3.COMPZ Signal // SD1FLT3.DRINT Signal // SD1FLT4.COMPZ Signal // SD1FLT4.DRINT Signal //***************************************************************************** // // The following are defines for the bit fields in the XBARCLR4 register // //***************************************************************************** // Signal //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** //***************************************************************************** // // The following values define the muxes parameter for XBAR_enableEPWMMux(), // XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and // XBAR_disableOutputMux(). // //***************************************************************************** //***************************************************************************** // //! The following values define the \e output parameter for //! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and //! XBAR_disableOutputMux(). // //***************************************************************************** typedef enum { XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR XBAR_OUTPUT8 = 14 //!< OUTPUT8 of the Output X-BAR } XBAR_OutputNum; //***************************************************************************** // //! The following values define the \e trip parameter for //! XBAR_setEPWMMuxConfig(), XBAR_enableEPWMMux(), and XBAR_disableEPWMMux(). // //***************************************************************************** typedef enum { XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR } XBAR_TripNum; //***************************************************************************** // //! The following values define the \e input parameter for XBAR_setInputPin(). // //***************************************************************************** typedef enum { XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs, eCAPs XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs, eCAPs XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs, eCAPs XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1, eCAPs XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2, eCAPs XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3, eCAPs XBAR_INPUT7, //!< X-BARs, eCAPs XBAR_INPUT8, //!< X-BARs, eCAPs XBAR_INPUT9, //!< X-BARs, eCAPs XBAR_INPUT10, //!< X-BARs, eCAPs XBAR_INPUT11, //!< X-BARs, eCAPs XBAR_INPUT12, //!< X-BARs, eCAPs XBAR_INPUT13, //!< XINT4, X-BARs, eCAPs XBAR_INPUT14, //!< XINT5, X-BARs, eCAPs XBAR_INPUT15, //!< eCAPs XBAR_INPUT16 //!< eCAPs } XBAR_InputNum; //***************************************************************************** // //! The following values define the \e muxConfig parameter for //! XBAR_setOutputMuxConfig(). // //***************************************************************************** typedef enum { XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000, XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001, XBAR_OUT_MUX00_ADCAEVT1 = 0x0002, XBAR_OUT_MUX00_ECAP1_OUT = 0x0003, XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200, XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201, XBAR_OUT_MUX01_ADCCEVT1 = 0x0203, XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400, XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401, XBAR_OUT_MUX02_ADCAEVT2 = 0x0402, XBAR_OUT_MUX02_ECAP2_OUT = 0x0403, XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600, XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601, XBAR_OUT_MUX03_ADCCEVT2 = 0x0603, XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800, XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801, XBAR_OUT_MUX04_ADCAEVT3 = 0x0802, XBAR_OUT_MUX04_ECAP3_OUT = 0x0803, XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00, XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01, XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03, XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00, XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01, XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02, XBAR_OUT_MUX06_ECAP4_OUT = 0x0C03, XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00, XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01, XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03, XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH = 0x1000, XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L = 0x1001, XBAR_OUT_MUX08_ADCBEVT1 = 0x1002, XBAR_OUT_MUX08_ECAP5_OUT = 0x1003, XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL = 0x1200, XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201, XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH = 0x1400, XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L = 0x1401, XBAR_OUT_MUX10_ADCBEVT2 = 0x1402, XBAR_OUT_MUX10_ECAP6_OUT = 0x1403, XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL = 0x1600, XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601, XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH = 0x1800, XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L = 0x1801, XBAR_OUT_MUX12_ADCBEVT3 = 0x1802, XBAR_OUT_MUX12_ECAP7_OUT = 0x1803, XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL = 0x1A00, XBAR_OUT_MUX13_ADCSOCA = 0x1A01, XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02, XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03, XBAR_OUT_MUX15_ADCSOCB = 0x1E01, XBAR_OUT_MUX16_SD1FLT1_COMPH = 0x2000, XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, XBAR_OUT_MUX17_SD1FLT1_COMPL = 0x2200, XBAR_OUT_MUX17_CLAHALT = 0x2203, XBAR_OUT_MUX18_SD1FLT2_COMPH = 0x2400, XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, XBAR_OUT_MUX19_SD1FLT2_COMPL = 0x2600, XBAR_OUT_MUX20_SD1FLT3_COMPH = 0x2800, XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, XBAR_OUT_MUX21_SD1FLT3_COMPL = 0x2A00, XBAR_OUT_MUX22_SD1FLT4_COMPH = 0x2C00, XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, XBAR_OUT_MUX23_SD1FLT4_COMPL = 0x2E00 } XBAR_OutputMuxConfig; //***************************************************************************** // //! The following values define the \e muxConfig parameter for //! XBAR_setEPWMMuxConfig(). // //***************************************************************************** typedef enum { XBAR_EPWM_MUX00_CMPSS1_CTRIPH = 0x0000, XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, XBAR_EPWM_MUX00_ADCAEVT1 = 0x0002, XBAR_EPWM_MUX00_ECAP1_OUT = 0x0003, XBAR_EPWM_MUX01_CMPSS1_CTRIPL = 0x0200, XBAR_EPWM_MUX01_INPUTXBAR1 = 0x0201, XBAR_EPWM_MUX01_ADCCEVT1 = 0x0203, XBAR_EPWM_MUX02_CMPSS2_CTRIPH = 0x0400, XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, XBAR_EPWM_MUX02_ADCAEVT2 = 0x0402, XBAR_EPWM_MUX02_ECAP2_OUT = 0x0403, XBAR_EPWM_MUX03_CMPSS2_CTRIPL = 0x0600, XBAR_EPWM_MUX03_INPUTXBAR2 = 0x0601, XBAR_EPWM_MUX03_ADCCEVT2 = 0x0603, XBAR_EPWM_MUX04_CMPSS3_CTRIPH = 0x0800, XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, XBAR_EPWM_MUX04_ADCAEVT3 = 0x0802, XBAR_EPWM_MUX04_ECAP3_OUT = 0x0803, XBAR_EPWM_MUX05_CMPSS3_CTRIPL = 0x0A00, XBAR_EPWM_MUX05_INPUTXBAR3 = 0x0A01, XBAR_EPWM_MUX05_ADCCEVT3 = 0x0A03, XBAR_EPWM_MUX06_CMPSS4_CTRIPH = 0x0C00, XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, XBAR_EPWM_MUX06_ADCAEVT4 = 0x0C02, XBAR_EPWM_MUX06_ECAP4_OUT = 0x0C03, XBAR_EPWM_MUX07_CMPSS4_CTRIPL = 0x0E00, XBAR_EPWM_MUX07_INPUTXBAR4 = 0x0E01, XBAR_EPWM_MUX07_ADCCEVT4 = 0x0E03, XBAR_EPWM_MUX08_CMPSS5_CTRIPH = 0x1000, XBAR_EPWM_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, XBAR_EPWM_MUX08_ADCBEVT1 = 0x1002, XBAR_EPWM_MUX08_ECAP5_OUT = 0x1003, XBAR_EPWM_MUX09_CMPSS5_CTRIPL = 0x1200, XBAR_EPWM_MUX09_INPUTXBAR5 = 0x1201, XBAR_EPWM_MUX10_CMPSS6_CTRIPH = 0x1400, XBAR_EPWM_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, XBAR_EPWM_MUX10_ADCBEVT2 = 0x1402, XBAR_EPWM_MUX10_ECAP6_OUT = 0x1403, XBAR_EPWM_MUX11_CMPSS6_CTRIPL = 0x1600, XBAR_EPWM_MUX11_INPUTXBAR6 = 0x1601, XBAR_EPWM_MUX12_CMPSS7_CTRIPH = 0x1800, XBAR_EPWM_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, XBAR_EPWM_MUX12_ADCBEVT3 = 0x1802, XBAR_EPWM_MUX12_ECAP7_OUT = 0x1803, XBAR_EPWM_MUX13_CMPSS7_CTRIPL = 0x1A00, XBAR_EPWM_MUX13_ADCSOCA = 0x1A01, XBAR_EPWM_MUX14_ADCBEVT4 = 0x1C02, XBAR_EPWM_MUX14_EXTSYNCOUT = 0x1C03, XBAR_EPWM_MUX15_ADCSOCB = 0x1E01, XBAR_EPWM_MUX16_SD1FLT1_COMPH = 0x2000, XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, XBAR_EPWM_MUX17_SD1FLT1_COMPL = 0x2200, XBAR_EPWM_MUX17_INPUTXBAR7 = 0x2201, XBAR_EPWM_MUX17_CLAHALT = 0x2203, XBAR_EPWM_MUX18_SD1FLT2_COMPH = 0x2400, XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, XBAR_EPWM_MUX19_SD1FLT2_COMPL = 0x2600, XBAR_EPWM_MUX19_INPUTXBAR8 = 0x2601, XBAR_EPWM_MUX20_SD1FLT3_COMPH = 0x2800, XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, XBAR_EPWM_MUX21_SD1FLT3_COMPL = 0x2A00, XBAR_EPWM_MUX21_INPUTXBAR9 = 0x2A01, XBAR_EPWM_MUX22_SD1FLT4_COMPH = 0x2C00, XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, XBAR_EPWM_MUX23_SD1FLT4_COMPL = 0x2E00, XBAR_EPWM_MUX23_INPUTXBAR10 = 0x2E01, XBAR_EPWM_MUX25_INPUTXBAR11 = 0x3201, XBAR_EPWM_MUX27_INPUTXBAR12 = 0x3601, XBAR_EPWM_MUX29_INPUTXBAR13 = 0x3A01, XBAR_EPWM_MUX31_INPUTXBAR14 = 0x3E01 } XBAR_EPWMMuxConfig; //***************************************************************************** // //! The following values define the \e inputFlag parameter for //! XBAR_getInputFlagStatus() and XBAR_clearInputFlag(). // //***************************************************************************** typedef enum { // XBARFLG1 XBAR_INPUT_FLG_CMPSS1_CTRIPL = 0x0000, XBAR_INPUT_FLG_CMPSS1_CTRIPH = 0x0001, XBAR_INPUT_FLG_CMPSS2_CTRIPL = 0x0002, XBAR_INPUT_FLG_CMPSS2_CTRIPH = 0x0003, XBAR_INPUT_FLG_CMPSS3_CTRIPL = 0x0004, XBAR_INPUT_FLG_CMPSS3_CTRIPH = 0x0005, XBAR_INPUT_FLG_CMPSS4_CTRIPL = 0x0006, XBAR_INPUT_FLG_CMPSS4_CTRIPH = 0x0007, XBAR_INPUT_FLG_CMPSS5_CTRIPL = 0x0008, XBAR_INPUT_FLG_CMPSS5_CTRIPH = 0x0009, XBAR_INPUT_FLG_CMPSS6_CTRIPL = 0x000A, XBAR_INPUT_FLG_CMPSS6_CTRIPH = 0x000B, XBAR_INPUT_FLG_CMPSS7_CTRIPL = 0x000C, XBAR_INPUT_FLG_CMPSS7_CTRIPH = 0x000D, XBAR_INPUT_FLG_CMPSS8_CTRIPL = 0x000E, XBAR_INPUT_FLG_CMPSS8_CTRIPH = 0x000F, XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010, XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011, XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012, XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013, XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014, XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015, XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016, XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017, XBAR_INPUT_FLG_CMPSS5_CTRIPOUTL = 0x0018, XBAR_INPUT_FLG_CMPSS5_CTRIPOUTH = 0x0019, XBAR_INPUT_FLG_CMPSS6_CTRIPOUTL = 0x001A, XBAR_INPUT_FLG_CMPSS6_CTRIPOUTH = 0x001B, XBAR_INPUT_FLG_CMPSS7_CTRIPOUTL = 0x001C, XBAR_INPUT_FLG_CMPSS7_CTRIPOUTH = 0x001D, XBAR_INPUT_FLG_CMPSS8_CTRIPOUTL = 0x001E, XBAR_INPUT_FLG_CMPSS8_CTRIPOUTH = 0x001F, // XBARFLG2 XBAR_INPUT_FLG_INPUT1 = 0x0100, XBAR_INPUT_FLG_INPUT2 = 0x0101, XBAR_INPUT_FLG_INPUT3 = 0x0102, XBAR_INPUT_FLG_INPUT4 = 0x0103, XBAR_INPUT_FLG_INPUT5 = 0x0104, XBAR_INPUT_FLG_INPUT6 = 0x0105, XBAR_INPUT_FLG_ADCSOCA = 0x0106, XBAR_INPUT_FLG_ADCSOCB = 0x0107, XBAR_INPUT_FLG_INPUT7 = 0x0108, XBAR_INPUT_FLG_INPUT8 = 0x0109, XBAR_INPUT_FLG_INPUT9 = 0x010A, XBAR_INPUT_FLG_INPUT10 = 0x010B, XBAR_INPUT_FLG_INPUT11 = 0x010C, XBAR_INPUT_FLG_INPUT12 = 0x010D, XBAR_INPUT_FLG_INPUT13 = 0x010E, XBAR_INPUT_FLG_INPUT14 = 0x010F, XBAR_INPUT_FLG_ECAP1_OUT = 0x0110, XBAR_INPUT_FLG_ECAP2_OUT = 0x0111, XBAR_INPUT_FLG_ECAP3_OUT = 0x0112, XBAR_INPUT_FLG_ECAP4_OUT = 0x0113, XBAR_INPUT_FLG_ECAP5_OUT = 0x0114, XBAR_INPUT_FLG_ECAP6_OUT = 0x0115, XBAR_INPUT_FLG_EXTSYNCOUT = 0x0116, XBAR_INPUT_FLG_ADCAEVT1 = 0x0117, XBAR_INPUT_FLG_ADCAEVT2 = 0x0118, XBAR_INPUT_FLG_ADCAEVT3 = 0x0119, XBAR_INPUT_FLG_ADCAEVT4 = 0x011A, XBAR_INPUT_FLG_ADCBEVT1 = 0x011B, XBAR_INPUT_FLG_ADCBEVT2 = 0x011C, XBAR_INPUT_FLG_ADCBEVT3 = 0x011D, XBAR_INPUT_FLG_ADCBEVT4 = 0x011E, XBAR_INPUT_FLG_ADCCEVT1 = 0x011F, // XBARFLG3 XBAR_INPUT_FLG_ADCCEVT2 = 0x0200, XBAR_INPUT_FLG_ADCCEVT3 = 0x0201, XBAR_INPUT_FLG_ADCCEVT4 = 0x0202, XBAR_INPUT_FLG_ADCDEVT1 = 0x0203, XBAR_INPUT_FLG_ADCDEVT2 = 0x0204, XBAR_INPUT_FLG_ADCDEVT3 = 0x0205, XBAR_INPUT_FLG_ADCDEVT4 = 0x0206, XBAR_INPUT_FLG_SD1FLT1_COMPL = 0x0207, XBAR_INPUT_FLG_SD1FLT1_COMPH = 0x0208, XBAR_INPUT_FLG_SD1FLT2_COMPL = 0x0209, XBAR_INPUT_FLG_SD1FLT2_COMPH = 0x020A, XBAR_INPUT_FLG_SD1FLT3_COMPL = 0x020B, XBAR_INPUT_FLG_SD1FLT3_COMPH = 0x020C, XBAR_INPUT_FLG_SD1FLT4_COMPL = 0x020D, XBAR_INPUT_FLG_SD1FLT4_COMPH = 0x020E, XBAR_INPUT_FLG_ECAP7_OUT = 0x0217, XBAR_INPUT_FLG_SD1FLT1_COMPZ = 0x0218, XBAR_INPUT_FLG_SD1FLT1_DRINT = 0x0219, XBAR_INPUT_FLG_SD1FLT2_COMPZ = 0x021A, XBAR_INPUT_FLG_SD1FLT2_DRINT = 0x021B, XBAR_INPUT_FLG_SD1FLT3_COMPZ = 0x021C, XBAR_INPUT_FLG_SD1FLT3_DRINT = 0x021D, XBAR_INPUT_FLG_SD1FLT4_COMPZ = 0x021E, XBAR_INPUT_FLG_SD1FLT4_DRINT = 0x021F, // XBARFLG4 XBAR_INPUT_FLG_CLAHALT = 0x031F } XBAR_InputFlag; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Enables the Output X-BAR mux values to be passed to the output signal. //! //! \param output is the X-BAR output being configured. //! \param muxes is a bit field of the muxes to be enabled. //! //! This function enables the mux values to be passed to the X-BAR output //! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is //! the output number between 1 and 8 inclusive. //! //! The \e muxes parameter is a bit field of the muxes being enabled where bit //! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided //! in the form of \b XBAR_MUXnn that can be OR'd together to enable several //! muxes on an output at the same time. For example, passing this function //! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10. //! //! \return None. // //***************************************************************************** static inline void XBAR_enableOutputMux(XBAR_OutputNum output, uint32_t muxes) { // // Set the enable bit. // __eallow(); (*((volatile uint32_t *)((0x00007A80U + 0x20U) + (uint16_t)output))) |= muxes; __edis(); } //***************************************************************************** // //! Disables the Output X-BAR mux values from being passed to the output. //! //! \param output is the X-BAR output being configured. //! \param muxes is a bit field of the muxes to be disabled. //! //! This function disables the mux values from being passed to the X-BAR output //! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is //! the output number between 1 and 8 inclusive. //! //! The \e muxes parameter is a bit field of the muxes being disabled where bit //! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided //! in the form of \b XBAR_MUXnn that can be OR'd together to disable several //! muxes on an output at the same time. For example, passing this function //! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10. //! //! \return None. // //***************************************************************************** static inline void XBAR_disableOutputMux(XBAR_OutputNum output, uint32_t muxes) { // // Clear the enable bit. // __eallow(); (*((volatile uint32_t *)((0x00007A80U + 0x20U) + (uint16_t)output))) &= ~(muxes); __edis(); } //***************************************************************************** // //! Enables or disables the output latch to drive the selected output. //! //! \param output is the X-BAR output being configured. //! \param enable is a flag that determines whether or not the latch is //! selected to drive the X-BAR output. //! //! This function sets the Output X-BAR output signal latch mode. If the //! \e enable parameter is \b true, the output specified by \e output will be //! driven by the output latch. //! //! \return None. // //***************************************************************************** static inline void XBAR_setOutputLatchMode(XBAR_OutputNum output, _Bool enable) { __eallow(); // // Set or clear the latch setting bit based on the enable parameter. // if(enable) { (*((volatile uint16_t *)(0x00007A80U + 0x36U))) |= 0x1U << ((uint16_t)output / 2U); } else { (*((volatile uint16_t *)(0x00007A80U + 0x36U))) &= ~(0x1U << ((uint16_t)output / 2U)); } __edis(); } //***************************************************************************** // //! Returns the status of the output latch //! //! \param output is the X-BAR output being checked. //! //! \return Returns \b true if the output corresponding to \e output was //! triggered. If not, it will return \b false. // //***************************************************************************** static inline _Bool XBAR_getOutputLatchStatus(XBAR_OutputNum output) { // // Get the status of the Output X-BAR output latch. // return(((*((volatile uint16_t *)(0x00007A80U + 0x30U))) & (0x1U << ((uint16_t)output / 2U))) != 0U); } //***************************************************************************** // //! Clears the output latch for the specified output. //! //! \param output is the X-BAR output being configured. //! //! This function clears the Output X-BAR output latch. The output to be //! configured is specified by the \e output parameter. //! //! \return None. // //***************************************************************************** static inline void XBAR_clearOutputLatch(XBAR_OutputNum output) { // // Set the bit that clears the corresponding OUTPUTLATCH bit. // (*((volatile uint16_t *)(0x00007A80U + 0x32U))) |= 0x1U << ((uint16_t)output / 2U); } //***************************************************************************** // //! Forces the output latch for the specified output. //! //! \param output is the X-BAR output being configured. //! //! This function forces the Output X-BAR output latch. The output to be //! configured is specified by the \e output parameter. //! //! \return None. // //***************************************************************************** static inline void XBAR_forceOutputLatch(XBAR_OutputNum output) { // // Set the bit that forces the corresponding OUTPUTLATCH bit. // (*((volatile uint16_t *)(0x00007A80U + 0x34U))) = 0x1U << ((uint16_t)output / 2U); } //***************************************************************************** // //! Configures the polarity of an Output X-BAR output. //! //! \param output is the X-BAR output being configured. //! \param invert is a flag that determines whether the output is active-high //! or active-low. //! //! This function inverts the Output X-BAR signal if the \e invert parameter is //! \b true. If \e invert is \b false, the signal will be passed as is. The //! \e output parameter is a value \b XBAR_OUTPUTy where y is the output //! number between 1 and 8 inclusive. //! //! \return None. // //***************************************************************************** static inline void XBAR_invertOutputSignal(XBAR_OutputNum output, _Bool invert) { // // Set or clear the polarity setting bit based on the invert parameter. // __eallow(); if(invert) { (*((volatile uint16_t *)(0x00007A80U + 0x38U))) |= 0x1U << ((uint16_t)output / 2U); } else { (*((volatile uint16_t *)(0x00007A80U + 0x38U))) &= ~(0x1U << ((uint16_t)output / 2U)); } __edis(); } //***************************************************************************** // //! Enables the ePWM X-BAR mux values to be passed to an ePWM module. //! //! \param trip is the X-BAR output being configured. //! \param muxes is a bit field of the muxes to be enabled. //! //! This function enables the mux values to be passed to the X-BAR trip //! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is //! the number of the trip signal on the ePWM. //! //! The \e muxes parameter is a bit field of the muxes being enabled where bit //! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided //! in the form of \b XBAR_MUXnn that can be logically OR'd together to //! enable several muxes on an output at the same time. //! //! \return None. // //***************************************************************************** static inline void XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes) { // // Set the enable bit. // __eallow(); (*((volatile uint32_t *)((0x00007A00U + 0x20U) + (uint16_t)trip))) |= muxes; __edis(); } //***************************************************************************** // //! Disables the ePWM X-BAR mux values to be passed to an ePWM module. //! //! \param trip is the X-BAR output being configured. //! \param muxes is a bit field of the muxes to be disabled. //! //! This function disables the mux values to be passed to the X-BAR trip //! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is //! the number of the trip signal on the ePWM. //! //! The \e muxes parameter is a bit field of the muxes being disabled where bit //! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided //! in the form of \b XBAR_MUXnn that can be logically OR'd together to //! disable several muxes on an output at the same time. //! //! \return None. // //***************************************************************************** static inline void XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes) { // // Clear the enable bit. // __eallow(); (*((volatile uint32_t *)((0x00007A00U + 0x20U) + (uint16_t)trip))) &= ~(muxes); __edis(); } //***************************************************************************** // //! Configures the polarity of an ePWM X-BAR output. //! //! \param trip is the X-BAR output being configured. //! \param invert is a flag that determines whether the output is active-high //! or active-low. //! //! This function inverts the ePWM X-BAR trip signal if the \e invert //! parameter is \b true. If \e invert is \b false, the signal will be passed //! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is //! the number of the trip signal on the ePWM X-BAR that is being configured. //! //! \return None. // //***************************************************************************** static inline void XBAR_invertEPWMSignal(XBAR_TripNum trip, _Bool invert) { // // Set or clear the polarity setting bit based on the invert parameter. // __eallow(); if(invert) { (*((volatile uint16_t *)(0x00007A00U + 0x38U))) |= 0x1U << ((uint16_t)trip / 2U); } else { (*((volatile uint16_t *)(0x00007A00U + 0x38U))) &= ~(0x1U << ((uint16_t)trip / 2U)); } __edis(); } //***************************************************************************** // //! Sets the GPIO pin for an Input X-BAR input. //! //! \param input is the X-BAR input being configured. //! \param pin is the identifying number of the pin. //! //! This function configures which GPIO is assigned to an Input X-BAR input. //! The \e input parameter is a value in the form of a define \b XBAR_INPUTy //! where y is a the input number for the Input X-BAR. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** static inline void XBAR_setInputPin(XBAR_InputNum input, uint16_t pin) { // // Check the argument. // ; // // Write the requested pin to the appropriate input select register. // __eallow(); (*((volatile uint16_t *)((0x00007900U + 0x0U) + (uint16_t)input))) = pin; __edis(); } //***************************************************************************** // //! Locks an input to the Input X-BAR. //! //! \param input is an input to the Input X-BAR. //! //! This function locks the specific input on the Input X-BAR. //! //! \return None. // //***************************************************************************** static inline void XBAR_lockInput(XBAR_InputNum input) { // // lock the input in the INPUTSELECTLOCK register. // __eallow(); (*((volatile uint32_t *)(0x00007900U + 0x1EU))) = (uint32_t)1U << (uint16_t)input; __edis(); } //***************************************************************************** // //! Locks the Output X-BAR. //! //! This function locks the Output X-BAR. //! //! \return None. // //***************************************************************************** static inline void XBAR_lockOutput(void) { // // Lock the Output X-BAR with the OUTPUTLOCK register. // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. // __eallow(); (*((volatile uint32_t *)(0x00007A80U + 0x3EU))) = ((uint32_t)0x5A5A << 16U) | (uint32_t)0x1U; __edis(); } //***************************************************************************** // //! Locks the ePWM X-BAR. //! //! This function locks the ePWM X-BAR. //! //! \return None. // //***************************************************************************** static inline void XBAR_lockEPWM(void) { // // Lock the ePWM X-BAR with the TRIPLOCK register. // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. // __eallow(); (*((volatile uint32_t *)(0x00007A00U + 0x3EU))) = ((uint32_t)0x5A5A << 16U) | (uint32_t)0x1U; __edis(); } //***************************************************************************** // //! Configures the Output X-BAR mux that determines the signals passed to an //! output. //! //! \param output is the X-BAR output being configured. //! \param muxConfig is mux configuration that specifies the signal. //! //! This function configures an Output X-BAR mux. This determines which //! signal(s) should be passed through the X-BAR to a GPIO. The \e output //! parameter is a value \b XBAR_OUTPUTy where y is a the output number //! between 1 and 8 inclusive. //! //! The \e muxConfig parameter is the mux configuration value that specifies //! which signal will be passed from the mux. The values have the format of //! \b XBAR_OUT_MUXnn_xx where the 'xx' is the signal and nn is the mux //! number (00 through 11). The possible values are found in xbar.h //! //! This function may be called for each mux of an output and their values will //! be logically OR'd before being passed to the output signal. This means that //! this function may be called, for example, with the argument //! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument //! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX03 //! being logically OR'd if both are enabled. Calling the function twice for //! the same mux on the output will result in the configuration in the second //! call overwriting the first. //! //! \return None. // //***************************************************************************** extern void XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig); //***************************************************************************** // //! Configures the ePWM X-BAR mux that determines the signals passed to an //! ePWM module. //! //! \param trip is the X-BAR output being configured. //! \param muxConfig is mux configuration that specifies the signal. //! //! This function configures an ePWM X-BAR mux. This determines which signal(s) //! should be passed through the X-BAR to an ePWM module. The \e trip //! parameter is a value \b XBAR_TRIPy where y is a the number of the trip //! signal on the ePWM. //! //! The \e muxConfig parameter is the mux configuration value that specifies //! which signal will be passed from the mux. The values have the format of //! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux //! number (0 through 31). The possible values are found in xbar.h //! //! This function may be called for each mux of an output and their values will //! be logically OR'd before being passed to the trip signal. This means that //! this function may be called, for example, with the argument //! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument //! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX03 //! being logically OR'd if both are enabled. Calling the function twice for //! the same mux on the output will result in the configuration in the second //! call overwriting the first. //! //! \return None. // //***************************************************************************** extern void XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig); //***************************************************************************** // //! Returns the status of the input latch. //! //! \param inputFlag is the X-BAR input latch being checked. Values are in the //! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal. //! //! \return Returns \b true if the X-BAR input corresponding to the //! \e inputFlag has been triggered. If not, it will return \b false. // //***************************************************************************** extern _Bool XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag); //***************************************************************************** // //! Clears the input latch for the specified input latch. //! //! \param inputFlag is the X-BAR input latch being cleared. //! //! This function clears the Input X-BAR input latch. The input latch to be //! cleared is specified by the \e inputFlag parameter. //! //! \return None. // //***************************************************************************** extern void XBAR_clearInputFlag(XBAR_InputFlag inputFlag); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to GPIO_setPadConfig() as the pinType parameter // and returned by GPIO_getPadConfig(). // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO //! parameter and returned from GPIO_getDirectionMode(). // //***************************************************************************** typedef enum { GPIO_DIR_MODE_IN, //!< Pin is a GPIO input GPIO_DIR_MODE_OUT //!< Pin is a GPIO output } GPIO_Direction; //***************************************************************************** // //! Values that can be passed to GPIO_setInterruptType() as the \e intType //! parameter and returned from GPIO_getInterruptType(). // //***************************************************************************** typedef enum { GPIO_INT_TYPE_FALLING_EDGE = 0x00, //!< Interrupt on falling edge GPIO_INT_TYPE_RISING_EDGE = 0x04, //!< Interrupt on rising edge GPIO_INT_TYPE_BOTH_EDGES = 0x0C //!< Interrupt on both edges } GPIO_IntType; //***************************************************************************** // //! Values that can be passed to GPIO_setQualificationMode() as the //! \e qualification parameter and returned by GPIO_getQualificationMode(). // //***************************************************************************** typedef enum { GPIO_QUAL_SYNC, //!< Synchronization to SYSCLKOUT GPIO_QUAL_3SAMPLE, //!< Qualified with 3 samples GPIO_QUAL_6SAMPLE, //!< Qualified with 6 samples GPIO_QUAL_ASYNC //!< No synchronization } GPIO_QualificationMode; //***************************************************************************** // //! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter. // //***************************************************************************** typedef enum { GPIO_ANALOG_DISABLED, //!< Pin is in digital mode GPIO_ANALOG_ENABLED //!< Pin is in analog mode } GPIO_AnalogMode; //***************************************************************************** // //! Values that can be passed to GPIO_setMasterCore() as the \e core parameter. // //***************************************************************************** typedef enum { GPIO_CORE_CPU1, //!< CPU1 selected as master core GPIO_CORE_CPU1_CLA1 //!< CPU1's CLA1 selected as master core } GPIO_CoreSelect; //***************************************************************************** // //! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(), //! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter. // //***************************************************************************** typedef enum { GPIO_PORT_A = 0, //!< GPIO port A GPIO_PORT_B = 1, //!< GPIO port B GPIO_PORT_H = 7 //!< GPIO port H } GPIO_Port; //***************************************************************************** // //! Values that can be passed to GPIO_setInterruptPin(), //! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(), //! GPIO_disableInterrupt(), as the \e extIntNum parameter. // //***************************************************************************** typedef enum { GPIO_INT_XINT1, //!< External Interrupt 1 GPIO_INT_XINT2, //!< External Interrupt 2 GPIO_INT_XINT3, //!< External Interrupt 3 GPIO_INT_XINT4, //!< External Interrupt 4 GPIO_INT_XINT5 //!< External Interrupt 5 } GPIO_ExternalIntNum; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks that a pin number is valid for a device. //! //! Note that this function reflects the highest possible GPIO number of a //! device on its biggest package. Check the datasheet to see what the actual //! range of valid pin numbers is for a specific package. //! //! \return None. // //***************************************************************************** //***************************************************************************** // //! Sets the interrupt type for the specified pin. //! //! \param extIntNum specifies the external interrupt. //! \param intType specifies the type of interrupt trigger mechanism. //! //! This function sets up the various interrupt trigger mechanisms for the //! specified pin on the selected GPIO port. //! //! The following defines can be used to specify the external interrupt for the //! \e extIntNum parameter: //! //! - \b GPIO_INT_XINT1 //! - \b GPIO_INT_XINT2 //! - \b GPIO_INT_XINT3 //! - \b GPIO_INT_XINT4 //! - \b GPIO_INT_XINT5 //! //! One of the following flags can be used to define the \e intType //! parameter: //! //! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to //! falling //! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising //! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges //! //! \return None. // //***************************************************************************** static inline void GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType) { // // Write the selected polarity to the appropriate register. // (*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) = ((*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) & ~0xCU) | (uint16_t)intType; } //***************************************************************************** // //! Gets the interrupt type for a pin. //! //! \param extIntNum specifies the external interrupt. //! //! This function gets the interrupt type for a interrupt. The interrupt can be //! configured as a falling-edge, rising-edge, or both-edges detected //! interrupt. //! //! The following defines can be used to specify the external interrupt for the //! \e extIntNum parameter: //! //! - \b GPIO_INT_XINT1 //! - \b GPIO_INT_XINT2 //! - \b GPIO_INT_XINT3 //! - \b GPIO_INT_XINT4 //! - \b GPIO_INT_XINT5 //! //! \return Returns one of the flags described for GPIO_setInterruptType(). // //***************************************************************************** static inline GPIO_IntType GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum) { // // Read the selected polarity from the appropriate register. // return((GPIO_IntType)((*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) & 0xCU)); } //***************************************************************************** // //! Enables the specified external interrupt. //! //! \param extIntNum specifies the external interrupt. //! //! This function enables the indicated external interrupt sources. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! The following defines can be used to specify the external interrupt for the //! \e extIntNum parameter: //! //! - \b GPIO_INT_XINT1 //! - \b GPIO_INT_XINT2 //! - \b GPIO_INT_XINT3 //! - \b GPIO_INT_XINT4 //! - \b GPIO_INT_XINT5 //! //! \return None. // //***************************************************************************** static inline void GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum) { // // Set the enable bit for the specified interrupt. // (*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) |= 0x1U; } //***************************************************************************** // //! Disables the specified external interrupt. //! //! \param extIntNum specifies the external interrupt. //! //! This function disables the indicated external interrupt sources. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! The following defines can be used to specify the external interrupt for the //! \e extIntNum parameter: //! //! - \b GPIO_INT_XINT1 //! - \b GPIO_INT_XINT2 //! - \b GPIO_INT_XINT3 //! - \b GPIO_INT_XINT4 //! - \b GPIO_INT_XINT5 //! //! \return None. // //***************************************************************************** static inline void GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum) { // // Clear the enable bit for the specified interrupt // (*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) &= ~0x1U; } //***************************************************************************** // //! Reads the value present on the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! //! The value at the specified pin are read, as specified by \e pin. The value //! is returned for both input and output pins. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return Returns the value in the data register for the specified pin. // //***************************************************************************** static inline uint32_t GPIO_readPin(uint32_t pin) { volatile uint32_t *gpioDataReg; // // Check the arguments. // ; gpioDataReg = (uint32_t *)0x00007F00U + ((pin / 32U) * ((0x8U - 0x0U) / 2U)); return((gpioDataReg[(0x0U / 2U)] >> (pin % 32U)) & (uint32_t)0x1U); } //***************************************************************************** // //! Writes a value to the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! \param outVal is the value to write to the pin. //! //! Writes the corresponding bit values to the output pin specified by //! \e pin. Writing to a pin configured as an input pin has no effect. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** static inline void GPIO_writePin(uint32_t pin, uint32_t outVal) { volatile uint32_t *gpioDataReg; uint32_t pinMask; // // Check the arguments. // ; gpioDataReg = (uint32_t *)0x00007F00U + ((pin / 32U) * ((0x8U - 0x0U) / 2U)); pinMask = (uint32_t)1U << (pin % 32U); if(outVal == 0U) { gpioDataReg[(0x4U / 2U)] = pinMask; } else { gpioDataReg[(0x2U / 2U)] = pinMask; } } //***************************************************************************** // //! Toggles the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! //! Writes the corresponding bit values to the output pin specified by //! \e pin. Writing to a pin configured as an input pin has no effect. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** static inline void GPIO_togglePin(uint32_t pin) { volatile uint32_t *gpioDataReg; // // Check the arguments. // ; gpioDataReg = (uint32_t *)0x00007F00U + ((pin / 32U) * ((0x8U - 0x0U) / 2U)); gpioDataReg[(0x6U / 2U)] = (uint32_t)1U << (pin % 32U); } //***************************************************************************** // //! Reads the data on the specified port. //! //! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X //! where X is the port letter. //! //! \return Returns the value in the data register for the specified port. Each //! bit of the the return value represents a pin on the port, where bit 0 //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. // //***************************************************************************** static inline uint32_t GPIO_readPortData(GPIO_Port port) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and return DATA. // gpioDataReg = (uint32_t *)0x00007F00U + ((uint32_t)port * ((0x8U - 0x0U) / 2U)); return(gpioDataReg[(0x0U / 2U)]); } //***************************************************************************** // //! Writes a value to the specified port. //! //! \param port is the GPIO port being accessed. //! \param outVal is the value to write to the port. //! //! This function writes the value \e outVal to the port specified by the //! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X //! is the port letter. For example, use \b GPIO_PORT_A to affect port A //! (GPIOs 0-31). //! //! The \e outVal is a bit-packed value, where each bit represents a bit on a //! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port //! pin 1, and so on. //! //! \return None. // //***************************************************************************** static inline void GPIO_writePortData(GPIO_Port port, uint32_t outVal) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to DATA. // gpioDataReg = (uint32_t *)0x00007F00U + ((uint32_t)port * ((0x8U - 0x0U) / 2U)); gpioDataReg[(0x0U / 2U)] = outVal; } //***************************************************************************** // //! Sets all of the specified pins on the specified port. //! //! \param port is the GPIO port being accessed. //! \param pinMask is a mask of which of the 32 pins on the port are affected. //! //! This function sets all of the pins specified by the \e pinMask parameter on //! the port specified by the \e port parameter which takes a value in the //! form of \b GPIO_PORT_X where X is the port letter. For example, use //! \b GPIO_PORT_A to affect port A (GPIOs 0-31). //! //! The \e pinMask is a bit-packed value, where each bit that is set identifies //! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO //! port pin 1, and so on. //! //! \return None. // //***************************************************************************** static inline void GPIO_setPortPins(GPIO_Port port, uint32_t pinMask) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to SET. // gpioDataReg = (uint32_t *)0x00007F00U + ((uint32_t)port * ((0x8U - 0x0U) / 2U)); gpioDataReg[(0x2U / 2U)] = pinMask; } //***************************************************************************** // //! Clears all of the specified pins on the specified port. //! //! \param port is the GPIO port being accessed. //! \param pinMask is a mask of which of the 32 pins on the port are affected. //! //! This function clears all of the pins specified by the \e pinMask parameter //! on the port specified by the \e port parameter which takes a value in the //! form of \b GPIO_PORT_X where X is the port letter. For example, use //! \b GPIO_PORT_A to affect port A (GPIOs 0-31). //! //! The \e pinMask is a bit-packed value, where each bit that is \b set //! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1 //! represents GPIO port pin 1, and so on. //! //! \return None. // //***************************************************************************** static inline void GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to CLEAR. // gpioDataReg = (uint32_t *)0x00007F00U + ((uint32_t)port * ((0x8U - 0x0U) / 2U)); gpioDataReg[(0x4U / 2U)] = pinMask; } //***************************************************************************** // //! Toggles all of the specified pins on the specified port. //! //! \param port is the GPIO port being accessed. //! \param pinMask is a mask of which of the 32 pins on the port are affected. //! //! This function toggles all of the pins specified by the \e pinMask parameter //! on the port specified by the \e port parameter which takes a value in the //! form of \b GPIO_PORT_X where X is the port letter. For example, use //! \b GPIO_PORT_A to affect port A (GPIOs 0-31). //! //! The \e pinMask is a bit-packed value, where each bit that is set identifies //! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents //! GPIO port pin 1, and so on. //! //! \return None. // //***************************************************************************** static inline void GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to TOGGLE. // gpioDataReg = (uint32_t *)0x00007F00U + ((uint32_t)port * ((0x8U - 0x0U) / 2U)); gpioDataReg[(0x6U / 2U)] = pinMask; } //***************************************************************************** // //! Locks the configuration of the specified pins on the specified port. //! //! \param port is the GPIO port being accessed. //! \param pinMask is a mask of which of the 32 pins on the port are affected. //! //! This function locks the configuration registers of the pins specified by //! the \e pinMask parameter on the port specified by the \e port parameter //! which takes a value in the form of \b GPIO_PORT_X where X is the port //! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). //! //! The \e pinMask is a bit-packed value, where each bit that is set identifies //! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents //! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. //! //! Note that this function is for locking the configuration of a pin such as //! the pin muxing, direction, open drain mode, and other settings. It does not //! affect the ability to change the value of the pin. //! //! \return None. // //***************************************************************************** static inline void GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to the lock. // gpioDataReg = (uint32_t *)0x00007C00U + ((uint32_t)port * ((0x40U - 0x0U) / 2U)); __eallow(); gpioDataReg[(0x3CU / 2U)] |= pinMask; __edis(); } //***************************************************************************** // //! Unlocks the configuration of the specified pins on the specified port. //! //! \param port is the GPIO port being accessed. //! \param pinMask is a mask of which of the 32 pins on the port are affected. //! //! This function locks the configuration registers of the pins specified by //! the \e pinMask parameter on the port specified by the \e port parameter //! which takes a value in the form of \b GPIO_PORT_X where X is the port //! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). //! //! The \e pinMask is a bit-packed value, where each bit that is set identifies //! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents //! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. //! //! \return None. // //***************************************************************************** static inline void GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to the lock. // gpioDataReg = (uint32_t *)0x00007C00U + ((uint32_t)port * ((0x40U - 0x0U) / 2U)); __eallow(); gpioDataReg[(0x3CU / 2U)] &= ~pinMask; __edis(); } //***************************************************************************** // //! Commits the lock configuration of the specified pins on the specified port. //! //! \param port is the GPIO port being accessed. //! \param pinMask is a mask of which of the 32 pins on the port are affected. //! //! This function commits the lock configuration registers of the pins //! specified by the \e pinMask parameter on the port specified by the \e port //! parameter which takes a value in the form of \b GPIO_PORT_X where X is the //! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). //! //! The \e pinMask is a bit-packed value, where each bit that is set identifies //! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents //! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. //! //! Note that once this function is called, GPIO_lockPortConfig() and //! GPIO_unlockPortConfig() will no longer have any effect on the specified //! pins. //! //! \return None. // //***************************************************************************** static inline void GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask) { volatile uint32_t *gpioDataReg; // // Get the starting address of the port's registers and write to the lock. // gpioDataReg = (uint32_t *)0x00007C00U + ((uint32_t)port * ((0x40U - 0x0U) / 2U)); __eallow(); gpioDataReg[(0x3EU / 2U)] |= pinMask; __edis(); } //***************************************************************************** // //! Sets the direction and mode of the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! \param pinIO is the pin direction mode. //! //! This function configures the specified pin on the selected GPIO port as //! either input or output. //! //! The parameter \e pinIO is an enumerated data type that can be one of the //! following values: //! //! - \b GPIO_DIR_MODE_IN //! - \b GPIO_DIR_MODE_OUT //! //! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input //! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** extern void GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO); //***************************************************************************** // //! Gets the direction mode of a pin. //! //! \param pin is the identifying GPIO number of the pin. //! //! This function gets the direction mode for a specified pin. The pin can be //! configured as either an input or output The type of direction is returned //! as an enumerated data type. //! //! \return Returns one of the enumerated data types described for //! GPIO_setDirectionMode(). // //***************************************************************************** extern GPIO_Direction GPIO_getDirectionMode(uint32_t pin); //***************************************************************************** // //! Sets the pin for the specified external interrupt. //! //! \param pin is the identifying GPIO number of the pin. //! \param extIntNum specifies the external interrupt. //! //! This function sets which pin triggers the selected external interrupt. //! //! The following defines can be used to specify the external interrupt for the //! \e extIntNum parameter: //! //! - \b GPIO_INT_XINT1 //! - \b GPIO_INT_XINT2 //! - \b GPIO_INT_XINT3 //! - \b GPIO_INT_XINT4 //! - \b GPIO_INT_XINT5 //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \sa XBAR_setInputPin() //! //! \return None. // //***************************************************************************** extern void GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum); //***************************************************************************** // //! Sets the pad configuration for the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! \param pinType specifies the pin type. //! //! This function sets the pin type for the specified pin. The parameter //! \e pinType can be the following values: //! //! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input //! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input //! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin //! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input //! //! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or //! \b GPIO_PIN_TYPE_PULLUP. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** extern void GPIO_setPadConfig(uint32_t pin, uint32_t pinType); //***************************************************************************** // //! Gets the pad configuration for a pin. //! //! \param pin is the identifying GPIO number of the pin. //! //! This function returns the pin type for the specified pin. The value //! returned corresponds to the values used in GPIO_setPadConfig(). //! //! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD, //! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT. // //***************************************************************************** extern uint32_t GPIO_getPadConfig(uint32_t pin); //***************************************************************************** // //! Sets the qualification mode for the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! \param qualification specifies the qualification mode of the pin. //! //! This function sets the qualification mode for the specified pin. The //! parameter \e qualification can be one of the following values: //! - \b GPIO_QUAL_SYNC //! - \b GPIO_QUAL_3SAMPLE //! - \b GPIO_QUAL_6SAMPLE //! - \b GPIO_QUAL_ASYNC //! //! To set the qualification sampling period, use //! GPIO_setQualificationPeriod(). //! //! \return None. // //***************************************************************************** extern void GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification); //***************************************************************************** // //! Gets the qualification type for the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! //! \return Returns the qualification mode in the form of one of the values //! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or //! \b GPIO_QUAL_ASYNC. // //***************************************************************************** extern GPIO_QualificationMode GPIO_getQualificationMode(uint32_t pin); //***************************************************************************** // //! Sets the qualification period for a set of pins //! //! \param pin is the identifying GPIO number of the pin. //! \param divider specifies the output drive strength. //! //! This function sets the qualification period for a set of \b 8 \b pins, //! specified by the \e pin parameter. For instance, passing in 3 as the value //! of \e pin will set the qualification period for GPIO0 through GPIO7, and a //! value of 98 will set the qualification period for GPIO96 through GPIO103. //! This is because the register field that configures the divider is shared. //! //! To think of this in terms of an equation, configuring \e pin as \b n will //! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7). //! //! \e divider is the value by which the frequency of SYSCLKOUT is divided. It //! can be 1 or an even value between 2 and 510 inclusive. //! //! \return None. // //***************************************************************************** extern void GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider); //***************************************************************************** // //! Selects the master core of a specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! \param core is the core that is master of the specified pin. //! //! This function configures which core owns the specified pin's data registers //! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data //! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's //! CLA1 master of the pin. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** extern void GPIO_setMasterCore(uint32_t pin, GPIO_CoreSelect core); //***************************************************************************** // //! Sets the analog mode of the specified pin. //! //! \param pin is the identifying GPIO number of the pin. //! \param mode is the selected analog mode. //! //! This function configures the specified pin for either analog or digital //! mode. Not all GPIO pins have the ability to be switched to analog mode, //! so refer to the technical reference manual for details. This setting should //! be thought of as another level of muxing. //! //! The parameter \e mode is an enumerated data type that can be one of the //! following values: //! //! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode //! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. //! //! \return None. // //***************************************************************************** extern void GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode); //***************************************************************************** // //! Configures the alternate function of a GPIO pin. //! //! \param pinConfig is the pin configuration value, specified as only one //! of the \b GPIO_#_???? values. //! //! This function configures the pin mux that selects the peripheral function //! associated with a particular GPIO pin. Only one peripheral function at a //! time can be associated with a GPIO pin, and each peripheral function should //! only be associated with a single GPIO pin at a time (despite the fact that //! many of them can be associated with more than one GPIO pin). //! //! The available mappings are supplied in pin_map.h. //! //! \return None. // //***************************************************************************** extern void GPIO_setPinConfig(uint32_t pinConfig); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: hrcap.h // // TITLE: C28x HRCAP Driver. // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup hrcap_api HRCAP //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_hrcap.h // // TITLE: Definitions for the HRCAP registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the HRCAP register offsets // //***************************************************************************** // Register // Register // Register // Register // Register // Interrupt Enable Register // Interrupt Flag Register // Interrupt Clear Register // Interrupt Force Register // Register // Counter Register // Capture Register // Counter Register // Capture Register //***************************************************************************** // // The following are defines for the bit fields in the ECCTL0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ECCTL1 register // //***************************************************************************** // select // Event 1 // select // Event 2 // select // Event 3 // select // Event 4 // a Cap Event //***************************************************************************** // // The following are defines for the bit fields in the ECCTL2 register // //***************************************************************************** // for continuous // select // counter, and interrupt flags. //***************************************************************************** // // The following are defines for the bit fields in the ECEINT register // //***************************************************************************** // Enable // Enable // Enable // Enable // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the ECFLG register // //***************************************************************************** // Flag // Flag // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the ECCLR register // //***************************************************************************** // Clear //***************************************************************************** // // The following are defines for the bit fields in the ECFRC register // //***************************************************************************** // Interrupt // Interrupt // Interrupt // Interrupt // Interrupt //***************************************************************************** // // The following are defines for the bit fields in the ECAPSYNCINSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the HRCTL register // //***************************************************************************** // Select //***************************************************************************** // // The following are defines for the bit fields in the HRINTEN register // //***************************************************************************** // enable // status enable //***************************************************************************** // // The following are defines for the bit fields in the HRFLG register // //***************************************************************************** // Status Flag // Flag Bit // status Flag Bi //***************************************************************************** // // The following are defines for the bit fields in the HRCLR register // //***************************************************************************** // Interrupt Flag // Interrupt Flag Bit // check status Flag Bit: //***************************************************************************** // // The following are defines for the bit fields in the HRFRC register // //***************************************************************************** // Interrupt Flag Bit // check status Flag Bit: //***************************************************************************** // // Values that can be passed to HRCAP_enableCalibrationInterrupt(), // HRCAP_disableCalibrationInterrupt() as the intFlags parameter and // HRCAP_clearCalibrationFlags() and HRCAP_swForceCalibration() as the flags // parameter and returned by HRCAP_getCalibrationFlags(). // //***************************************************************************** //! Global calibration interrupt flag //! //! Calibration done flag //! //! Calibration period overflow flag //! //***************************************************************************** // //! Values that can be passed to HRCAP_getCalibrationClockPeriod() as the //! \e clockSource parameter. // //***************************************************************************** typedef enum { HRCAP_CALIBRATION_CLOCK_SYSCLK = 0x0, //!< Use SYSCLK for period match. HRCAP_CALIBRATION_CLOCK_HRCLK = 0x4 //!< Use HRCLK for period match. }HRCAP_CalibrationClockSource; //***************************************************************************** // //! \internal //! Checks HRCAP base address. //! //! \param base specifies the HRCAP module base address. //! //! This function determines if an HRCAP module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! enables HRCAP. //! //! \param base is the base address of the HRCAP instance used. //! //! This function enables High Resolution Capture module. //! //! \note High resolution clock must be enabled before High Resolution Module //! is enabled. //! //! \return None. // //***************************************************************************** static inline void HRCAP_enableHighResolution(uint32_t base) { ; __eallow(); // Set HRE bit (*((volatile uint16_t *)(base + 0x0U))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disables HRCAP. //! //! \param base is the base address of the HRCAP instance used. //! //! This function disable High Resolution Capture module. //! //! //! \return None. // //***************************************************************************** static inline void HRCAP_disableHighResolution(uint32_t base) { ; __eallow(); // Set HRE bit (*((volatile uint16_t *)(base + 0x0U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Enables high resolution clock. //! //! \param base is the base address of the HRCAP instance used. //! //! This function enables High Resolution clock. //! //! \return None. // //***************************************************************************** static inline void HRCAP_enableHighResolutionClock(uint32_t base) { ; __eallow(); // Set HRCLKE bit (*((volatile uint16_t *)(base + 0x0U))) |= 0x2U; __edis(); } //***************************************************************************** // //! Disables High resolution clock. //! //! \param base is the base address of the HRCAP instance used. //! //! This function disables High Resolution clock. //! //! \return None. // //***************************************************************************** static inline void HRCAP_disbleHighResolutionClock(uint32_t base) { ; __eallow(); // Clear HRCLKE bit (*((volatile uint16_t *)(base + 0x0U))) &= ~0x2U; __edis(); } //***************************************************************************** // //! Starts calibration. //! //! \param base is the base address of the HRCAP instance used. //! //! This function starts calibration. //! //! \return None. // //***************************************************************************** static inline void HRCAP_startCalibration(uint32_t base) { ; __eallow(); // Set CALIBSTART bit (*((volatile uint16_t *)(base + 0x0U))) |= 0x8U; __edis(); } //***************************************************************************** // //! Sets the calibration mode. //! //! \param base is the base address of the HRCAP instance used. //! //! This function sets the the calibration mode by turning on continuous //! calibration. //! //! \return None. // //***************************************************************************** static inline void HRCAP_setCalibrationMode(uint32_t base) { ; __eallow(); // Write to CALIBSTS and CALIBCONT bits (*((volatile uint16_t *)(base + 0x0U))) |= 0x20U; __edis(); } //***************************************************************************** // //! Enables calibration interrupt. //! //! \param base is the base address of the HRCAP module. //! \param intFlags is the calibration interrupt flags to be enabled. //! //! This function enables HRCAP calibration interrupt flags. //! Valid values for intFlags are: //! - HRCAP_CALIBRATION_DONE - Calibration done interrupt. //! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow //! check interrupt. //! \return None. // //***************************************************************************** static inline void HRCAP_enableCalibrationInterrupt(uint32_t base, uint16_t intFlags) { ; ; __eallow(); // Set CALIBDONE or CALPRDCHKSTS (*((volatile uint16_t *)(base + 0x4U))) |= intFlags; __edis(); } //***************************************************************************** // //! Disables calibration interrupt source. //! //! \param base is the base address of the HRCAP module. //! \param intFlags is the calibration interrupt flags to be disabled. //! //! This function disables HRCAP calibration interrupt flags. //! Valid values for intFlags are: //! - HRCAP_CALIBRATION_DONE - Calibration done interrupt. //! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period check //! interrupt. //! \return None. // //***************************************************************************** static inline void HRCAP_disableCalibrationInterrupt(uint32_t base, uint16_t intFlags) { ; ; __eallow(); // Clear CALIBDONE or CALPRDCHKSTS (*((volatile uint16_t *)(base + 0x4U))) &= ~intFlags; __edis(); } //***************************************************************************** // //! Returns the calibration interrupt source. //! //! \param base is the base address of the HRCAP module. //! //! This function returns the HRCAP calibration interrupt source. //! //! \return Returns the HRCAP interrupt that has occurred. The following are //! valid return values. //! - HRCAP_GLOBAL_CALIBRATION_INTERRUPT - Global calibration //! interrupt. //! - HRCAP_CALIBRATION_DONE - Calibration done interrupt. //! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow //! interrupt. //! //! \note - User can check if a combination of the interrupts have occurred //! by ORing the above return values. // //***************************************************************************** static inline uint16_t HRCAP_getCalibrationFlags(uint32_t base) { ; // Return contents of HRFLG register return((uint16_t)((*((volatile uint16_t *)(base + 0x6U))) & 0x7U)); } //***************************************************************************** // //! Clears calibration flags. //! //! \param base is the base address of the HRCAP module. //! \param flags is the calibration flags to be cleared. //! //! This function clears HRCAP calibration flags. //! The following are valid values for flags. //! - HRCAP_GLOBAL_CALIBRATION_INTERRUPT - Global calibration interrupt. //! - HRCAP_CALIBRATION_DONE - Calibration done flag. //! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow flag. //! //! \return None. // //***************************************************************************** static inline void HRCAP_clearCalibrationFlags(uint32_t base, uint16_t flags) { ; ; // Write to HRCLR register (*((volatile uint16_t *)(base + 0x8U))) |= flags; } //***************************************************************************** // //! Sets the calibration period count //! //! \param base is the base address of the HRCAP instance used. //! \param sysclkHz is the rate of the SYSCLK in Hz. //! //! This function sets the calibration period count value to achieve a period //! of 1.6 microseconds given the SYSCLK frequency in Hz (the \e sysclkHz //! parameter). //! //! \return None. // //***************************************************************************** static inline void HRCAP_setCalibrationPeriod(uint32_t base, uint32_t sysclkHz) { ; __eallow(); (*((volatile uint32_t *)(base + 0xCU))) = (sysclkHz * 16U) / 10000U; __edis(); } //***************************************************************************** // //! Returns the calibration clock period //! //! \param base is the base address of the HRCAP instance used. //! \param clockSource is the calibration clock source //! (\b HRCAP_CALIBRATION_CLOCK_SYSCLK or \b HRCAP_CALIBRATION_CLOCK_HRCLK). //! //! This function returns the period match value of the calibration clock. The //! return value has a valid count when a period match occurs. //! //! \return This function returns the captured value of the clock counter //! specified by clockSource. // //***************************************************************************** static inline uint32_t HRCAP_getCalibrationClockPeriod(uint32_t base, HRCAP_CalibrationClockSource clockSource) { ; // Return HRCAP_O_HRSYSCLKCAP or HRCAP_O_HRCLKCAP return((*((volatile uint32_t *)(base + 0x10U + (uint32_t)clockSource)))); } //***************************************************************************** // //! Calculates the scale factor //! //! \param base is the base address of the HRCAP instance used. //! //! This function reads the SYSCLK and HRCLK calibration periods and then //! uses them to calculate the scale factor. //! //! \return This function returns the calculated scale factor. // //***************************************************************************** static inline float32_t HRCAP_getScaleFactor(uint32_t base) { ; // Calculate and return the scale factor return((float32_t)HRCAP_getCalibrationClockPeriod(base, HRCAP_CALIBRATION_CLOCK_SYSCLK) / (float32_t)HRCAP_getCalibrationClockPeriod(base, HRCAP_CALIBRATION_CLOCK_HRCLK)); } //***************************************************************************** // //! Returns event time stamp in nanoseconds //! //! \param timeStamp is a raw time stamp count returned by //! ECAP_getEventTimeStamp(). //! \param scaleFactor is the calculated scale factor returned by //! HRCAP_getScaleFactor(). //! //! This function converts a raw CAP time stamp (the \e timeStamp parameter) to //! nanoseconds using the provided scale factor (the \e scaleFactor parameter). //! //! \return Returns the converted time stamp in nanoseconds. // //***************************************************************************** static inline float32_t HRCAP_convertEventTimeStampNanoseconds(uint32_t timeStamp, float32_t scaleFactor) { // Convert the raw count value to nanoseconds using the given scale factor return((float32_t)timeStamp * scaleFactor * ((float32_t)10.0 / (float32_t)128.0)); } //***************************************************************************** // Close the Doxygen group. //! @} // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //############################################################################# // // FILE: hrpwm.h // // TITLE: C28x HRPWM Driver // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup hrpwm_api HRPWM //! @{ // //***************************************************************************** // **************************************************************************** // the includes // **************************************************************************** //########################################################################### // // FILE: hw_hrpwm.h // // TITLE: Definitions for the HRPWM registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the HRPWM register offsets // //***************************************************************************** // Register // Register 2 // Register // Register 2 // Register // Event Source Select Register // Register // Register // Register // Control Register // Remainder Register // Register // Register // Register For Output A // Control Register For Output A // Register For Output B // Control Register For Output B // Force Register // S/W Force Register // Edge Delay High Resolution // Mirror Register // Edge Delay High Resolution // Mirror Register // Edge Delay High Resolution // Register // Edge Delay Count Register // Resolution Register // Register 2 // Register // Select Register // Register // Digital Compare A // Digital Compare B // Register // Register // Register // Pre-Scale Register // Register // Initialization Control Register // Initialization Register // Register // Register // Register // Control Register // Control Register // Register // Counter Register // Register // Counter Register // Capture Register // Select // Select // Select // Select // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the TBCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TBCTL2 register // //***************************************************************************** // SYNC Event //***************************************************************************** // // The following are defines for the bit fields in the TBSTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CMPCTL register // //***************************************************************************** // Operating Mode // Operating Mode // Full Status // Full Status //***************************************************************************** // // The following are defines for the bit fields in the CMPCTL2 register // //***************************************************************************** // Mode // Mode //***************************************************************************** // // The following are defines for the bit fields in the DBCTL register // //***************************************************************************** // Control // Control //***************************************************************************** // // The following are defines for the bit fields in the DBCTL2 register // //***************************************************************************** // Select //***************************************************************************** // // The following are defines for the bit fields in the AQCTL register // //***************************************************************************** // Select // Select // Mode // Mode //***************************************************************************** // // The following are defines for the bit fields in the AQTSRCSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the VCAPCTL register // //***************************************************************************** // Enable // Select //***************************************************************************** // // The following are defines for the bit fields in the VCNTCFG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the HRCNFG register // //***************************************************************************** // Bits // Bits // Bit // Bits // Bits //***************************************************************************** // // The following are defines for the bit fields in the HRPWR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the HRMSTEP register // //***************************************************************************** // Value //***************************************************************************** // // The following are defines for the bit fields in the HRCNFG2 register // //***************************************************************************** // Bits // Bits // Bits //***************************************************************************** // // The following are defines for the bit fields in the HRPCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TRREM register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GLDCTL register // //***************************************************************************** // event control // Pulse Selection // bit // Select Register // Register //***************************************************************************** // // The following are defines for the bit fields in the GLDCFG register // //***************************************************************************** // configuration for TBPRD:TBPRDHR // configuration for CMPA:CMPAHR // configuration for CMPB:CMPBHR // configuration for CMPC // configuration for CMPD // configuration for DBRED:DBREDHR // configuration for DBFED:DBFEDHR // configuration for DBCTL // configuration for AQCTLA/A2 // configuration for AQCTLB/B2 // configuration for AQCSFRC //***************************************************************************** // // The following are defines for the bit fields in the EPWMXLINK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the EPWMREV register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the AQCTLA register // //***************************************************************************** // Down // Down //***************************************************************************** // // The following are defines for the bit fields in the AQCTLA2 register // //***************************************************************************** // T1 in UP-Count // T1 in DOWN-Count // T2 in UP-Count // T2 in DOWN-Count //***************************************************************************** // // The following are defines for the bit fields in the AQCTLB register // //***************************************************************************** // Down // Down //***************************************************************************** // // The following are defines for the bit fields in the AQCTLB2 register // //***************************************************************************** // T1 in UP-Count // T1 in DOWN-Count // T2 in UP-Count // T2 in DOWN-Count //***************************************************************************** // // The following are defines for the bit fields in the AQSFRC register // //***************************************************************************** // A Invoked // B Invoked //***************************************************************************** // // The following are defines for the bit fields in the AQCSFRC register // //***************************************************************************** // output A // output B //***************************************************************************** // // The following are defines for the bit fields in the DBREDHR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DBRED register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DBFEDHR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DBFED register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TBPHS register // //***************************************************************************** // Phase (8-bits) //***************************************************************************** // // The following are defines for the bit fields in the CMPA register // //***************************************************************************** // Register //***************************************************************************** // // The following are defines for the bit fields in the CMPB register // //***************************************************************************** // Bits //***************************************************************************** // // The following are defines for the bit fields in the GLDCTL2 register // //***************************************************************************** // shot mode // shot mode //***************************************************************************** // // The following are defines for the bit fields in the TZSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TZDCSEL register // //***************************************************************************** // Event 1 // Event 2 // Event 1 // Event 2 //***************************************************************************** // // The following are defines for the bit fields in the TZCTL register // //***************************************************************************** // EPWMxA // EPWMxB //***************************************************************************** // // The following are defines for the bit fields in the TZCTL2 register // //***************************************************************************** // Count direction is UP // Count direction is DOWN // Count direction is UP // Count direction is DOWN //***************************************************************************** // // The following are defines for the bit fields in the TZCTLDCA register // //***************************************************************************** // while Count direction is UP // while Count direction is DOWN // while Count direction is UP // while Count direction is DOWN //***************************************************************************** // // The following are defines for the bit fields in the TZCTLDCB register // //***************************************************************************** // while Count direction is UP // while Count direction is DOWN // while Count direction is UP // while Count direction is DOWN //***************************************************************************** // // The following are defines for the bit fields in the TZEINT register // //***************************************************************************** // Enable // Enable // Enable // Enable // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the TZFLG register // //***************************************************************************** // Flag // Flag // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the TZCBCFLG register // //***************************************************************************** // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Digital Compare Output A Event 2 // Digital Compare Output B Event 2 //***************************************************************************** // // The following are defines for the bit fields in the TZOSTFLG register // //***************************************************************************** // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Digital Compare Output A Event 1 // Digital Compare Output B Event 1 //***************************************************************************** // // The following are defines for the bit fields in the TZCLR register // //***************************************************************************** // Latch //***************************************************************************** // // The following are defines for the bit fields in the TZCBCCLR register // //***************************************************************************** // (CBC1) Trip Latch // (CBC2) Trip Latch // (CBC3) Trip Latch // (CBC4) Trip Latch // (CBC5) Trip Latch // (CBC6) Trip Latch // selected for CBC // selected for CBC //***************************************************************************** // // The following are defines for the bit fields in the TZOSTCLR register // //***************************************************************************** // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // Trip Latch // selected for OST // selected for OST //***************************************************************************** // // The following are defines for the bit fields in the TZFRC register // //***************************************************************************** // Cycle Event // Event // 1 // 2 // 1 // 2 //***************************************************************************** // // The following are defines for the bit fields in the ETSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETPS register // //***************************************************************************** // Bits // Selection Bits //***************************************************************************** // // The following are defines for the bit fields in the ETFLG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETCLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETFRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETINTPS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETSOCPS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the ETCNTINITCTL register // //***************************************************************************** // Initialization Force // Initialization Force // Initialization Force // Initialization Enable // Initialization Enable // Initialization Enable //***************************************************************************** // // The following are defines for the bit fields in the ETCNTINIT register // //***************************************************************************** // Initialization Bits // Initialization Bits // Initialization Bits //***************************************************************************** // // The following are defines for the bit fields in the DCTRIPSEL register // //***************************************************************************** // Input Select // Input Select // Input Select // Input Select //***************************************************************************** // // The following are defines for the bit fields in the DCACTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCBCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DCFCTL register // //***************************************************************************** // Select // Capture Alignment //***************************************************************************** // // The following are defines for the bit fields in the DCCAPCTL register // //***************************************************************************** // Capture Event // Clear Flag //***************************************************************************** // // The following are defines for the bit fields in the DCAHTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the DCALTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the DCBHTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the DCBLTRIPSEL register // //***************************************************************************** // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux // Mux //***************************************************************************** // // The following are defines for the bit fields in the EPWMLOCK register // //***************************************************************************** // Lock // Lock //############################################################################# // // FILE: hrpwm.h // // TITLE: C28x HRPWM Driver // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // //! Values that can be passed to HRPWM_setMEPEdgeSelect(), //! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent() //! as the \e channel parameter. // //***************************************************************************** typedef enum { HRPWM_CHANNEL_A = 0, //!< HRPWM A HRPWM_CHANNEL_B = 8 //!< HRPWM B }HRPWM_Channel; //***************************************************************************** // //! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode //! parameter. // //***************************************************************************** typedef enum { //! HRPWM is disabled HRPWM_MEP_CTRL_DISABLE = 0, //! MEP controls rising edge HRPWM_MEP_CTRL_RISING_EDGE = 1, //! MEP controls falling edge HRPWM_MEP_CTRL_FALLING_EDGE = 2, //! MEP controls both rising and falling edge HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3 }HRPWM_MEPEdgeMode; //***************************************************************************** // //! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e //! parameter. // //***************************************************************************** typedef enum { //! CMPAHR/CMPBHR or TBPRDHR controls MEP edge HRPWM_MEP_DUTY_PERIOD_CTRL = 0, //! TBPHSHR controls MEP edge HRPWM_MEP_PHASE_CTRL = 1 }HRPWM_MEPCtrlMode; //***************************************************************************** // //! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(), //! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode //! as the \e loadEvent parameter. // //***************************************************************************** typedef enum { //! load when counter equals zero HRPWM_LOAD_ON_CNTR_ZERO = 0, //! load when counter equals period HRPWM_LOAD_ON_CNTR_PERIOD = 1, //! load when counter equals zero or period HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2 }HRPWM_LoadMode; //***************************************************************************** // //! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e //! outputOnB parameter. // //***************************************************************************** typedef enum { HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal. HRPWM_OUTPUT_ON_B_INV_A = 1 //!< ePWMxB output is inverted //!< version of ePWMxA signal }HRPWM_ChannelBOutput; //***************************************************************************** // //! Values that can be passed to HRPWM_setSyncPulseSource() as the \e //! syncPulseSource parameter. // //***************************************************************************** typedef enum { //! Counter equals Period HRPWM_PWMSYNC_SOURCE_PERIOD = 0, //! Counter equals zero HRPWM_PWMSYNC_SOURCE_ZERO = 1, //! Counter equals COMPC when counting up HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4, //! Counter equals COMPC when counting down HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5, //! Counter equals COMPD when counting up HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6, //! Counter equals COMPD when counting down HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7 }HRPWM_SyncPulseSource; //***************************************************************************** // //! Values that can be passed to HRPWM_setCounterCompareValue() as the \e //! compModule parameter. // //***************************************************************************** typedef enum { HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A HRPWM_COUNTER_COMPARE_B = 4 //!< counter compare B }HRPWM_CounterCompareModule; //***************************************************************************** // //! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e //! mepDBEdge. // //***************************************************************************** typedef enum { //! HRPWM is disabled HRPWM_DB_MEP_CTRL_DISABLE = 0, //! MEP controls Rising Edge Delay HRPWM_DB_MEP_CTRL_RED = 1, //! MEP controls Falling Edge Delay HRPWM_DB_MEP_CTRL_FED = 2, //! MEP controls both Falling and Rising edge delay HRPWM_DB_MEP_CTRL_RED_FED = 3 }HRPWM_MEPDeadBandEdgeMode; //***************************************************************************** // //! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup //! parameter. // //***************************************************************************** typedef enum { HRPWM_REGISTER_GROUP_HRPWM = 0x1, //!< HRPWM register group HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group }HRPWM_LockRegisterGroup; // Functions APIs shared with ePWM module // // HRPWM_getTripZoneInterruptStatus API define is obsolete please use // HRPWM_getTripZoneFlagStatus going forward. // // // HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete // please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward. // // // HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use // HRPWM_getOneShotTripZoneFlagStatus going forward. // // // HRPWM_clearTripZoneInterruptFlag is obsolete please use // HRPWM_clearTripZoneFlag going forward. // // // HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use // HRPWM_clearCycleByCycleTripZoneFlag going forward. // // // HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use // HRPWM_clearOneShotTripZoneFlag going forward. // // API Function prototypes //***************************************************************************** // //! Sets the high resolution phase shift value. //! //! \param base is the base address of the EPWM module. //! \param phaseCount is the high resolution phase shift count value. //! //! This function sets the high resolution phase shift value. Call the //! HRPWM_enableHRPhaseShiftLoad() function to enable loading of the phaseCount //! //! \b Note: phaseCount is a 24 bit value //! //! \return None. // //***************************************************************************** static inline void HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount) { ; ; // write to TBPHS:TBPHSHR bit (*((volatile uint32_t *)(base + 0x60U))) = phaseCount << 8U; } //***************************************************************************** // //! Sets the period of the high resolution time base counter. //! //! \param base is the base address of the EPWM module. //! \param periodCount is high resolution period count value. //! //! This function sets the period of the high resolution time base counter. The //! value of periodCount is the value written to the register. User should //! map the desired period or frequency of the waveform into the correct //! periodCount. //! //! \b Note: periodCount is a 24 bit value //! //! \return None. // //***************************************************************************** static inline void HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount) { ; ; // write to TBPRD:TBPRDHR bit (*((volatile uint32_t *)(base + 0x62U))) = periodCount << 8U; } //***************************************************************************** // //! Gets the HRPWM period count. //! //! \param base is the base address of the EPWM module. //! //! This function gets the period of the HRPWM count. //! //! \return The period count value. // //***************************************************************************** static inline uint32_t HRPWM_getTimeBasePeriod(uint32_t base) { ; // read from TBPRD:TBPRDHR bit return((*((volatile uint32_t *)(base + 0x62U))) >> 8U); } //***************************************************************************** // //! Sets the high resolution edge controlled by MEP (Micro Edge Positioner). //! //! \param base is the base address of the EPWM module. //! \param channel is high resolution period module. //! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge //! Positioner). //! //! This function sets the edge of the PWM that is controlled by MEP (Micro //! Edge Positioner). Valid values for the parameters are: //! channel //! - HRPWM_CHANNEL_A - HRPWM A //! - HRPWM_CHANNEL_B - HRPWM B //! mepEdgeMode //! - HRPWM_MEP_CTRL_DISABLE - HRPWM is disabled //! - HRPWM_MEP_CTRL_RISING_EDGE - MEP (Micro Edge Positioner) //! controls rising edge. //! - HRPWM_MEP_CTRL_FALLING_EDGE - MEP (Micro Edge Positioner) //! controls falling edge. //! - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner) //! controls both edges. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, HRPWM_MEPEdgeMode mepEdgeMode) { ; // Set the edge mode __eallow(); (*((volatile uint16_t *)(base + 0x20U))) = (((*((volatile uint16_t *)(base + 0x20U))) & ~(0x3U << (uint16_t)channel )) | ((uint16_t)mepEdgeMode << (uint16_t)channel)); __edis(); } //***************************************************************************** // //! Sets the MEP (Micro Edge Positioner) control mode. //! //! \param base is the base address of the EPWM module. //! \param channel is high resolution period module. //! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode. //! //! This function sets the mode (register type) the MEP (Micro Edge Positioner) //! will control. Valid values for the parameters are: //! channel //! - HRPWM_CHANNEL_A - HRPWM A //! - HRPWM_CHANNEL_B - HRPWM B //! mepCtrlMode //! - HRPWM_MEP_DUTY_PERIOD_CTRL - MEP (Micro Edge Positioner) is //! controled by value of CMPAHR/ //! CMPBHR(depedning on the value of //! channel) or TBPRDHR. //! - HRPWM_MEP_PHASE_CTRL - MEP (Micro Edge Positioner) is //! controlled by TBPHSHR. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, HRPWM_MEPCtrlMode mepCtrlMode) { ; // Set the MEP control __eallow(); (*((volatile uint16_t *)(base + 0x20U))) = (((*((volatile uint16_t *)(base + 0x20U))) & ~(0x1U << ((uint16_t)channel + 2U))) | ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))); __edis(); } //***************************************************************************** // //! Sets the high resolution comparator load mode. //! //! \param base is the base address of the EPWM module. //! \param channel is high resolution period module. //! \param loadEvent is the MEP (Micro Edge Positioner) control mode. //! //! This function sets the shadow load mode of the high resolution comparator. //! The function sets the COMPA or COMPB register depending on the channel //! variable. //! Valid values for the parameters are: //! channel //! - HRPWM_CHANNEL_A - HRPWM A //! - HRPWM_CHANNEL_B - HRPWM B //! loadEvent //! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero //! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period //! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero //! or period //! //! \return None. // //***************************************************************************** static inline void HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, HRPWM_LoadMode loadEvent) { ; // Set the CMPAHR or CMPBHR load mode __eallow(); (*((volatile uint16_t *)(base + 0x20U))) = (((*((volatile uint16_t *)(base + 0x20U))) & ~(0x3U << ((uint16_t)channel + 3U))) | ((uint16_t)loadEvent << ((uint16_t)channel + 3U))); __edis(); } //***************************************************************************** // //! Sets the high resolution output swap mode. //! //! \param base is the base address of the EPWM module. //! \param enableOutputSwap is the output swap flag. //! //! This function sets the HRPWM output swap mode. If enableOutputSwap is true, //! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA //! output. If it is false ePWMxA and ePWMxB outputs are unchanged //! //! \return None. // //***************************************************************************** static inline void HRPWM_setOutputSwapMode(uint32_t base, _Bool enableOutputSwap) { ; __eallow(); if(enableOutputSwap) { (*((volatile uint16_t *)(base + 0x20U))) |= 0x80U; } else { (*((volatile uint16_t *)(base + 0x20U))) &= ~0x80U; } __edis(); } //***************************************************************************** // //! Sets the high resolution output on ePWMxB //! //! \param base is the base address of the EPWM module. //! \param outputOnB is the output signal on ePWMxB. //! //! This function sets the HRPWM output signal on ePWMxB. If outputOnB is //! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of //! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is //! ePWMxB. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB) { ; // Set the output on ePWM B __eallow(); (*((volatile uint16_t *)(base + 0x20U))) = (((*((volatile uint16_t *)(base + 0x20U))) & ~(0x20U)) | ((uint16_t)outputOnB << 5U)); __edis(); } //***************************************************************************** // //! Enables MEP (Micro Edge Positioner) automatic scale mode. //! //! \param base is the base address of the EPWM module. //! //! This function enables the MEP (Micro Edge Positioner) to automatically //! scale HRMSTEP. //! //! \return None. // //***************************************************************************** static inline void HRPWM_enableAutoConversion(uint32_t base) { ; // Enable MEP automatic scale __eallow(); (*((volatile uint16_t *)(base + 0x20U))) |= 0x40U; __edis(); } //***************************************************************************** // //! Disables MEP automatic scale mode. //! //! \param base is the base address of the EPWM module. //! //! This function disables the MEP (Micro Edge Positioner) from automatically //! scaling HRMSTEP. //! //! \return None. // //***************************************************************************** static inline void HRPWM_disableAutoConversion(uint32_t base) { ; // Disable MEP automatic scale __eallow(); (*((volatile uint16_t *)(base + 0x20U))) &= ~0x40U; __edis(); } //***************************************************************************** // //! Enable high resolution period feature. //! //! \param base is the base address of the EPWM module. //! //! This function enables the high resolution period feature. //! //! \return None. // //***************************************************************************** static inline void HRPWM_enablePeriodControl(uint32_t base) { ; // Set HRPE bit __eallow(); (*((volatile uint16_t *)(base + 0x2DU))) |= 0x1U; __edis(); } //***************************************************************************** // //! Disable high resolution period feature. //! //! \param base is the base address of the EPWM module. //! //! This function disables the high resolution period feature. //! //! \return None. // //***************************************************************************** static inline void HRPWM_disablePeriodControl(uint32_t base) { ; // Clear HRPE bit __eallow(); (*((volatile uint16_t *)(base + 0x2DU))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Enable high resolution phase load //! //! \param base is the base address of the EPWM module. //! //! This function enables loading of high resolution phase shift value which is //! set by the function HRPWM_setPhaseShift(). //! //! \return None. // //***************************************************************************** static inline void HRPWM_enablePhaseShiftLoad(uint32_t base) { ; // Set TBPHSHRLOADE bit __eallow(); (*((volatile uint16_t *)(base + 0x2DU))) |= 0x4U; __edis(); } //***************************************************************************** // //! Disable high resolution phase load //! //! \param base is the base address of the EPWM module. //! //! This function disables loading of high resolution phase shift value. //! //! \return // //***************************************************************************** static inline void HRPWM_disablePhaseShiftLoad(uint32_t base) { ; // Clear TBPHSHRLOADE bit __eallow(); (*((volatile uint16_t *)(base + 0x2DU))) &= ~0x4U; __edis(); } //***************************************************************************** // //! Set high resolution PWMSYNC source. //! //! \param base is the base address of the EPWM module. //! \param syncPulseSource is the PWMSYNC source. //! //! This function sets the high resolution PWMSYNC pulse source. //! Valid values for syncPulseSource are: //! - HRPWM_PWMSYNC_SOURCE_PERIOD - Counter equals Period. //! - HRPWM_PWMSYNC_SOURCE_ZERO - Counter equals zero. //! - HRPWM_PWMSYNC_SOURCE_COMPC_UP - Counter equals COMPC when //! counting up. //! - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN - Counter equals COMPC when //! counting down. //! - HRPWM_PWMSYNC_SOURCE_COMPD_UP - Counter equals COMPD when //! counting up. //! - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN - Counter equals COMPD when //! counting down. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource) { ; // Set the PWMSYNC source __eallow(); // If HRPWM_PWMSYNC_SOURCE_PERIOD or HRPWM_PWMSYNC_SOURCE_ZERO if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP) { (*((volatile uint16_t *)(base + 0x2DU))) = (((*((volatile uint16_t *)(base + 0x2DU))) & ~(0x70U | 0x2U)) | ((uint16_t)syncPulseSource << 1U)); } else { (*((volatile uint16_t *)(base + 0x2DU))) = (((*((volatile uint16_t *)(base + 0x2DU))) & ~0x70U) | ((uint16_t)syncPulseSource << 4U)); } __edis(); } //***************************************************************************** // //! Set high resolution counter compare values. //! //! \param base is the base address of the EPWM module. //! \param compModule is the Compare value module. //! \param compCount is the counter compare count value. //! //! This function sets the high resolution counter compare value for counter //! compare registers. //! Valid values for compModule are: //! - HRPWM_COUNTER_COMPARE_A - counter compare A. //! - HRPWM_COUNTER_COMPARE_B - counter compare B. //! //! \b Note: compCount is a 24 bit value //! //! \return None. // //***************************************************************************** static inline void HRPWM_setCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint32_t compCount) { ; ; // Write to the high resolution counter compare registers. if(compModule == HRPWM_COUNTER_COMPARE_A) { // write to CMPAHR (*((volatile uint32_t *)(base + 0x6AU))) = compCount << 8U; } else { // write to CMPBHR (*((volatile uint32_t *)(base + 0x6CU))) = compCount << 8U; } } //***************************************************************************** // //! Gets high resolution counter compare values. //! //! \param base is the base address of the EPWM module. //! \param compModule is the Compare value module. //! //! This function gets the high resolution counter compare value for counter //! compare registers specified. //! Valid values for compModule are: //! - HRPWM_COUNTER_COMPARE_A - counter compare A. //! - HRPWM_COUNTER_COMPARE_B - counter compare B. //! //! //! \return None. // //***************************************************************************** static inline uint32_t HRPWM_getCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule) { uint32_t compCount; ; // Write to the high resolution counter compare registers. if(compModule == HRPWM_COUNTER_COMPARE_A) { // read from CMPAHR compCount = (*((volatile uint32_t *)(base + 0x6AU))) >> 8U; } else { // read from CMPBHR compCount = (*((volatile uint32_t *)(base + 0x6CU))) >> 8U; } return(compCount); } //***************************************************************************** // //! Set High Resolution RED count //! //! \param base is the base address of the EPWM module. //! \param redCount is the high resolution RED count. //! //! This function sets the high resolution RED (Rising Edge Delay) count value. //! The value of redCount should be less than 0x200000. //! //! \b Note: redCount is a 21 bit value //! //! \return None. // //***************************************************************************** static inline void HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount) { ; ; // Set the High Resolution RED (Rising Edge Delay) count (*((volatile uint32_t *)(base + 0x50U))) = redCount << 9U; } //***************************************************************************** // //! Set High Resolution FED count //! //! \param base is the base address of the EPWM module. //! \param fedCount is the high resolution FED count. //! //! This function sets the high resolution FED (Falling Edge Delay) count //! value. The value of fedCount should be less than 0x200000. //! //! \b Note: fedCount is a 21 bit value //! //! \return None. // //***************************************************************************** static inline void HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount) { ; ; // Set the High Resolution FED (Falling Edge Delay) count (*((volatile uint32_t *)(base + 0x52U))) = fedCount << 9U; } //***************************************************************************** // //! Set high resolution MEP (Micro Edge Positioner) step. //! //! \param base is the base address of the EPWM module. //! \param mepCount is the high resolution MEP (Micro Edge Positioner) step //! count. //! //! This function sets the high resolution MEP (Micro Edge Positioner) step //! count. The maximum value for the MEP count step is 255. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setMEPStep(uint32_t base, uint16_t mepCount) { ; ; // Set HRPWM MEP count __eallow(); (*((volatile uint16_t *)(base + 0x26U))) = (((*((volatile uint16_t *)(base + 0x26U))) & ~0xFFU) | mepCount); __edis(); } //***************************************************************************** // //! Set high resolution Dead Band MEP (Micro Edge Positioner) control. //! //! \param base is the base address of the EPWM module. //! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control //! edge. //! //! This function sets the high resolution Dead Band edge that the MEP (Micro //! Edge Positioner) controls Valid values for mepDBEdge are: //! - HRPWM_DB_MEP_CTRL_DISABLE - HRPWM is disabled //! - HRPWM_DB_MEP_CTRL_RED - MEP (Micro Edge Positioner) controls //! Rising Edge Delay //! - HRPWM_DB_MEP_CTRL_FED - MEP (Micro Edge Positioner) controls //! Falling Edge Delay //! - HRPWM_DB_MEP_CTRL_RED_FED - MEP (Micro Edge Positioner) controls both //! Falling and Rising edge delays //! //! \return None. // //***************************************************************************** static inline void HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, HRPWM_MEPDeadBandEdgeMode mepDBEdge) { ; // Set the HRPWM DB edge mode __eallow(); (*((volatile uint16_t *)(base + 0x27U))) = (((*((volatile uint16_t *)(base + 0x27U))) & ~0x3U) | ((uint16_t)mepDBEdge)); __edis(); } //***************************************************************************** // //! Set the high resolution Dead Band RED load mode. //! //! \param base is the base address of the EPWM module. //! \param loadEvent is the shadow to active load event. //! //! This function sets the high resolution Rising Edge Delay(RED)Dead Band //! count load mode. //! Valid values for loadEvent are: //! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. //! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period //! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero //! or period. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent) { ; // Set the HRPWM RED load mode __eallow(); (*((volatile uint16_t *)(base + 0x27U))) = (((*((volatile uint16_t *)(base + 0x27U))) & ~0xCU) | ((uint16_t)loadEvent << 2U)); __edis(); } //***************************************************************************** // //! Set the high resolution Dead Band FED load mode. //! //! \param base is the base address of the EPWM module. //! \param loadEvent is the shadow to active load event. //! //! This function sets the high resolution Falling Edge Delay(FED) Dead Band //! count load mode. //! Valid values for loadEvent are: //! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. //! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period //! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero //! or period. //! //! \return None. // //***************************************************************************** static inline void HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent) { ; // Set the HRPWM FED load mode __eallow(); (*((volatile uint16_t *)(base + 0x27U))) = (((*((volatile uint16_t *)(base + 0x27U))) & ~0x30U) | ((uint16_t)loadEvent << 4U)); __edis(); } //***************************************************************************** // //! Lock EALLOW protected register groups //! //! \param base is the base address of the EPWM module. //! \param registerGroup is the EALLOW register groups. //! //! This functions locks the EALLOW protected register groups specified by //! the registerGroup variable. //! //! \return None. // //***************************************************************************** static inline void HRPWM_lockRegisters(uint32_t base, HRPWM_LockRegisterGroup registerGroup) { ; // write the Key to EPWMLOCK register (*((volatile uint32_t *)(base + 0xFAU))) = ((uint32_t)0xA5A50000U |((uint32_t)registerGroup)); } //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: i2c.h // // TITLE: C28x I2C driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup i2c_api I2C //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_i2c.h // // TITLE: Definitions for the I2C registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the I2C register offsets // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2COAR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2CIER register // //***************************************************************************** // enable // enable // interrupt enable // enable // enable // interrupt enable // enable //***************************************************************************** // // The following are defines for the bit fields in the I2CSTR register // //***************************************************************************** // flag bit // flag bit. // interrupt flag bit // flag bit. // flag bit. // bit. // bit. //***************************************************************************** // // The following are defines for the bit fields in the I2CDRR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2CSAR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2CDXR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2CMDR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2CISRC register // //***************************************************************************** // field //***************************************************************************** // // The following are defines for the bit fields in the I2CEMDR register // //***************************************************************************** // behav in Type1 //***************************************************************************** // // The following are defines for the bit fields in the I2CPSC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the I2CFFTX register // //***************************************************************************** // Enable // Clear //***************************************************************************** // // The following are defines for the bit fields in the I2CFFRX register // //***************************************************************************** // Clear //***************************************************************************** // // Defines for the API. // //***************************************************************************** //***************************************************************************** // // I2C Master commands. // //***************************************************************************** //***************************************************************************** // // I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(), // I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by // I2C_getInterruptStatus(). // //***************************************************************************** // // Helpful define to mask out the bits in the I2CSTR register that aren't // associated with interrupts. // //***************************************************************************** // // Flags for use as the stsFlags parameter of I2C_clearStatus() and to be // returned by I2C_getStatus(). // //***************************************************************************** //***************************************************************************** // //! I2C interrupts to be returned by I2C_getInterruptSource(). // //***************************************************************************** typedef enum { I2C_INTSRC_NONE, //!< No interrupt pending I2C_INTSRC_ARB_LOST, //!< Arbitration-lost interrupt I2C_INTSRC_NO_ACK, //!< NACK interrupt I2C_INTSRC_REG_ACCESS_RDY, //!< Register-access-ready interrupt I2C_INTSRC_RX_DATA_RDY, //!< Receive-data-ready interrupt I2C_INTSRC_TX_DATA_RDY, //!< Transmit-data-ready interrupt I2C_INTSRC_STOP_CONDITION, //!< Stop condition detected I2C_INTSRC_ADDR_SLAVE //!< Addressed as slave interrupt } I2C_InterruptSource; //***************************************************************************** // //! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel //! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel //! parameter, and returned by I2C_getTxFIFOStatus(). // //***************************************************************************** typedef enum { I2C_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty I2C_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty I2C_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full I2C_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full I2C_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full I2C_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full I2C_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full I2C_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full I2C_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full I2C_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full I2C_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full I2C_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full I2C_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full I2C_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full I2C_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full I2C_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full I2C_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full I2C_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full I2C_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full } I2C_TxFIFOLevel; //***************************************************************************** // //! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel //! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel //! parameter, and returned by I2C_getRxFIFOStatus(). // //***************************************************************************** typedef enum { I2C_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty I2C_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty I2C_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full I2C_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full I2C_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full I2C_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full I2C_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full I2C_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full I2C_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full I2C_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full I2C_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full I2C_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full I2C_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full I2C_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full I2C_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full I2C_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full I2C_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full I2C_FIFO_RX16 = 0x0010U, //!< Receive FIFO full I2C_FIFO_RXFULL = 0x0010U //!< Receive FIFO full } I2C_RxFIFOLevel; //***************************************************************************** // //! Values that can be passed to I2C_setBitCount() as the \e size parameter. // //***************************************************************************** typedef enum { I2C_BITCOUNT_1 = 1U, //!< 1 bit per data byte I2C_BITCOUNT_2 = 2U, //!< 2 bits per data byte I2C_BITCOUNT_3 = 3U, //!< 3 bits per data byte I2C_BITCOUNT_4 = 4U, //!< 4 bits per data byte I2C_BITCOUNT_5 = 5U, //!< 5 bits per data byte I2C_BITCOUNT_6 = 6U, //!< 6 bits per data byte I2C_BITCOUNT_7 = 7U, //!< 7 bits per data byte I2C_BITCOUNT_8 = 0U //!< 8 bits per data byte } I2C_BitCount; //***************************************************************************** // //! Values that can be passed to I2C_setAddressMode() as the \e mode parameter. // //***************************************************************************** typedef enum { I2C_ADDR_MODE_7BITS = 0x0000U, //!< 7-bit address I2C_ADDR_MODE_10BITS = 0x0100U //!< 10-bit address } I2C_AddressMode; //***************************************************************************** // //! Values that can be passed to I2C_setEmulationMode() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! If SCL is low, keep it low. If high, stop when it goes low again. I2C_EMULATION_STOP_SCL_LOW = 0x0000U, //! Continue I2C operation regardless I2C_EMULATION_FREE_RUN = 0x4000U } I2C_EmulationMode; //***************************************************************************** // //! Values that can be passed to I2C_initMaster() as the \e dutyCycle //! parameter. // //***************************************************************************** typedef enum { I2C_DUTYCYCLE_33, //!< Clock duty cycle is 33% I2C_DUTYCYCLE_50 //!< Clock duty cycle is 55% } I2C_DutyCycle; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks an I2C base address. //! //! \param base is the base address of the I2C instance used. //! //! This function determines if a I2C module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enables the I2C module. //! //! \param base is the base address of the I2C instance used. //! //! This function enables operation of the I2C module. //! //! \return None. // //***************************************************************************** static inline void I2C_enableModule(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x9U))) |= 0x20U; } //***************************************************************************** // //! Disables the I2C module. //! //! \param base is the base address of the I2C instance used. //! //! This function disables operation of the I2C module. //! //! \return None. // //***************************************************************************** static inline void I2C_disableModule(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x9U))) &= ~(0x20U); } //***************************************************************************** // //! Enables the transmit and receive FIFOs. //! //! \param base is the base address of the I2C instance used. //! //! This functions enables the transmit and receive FIFOs in the I2C. //! //! \return None. // //***************************************************************************** static inline void I2C_enableFIFO(uint32_t base) { // // Check the arguments. // ; // // Enable the FIFO. // (*((volatile uint16_t *)(base + 0x20U))) |= 0x4000U | 0x2000U; (*((volatile uint16_t *)(base + 0x21U))) |= 0x2000U; } //***************************************************************************** // //! Disables the transmit and receive FIFOs. //! //! \param base is the base address of the I2C instance used. //! //! This functions disables the transmit and receive FIFOs in the I2C. //! //! \return None. // //***************************************************************************** static inline void I2C_disableFIFO(uint32_t base) { // // Check the arguments. // ; // // Disable the FIFO. // (*((volatile uint16_t *)(base + 0x20U))) &= ~(0x4000U | 0x2000U); (*((volatile uint16_t *)(base + 0x21U))) &= ~0x2000U; } //***************************************************************************** // //! Sets the FIFO level at which interrupts are generated. //! //! \param base is the base address of the I2C instance used. //! \param txLevel is the transmit FIFO interrupt level, specified as //! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or //! \b I2C_FIFO_TX16. //! \param rxLevel is the receive FIFO interrupt level, specified as //! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or //! \b I2C_FIFO_RX16. //! //! This function sets the FIFO level at which transmit and receive interrupts //! are generated. The transmit FIFO interrupt flag will be set when the FIFO //! reaches a value less than or equal to \e txLevel. The receive FIFO //! flag will be set when the FIFO reaches a value greater than or equal to //! \e rxLevel. //! //! \return None. // //***************************************************************************** static inline void I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel, I2C_RxFIFOLevel rxLevel) { // // Check the arguments. // ; // // Set the FIFO interrupt levels. // (*((volatile uint16_t *)(base + 0x20U))) = ((*((volatile uint16_t *)(base + 0x20U))) & (~0x1FU)) | (uint16_t)txLevel; (*((volatile uint16_t *)(base + 0x21U))) = ((*((volatile uint16_t *)(base + 0x21U))) & (~0x1FU)) | (uint16_t)rxLevel; } //***************************************************************************** // //! Gets the FIFO level at which interrupts are generated. //! //! \param base is the base address of the I2C instance used. //! \param txLevel is a pointer to storage for the transmit FIFO level, //! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, //! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16. //! \param rxLevel is a pointer to storage for the receive FIFO level, //! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, //! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16. //! //! This function gets the FIFO level at which transmit and receive interrupts //! are generated. The transmit FIFO interrupt flag will be set when the FIFO //! reaches a value less than or equal to \e txLevel. The receive FIFO //! flag will be set when the FIFO reaches a value greater than or equal to //! \e rxLevel. //! //! \return None. // //***************************************************************************** static inline void I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel, I2C_RxFIFOLevel *rxLevel) { // // Check the arguments. // ; // // Extract the transmit and receive FIFO levels. // *txLevel = (I2C_TxFIFOLevel)((*((volatile uint16_t *)(base + 0x20U))) & 0x1FU); *rxLevel = (I2C_RxFIFOLevel)((*((volatile uint16_t *)(base + 0x21U))) & 0x1FU); } //***************************************************************************** // //! Get the transmit FIFO status //! //! \param base is the base address of the I2C instance used. //! //! This function gets the current number of words in the transmit FIFO. //! //! \return Returns the current number of words in the transmit FIFO specified //! as one of the following: //! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3, //! ..., or \b I2C_FIFO_TX16 // //***************************************************************************** static inline I2C_TxFIFOLevel I2C_getTxFIFOStatus(uint32_t base) { // // Check the arguments. // ; // // Get the current FIFO status // return((I2C_TxFIFOLevel)(((*((volatile uint16_t *)(base + 0x20U))) & 0x1F00U) >> 8U)); } //***************************************************************************** // //! Get the receive FIFO status //! //! \param base is the base address of the I2C instance used. //! //! This function gets the current number of words in the receive FIFO. //! //! \return Returns the current number of words in the receive FIFO specified //! as one of the following: //! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3, //! ..., or \b I2C_FIFO_RX16 // //***************************************************************************** static inline I2C_RxFIFOLevel I2C_getRxFIFOStatus(uint32_t base) { // // Check the arguments. // ; // // Get the current FIFO status // return((I2C_RxFIFOLevel)(((*((volatile uint16_t *)(base + 0x21U))) & 0x1F00U) >> 8U)); } //***************************************************************************** // //! Sets the address that the I2C Master places on the bus. //! //! \param base is the base address of the I2C instance used. //! \param slaveAddr 7-bit or 10-bit slave address //! //! This function configures the address that the I2C Master places on the bus //! when initiating a transaction. //! //! \return None. // //***************************************************************************** static inline void I2C_setSlaveAddress(uint32_t base, uint16_t slaveAddr) { // // Check the arguments. // ; ; (*((volatile uint16_t *)(base + 0x7U))) = slaveAddr; } //***************************************************************************** // //! Sets the slave address for this I2C module. //! //! \param base is the base address of the I2C Slave module. //! \param slaveAddr is the 7-bit or 10-bit slave address //! //! This function writes the specified slave address. //! //! The parameter \e slaveAddr is the value that is compared against the //! slave address sent by an I2C master. //! //! \return None. // //***************************************************************************** static inline void I2C_setOwnSlaveAddress(uint32_t base, uint16_t slaveAddr) { // // Check the arguments. // ; ; (*((volatile uint16_t *)(base + 0x0U))) = slaveAddr; } //***************************************************************************** // //! Indicates whether or not the I2C bus is busy. //! //! \param base is the base address of the I2C instance used. //! //! This function returns an indication of whether or not the I2C bus is busy. //! This function can be used in a multi-master environment to determine if the //! bus is free for another data transfer. //! //! \return Returns \b true if the I2C bus is busy; otherwise, returns //! \b false. // //***************************************************************************** static inline _Bool I2C_isBusBusy(uint32_t base) { // // Check the arguments. // ; return(((*((volatile uint16_t *)(base + 0x2U))) & 0x1000U) == 0x1000U); } //***************************************************************************** // //! Gets the current I2C module status. //! //! \param base is the base address of the I2C instance used. //! //! This function returns the status for the I2C module. //! //! \return The current module status, enumerated as a bit field of //! - \b I2C_STS_ARB_LOST - Arbitration-lost //! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK) //! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY) //! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready //! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready //! - \b I2C_STS_STOP_CONDITION - Stop condition detected //! - \b I2C_STS_BYTE_SENT - Byte transmit complete //! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected //! - \b I2C_STS_ADDR_SLAVE - Addressed as slave //! - \b I2C_STS_TX_EMPTY - Transmit shift register empty //! - \b I2C_STS_RX_FULL - Receive shift register full //! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset //! - \b I2C_STS_NACK_SENT - NACK was sent //! - \b I2C_STS_SLAVE_DIR- Addressed as slave transmitter // //***************************************************************************** static inline uint16_t I2C_getStatus(uint32_t base) { // // Check the arguments. // ; // // Return contents of the status register // return((*((volatile uint16_t *)(base + 0x2U)))); } //***************************************************************************** // //! Clears I2C status flags. //! //! \param base is the base address of the I2C instance used. //! \param stsFlags is a bit mask of the status flags to be cleared. //! //! This function clears the specified I2C status flags. The \e stsFlags //! parameter is the logical OR of the following values: //! - \b I2C_STS_ARB_LOST //! - \b I2C_STS_NO_ACK, //! - \b I2C_STS_REG_ACCESS_RDY //! - \b I2C_STS_RX_DATA_RDY //! - \b I2C_STS_STOP_CONDITION //! - \b I2C_STS_BYTE_SENT //! - \b I2C_STS_NACK_SENT //! - \b I2C_STS_SLAVE_DIR //! //! \note Note that some of the status flags returned by I2C_getStatus() cannot //! be cleared by this function. Some may only be cleared by hardware or a //! reset of the I2C module. //! //! \return None. // //***************************************************************************** static inline void I2C_clearStatus(uint32_t base, uint16_t stsFlags) { // // Check the arguments. // ; // // Write to the status registers to clear them. // (*((volatile uint16_t *)(base + 0x2U))) = stsFlags; } //***************************************************************************** // //! Controls the state of the I2C module. //! //! \param base is the base address of the I2C instance used. //! \param config is the command to be issued to the I2C module. //! //! This function is used to control the state of the master and slave send and //! receive operations. The \e config is a logical OR of the following options. //! //! One of the following four options: //! - \b I2C_MASTER_SEND_MODE - Master-transmitter mode //! - \b I2C_MASTER_RECEIVE_MODE - Master-receiver mode //! - \b I2C_SLAVE_SEND_MODE - Slave-transmitter mode //! - \b I2C_SLAVE_RECEIVE_MODE - Slave-receiver mode //! //! Any of the following: //! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count //! - \b I2C_START_BYTE_MODE - Use start byte mode //! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address //! //! \return None. // //***************************************************************************** static inline void I2C_setConfig(uint32_t base, uint16_t config) { // // Check the arguments. // ; // // Write the selected options to the mode register. // (*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~(0x400U | 0x200U | 0x80U | 0x10U | 0x8U)) | config; } //***************************************************************************** // //! Sets the data byte bit count the I2C module. //! //! \param base is the base address of the I2C instance used. //! \param size is the number of bits per data byte. //! //! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of //! bits per data byte. The default and maximum size is 8 bits. //! //! \return None. // //***************************************************************************** static inline void I2C_setBitCount(uint32_t base, I2C_BitCount size) { // // Check the arguments. // ; // // Write the selected options to the mode register. // (*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x7U) | (uint16_t)size; } //***************************************************************************** // //! Issues an I2C START condition. //! //! \param base is the base address of the I2C instance used. //! //! This function causes the I2C module to generate a start condition. This //! function is only valid when the I2C module specified by the \b base //! parameter is a master. //! //! \return None. // //***************************************************************************** static inline void I2C_sendStartCondition(uint32_t base) { // // Check the arguments. // ; // // Set the START condition bit. // (*((volatile uint16_t *)(base + 0x9U))) |= 0x2000U; } //***************************************************************************** // //! Issues an I2C STOP condition. //! //! \param base is the base address of the I2C instance used. //! //! This function causes the I2C module to generate a stop condition. This //! function is only valid when the I2C module specified by the \b base //! parameter is a master. //! //! To check on the status of the STOP condition, I2C_getStopConditionStatus() //! can be used. //! //! \return None. // //***************************************************************************** static inline void I2C_sendStopCondition(uint32_t base) { // // Check the arguments. // ; // // Set the STOP condition bit. // (*((volatile uint16_t *)(base + 0x9U))) |= 0x800U; } //***************************************************************************** // //! Issues a no-acknowledge (NACK) bit. //! //! \param base is the base address of the I2C instance used. //! //! This function causes the I2C module to generate a NACK bit. This is only //! applicable when the I2C module is acting as a receiver. //! //! \return None. // //***************************************************************************** static inline void I2C_sendNACK(uint32_t base) { // // Check the arguments. // ; // // Set the NACK mode bit. // (*((volatile uint16_t *)(base + 0x9U))) |= 0x8000U; } //***************************************************************************** // //! Receives a byte that has been sent to the I2C. //! //! \param base is the base address of the I2C instance used. //! //! This function reads a byte of data from the I2C Data Receive Register. //! //! \return Returns the byte received from by the I2C cast as an uint16_t. // //***************************************************************************** static inline uint16_t I2C_getData(uint32_t base) { // // Check the arguments. // ; // // Return the contents of the receive register. // return((*((volatile uint16_t *)(base + 0x6U)))); } //***************************************************************************** // //! Transmits a byte from the I2C. //! //! \param base is the base address of the I2C instance used. //! \param data is the data to be transmitted from the I2C Master. //! //! This function places the supplied data into I2C Data Transmit Register. //! //! \return None. // //***************************************************************************** static inline void I2C_putData(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Place the data into the transmit register. // (*((volatile uint16_t *)(base + 0x8U))) = data; } //***************************************************************************** // //! Get stop condition status. //! //! \param base is the base address of the I2C instance used. //! //! This function reads and returns the stop condition bit status. //! //! \return Returns \b true if the STP bit has been set by the device to //! generate a stop condition when the internal data counter of the I2C module //! has reached 0. Returns \b false when the STP bit is zero. This bit is //! automatically cleared after the stop condition has been generated. // //***************************************************************************** static inline _Bool I2C_getStopConditionStatus(uint32_t base) { // // Check the arguments. // ; // // Check the stop condition bit and return appropriately. // return(((*((volatile uint16_t *)(base + 0x9U))) & 0x800U) != 0U); } //***************************************************************************** // //! Set number of bytes to be to transfer or receive when repeat mode is off. //! //! \param base is the base address of the I2C instance used. //! \param count is the value to be put in the I2C data count register. //! //! This function sets the number of bytes to transfer or receive when repeat //! mode is off. //! //! \return None. // //***************************************************************************** static inline void I2C_setDataCount(uint32_t base, uint16_t count) { // // Check the arguments. // ; // // Write the count value to the appropriate register. // (*((volatile uint16_t *)(base + 0x5U))) = count; } //***************************************************************************** // //! Sets the addressing mode to either 7-bit or 10-bit. //! //! \param base is the base address of the I2C instance used. //! \param mode is the address mode, 7-bit or 10-bit. //! //! This function configures the I2C module for either a 7-bit address //! (default) or a 10-bit address. The \e mode parameter configures the address //! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when //! \b I2C_ADDR_MODE_7BITS. //! //! \return None. // //***************************************************************************** static inline void I2C_setAddressMode(uint32_t base, I2C_AddressMode mode) { // // Check the arguments. // ; // // Write the appropriate value to the address expansion bit. // (*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x100U) | (uint16_t)mode; } //***************************************************************************** // //! Sets I2C emulation mode. //! //! \param base is the base address of the I2C instance used. //! \param mode is the emulation mode. //! //! This function sets the behavior of the I2C operation when an emulation //! suspend occurs. The \e mode parameter can be one of the following: //! //! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs, //! the I2C module stops immediately. If SCL is high, the I2C module waits //! until SCL becomes low and then stops. //! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a //! the suspend. //! //! \return None. // //***************************************************************************** static inline void I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode) { // // Check the arguments. // ; // // Write the desired emulation mode to the register. // (*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x4000U) | (uint16_t)mode; } //***************************************************************************** // //! Enables I2C loopback mode. //! //! \param base is the base address of the I2C instance used. //! //! This function enables loopback mode. This mode is only valid during master //! mode and is helpful during device testing as it causes data transmitted out //! of the data transmit register to be received in data receive register. //! //! \return None. // //***************************************************************************** static inline void I2C_enableLoopback(uint32_t base) { // // Check the arguments. // ; // // Set the bit that enables loopback mode. // (*((volatile uint16_t *)(base + 0x9U))) |= 0x40U; } //***************************************************************************** // //! Disables I2C loopback mode. //! //! \param base is the base address of the I2C instance used. //! //! This function disables loopback mode. Loopback mode is disabled by default //! after reset. //! //! \return None. // //***************************************************************************** static inline void I2C_disableLoopback(uint32_t base) { // // Check the arguments. // ; // // Clear the bit that enables loopback mode. // (*((volatile uint16_t *)(base + 0x9U))) &= ~0x40U; } //***************************************************************************** // //! Returns the current I2C interrupt source. //! //! \param base is the base address of the I2C instance used. //! //! This function returns the event that generated an I2C basic (non-FIFO) //! interrupt. The possible sources are the following: //! - \b I2C_INTSRC_NONE //! - \b I2C_INTSRC_ARB_LOST //! - \b I2C_INTSRC_NO_ACK //! - \b I2C_INTSRC_REG_ACCESS_RDY //! - \b I2C_INTSRC_RX_DATA_RDY //! - \b I2C_INTSRC_TX_DATA_RDY //! - \b I2C_INTSRC_STOP_CONDITION //! - \b I2C_INTSRC_ADDR_SLAVE //! //! Calling this function will result in hardware automatically clearing the //! current interrupt code and if ready, loading the next pending enabled //! interrupt. It will also clear the corresponding interrupt flag if the //! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or //! \b I2C_INTSRC_STOP_CONDITION. //! //! \note Note that this function differs from I2C_getInterruptStatus() in that //! it returns a single interrupt source. I2C_getInterruptSource() will return //! the status of all interrupt flags possible, including the flags that aren't //! necessarily enabled to generate interrupts. //! //! \return None. // //***************************************************************************** static inline I2C_InterruptSource I2C_getInterruptSource(uint32_t base) { // // Check the arguments. // ; // // Return the interrupt source value // return((I2C_InterruptSource)((*((volatile uint16_t *)(base + 0xAU))) & 0x7U)); } //***************************************************************************** // //! Initializes the I2C Master. //! //! \param base is the base address of the I2C instance used. //! \param sysclkHz is the rate of the clock supplied to the I2C module //! (SYSCLK) in Hz. //! \param bitRate is the rate of the master clock signal, SCL. //! \param dutyCycle is duty cycle of the SCL signal. //! //! This function initializes operation of the I2C Master by configuring the //! bus speed for the master. Note that the I2C module \b must be put into //! reset before calling this function. You can do this with the function //! I2C_disableModule(). //! //! A programmable prescaler in the I2C module divides down the input clock //! (rate specified by \e sysclkHz) to produce the module clock (calculated to //! be around 10 MHz in this function). That clock is then divided down further //! to configure the SCL signal to run at the rate specified by \e bitRate. The //! \e dutyCycle parameter determines the percentage of time high and time low //! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and //! \b I2C_DUTYCYCLE_50 for 50%. //! //! The peripheral clock is the system clock. This value is returned by //! SysCtl_getClock(), or it can be explicitly hard coded if it is //! constant and known (to save the code/execution overhead of a call to //! SysCtl_getClock()). //! //! \return None. // //***************************************************************************** extern void I2C_initMaster(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, I2C_DutyCycle dutyCycle); //***************************************************************************** // //! Enables I2C interrupt sources. //! //! \param base is the base address of the I2C instance used. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! This function enables the indicated I2C Master interrupt sources. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! The \e intFlags parameter is the logical OR of any of the following: //! //! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt //! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt //! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt //! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt //! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt //! - \b I2C_INT_STOP_CONDITION - Stop condition detected //! - \b I2C_INT_ADDR_SLAVE - Addressed as slave interrupt //! - \b I2C_INT_RXFF - RX FIFO level interrupt //! - \b I2C_INT_TXFF - TX FIFO level interrupt //! //! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO //! interrupt vector. All others are associated with the I2C basic interrupt. //! //! \return None. // //***************************************************************************** extern void I2C_enableInterrupt(uint32_t base, uint32_t intFlags); //***************************************************************************** // //! Disables I2C interrupt sources. //! //! \param base is the base address of the I2C instance used. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! This function disables the indicated I2C Slave interrupt sources. Only //! the sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! The \e intFlags parameter has the same definition as the \e intFlags //! parameter to I2C_enableInterrupt(). //! //! \return None. // //***************************************************************************** extern void I2C_disableInterrupt(uint32_t base, uint32_t intFlags); //***************************************************************************** // //! Gets the current I2C interrupt status. //! //! \param base is the base address of the I2C instance used. //! //! This function returns the interrupt status for the I2C module. //! //! \return The current interrupt status, enumerated as a bit field of //! - \b I2C_INT_ARB_LOST //! - \b I2C_INT_NO_ACK //! - \b I2C_INT_REG_ACCESS_RDY //! - \b I2C_INT_RX_DATA_RDY //! - \b I2C_INT_TX_DATA_RDY //! - \b I2C_INT_STOP_CONDITION //! - \b I2C_INT_ADDR_SLAVE //! - \b I2C_INT_RXFF //! - \b I2C_INT_TXFF //! //! \note This function will only return the status flags associated with //! interrupts. However, a flag may be set even if its corresponding interrupt //! is disabled. // //***************************************************************************** extern uint32_t I2C_getInterruptStatus(uint32_t base); //***************************************************************************** // //! Clears I2C interrupt sources. //! //! \param base is the base address of the I2C instance used. //! \param intFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified I2C interrupt sources are cleared, so that they no longer //! assert. This function must be called in the interrupt handler to keep the //! interrupt from being triggered again immediately upon exit. //! //! The \e intFlags parameter has the same definition as the \e intFlags //! parameter to I2C_enableInterrupt(). //! //! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO //! interrupt vector. All others are associated with the I2C basic interrupt. //! //! \note Also note that some of the status flags returned by //! I2C_getInterruptStatus() cannot be cleared by this function. Some may only //! be cleared by hardware or a reset of the I2C module. //! //! \return None. // //***************************************************************************** extern void I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: lin.h // // TITLE: C28x LIN driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup lin_api LIN //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_lin.h // // TITLE: Definitions for the LIN registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the LIN register offsets // //***************************************************************************** // Register // Register 0 // Register 1 // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the SCIGCR0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIGCR1 register // //***************************************************************************** // bit // be set to 1 for SCI mode. // and SCI clock enable // mode) // control(LIN mode) // control (LIN mode) // communication (LIN mode) //***************************************************************************** // // The following are defines for the bit fields in the SCIGCR2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCISETINT register // //***************************************************************************** // (SCI compatible mode) // only) // Signal Interrupt (LIN only) // Signals Interrupt (LIN only) // only) // Interrupt (LIN only) // Inconsistent-Synch-Field-Error Interrupt (LIN only) // (LIN only) // Interrupt (LIN only) // only) //***************************************************************************** // // The following are defines for the bit fields in the SCICLEARINT register // //***************************************************************************** // (SCI compatible mode // only) // Signal Interrupt (LIN only) // Signals Interrupt (LIN only) // (LIN only) // Interrupt (LIN only) // Inconsistent-Synch-Field-Error Interrupt (LIN only) // Interrupt (LIN only) // Interrupt (LIN only) // (LIN only) //***************************************************************************** // // The following are defines for the bit fields in the SCISETINTLVL register // //***************************************************************************** // Level (SCI compatible mode) // (LIN only) // Signal Interrupt Level (LIN only) // Signals // Level // Level // Level (LIN only) // Level // Level // Interrupt Level (LIN only) // Inconsistent-Synch-Field-Error Interrupt Level // Level (LIN only) // Interrupt Level (LIN only) // Level(LIN only) //***************************************************************************** // // The following are defines for the bit fields in the SCICLEARINTLVL register // //***************************************************************************** // Level (SCI compatible mode) // (LIN only) // Signal Interrupt Level (LIN // only) // Signals // Level // Level. // Level (LIN only) // Level // Level // Interrupt Level (LIN only) // Inconsistent-Synch-Field-Error // Interrupt Level (LIN only) // Interrupt Level (LIN only) // Level (LIN only) //***************************************************************************** // // The following are defines for the bit fields in the SCIFLR register // //***************************************************************************** // compatible mode) // (SCI compatible mode) // (LIN only) // Flag (LIN only) // Signals Flag (LIN only) // Select // (LIN only) // only) // Error Flag (LIN only) // only) // only) //***************************************************************************** // // The following are defines for the bit fields in the SCIINTVECT0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIINTVECT1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIFORMAT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the BRSR register // //***************************************************************************** // Select //***************************************************************************** // // The following are defines for the bit fields in the SCIED register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIRD register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCITD register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIPIO0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIPIO2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LINCOMP register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LINRD0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LINRD1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LINMASK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LINID register // //***************************************************************************** // (LIN only) //***************************************************************************** // // The following are defines for the bit fields in the LINTD0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LINTD1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MBRSR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the IODFTCTRL register // //***************************************************************************** // Pin Enable // (SCI compatibility mode) // compatibility mode) // compatibility mode) // Error Enable (LIN mode) // mode) // (LIN mode) //***************************************************************************** // // The following are defines for the bit fields in the LIN_GLB_INT_EN register // //***************************************************************************** // LIN INT0 // LIN INT1 //***************************************************************************** // // The following are defines for the bit fields in the LIN_GLB_INT_FLG register // //***************************************************************************** // INT0 // INT1 //***************************************************************************** // // The following are defines for the bit fields in the LIN_GLB_INT_CLR register // //***************************************************************************** // for LIN INT0 // for LIN INT1 //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** // // The IO DFT Enable Key // // // LIN Wakeup Signal Key // // // LIN Parity ID Masks // //***************************************************************************** // // Definitions for the intFlags parameter of LIN_enableInterrupt(), // LIN_disableInterrupt(), LIN_clearInterruptStatus(), // LIN_setInterruptLevel0() and LIN_setInterruptLevel1(). // //***************************************************************************** //***************************************************************************** // // Definitions for the return value of LIN_getInterruptStatus(). // //***************************************************************************** //!< signal //!< signals //!< Method Select //!< Error //***************************************************************************** // // Definitions for the return value of LIN_getInterruptLine0Offset() and // LIN_getInterruptLine1Offset(). // //***************************************************************************** //***************************************************************************** // // Definitions for the LIN errors parameter of LIN_enableModuleErrors() and // LIN_disableModuleErrors(). // //***************************************************************************** //***************************************************************************** // // Definitions for the SCI errors parameter of LIN_enableSCIModuleErrors() and // LIN_disableSCIModuleErrors(). // //***************************************************************************** //***************************************************************************** // // Definitions for the intFlags parameter of LIN_enableSCIInterrupt(), // LIN_disableSCIInterrupt(), LIN_clearSCIInterruptStatus(), // LIN_setSCIInterruptLevel0() and LIN_setSCIInterruptLevel1(). // //***************************************************************************** //***************************************************************************** // //! The following are defines for the \e type parameter of the //! LIN_enableExtLoopback() function. // //***************************************************************************** typedef enum { LIN_LOOPBACK_DIGITAL = 0U, //!< Digital Loopback Mode LIN_LOOPBACK_ANALOG = 2U //!< Analog Loopback Mode } LIN_LoopbackType; //***************************************************************************** // //! The following are defines for the \e path parameter of the //! LIN_enableExtLoopback() function. // //***************************************************************************** typedef enum { LIN_ANALOG_LOOP_NONE = 0U, //!< Default path for digital loopback mode LIN_ANALOG_LOOP_TX = 0U, //!< Analog loopback through transmit pin LIN_ANALOG_LOOP_RX = 1U //!< Analog loopback through receive pin } LIN_AnalogLoopback; //***************************************************************************** // //! The following are defines for the \e mode parameter of the //! LIN_setCommMode() function. // //***************************************************************************** typedef enum { //! Use the length indicated in the LENGTH field of the SCIFORMAT register LIN_COMM_LIN_USELENGTHVAL = 0x0000U, //! Use ID4 and ID5 to convey the length LIN_COMM_LIN_ID4ID5LENCTL = 0x0001U } LIN_CommMode; //***************************************************************************** // //! The following are defines for the \e mode parameter of the //! LIN_setSCICommMode() function. // //***************************************************************************** typedef enum { //! Idle-line mode is used LIN_COMM_SCI_IDLELINE = 0x0000U, //! Address bit mode is used LIN_COMM_SCI_ADDRBIT = 0x0001U } LIN_SCICommMode; //***************************************************************************** // //! The following are defines for the \e mode parameter of the LIN_setLINMode() //! function. // //***************************************************************************** typedef enum { LIN_MODE_LIN_SLAVE = 0x0000U, //!< The node is in slave mode LIN_MODE_LIN_MASTER = 0x0020U //!< The node is in master mode } LIN_LINMode; //***************************************************************************** // //! The following are defines for the \e line parameter of the //! LIN_enableGlobalInterrupt(), LIN_disableGlobalInterrupt(), //! LIN_clearGlobalInterruptStatus(), and LIN_getGlobalInterruptStatus() //! functions. // //***************************************************************************** typedef enum { LIN_INTERRUPT_LINE0 = 0x0U, //!< Interrupt line 0 LIN_INTERRUPT_LINE1 = 0x1U //!< Interrupt line 1 } LIN_InterruptLine; //***************************************************************************** // //! The following are defines for the \e type parameter of the //! LIN_setMessageFiltering() function. // //***************************************************************************** typedef enum { LIN_MSG_FILTER_IDBYTE = 0x0U, //!< LIN Message ID Byte Filtering LIN_MSG_FILTER_IDSLAVE = 0x1U //!< Slave Task ID Byte Filtering } LIN_MessageFilter; //***************************************************************************** // //! The following are defines for the \e type parameter of the //! LIN_setChecksumType() function. // //***************************************************************************** typedef enum { LIN_CHECKSUM_CLASSIC = 0x0U, //!< Checksum Classic LIN_CHECKSUM_ENHANCED = 0x1U //!< Checksum Enhanced } LIN_ChecksumType; //***************************************************************************** // //! The following are defines for the \e mode parameter of the //! LIN_setDebugSuspendMode() function. // //***************************************************************************** typedef enum { LIN_DEBUG_FROZEN = 0x0U, //!< Freeze module during debug LIN_DEBUG_COMPLETE = 0x1U //!< Complete Tx/Rx before Freezing } LIN_DebugMode; //***************************************************************************** // //! The following are defines for the \e mask parameter of the //! LIN_setPinSampleMask() function. // //***************************************************************************** typedef enum { //! No Pin Mask LIN_PINMASK_NONE = 0x0U, //! Invert Tx Pin value at T-bit center LIN_PINMASK_CENTER = 0x1U, //! Invert Tx Pin value at T-bit center + SCLK LIN_PINMASK_CENTER_SCLK = 0x2U, //! Invert Tx Pin value at T-bit center + 2 SCLK LIN_PINMASK_CENTER_2SCLK = 0x3U } LIN_PinSampleMask; //***************************************************************************** // //! The following are defines for the \e parity parameter of the //! LIN_enableSCIParity() function. // //***************************************************************************** typedef enum { LIN_SCI_PAR_ODD = 0x0U, //!< Odd parity LIN_SCI_PAR_EVEN = 0x1U //!< Even parity } LIN_SCIParityType; //***************************************************************************** // //! The following are defines for the \e number parameter of the //! LIN_setSCIStopBits() function. // //***************************************************************************** typedef enum { LIN_SCI_STOP_ONE = 0x0U, //!< Use One Stop bit LIN_SCI_STOP_TWO = 0x1U //!< Use Two Stop bits } LIN_SCIStopBits; //***************************************************************************** // // Prototypes for the LIN mode APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! //! Checks a LIN base address. //! //! \param base is the base address of the LIN controller. //! //! This function determines if a LIN controller base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Sets the LIN mode //! //! \param base is the LIN module base address //! \param mode is the desired mode (slave or master) //! //! In LIN mode only, this function sets the mode of the LIN mode to either //! slave or master. The \e mode parameter should be passed a value of //! \b LIN_MODE_LIN_SLAVE or \b LIN_MODE_LIN_MASTER to configure the mode of //! the LIN module specified by \e base. //! //! \return None. // //***************************************************************************** static inline void LIN_setLINMode(uint32_t base, LIN_LINMode mode) { // // Check the arguments. // ; // // Write the LIN mode to the appropriate register. // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & ~0x20U) | (uint16_t)mode; __edis(); } //***************************************************************************** // //! Set Maximum Baud Rate Prescaler //! //! \param base is the LIN module base address //! \param clock is the device system clock (Hz) //! //! In LIN mode only, this function is used to set the maximum baud rate //! prescaler used during synchronization phase of a slave module if the //! ADAPT bit is set. The maximum baud rate prescaler is used by the wakeup //! and idle timer counters for a constant 4 second expiration time relative //! to a 20kHz rate. //! //! \note Use LIN_enableAutomaticBaudrate() to set the ADAPT bit and enable //! automatic bit rate mod detection. //! //! \return None. // //***************************************************************************** static inline void LIN_setMaximumBaudRate(uint32_t base, uint32_t clock) { // // Check the arguments. // ; // // Calculate maximum baud rate prescaler // (*((volatile uint16_t *)(base + 0x7CU))) = (uint16_t)(clock / 20000U); } //***************************************************************************** // //! Set Message filtering Type //! //! \param base is the LIN module base address //! \param type is the mask filtering comparison type //! //! In LIN mode only, this function sets the message filtering type. The \e //! type parameter can be one of the following values: //! - \b LIN_MSG_FILTER_IDBYTE - Filtering uses LIN message ID Byte //! - \b LIN_MSG_FILTER_IDSLAVE - Filtering uses the Slave Task ID Byte //! //! \return None. // //***************************************************************************** static inline void LIN_setMessageFiltering(uint32_t base, LIN_MessageFilter type) { // // Check the arguments. // ; // // Sets the message filtering type // if (type == LIN_MSG_FILTER_IDBYTE) { (*((volatile uint16_t *)(base + 0x4U))) &= ~0x1000U; } else { (*((volatile uint16_t *)(base + 0x4U))) |= 0x1000U; } } //***************************************************************************** // //! Enable Parity mode. //! //! \param base is the LIN module base address //! //! In LIN mode only, this function enables the parity check. //! //! \return None. // //***************************************************************************** static inline void LIN_enableParity(uint32_t base) { // // Check the arguments. // ; // // Enable the parity mode // (*((volatile uint16_t *)(base + 0x4U))) |= 0x4U; } //***************************************************************************** // //! Disable Parity mode. //! //! \param base is the LIN module base address //! //! In LIN mode only, this function disables the parity check. //! //! \return None. // //***************************************************************************** static inline void LIN_disableParity(uint32_t base) { // // Check the arguments. // ; // // Disable the parity mode // (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x4U); } //***************************************************************************** // //! Generate Parity Identifier //! \param identifier is the LIN header ID byte //! //! In LIN mode only, this function generates the identifier parity bits and //! appends them to the identifier. //! //! \note An ID must be generated with parity before header generation in //! LIN master mode when parity is enabled using the function //! LIN_enableParity(). //! //! \return Returns the identifier appended with parity bits. // //***************************************************************************** static inline uint16_t LIN_generateParityID(uint16_t identifier) { uint16_t p0, p1, parityIdentifier; // // Calculate parity bits and generate updated identifier // p0 = ((identifier & (0x1U)) ^ ((identifier & (0x2U)) >> 1U) ^ ((identifier & (0x4U)) >> 2U) ^ ((identifier & (0x10U)) >> 4U)); p1 = !(((identifier & (0x2U)) >> 1U) ^ ((identifier & (0x8U)) >> 3U) ^ ((identifier & (0x10U)) >> 4U) ^ ((identifier & (0x20U)) >> 5U)); parityIdentifier = identifier | ((p0 << 6U) | (p1 << 7U)); return(parityIdentifier); } //***************************************************************************** // //! Set ID Byte //! //! \param base is the LIN module base address //! \param identifier is the LIN header ID byte //! //! In LIN mode only, this function sets the message ID byte. In master mode, //! writing to this ID initiates a header transmission. In slave task, this //! ID is used for message filtering when HGENCTRL is 0. //! //! \return None. // //***************************************************************************** static inline void LIN_setIDByte(uint32_t base, uint16_t identifier) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x70U))) = ((*((volatile uint16_t *)(base + 0x70U))) & ~(0xFFU)) | (identifier & 0xFFU); } //***************************************************************************** // //! Set ID-SlaveTask //! //! \param base is the LIN module base address //! \param identifier is the Received ID comparison ID //! //! In LIN mode only, this function sets the identifier to which the received //! ID of an incoming Header will be compared in order to decide whether a RX //! response, a TX response, or no action is required. //! //! \return None. // //***************************************************************************** static inline void LIN_setIDSlaveTask(uint32_t base, uint16_t identifier) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x70U))) = (((*((volatile uint16_t *)(base + 0x70U))) & ~(0xFF00U)) | ((identifier & 0xFFU) << 8U)); } //***************************************************************************** // //! Send LIN wakeup signal //! //! \param base is the LIN module base address //! //! In LIN mode only, this function sends the LIN wakeup signal to terminate //! the sleep mode of any LIN node connected to the bus. //! //! \return None. // //***************************************************************************** static inline void LIN_sendWakeupSignal(uint32_t base) { // // Check the arguments. // ; // // Set key in Byte 0 (MSB) of transmit buffer 0 register // __byte((int16_t *)(base + 0x74U + 0x3U),0) = (uint16_t)(0xF0U); // // Transmit TDO for wakeup // (*((volatile uint16_t *)(base + 0x8U))) |= 0x100U; } //***************************************************************************** // //! Enter LIN Sleep Mode. //! //! \param base is the LIN module base address //! //! In LIN mode only, this function puts the LIN module into a low-power, sleep //! mode. This can also be called to forcefully enter sleep when there is no //! activity on the bus. //! //! \note If this function is called while the receiver is actively receiving //! data and the wakeup interrupt is disabled, then the module will delay //! sleep mode from being entered until completion of reception. //! //! \return None. // //***************************************************************************** static inline void LIN_enterSleep(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x8U))) |= 0x1U; } //***************************************************************************** // //! Send Checksum Byte //! //! \param base is the LIN module base address //! //! In LIN mode only, this function enables the transmitter with extended //! frames to send a checkbyte. //! //! \return None. // //***************************************************************************** static inline void LIN_sendChecksum(uint32_t base) { __byte_peripheral_32((uint32_t *)(base + 0x8U)) |= 0x10000U; } //***************************************************************************** // //! Trigger Checksum Compare //! //! \param base is the LIN module base address //! //! In LIN mode only, this function enables the receiver for extended frames //! to trigger a checksum compare. //! //! \return None. // //***************************************************************************** static inline void LIN_triggerChecksumCompare(uint32_t base) { // // Check the arguments. // ; __byte_peripheral_32((uint32_t *)(base + 0x8U)) |= 0x20000U; } //***************************************************************************** // //! Check Tx buffer ready flag //! //! \param base is the LIN module base address //! //! In LIN mode only, this function checks to see if the Tx ready flag is set //! indicating that the Tx buffer(s) is/are ready to get another character. //! //! \return Returns \b true if the TX ready flag is set, else returns \b false // //***************************************************************************** static inline _Bool LIN_isTxReady(uint32_t base) { // // Check the arguments. // ; // // Read Tx Buffer flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x100U) == 0x100U); } //***************************************************************************** // //! Set LIN Frame Length //! //! \param base is the LIN module base address //! \param length is the number of bytes. //! //! In LIN mode only, this function sets the number of bytes in the response //! field. //! //! The \e length parameter must be in a range between 1 and 8. //! //! \return None. // //***************************************************************************** static inline void LIN_setFrameLength(uint32_t base, uint16_t length) { // // Check the arguments. // ; ; // // Clear and set frame length value // __byte_peripheral_32((uint32_t *)(base + 0x28U)) &= ~(0x70000U); __byte_peripheral_32((uint32_t *)(base + 0x28U)) |= ((((uint32_t)length - (uint32_t)1U) << 16U)); } //***************************************************************************** // //! Set LIN communication mode //! //! \param base is the LIN module base address //! \param mode is the selected communication mode //! //! In LIN mode only, this function is used to choose how the length of data is //! conveyed. This choice relates to the version of LIN being used. The \e mode //! parameter can have one of two values: //! - \b LIN_COMM_LIN_USELENGTHVAL will use the length set with the //! LIN_setFrameLength() function. //! - \b LIN_COMM_LIN_ID4ID5LENCTL will use ID4 and ID5 for length control. //! //! \return None. // //***************************************************************************** static inline void LIN_setCommMode(uint32_t base, LIN_CommMode mode) { // // Check the arguments. // ; // // Write communication mode selection to the appropriate bit. // (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & ~0x1U) | (uint16_t)mode; } //***************************************************************************** // //! Sets the transmit ID mask //! //! \param base is the LIN module base address //! \param mask is the mask value to be set //! //! In LIN mode only, this function sets the mask used for filtering an //! incoming ID message to determine if the TX ID flag should be set. //! //! \return None. // //***************************************************************************** static inline void LIN_setTxMask(uint32_t base, uint16_t mask) { // // Check the arguments. // ; // // Clear previous mask value and set new mask // (*((volatile uint16_t *)(base + 0x6CU))) &= ~(0xFFU); (*((volatile uint16_t *)(base + 0x6CU))) |= (mask & 0xFFU); } //***************************************************************************** // //! Sets the receive ID mask //! //! \param base is the LIN module base address //! \param mask is the mask value to be set //! //! In LIN mode only, this function sets the mask used for filtering an //! incoming ID message to determine if the ID RX flag should be set. //! //! \return None. // //***************************************************************************** static inline void LIN_setRxMask(uint32_t base, uint16_t mask) { // // Check the arguments. // ; // // Clear previous mask value and set new mask // __byte_peripheral_32((uint32_t *)(base + 0x6CU)) &= ~(0xFF0000U); __byte_peripheral_32((uint32_t *)(base + 0x6CU)) |= ((uint32_t)mask << 16U) & 0xFF0000U; } //***************************************************************************** // //! Gets the transmit ID mask //! //! \param base is the LIN module base address //! //! In LIN mode only, this function gets the mask used for filtering an //! incoming ID message to determine if the TX ID flag should be set. //! //! \return Returns the Transmit ID Mask. // //***************************************************************************** static inline uint16_t LIN_getTxMask(uint32_t base) { // // Check the arguments. // ; return((*((volatile uint16_t *)(base + 0x6CU))) & 0xFFU); } //***************************************************************************** // //! Gets the receive ID mask //! //! \param base is the LIN module base address //! //! In LIN mode only, this function gets the mask used for filtering an //! incoming ID message to determine if the ID RX flag should be set. //! //! \return Returns the Receive ID Mask. // //***************************************************************************** static inline uint16_t LIN_getRxMask(uint32_t base) { // // Check the arguments. // ; return((uint16_t)((__byte_peripheral_32((uint32_t *)(base + 0x6CU)) & 0xFF0000U) >> 16U)); } //***************************************************************************** // //! Check if Rx data is ready //! //! \param base is the LIN module base address //! //! In LIN mode only, checks to see if the Rx ready bit is set indicating that //! a valid message frame has been received. //! //! \return Returns \b true if the Rx ready flag is set, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isRxReady(uint32_t base) { // // Check the arguments. // ; // // Ready Rx ready flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x200U) == 0x200U); } //***************************************************************************** // //! Get last received identifier //! //! \param base is the LIN module base address //! //! In LIN mode only, this function gets the last received identifier. //! //! \return Returns the Received Identifier. // //***************************************************************************** static inline uint16_t LIN_getRxIdentifier(uint32_t base) { // // Check the arguments. // ; return((uint16_t)((__byte_peripheral_32((uint32_t *)(base + 0x70U)) & 0xFF0000U) >> 16U)); } //***************************************************************************** // //! Checks for Tx ID Match Received //! //! \param base is the LIN module base address //! //! In LIN mode only, this function checks if an ID is received with a TX match //! and no ID-parity error. //! //! \return Returns \b true if a valid ID is matched, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isTxMatch(uint32_t base) { // // Check the arguments. // ; // // Read Tx ID flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x2000U) == 0x2000U); } //***************************************************************************** // //! Checks for Rx ID Match Received //! //! \param base is the LIN module base address //! //! In LIN mode only, this function checks if an ID is received with a RX match //! and no ID-parity error. //! //! \return Returns \b true if a valid ID is matched, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isRxMatch(uint32_t base) { // // Check the arguments. // ; // // Read Rx ID flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x4000U) == 0x4000U); } //***************************************************************************** // //! Enable interrupts //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! In LIN mode only, this function enables the interrupts for the specified //! interrupt sources. //! //! The \e intFlags parameter can be set to the following value to set //! all the flag bits: //! - \b LIN_INT_ALL - All Interrupts //! //! To set individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_INT_WAKEUP - Wakeup //! - \b LIN_INT_TO - Time out //! - \b LIN_INT_TOAWUS - Time out after wakeup signal //! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals //! - \b LIN_INT_TX - Transmit buffer ready //! - \b LIN_INT_RX - Receive buffer ready //! - \b LIN_INT_ID - Received matching identifier //! - \b LIN_INT_PE - Parity error //! - \b LIN_INT_OE - Overrun error //! - \b LIN_INT_FE - Framing error //! - \b LIN_INT_NRE - No response error //! - \b LIN_INT_ISFE - Inconsistent sync field error //! - \b LIN_INT_CE - Checksum error //! - \b LIN_INT_PBE - Physical bus error //! - \b LIN_INT_BE - Bit error //! //! \return None. // //***************************************************************************** static inline void LIN_enableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; __byte_peripheral_32((uint32_t *)(base + 0xCU)) |= intFlags; } //***************************************************************************** // //! Disable interrupts //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! In LIN mode only, this function disables the interrupts for the specified //! interrupt sources. //! //! The \e intFlags parameter can be set to the following value to disable //! all the flag bits: //! - \b LIN_INT_ALL - All Interrupts //! //! To disable individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_INT_WAKEUP - Wakeup //! - \b LIN_INT_TO - Time out //! - \b LIN_INT_TOAWUS - Time out after wakeup signal //! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals //! - \b LIN_INT_TX - Transmit buffer ready //! - \b LIN_INT_RX - Receive buffer ready //! - \b LIN_INT_ID - Received matching identifier //! - \b LIN_INT_PE - Parity error //! - \b LIN_INT_OE - Overrun error //! - \b LIN_INT_FE - Framing error //! - \b LIN_INT_NRE - No response error //! - \b LIN_INT_ISFE - Inconsistent sync field error //! - \b LIN_INT_CE - Checksum error //! - \b LIN_INT_PBE - Physical bus error //! - \b LIN_INT_BE - Bit error //! //! \return None. // //***************************************************************************** static inline void LIN_disableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; __byte_peripheral_32((uint32_t *)(base + 0x10U)) |= intFlags; } //***************************************************************************** // //! Clear interrupt status //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of the interrupt sources to be cleared. //! //! In LIN mode only, this function clears the specified status flags. //! //! The \e intFlags parameter can be set to the following value to clear //! all the flag bits: //! - \b LIN_INT_ALL - All Interrupts //! //! To clear individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_INT_WAKEUP - Wakeup //! - \b LIN_INT_TO - Time out //! - \b LIN_INT_TOAWUS - Time out after wakeup signal //! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals //! - \b LIN_INT_TX - Transmit buffer ready //! - \b LIN_INT_RX - Receive buffer ready //! - \b LIN_INT_ID - Received matching identifier //! - \b LIN_INT_PE - Parity error //! - \b LIN_INT_OE - Overrun error //! - \b LIN_INT_FE - Framing error //! - \b LIN_INT_NRE - No response error //! - \b LIN_INT_ISFE - Inconsistent sync field error //! - \b LIN_INT_CE - Checksum error //! - \b LIN_INT_PBE - Physical bus error //! - \b LIN_INT_BE - Bit error //! //! \return None. // //***************************************************************************** static inline void LIN_clearInterruptStatus(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; // // Clear the status flags // __byte_peripheral_32((uint32_t *)(base + 0x1CU)) |= intFlags; } //***************************************************************************** // //! Set interrupt level to 0 //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of interrupt sources to be configured //! //! In LIN mode only, this function sets the specified interrupt sources to //! level 0. //! //! The \e intFlags parameter can be set to the following value to set //! all the flag bits: //! - \b LIN_INT_ALL - All Interrupts //! //! To set individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_INT_WAKEUP - Wakeup //! - \b LIN_INT_TO - Time out //! - \b LIN_INT_TOAWUS - Time out after wakeup signal //! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals //! - \b LIN_INT_TX - Transmit buffer ready //! - \b LIN_INT_RX - Receive buffer ready //! - \b LIN_INT_ID - Received matching identifier //! - \b LIN_INT_PE - Parity error //! - \b LIN_INT_OE - Overrun error //! - \b LIN_INT_FE - Framing error //! - \b LIN_INT_NRE - No response error //! - \b LIN_INT_ISFE - Inconsistent sync field error //! - \b LIN_INT_CE - Checksum error //! - \b LIN_INT_PBE - Physical bus error //! - \b LIN_INT_BE - Bit error //! //! \return None. // //***************************************************************************** static inline void LIN_setInterruptLevel0(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; // // Clear interrupt levels to 0 // __byte_peripheral_32((uint32_t *)(base + 0x18U)) |= intFlags; } //***************************************************************************** // //! Set interrupt level to 1 //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of interrupt sources to be configured //! //! In LIN mode only, this function sets the specified interrupt sources to //! level 1. //! //! The \e intFlags parameter can be set to the following value to set //! all the flag bits: //! - \b LIN_INT_ALL - All Interrupts //! //! To set individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_INT_WAKEUP - Wakeup //! - \b LIN_INT_TO - Time out //! - \b LIN_INT_TOAWUS - Time out after wakeup signal //! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals //! - \b LIN_INT_TX - Transmit buffer ready //! - \b LIN_INT_RX - Receive buffer ready //! - \b LIN_INT_ID - Received matching identifier //! - \b LIN_INT_PE - Parity error //! - \b LIN_INT_OE - Overrun error //! - \b LIN_INT_FE - Framing error //! - \b LIN_INT_NRE - No response error //! - \b LIN_INT_ISFE - Inconsistent sync field error //! - \b LIN_INT_CE - Checksum error //! - \b LIN_INT_PBE - Physical bus error //! - \b LIN_INT_BE - Bit error //! //! \return None. // //***************************************************************************** static inline void LIN_setInterruptLevel1(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; // // Set interrupt levels to 1 // __byte_peripheral_32((uint32_t *)(base + 0x14U)) |= intFlags; } //***************************************************************************** // //! Enable Module Errors for Testing //! //! \param base is the LIN module base address //! \param errors is the specified errors to be enabled //! //! In LIN mode only, this function enables the specified errors in the module //! for testing. The \e errors parameter can be a logical OR-ed result of the //! following values or \b LIN_ALL_ERRORS can be used to enable all of them: //! - \b LIN_BIT_ERROR - Simulates a bit error //! - \b LIN_BUS_ERROR - Simulates a physical bus error //! - \b LIN_CHECKSUM_ERROR - Simulates a checksum error //! - \b LIN_ISF_ERROR - Simulates an inconsistent synch field error //! //! \note To disable these errors, use the LIN_disableModuleErrors() function. //! //! \return None. // //***************************************************************************** static inline void LIN_enableModuleErrors(uint32_t base, uint32_t errors) { // // Check the arguments. // ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable write access // (*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) << 8U); // // Enable specified error bits // __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= errors; // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) << 8U); __edis(); } //***************************************************************************** // //! Disable Module Errors for Testing //! //! \param base is the LIN module base address //! \param errors is the specified errors to be disabled //! //! In LIN mode only, this function disables the specified errors in the module //! for testing. The \e errors parameter can be a logical OR-ed result of the //! following values or \b LIN_ALL_ERRORS can be used to disable all of them: //! - \b LIN_BIT_ERROR - Simulates a bit error //! - \b LIN_BUS_ERROR - Simulates a physical bus error //! - \b LIN_CHECKSUM_ERROR - Simulates a checksum error //! - \b LIN_ISF_ERROR - Simulates an inconsistent synch field error //! //! \return None. // //***************************************************************************** static inline void LIN_disableModuleErrors(uint32_t base, uint32_t errors) { // // Check the arguments. // ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable write access // (*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) << 8U); // // Disable specified error bits // __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(errors); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) << 8U); __edis(); } //***************************************************************************** // //! Enable Automatic Baudrate Adjustment //! //! \param base is the LIN module base address //! //! In LIN mode only, this function enables the automatic baudrate adjustment //! mode during the detection of the Synch Field. //! //! \note The baudrate selection register will be updated automatically by a //! slave node if this mode is enabled. //! //! \return None. // //***************************************************************************** static inline void LIN_enableAutomaticBaudrate(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x200U; __edis(); } //***************************************************************************** // //! Disable Automatic Baudrate Adjustment //! //! \param base is the LIN module base address //! //! In LIN mode only, this function disables the automatic baudrate adjustment //! mode during the detection of the Synch Field. This results in a fixed //! baud rate. //! //! \return None. // //***************************************************************************** static inline void LIN_disableAutomaticBaudrate(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x200U; __edis(); } //***************************************************************************** // //! Stops LIN Extended Frame Communication //! //! \param base is the LIN module base address //! //! In LIN mode only, this function stops the extended frame communication. //! Once stopped, the bit is automatically cleared. //! //! \note This function can only be called during extended frame communication. //! //! \return None. // //***************************************************************************** static inline void LIN_stopExtendedFrame(uint32_t base) { // // Check the arguments. // ; // // Set stop bit // (*((volatile uint16_t *)(base + 0x4U))) |= 0x2000U; } //***************************************************************************** // //! Set Checksum Type //! //! \param base is the LIN module base address //! \param type is the checksum type //! //! In LIN mode only, this function sets the checksum type. The \e type //! parameter can be one of the following two values: //! - \b LIN_CHECKSUM_CLASSIC - Checksum Classic //! - \b LIN_CHECKSUM_ENHANCED - Checksum Enhanced //! //! \return None. // //***************************************************************************** static inline void LIN_setChecksumType(uint32_t base, LIN_ChecksumType type) { // // Check the arguments. // ; if(type == LIN_CHECKSUM_ENHANCED) { (*((volatile uint16_t *)(base + 0x4U))) |= 0x800U; } else { (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x800U); } } //***************************************************************************** // //! Set Sync Break Extend and Delimiter //! //! \param base is the LIN module base address //! \param syncBreak is the sync break extend value //! \param delimiter is the sync delimiter value //! //! In LIN mode only, this function sets the 3-bit sync break extend value //! and the 2-bit sync delimiter compare value. //! //! The \e break parameter can be a value between 0 to 7. Details: //! - \b 0 - Sync Break has no additional T-bit //! - \b 1 - Sync Break has 1 additional T-bit //! - \b ... //! - \b 7 - Sync Break has 7 additional T-bits //! //! The \e delimiter parameter can be a value between 1 to 4. Details: //! - \b 1 - Delimiter has 1 T-bit //! - \b 2 - Delimiter has 2 T-bits //! - \b 3 - Delimiter has 3 T-bits //! - \b 4 - Delimiter has 4 T-bits //! //! \return None. // //***************************************************************************** static inline void LIN_setSyncFields(uint32_t base, uint16_t syncBreak, uint16_t delimiter) { // // Check the arguments. // ; ; ; // // Clear sync values and set new values // (*((volatile uint16_t *)(base + 0x60U))) &= ~((uint16_t)0x7U | (uint16_t)0x300U); (*((volatile uint16_t *)(base + 0x60U))) |= (syncBreak | ((delimiter - 1U) << 8U)); } //***************************************************************************** // // Prototypes for the SCI mode APIs. // //***************************************************************************** //***************************************************************************** // //! Enable SCI Mode //! //! \param base is the LIN module base address //! //! This function enables the LIN peripheral to function as a SCI. //! //! \return None. // //***************************************************************************** static inline void LIN_enableSCIMode(uint32_t base) { // // Check the arguments. // ; // // Enable SCI communications mode // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x40U; (*((volatile uint16_t *)(base + 0x4U))) |= 0x20U | 0x2U; __edis(); } //***************************************************************************** // //! Disable SCI Mode //! //! \param base is the LIN module base address //! //! This function disables the SCI mode of the LIN peripheral. //! //! \return None. // //***************************************************************************** static inline void LIN_disableSCIMode(uint32_t base) { // // Check the arguments. // ; // // Disable SCI communications mode // __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x20U | 0x2U); (*((volatile uint16_t *)(base + 0x4U))) |= 0x40U; __edis(); } //***************************************************************************** // //! Set SCI communication mode //! //! \param base is the LIN module base address //! \param mode is the selected communication mode //! //! In SCI mode only, this function is used to select between idle-line mode //! and address-bit mode. The \e mode parameter can have one of the following //! values: //! - \b LIN_COMM_SCI_IDLELINE - Idle-line mode. //! - \b LIN_COMM_SCI_ADDRBIT - Address-bit mode. //! //! \return None. // //***************************************************************************** static inline void LIN_setSCICommMode(uint32_t base, LIN_SCICommMode mode) { // // Check the arguments. // ; ; // // Write communication mode selection to the appropriate bit. // (*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) & ~0x1U) | (uint16_t)mode; } //***************************************************************************** // //! Enable SCI Parity mode. //! //! \param base is the LIN module base address //! \param parity is the SCI parity type //! //! In SCI mode only, this function enables the parity check and sets the //! parity type. The \e parity parameter can one of the following values: //! - \b LIN_SCI_PAR_ODD - Sets Odd parity //! - \b LIN_SCI_PAR_EVEN - Sets Even parity //! //! \return None. // //***************************************************************************** static inline void LIN_enableSCIParity(uint32_t base, LIN_SCIParityType parity) { // // Check the arguments. // ; ; // // Enable the parity mode // (*((volatile uint16_t *)(base + 0x4U))) |= 0x4U; // // Set the parity type // if(parity == LIN_SCI_PAR_ODD) { (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x8U); } else { (*((volatile uint16_t *)(base + 0x4U))) |= 0x8U; } } //***************************************************************************** // //! Disable SCI Parity mode. //! //! \param base is the LIN module base address //! //! In SCI mode only, this function disables the parity check. //! //! \return None. // //***************************************************************************** static inline void LIN_disableSCIParity(uint32_t base) { // // Check the arguments. // ; ; // // Disable the parity mode // (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x4U); } //***************************************************************************** // //! Set the number of stop bits for SCI //! //! \param base is the LIN module base address //! \param number is the number of stop bits //! //! In SCI mode only, this function sets the number of stop bits transmitted. //! The \e number parameter can be one of the following values: //! - \b LIN_SCI_STOP_ONE - Set one stop bit //! - \b LIN_SCI_STOP_TWO - Set two stop bits //! //! \return None. // //***************************************************************************** static inline void LIN_setSCIStopBits(uint32_t base, LIN_SCIStopBits number) { // // Check the arguments. // ; ; // // Set the number of stop bits // if(number == LIN_SCI_STOP_ONE) { (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x10U); } else { (*((volatile uint16_t *)(base + 0x4U))) |= 0x10U; } } //***************************************************************************** // //! Enable SCI Sleep mode. //! //! \param base is the LIN module base address //! //! In SCI mode only, this function enables the receive sleep mode //! functionality. //! //! \note The receiver still operates when the sleep mode is enabled, however, //! RXRDY is updated and SCIRD is loaded with new data only when an address //! frame is detected. //! //! \return None. // //***************************************************************************** static inline void LIN_enableSCISleepMode(uint32_t base) { // // Check the arguments. // ; ; // // Set sleep mode bit // (*((volatile uint16_t *)(base + 0x4U))) |= 0x100U; } //***************************************************************************** // //! Disable SCI Sleep mode. //! //! \param base is the LIN module base address //! //! In SCI mode only, this function disables the receive sleep mode //! functionality. //! //! \return None. // //***************************************************************************** static inline void LIN_disableSCISleepMode(uint32_t base) { // // Check the arguments. // ; ; // // Clear sleep mode bit // (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x100U); } //***************************************************************************** // //! Enter SCI Local Low-Power Mode //! //! \param base is the LIN module base address //! //! In SCI mode only, this function enters the SCI local low-power mode. //! //! \note If this function is called while the receiver is actively receiving //! data and the wakeup interrupt is disabled, then the module will delay //! sleep mode from being entered until completion of reception. //! //! \return None. // //***************************************************************************** static inline void LIN_enterSCILowPower(uint32_t base) { // // Check the arguments. // ; ; // // Set low power bit // (*((volatile uint16_t *)(base + 0x8U))) |= 0x1U; } //***************************************************************************** // //! Exit SCI Local Low-Power Mode //! //! \param base is the LIN module base address //! //! In SCI mode only, this function exits the SCI local low-power mode. //! //! \return None. // //***************************************************************************** static inline void LIN_exitSCILowPower(uint32_t base) { // // Check the arguments. // ; ; // // Clear low power bit // (*((volatile uint16_t *)(base + 0x8U))) &= ~0x1U; } //***************************************************************************** // //! Set SCI character length //! //! \param base is the LIN module base address //! \param numBits is the number of bits per character. //! //! In SCI mode only, this function sets the number of bits per character. //! //! The \e numBits parameter must be in a range between 1 and 8. //! //! \return None. // //***************************************************************************** static inline void LIN_setSCICharLength(uint32_t base, uint16_t numBits) { // // Check the arguments. // ; ; ; // // Set the number of bits per character // (*((volatile uint16_t *)(base + 0x28U))) = ((*((volatile uint16_t *)(base + 0x28U))) & ~0x1FU) | (uint16_t)(numBits - 1U); } //***************************************************************************** // //! Set SCI Frame Length //! //! \param base is the LIN module base address //! \param length is the number of characters //! //! In SCI mode only, this function sets the number of characters in the //! response field. //! //! The \e length parameter must be in a range between 1 and 8. //! //! \return None. // //***************************************************************************** static inline void LIN_setSCIFrameLength(uint32_t base, uint16_t length) { // // Check the arguments. // ; ; ; // // Set number of characters // __byte_peripheral_32((uint32_t *)(base + 0x28U)) = (__byte_peripheral_32((uint32_t *)(base + 0x28U)) & ~(0x70000U)) | (((uint32_t)length - (uint32_t)1U) << 16U); } //***************************************************************************** // //! Check if new SCI data is ready to be read //! //! \param base is the LIN module base address //! //! In SCI mode only, this function checks to see if the Rx ready bit is set //! indicating that a new data has been received. //! //! \return Returns \b true if the Rx ready flag is set, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isSCIDataAvailable(uint32_t base) { // // Check the arguments. // ; ; // // Read Rx Ready flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x200U) == 0x200U); } //***************************************************************************** // //! Check if Space is available in SCI Transmit Buffer //! //! \param base is the LIN module base address //! //! In SCI mode only, this function checks to see if the Tx ready flag is set //! indicating that the Tx buffer(s) is/are ready to get another character. //! //! \return Returns \b true if the TX ready flag is set, else returns \b false // //***************************************************************************** static inline _Bool LIN_isSCISpaceAvailable(uint32_t base) { // // Check the arguments. // ; ; // // Read Tx buffer flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x100U) == 0x100U); } //***************************************************************************** // //! Reads a SCI character without Blocking //! //! \param base is the LIN module base address //! \param emulation sets whether the data is being read by an emulator or not //! //! In SCI mode only, this function gets the byte of data received. The //! \e emulation parameter can have one of the following values: //! - \b true - Emulator is being used, the RXRDY flag won't be cleared //! - \b false - Emulator isn't being used, the RXRDY flag will be cleared //! automatically on read //! //! \note //! -# If the SCI receives data that is fewer than 8 bits in length, the //! data is left-justified and padded with trailing zeros. //! -# To determine if new data is available to read, use the function //! LIN_isSCIDataAvailable(). //! //! \return Returns the received data. // //***************************************************************************** static inline uint16_t LIN_readSCICharNonBlocking(uint32_t base, _Bool emulation) { // // Check the arguments. // ; ; // // Read specific data register // return(emulation ? ((*((volatile uint16_t *)(base + 0x30U))) & 0xFFU) : ((*((volatile uint16_t *)(base + 0x34U))) & 0xFFU)); } //***************************************************************************** // //! Reads a SCI character with Blocking //! //! \param base is the LIN module base address //! \param emulation sets whether the data is being read by an emulator or not //! //! In SCI mode only, this function gets the byte of data received. If new data //! isn't available, this function will wait until new data arrives. The //! \e emulation parameter can have one of the following values: //! - \b true - Emulator is being used, the RXRDY flag won't be cleared //! - \b false - Emulator isn't being used, the RXRDY flag will be cleared //! automatically on read //! //! \note If the SCI receives data that is fewer than 8 bits in length, the //! data is left-justified and padded with trailing zeros. //! //! \return Returns the received data. // //***************************************************************************** static inline uint16_t LIN_readSCICharBlocking(uint32_t base, _Bool emulation) { // // Check the arguments. // ; ; // // Wait until a character is available in buffer. // while(!LIN_isSCIDataAvailable(base)) { } // // Read specific data register // return(emulation ? ((*((volatile uint16_t *)(base + 0x30U))) & 0xFFU) : ((*((volatile uint16_t *)(base + 0x34U))) & 0xFFU)); } //***************************************************************************** // //! Sends a SCI character without blocking //! //! \param base is the LIN module base address //! \param data is the byte of data to be transmitted //! //! In SCI mode only, this function sets the byte of data to be transmitted //! without blocking. //! //! \note The transmit ready flag gets set when this buffer is ready to be //! loaded with another byte of data. Use LIN_isSCISpaceAvailable() to //! determine if space is available to write another character. //! //! \return None. // //***************************************************************************** static inline void LIN_writeSCICharNonBlocking(uint32_t base, uint16_t data) { // // Check the arguments. // ; ; ; // // Set the Tx Data // (*((volatile uint16_t *)(base + 0x38U))) = (data & 0xFFU); } //***************************************************************************** // //! Sends a SCI character with blocking //! //! \param base is the LIN module base address //! \param data is the byte of data to be transmitted //! //! In SCI mode only, this function sets the byte of data to be transmitted //! with blocking functionality. If the buffer isn't ready to get new data //! written to, this function will wait until space is available. //! //! \return None. // //***************************************************************************** static inline void LIN_writeSCICharBlocking(uint32_t base, uint16_t data) { // // Check the arguments. // ; ; ; // // Wait until space is available in the transmit buffer. // while(!LIN_isSCISpaceAvailable(base)) { } // // Set the Tx Data // (*((volatile uint16_t *)(base + 0x38U))) = (data & 0xFFU); } //***************************************************************************** // //! Enable SCI Module Errors for Testing //! //! \param base is the LIN module base address //! \param errors is the specified errors to be enabled //! //! In SCI mode only, this function enables the specified errors in the module //! for testing. The \e errors parameter can be a logical OR-ed result of the //! following values or \b LIN_SCI_ALL_ERRORS can be used to enable all of //! them: //! - \b LIN_SCI_FRAME_ERROR - Simulates a frame error //! - \b LIN_SCI_PARITY_ERROR - Simulates a parity error //! - \b LIN_SCI_BREAK_ERROR - Simulates a break detect error //! //! \note To disable these errors, use the LIN_disableSCIModuleErrors() //! function. //! //! \return None. // //***************************************************************************** static inline void LIN_enableSCIModuleErrors(uint32_t base, uint32_t errors) { // // Check the arguments. // ; ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable write access // (*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) << 8U); // // Enable specified error bits // __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= errors; // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) << 8U); __edis(); } //***************************************************************************** // //! Disable SCI Module Errors for Testing //! //! \param base is the LIN module base address //! \param errors is the specified errors to be disabled //! //! In SCI mode only, this function disables the specified errors in the module //! for testing. The \e errors parameter can be a logical OR-ed result of the //! following values or \b LIN_SCI_ALL_ERRORS can be used to enable all of //! them: //! - \b LIN_SCI_FRAME_ERROR - Simulates a frame error //! - \b LIN_SCI_PARITY_ERROR - Simulates a parity error //! - \b LIN_SCI_BREAK_ERROR - Simulates a break detect error //! //! \return None. // //***************************************************************************** static inline void LIN_disableSCIModuleErrors(uint32_t base, uint32_t errors) { // // Check the arguments. // ; ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable write access // (*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) << 8U); // // Disable specified error bits // __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(errors); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) << 8U); __edis(); } //***************************************************************************** // //! Enable SCI interrupts //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! In SCI mode only, this function enables the interrupts for the specified //! interrupt sources. //! //! The \e intFlags parameter can be set to the following value to set //! all the flag bits: //! - \b LIN_SCI_INT_ALL - All Interrupts //! //! To set individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_SCI_INT_BREAK - Break Detect //! - \b LIN_SCI_INT_WAKEUP - Wakeup //! - \b LIN_SCI_INT_TX - Transmit Buffer //! - \b LIN_SCI_INT_RX - Receive Buffer //! - \b LIN_SCI_INT_PARITY - Parity Error //! - \b LIN_SCI_INT_OVERRUN - Overrun Error //! - \b LIN_SCI_INT_FRAME - Framing Error //! //! \return None. // //***************************************************************************** static inline void LIN_enableSCIInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Set specified interrupts // __byte_peripheral_32((uint32_t *)(base + 0xCU)) |= intFlags; } //***************************************************************************** // //! Disable SCI interrupts //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! In SCI mode only, this function disables the interrupts for the specified //! interrupt sources. //! //! The \e intFlags parameter can be set to the following value to disable //! all the flag bits: //! - \b LIN_SCI_INT_ALL - All Interrupts //! //! To disable individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_SCI_INT_BREAK - Break Detect //! - \b LIN_SCI_INT_WAKEUP - Wakeup //! - \b LIN_SCI_INT_TX - Transmit Buffer //! - \b LIN_SCI_INT_RX - Receive Buffer //! - \b LIN_SCI_INT_PARITY - Parity Error //! - \b LIN_SCI_INT_OVERRUN - Overrun Error //! - \b LIN_SCI_INT_FRAME - Framing Error //! //! \return None. // //***************************************************************************** static inline void LIN_disableSCIInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Set specified interrupts to be cleared // __byte_peripheral_32((uint32_t *)(base + 0x10U)) |= intFlags; } //***************************************************************************** // //! Clear SCI interrupt status //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of the interrupt sources to be cleared. //! //! In SCI mode only, this function clears the specified status flags. //! //! The \e intFlags parameter can be set to the following value to clear //! all the flag bits: //! - \b LIN_SCI_INT_ALL - All Interrupts //! //! To clear individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_SCI_INT_BREAK - Break Detect //! - \b LIN_SCI_INT_WAKEUP - Wakeup //! - \b LIN_SCI_INT_TX - Transmit Buffer //! - \b LIN_SCI_INT_RX - Receive Buffer //! - \b LIN_SCI_INT_PARITY - Parity Error //! - \b LIN_SCI_INT_OVERRUN - Overrun Error //! - \b LIN_SCI_INT_FRAME - Framing Error //! //! \return None. // //***************************************************************************** static inline void LIN_clearSCIInterruptStatus(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Clear the status flags // __byte_peripheral_32((uint32_t *)(base + 0x1CU)) |= intFlags; } //***************************************************************************** // //! Set SCI interrupt level to 0 //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of interrupt sources to be configured //! //! In SCI mode only, this function sets the specified interrupt sources to //! level 0. //! //! The \e intFlags parameter can be set to the following value to set //! all the flag bits: //! - \b LIN_SCI_INT_ALL - All Interrupts //! //! To set individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_SCI_INT_BREAK - Break Detect //! - \b LIN_SCI_INT_WAKEUP - Wakeup //! - \b LIN_SCI_INT_TX - Transmit Buffer //! - \b LIN_SCI_INT_RX - Receive Buffer //! - \b LIN_SCI_INT_PARITY - Parity Error //! - \b LIN_SCI_INT_OVERRUN - Overrun Error //! - \b LIN_SCI_INT_FRAME - Framing Error //! //! \return None. // //***************************************************************************** static inline void LIN_setSCIInterruptLevel0(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Clear interrupt levels to 0 // __byte_peripheral_32((uint32_t *)(base + 0x18U)) |= intFlags; } //***************************************************************************** // //! Set SCI interrupt level to 1 //! //! \param base is the LIN module base address //! \param intFlags is the bit mask of interrupt sources to be configured //! //! In SCI mode only, this function sets the specified interrupt sources to //! level 1. //! //! The \e intFlags parameter can be set to the following value to set //! all the flag bits: //! - \b LIN_SCI_INT_ALL - All Interrupts //! //! To set individual flags, the \e intFlags parameter can be the logical //! OR of any of the following: //! - \b LIN_SCI_INT_BREAK - Break Detect //! - \b LIN_SCI_INT_WAKEUP - Wakeup //! - \b LIN_SCI_INT_TX - Transmit Buffer //! - \b LIN_SCI_INT_RX - Receive Buffer //! - \b LIN_SCI_INT_PARITY - Parity Error //! - \b LIN_SCI_INT_OVERRUN - Overrun Error //! - \b LIN_SCI_INT_FRAME - Framing Error //! //! \return None. // //***************************************************************************** static inline void LIN_setSCIInterruptLevel1(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; ; // // Set interrupt levels to 1 // __byte_peripheral_32((uint32_t *)(base + 0x14U)) |= intFlags; } //***************************************************************************** // //! Check if SCI Receiver is Idle //! //! \param base is the LIN module base address //! //! In SCI mode only, this function checks if the receiver is in an idle state. //! //! \return Returns \b true if the state is idle, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isSCIReceiverIdle(uint32_t base) { // // Check the arguments. // ; ; // // Read Rx Idle flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x4U) == 0U); } //***************************************************************************** // //! Gets the SCI Transmit Frame Type //! //! \param base is the LIN module base address //! //! In SCI mode only, this function gets the transmit frame type which can be //! either data or an address. //! //! \return Returns \b true if the frame will be an address, and returns //! \b false if the frame will be data. // //***************************************************************************** static inline _Bool LIN_getSCITxFrameType(uint32_t base) { // // Check the arguments. // ; ; // // Read Tx Wake flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x400U) == 0x400U); } //***************************************************************************** // //! Gets the SCI Receiver Frame Type //! //! \param base is the LIN module base address //! //! In SCI mode only, this function gets the receiver frame type which can be //! either an address or not an address. //! //! \return Returns \b true if the frame is an address, and returns //! \b false if the frame isn't an address. // //***************************************************************************** static inline _Bool LIN_getSCIRxFrameType(uint32_t base) { // // Check the arguments. // ; ; // // Read Rx Wake flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x1000U) == 0x1000U); } //***************************************************************************** // //! Check if SCI Detected a Break Condition //! //! \param base is the LIN module base address //! //! In SCI mode only, this function checks if the module detected a break //! condition on the Rx pin. //! //! \return Returns \b true if break detected, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isSCIBreakDetected(uint32_t base) { // // Check the arguments. // ; ; // // Read Break condition flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x1U) == 0x1U); } //***************************************************************************** // // Prototypes for the LIN and SCI mode APIs. // //***************************************************************************** //***************************************************************************** // //! Enables the LIN module. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function sets the RESET bit of the SCIGCR0 //! register. Registers in this module are not writable until this has been //! done. Additionally, the transmit and receive pin control functionality is //! enabled. //! //! \return None. // //***************************************************************************** static inline void LIN_enableModule(uint32_t base) { // // Check the arguments. // ; __eallow(); // // Set reset bit. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x1U; // // Enable TX and RX pin control functionality // (*((volatile uint16_t *)(base + 0x3CU))) |= (0x2U | 0x4U); __edis(); } //***************************************************************************** // //! Disable the LIN module. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function clears the RESET bit of the SCIGCR0 //! register. Registers in this module are not writable when this bit is //! cleared. Additionally, the transmit and receive pin control functionality //! is disabled. //! //! \return None. // //***************************************************************************** static inline void LIN_disableModule(uint32_t base) { // // Check the arguments. // ; __eallow(); // // Disable TX and RX pin control functionality // (*((volatile uint16_t *)(base + 0x3CU))) &= ~(0x2U | 0x4U); // // Clear reset bit. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x1U; __edis(); } //***************************************************************************** // //! Set Baud Rate Prescaler //! //! \param base is the LIN module base address //! \param prescaler is the 24-bit integer prescaler //! \param divider is the 4-bit fractional divider //! //! In LIN and SCI mode, this function is used to set the baudrate based on //! the \e prescaler and \e divider values. //! //! P = Prescaler \n //! M = Fractional Divider \n //! Bitrate = (SYSCLOCK) / ((P + 1 + M/16) * 16) \n //! //! \return None. // //***************************************************************************** static inline void LIN_setBaudRatePrescaler(uint32_t base, uint32_t prescaler, uint32_t divider) { // // Check the arguments. // ; ; ; // // Set baud rate prescaler and divider // __byte_peripheral_32((uint32_t *)(base + 0x2CU)) = (prescaler | (divider << 24U)); } //***************************************************************************** // //! Enable Transmit Data Transfer. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function enables the transfer of data from //! SCITD or TDy to the transmit shift register. //! //! \return None. // //***************************************************************************** static inline void LIN_enableDataTransmitter(uint32_t base) { // // Check the arguments. // ; // // Enable transmit bit // __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x2000000U; } //***************************************************************************** // //! Disable Transmit Data Transfer. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function disables the transfer of data from //! SCITD or TDy to the transmit shift register. //! //! \return None. // //***************************************************************************** static inline void LIN_disableDataTransmitter(uint32_t base) { // // Check the arguments. // ; // // Disable transmit bit // __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x2000000U); } //***************************************************************************** // //! Enable Receive Data Transfer. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function enables the receiver to transfer data //! from the shift buffer register to the receive buffer or multi-buffer. //! //! \return None. // //***************************************************************************** static inline void LIN_enableDataReceiver(uint32_t base) { // // Check the arguments. // ; // // Enable receive bit // __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x1000000U; } //***************************************************************************** // //! Disable Receive Data Transfer. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function disables the receiver to transfer data //! from the shift buffer register to the receive buffer or multi-buffer. //! //! \return None. // //***************************************************************************** static inline void LIN_disableDataReceiver(uint32_t base) { // // Check the arguments. // ; // // Disable receive bit // __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x1000000U); } //***************************************************************************** // //! Perform software reset. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function will reset the LIN state machine and //! clear all pending flags. It is required to call this function after a //! wakeup signal has been sent. //! //! To enter the reset state separately, use LIN_enterSoftwareReset(). To come //! out of reset, use LIN_exitSoftwareReset(). //! //! \return None. // //***************************************************************************** static inline void LIN_performSoftwareReset(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x80U); (*((volatile uint16_t *)(base + 0x4U))) |= 0x80U; } //***************************************************************************** // //! Put LIN into its reset state. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function will reset the LIN state machine and //! clear all pending flags. It is required to call this function after a //! wakeup signal has been sent. When in this state, changes to the //! configuration of this module may be made. //! //! To take LIN out of the reset state and back into the ready state, use //! LIN_exitSoftwareReset(). //! //! \return None. // //***************************************************************************** static inline void LIN_enterSoftwareReset(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x4U))) &= ~(0x80U); } //***************************************************************************** // //! Put LIN into its ready state. //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function will put LIN into its ready state. //! Transmission and reception can be done in this state. While in the ready //! state, configuration of the module should not be changed. //! //! To put the module into its reset state, use LIN_enterSoftwareReset(). //! //! \return None. // //***************************************************************************** static inline void LIN_exitSoftwareReset(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x4U))) |= 0x80U; } //***************************************************************************** // //! Check if Bus is Busy //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function checks if the receiver bus is busy //! receiving a frame. //! //! \return Returns \b true if the bus is busy, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isBusBusy(uint32_t base) { // // Check the arguments. // ; // // Read Bus busy flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x8U) == 0x8U); } //***************************************************************************** // //! Check if the Transmit Buffer is Empty //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function checks if the transmit buffer is empty //! or not. //! //! \return Returns \b true if the Tx buffer is empty, else returns \b false. // //***************************************************************************** static inline _Bool LIN_isTxBufferEmpty(uint32_t base) { // // Check the arguments. // ; // // Read Tx Empty Flag and return status // return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x800U) == 0x800U); } //***************************************************************************** // //! Enable External Loopback mode for self test //! //! \param base is the LIN module base address //! \param loopbackType is the loopback type (analog or digital) //! \param path sets the transmit or receive pin to be included in the //! communication path (Analog loopback mode only) //! //! In LIN and SCI mode, this function enables the external Loopback mode for //! self test. The \e loopbackType parameter can be one of the following //! values: //! - \b LIN_LOOPBACK_DIGITAL - Digital Loopback //! - \b LIN_LOOPBACK_ANALOG - Analog Loopback //! //! The \e path parameter is only applicable in analog loopback mode and can //! be one of the following values: //! - \b LIN_ANALOG_LOOP_NONE - Default option for digital loopback mode //! - \b LIN_ANALOG_LOOP_TX - Enables analog loopback through the Tx pin //! - \b LIN_ANALOG_LOOP_RX - Enables analog loopback through the Rx pin //! //! \return None. // //***************************************************************************** static inline void LIN_enableExtLoopback(uint32_t base, LIN_LoopbackType loopbackType, LIN_AnalogLoopback path) { // // Check the arguments. // ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable Loopback either in Analog or Digital Mode // (*((volatile uint16_t *)(base + 0x90U))) |= (((0xAU) << 8U) | (uint16_t)loopbackType | (uint16_t)path); __edis(); } //***************************************************************************** // //! Disable External Loopback mode for self test //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function disables the external Loopback mode. //! //! \note This function also resets the analog loopback communication path to //! the default transmit pin. //! //! \return None. // //***************************************************************************** static inline void LIN_disableExtLoopback(uint32_t base) { // // Check the arguments. // ; // //Disable Loopback Mode // __eallow(); (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U | 0x2U | 0x1U); __edis(); } //***************************************************************************** // //! Enable Internal Loopback mode for self test //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function enables the internal Loopback mode for //! self test. //! //! \return None. // //***************************************************************************** static inline void LIN_enableIntLoopback(uint32_t base) { // // Check the arguments. // ; // // Enable the internal loopback // __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x10000U; } //***************************************************************************** // //! Disable Internal Loopback mode for self test //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function disables the internal Loopback mode for //! self test. //! //! \return None. // //***************************************************************************** static inline void LIN_disableIntLoopback(uint32_t base) { // // Check the arguments. // ; // // Disable the internal loopback // __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x10000U); } //***************************************************************************** // //! Get Interrupt Flags Status //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function returns the interrupt status register. //! //! The following flags can be used to mask the value returned: //! - \b LIN_FLAG_BREAK - Break Detect Flag (SCI mode only) //! - \b LIN_FLAG_WAKEUP - Wake-up Flag //! - \b LIN_FLAG_IDLE - Receiver in Idle State (SCI mode only) //! - \b LIN_FLAG_BUSY - Busy Flag //! - \b LIN_FLAG_TO - Bus Idle Timeout Flag (LIN mode only) //! - \b LIN_FLAG_TOAWUS - Timeout after Wakeup Signal (LIN mode only) //! - \b LIN_FLAG_TOA3WUS - Timeout after 3 Wakeup Signals (LIN mode only) //! - \b LIN_FLAG_TXRDY - Transmitter Buffer Ready Flag //! - \b LIN_FLAG_RXRDY - Receiver Buffer Ready Flag //! - \b LIN_FLAG_TXWAKE - Transmitter Wakeup Method Select (SCI mode only) //! - \b LIN_FLAG_TXEMPTY - Transmitter Empty Flag //! - \b LIN_FLAG_RXWAKE - Receiver Wakeup Detect Flag //! - \b LIN_FLAG_TXID - Identifier on Transmit Flag (LIN mode only) //! - \b LIN_FLAG_RXID - Identifier on Receive Flag (LIN mode only) //! - \b LIN_FLAG_PE - Parity Error Flag //! - \b LIN_FLAG_OE - Overrun Error Flag //! - \b LIN_FLAG_FE - Framing Error Flag //! - \b LIN_FLAG_NRE - No-Response Error Flag (LIN mode only) //! - \b LIN_FLAG_ISFE - Inconsistent Synch Field Error Flag (LIN mode only) //! - \b LIN_FLAG_CE - Checksum Error Flag (LIN mode only) //! - \b LIN_FLAG_PBE - Physical Bus Error Flag (LIN mode only) //! - \b LIN_FLAG_BE - Bit Error Flag (LIN mode only) //! //! \return Returns the status flag register. // //***************************************************************************** static inline uint32_t LIN_getInterruptStatus(uint32_t base) { // // Check the arguments. // ; // // Read and return the flag register // return(__byte_peripheral_32((uint32_t *)(base + 0x1CU))); } //***************************************************************************** // //! Get the Interrupt Level //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function gets the interrupt level status for //! all interrupt sources. //! //! \return Returns the value of the interrupt level register. // //***************************************************************************** static inline uint32_t LIN_getInterruptLevel(uint32_t base) { // // Check the arguments. // ; // // Gets the interrupt levels for all sources // return(__byte_peripheral_32((uint32_t *)(base + 0x14U))); } //***************************************************************************** // //! Gets the Interrupt Vector Offset for Line 0 //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function gets the offset for interrupt line 0. //! A read to the specified line register updates its value to the next highest //! priority pending interrupt in the flag register and clears the flag //! corresponding to the offset that was read. //! //! \note The flags for the receive and the transmit interrupts cannot be //! cleared by reading the corresponding offset vector in this function. //! //! The following are values that can be returned: //! - \b LIN_VECT_NONE - No Interrupt //! - \b LIN_VECT_WAKEUP - Wakeup //! - \b LIN_VECT_ISFE - Inconsistent-sync-field Error //! - \b LIN_VECT_PE - Parity Error //! - \b LIN_VECT_ID - ID Interrupt //! - \b LIN_VECT_PBE - Physical Bus Error //! - \b LIN_VECT_FE - Frame Error //! - \b LIN_VECT_BREAK - Break detect //! - \b LIN_VECT_CE - Checksum Error //! - \b LIN_VECT_OE - Overrun Error //! - \b LIN_VECT_BE - Bit Error //! - \b LIN_VECT_RX - Receive Interrupt //! - \b LIN_VECT_TX - Transmit Interrupt //! - \b LIN_VECT_NRE - No-response Error //! - \b LIN_VECT_TOAWUS - Timeout after wakeup signal //! - \b LIN_VECT_TOA3WUS - Timeout after 3 wakeup signals //! - \b LIN_VECT_TO - Timeout (Bus Idle) //! //! \return Returns the interrupt vector offset for interrupt line 0. // //***************************************************************************** static inline uint16_t LIN_getInterruptLine0Offset(uint32_t base) { // // Check the arguments. // ; // // Get interrupt vector line offset // return((*((volatile uint16_t *)(base + 0x20U))) & 0x1FU); } //***************************************************************************** // //! Gets the Interrupt Vector Offset for Line 1 //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function gets the offset for interrupt line 1. //! A read to the specified line register updates its value to the next highest //! priority pending interrupt in the flag register and clears the flag //! corresponding to the offset that was read. //! //! \note The flags for the receive and the transmit interrupts cannot be //! cleared by reading the corresponding offset vector in this function. //! //! The following are values that can be returned: //! - \b LIN_VECT_NONE - No Interrupt //! - \b LIN_VECT_WAKEUP - Wakeup //! - \b LIN_VECT_ISFE - Inconsistent-sync-field Error //! - \b LIN_VECT_PE - Parity Error //! - \b LIN_VECT_ID - ID Interrupt //! - \b LIN_VECT_PBE - Physical Bus Error //! - \b LIN_VECT_FE - Frame Error //! - \b LIN_VECT_BREAK - Break detect //! - \b LIN_VECT_CE - Checksum Error //! - \b LIN_VECT_OE - Overrun Error //! - \b LIN_VECT_BE - Bit Error //! - \b LIN_VECT_RX - Receive Interrupt //! - \b LIN_VECT_TX - Transmit Interrupt //! - \b LIN_VECT_NRE - No-response Error //! - \b LIN_VECT_TOAWUS - Timeout after wakeup signal //! - \b LIN_VECT_TOA3WUS - Timeout after 3 wakeup signals //! - \b LIN_VECT_TO - Timeout (Bus Idle) //! //! \return Returns the interrupt vector offset for interrupt line 1. // //***************************************************************************** static inline uint16_t LIN_getInterruptLine1Offset(uint32_t base) { // // Check the arguments. // ; // // Get interrupt vector line offset // return((*((volatile uint16_t *)(base + 0x24U))) & 0x1FU); } //***************************************************************************** // //! Enable Multi-buffer Mode //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function enables the multi-buffer mode. //! //! \return None. // //***************************************************************************** static inline void LIN_enableMultibufferMode(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x4U))) |= 0x400U; } //***************************************************************************** // //! Disable Multi-buffer Mode //! //! \param base is the LIN module base address //! //! In LIN and SCI mode, this function disables the multi-buffer mode. //! //! \return None. // //***************************************************************************** static inline void LIN_disableMultibufferMode(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x4U))) &= ~0x400U; } //***************************************************************************** // //! Set Transmit Pin Delay //! //! \param base is the LIN module base address //! \param delay is number of clock delays for the Tx pin (0 to 7) //! //! In LIN and SCI mode, this function sets the delay by which the value on //! the transmit pin is delayed so that the value on the receive pin is //! asynchronous. //! //! \note This is not applicable to the Start bit. //! //! \return None. // //***************************************************************************** static inline void LIN_setTransmitDelay(uint32_t base, uint16_t delay) { // // Check the arguments. // ; ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable write access // (*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) << 8U); // // Clear delay value // __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(0x70000U); // // Set the delay value // __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= ((uint32_t)delay << 16U); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); __edis(); } //***************************************************************************** // //! Set Pin Sample Mask //! //! \param base is the LIN module base address //! \param mask is the pin sample mask to be set //! //! In LIN and SCI mode, this function sets sample number at which the transmit //! pin value that is being transmitted will be inverted to verify the //! receive pin samples correctly with the majority detection circuitry. //! The \e mask parameter can be one of the following values: //! - \b LIN_PINMASK_NONE - No mask //! - \b LIN_PINMASK_CENTER - Invert Tx Pin value at T-bit center //! - \b LIN_PINMASK_CENTER_SCLK - Invert Tx Pin value at T-bit center + SCLK //! - \b LIN_PINMASK_CENTER_2SCLK - Invert Tx Pin value at T-bit center + //! 2 SCLK //! //! \return None. // //***************************************************************************** static inline void LIN_setPinSampleMask(uint32_t base, LIN_PinSampleMask mask) { // // Check the arguments. // ; __eallow(); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); // // Enable write access // (*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) << 8U); // // Clear pin mask // __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(0x180000U); // // Set new pin mask value // __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= ((uint32_t)mask << 19U); // // Clear the IO DFT Enable Key // (*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U); __edis(); } //***************************************************************************** // //! Set the Debug Suspended Mode //! //! \param base is the LIN module base address //! \param mode is the debug mode //! //! In LIN and SCI mode, this function sets how the module operates when the //! program is suspended and being debugged with an emulator. The \e mode //! parameter can be one of the following values: //! - \b LIN_DEBUG_FROZEN - The module state machine is frozen; transmissions //! and LIN counters are halted until debug mode is exited. //! - \b LIN_DEBUG_COMPLETE - The module continues to operate until the //! current transmit and receive functions are complete. //! //! \return None. // //***************************************************************************** static inline void LIN_setDebugSuspendMode(uint32_t base, LIN_DebugMode mode) { // // Check the arguments. // ; // // Set the debug suspend mode type // if(mode == LIN_DEBUG_FROZEN) { __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x20000U); } else { __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x20000U; } } //***************************************************************************** // //! Enables a LIN global interrupt. //! //! \param base is the LIN module base address //! \param line is specified interrupt vector line //! //! In LIN and SCI mode, this function globally enables an interrupt //! corresponding to a specified interrupt line. The \e line parameter can be //! one of the following enumerated values: //! //! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0 //! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1 //! //! \return None. // //***************************************************************************** static inline void LIN_enableGlobalInterrupt(uint32_t base, LIN_InterruptLine line) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0xE0U))) |= 0x1U << (uint16_t)line; } //***************************************************************************** // //! Disables a LIN global interrupt. //! //! \param base is the LIN module base address //! \param line is specified interrupt vector line //! //! In LIN and SCI mode, this function globally disables an interrupt //! corresponding to a specified interrupt line. The \e line parameter can be //! one of the following enumerated values: //! //! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0 //! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1 //! //! \return None. // //***************************************************************************** static inline void LIN_disableGlobalInterrupt(uint32_t base, LIN_InterruptLine line) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0xE0U))) &= ~(0x1U << (uint16_t)line); } //***************************************************************************** // //! Clears a LIN global interrupt flag. //! //! \param base is the LIN module base address //! \param line is specified interrupt vector line //! //! In LIN and SCI mode, this function clears the global interrupt flag that //! corresponds to a specified interrupt line. The \e line parameter can be //! one of the following enumerated values: //! //! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0 //! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1 //! //! \return None. // //***************************************************************************** static inline void LIN_clearGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0xE8U))) |= 0x1U << (uint16_t)line; } //***************************************************************************** // //! Returns a LIN global interrupt flag status. //! //! \param base is the LIN module base address //! \param line is specified interrupt vector line //! //! In LIN and SCI mode, this function returns the status of a global interrupt //! flag that corresponds to a specified interrupt line. The \e line parameter //! can be one of the following enumerated values: //! //! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0 //! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1 //! //! \return Returns \b true if the interrupt flag is set. Return \b false if //! not. // //***************************************************************************** static inline _Bool LIN_getGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line) { // // Check the arguments. // ; // // Read the flag register and return true if the specified flag is set. // return(((*((volatile uint16_t *)(base + 0xE4U))) & (0x1U << (uint16_t)line)) == (0x1U << (uint16_t)line)); } //***************************************************************************** // //! Initializes the LIN Driver //! //! \param base is the LIN module base address //! //! This function initializes the LIN module. //! //! \return None. // //***************************************************************************** extern void LIN_initModule(uint32_t base); //***************************************************************************** // //! Send Data //! //! \param base is the LIN module base address //! \param data is the pointer to data to send //! //! In LIN mode only, this function sends a block of data pointed to by 'data'. //! The number of data to transmit must be set with LIN_setFrameLength() //! before. //! //! \return None. // //***************************************************************************** extern void LIN_sendData(uint32_t base, uint16_t *data); //***************************************************************************** // //! Read received data //! //! \param base is the LIN module base address //! \param data is the pointer to the data buffer //! //! In LIN mode only, this function reads a block of bytes and place it into //! the data buffer pointed to by 'data'. //! //! \return None. // //***************************************************************************** extern void LIN_getData(uint32_t base, uint16_t * const data); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: memcfg.h // // TITLE: C28x RAM config driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup memcfg_api MemCfg //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_memcfg.h // // TITLE: Definitions for the MEMCFG registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the MEMCFG register offsets // //***************************************************************************** // Register // Commit Register // Register // Register // Commit Register // Register // control Register // Register 0 // Register 1 // Register // Register // Status Register // Register // Commit Register // Register 0 // Register // Register // Status Register // Register // Commit Register // Register // Flag Register // Flag Set Register // Flag Clear Register // Interrupt Enable Register // Violation Address // Violation Address // Violation Address // Violation Address // Violation Address // Violation Address // Register // Set Register // Clear Register // Interrupt Enable Register // Violation Address // Violation Address // Violation Address // Register // Register // Clear Register // Address // Address // Address // Register // Register // Register // Address // Register // Value Register // Flag Status Register // Flag Clear Register // Flag Set Register // Enable Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the DXLOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DXCOMMIT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DXTEST register // //***************************************************************************** // for M0 RAM // for M1 RAM //***************************************************************************** // // The following are defines for the bit fields in the DXINIT register // //***************************************************************************** // for M0 RAM. // for M1 RAM. //***************************************************************************** // // The following are defines for the bit fields in the DXINITDONE register // //***************************************************************************** // M0 RAM. // M1 RAM. //***************************************************************************** // // The following are defines for the bit fields in the LSXLOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LSXCOMMIT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LSXMSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LSXCLAPGM register // //***************************************************************************** // data memory for CLA // data memory for CLA // data memory for CLA // data memory for CLA // data memory for CLA // data memory for CLA // data memory for CLA // data memory for CLA //***************************************************************************** // // The following are defines for the bit fields in the LSXACCPROT0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LSXACCPROT1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LSXTEST register // //***************************************************************************** // for LS0 RAM // for LS1 RAM // for LS2 RAM // for LS3 RAM // for LS4 RAM // for LS5 RAM // for LS6 RAM // for LS7 RAM //***************************************************************************** // // The following are defines for the bit fields in the LSXINIT register // //***************************************************************************** // for LS0 RAM. // for LS1 RAM. // for LS2 RAM. // for LS3 RAM. // for LS4 RAM. // for LS5 RAM. // for LS6 RAM. // for LS7 RAM. //***************************************************************************** // // The following are defines for the bit fields in the LSXINITDONE register // //***************************************************************************** // LS0 RAM. // LS1 RAM. // LS2 RAM. // LS3 RAM. // LS4 RAM. // LS5 RAM. // LS6 RAM. // LS7 RAM. //***************************************************************************** // // The following are defines for the bit fields in the GSXLOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GSXCOMMIT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GSXACCPROT0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GSXTEST register // //***************************************************************************** // for GS0 RAM // for GS1 RAM // for GS2 RAM // for GS3 RAM //***************************************************************************** // // The following are defines for the bit fields in the GSXINIT register // //***************************************************************************** // for GS0 RAM. // for GS1 RAM. // for GS2 RAM. // for GS3 RAM. //***************************************************************************** // // The following are defines for the bit fields in the GSXINITDONE register // //***************************************************************************** // GS0 RAM. // GS1 RAM. // GS2 RAM. // GS3 RAM. //***************************************************************************** // // The following are defines for the bit fields in the MSGXLOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MSGXCOMMIT register // //***************************************************************************** // COMMIT bit // COMMIT bit //***************************************************************************** // // The following are defines for the bit fields in the MSGXTEST register // //***************************************************************************** // Select // Select //***************************************************************************** // // The following are defines for the bit fields in the MSGXINIT register // //***************************************************************************** // CPUTOCLA1 MSG RAM // CLA1TOCPU MSG RAM //***************************************************************************** // // The following are defines for the bit fields in the MSGXINITDONE register // //***************************************************************************** // to CLA1 MSG RAM // CLA1 to CPU MSG RAM //***************************************************************************** // // The following are defines for the bit fields in the NMAVFLG register // //***************************************************************************** // Violation Flag // Violation Flag // Violation Flag // Violation Flag // Violation Flag // Violation Flag // Violation Flag //***************************************************************************** // // The following are defines for the bit fields in the NMAVSET register // //***************************************************************************** // Violation Flag Set // Violation Flag Set // Violation Flag Set // Violation Flag Set // Violation Flag Set // Violation Flag Set // Violation Flag Set //***************************************************************************** // // The following are defines for the bit fields in the NMAVCLR register // //***************************************************************************** // Violation Flag Clear // Violation Flag Clear // Violation Flag Clear // Violation Flag Clear // Violation Flag Clear // Violation Flag Clear // Violation Flag Clear //***************************************************************************** // // The following are defines for the bit fields in the NMAVINTEN register // //***************************************************************************** // Violation Interrupt Enable // Violation Interrupt Enable // Violation Interrupt Enable // Violation Interrupt Enable // Violation Interrupt Enable // Violation Interrupt Enable //***************************************************************************** // // The following are defines for the bit fields in the MAVFLG register // //***************************************************************************** // Violation Flag // Violation Flag // Violation Flag //***************************************************************************** // // The following are defines for the bit fields in the MAVSET register // //***************************************************************************** // Violation Flag Set // Violation Flag Set // Violation Flag Set //***************************************************************************** // // The following are defines for the bit fields in the MAVCLR register // //***************************************************************************** // Violation Flag Clear // Violation Flag Clear // Violation Flag Clear //***************************************************************************** // // The following are defines for the bit fields in the MAVINTEN register // //***************************************************************************** // Violation Interrupt Enable // Violation Interrupt Enable // Violation Interrupt Enable //***************************************************************************** // // The following are defines for the bit fields in the UCERRFLG register // //***************************************************************************** // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the UCERRSET register // //***************************************************************************** // Flag Set // Flag Set // Flag Set //***************************************************************************** // // The following are defines for the bit fields in the UCERRCLR register // //***************************************************************************** // Flag Clear // Flag Clear // Flag Clear //***************************************************************************** // // The following are defines for the bit fields in the CERRFLG register // //***************************************************************************** // Flag // Flag // Flag //***************************************************************************** // // The following are defines for the bit fields in the CERRSET register // //***************************************************************************** // Flag Set // Flag Set // Flag Set //***************************************************************************** // // The following are defines for the bit fields in the CERRCLR register // //***************************************************************************** // Flag Clear // Flag Clear // Flag Clear //***************************************************************************** // // The following are defines for the bit fields in the CEINTFLG register // //***************************************************************************** // exceeded threshold flag. //***************************************************************************** // // The following are defines for the bit fields in the CEINTCLR register // //***************************************************************************** // Exceeded Error Clear. //***************************************************************************** // // The following are defines for the bit fields in the CEINTSET register // //***************************************************************************** // exceeded flag set. //***************************************************************************** // // The following are defines for the bit fields in the CEINTEN register // //***************************************************************************** // Interrupt Enable. //***************************************************************************** // // The following are defines for the bit fields in the ROMWAITSTATE register // //***************************************************************************** // Control //***************************************************************************** // // The following are defines for the bit fields in the ROMPREFETCH register // //***************************************************************************** // Control //***************************************************************************** // // Useful defines used within the driver functions. Not intended for use by // application code. // //***************************************************************************** // Masks to decode RAM section defines. // Used for access violation functions. //***************************************************************************** // // Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(), // MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(), // MemCfg_setCLAMemType(), MemCfg_setLSRAMMasterSel(), MemCfg_getInitStatus() // as the ramSection(s) parameter. // //***************************************************************************** // DxRAM - Dedicated RAM config // LSxRAM - Local shared RAM config // GSxRAM - Global shared RAM config // MSGxRAM - Message RAM config // All sections //***************************************************************************** // // Values that can be passed to MemCfg_setProtection() as the protectMode // parameter. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to MemCfg_enableViolationInterrupt() // MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), // MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as // the intFlags parameter. They also make up the return value of // MemCfg_getViolationInterruptStatus(). // //***************************************************************************** //***************************************************************************** // // Values that can be passed to MemCfg_forceCorrErrorStatus(), // MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the // stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus(). // // Note that MEMCFG_CERR_CPUREAD is the only value below that has a // corresponding interrupt and may be used with the error functions that take // an intFlag(s) parameter. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to MemCfg_forceUncorrErrorStatus(), // MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the // stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus(). // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType //! parameter. // //***************************************************************************** typedef enum { MEMCFG_CLA_MEM_DATA, //!< Section is CLA data memory MEMCFG_CLA_MEM_PROGRAM //!< Section is CLA program memory } MemCfg_CLAMemoryType; //***************************************************************************** // //! Values that can be passed to MemCfg_setLSRAMMasterSel() as the \e masterSel //! parameter. // //***************************************************************************** typedef enum { MEMCFG_LSRAMMASTER_CPU_ONLY, //!< CPU is the master of the section MEMCFG_LSRAMMASTER_CPU_CLA1 //!< CPU and CLA1 share this section } MemCfg_LSRAMMasterSel; //***************************************************************************** // //! Values that can be passed to MemCfg_setTestMode() as the \e testMode //! parameter. // //***************************************************************************** typedef enum { //! Functional mode MEMCFG_TEST_FUNCTIONAL = 0, //! Writes allowed to data only MEMCFG_TEST_WRITE_DATA = 1, //! Writes allowed to ECC only (for DxRAM) MEMCFG_TEST_WRITE_ECC = 2, //! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM) MEMCFG_TEST_WRITE_PARITY = 2 } MemCfg_TestMode; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Sets the CLA memory type of the specified RAM section. //! //! \param ramSections is the logical OR of the sections to be configured. //! \param claMemType indicates data memory or program memory. //! //! This function sets the CLA memory type configuration of the RAM section. If //! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will //! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM //! section will be configured as CLA program memory. //! //! The \e ramSections parameter is an OR of the following indicators: //! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx. //! //! \note This API only applies to LSx RAM and has no effect if the CLA isn't //! master of the memory section. //! //! \sa MemCfg_setLSRAMMasterSel() //! //! \return None. // //***************************************************************************** static inline void MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType) { // // Check the arguments. // ; // // Write the CLA memory configuration to the appropriate register. Either // set or clear the bit that determines the function of the RAM section as // it relates to the CLA. // __eallow(); if(claMemType == MEMCFG_CLA_MEM_PROGRAM) { // Program memory (*((volatile uint32_t *)(0x0005F400U + 0x26U))) |= ramSections; } else { // Data memory (*((volatile uint32_t *)(0x0005F400U + 0x26U))) &= ~ramSections; } __edis(); } //***************************************************************************** // //! Enables individual RAM access violation interrupt sources. //! //! \param intFlags is a bit mask of the interrupt sources to be enabled. //! Can be a logical OR any of the following values: //! - \b MEMCFG_NMVIOL_CPUREAD - Non-master CPU read access //! - \b MEMCFG_NMVIOL_CPUWRITE - Non-master CPU write access //! - \b MEMCFG_NMVIOL_CPUFETCH - Non-master CPU fetch access //! - \b MEMCFG_NMVIOL_DMAWRITE - Non-master DMA write access //! - \b MEMCFG_NMVIOL_CLA1READ - Non-master CLA1 read access //! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access //! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access //! - \b MEMCFG_MVIOL_CPUFETCH - Master CPU fetch access //! - \b MEMCFG_MVIOL_CPUWRITE - Master CPU write access //! - \b MEMCFG_MVIOL_DMAWRITE - Master DMA write access //! //! This function enables the indicated RAM access violation interrupt sources. //! Only the sources that are enabled can be reflected to the processor //! interrupt; disabled sources have no effect on the processor. //! //! \return None. // //***************************************************************************** static inline void MemCfg_enableViolationInterrupt(uint32_t intFlags) { // // Enable the specified interrupts. // __eallow(); (*((volatile uint32_t *)(0x0005F4C0U + 0x6U))) |= intFlags & 0x00000FFFU; (*((volatile uint32_t *)(0x0005F4C0U + 0x26U))) |= (intFlags & 0x0000F000U) >> 12U; __edis(); } //***************************************************************************** // //! Disables individual RAM access violation interrupt sources. //! //! \param intFlags is a bit mask of the interrupt sources to be disabled. //! Can be a logical OR any of the following values: //! - \b MEMCFG_NMVIOL_CPUREAD //! - \b MEMCFG_NMVIOL_CPUWRITE //! - \b MEMCFG_NMVIOL_CPUFETCH //! - \b MEMCFG_NMVIOL_DMAWRITE //! - \b MEMCFG_NMVIOL_CLA1READ //! - \b MEMCFG_NMVIOL_CLA1WRITE //! - \b MEMCFG_NMVIOL_CLA1FETCH //! - \b MEMCFG_MVIOL_CPUFETCH //! - \b MEMCFG_MVIOL_CPUWRITE //! - \b MEMCFG_MVIOL_DMAWRITE //! //! This function disables the indicated RAM access violation interrupt //! sources. Only the sources that are enabled can be reflected to the //! processor interrupt; disabled sources have no effect on the processor. //! //! \note Note that only non-master violations may generate interrupts. //! //! \return None. // //***************************************************************************** static inline void MemCfg_disableViolationInterrupt(uint32_t intFlags) { // // Disable the specified interrupts. // __eallow(); (*((volatile uint32_t *)(0x0005F4C0U + 0x6U))) &= ~(intFlags & 0x00000FFFU); (*((volatile uint32_t *)(0x0005F4C0U + 0x26U))) &= ~((intFlags & 0x0000F000U) >> 12U); __edis(); } //***************************************************************************** // //! Gets the current RAM access violation status. //! //! This function returns the RAM access violation status. This function will //! return flags for both master and non-master access violations although only //! the non-master flags have the ability to cause the generation of an //! interrupt. //! //! \return Returns the current violation status, enumerated as a bit field of //! the values: //! - \b MEMCFG_NMVIOL_CPUREAD - Non-master CPU read access //! - \b MEMCFG_NMVIOL_CPUWRITE - Non-master CPU write access //! - \b MEMCFG_NMVIOL_CPUFETCH - Non-master CPU fetch access //! - \b MEMCFG_NMVIOL_DMAWRITE - Non-master DMA write access //! - \b MEMCFG_NMVIOL_CLA1READ - Non-master CLA1 read access //! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access //! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access //! - \b MEMCFG_MVIOL_CPUFETCH - Master CPU fetch access //! - \b MEMCFG_MVIOL_CPUWRITE - Master CPU write access //! - \b MEMCFG_MVIOL_DMAWRITE - Master DMA write access // //***************************************************************************** static inline uint32_t MemCfg_getViolationInterruptStatus(void) { uint32_t status; // // Read and return RAM access status flags. // status = ((*((volatile uint32_t *)(0x0005F4C0U + 0x0U)))) | ((*((volatile uint32_t *)(0x0005F4C0U + 0x20U))) << 12U); return(status); } //***************************************************************************** // //! Sets the RAM access violation status. //! //! \param intFlags is a bit mask of the access violation flags to be set. //! Can be a logical OR any of the following values: //! - \b MEMCFG_NMVIOL_CPUREAD //! - \b MEMCFG_NMVIOL_CPUWRITE //! - \b MEMCFG_NMVIOL_CPUFETCH //! - \b MEMCFG_NMVIOL_DMAWRITE //! - \b MEMCFG_NMVIOL_CLA1READ //! - \b MEMCFG_NMVIOL_CLA1WRITE //! - \b MEMCFG_NMVIOL_CLA1FETCH //! - \b MEMCFG_MVIOL_CPUFETCH //! - \b MEMCFG_MVIOL_CPUWRITE //! - \b MEMCFG_MVIOL_DMAWRITE //! //! This function sets the RAM access violation status. This function will //! set flags for both master and non-master access violations, and an //! interrupt will be generated if it is enabled. //! //! \return None. // //***************************************************************************** static inline void MemCfg_forceViolationInterrupt(uint32_t intFlags) { // // Shift and mask the flags appropriately and write them to the // corresponding SET register. // __eallow(); (*((volatile uint32_t *)(0x0005F4C0U + 0x2U))) = intFlags & 0x00000FFFU; (*((volatile uint32_t *)(0x0005F4C0U + 0x22U))) = (intFlags & 0x0000F000U) >> 12U; __edis(); } //***************************************************************************** // //! Clears RAM access violation flags. //! //! \param intFlags is a bit mask of the access violation flags to be cleared. //! Can be a logical OR any of the following values: //! - \b MEMCFG_NMVIOL_CPUREAD //! - \b MEMCFG_NMVIOL_CPUWRITE //! - \b MEMCFG_NMVIOL_CPUFETCH //! - \b MEMCFG_NMVIOL_DMAWRITE //! - \b MEMCFG_NMVIOL_CLA1READ //! - \b MEMCFG_NMVIOL_CLA1WRITE //! - \b MEMCFG_NMVIOL_CLA1FETCH //! - \b MEMCFG_MVIOL_CPUFETCH //! - \b MEMCFG_MVIOL_CPUWRITE //! - \b MEMCFG_MVIOL_DMAWRITE //! //! \return None. // //***************************************************************************** static inline void MemCfg_clearViolationInterruptStatus(uint32_t intFlags) { // // Clear the requested access violation flags. // __eallow(); (*((volatile uint32_t *)(0x0005F4C0U + 0x4U))) |= intFlags & 0x00000FFFU; (*((volatile uint32_t *)(0x0005F4C0U + 0x24U))) |= (intFlags & 0x0000F000U) >> 12U; __edis(); } //***************************************************************************** // //! Sets the correctable error threshold value. //! //! \param threshold is the correctable error threshold. //! //! This value sets the error-count threshold at which a correctable error //! interrupt is generated. That is when the error count register reaches the //! value specified by the \e threshold parameter, an interrupt is //! generated if it is enabled. //! //! \return None. // //***************************************************************************** static inline void MemCfg_setCorrErrorThreshold(uint32_t threshold) { // // Write the threshold value to the appropriate register. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x30U))) = threshold; __edis(); } //***************************************************************************** // //! Gets the correctable error count. //! //! \return Returns the number of correctable error have occurred. // //***************************************************************************** static inline uint32_t MemCfg_getCorrErrorCount(void) { // // Read and return the number of errors that have occurred. // return((*((volatile uint32_t *)(0x0005F500U + 0x2EU)))); } //***************************************************************************** // //! Enables individual RAM correctable error interrupt sources. //! //! \param intFlags is a bit mask of the interrupt sources to be enabled. Can //! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. //! //! This function enables the indicated RAM correctable error interrupt //! sources. Only the sources that are enabled can be reflected to the //! processor interrupt; disabled sources have no effect on the processor. //! //! \note Note that only correctable errors may generate interrupts. //! //! \return None. // //***************************************************************************** static inline void MemCfg_enableCorrErrorInterrupt(uint32_t intFlags) { // // Enable the specified interrupts. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x38U))) |= intFlags; __edis(); } //***************************************************************************** // //! Disables individual RAM correctable error interrupt sources. //! //! \param intFlags is a bit mask of the interrupt sources to be disabled. Can //! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. //! //! This function disables the indicated RAM correctable error interrupt //! sources. Only the sources that are enabled can be reflected to the //! processor interrupt; disabled sources have no effect on the processor. //! //! \note Note that only correctable errors may generate interrupts. //! //! \return None. // //***************************************************************************** static inline void MemCfg_disableCorrErrorInterrupt(uint32_t intFlags) { // // Disable the specified interrupts. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x38U))) &= ~(intFlags); __edis(); } //***************************************************************************** // //! Gets the current RAM correctable error interrupt status. //! //! \return Returns the current error interrupt status. Will return a value of //! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the //! function will return 0. // //***************************************************************************** static inline uint32_t MemCfg_getCorrErrorInterruptStatus(void) { // // Read and return correctable error interrupt flags. // return((*((volatile uint32_t *)(0x0005F500U + 0x32U)))); } //***************************************************************************** // //! Sets the RAM correctable error interrupt status. //! //! \param intFlags is a bit mask of the interrupt sources to be set. Can take //! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. //! //! This function sets the correctable error interrupt flag. //! //! \note Note that only correctable errors may generate interrupts. //! //! \return None. // //***************************************************************************** static inline void MemCfg_forceCorrErrorInterrupt(uint32_t intFlags) { // // Write the flags to the appropriate SET register. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x36U))) = intFlags; __edis(); } //***************************************************************************** // //! Clears the RAM correctable error interrupt status. //! //! \param intFlags is a bit mask of the interrupt sources to be cleared. Can //! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. //! //! This function clears the correctable error interrupt flag. //! //! \note Note that only correctable errors may generate interrupts. //! //! \return None. // //***************************************************************************** static inline void MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags) { // // Clear the requested flags. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x34U))) |= intFlags; __edis(); } //***************************************************************************** // //! Gets the current correctable RAM error status. //! //! \return Returns the current error status, enumerated as a bit field of //! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ // //***************************************************************************** static inline uint32_t MemCfg_getCorrErrorStatus(void) { // // Read and return RAM error status flags. // return((*((volatile uint32_t *)(0x0005F500U + 0x20U)))); } //***************************************************************************** // //! Gets the current uncorrectable RAM error status. //! //! \return Returns the current error status, enumerated as a bit field of //! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or //! \b MEMCFG_UCERR_CLA1READ. // //***************************************************************************** static inline uint32_t MemCfg_getUncorrErrorStatus(void) { // // Read and return RAM error status flags. // return((*((volatile uint32_t *)(0x0005F500U + 0x0U)))); } //***************************************************************************** // //! Sets the specified correctable RAM error status flag. //! //! \param stsFlags is a bit mask of the error sources. This parameter can be //! any of the following values: \b MEMCFG_CERR_CPUREAD, //! \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ. //! //! This function sets the specified correctable RAM error status flag. //! //! \return None. // //***************************************************************************** static inline void MemCfg_forceCorrErrorStatus(uint32_t stsFlags) { // // Write the flags to the appropriate SET register. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x22U))) = stsFlags; __edis(); } //***************************************************************************** // //! Sets the specified uncorrectable RAM error status flag. //! //! \param stsFlags is a bit mask of the error sources. This parameter can be //! any of the following values: \b MEMCFG_UCERR_CPUREAD, //! \b MEMCFG_UCERR_DMAREAD, or \b MEMCFG_UCERR_CLA1READ. //! //! This function sets the specified uncorrectable RAM error status flag. //! //! \return None. // //***************************************************************************** static inline void MemCfg_forceUncorrErrorStatus(uint32_t stsFlags) { // // Write the flags to the appropriate SET register. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x2U))) = stsFlags; __edis(); } //***************************************************************************** // //! Clears correctable RAM error flags. //! //! \param stsFlags is a bit mask of the status flags to be cleared. //! This parameter can be any of the \b MEMCFG_CERR_CPUREAD, //! \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ values. //! //! This function clears the specified correctable RAM error flags. //! //! \return None. // //***************************************************************************** static inline void MemCfg_clearCorrErrorStatus(uint32_t stsFlags) { // // Clear the requested flags. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x24U))) |= stsFlags; __edis(); } //***************************************************************************** // //! Clears uncorrectable RAM error flags. //! //! \param stsFlags is a bit mask of the status flags to be cleared. //! This parameter can be any of the \b MEMCFG_UCERR_CPUREAD, //! \b MEMCFG_UCERR_DMAREAD, or \b MEMCFG_UCERR_CLA1READ values. //! //! This function clears the specified uncorrectable RAM error flags. //! //! \return None. // //***************************************************************************** static inline void MemCfg_clearUncorrErrorStatus(uint32_t stsFlags) { // // Clear the requested flags. // __eallow(); (*((volatile uint32_t *)(0x0005F500U + 0x4U))) |= stsFlags; __edis(); } //***************************************************************************** // //! Locks the writes to the configuration of specified RAM sections. //! //! \param ramSections is the logical OR of the sections to be configured. //! //! This function locks writes to the access protection and master select //! configuration of a RAM section. That means calling MemCfg_setProtection() //! or MemCfg_setLSRAMMasterSel() for a locked RAM section will have no effect //! until MemCfg_unlockConfig() is called. //! //! The \e ramSections parameter is an OR of one of the following sets of //! indicators: //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL //! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. //! //! \return None. // //***************************************************************************** extern void MemCfg_lockConfig(uint32_t ramSections); //***************************************************************************** // //! Unlocks the writes to the configuration of a RAM section. //! //! \param ramSections is the logical OR of the sections to be configured. //! //! This function unlocks writes to the access protection and master select //! configuration of a RAM section that has been locked using //! MemCfg_lockConfig(). //! //! The \e ramSections parameter is an OR of one of the following sets of //! indicators: //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL //! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. //! //! \return None. // //***************************************************************************** extern void MemCfg_unlockConfig(uint32_t ramSections); //***************************************************************************** // //! Permanently locks writes to the configuration of a RAM section. //! //! \param ramSections is the logical OR of the sections to be configured. //! //! This function permanently locks writes to the access protection and master //! select configuration of a RAM section. That means calling //! MemCfg_setProtection() or MemCfg_setLSRAMMasterSel() for a locked RAM //! section will have no effect. To lock the configuration in a nonpermanent //! way, use MemCfg_lockConfig(). //! //! The \e ramSections parameter is an OR of one of the following sets of //! indicators: //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL //! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. //! //! \return None. // //***************************************************************************** extern void MemCfg_commitConfig(uint32_t ramSections); //***************************************************************************** // //! Sets the access protection mode of a single RAM section. //! //! \param ramSection is the RAM section to be configured. //! \param protectMode is the logical OR of the settings to be applied. //! //! This function sets the access protection mode of the specified RAM section. //! The mode is passed into the \e protectMode parameter as the logical OR of //! the following values: //! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch //! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write //! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write //! //! The \e ramSection parameter is one of the following indicators: //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx //! //! This function will have no effect if the associated registers have been //! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory //! is configured as CLA program memory. //! //! \return None. // //***************************************************************************** extern void MemCfg_setProtection(uint32_t ramSection, uint32_t protectMode); //***************************************************************************** // //! Sets the master of the specified RAM section. //! //! \param ramSection is the RAM section to be configured. //! \param masterSel is the sharing selection. //! //! This function sets the master select configuration of the RAM section. If //! the \e masterSel parameter is \b MEMCFG_LSRAMMASTER_CPU_ONLY, the RAM //! section passed into the \e ramSection parameter will be dedicated to the //! CPU. If \b MEMCFG_LSRAMMASTER_CPU_CLA1, the memory section will be shared //! between the CPU and the CLA. //! //! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0 //! through \b MEMCFG_SECT_LSx. //! //! This function will have no effect if the associated registers have been //! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). //! //! \note This API only applies to LSx RAM. //! //! \return None. // //***************************************************************************** extern void MemCfg_setLSRAMMasterSel(uint32_t ramSection, MemCfg_LSRAMMasterSel masterSel); //***************************************************************************** // //! Sets the test mode of the specified RAM section. //! //! \param ramSection is the RAM section to be configured. //! \param testMode is the test mode selected. //! //! This function sets the test mode configuration of the RAM section. The //! \e testMode parameter can take one of the following values: //! - \b MEMCFG_TEST_FUNCTIONAL //! - \b MEMCFG_TEST_WRITE_DATA //! - \b MEMCFG_TEST_WRITE_ECC (DxRAM) or MEMCFG_TEST_WRITE_PARITY (LSx, GSx, //! or MSGxRAM) //! //! The \e ramSection parameter is one of the following indicators: //! - \b MEMCFG_SECT_M0 or \b MEMCFG_SECT_M1 //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx //! - \b MEMCFG_SECT_MSGCPUTOCLA1 or \b MEMCFG_SECT_MSGCLA1TOCPU //! //! \return None. // //***************************************************************************** extern void MemCfg_setTestMode(uint32_t ramSection, MemCfg_TestMode testMode); //***************************************************************************** // //! Starts the initialization the specified RAM sections. //! //! \param ramSections is the logical OR of the sections to be initialized. //! //! This function starts the initialization of the specified RAM sections. Use //! MemCfg_getInitStatus() to check if the initialization is done. //! //! The \e ramSections parameter is an OR of one of the following sets of //! indicators: //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL //! - \b MEMCFG_SECT_MSGCPUTOCLA1 and \b MEMCFG_SECT_MSGCLA1TOCPU or //! \b MEMCFG_SECT_MSGX_ALL //! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. //! //! \return None. // //***************************************************************************** extern void MemCfg_initSections(uint32_t ramSections); //***************************************************************************** // //! Get the status of initialized RAM sections. //! //! \param ramSections is the logical OR of the sections to be checked. //! //! This function gets the initialization status of the RAM sections specified //! by the \e ramSections parameter. //! //! The \e ramSections parameter is an OR of one of the following sets of //! indicators: //! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL //! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL //! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL //! - \b MEMCFG_SECT_MSGCPUTOCLA1 and \b MEMCFG_SECT_MSGCLA1TOCPU or //! \b MEMCFG_SECT_MSGX_ALL //! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections. //! //! \note Use MemCfg_initSections() to start the initialization. //! //! \return Returns \b true if all the sections specified by \e ramSections //! have been initialized and \b false if not. // //***************************************************************************** extern _Bool MemCfg_getInitStatus(uint32_t ramSections); //***************************************************************************** // //! Get the violation address associated with a intFlag. //! //! \param intFlag is the type of access violation as indicated by ONE of //! these values: //! - \b MEMCFG_NMVIOL_CPUREAD //! - \b MEMCFG_NMVIOL_CPUWRITE //! - \b MEMCFG_NMVIOL_CPUFETCH //! - \b MEMCFG_NMVIOL_DMAWRITE //! - \b MEMCFG_NMVIOL_CLA1READ //! - \b MEMCFG_NMVIOL_CLA1WRITE //! - \b MEMCFG_NMVIOL_CLA1FETCH //! - \b MEMCFG_MVIOL_CPUFETCH //! - \b MEMCFG_MVIOL_CPUWRITE //! - \b MEMCFG_MVIOL_DMAWRITE //! //! \return Returns the violation address associated with the \e intFlag. // //***************************************************************************** extern uint32_t MemCfg_getViolationAddress(uint32_t intFlag); //***************************************************************************** // //! Get the correctable error address associated with a stsFlag. //! //! \param stsFlag is the type of error to which the returned address will //! correspond. Can currently take the value \b MEMCFG_CERR_CPUREAD only. //! Other values are reserved. //! //! \return Returns the error address associated with the stsFlag. // //***************************************************************************** extern uint32_t MemCfg_getCorrErrorAddress(uint32_t stsFlag); //***************************************************************************** // //! Get the uncorrectable error address associated with a stsFlag. //! //! \param stsFlag is the type of error to which the returned address will //! correspond. It may be passed one of these values: \b MEMCFG_UCERR_CPUREAD, //! \b MEMCFG_UCERR_DMAREAD, or \b MEMCFG_UCERR_CLA1READ values. //! //! \return Returns the error address associated with the stsFlag. // //***************************************************************************** extern uint32_t MemCfg_getUncorrErrorAddress(uint32_t stsFlag); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: pga.h // // TITLE: C28x PGA driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup pga_api PGA //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_pga.h // // TITLE: Definitions for the PGA registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the PGA register offsets // //***************************************************************************** // gain setting of 3 // gain setting of 6 // gain setting of 12 // gain setting of 24 //***************************************************************************** // // The following are defines for the bit fields in the PGACTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PGALOCK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PGAGAIN3TRIM register // //***************************************************************************** // setting is 3 // setting is 3 //***************************************************************************** // // The following are defines for the bit fields in the PGAGAIN6TRIM register // //***************************************************************************** // setting is 6 // setting is 6 //***************************************************************************** // // The following are defines for the bit fields in the PGAGAIN12TRIM register // //***************************************************************************** // setting is 12 // setting is 12 //***************************************************************************** // // The following are defines for the bit fields in the PGAGAIN24TRIM register // //***************************************************************************** // setting is 24 // setting is 24 //***************************************************************************** // // The following are defines for the bit fields in the PGATYPE register // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to PGA_setGain() as the \e gainValue parameter. // //***************************************************************************** typedef enum { PGA_GAIN_3 = 0x0, //!< PGA gain value of 3 PGA_GAIN_6 = 0x20, //!< PGA gain value of 6 PGA_GAIN_12 = 0x40, //!< PGA gain value of 12 PGA_GAIN_24 = 0x60 //!< PGA gain value of 24 }PGA_GainValue; //***************************************************************************** // //! Values that can be passed to PGA_setFilterResistor() as the \e //! resistorValue parameter. // //***************************************************************************** typedef enum { //! Low pass filter disabled (open circuit) PGA_LOW_PASS_FILTER_DISABLED = 0, //! Resistor value of 200 Ohm PGA_LOW_PASS_FILTER_RESISTOR_200_OHM = 2, //! Resistor value of 160 Ohm PGA_LOW_PASS_FILTER_RESISTOR_160_OHM = 4, //! Resistor value of 130 Ohm PGA_LOW_PASS_FILTER_RESISTOR_130_OHM = 6, //! Resistor value of 100 Ohm PGA_LOW_PASS_FILTER_RESISTOR_100_OHM = 8, //! Resistor value of 80 Ohm PGA_LOW_PASS_FILTER_RESISTOR_80_OHM = 10, //! Resistor value of 50 Ohm PGA_LOW_PASS_FILTER_RESISTOR_50_OHM = 12 }PGA_LowPassResistorValue; //***************************************************************************** // // Values that can be passed to PGA_lockRegisters() as the registerType // parameter. // //***************************************************************************** //! PGA Register PGACTL //! //! PGA Register GAIN3TRIM //! //! PGA Register GAIN6TRIM //! //! PGA Register GAIN12TRIM //! //! PGA Register GAIN24TRIM //! //***************************************************************************** // //! \internal //! Checks PGA wrapper base address. //! //! \param base specifies the PGA wrapper base address. //! //! This function determines if a PGA wrapper base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enables PGA. //! //! \param base is the base address of the PGA module. //! //! This function enables the PGA module. //! //! \return None. // //***************************************************************************** static inline void PGA_enable(uint32_t base) { ; __eallow(); // Set PGAEN bit (*((volatile uint32_t *)(base + 0x0U))) |= (uint32_t)0x1U; __edis(); } //***************************************************************************** // //! Disables PGA. //! //! \param base is the base address of the PGA module. //! //! This function disables the PGA module. //! //! \return None. // //***************************************************************************** static inline void PGA_disable(uint32_t base) { ; __eallow(); // Set PGAEN bit (*((volatile uint32_t *)(base + 0x0U))) &= ~((uint32_t)0x1U); __edis(); } //***************************************************************************** // //! Sets PGA gain value //! //! \param base is the base address of the PGA module. //! \param gainValue is the PGA gain value. //! //! This function sets the PGA gain value. //! //! \return None. // //***************************************************************************** static inline void PGA_setGain(uint32_t base, PGA_GainValue gainValue) { ; __eallow(); // Write to the GAIN bits (*((volatile uint32_t *)(base + 0x0U))) = (((*((volatile uint32_t *)(base + 0x0U))) & ~((uint32_t)0xE0U)) | (uint16_t)gainValue); __edis(); } //***************************************************************************** // //! Sets PGA output filter resistor value //! //! \param base is the base address of the PGA module. //! \param resistorValue is the PGA output resistor value. //! //! This function sets the resistor value for the PGA output low pass RC //! filter. The resistance for the RC low pass filter is provided within the //! microprocessor and is determined by the value of resistorValue. The //! capacitor, however, has to be connected outside the microprocessor. //! //! \b Note: Setting a value of PGA_LOW_PASS_FILTER_RESISTOR_0_OHM will //! disable the internal resistance value. //! //! \return None. // //***************************************************************************** static inline void PGA_setFilterResistor(uint32_t base, PGA_LowPassResistorValue resistorValue) { ; __eallow(); // Write to the FILTRESSEL bits (*((volatile uint32_t *)(base + 0x0U))) = (((*((volatile uint32_t *)(base + 0x0U))) & ~((uint32_t)0x1EU)) | (uint16_t)resistorValue); __edis(); } //***************************************************************************** // //! Returns the PGA revision number. //! //! \param base is the base address of the PGA module. //! //! This function returns the PGA revision number. //! //! \return Returns PGA revision. // //***************************************************************************** static inline uint16_t PGA_getPGARevision(uint32_t base) { ; // return PGA revision number return((uint16_t)((*((volatile uint16_t *)(base + 0x8U))) & 0xFFU)); } //***************************************************************************** // //! Returns the PGA Type. //! //! \param base is the base address of the PGA module. //! //! This function returns the PGA Type number. //! //! \return Returns PGA type. // //***************************************************************************** static inline uint16_t PGA_getPGAType(uint32_t base) { ; // return PGA Type number return((uint16_t)((*((volatile uint16_t *)(base + 0x8U))) >> 8U)); } //***************************************************************************** // //! Locks PGA registers. //! //! \param base is the base address of the PGA module. //! \param registerType is the PGA register to be locked. //! //! This function locks the PGA registers specified by registerType. Valid //! values for registerType are: //! PGA_REGISTER_PGACTL, PGA_REGISTER_GAINxTRIM, where x is //! 3,6,12 or 24. //! //! \return None. // //***************************************************************************** static inline void PGA_lockRegisters(uint32_t base, uint16_t registerType) { ; ; __eallow(); // Write to the appropriate bits of PGALOCK register bits (*((volatile uint16_t *)(base + 0x2U))) |= registerType; __edis(); } //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: pin_map.h // // TITLE: Definitions of pin mux info for gpio.c. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // 0x00000003 = MUX register value // 0x0000000C = GMUX register value // 0x0000FF00 = Shift amount within mux registers // 0xFFFF0000 = Offset of MUX register //***************************************************************************** //############################################################################# // // FILE: pmbus.h // // TITLE: C28x PMBUS Driver // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup pmbus_api PMBus //! @{ // // // Defines for the API. // //***************************************************************************** //########################################################################### // // FILE: hw_pmbus.h // // TITLE: Definitions for the PMBUS registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the PMBUS register offsets // //***************************************************************************** // Register // Configuration Register // Register // Register // Register // Value Register //***************************************************************************** // // The following are defines for the bit fields in the PMBMC register // //***************************************************************************** // Enable // Enable // Enable //***************************************************************************** // // The following are defines for the bit fields in the PMBACK register // //***************************************************************************** // received data //***************************************************************************** // // The following are defines for the bit fields in the PMBSTS register // //***************************************************************************** // available in Receive Data Register // Status // Status //***************************************************************************** // // The following are defines for the bit fields in the PMBINTM register // //***************************************************************************** // Mask // Mask // Mask // Mask // Mask // Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the PMBSC register // //***************************************************************************** // address of the slave. // Acknowledgement Mode // Transmit Data Register // message // Acknowledgement Mode // automatically acknowledge //***************************************************************************** // // The following are defines for the bit fields in the PMBHSA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PMBCTRL register // //***************************************************************************** // Reset // Edge Select // Alert pin in GPIO Mode // pin in GPIO mode // pin // Control pin in GPIO Mode // Control pin in GPIO mode // pin // PMBus data pin in GPIO Mode // data pin in GPIO mode // Clock pin // PMBus clock pin in GPIO Mode // clock pin in GPIO mode // Control // Control //***************************************************************************** // // The following are defines for the bit fields in the PMBTIMCTL register // //***************************************************************************** // of the timing parameters. //***************************************************************************** // // The following are defines for the bit fields in the PMBTIMCLK register // //***************************************************************************** // clock high pulse width. // clock frequency. //***************************************************************************** // // The following are defines for the bit fields in the PMBTIMSTSETUP register // //***************************************************************************** // PMBUS master clock to start edge. //***************************************************************************** // // The following are defines for the bit fields in the PMBTIMBIDLE register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PMBTIMLOWTIMOUT register // //***************************************************************************** // timeout value //***************************************************************************** // // The following are defines for the bit fields in the PMBTIMHIGHTIMOUT register // //***************************************************************************** // timeout value //! Specifies whether to include the CRC8 table in the //! library build //***************************************************************************** // PMBMC Commands -> used in PMBus_configMaster() //***************************************************************************** //! Enable Process call message //! Enable Group command message //! Enable PEC byte //! Enable Extended command //! Enable Command word //! Enable read //***************************************************************************** // PMBINTM Commands -> used in PMBus_enableInterrupt() and // PMBus_disableInterrupt() //***************************************************************************** //! Bus Free Interrupt //! Clock Low Time-out Interrupt //! Data Ready Interrupt //! Data Request Interrupt //! Slave Address Ready Interrupt //! End of Message Interrupt //! Alert Detection Interrupt //! Control Detection Interrupt //! Lost Arbitration Interrupt //! Clock High Detection Interrupt //! all PMBus interrupts //***************************************************************************** // PMBSTS Commands -> returned by PMBus_getInterruptStatus() //***************************************************************************** //! Bus Free Interrupt //! Clock Low Time-out Interrupt //! Data Ready Interrupt //! Data Request Interrupt //! Slave Address Ready Interrupt //! End of Message Interrupt //! Alert Detection Interrupt //! Control Detection Interrupt //! Lost Arbitration Interrupt //! Clock High Detection Interrupt //***************************************************************************** // PMBSC Commands -> They are used in the configWord passed to // PMBus_configSlave() //***************************************************************************** //! Enable manual slave ack modes //! Enable PEC byte processing //! Transmit PEC at end of transaction //! Data Request flag generated after receipt of command code, firmware //! required to issue ACK to continue message //! any bits cleared in slave address mask make that bit a don't care //! Slave will auto acknowledge every received byte //! Slave will auto acknowledge every 2 received bytes //! Slave will auto acknowledge every 3 received bytes //! Slave will auto acknowledge every 4 received bytes //***************************************************************************** // PMBCTRL Commands //***************************************************************************** //! Reset control state machines //! Enable Slave Alert //! Set Clock Low Time-out Interrupt generation on falling edge //! Set Control Interrupt to be generated on rising edge //! Enable PMBus Current Source A Control //! Enable PMBus Current Source B Control //! Disable Clock Low Time-out //! Enable PMBus Slave Enable //! Enable PMBus Master Enable //***************************************************************************** //PMBus Version 1.2 command number constants: //***************************************************************************** //! PMBus Command PAGE //! PMBus Command OPERATION //! PMBus Command ON_OFF_CONFIG //! PMBus Command CLEAR_FAULTS //! PMBus Command PHASE //! PMBus Command PAGE_PLUS_WRITE //! PMBus Command PAGE_PLUS_READ // 0x07-0x0F Reserved //! PMBus Command WRITE_PROTECT //! PMBus Command STORE_DEFAULT_ALL //! PMBus Command RESTORE_DEFAULT_ALL //! PMBus Command STORE_DEFAULT_CODE //! PMBus Command RESTORE_DEFAULT_CODE //! PMBus Command STORE_USER_ALL //! PMBus Command RESTORE_USER_ALL //! PMBus Command STORE_USER_CODE //! PMBus Command RESTORE_USER_CODE //! PMBus Command CAPABILITY //! PMBus Command QUERY //! PMBus Command SMBALERT_MASK // 0x1C - 0x1F Reserved //! PMBus Command VOUT_MODE //! PMBus Command VOUT_COMMAND //! PMBus Command VOUT_TRIM //! PMBus Command VOUT_CAL_OFFSET //! PMBus Command VOUT_MAX //! PMBus Command VOUT_MARGIN_HIGH //! PMBus Command VOUT_MARGIN_LOW //! PMBus Command VOUT_TRANSITION_RATE //! PMBus Command VOUT_DROOP //! PMBus Command VOUT_SCALE_LOOP //! PMBus Command VOUT_SCALE_MONITOR // 0x2B - 0x2F Reserved //! PMBus Command COEFFICIENTS //! PMBus Command POUT_MAX //! PMBus Command MAX_DUTY //! PMBus Command FREQUENCY_SWITCH // 0x34 Reserved //! PMBus Command VIN_ON //! PMBus Command VIN_OFF //! PMBus Command INTERLEAVE //! PMBus Command IOUT_CAL_GAIN //! PMBus Command IOUT_CAL_OFFSET //! PMBus Command FAN_CONFIG_1_2 //! PMBus Command FAN_COMMAND_1 //! PMBus Command FAN_COMMAND_2 //! PMBus Command FAN_CONFIG_3_4 //! PMBus Command FAN_COMMAND_3 //! PMBus Command FAN_COMMAND_4 //! PMBus Command VOUT_OV_FAULT_LIMIT //! PMBus Command VOUT_OV_FAULT_RESPONSE //! PMBus Command VOUT_OV_WARN_LIMIT //! PMBus Command VOUT_UV_WARN_LIMIT //! PMBus Command VOUT_UV_FAULT_LIMIT //! PMBus Command VOUT_UV_FAULT_RESPONSE //! PMBus Command IOUT_OC_FAULT_LIMIT //! PMBus Command IOUT_OC_FAULT_RESPONSE //! PMBus Command IOUT_OC_LV_FAULT_LIMIT //! PMBus Command IOUT_OC_LV_FAULT_RESPONSE //! PMBus Command IOUT_OC_WARN_LIMIT //! PMBus Command IOUT_UC_FAULT_LIMIT //! PMBus Command IOUT_UC_FAULT_RESPONSE // 0x4D – 0x4E Reserved //! PMBus Command OT_FAULT_LIMIT //! PMBus Command OT_FAULT_RESPONSE //! PMBus Command OT_WARN_LIMIT //! PMBus Command UT_WARN_LIMIT //! PMBus Command UT_FAULT_LIMIT //! PMBus Command UT_FAULT_RESPONSE //! PMBus Command VIN_OV_FAULT_LIMIT //! PMBus Command VIN_OV_FAULT_RESPONSE //! PMBus Command VIN_OV_WARN_LIMIT //! PMBus Command VIN_UV_WARN_LIMIT //! PMBus Command VIN_UV_FAULT_LIMIT //! PMBus Command VIN_UV_FAULT_RESPONSE //! PMBus Command IIN_OC_FAULT_LIMIT (For CBC current limit) //! PMBus Command IIN_OC_FAULT_RESPONSE //! PMBus Command IIN_OC_WARN_LIMIT //! PMBus Command POWER_GOOD_ON //! PMBus Command POWER_GOOD_OFF //! PMBus Command TON_DELAY //! PMBus Command TON_RISE //! PMBus Command TON_MAX_FAULT_LIMIT //! PMBus Command TON_MAX_FAULT_RESPONSE //! PMBus Command TOFF_DELAY //! PMBus Command TOFF_FALL //! PMBus Command TOFF_MAX_WARN_LIMIT // 0x67 Rsvd Deleted PMBus v1.1 //! PMBus Command POUT_OP_FAULT_LIMIT //! PMBus Command POUT_OP_FAULT_RESPONSE //! PMBus Command POUT_OP_WARN_LIMIT //! PMBus Command PIN_OP_WARN_LIMIT // 0x6C - 0x77 Reserved //! PMBus Command STATUS_BYTE //! PMBus Command STATUS_WORD //! PMBus Command STATUS_VOUT //! PMBus Command STATUS_IOUT //! PMBus Command STATUS_INPUT //! PMBus Command STATUS_TEMPERATURE //! PMBus Command STATUS_CML //! PMBus Command STATUS_OTHER //! PMBus Command STATUS_MFR_SPECIFIC //! PMBus Command STATUS_FANS_1_2 //! PMBus Command STATUS_FANS_3_4 // 0x83 - 0x85 Reserved //! PMBus Command READ_EIN //! PMBus Command READ_EOUT //! PMBus Command READ_VIN //! PMBus Command READ_IIN //! PMBus Command READ_VCAP //! PMBus Command READ_VOUT //! PMBus Command READ_IOUT //! PMBus Command READ_TEMPERATURE_1 //! PMBus Command READ_TEMPERATURE_2 //! PMBus Command READ_TEMPERATURE_3 //! PMBus Command READ_FAN_SPEED_1 //! PMBus Command READ_FAN_SPEED_2 //! PMBus Command READ_FAN_SPEED_3 //! PMBus Command READ_FAN_SPEED_4 //! PMBus Command READ_DUTY_CYCLE //! PMBus Command READ_FREQUENCY //! PMBus Command READ_POUT //! PMBus Command READ_PIN //! PMBus Command PMBUS_REVISION //! PMBus Command MFR_ID //! PMBus Command MFR_MODEL //! PMBus Command MFR_REVISION //! PMBus Command MFR_LOCATION //! PMBus Command MFR_DATE //! PMBus Command MFR_SERIAL //! PMBus Command APP_PROFILE_SUPPORT //! PMBus Command MFR_VIN_MIN //! PMBus Command MFR_VIN_MAX //! PMBus Command MFR_IIN_MAX //! PMBus Command MFR_PIN_MAX //! PMBus Command MFR_VOUT_MIN //! PMBus Command MFR_VOUT_MAX //! PMBus Command MFR_IOUT_MAX //! PMBus Command MFR_POUT_MAX //! PMBus Command MFR_TAMBIENT_MAX //! PMBus Command MFR_TAMBIENT_MIN //! PMBus Command MFR_EFFICIENCY_LL //! PMBus Command MFR_EFFICIENCY_HL //! PMBus Command MFR_PIN_ACURRACY //! PMBus Command MFR_IC_DEVICE //! PMBus Command MFR_IC_DEVICE_REV // 0xAF Reserved //! PMBus Command USER_DATA_00 //! PMBus Command USER_DATA_01 //! PMBus Command USER_DATA_02 //! PMBus Command USER_DATA_03 //! PMBus Command USER_DATA_04 //! PMBus Command USER_DATA_05 //! PMBus Command USER_DATA_06 //! PMBus Command USER_DATA_07 //! PMBus Command USER_DATA_08 //! PMBus Command USER_DATA_09 //! PMBus Command USER_DATA_10 //! PMBus Command USER_DATA_11 //! PMBus Command USER_DATA_12 //! PMBus Command USER_DATA_13 //! PMBus Command USER_DATA_14 //! PMBus Command USER_DATA_15 //! PMBus Command MFR_MAX_TEMP_1 //! PMBus Command MFR_MAX_TEMP_2 //! PMBus Command MFR_MAX_TEMP_3 // 0xC3-0xCF Reserved //! PMBus Command MFR_LIGHT_LOAD_ENB //! PMBus Command MFR_SPECIFIC_01 //! PMBus Command MFR_SPECIFIC_02 //! PMBus Command MFR_SPECIFIC_03 //! PMBus Command MFR_SPECIFIC_04 //! PMBus Command MFR_SPECIFIC_05 //! PMBus Command MFR_SPECIFIC_06 //! PMBus Command MFR_SPECIFIC_07 //! PMBus Command MFR_SPECIFIC_08 //! PMBus Command ROM_MODE //! PMBus Command USER_RAM_00 //! PMBus Command MFR_PHASE_CONTROL //! PMBus Command MFR_IOUT_OC_FAULT_LIMIT_LOW //! PMBus Command MFR_VIN_SCALE //! PMBus Command MFR_VIN_OFFSET //! PMBus Command MFR_READ_TEMPERATURE_4 //! PMBus Command MFR_OT_LIMIT_1 //! PMBus Command MFR_OT_LIMIT_2 //! PMBus Command MFR_PARM_INFO //! PMBus Command MFR_PARM_VALUE //! PMBus Command MFR_CMDS_DCDC_PAGED //! PMBus Command MFR_CMDS_DCDC_NONPAGED //! PMBus Command MFR_CMDS_PFC //! PMBus Command MFR_SETUP_ID //! PMBus Command MFR_OT_LIMIT_3 //! PMBus Command MFR_OT_LIMIT_4 //! PMBus Command MFR_DEADBAND_CONFIG //! PMBus Command MFR_PIN_CAL_A //! PMBus Command MFR_PIN_CAL_B //! PMBus Command MFR_PIN_CAL_C //! PMBus Command MFR_PIN_CAL_D //! PMBus Command MFR_TEMP_CAL_OFFSET //! PMBus Command MFR_DEBUG_BUFFER //! PMBus Command MFR_TEMP_CAL_GAIN //! PMBus Command MFR_STATUS_BIT_MASK //! PMBus Command MFR_SPECIFIC_35 //! PMBus Command MFR_SPECIFIC_36 //! PMBus Command MFR_SPECIFIC_37 //! PMBus Command MFR_SPECIFIC_38 //! PMBus Command MFR_SPECIFIC_39 //! PMBus Command MFR_VOUT_CAL_MONITOR //! PMBus Command ROM_MODE_WITH_PASSWORD //! PMBus Command MFR_SPECIFIC_42 //! PMBus Command MFR_SPECIFIC_43 //! PMBus Command MFR_SPECIFIC_44 //! PMBus Command MFR_DEVICE_ID //! PMBus Command MFR_SPECIFIC_COMMAND //! PMBus Command PMBUS_COMMAND_EXT //***************************************************************************** // //! Transaction Descriptor //! //! Defines the transaction type, used in the command object //! and passed to PMBus_configTransfer() // //***************************************************************************** typedef enum{ PMBUS_TRANSACTION_NONE = 0U, //!< No Transaction PMBUS_TRANSACTION_QUICKCOMMAND = 1U, //!< Quick Command PMBUS_TRANSACTION_WRITEBYTE = 2U, //!< Write single byte PMBUS_TRANSACTION_READBYTE = 3U, //!< Read single byte PMBUS_TRANSACTION_SENDBYTE = 4U, //!< Send Byte PMBUS_TRANSACTION_RECEIVEBYTE = 5U, //!< Receive Byte PMBUS_TRANSACTION_BLOCKWRITE = 6U, //!< Block Write (up to 255 bytes) PMBUS_TRANSACTION_BLOCKREAD = 7U, //!< Block Read (up to 255 bytes) PMBUS_TRANSACTION_WRITEWORD = 8U, //!< Write word PMBUS_TRANSACTION_READWORD = 9U, //!< Read word PMBUS_TRANSACTION_BLOCKWRPC = 10U //!< Block write, then process call }PMBus_Transaction; //***************************************************************************** // PMBUS Module Clock defines //***************************************************************************** //! Min SYSCLK input to PMBus module //! Max SYSCLK input to PMBus module //! Max module frequency of 20 MHz //! Min module frequency = min_sys_freq/32 //***************************************************************************** // //! Clock Mode Descriptor //! //! Used in PMBus_configBusClock() to set up the bus speed. There are three //! possible modes of operation: //! -# Standard Mode 100 kHz //! -# Fast Mode 400 kHz //! -# Fast Mode Plus 1 MHz // //***************************************************************************** typedef enum{ PMBUS_CLOCKMODE_STANDARD = 0U, //!< Standard mode 100 kHz PMBUS_CLOCKMODE_FAST = 1U, //!< Fast Mode 400 kHz PMBUS_CLOCKMODE_FASTPLUS = 2U //!< Fast Mode plus 1 MHz }PMBus_ClockMode; //***************************************************************************** // //! Access Type Descriptor //! //! Used in PMBus_getCurrentAccessType() to determine if the device, in slave //! mode, was accessed with read or write enabled. // //***************************************************************************** typedef enum{ PMBUS_ACCESSTYPE_WRITE = 0U, //!< Slave last address for write transaction PMBUS_ACCESSTYPE_READ = 1U //!< Slave last address for read transaction }PMBus_accessType; //***************************************************************************** // //! Interrupt Edge Descriptor //! //! Used in PMBus_setCtrlIntEdge() and PMBus_setClkLowTimeoutIntEdge() to set //! the edge, falling or rising, that triggers an interrupt // //***************************************************************************** typedef enum{ PMBUS_INTEDGE_FALLING = 0U, //!< Interrupt generated on falling edge PMBUS_INTEDGE_RISING = 1U //!< Interrupt generated on rising edge }PMBus_intEdge; //***************************************************************************** // // globals // //***************************************************************************** //! CRC table for the polynomial x^8+x^2+x^1+1 or 0x7 (File scope only) extern const uint16_t PMBus_crc8Table[256U]; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks a PMBus base address. //! //! \param base is the base address of the PMBus instance used. //! //! This function determines if a PMBus module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Disables the PMBus module. //! //! \param base is the base address of the PMBus instance used. //! //! This function resets the internal state machine of the PMBus module and //! holds it in that state //! //! \return None. // //***************************************************************************** static inline void PMBus_disableModule(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(base + 0x10U))) |= 0x00000001U; __edis(); } //***************************************************************************** // //! Enables the PMBus module. //! //! \param base is the base address of the PMBus instance used. //! //! This function enables operation of the PMBus module by removing it from the //! reset state //! //! \return None. // //***************************************************************************** static inline void PMBus_enableModule(uint32_t base) { // // Check the arguments. // ; __eallow(); (*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x00000001U; __edis(); } //***************************************************************************** // //! Enables PMBus interrupt sources. //! //! \param base is the base address of the PMBus instance used. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! This function enables the indicated PMBus interrupt sources. Only the //! sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! The \e intFlags parameter is the logical OR of any of the following: //! //! - \b PMBUS_INT_BUS_FREE - Bus Free Interrupt //! - \b PMBUS_INT_CLK_LOW_TIMEOUT - Clock Low Time-out Interrupt //! - \b PMBUS_INT_DATA_READY - Data Ready Interrupt //! - \b PMBUS_INT_DATA_REQUEST - Data Request Interrupt //! - \b PMBUS_INT_SLAVE_ADDR_READY - Slave Address Ready Interrupt //! - \b PMBUS_INT_EOM - End of Message Interrupt //! - \b PMBUS_INT_ALERT - Alert Detection Interrupt //! - \b PMBUS_INT_CONTROL - Control Detection Interrupt //! - \b PMBUS_INT_LOST_ARB - Lost Arbitration Interrupt //! - \b PMBUS_INT_CLK_HIGH_DETECT - Clock High Detection Interrupt //! - \b PMBUS_INT_ALL - all PMBus interrupts //! //! \return None. // //***************************************************************************** static inline void PMBus_enableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; __eallow(); // // Enable the desired basic interrupts i.e. clear their mask bits // in PMBINTM // (*((volatile uint32_t *)(base + 0xAU))) &= ~(intFlags & 0x03FFU); __edis(); } //***************************************************************************** // //! Disables PMBus interrupt sources. //! //! \param base is the base address of the PMBus instance used. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! This function disables the indicated PMBus interrupt sources. Only //! the sources that are enabled can be reflected to the processor interrupt. //! Disabled sources have no effect on the processor. //! //! The \e intFlags parameter has the same definition as the \e intFlags //! parameter to PMBus_enableInterrupt(). //! //! \return None. // //***************************************************************************** static inline void PMBus_disableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // ; __eallow(); // // Disable the desired interrupts // (*((volatile uint32_t *)(base + 0xAU))) |= (intFlags & 0x03FFU); __edis(); } //***************************************************************************** // //! Indicates whether or not the PMBus bus is busy. //! //! \param status the value of the status register (PMBUS_O_PMBSTS) //! //! This function returns an indication of whether or not the PMBus bus is busy //! //! \note The status register is cleared each time it is read, therefore, it //! should be read once at the beginning of an interrupt service routine using //! PMBus_getInterruptStatus() and saved to a temporary variable for further //! processing. //! //! \return Returns \b true if the PMBus bus is busy; otherwise, returns //! \b false. // //***************************************************************************** static inline _Bool PMBus_isBusBusy(uint32_t status) { return(((status & 0x2000U) == 0U) ? 1 : 0); } //***************************************************************************** // //! Indicates whether or not the PEC is valid //! //! \param status the value of the status register (PMBUS_O_PMBSTS) //! //! This function returns an indication of whether or not the received PEC //! was valid //! //! \note The status register is cleared each time it is read, therefore, it //! should be read once at the beginning of an interrupt service routine using //! PMBus_getStatus() and saved to a temporary variable for further //! processing. //! //! \return Returns \b true if the PEC is valid; otherwise, returns //! \b false. // //***************************************************************************** static inline _Bool PMBus_isPECValid(uint32_t status) { return(((status & 0x80U) != 0U) ? 1 : 0); } //***************************************************************************** // //! Enable I2C mode //! //! \param base is the base address of the PMBus instance used. //! //! Set the PMBus module to work in I2C mode //! //! \return None. // //***************************************************************************** static inline void PMBus_enableI2CMode(uint32_t base) { // Locals uint32_t interruptState; // Check the arguments. ; __eallow(); // Save off the interrupt state and disable them interruptState = (*((volatile uint32_t *)(base + 0xAU))); (*((volatile uint32_t *)(base + 0xAU))) = 0x000003FFU; // Set module to I2C mode (*((volatile uint32_t *)(base + 0x10U))) |= 0x80000000U; // Restore the interrupt status (*((volatile uint32_t *)(base + 0xAU))) = interruptState; __edis(); } //***************************************************************************** // //! Disable I2C mode //! //! \param base is the base address of the PMBus instance used. //! //! Set the PMBus module to work in PMBus mode //! //! \return None. // //***************************************************************************** static inline void PMBus_disableI2CMode(uint32_t base) { // Locals uint32_t interruptState; // Check the arguments. ; __eallow(); // Save off the interrupt state and disable them interruptState = (*((volatile uint32_t *)(base + 0xAU))); (*((volatile uint32_t *)(base + 0xAU))) = 0x000003FFU; // Set module to PMBUS mode (*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x80000000U; // Restore the interrupt status (*((volatile uint32_t *)(base + 0xAU))) = interruptState; __edis(); } //***************************************************************************** // //! Read the status register //! //! \param base is the base address of the PMBus instance used. //! //! \return Contents of the status register. // //***************************************************************************** static inline uint32_t PMBus_getStatus(uint32_t base) { // Check the arguments. ; return((*((volatile uint32_t *)(base + 0x8U)))); } //***************************************************************************** // //! Acknowledge the transaction by writing to the PMBACK register //! //! \param base is the base address of the PMBus instance used. //! //! \return None. // //***************************************************************************** static inline void PMBus_ackTransaction(uint32_t base) { // Check the arguments. ; //acknowledge (*((volatile uint32_t *)(base + 0x6U))) |= 0x1U; } //***************************************************************************** // //! Nack the transaction by writing to the PMBACK register //! //! \param base is the base address of the PMBus instance used. //! //! \return None. // //***************************************************************************** static inline void PMBus_nackTransaction(uint32_t base) { // Check the arguments. ; //NACK (*((volatile uint32_t *)(base + 0x6U))) &= ~(uint32_t)0x1U; } //***************************************************************************** // //! Alert the master by asserting the ALERT line //! //! \param base is the base address of the PMBus instance used. //! //! A slave PMBus can alert the master by pulling the alert line low. //! This triggers an Alert Response from the master, where the master issues //! the \b Alert \b Response \b Address on the bus with a read bit and the //! alerting slave is required to reply with its address. //! //! \note The alerting device should be in slave mode. //! //! \return None. // //***************************************************************************** static inline void PMBus_assertAlertLine(uint32_t base) { // Check the arguments. ; __eallow(); //Pull the alert line low (*((volatile uint32_t *)(base + 0x10U))) |= 0x2U; __edis(); } //***************************************************************************** // //! De-assert the alert line //! //! \param base is the base address of the PMBus instance used. //! //! \return None. // //***************************************************************************** static inline void PMBus_deassertAlertLine(uint32_t base) { // Check the arguments. ; __eallow(); //Pull the alert line low (*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x2U; __edis(); } //***************************************************************************** // //! Configure the PMBus operation in Master Mode. //! //! \param base is the base address of the PMBus instance used. //! \param slaveAddress address of the Slave device //! \param byteCount number of bytes transmitted (or read) in the message //! (up to 255) //! \param configWord can be a combination of the following //! -# PMBUS_MASTER_ENABLE_PRC_CALL //! -# PMBUS_MASTER_ENABLE_GRP_CMD //! -# PMBUS_MASTER_ENABLE_PEC //! -# PMBUS_MASTER_ENABLE_EXT_CMD //! -# PMBUS_MASTER_ENABLE_CMD //! -# PMBUS_MASTER_ENABLE_READ //! //! Assuming the PMBus module is set to Master mode this function will //! configure the PMBMC register. It overwrites the contents of the PMBMC //! register. //! \note //! -# Writing to the PMBMC register initiates a message on the bus once //! the bus is free. In the event of a write the TXBUF must be loaded prior //! to configuration, or very quickly after configuration, before the module //! starts the bus clock. //! -# If the user does not specify an option for example, //! PMBUS_MASTER_ENABLE_READ, the code will write a 0 (a write) in its //! bit field. //! -# setting byteCount to 0U (on a write) triggers a quick command; there //! is no need to precede this command with the PMBus_putMasterData() //! -# If transmitting with a non-zero byteCount the user must precede this //! with the PMBus_putMasterData(), supplying it with the location of the data //! and the number of bytes (<= 4). For block transmissions the user will have //! to call PMBus_putMasterData(), PMBus_configMaster() and then continue //! calling PMBus_putMasterData() transmitting 4 (or less for the final //! transmit) bytes at a time till all the data bytes are transmitted. //! -# If receiving the user must follow up with the PMBus_getData(), //! supplying it with the location of an empty buffer and the status byte //! -# In cases where the master must transmit for example, process call, //! the user must call PMBus_putMasterData(), then configure the master to //! transmit the command and two bytes, then call PMBus_getData() to //! read two bytes from the slave. The master module need not be reconfigured //! between write and read whenever a repeated start is involved in the //! transaction //! \return None. // //***************************************************************************** static inline void PMBus_configMaster(uint32_t base, uint16_t slaveAddress, uint16_t byteCount, uint32_t configWord) { // Locals // form a bit mask of the bit fields configWord changes const uint32_t bitmask = (0x1U | 0x10000U | 0x20000U | 0x40000U | 0x80000U | 0x100000U); // Check the arguments. ; ; ; __eallow(); // write the user configured bit fields (passed in configWord) as well // as slave address and message byte counts. Writing to PMBMC triggers // activity on the bus, once the bus is free (PMBSTS.BUS_FREE = 1) (*((volatile uint32_t *)(base + 0x0U))) = ((configWord & bitmask) | (((uint32_t)slaveAddress << 1U) & 0xFEU) | (((uint32_t)byteCount << 8U) & 0xFF00U)); __edis(); } //***************************************************************************** // //! Get the address that the PMBus module will respond to (in slave mode) //! //! \param base is the base address of the PMBus instance used. //! \param ownAddress address that the module will respond to. //! //! This function will query the PMBUS_O_PMBHSA register, this //! will be the address of the module when used in Slave Mode. //! \return Address of the PMBus device (in slave mode). // //***************************************************************************** static inline uint16_t PMBus_getOwnAddress(uint32_t base) { // Check the arguments. ; return(((*((volatile uint32_t *)(base + 0xEU))) & 0xFEU) >> 1U); } //***************************************************************************** // //! Determine the current access (read/write) type //! //! \param base is the base address of the PMBus instance used. //! //! This function will query the PMBUS_O_PMBHSA register, to determine if //! the current access type was a read or write access. This bit is relevant //! only when the PMBus module is addressed as a slave. //! //! \return an enum of the type PMBus_accessType which specifies if the device, //! in slave mode, was addressed for a read or write operation // //***************************************************************************** static inline PMBus_accessType PMBus_getCurrentAccessType(uint32_t base) { // Check the arguments. ; return((PMBus_accessType)((*((volatile uint32_t *)(base + 0xEU))) & 0x01U)); } //***************************************************************************** // //! Sets the triggering edge of the Control Interrupt //! //! \param base is the base address of the PMBus instance used. //! \param intEdge interrupt to trigger on rising or falling edge //! //! \return None. // //***************************************************************************** static inline void PMBus_setCtrlIntEdge(uint32_t base, PMBus_intEdge intEdge) { // Check the arguments. ; __eallow(); if(intEdge == PMBUS_INTEDGE_FALLING) { // Clear bit (*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x20U; } else // PMBUS_INTEDGE_RISING { // Set bit (*((volatile uint32_t *)(base + 0x10U))) |= 0x20U; } __edis(); } //***************************************************************************** // //! Sets the triggering edge of the Clock Low Time-out Interrupt //! //! \param base is the base address of the PMBus instance used. //! \param intEdge interrupt to trigger on rising or falling edge //! //! \return None. // //***************************************************************************** static inline void PMBus_setClkLowTimeoutIntEdge(uint32_t base, PMBus_intEdge intEdge) { // Check the arguments. ; __eallow(); if(intEdge == PMBUS_INTEDGE_FALLING) { // Set bit (*((volatile uint32_t *)(base + 0x10U))) |= 0x4U; } else // PMBUS_INTEDGE_RISING { // Clear bit (*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x4U; } __edis(); } //***************************************************************************** // //! Initializes the PMBus to Slave Mode. //! //! \param base is the base address of the PMBus instance used. //! \param address Slave address //! \param mask Slave address mask - Used in address detection, the slave //! mask enables acknowledgement of multiple device addresses by the slave. //! Writing a '0' to a bit within the slave mask enables the corresponding bit //! in the slave address to be either '1' or '0' and still allow for a match. //! Writing a '0' to all bits in the mask enables the PMBus Interface to //! acknowledge any device address. Upon power-up, the slave mask defaults to //! 7Fh, indicating the slave will only acknowledge the address programmed //! into the Slave Address (Bits 6-0). //! Set to PMBUS_DISABLE_SLAVE_ADDRESS_MASK if you do not wish to have a mask //! //! This function sets up the PMBus in slave mode and also configures the slave //! address for the PMBus module //! //! \return None. // //***************************************************************************** extern void PMBus_initSlaveMode(uint32_t base, uint16_t address, uint16_t mask); //***************************************************************************** // //! Configure the PMBus operation in Slave Mode. //! //! \param base is the base address of the PMBus instance used. //! \param configWord can be a combination of the following //! -# PMBUS_SLAVE_ENABLE_MANUAL_ACK //! -# PMBUS_SLAVE_ENABLE_PEC_PROCESSING //! -# PMBUS_SLAVE_ENABLE_MANUAL_CMD_ACK //! -# PMBUS_SLAVE_DISABLE_ADDRESS_MASK //! -# PMBUS_SLAVE_AUTO_ACK_1_BYTES //! -# PMBUS_SLAVE_AUTO_ACK_2_BYTES //! -# PMBUS_SLAVE_AUTO_ACK_3_BYTES //! -# PMBUS_SLAVE_AUTO_ACK_4_BYTES //! //! Assuming the PMBus module is set to slave mode, this function will //! configure the PMBSC register. It overwrites the contents of the PMBSC //! register, with the exception of the address, slave mask, TXPEC and byte //! count bit fields. //! \note If the user does not specify an option, for example, //! PMBUS_SLAVE_ENABLE_PEC_PROCESSING, the code will write a 0 (a write) in //! its bit field. //! //! \return None. // //***************************************************************************** extern void PMBus_configSlave(uint32_t base, uint32_t configWord); //***************************************************************************** // //! Gets the current PMBus interrupt status. //! //! \param base is the base address of the PMBus instance used. //! //! This function returns the interrupt status for the PMBus module. //! //! \return The current interrupt status, as a bit field of //! - \b PMBUS_INTSRC_BUS_FREE //! - \b PMBUS_INTSRC_CLK_LOW_TIMEOUT //! - \b PMBUS_INTSRC_DATA_READY //! - \b PMBUS_INTSRC_DATA_REQUEST //! - \b PMBUS_INTSRC_SLAVE_ADDR_READY //! - \b PMBUS_INTSRC_EOM //! - \b PMBUS_INTSRC_ALERT //! - \b PMBUS_INTSRC_CONTROL //! - \b PMBUS_INTSRC_LOST_ARB //! - \b PMBUS_INTSRC_CLK_HIGH_DETECT // //***************************************************************************** extern uint32_t PMBus_getInterruptStatus(uint32_t base); //***************************************************************************** // //! Read the receive buffer (Slave or Master mode) //! //! \param base is the base address of the PMBus instance used. //! \param buffer pointer to the message buffer where the received bytes //! will be written to //! \param status the value of the status register (PMBUS_O_PMBSTS) //! //! This function can read up to 4 bytes in the receive buffer. //! \note //! -# The status register is cleared each time it is read, therefore, it //! should be read once at the beginning of an interrupt service routine using //! PMBus_getStatus() and saved to a temporary variable for further //! processing. //! //! -# The buffer should be at least 4 words long; anything smaller will //! lead to the possibility of memory overrun when a transaction of 4 bytes //! happens. //! //! \return Returns the number of byte(s) received by the PMBus in the //! array pointed to by buffer. // //***************************************************************************** extern uint16_t PMBus_getData(uint32_t base, uint16_t *buffer, uint32_t status); //***************************************************************************** // //! write to the transmit buffer (Slave mode) //! //! \param base is the base address of the PMBus instance used. //! \param buffer pointer to the message buffer where the transmit bytes //! are stored //! \param nBytes number of transmit bytes, up to 4 //! \param txPEC 1 transmit PEC at end of message, 0 no PEC //! //! This function can write up to 4 bytes in the transmit buffer. //! //! \note //! -# The user must check the UNIT_BUSY bit before attempting a transmission. //! -# The buffer should be at least 4 words long; anything smaller will //! lead to the possibility of memory overrun when a transaction of 4 bytes //! happens. //! //! \return None. // //***************************************************************************** extern void PMBus_putSlaveData(uint32_t base, uint16_t *buffer, uint16_t nBytes, _Bool txPEC); //***************************************************************************** // //! Manual acknowledgement of the slave address //! //! \param base is the base address of the PMBus instance used. //! \param address address of the slave //! \param status the value of the status register (PMBUS_O_PMBSTS) //! \param buffer pointer to a buffer to store the received data //! //! This function will read the address that was put on the bus, compare it //! with address passed to this function and then acknowledge on a match (or //! nack on mismatch). For this function to work, SLAVE_ADDR_READY bit in //! PBINTM must be enabled. This function checks the SLAVE_ADDR_READY bit in //! the status register before acknowledging so it would be preferable to use //! this function in an interrupt handler that responds to the SLAVE_ADDR_READY //! interrupt. //! //! \note //! -# The status register is cleared each time it is read, therefore, it //! should be read once at the beginning of an interrupt service routine using //! PMBus_getStatus() and saved to a temporary variable for further //! processing. //! -# The buffer should be at least 4 words long; anything smaller will //! lead to the possibility of memory overrun when a transaction of 4 bytes //! happens. //! //! \return None. // //***************************************************************************** extern void PMBus_ackAddress(uint32_t base, uint32_t address, uint32_t status, uint16_t *buffer); //***************************************************************************** // //! Manual acknowledgement of a command //! //! \param base is the base address of the PMBus instance used. //! \param command command to manually acknowledge - it can be any of the //! commands listed in this header file. All commands have the common //! prefix \b PMBUS_CMD. //! \param status contents of the status register PMBUS_O_PMBSTS //! \param buffer pointer to a buffer to store the received data //! //! This function will read the command that was put on the bus, compare it //! with command passed to this function and then acknowledge on a match (or //! nack on mismatch). For this function to work, DATA_READY bit in PBINTM //! must be enabled. This function checks the DATA_READY bit in the status //! register before acknowledging so it would be preferable to use this //! function in an interrupt handler that responds to the DATA_READY interrupt. //! //! \note //! -# The status register is cleared each time it is read, therefore, it //! should be read once at the beginning of an interrupt service routine using //! PMBus_getStatus() and saved to a temporary variable for further //! processing. //! -# The buffer should be at least 4 words long; anything smaller will //! lead to the possibility of memory overrun when a transaction of 4 bytes //! happens. //! //! \return None. // //***************************************************************************** extern void PMBus_ackCommand(uint32_t base, uint32_t command, uint32_t status, uint16_t *buffer); //***************************************************************************** // //! Generate a CRC table at run time //! //! \param base is the base address of the PMBus instance used. //! \param crcTable points to the CRC8 Table (must be size 256) //! //! This function generates a CRC lookup table to run a CRC on the //! received data. The table is generated from the polynomial //! x^8 + x^2 + x^1 + 1 (0x7 - leading 1 is implicit) //! //! \return None. // //***************************************************************************** extern void PMBus_generateCRCTable(uint16_t *crcTable); //***************************************************************************** // //! Run a CRC on the received data and check against the //! received PEC to validate the integrity of the data //! //! \param base is the base address of the PMBus instance used. //! \param buffer points to the received message //! \buffer crcTable points to the CRC8 Table //! \param byteCount size of the message, does not include the PEC byte //! \param pec is the received PEC to check against //! //! This function uses a CRC lookup table to run a CRC on the //! received data. The table was generated from the polynomial //! x^8 + x^2 + x^1 + 1 (0x7 - leading 1 is implicit) //! //! \note The buffer should be at least 4 words long; anything smaller will //! lead to the possibility of memory overrun when a transaction of 4 bytes //! happens. //! //! \return \b true if the calculated CRC is equal to the PEC, \b false //! otherwise. // //***************************************************************************** extern _Bool PMBus_verifyPEC(uint32_t base, uint16_t *buffer, const uint16_t *crcTable, uint16_t byteCount, uint16_t pec); //***************************************************************************** // //! Initializes the PMBus to Master Mode. //! //! \param base is the base address of the PMBus instance used. //! //! This function sets up the PMBus in master mode. //! //! \return None. // //***************************************************************************** extern void PMBus_initMasterMode(uint32_t base); //***************************************************************************** // //! write to the transmit buffer (Master mode) //! //! \param base is the base address of the PMBus instance used. //! \param buffer pointer to the message buffer where the transmit bytes //! are stored //! \param nBytes number of transmit bytes, up to 255 //! //! This function can write up to 255 bytes in the transmit buffer. //! //! \note //! -# The user must check the UNIT_BUSY bit before attempting the //! first transmission. //! -# The buffer should be at least 4 words long; anything smaller will //! lead to the possibility of memory overrun when a transaction of 4 bytes //! happens. //! //! \return None. // //***************************************************************************** extern void PMBus_putMasterData(uint32_t base, uint16_t *buffer, uint16_t nBytes); //***************************************************************************** // //! Configure the PMBus module clock //! //! \param base is the base address of the PMBus instance used. //! \param moduleFrequency desired module frequency; can range from //! PMBUS_MODULE_FREQ_MIN Hz to PMBUS_MODULE_FREQ_MAX Hz. Please input the //! frequency in Hz, e.g. 312500 for 312.4 kHz etc. //! \param sysFrequency Frequency of the system clock (input to PMBus). The //! values may range anywhere from PMBUS_SYS_FREQ_MIN Hz to PMBUS_SYS_FREQ_MAX //! Hz. Please input the frequency in Hz, e.g. 100000000 for 100 MHz etc. //! //! The frequency to the PMBus module may not exceed PMBUS_MODULE_FREQ_MAX Hz, //! the appropriate clock divider is chosen to bring the module clock to the //! desired frequency - this value is then returned by the function. //! In the event that the desired bus frequency is unattainable, the clock //! divider is set to the maximum possible value //! //! \return module frequency calculated from the system frequency and clock //! divider. // //***************************************************************************** extern uint32_t PMBus_configModuleClock(uint32_t base, uint32_t moduleFrequency, uint32_t sysFrequency); //***************************************************************************** // //! Configure the bus clock by overriding the default settings //! //! \param base is the base address of the PMBus instance used. //! \param mode is the operating mode for the PMBus, can be //! - Standard Mode //! - Fast Mode //! - Fast Mode Plus //! \param moduleFrequency desired module frequency; can range from //! PMBUS_MODULE_FREQ_MIN Hz to PMBUS_MODULE_FREQ_MAX Hz. Please input the //! frequency in Hz, e.g. 312500 for 312.4 kHz etc. //! //! The frequency to the PMBus module may not exceed PMBUS_MODULE_FREQ_MAX Hz. //! //! \note //! -# The module comes out of reset with preprogrammed values that allow //! it to work in standard mode with a module clock of 10MHz. The module clock //! is set to 10MHz at power cycle, therefore, the user does not have to call //! this function unless they wish to change the operating frequency of the //! module clock from the default 10 MHz. //! -# As per PMBus Standard 'PMBus_Specification_Part_I_Rev_1-0_20100906' //! the maximum bus Speed is 400 kHz hence FASTPLUS mode does not apply to PMBus //! but rather to the I2C mode of the PMBus module. //! //! \return \b true for successful override, \b false on failure. // //***************************************************************************** extern _Bool PMBus_configBusClock(uint32_t base, PMBus_ClockMode mode, uint32_t moduleFrequency); //***************************************************************************** // Close the Doxygen group. //! @} // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: sci.h // // TITLE: C28x SCI driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup sci_api SCI //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_sci.h // // TITLE: Definitions for the SCI registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the SCI register offsets // //***************************************************************************** // register // register //***************************************************************************** // // The following are defines for the bit fields in the SCICCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCICTL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIHBAUD register // //***************************************************************************** // Registers SCIHBAUD //***************************************************************************** // // The following are defines for the bit fields in the SCILBAUD register // //***************************************************************************** // Registers SCILBAUD //***************************************************************************** // // The following are defines for the bit fields in the SCICTL2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIRXST register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIRXEMU register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIRXBUF register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCITXBUF register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIFFTX register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIFFRX register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIFFCT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SCIPRI register // //***************************************************************************** //***************************************************************************** // // Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and // SCI_clearInterruptStatus as the intFlags parameter, and returned from // SCI_getInterruptStatus. // //***************************************************************************** //***************************************************************************** // // Values that can be passed to SCI_setConfig as the config parameter // and returned by SCI_getConfig in the config parameter. // Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to // SCI_setParityMode as the parity parameter, and are returned by // SCI_getParityMode. // //***************************************************************************** //***************************************************************************** // //! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to //! describe the parity of the SCI communication. // //***************************************************************************** typedef enum { SCI_CONFIG_PAR_NONE = 0x0000U, //!< No parity SCI_CONFIG_PAR_EVEN = 0x0060U, //!< Even parity SCI_CONFIG_PAR_ODD = 0x0020U //!< Odd parity } SCI_ParityType; //***************************************************************************** // //! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel //! parameter and returned by SCI_getFIFOInteruptLevel() and //! SCI_getTxFIFOStatus(). // //***************************************************************************** typedef enum { SCI_FIFO_TX0 = 0x0000U, //!< Transmit interrupt empty SCI_FIFO_TX1 = 0x0001U, //!< Transmit interrupt 1/16 full SCI_FIFO_TX2 = 0x0002U, //!< Transmit interrupt 2/16 full SCI_FIFO_TX3 = 0x0003U, //!< Transmit interrupt 3/16 full SCI_FIFO_TX4 = 0x0004U, //!< Transmit interrupt 4/16 full SCI_FIFO_TX5 = 0x0005U, //!< Transmit interrupt 5/16 full SCI_FIFO_TX6 = 0x0006U, //!< Transmit interrupt 6/16 full SCI_FIFO_TX7 = 0x0007U, //!< Transmit interrupt 7/16 full SCI_FIFO_TX8 = 0x0008U, //!< Transmit interrupt 8/16 full SCI_FIFO_TX9 = 0x0009U, //!< Transmit interrupt 9/16 full SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full SCI_FIFO_TX16 = 0x0010U //!< Transmit interrupt full } SCI_TxFIFOLevel; //***************************************************************************** // //! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel //! parameter and returned by SCI_getFIFOInterruptLevel() and //! SCI_getRxFIFOStatus(). // //***************************************************************************** typedef enum { SCI_FIFO_RX0 = 0x0000U, //!< Receive interrupt empty SCI_FIFO_RX1 = 0x0001U, //!< Receive interrupt 1/16 full SCI_FIFO_RX2 = 0x0002U, //!< Receive interrupt 2/16 full SCI_FIFO_RX3 = 0x0003U, //!< Receive interrupt 3/16 full SCI_FIFO_RX4 = 0x0004U, //!< Receive interrupt 4/16 full SCI_FIFO_RX5 = 0x0005U, //!< Receive interrupt 5/16 full SCI_FIFO_RX6 = 0x0006U, //!< Receive interrupt 6/16 full SCI_FIFO_RX7 = 0x0007U, //!< Receive interrupt 7/16 full SCI_FIFO_RX8 = 0x0008U, //!< Receive interrupt 8/16 full SCI_FIFO_RX9 = 0x0009U, //!< Receive interrupt 9/16 full SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full SCI_FIFO_RX16 = 0x0010U //!< Receive interrupt full } SCI_RxFIFOLevel; //***************************************************************************** // // Values returned from SCI_getRxStatus(). These correspond to the different // bits and flags of the SCIRXST register. // //***************************************************************************** //***************************************************************************** // // API Function prototypes // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks a SCI base address. //! //! \param base is the base address of the SCI port. //! //! This function determines if a SCI port base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Sets the type of parity. //! //! \param base is the base address of the SCI port. //! \param parity specifies the type of parity to use. //! //! Sets the type of parity to use for transmitting and expect when receiving. //! The \e parity parameter must be one of the following: //! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. //! //! \return None. // //***************************************************************************** static inline void SCI_setParityMode(uint32_t base, SCI_ParityType parity) { // // Check the arguments. // ; // // Set the parity mode. // (*((volatile uint16_t *)(base + 0x0U))) = (((*((volatile uint16_t *)(base + 0x0U))) & ~(0x0060U)) | (uint16_t)parity); } //***************************************************************************** // //! Gets the type of parity currently being used. //! //! \param base is the base address of the SCI port. //! //! This function gets the type of parity used for transmitting data and //! expected when receiving data. //! //! \return Returns the current parity settings, specified as one of the //! following: //! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. // //***************************************************************************** static inline SCI_ParityType SCI_getParityMode(uint32_t base) { uint16_t parity; // // Check the arguments. // ; // // Return the current parity setting. // parity = ((*((volatile uint16_t *)(base + 0x0U))) & (0x0060U)); return((SCI_ParityType)parity); } //***************************************************************************** // //! Locks Autobaud. //! //! \param base is the base address of the SCI port. //! //! This function performs an autobaud lock for the SCI. //! //! \return None. // //***************************************************************************** static inline void SCI_lockAutobaud(uint32_t base) { // // Check the arguments. // ; // // Prime the baud register // (*((volatile uint16_t *)(base + 0x2U))) = 0x0U; (*((volatile uint16_t *)(base + 0x3U))) = 0x1U; // // Prepare for autobaud detection. // Set the CDC bit to enable autobaud detection and clear the ABD bit. // (*((volatile uint16_t *)(base + 0xCU))) |= 0x2000U; (*((volatile uint16_t *)(base + 0xCU))) |= 0x4000U; // // Wait until we correctly read an 'A' or 'a' and lock // while(((*((volatile uint16_t *)(base + 0xCU))) & 0x8000U) != 0x8000U) { } // // After autobaud lock, clear the ABD and CDC bits // (*((volatile uint16_t *)(base + 0xCU))) |= 0x4000U; (*((volatile uint16_t *)(base + 0xCU))) &= ~0x2000U; } //***************************************************************************** // //! Sets the FIFO interrupt level at which interrupts are generated. //! //! \param base is the base address of the SCI port. //! \param txLevel is the transmit FIFO interrupt level, specified as one of //! the following: //! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or //! \b SCI_FIFO_TX15. //! \param rxLevel is the receive FIFO interrupt level, specified as one of //! the following //! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX15. //! //! This function sets the FIFO level at which transmit and receive interrupts //! are generated. //! //! \return None. // //***************************************************************************** static inline void SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel, SCI_RxFIFOLevel rxLevel) { // // Check the arguments. // ; // // Set the FIFO interrupt levels. // (*((volatile uint16_t *)(base + 0xAU))) = ((*((volatile uint16_t *)(base + 0xAU))) & (~0x1FU)) | (uint16_t)txLevel; (*((volatile uint16_t *)(base + 0xBU))) = ((*((volatile uint16_t *)(base + 0xBU))) & (~0x1FU)) | (uint16_t)rxLevel; } //***************************************************************************** // //! Gets the FIFO interrupt level at which interrupts are generated. //! //! \param base is the base address of the SCI port. //! \param txLevel is a pointer to storage for the transmit FIFO interrupt //! level, returned as one of the following: //! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX15. //! \param rxLevel is a pointer to storage for the receive FIFO interrupt //! level, returned as one of the following: //! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX15. //! //! This function gets the FIFO level at which transmit and receive interrupts //! are generated. //! //! \return None. // //***************************************************************************** static inline void SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel, SCI_RxFIFOLevel *rxLevel) { // // Check the arguments. // ; // // Extract the transmit and receive FIFO levels. // *txLevel = (SCI_TxFIFOLevel)((*((volatile uint16_t *)(base + 0xAU))) & 0x1FU); *rxLevel = (SCI_RxFIFOLevel)((*((volatile uint16_t *)(base + 0xBU))) & 0x1FU); } //***************************************************************************** // //! Gets the current configuration of a SCI. //! //! \param base is the base address of the SCI port. //! \param lspclkHz is the rate of the clock supplied to the SCI module. This //! is the LSPCLK. //! \param baud is a pointer to storage for the baud rate. //! \param config is a pointer to storage for the data format. //! //! The baud rate and data format for the SCI is determined, given an //! explicitly provided peripheral clock (hence the ExpClk suffix). The //! returned baud rate is the actual baud rate; it may not be the exact baud //! rate requested or an ``official'' baud rate. The data format returned in //! \e config is enumerated the same as the \e config parameter of //! SCI_setConfig(). //! //! The peripheral clock is the low speed peripheral clock. This will be //! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly //! hard coded if it is constant and known (to save the code/execution overhead //! of a call to SysCtl_getLowSpeedClock()). //! //! \return None. // //***************************************************************************** static inline void SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud, uint32_t *config) { // // Check the arguments. // ; // // Compute the baud rate. // *baud = lspclkHz / ((1U + (uint32_t)((uint32_t)((*((volatile uint16_t *)(base + 0x2U))) << 8U) | (*((volatile uint16_t *)(base + 0x3U))))) * 8U); // // Get the parity, data length, and number of stop bits. // *config = (*((volatile uint16_t *)(base + 0x0U))) & (0x0060U | 0x0080U | 0x0007U); } //***************************************************************************** // //! Enables transmitting and receiving. //! //! \param base is the base address of the SCI port. //! //! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and //! RXENA bits which enables transmit and receive. //! //! \return None. // //***************************************************************************** static inline void SCI_enableModule(uint32_t base) { // // Check the arguments. // ; // // Enable RX, TX, and the SCI. // (*((volatile uint16_t *)(base + 0x1U))) |= (0x2U | 0x1U | 0x20U); } //***************************************************************************** // //! Disables transmitting and receiving. //! //! \param base is the base address of the SCI port. //! //! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the //! data has been sent before disable the module during transmission. //! //! \return None. // //***************************************************************************** static inline void SCI_disableModule(uint32_t base) { // // Check the arguments. // ; // // Disable the FIFO. // (*((volatile uint16_t *)(base + 0xAU))) &= ~(0x4000U); // // Disable the SCI. // (*((volatile uint16_t *)(base + 0x1U))) &= ~(0x2U | 0x1U); } //***************************************************************************** // //! Enables the transmit and receive FIFOs. //! //! \param base is the base address of the SCI port. //! //! This functions enables the transmit and receive FIFOs in the SCI. //! //! \return None. // //***************************************************************************** static inline void SCI_enableFIFO(uint32_t base) { // // Check the arguments. // ; // // Enable the FIFO. // (*((volatile uint16_t *)(base + 0xAU))) |= 0x8000U; (*((volatile uint16_t *)(base + 0xAU))) |= 0x4000U | 0x2000U; (*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U; } //***************************************************************************** // //! Disables the transmit and receive FIFOs. //! //! \param base is the base address of the SCI port. //! //! This functions disables the transmit and receive FIFOs in the SCI. //! //! \return None. // //***************************************************************************** static inline void SCI_disableFIFO(uint32_t base) { // // Check the arguments. // ; // // Disable the FIFO. // (*((volatile uint16_t *)(base + 0xAU))) &= ~0x4000U; } //***************************************************************************** // //! Determines if the FIFO enhancement is enabled. //! //! \param base is the base address of the SCI port. //! //! This function returns a flag indicating whether or not the FIFO enhancement //! is enabled. //! //! \return Returns \b true if the FIFO enhancement is enabled or \b false //! if the FIFO enhancement is disabled. // //***************************************************************************** static inline _Bool SCI_isFIFOEnabled(uint32_t base) { // // Check the arguments. // ; // // Return true if the FIFO is enabled and false if it is disabled. // return((((*((volatile uint16_t *)(base + 0xAU))) & 0x4000U) == 0x4000U) ? 1 : 0); } //***************************************************************************** // //! Resets the receive FIFO. //! //! \param base is the base address of the SCI port. //! //! This functions resets the receive FIFO of the SCI. //! //! \return None. // //***************************************************************************** static inline void SCI_resetRxFIFO(uint32_t base) { // // Check the arguments. // ; // // Reset the specified FIFO. // (*((volatile uint16_t *)(base + 0xBU))) &= ~0x2000U; (*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U; } //***************************************************************************** // //! Resets the transmit FIFO. //! //! \param base is the base address of the SCI port. //! //! This functions resets the transmit FIFO of the SCI. //! //! \return None. // //***************************************************************************** static inline void SCI_resetTxFIFO(uint32_t base) { // // Check the arguments. // ; // // Reset the specified FIFO. // (*((volatile uint16_t *)(base + 0xAU))) &= ~0x2000U; (*((volatile uint16_t *)(base + 0xAU))) |= 0x2000U; } //***************************************************************************** // //! Resets the SCI Transmit and Receive Channels //! //! \param base is the base address of the SCI port. //! //! This functions resets transmit and receive channels in the SCI. //! //! \return None. // //***************************************************************************** static inline void SCI_resetChannels(uint32_t base) { // // Check the arguments. // ; // // Reset the Tx and Rx Channels // (*((volatile uint16_t *)(base + 0xAU))) |= 0x8000U; } //***************************************************************************** // //! Determines if there are any characters in the receive buffer when the //! FIFO enhancement is not enabled. //! //! \param base is the base address of the SCI port. //! //! This function returns a flag indicating whether or not there is data //! available in the receive buffer. //! //! \return Returns \b true if there is data in the receive buffer or \b false //! if there is no data in the receive buffer. // //***************************************************************************** static inline _Bool SCI_isDataAvailableNonFIFO(uint32_t base) { // // Check the arguments. // ; // // Return the availability of characters with FIFO disabled. // return((((*((volatile uint16_t *)(base + 0x5U))) & 0x40U) == 0x40U) ? 1 : 0); } //***************************************************************************** // //! Determines if there is any space in the transmit buffer when the FIFO //! enhancement is not enabled. //! //! \param base is the base address of the SCI port. //! //! This function returns a flag indicating whether or not there is space //! available in the transmit buffer when not using the FIFO enhancement. //! //! \return Returns \b true if there is space available in the transmit buffer //! or \b false if there is no space available in the transmit buffer. // //***************************************************************************** static inline _Bool SCI_isSpaceAvailableNonFIFO(uint32_t base) { // // Check the arguments. // ; // // Return the availability of space. // return((((*((volatile uint16_t *)(base + 0x4U))) & 0x80U) == 0x80U) ? 1 : 0); } //***************************************************************************** // //! Get the transmit FIFO status //! //! \param base is the base address of the SCI port. //! //! This functions gets the current number of words in the transmit FIFO. //! //! \return Returns the current number of words in the transmit FIFO specified //! as one of the following: //! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3 //! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16 // //***************************************************************************** static inline SCI_TxFIFOLevel SCI_getTxFIFOStatus(uint32_t base) { // // Check the arguments. // ; // // Get the current FIFO status // return((SCI_TxFIFOLevel)(((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) >> 8U)); } //***************************************************************************** // //! Get the receive FIFO status //! //! \param base is the base address of the SCI port. //! //! This functions gets the current number of words in the receive FIFO. //! //! \return Returns the current number of words in the receive FIFO specified //! as one of the following: //! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3 //! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16 // //***************************************************************************** static inline SCI_RxFIFOLevel SCI_getRxFIFOStatus(uint32_t base) { // // Check the arguments. // ; // // Get the current FIFO status // return((SCI_RxFIFOLevel)(((*((volatile uint16_t *)(base + 0xBU))) & 0x1F00U) >> 8U)); } //***************************************************************************** // //! Determines whether the SCI transmitter is busy or not. //! //! \param base is the base address of the SCI port. //! //! Allows the caller to determine whether all transmitted bytes have cleared //! the transmitter hardware when the FIFO is not enabled. When the FIFO is //! enabled, this function allows the caller to determine whether there is any //! data in the FIFO. //! //! Without the FIFO enabled, if \b false is returned, the transmit buffer and //! shift registers are empty and the transmitter is not busy. With the FIFO //! enabled, if \b false is returned, the FIFO is empty. This does not //! necessarily mean that the transmitter is not busy. The empty FIFO does not //! reflect the status of the transmitter shift register. The FIFO may be empty //! while the transmitter is still transmitting data. //! //! \return Returns \b true if the SCI is transmitting or \b false if //! transmissions are complete. // //***************************************************************************** static inline _Bool SCI_isTransmitterBusy(uint32_t base) { // // Check the argument. // ; // // Check if FIFO enhancement is enabled. // if(SCI_isFIFOEnabled(base)) { // // With FIFO enhancement, determine if the SCI is busy. // return((((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) == 0x1F00U) ? 1 : 0); } else { // // Without FIFO enhancement, determine if the SCI is busy. // Check if the transmit buffer and shift register empty. // return((((*((volatile uint16_t *)(base + 0x4U))) & 0x40U) == 0x40U) ? 0 : 1); } } //***************************************************************************** // //! Waits to send a character from the specified port when the FIFO enhancement //! is enabled. //! //! \param base is the base address of the SCI port. //! \param data is the character to be transmitted. //! //! Sends the character \e data to the transmit buffer for the specified port. //! If there is no space available in the transmit FIFO, this function waits //! until there is space available before returning. \e data is a uint16_t but //! only 8 bits are written to the SCI port. SCI only transmits 8 bit //! characters. //! //! \return None. // //***************************************************************************** static inline void SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Wait until space is available in the transmit FIFO. // while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX15) { } // // Send a char. // (*((volatile uint16_t *)(base + 0x9U))) = data; } //***************************************************************************** // //! Waits to send a character from the specified port. //! //! \param base is the base address of the SCI port. //! \param data is the character to be transmitted. //! //! Sends the character \e data to the transmit buffer for the specified port. //! If there is no space available in the transmit buffer, or the transmit //! FIFO if it is enabled, this function waits until there is space available //! before returning. \e data is a uint16_t but only 8 bits are written to the //! SCI port. SCI only transmits 8 bit characters. //! //! \return None. // //***************************************************************************** static inline void SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Wait until space is available in the transmit buffer. // while(!SCI_isSpaceAvailableNonFIFO(base)) { } // // Send a char. // (*((volatile uint16_t *)(base + 0x9U))) = data; } //***************************************************************************** // //! Sends a character to the specified port. //! //! \param base is the base address of the SCI port. //! \param data is the character to be transmitted. //! //! Writes the character \e data to the transmit buffer for the specified port. //! This function does not block and only writes to the transmit buffer. //! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus() //! to determine if the transmit buffer or FIFO have space available. //! \e data is a uint16_t but only 8 bits are written to the SCI port. SCI //! only transmits 8 bit characters. //! //! This function replaces the original SCICharNonBlockingPut() API and //! performs the same actions. A macro is provided in sci.h to map //! the original API to this API. //! //! \return None. // //***************************************************************************** static inline void SCI_writeCharNonBlocking(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Send a char. // (*((volatile uint16_t *)(base + 0x9U))) = data; } //***************************************************************************** // //! Waits for a character from the specified port when the FIFO enhancement //! is enabled. //! //! \param base is the base address of the SCI port. //! //! Gets a character from the receive FIFO for the specified port. If there //! are no characters available, this function waits until a character is //! received before returning. //! //! \return Returns the character read from the specified port as \e uint16_t. // //***************************************************************************** static inline uint16_t SCI_readCharBlockingFIFO(uint32_t base) { // // Check the arguments. // ; // // Wait until a character is available in the receive FIFO. // while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) { } // // Return the character from the receive buffer. // return(uint16_t)((*((volatile uint16_t *)(base + 0x7U))) & 0xFFU); } //***************************************************************************** // //! Waits for a character from the specified port when the FIFO enhancement //! is not enabled. //! //! \param base is the base address of the SCI port. //! //! Gets a character from the receive buffer for the specified port. If there //! is no characters available, this function waits until a character is //! received before returning. //! //! \return Returns the character read from the specified port as \e uint16_t. // //***************************************************************************** static inline uint16_t SCI_readCharBlockingNonFIFO(uint32_t base) { // // Check the arguments. // ; // // Wait until a character is available in the receive FIFO. // while(!SCI_isDataAvailableNonFIFO(base)) { } // // Return the character from the receive buffer. // return(uint16_t)((*((volatile uint16_t *)(base + 0x7U))) & 0xFFU); } //***************************************************************************** // //! Receives a character from the specified port. //! //! \param base is the base address of the SCI port. //! //! Gets a character from the receive buffer for the specified port. This //! function does not block and only reads the receive buffer. The user should //! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if //! the receive buffer or FIFO have data available. //! //! This function replaces the original SCICharNonBlockingGet() API and //! performs the same actions. A macro is provided in sci.h to map //! the original API to this API. //! //! \return Returns \e uin16_t which is read from the receive buffer. // //***************************************************************************** static inline uint16_t SCI_readCharNonBlocking(uint32_t base) { // // Check the arguments. // ; // // Return the character from the receive buffer. // return(uint16_t)((*((volatile uint16_t *)(base + 0x7U))) & 0xFFU); } //***************************************************************************** // //! Gets current receiver status flags. //! //! \param base is the base address of the SCI port. //! //! This function returns the current receiver status flags. The returned //! error flags are equivalent to the error bits returned via the previous //! reading or receiving of a character with the exception that the overrun //! error is set immediately the overrun occurs rather than when a character //! is next read. //! //! \return Returns a bitwise OR combination of the receiver status flags, //! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN, //! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY, //! and \b SCI_RXSTATUS_ERROR. // //***************************************************************************** static inline uint16_t SCI_getRxStatus(uint32_t base) { // // Check the arguments. // ; // // Return the current value of the receive status register. // return((*((volatile uint16_t *)(base + 0x5U)))); } //***************************************************************************** // //! Performs a software reset of the SCI and Clears all reported receiver //! status flags. //! //! \param base is the base address of the SCI port. //! //! This function performs a software reset of the SCI port. It affects the //! operating flags of the SCI, but it neither affects the configuration bits //! nor restores the reset values. //! //! \return None. // //***************************************************************************** static inline void SCI_performSoftwareReset(uint32_t base) { // // Check the arguments. // ; // // To clear all errors a sw reset of the module is required // (*((volatile uint16_t *)(base + 0x1U))) &= ~0x20U; (*((volatile uint16_t *)(base + 0x1U))) |= 0x20U; } //***************************************************************************** // //! Enables Loop Back Test Mode //! //! \param base is the base address of the SCI port. //! //! Enables the loop back test mode where the Tx pin is internally connected //! to the Rx pin. //! //! \return None. // //***************************************************************************** static inline void SCI_enableLoopback(uint32_t base) { // // Check the arguments. // ; // // Set the loop back mode. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x10U; } //***************************************************************************** // //! Disables Loop Back Test Mode //! //! \param base is the base address of the SCI port. //! //! Disables the loop back test mode where the Tx pin is no longer internally //! connected to the Rx pin. //! //! \return None. // //***************************************************************************** static inline void SCI_disableLoopback(uint32_t base) { // // Check the arguments. // ; // // Clear the loop back mode. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x10U; } //***************************************************************************** // //! Get the receive FIFO Overflow flag status //! //! \param base is the base address of the SCI port. //! //! This functions gets the receive FIFO overflow flag status. //! //! \return Returns \b true if overflow has occurred, else returned \b false if //! an overflow hasn't occurred. // //***************************************************************************** static inline _Bool SCI_getOverflowStatus(uint32_t base) { // // Check the arguments. // ; // // Return the current FIFO overflow status // return(((*((volatile uint16_t *)(base + 0xBU))) & 0x8000U) == 0x8000U); } //***************************************************************************** // //! Clear the receive FIFO Overflow flag status //! //! \param base is the base address of the SCI port. //! //! This functions clears the receive FIFO overflow flag status. //! //! \return None. // //***************************************************************************** static inline void SCI_clearOverflowStatus(uint32_t base) { // // Check the arguments. // ; // // Clear the current FIFO overflow status // (*((volatile uint16_t *)(base + 0xBU))) |= 0x4000U; } //***************************************************************************** // //! Sets the configuration of a SCI. //! //! \param base is the base address of the SCI port. //! \param lspclkHz is the rate of the clock supplied to the SCI module. This //! is the LSPCLK. //! \param baud is the desired baud rate. //! \param config is the data format for the port (number of data bits, //! number of stop bits, and parity). //! //! This function configures the SCI for operation in the specified data //! format. The baud rate is provided in the \e baud parameter and the data //! format in the \e config parameter. //! //! The \e config parameter is the bitwise OR of three values: the number of //! data bits, the number of stop bits, and the parity. \b SCI_CONFIG_WLEN_8, //! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5, //! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and //! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte //! (respectively). //! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop //! bits (respectively). \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, //! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity //! bit, odd parity bit respectively). //! //! The peripheral clock is the low speed peripheral clock. This will be //! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly //! hard coded if it is constant and known (to save the code/execution overhead //! of a call to SysCtl_getLowSpeedClock()). //! //! \return None. // //***************************************************************************** extern void SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, uint32_t config); //***************************************************************************** // //! Waits to send an array of characters from the specified port. //! //! \param base is the base address of the SCI port. //! \param array is the address of the array of characters to be transmitted. //! It is pointer to the array of characters to be transmitted. //! \param length is the length of the array, or number of characters in the //! array to be transmitted. //! //! Sends the number of characters specified by \e length, starting at the //! address \e array, out of the transmit buffer for the specified port. //! If there is no space available in the transmit buffer, or the transmit //! FIFO if it is enabled, this function waits until there is space available //! and \e length number of characters are transmitted before returning. //! \e array is a pointer to uint16_ts but only the least significant 8 bits //! are written to the SCI port. SCI only transmits 8 bit characters. //! //! \return None. // //***************************************************************************** extern void SCI_writeCharArray(uint32_t base, const uint16_t * const array, uint16_t length); //***************************************************************************** // //! Waits to receive an array of characters from the specified port. //! //! \param base is the base address of the SCI port. //! \param array is the address of the array of characters to be received. //! It is a pointer to the array of characters to be received. //! \param length is the length of the array, or number of characters in the //! array to be received. //! //! Receives an array of characters from the receive buffer for the specified //! port, and stores them as an array of characters starting at address //! \e array. This function waits until the \e length number of characters are //! received before returning. //! //! \return None. // //***************************************************************************** extern void SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length); //***************************************************************************** // //! Enables individual SCI interrupt sources. //! //! \param base is the base address of the SCI port. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Enables the indicated SCI interrupt sources. Only the sources that are //! enabled can be reflected to the processor interrupt; disabled sources have //! no effect on the processor. //! //! The \e intFlags parameter is the bitwise OR of any of the following: //! //! - \b SCI_INT_RXERR - RXERR Interrupt //! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt //! - \b SCI_INT_TXRDY - TXRDY Interrupt //! - \b SCI_INT_TXFF - TX FIFO Level Interrupt //! - \b SCI_INT_RXFF - RX FIFO Level Interrupt //! - \b SCI_INT_FE - Frame Error //! - \b SCI_INT_OE - Overrun Error //! - \b SCI_INT_PE - Parity Error //! //! \return None. // //***************************************************************************** extern void SCI_enableInterrupt(uint32_t base, uint32_t intFlags); //***************************************************************************** // //! Disables individual SCI interrupt sources. //! //! \param base is the base address of the SCI port. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! Disables the indicated SCI interrupt sources. Only the sources that are //! enabled can be reflected to the processor interrupt; disabled sources have //! no effect on the processor. //! //! The \e intFlags parameter has the same definition as the \e intFlags //! parameter to SCI_enableInterrupt(). //! //! \return None. // //***************************************************************************** extern void SCI_disableInterrupt(uint32_t base, uint32_t intFlags); //***************************************************************************** // //! Gets the current interrupt status. //! //! \param base is the base address of the SCI port. //! //! \return Returns the current interrupt status, enumerated as a bit field of //! values described in SCI_enableInterrupt(). // //***************************************************************************** extern uint32_t SCI_getInterruptStatus(uint32_t base); //***************************************************************************** // //! Clears SCI interrupt sources. //! //! \param base is the base address of the SCI port. //! \param intFlags is a bit mask of the interrupt sources to be cleared. //! //! The specified SCI interrupt sources are cleared, so that they no longer //! assert. This function must be called in the interrupt handler to keep the //! interrupt from being recognized again immediately upon exit. //! //! The \e intFlags parameter has the same definition as the \e intFlags //! parameter to SCI_enableInterrupt(). //! //! \return None. // //***************************************************************************** extern void SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: sdfm.h // // TITLE: C28x SDFM Driver // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup sdfm_api SDFM //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_sdfm.h // // TITLE: Definitions for the SDFM registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the SDFM register offsets // //***************************************************************************** // Register // for Ch1 // Register for Ch1 // Ch1 // for Ch1 // for Ch1 // Register for Ch1 // or 32bit) for Ch1 // for Ch1 // Register (16b) for Ch1 // Register for Ch1 // Ch1 // for Ch2 // Register for Ch2 // Ch2 // for Ch2 // for Ch2 // Register for Ch2 // or 32bit) for Ch2 // for Ch2 // Register (16b) for Ch2 // Register for Ch2 // Ch2 // for Ch3 // Register for Ch3 // Ch3 // for Ch3 // for Ch3 // Register for Ch3 // or 32bit) for Ch3 // for Ch3 // Register (16b) for Ch3 // Register for Ch3 // Ch3 // for Ch4 // Register for Ch4 // Ch4 // for Ch4 // for Ch4 // Register for Ch4 // or 32bit) for Ch4 // for Ch4 // Register (16b) for Ch4 // Register for Ch4 // Ch4 //***************************************************************************** // // The following are defines for the bit fields in the SDIFLG register // //***************************************************************************** // Ch1 // Ch1 // Ch2 // Ch2 // Ch3 // Ch3 // Ch4 // Ch4 // 1 // 2 // 3 // 4 //***************************************************************************** // // The following are defines for the bit fields in the SDIFLGCLR register // //***************************************************************************** // Ch1 // Ch1 // Ch2 // Ch2 // Ch3 // Ch3 // Ch4 // Ch4 // 1 // 2 // 3 // 4 // bit for Ch1 // bit for Ch2 // bit for Ch3 // bit for Ch4 //***************************************************************************** // // The following are defines for the bit fields in the SDCTL register // //***************************************************************************** // (Z) flag Ch1 // (Z) flag Ch2 // (Z) flag Ch3 // (Z) flag Ch4 // enable //***************************************************************************** // // The following are defines for the bit fields in the SDMFILEN register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SDSTATUS register // //***************************************************************************** // (Z) flag Ch1 // (Z) flag Ch2 // (Z) flag Ch3 // (Z) flag Ch4 //***************************************************************************** // // The following are defines for the bit fields in the SDCTLPARM1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SDDFPARM1 register // //***************************************************************************** // DOSR+1 // (SincFast/1/2/3) //***************************************************************************** // // The following are defines for the bit fields in the SDDPARM1 register // //***************************************************************************** // 16/32b 2's complement) // shift in 16b mode) //***************************************************************************** // // The following are defines for the bit fields in the SDCMPH1 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCMPL1 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCPARM1 register // //***************************************************************************** // Actual rate COSR+1 // (SincFast/1/2/3) // enable // crossing output enable //***************************************************************************** // // The following are defines for the bit fields in the SDDATA1 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDDATFIFO1 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDCMPHZ1 register // //***************************************************************************** // the comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDFIFOCTL1 register // //***************************************************************************** // Enable // Select // enable //***************************************************************************** // // The following are defines for the bit fields in the SDSYNC1 register // //***************************************************************************** // Enable //***************************************************************************** // // The following are defines for the bit fields in the SDCTLPARM2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SDDFPARM2 register // //***************************************************************************** // DOSR+1 // (SincFast/1/2/3) //***************************************************************************** // // The following are defines for the bit fields in the SDDPARM2 register // //***************************************************************************** // 16/32b 2's complement) // shift in 16b mode) //***************************************************************************** // // The following are defines for the bit fields in the SDCMPH2 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCMPL2 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCPARM2 register // //***************************************************************************** // Actual rate COSR+1 // (SincFast/1/2/3) // enable // crossing output enable //***************************************************************************** // // The following are defines for the bit fields in the SDDATA2 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDDATFIFO2 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDCMPHZ2 register // //***************************************************************************** // the comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDFIFOCTL2 register // //***************************************************************************** // Enable // Select // enable //***************************************************************************** // // The following are defines for the bit fields in the SDSYNC2 register // //***************************************************************************** // Enable //***************************************************************************** // // The following are defines for the bit fields in the SDCTLPARM3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SDDFPARM3 register // //***************************************************************************** // DOSR+1 // (SincFast/1/2/3) //***************************************************************************** // // The following are defines for the bit fields in the SDDPARM3 register // //***************************************************************************** // 16/32b 2's complement) // shift in 16b mode) //***************************************************************************** // // The following are defines for the bit fields in the SDCMPH3 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCMPL3 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCPARM3 register // //***************************************************************************** // Actual rate COSR+1 // (SincFast/1/2/3) // enable // crossing output enable //***************************************************************************** // // The following are defines for the bit fields in the SDDATA3 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDDATFIFO3 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDCMPHZ3 register // //***************************************************************************** // the comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDFIFOCTL3 register // //***************************************************************************** // Enable // Select // enable //***************************************************************************** // // The following are defines for the bit fields in the SDSYNC3 register // //***************************************************************************** // Enable //***************************************************************************** // // The following are defines for the bit fields in the SDCTLPARM4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SDDFPARM4 register // //***************************************************************************** // DOSR+1 // (SincFast/1/2/3) //***************************************************************************** // // The following are defines for the bit fields in the SDDPARM4 register // //***************************************************************************** // 16/32b 2's complement) // shift in 16b mode) //***************************************************************************** // // The following are defines for the bit fields in the SDCMPH4 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCMPL4 register // //***************************************************************************** // comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDCPARM4 register // //***************************************************************************** // Actual rate COSR+1 // (SincFast/1/2/3) // enable // crossing output enable //***************************************************************************** // // The following are defines for the bit fields in the SDDATA4 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDDATFIFO4 register // //***************************************************************************** // 16-bit Data in 16b mode //***************************************************************************** // // The following are defines for the bit fields in the SDCMPHZ4 register // //***************************************************************************** // the comparator filter output //***************************************************************************** // // The following are defines for the bit fields in the SDFIFOCTL4 register // //***************************************************************************** // Enable // Select // enable //***************************************************************************** // // The following are defines for the bit fields in the SDSYNC4 register // //***************************************************************************** // Enable //! Macro to get the low threshold //! //! Macro to get the high threshold //! //! Macro to convert comparator over sampling ratio to acceptable bit location //! //! Macro to convert the data shift bit values to acceptable bit location //! //! Macro to combine high threshold and low threshold values //! //! Macro to set the FIFO level to acceptable bit location //! //! Macro to set and enable the zero cross threshold value. //! //! Macros to enable or disable filter. //! //***************************************************************************** // //! Values that can be returned from SDFM_getThresholdStatus() // //***************************************************************************** typedef enum { SDFM_OUTPUT_WITHIN_THRESHOLD = 0, //!< SDFM output is within threshold SDFM_OUTPUT_ABOVE_THRESHOLD = 1, //!< SDFM output is above threshold SDFM_OUTPUT_BELOW_THRESHOLD = 2 //!< SDFM output is below threshold } SDFM_OutputThresholdStatus; //***************************************************************************** // //! Values that can be passed to all functions as the \e filterNumber //! parameter. // //***************************************************************************** typedef enum { SDFM_FILTER_1 = 0, //!< Digital filter 1 SDFM_FILTER_2 = 1, //!< Digital filter 2 SDFM_FILTER_3 = 2, //!< Digital filter 3 SDFM_FILTER_4 = 3 //!< Digital filter 4 } SDFM_FilterNumber; //***************************************************************************** // //! Values that can be passed to SDFM_setFilterType(), //! SDFM_setComparatorFilterType() as the \e filterType parameter. // //***************************************************************************** typedef enum { //! Digital filter with SincFast structure. SDFM_FILTER_SINC_FAST = 0x00, //! Digital filter with Sinc1 structure SDFM_FILTER_SINC_1 = 0x10, //! Digital filter with Sinc3 structure. SDFM_FILTER_SINC_2 = 0x20, //! Digital filter with Sinc4 structure. SDFM_FILTER_SINC_3 = 0x30 } SDFM_FilterType; //***************************************************************************** // //! Values that can be passed to SDFM_setupModulatorClock(),as the //! \e clockMode parameter. // //***************************************************************************** typedef enum { //! Modulator clock is identical to the data rate SDFM_MODULATOR_CLK_EQUAL_DATA_RATE = 0, //! Modulator clock is half the data rate SDFM_MODULATOR_CLK_HALF_DATA_RATE = 1, //! Modulator clock is off. Data is Manchester coded. SDFM_MODULATOR_CLK_OFF = 2, //! Modulator clock is double the data rate. SDFM_MODULATOR_CLK_DOUBLE_DATA_RATE = 3 } SDFM_ModulatorClockMode; //***************************************************************************** // //! Values that can be passed to SDFM_setOutputDataFormat(),as the //! \e dataFormat parameter. // //***************************************************************************** typedef enum { //! Filter output is in 16 bits 2's complement format. SDFM_DATA_FORMAT_16_BIT = 0, //! Filter output is in 32 bits 2's complement format. SDFM_DATA_FORMAT_32_BIT = 1 } SDFM_OutputDataFormat; //***************************************************************************** // //! Values that can be passed to SDFM_setDataReadyInterruptSource(),as the //! \e dataReadySource parameter. // //***************************************************************************** typedef enum { //! Data ready interrupt source is direct (non -FIFO). SDFM_DATA_READY_SOURCE_DIRECT = 0, //! Data ready interrupt source is FIFO. SDFM_DATA_READY_SOURCE_FIFO = 1 } SDFM_DataReadyInterruptSource; //***************************************************************************** // //! Values that can be passed to SDFM_setPWMSyncSource(),as the //! \e syncSource parameter. // //***************************************************************************** typedef enum { SDFM_SYNC_PWM1_SOCA = 0, //!< SDFM sync source is PWM1 SOCA SDFM_SYNC_PWM1_SOCB = 1, //!< SDFM sync source is PWM1 SOCB SDFM_SYNC_PWM2_SOCA = 4, //!< SDFM sync source is PWM2 SOCA SDFM_SYNC_PWM2_SOCB = 5, //!< SDFM sync source is PWM2 SOCB SDFM_SYNC_PWM3_SOCA = 8, //!< SDFM sync source is PWM3 SOCA SDFM_SYNC_PWM3_SOCB = 9, //!< SDFM sync source is PWM3 SOCB SDFM_SYNC_PWM4_SOCA = 12, //!< SDFM sync source is PWM4 SOCA SDFM_SYNC_PWM4_SOCB = 13, //!< SDFM sync source is PWM4 SOCB SDFM_SYNC_PWM5_SOCA = 16, //!< SDFM sync source is PWM5 SOCA SDFM_SYNC_PWM5_SOCB = 17, //!< SDFM sync source is PWM5 SOCB SDFM_SYNC_PWM6_SOCA = 20, //!< SDFM sync source is PWM6 SOCA SDFM_SYNC_PWM6_SOCB = 21, //!< SDFM sync source is PWM6 SOCB SDFM_SYNC_PWM7_SOCA = 24, //!< SDFM sync source is PWM7 SOCA SDFM_SYNC_PWM7_SOCB = 25, //!< SDFM sync source is PWM7 SOCB SDFM_SYNC_PWM8_SOCA = 28, //!< SDFM sync source is PWM8 SOCA SDFM_SYNC_PWM8_SOCB = 29 //!< SDFM sync source is PWM8 SOCB } SDFM_PWMSyncSource; //***************************************************************************** // //! Values that can be passed to SDFM_setFIFOClearOnSyncMode(),as the //! \e fifoClearSyncMode parameter. // //***************************************************************************** typedef enum { //! SDFM FIFO buffer is not cleared on Sync signal SDFM_FIFO_NOT_CLEARED_ON_SYNC = 0, //! SDFM FIFO buffer is cleared on Sync signal SDFM_FIFO_CLEARED_ON_SYNC = 1 } SDFM_FIFOClearSyncMode; //***************************************************************************** // //! Values that can be passed to SDFM_setWaitForSyncClearMode(),as the //! \e syncClearMode parameter. // //***************************************************************************** typedef enum { //! Wait for sync cleared using software. SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC = 0, //! Wait for sync cleared automatically SDFM_AUTO_CLEAR_WAIT_FOR_SYNC = 1 } SDFM_WaitForSyncClearMode; //***************************************************************************** // // Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt // as intFlags parameter // //***************************************************************************** //! Interrupt is generated if Modulator fails. //! //! Interrupt on Comparator low-level threshold. //! //! Interrupt on Comparator high-level threshold. //! //! Interrupt on Acknowledge flag //! //! Interrupt on FIFO level //! //! Interrupt on FIFO overflow //! //***************************************************************************** // // Values that can be passed to SDFM_clearInterruptFlag flags parameter // //***************************************************************************** //! Master interrupt flag //! //! Filter 1 high -level threshold flag //! //! Filter 1 low -level threshold flag //! //! Filter 2 high -level threshold flag //! //! Filter 2 low -level threshold flag //! //! Filter 3 high -level threshold flag //! //! Filter 3 low -level threshold flag //! //! Filter 4 high -level threshold flag //! //! Filter 4 low -level threshold flag //! //! Filter 1 modulator failed flag //! //! Filter 2 modulator failed flag //! //! Filter 3 modulator failed flag //! //! Filter 4 modulator failed flag //! //! Filter 1 new data flag //! //! Filter 2 new data flag //! //! Filter 3 new data flag //! //! Filter 4 new data flag //! //! Filter 1 FIFO overflow flag //! //! Filter 2 FIFO overflow flag //! //! Filter 3 FIFO overflow flag //! //! Filter 4 FIFO overflow flag //! //! Filter 1 FIFO overflow flag //! //! Filter 2 FIFO overflow flag //! //! Filter 3 FIFO overflow flag //! //! Filter 4 FIFO overflow flag //! //***************************************************************************** // //! \internal //! Checks SDFM base address. //! //! \param base specifies the SDFM module base address. //! //! This function determines if SDFM module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enable external reset //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function enables data filter to be reset by an external source (PWM //! compare output). //! //! \return None. // //***************************************************************************** static inline void SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Set the FILRESEN bit __eallow(); (*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) |= 0x1000U; __edis(); } //***************************************************************************** // //! Disable external reset //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function disables data filter from being reset by an external source //! (PWM compare output). //! //! \return None. //***************************************************************************** static inline void SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Clear the FILRESEN bit __eallow(); (*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) &= ~0x1000U; __edis(); } //***************************************************************************** // //! Enable filter //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function enables the filter specified by the \e filterNumber variable. //! //! \return None. // //***************************************************************************** static inline void SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Set the FEN bit __eallow(); (*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) |= 0x100U; __edis(); } //***************************************************************************** // //! Disable filter //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function disables the filter specified by the \e filterNumber //! variable. //! //! \return None. //***************************************************************************** static inline void SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Clear the FEN bit __eallow(); (*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) &= ~0x100U; __edis(); } //***************************************************************************** // //! Enable FIFO buffer //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function enables the filter FIFO buffer specified by the //! \e filterNumber variable. //! //! \return None. // //***************************************************************************** static inline void SDFM_enableFIFOBuffer(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Set the FFEN bit __eallow(); (*((volatile uint16_t *)(base + 0x1DU + ((uint32_t)filterNumber * 16U)))) |= 0x2000U; __edis(); } //***************************************************************************** // //! Disable FIFO buffer //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function disables the filter FIFO buffer specified by the //! \e filterNumber variable. //! //! \return None. // //***************************************************************************** static inline void SDFM_disableFIFOBuffer(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Clear the FFEN bit __eallow(); (*((volatile uint16_t *)(base + 0x1DU + ((uint32_t)filterNumber * 16U)))) &= ~0x2000U; __edis(); } //***************************************************************************** // //! Return the Zero Cross Trip status //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the Zero Cross Trip status for the filter //! specified by filterNumber variable. //! //! \return \b true if Comparator filter output >= High-level threshold (Z) //! \b false if Comparator filter output < High-level threshold (Z) // //***************************************************************************** static inline _Bool SDFM_getZeroCrossTripStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; return((((*((volatile uint16_t *)(base + 0x7U))) >> (uint16_t)filterNumber) & 0x1U) == 1U); } //***************************************************************************** // //! Clear the Zero Cross Trip status //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function clears the Zero Cross Trip status for the filter //! specified by filterNumber variable. //! //! \return None. // //***************************************************************************** static inline void SDFM_clearZeroCrossTripStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Set SDCTL MIE bit __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= (1U << filterNumber); __edis(); } //***************************************************************************** // //! Enable Comparator. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function enables the Comparator for the selected filter. //! //! \return None. // //***************************************************************************** static inline void SDFM_enableComparator(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Set CEN bit __eallow(); (*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) |= 0x2000U; __edis(); } //***************************************************************************** // //! Disable Comparator. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function disables the Comparator for the selected filter. //! //! \return None. // //***************************************************************************** static inline void SDFM_disableComparator(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Clear CEN bit __eallow(); (*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) &= ~0x2000U; __edis(); } //***************************************************************************** // //! Set filter type. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param filterType is the filter type or structure. //! //! This function sets the filter type or structure to be used as specified by //! filterType for the selected filter number as specified by filterNumber. //! //! \return None. //***************************************************************************** static inline void SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_FilterType filterType) { uint32_t address; ; address = base + 0x11U + ((uint32_t)filterNumber * 16U); // write to SST bits __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0xC00U)) | ((uint16_t)filterType << 6U); __edis(); } //***************************************************************************** // //! Set data filter over sampling ratio. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param overSamplingRatio is the data filter over sampling ratio. //! //! This function sets the filter oversampling ratio for the filter specified //! by the filterNumber variable.Valid values for the variable //! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio //! will be this value plus one. //! //! \return None. //***************************************************************************** static inline void SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t overSamplingRatio) { uint32_t address; ; ; address = base + 0x11U + ((uint32_t)filterNumber * 16U); // write to DOSR bits __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0xFFU)) | overSamplingRatio; __edis(); } //***************************************************************************** // //! Set modulator clock mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param clockMode is the modulator clock mode. //! //! This function sets the modulator clock mode specified by clockMode //! for the filter specified by filterNumber. //! //! \return None. //***************************************************************************** static inline void SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_ModulatorClockMode clockMode) { uint32_t address; ; address = base + 0x10U + ((uint32_t)filterNumber * 16U); // write to MOD bits __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x3U)) | (uint16_t)clockMode; __edis(); } //***************************************************************************** // //! Set the output data format //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param dataFormat is the output data format. //! //! This function sets the output data format for the filter specified by //! filterNumber. //! //! \return None. // //***************************************************************************** static inline void SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_OutputDataFormat dataFormat) { uint32_t address; ; address = base + 0x12U + ((uint32_t)filterNumber * 16U); // write to DR bit __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x400U)) | ((uint16_t)dataFormat << 10U); __edis(); } //***************************************************************************** // //! Set data shift value. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param shiftValue is the data shift value. //! //! This function sets the shift value for the 16 bit 2's complement data //! format. The valid maximum value for shiftValue is 31. //! //! \b Note: Use this function with 16 bit 2's complement data format only. //! //! \return None. // //***************************************************************************** static inline void SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t shiftValue) { uint32_t address; ; ; address = base + 0x12U + ((uint32_t)filterNumber * 16U); // write to SH bit __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0xF800U)) | (shiftValue << 11U); __edis(); } //***************************************************************************** // //! Set Filter output high-level threshold. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param highThreshold is the high-level threshold. //! //! This function sets the unsigned high-level threshold value for the //! Comparator filter output. If the output value of the filter exceeds //! highThreshold and interrupt generation is enabled, an interrupt will be //! issued. //! //! \return None. // //***************************************************************************** static inline void SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t highThreshold) { uint32_t address; ; ; address = base + 0x13U + ((uint32_t)filterNumber * 16U); // write to HLT bit __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x7FFFU) | highThreshold; __edis(); } //***************************************************************************** // //! Set Filter output low-level threshold. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param lowThreshold is the low-level threshold. //! //! This function sets the unsigned low-level threshold value for the //! Comparator filter output. If the output value of the filter gets below //! lowThreshold and interrupt generation is enabled, an interrupt will be //! issued. //! //! \return None. // //***************************************************************************** static inline void SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t lowThreshold) { uint32_t address; ; ; address = base + 0x14U + ((uint32_t)filterNumber * 16U); // write to LLT bit __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x7FFFU) | lowThreshold; __edis(); } //***************************************************************************** // //! Set Filter output zero-cross threshold. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param zeroCrossThreshold is the zero-cross threshold. //! //! This function sets the unsigned zero-cross threshold value for the //! Comparator filter output. //! //! \return None. // //***************************************************************************** static inline void SDFM_setCompFilterZeroCrossThreshold(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t zeroCrossThreshold) { uint32_t address; ; ; address = base + 0x1CU + ((uint32_t)filterNumber * 16U); // write to ZCT bit __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x7FFFU) | zeroCrossThreshold; __edis(); } //***************************************************************************** // //! Enable zero-cross Edge detect mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function enables Zero Cross Edge detection. //! //! \return None. // //***************************************************************************** static inline void SDFM_enableZeroCrossEdgeDetect(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Set ZCEN bit __eallow(); (*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) |= 0x400U; __edis(); } //***************************************************************************** // //! Disable zero-cross Edge detect mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function disables Zero Cross Edge detection. //! //! \return None. // //***************************************************************************** static inline void SDFM_disableZeroCrossEdgeDetect(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Clear ZCEN bit __eallow(); (*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) &= ~0x400U; __edis(); } //***************************************************************************** // //! Enable SDFM interrupts. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param intFlags is the interrupt source. //! //! This function enables the low threshold , high threshold or modulator //! failure interrupt as determined by intFlags for the filter specified //! by filterNumber. //! Valid values for intFlags are: //! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, //! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT, SDFM_FIFO_INTERRUPT, //! SDFM_FIFO_OVERFLOW_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT //! //! \return None. // //***************************************************************************** static inline void SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t intFlags) { uint16_t offset; ; offset = (uint16_t)filterNumber * 16U; __eallow(); // Low, high threshold, Modulator failure if((intFlags & (0x200U | 0x40U | 0x20U)) != 0U) { // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx (*((volatile uint16_t *)(base + 0x15U + offset))) |= (intFlags & (0x200U | 0x40U | 0x20U)); } // Data filter acknowledge interrupt if((intFlags & 0x1U) != 0U) { (*((volatile uint16_t *)(base + 0x11U + offset))) |= 0x200U; } // FIFO , FIFO overflow interrupt if((intFlags & (0x1000U | 0x8000U)) != 0U) { // Set OVFIEN or FFIEN bits of SDFM_O_SDFIFOCTLx (*((volatile uint16_t *)(base + 0x1DU + offset))) |= (intFlags & (0x1000U | 0x8000U)); } __edis(); } //***************************************************************************** // //! Disable SDFM interrupts. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param intFlags is the interrupt source. //! //! This function disables the low threshold , high threshold or modulator //! failure interrupt as determined by intFlags for the filter //! specified by filterNumber. //! Valid values for intFlags are: //! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, //! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT, SDFM_FIFO_INTERRUPT, //! SDFM_FIFO_OVERFLOW_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT //! //! \return None. // //***************************************************************************** static inline void SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t intFlags) { uint16_t offset; ; offset = (uint16_t)filterNumber * 16U; __eallow(); // Low, high threshold, modulator failure interrupts if((intFlags & (0x200U | 0x40U | 0x20U)) != 0U) { // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx (*((volatile uint16_t *)(base + 0x15U + offset))) &= ~(intFlags & (0x200U | 0x40U | 0x20U)); } // Data filter acknowledge interrupt if((intFlags & 0x1U) != 0U) { (*((volatile uint16_t *)(base + 0x11U + offset))) &= ~0x200U; } // FIFO , FIFO overflow interrupt if((intFlags & (0x1000U | 0x8000U)) != 0U) { // Set OVFIEN or FFIEN bits of SDFM_O_SDFIFOCTLx (*((volatile uint16_t *)(base + 0x1DU + offset))) &= ~(intFlags & (0x1000U | 0x8000U)); } __edis(); } //***************************************************************************** // //! Set the comparator filter type. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param filterType is the comparator filter type or structure. //! //! This function sets the Comparator filter type or structure to be used as //! specified by filterType for the selected filter number as specified by //! filterNumber. //! //! \return None. //***************************************************************************** static inline void SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_FilterType filterType) { uint32_t address; ; address = base + 0x15U + ((uint32_t)filterNumber * 16U); // write to CS1_CS0 bits __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x180U)) | ((uint16_t)filterType << 3U); __edis(); } //***************************************************************************** // //! Set Comparator filter over sampling ratio. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param overSamplingRatio is the comparator filter over sampling ration. //! //! This function sets the comparator filter oversampling ratio for the filter //! specified by the filterNumber.Valid values for the variable //! overSamplingRatio are 0 to 31 inclusive. //! The actual oversampling ratio will be this value plus one. //! //! \return None. //***************************************************************************** static inline void SDFM_setCompFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t overSamplingRatio) { uint32_t address; ; ; address = base + 0x15U + ((uint32_t)filterNumber * 16U); // write to COSR bits __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x1FU)) | overSamplingRatio; __edis(); } //***************************************************************************** // //! Get the filter data output. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the latest data filter output. Depending on the //! filter data output format selected, the valid value will be the lower 16 //! bits or the whole 32 bits of the returned value. //! //! \return Returns the latest data filter output. //***************************************************************************** static inline uint32_t SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDDATA bits return((*((volatile uint32_t *)(base + 0x16U + ((uint32_t)filterNumber * 16U))))); } //***************************************************************************** // //! Get the Comparator threshold status. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the Comparator output threshold status for the given //! filterNumber. //! //! \return Returns the following status flags. //! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the //! specified threshold. //! - \b SDFM_OUTPUT_ABOVE_THRESHOLD if the output is above the high //! threshold //! - \b SDFM_OUTPUT_BELOW_THRESHOLD if the output is below the low //! threshold. //! //***************************************************************************** static inline SDFM_OutputThresholdStatus SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDIFLG IFH1, IFL1, IFH2, IFL2, etc ... bits return((SDFM_OutputThresholdStatus)(((*((volatile uint32_t *)(base + 0x0U))) >> (2U* (uint16_t)filterNumber)) & 0x3U)); } //***************************************************************************** // //! Get the Modulator status. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the Modulator status. //! //! \return Returns true if the Modulator is operating normally //! Returns false if the Modulator has failed //! //***************************************************************************** static inline _Bool SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDIFLG MF1, MF2, MF3 OR MF4 bits return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 8U)) & 0x1U) != 0x1U); } //***************************************************************************** // //! Check if new Filter data is available. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns new filter data status. //! //! \return Returns \b true if new filter data is available //! Returns \b false if no new filter data is available //! //***************************************************************************** static inline _Bool SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDIFLG AF1, AF2, AF3 OR AF4 bits return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 12U)) & 0x1U) == 0x1U); } //***************************************************************************** // //! Check if FIFO buffer is overflowed. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the status of the FIFO buffer overflow for the given //! filter value. //! //! \return Returns \b true if FIFO buffer is overflowed //! Returns \b false if FIFO buffer is not overflowed //! //***************************************************************************** static inline _Bool SDFM_getFIFOOverflowStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDIFLG SDFFOVF1, SDFFOVF2, SDFFOVF3 OR SDFFOVF4 bits return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 16U)) & 0x1U) == 0x1U); } //***************************************************************************** // //! Check FIFO buffer interrupt status. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the status of the FIFO buffer interrupt for the given //! filter. //! //! \return Returns \b true if FIFO buffer interrupt has occurred. //! Returns \b false if FIFO buffer interrupt has not occurred. //! //***************************************************************************** static inline _Bool SDFM_getFIFOISRStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDIFLG SDFFINT1, SDFFINT2, SDFFINT3 OR SDFFINT4 bits return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 20U)) & 0x1U) == 0x1U); } //***************************************************************************** // //! Get pending interrupt. //! //! \param base is the base address of the SDFM module //! //! This function returns any pending interrupt status. //! //! \return Returns \b true if there is a pending interrupt. //! Returns \b false if no interrupt is pending. //! //***************************************************************************** static inline _Bool SDFM_getIsrStatus(uint32_t base) { ; // Read SDIFLG MIF return(((*((volatile uint32_t *)(base + 0x0U))) >> 31U) == 0x1U); } //***************************************************************************** // //! Clear pending flags. //! //! \param base is the base address of the SDFM module //! \param flag is the SDFM status //! //! This function clears the specified pending interrupt flag. //! Valid values are //! SDFM_MASTER_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG, //! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG, //! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG, //! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG, //! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG, //! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG, //! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG, //! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG, //! SDFM_FILTER_4_LOW_THRESHOLD_FLAG,SDFM_FILTER_1_FIFO_OVERFLOW_FLAG, //! SDFM_FILTER_2_FIFO_OVERFLOW_FLAG,SDFM_FILTER_3_FIFO_OVERFLOW_FLAG //! SDFM_FILTER_4_FIFO_OVERFLOW_FLAG,SDFM_FILTER_1_FIFO_INTERRUPT_FLAG, //! SDFM_FILTER_2_FIFO_INTERRUPT_FLAG,SDFM_FILTER_3_FIFO_INTERRUPT_FLAG //! SDFM_FILTER_4_FIFO_INTERRUPT_FLAG or any combination of the above flags. //! //! \return None //! //***************************************************************************** static inline void SDFM_clearInterruptFlag(uint32_t base, uint32_t flag) { ; ; // Write to SDIFLGCLR register (*((volatile uint32_t *)(base + 0x2U))) |= flag; } //***************************************************************************** // //! Enable master interrupt. //! //! \param base is the base address of the SDFM module //! //! This function enables the master SDFM interrupt. //! //! \return None //! //***************************************************************************** static inline void SDFM_enableMasterInterrupt(uint32_t base) { ; // Set SDCTL MIE bit __eallow(); (*((volatile uint16_t *)(base + 0x4U))) |= 0x2000U; __edis(); } //***************************************************************************** // //! Disable master interrupt. //! //! \param base is the base address of the SDFM module //! //! This function disables the master SDFM interrupt. //! //! \return None //! //***************************************************************************** static inline void SDFM_disableMasterInterrupt(uint32_t base) { ; // Clear SDCTL MIE bit __eallow(); (*((volatile uint16_t *)(base + 0x4U))) &= ~0x2000U; __edis(); } //***************************************************************************** // //! Enable master interrupt. //! //! \param base is the base address of the SDFM module //! //! This function enables master filter. //! //! \return None //! //***************************************************************************** static inline void SDFM_enableMasterFilter(uint32_t base) { ; // Set SDMFILEN MFE bit __eallow(); (*((volatile uint16_t *)(base + 0x6U))) |= 0x800U; __edis(); } //***************************************************************************** // //! Disable master filter. //! //! \param base is the base address of the SDFM module //! //! This function disables master filter. //! //! \return None //! //***************************************************************************** static inline void SDFM_disableMasterFilter(uint32_t base) { ; // clear SDMFILEN MFE bit __eallow(); (*((volatile uint16_t *)(base + 0x6U))) &= ~0x800U; __edis(); } //***************************************************************************** // //! Return the FIFO data count //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the FIFO data count. //! //! \return Returns the number of data words available in FIFO buffer. // //***************************************************************************** static inline uint16_t SDFM_getFIFODataCount(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDFFST return(((*((volatile uint16_t *)(base + 0x1DU + ((uint32_t)filterNumber * 16U)))) & 0x7C0U) >> 6U); } //***************************************************************************** // //! Return the Comparator sinc filter data //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the Comparator sinc filter data output. //! //! \return Returns the Comparator sinc filter data output. //! // //***************************************************************************** static inline uint16_t SDFM_getComparatorSincData(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDCDATA return((*((volatile uint16_t *)(base + 0x1AU + ((uint32_t)filterNumber * 16U))))); } //***************************************************************************** // //! Return the FIFO data //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the latest FIFO data. //! //! \return Returns the latest FIFO data. //! //! \note Discard the upper 16 bits if the output data format is 16bits. // //***************************************************************************** static inline uint32_t SDFM_getFIFOData(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read SDDATFIFO return((*((volatile uint32_t *)(base + 0x18U + ((uint32_t)filterNumber * 16U))))); } //***************************************************************************** // //! Set the FIFO interrupt level. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param fifoLevel is the FIFO interrupt level. //! //! This function sets the FIFO interrupt level. Interrupt is generated when //! the FIFO buffer word count gets to or exceeds the value of \e fifoLevel. //! Maximum value for \e fifoLevel is 16. //! //! \return None. // //***************************************************************************** static inline void SDFM_setFIFOInterruptLevel(uint32_t base, SDFM_FilterNumber filterNumber, uint16_t fifoLevel) { uint32_t address; ; ; address = base + 0x1DU + ((uint32_t)filterNumber * 16U); // Write to SDFFIL bit __eallow(); (*((volatile uint16_t *)(address))) = (((*((volatile uint16_t *)(address))) & (~0x1FU)) | fifoLevel); __edis(); } //***************************************************************************** // //! Set data ready interrupt source. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param dataReadySource is the data ready interrupt source. //! //! This function sets the data ready interrupt source. //! Valid values for \e dataReadySource: //! - SDFM_DATA_READY_SOURCE_DIRECT - Direct data ready //! - SDFM_DATA_READY_SOURCE_FIFO - FIFO data ready. //! //! \return None. // //***************************************************************************** static inline void SDFM_setDataReadyInterruptSource(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_DataReadyInterruptSource dataReadySource) { uint32_t address; ; address = base + 0x1DU + ((uint32_t)filterNumber * 16U); // write to DRINTSEL __eallow(); (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x4000U) | ((uint16_t)dataReadySource << 14U); __edis(); } //***************************************************************************** // //! Get the wait-for-sync event status. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function returns the Wait-for-Sync event status. //! //! \return Returns true if sync event has occurred. //! Returns false if sync event has not occurred. // //***************************************************************************** static inline _Bool SDFM_getWaitForSyncStatus(uint32_t base, SDFM_FilterNumber filterNumber) { ; // Read WTSYNFLG bit return((((*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) & 0x80U) >> 7U) == 0x1U); } //***************************************************************************** // //! Clear the Wait-for-sync event status. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function clears the Wait-for-sync event status. //! //! \return None. // //***************************************************************************** static inline void SDFM_clearWaitForSyncFlag(uint32_t base, SDFM_FilterNumber filterNumber) { ; __eallow(); // Clear WTSYNCLR bit (*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) |= 0x100U; __edis(); } //***************************************************************************** // //! Enable wait for sync mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function enables the wait for sync mode. Data to FIFO will be written //! only after PWM sync event. //! //! \return None. // //***************************************************************************** static inline void SDFM_enableWaitForSync(uint32_t base, SDFM_FilterNumber filterNumber) { ; __eallow(); // Set WTSYNCEN bit (*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) |= 0x40U; __edis(); } //***************************************************************************** // //! Disable wait for sync mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! //! This function disables the wait for sync mode. Data to FIFO will be written //! every Data ready event. //! //! \return None. // //***************************************************************************** static inline void SDFM_disableWaitForSync(uint32_t base, SDFM_FilterNumber filterNumber) { ; __eallow(); // Clear WTSYNCEN bit (*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) &= ~0x40U; __edis(); } //***************************************************************************** // //! Set the PWM sync mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param syncSource is the PWM sync source. //! //! This function sets the PWM sync source for the specific SDFM filter. Valid //! values for syncSource are SDFM_SYNC_PWMx_CMPy. Where x ranges from 1 to 8 //! Representing PWM1 to PWM8 respectively and y ranges from A to D //! representing PWM comparators A to D. //! //! \return None. // //***************************************************************************** static inline void SDFM_setPWMSyncSource(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_PWMSyncSource syncSource) { uint32_t address; ; address = base + 0x1EU + ((uint32_t)filterNumber * 16U); __eallow(); // write to SYNCSEL bits (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x3FU) | (uint16_t)syncSource; __edis(); } //***************************************************************************** // //! Set FIFO clear on sync mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param fifoClearSyncMode is the FIFO clear on sync mode. //! //! This function sets the FIFO clear mode for the specified filter when a sync //! happens depending on the value of fifoClearSyncMode. //! Valid values for fifoClearSyncMode are: //! - SDFM_FIFO_NOT_CLEARED_ON_SYNC - FIFO is not cleared on sync. //! - SDFM_FIFO_CLEARED_ON_SYNC - FIFO is cleared on sync. //! //! \return None. // //***************************************************************************** static inline void SDFM_setFIFOClearOnSyncMode(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_FIFOClearSyncMode fifoClearSyncMode) { uint32_t address; ; address = base + 0x1EU + ((uint32_t)filterNumber * 16U); __eallow(); // write to FFSYNCCLREN bit (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x200U) | ((uint16_t)fifoClearSyncMode << 9U); __edis(); } //***************************************************************************** // //! Set Wait-for-sync clear mode. //! //! \param base is the base address of the SDFM module //! \param filterNumber is the filter number. //! \param syncClearMode is the wait-for-sync clear mode. //! //! This function sets the Wait-For-sync clear mode depending on the value of //! syncClearMode. //! Valid values for syncClearMode are: //! - SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC - Wait-for-sync flag is cleared by //! invoking SDFM_clearWaitForSyncFlag(). //! - SDFM_AUTO_CLEAR_WAIT_FOR_SYNC - Wait-for-sync flag is cleared //! automatically on FIFO interrupt. //! //! \return None. // //***************************************************************************** static inline void SDFM_setWaitForSyncClearMode(uint32_t base, SDFM_FilterNumber filterNumber, SDFM_WaitForSyncClearMode syncClearMode) { uint32_t address; ; address = base + 0x1EU + ((uint32_t)filterNumber * 16U); __eallow(); // write to WTSCLREN bit (*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x400U) | ((uint16_t)syncClearMode << 10U); __edis(); } //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Configure SDFM comparator high and low thresholds //! //! \param base is the base address of the SDFM module //! \param config1 is the filter number, filter type and over sampling ratio. //! \param config2 is high-level and low-level threshold values. //! \param config3 is the zero-cross threshold value. //! //! This function configures the comparator filter threshold values based on //! configurations config1 and config2. //! //! The config1 parameter is the logical OR of the filter number, filter type //! and oversampling ratio. //! The bit definitions for config1 are as follow: //! - config1.[3:0] filter number //! - config1.[7:4] filter type //! - config1.[15:8] Over sampling Ratio //! Valid values for filter number and filter type are defined in //! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. //! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling //! ratio ,which ranges [1,32] inclusive, in the appropriate bit location. //! For example the value //! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16)) //! will select Filter 1, SINC 2 type with an oversampling ratio of 16. //! //! The config2 parameter is the logical OR of the filter high and low //! threshold values. //! The bit definitions for config2 are as follow: //! - config2.[15:0] low threshold //! - config2.[31:16] high threshold //! The upper 16 bits define the high threshold and the lower //! 16 bits define the low threshold. //! SDFM_THRESHOLD(H,L) can be used to combine the high and low thresholds. //! //! The config3 parameter is the logical OR of the zero cross threshold //! enable flag and the zero-cross threshold value. //! The bit definitions for config3 are as follow: //! - config3.[15] - Enable or disable zero cross threshold. Valid values //! are 1 or 0 to enable or disable the zero cross threshold //! respectively. //! -config3.[14:0] - Zero Cross Threshold value. //! The SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) macro can be used to specify the //! zero-cross threshold value and OR the 1 to enable it. //! //! \return None. //! //***************************************************************************** extern void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2, uint16_t config3); //***************************************************************************** // //! Configure SDFM data filter //! //! \param base is the base address of the SDFM module //! \param config1 is the filter number, filter type and over sampling ratio //! configuration. //! \param config2 is filter switch, data representation and data shift values //! configuration. //! //! This function configures the data filter based on configurations //! config1 and config2. //! //! The config1 parameter is the logical OR of the filter number, filter type //! and oversampling ratio. //! The bit definitions for config1 are as follow: //! - config1.[3:0] Filter number //! - config1.[7:4] Filter type //! - config1.[15:8] Over sampling Ratio //! Valid values for filter number and filter type are defined in //! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. //! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling //! ratio , which ranges [1,256] inclusive , in the appropriate bit location //! for config1. For example the value //! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64)) //! will select Filter 2 , SINC 3 type with an oversampling ratio of 64. //! //! The config2 parameter is the logical OR of data representation, filter //! switch, and data shift values //! The bit definitions for config2 are as follow: //! - config2.[0] Data representation //! - config2.[1] Filter switch //! - config2.[15:2] Shift values //! Valid values for data representation are given in SDFM_OutputDataFormat //! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the //! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value //! of the data shift value,which ranges [0,31] inclusive, in the appropriate //! bit location for config2. //! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data //! representation format. //! //! \return None. //! //***************************************************************************** extern void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2); //***************************************************************************** // //! Configure SDFM comparator Zero Cross threshold //! //! \param base is the base address of the SDFM module //! \param config1 is the filter number, filter type and over sampling ratio. //! \param config2 is the zero cross threshold value. //! //! This function configures the comparator filter zero cross threshold values //! based on configurations config1 and config2. //! //! The config1 parameter is the logical OR of the filter number, filter type //! and oversampling ratio. //! The bit definitions for config1 are as follow: //! - config1.[3:0] filter number //! - config1.[7:4] filter type //! - config1.[15:8] Over sampling Ratio //! Valid values for filter number and filter type are defined in //! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. //! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling //! ratio ,which ranges [1,32] inclusive, in the appropriate bit location. //! For example the value //! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16)) //! will select Filter 1 , SINC 2 type with an oversampling ratio of 16. //! //! The config2 parameter is the value of the zero cross threshold. The maximum //! acceptable value is 32767. //! //! \return None. //! //***************************************************************************** extern void SDFM_configZeroCrossComparator(uint32_t base, uint16_t config1, uint16_t config2); //***************************************************************************** // //! Configure SDFM data filter FIFO //! //! \param base is the base address of the SDFM module //! \param config1 is the filter number, filter type and over sampling ratio //! configuration. //! \param config2 is filter switch, data representation and data shift values //! and FIFO level configuration. //! //! This function enables and configures the data filter FIFO based on //! configurations config1 and config2. //! //! The config1 parameter is the logical OR of the filter number, filter type //! and oversampling ratio. //! The bit definitions for config1 are as follow: //! - config1.[3:0] filter number //! - config1.[7:4] filter type //! - config1.[15:8] Over sampling Ratio //! Valid values for filter number and filter type are defined in //! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. //! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling //! ratio , which ranges [1,256] inclusive , in the appropriate bit location //! for config1. For example the value //! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64)) //! will select Filter 2 , SINC 3 type with an oversampling ratio of 64. //! //! The config2 parameter is the logical OR of data representation, filter //! switch, data shift value, and FIFO level //! The bit definitions for config2 are as follow: //! - config2.[0] Data representation //! - config2.[1] filter switch. //! - config2.[6:2] shift values. //! - config2.[15:7] FIFO level //! Valid values for data representation are given in SDFM_OutputDataFormat //! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the //! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value //! of the data shift value,which ranges [0,31] inclusive, in the appropriate //! bit location for config2. //! The value of FIFO level ranges [1,16] inclusive. The macro //! SDFM_SET_FIFO_LEVEL(X) can be used to set the value of the FIFO level. //! //! \return None. //! //***************************************************************************** extern void SDFM_configDataFilterFIFO(uint32_t base, uint16_t config1, uint16_t config2); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: spi.h // // TITLE: C28x SPI driver. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup spi_api SPI //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_spi.h // // TITLE: Definitions for the SPI registers. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the SPI register offsets // //***************************************************************************** // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the SPICCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPICTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPISTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPIBRR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPIFFTX register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPIFFRX register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPIFFCT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SPIPRI register // //***************************************************************************** //***************************************************************************** // // Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(), // and SPI_clearInterruptStatus() as the intFlags parameter, and returned by // SPI_getInterruptStatus(). // //***************************************************************************** //***************************************************************************** // //! Values that can be passed to SPI_setConfig() as the \e protocol parameter. // //***************************************************************************** typedef enum { //! Mode 0. Polarity 0, phase 0. Rising edge without delay. SPI_PROT_POL0PHA0 = 0x0000U, //! Mode 1. Polarity 0, phase 1. Rising edge with delay. SPI_PROT_POL0PHA1 = 0x0002U, //! Mode 2. Polarity 1, phase 0. Falling edge without delay. SPI_PROT_POL1PHA0 = 0x0001U, //! Mode 3. Polarity 1, phase 1. Falling edge with delay. SPI_PROT_POL1PHA1 = 0x0003U } SPI_TransferProtocol; //***************************************************************************** // //! Values that can be passed to SPI_setConfig() as the \e mode parameter. // //***************************************************************************** typedef enum { SPI_MODE_SLAVE = 0x0002U, //!< SPI slave SPI_MODE_MASTER = 0x0006U, //!< SPI master SPI_MODE_SLAVE_OD = 0x0000U, //!< SPI slave w/ output (TALK) disabled SPI_MODE_MASTER_OD = 0x0004U //!< SPI master w/ output (TALK) disabled } SPI_Mode; //***************************************************************************** // //! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel //! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel //! parameter, and returned by SPI_getTxFIFOStatus(). // //***************************************************************************** typedef enum { SPI_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty SPI_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty SPI_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full SPI_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full SPI_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full SPI_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full SPI_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full SPI_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full SPI_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full SPI_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full SPI_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full SPI_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full SPI_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full SPI_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full SPI_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full SPI_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full SPI_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full SPI_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full SPI_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full } SPI_TxFIFOLevel; //***************************************************************************** // //! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel //! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel //! parameter, and returned by SPI_getRxFIFOStatus(). // //***************************************************************************** typedef enum { SPI_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty SPI_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty SPI_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full SPI_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full SPI_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full SPI_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full SPI_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full SPI_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full SPI_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full SPI_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full SPI_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full SPI_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full SPI_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full SPI_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full SPI_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full SPI_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full SPI_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full SPI_FIFO_RX16 = 0x0010U, //!< Receive FIFO full SPI_FIFO_RXFULL = 0x0010U, //!< Receive FIFO full SPI_FIFO_RXDEFAULT = 0x001FU //!< To prevent interrupt at reset } SPI_RxFIFOLevel; //***************************************************************************** // //! Values that can be passed to SPI_setEmulationMode() as the \e mode //! parameter. // //***************************************************************************** typedef enum { //! Transmission stops after midway in the bit stream SPI_EMULATION_STOP_MIDWAY = 0x0000U, //! Continue SPI operation regardless SPI_EMULATION_FREE_RUN = 0x0010U, //! Transmission will stop after a started transmission completes SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U } SPI_EmulationMode; //***************************************************************************** // //! Values that can be passed to SPI_setSTESignalPolarity() as the \e polarity //! parameter. // //***************************************************************************** typedef enum { SPI_STE_ACTIVE_LOW = 0x0000U, //!< SPISTE is active low (normal) SPI_STE_ACTIVE_HIGH = 0x2U //!< SPISTE is active high (inverted) } SPI_STEPolarity; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! Checks an SPI base address. //! //! \param base specifies the SPI module base address. //! //! This function determines if a SPI module base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** //***************************************************************************** // //! Enables the serial peripheral interface. //! //! \param base specifies the SPI module base address. //! //! This function enables operation of the serial peripheral interface. The //! serial peripheral interface must be configured before it is enabled. //! //! \return None. // //***************************************************************************** static inline void SPI_enableModule(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x0U))) |= 0x80U; } //***************************************************************************** // //! Disables the serial peripheral interface. //! //! \param base specifies the SPI module base address. //! //! This function disables operation of the serial peripheral interface. Call //! this function before doing any configuration. //! //! \return None. // //***************************************************************************** static inline void SPI_disableModule(uint32_t base) { // // Check the arguments. // ; (*((volatile uint16_t *)(base + 0x0U))) &= ~(0x80U); } //***************************************************************************** // //! Enables the transmit and receive FIFOs. //! //! \param base is the base address of the SPI port. //! //! This functions enables the transmit and receive FIFOs in the SPI. //! //! \return None. // //***************************************************************************** static inline void SPI_enableFIFO(uint32_t base) { // // Check the arguments. // ; // // Enable the FIFO. // (*((volatile uint16_t *)(base + 0xAU))) |= 0x4000U | 0x2000U; (*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U; } //***************************************************************************** // //! Disables the transmit and receive FIFOs. //! //! \param base is the base address of the SPI port. //! //! This functions disables the transmit and receive FIFOs in the SPI. //! //! \return None. // //***************************************************************************** static inline void SPI_disableFIFO(uint32_t base) { // // Check the arguments. // ; // // Disable the FIFO. // (*((volatile uint16_t *)(base + 0xAU))) &= ~(0x4000U | 0x2000U); (*((volatile uint16_t *)(base + 0xBU))) &= ~0x2000U; } //***************************************************************************** // //! Resets the transmit FIFO. //! //! \param base is the base address of the SPI port. //! //! This function resets the transmit FIFO, setting the FIFO pointer back to //! zero. //! //! \return None. // //***************************************************************************** static inline void SPI_resetTxFIFO(uint32_t base) { // // Check the arguments. // ; // // Reset the TX FIFO. // (*((volatile uint16_t *)(base + 0xAU))) &= ~0x2000U; (*((volatile uint16_t *)(base + 0xAU))) |= 0x2000U; } //***************************************************************************** // //! Resets the receive FIFO. //! //! \param base is the base address of the SPI port. //! //! This function resets the receive FIFO, setting the FIFO pointer back to //! zero. //! //! \return None. // //***************************************************************************** static inline void SPI_resetRxFIFO(uint32_t base) { // // Check the arguments. // ; // // Reset the RX FIFO. // (*((volatile uint16_t *)(base + 0xBU))) &= ~0x2000U; (*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U; } //***************************************************************************** // //! Sets the FIFO level at which interrupts are generated. //! //! \param base is the base address of the SPI port. //! \param txLevel is the transmit FIFO interrupt level, specified as //! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or //! \b SPI_FIFO_TX16. //! \param rxLevel is the receive FIFO interrupt level, specified as //! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or //! \b SPI_FIFO_RX16. //! //! This function sets the FIFO level at which transmit and receive interrupts //! are generated. //! //! \return None. // //***************************************************************************** static inline void SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel, SPI_RxFIFOLevel rxLevel) { // // Check the arguments. // ; // // Set the FIFO interrupt levels. // (*((volatile uint16_t *)(base + 0xAU))) = ((*((volatile uint16_t *)(base + 0xAU))) & (~0x1FU)) | (uint16_t)txLevel; (*((volatile uint16_t *)(base + 0xBU))) = ((*((volatile uint16_t *)(base + 0xBU))) & (~0x1FU)) | (uint16_t)rxLevel; } //***************************************************************************** // //! Gets the FIFO level at which interrupts are generated. //! //! \param base is the base address of the SPI port. //! \param txLevel is a pointer to storage for the transmit FIFO level, //! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, //! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16. //! \param rxLevel is a pointer to storage for the receive FIFO level, //! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, //! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16. //! //! This function gets the FIFO level at which transmit and receive interrupts //! are generated. //! //! \return None. // //***************************************************************************** static inline void SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel, SPI_RxFIFOLevel *rxLevel) { // // Check the arguments. // ; // // Extract the transmit and receive FIFO levels. // *txLevel = (SPI_TxFIFOLevel)((*((volatile uint16_t *)(base + 0xAU))) & 0x1FU); *rxLevel = (SPI_RxFIFOLevel)((*((volatile uint16_t *)(base + 0xBU))) & 0x1FU); } //***************************************************************************** // //! Get the transmit FIFO status //! //! \param base is the base address of the SPI port. //! //! This function gets the current number of words in the transmit FIFO. //! //! \return Returns the current number of words in the transmit FIFO specified //! as one of the following: //! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3, //! ..., or \b SPI_FIFO_TX16 // //***************************************************************************** static inline SPI_TxFIFOLevel SPI_getTxFIFOStatus(uint32_t base) { // // Check the arguments. // ; // // Get the current FIFO status // return((SPI_TxFIFOLevel)(((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) >> 8U)); } //***************************************************************************** // //! Get the receive FIFO status //! //! \param base is the base address of the SPI port. //! //! This function gets the current number of words in the receive FIFO. //! //! \return Returns the current number of words in the receive FIFO specified //! as one of the following: //! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3, //! ..., or \b SPI_FIFO_RX16 // //***************************************************************************** static inline SPI_RxFIFOLevel SPI_getRxFIFOStatus(uint32_t base) { // // Check the arguments. // ; // // Get the current FIFO status // return((SPI_RxFIFOLevel)(((*((volatile uint16_t *)(base + 0xBU))) & 0x1F00U) >> 8U)); } //***************************************************************************** // //! Determines whether the SPI transmitter is busy or not. //! //! \param base is the base address of the SPI port. //! //! This function allows the caller to determine whether all transmitted bytes //! have cleared the transmitter hardware. If \b false is returned, then the //! transmit FIFO is empty and all bits of the last transmitted word have left //! the hardware shift register. This function is only valid when operating in //! FIFO mode. //! //! \return Returns \b true if the SPI is transmitting or \b false if all //! transmissions are complete. // //***************************************************************************** static inline _Bool SPI_isBusy(uint32_t base) { // // Check the arguments. // ; // // Determine if the SPI is busy. // return(((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) != 0U); } //***************************************************************************** // //! Puts a data element into the SPI transmit buffer. //! //! \param base specifies the SPI module base address. //! \param data is the left-justified data to be transmitted over SPI. //! //! This function places the supplied data into the transmit buffer of the //! specified SPI module. //! //! \note The data being sent must be left-justified in \e data. The lower //! 16 - N bits will be discarded where N is the data width selected in //! SPI_setConfig(). For example, if configured for a 6-bit data width, the //! lower 10 bits of data will be discarded. //! //! \return None. // //***************************************************************************** static inline void SPI_writeDataNonBlocking(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Write data to the transmit buffer. // (*((volatile uint16_t *)(base + 0x8U))) = data; } //***************************************************************************** // //! Gets a data element from the SPI receive buffer. //! //! \param base specifies the SPI module base address. //! //! This function gets received data from the receive buffer of the specified //! SPI module and returns it. //! //! \note Only the lower N bits of the value written to \e data contain valid //! data, where N is the data width as configured by SPI_setConfig(). For //! example, if the interface is configured for 8-bit data width, only the //! lower 8 bits of the value written to \e data contain valid data. //! //! \return Returns the word of data read from the SPI receive buffer. // //***************************************************************************** static inline uint16_t SPI_readDataNonBlocking(uint32_t base) { // // Check the arguments. // ; // // Check for data to read. // return((*((volatile uint16_t *)(base + 0x7U)))); } //***************************************************************************** // //! Waits for space in the FIFO and then puts data into the transmit buffer. //! //! \param base specifies the SPI module base address. //! \param data is the left-justified data to be transmitted over SPI. //! //! This function places the supplied data into the transmit buffer of the //! specified SPI module once space is available in the transmit FIFO. This //! function should only be used when the FIFO is enabled. //! //! \note The data being sent must be left-justified in \e data. The lower //! 16 - N bits will be discarded where N is the data width selected in //! SPI_setConfig(). For example, if configured for a 6-bit data width, the //! lower 10 bits of data will be discarded. //! //! \return None. // //***************************************************************************** static inline void SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Wait until space is available in the receive FIFO. // while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL) { } // // Write data to the transmit buffer. // (*((volatile uint16_t *)(base + 0x8U))) = data; } //***************************************************************************** // //! Waits for data in the FIFO and then reads it from the receive buffer. //! //! \param base specifies the SPI module base address. //! //! This function waits until there is data in the receive FIFO and then reads //! received data from the receive buffer. This function should only be used //! when FIFO mode is enabled. //! //! \note Only the lower N bits of the value written to \e data contain valid //! data, where N is the data width as configured by SPI_setConfig(). For //! example, if the interface is configured for 8-bit data width, only the //! lower 8 bits of the value written to \e data contain valid data. //! //! \return Returns the word of data read from the SPI receive buffer. // //***************************************************************************** static inline uint16_t SPI_readDataBlockingFIFO(uint32_t base) { // // Check the arguments. // ; // // Wait until data is available in the receive FIFO. // while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY) { } // // Check for data to read. // return((*((volatile uint16_t *)(base + 0x7U)))); } //***************************************************************************** // //! Waits for the transmit buffer to empty and then writes data to it. //! //! \param base specifies the SPI module base address. //! \param data is the left-justified data to be transmitted over SPI. //! //! This function places the supplied data into the transmit buffer of the //! specified SPI module once it is empty. This function should not be used //! when FIFO mode is enabled. //! //! \note The data being sent must be left-justified in \e data. The lower //! 16 - N bits will be discarded where N is the data width selected in //! SPI_setConfig(). For example, if configured for a 6-bit data width, the //! lower 10 bits of data will be discarded. //! //! \return None. // //***************************************************************************** static inline void SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data) { // // Check the arguments. // ; // // Wait until the transmit buffer is not full. // while(((*((volatile uint16_t *)(base + 0x2U))) & 0x20U) != 0U) { } // // Write data to the transmit buffer. // (*((volatile uint16_t *)(base + 0x8U))) = data; } //***************************************************************************** // //! Waits for data to be received and then reads it from the buffer. //! //! \param base specifies the SPI module base address. //! //! This function waits for data to be received and then reads it from the //! receive buffer of the specified SPI module. This function should not be //! used when FIFO mode is enabled. //! //! \note Only the lower N bits of the value written to \e data contain valid //! data, where N is the data width as configured by SPI_setConfig(). For //! example, if the interface is configured for 8-bit data width, only the //! lower 8 bits of the value written to \e data contain valid data. //! //! \return Returns the word of data read from the SPI receive buffer. // //***************************************************************************** static inline uint16_t SPI_readDataBlockingNonFIFO(uint32_t base) { // // Check the arguments. // ; // // Wait until data has been received. // while(((*((volatile uint16_t *)(base + 0x2U))) & 0x40U) == 0U) { } // // Check for data to read. // return((*((volatile uint16_t *)(base + 0x7U)))); } //***************************************************************************** // //! Enables SPI 3-wire mode. //! //! \param base is the base address of the SPI port. //! //! This function enables 3-wire mode. When in master mode, this allows SPISIMO //! to become SPIMOMI and SPISOMI to become free for non-SPI use. When in slave //! mode, SPISOMI because the SPISISO pin and SPISIMO is free for non-SPI use. //! //! \return None. // //***************************************************************************** static inline void SPI_enableTriWire(uint32_t base) { // // Check the arguments. // ; // // Set the tri-wire bit to enable 3-wire mode. // (*((volatile uint16_t *)(base + 0xFU))) |= 0x1U; } //***************************************************************************** // //! Disables SPI 3-wire mode. //! //! \param base is the base address of the SPI port. //! //! This function disables 3-wire mode. SPI will operate in normal 4-wire mode. //! //! \return None. // //***************************************************************************** static inline void SPI_disableTriWire(uint32_t base) { // // Check the arguments. // ; // // Clear the tri-wire bit to disable 3-wire mode. // (*((volatile uint16_t *)(base + 0xFU))) &= ~0x1U; } //***************************************************************************** // //! Enables SPI loopback mode. //! //! \param base is the base address of the SPI port. //! //! This function enables loopback mode. This mode is only valid during master //! mode and is helpful during device testing as it internally connects SIMO //! and SOMI. //! //! \return None. // //***************************************************************************** static inline void SPI_enableLoopback(uint32_t base) { // // Check the arguments. // ; // // Set the bit that enables loopback mode. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x10U; } //***************************************************************************** // //! Disables SPI loopback mode. //! //! \param base is the base address of the SPI port. //! //! This function disables loopback mode. Loopback mode is disabled by default //! after reset. //! //! \return None. // //***************************************************************************** static inline void SPI_disableLoopback(uint32_t base) { // // Check the arguments. // ; // // Clear the bit that enables loopback mode. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x10U; } //***************************************************************************** // //! Set the slave select (SPISTE) signal polarity. //! //! \param base is the base address of the SPI port. //! \param polarity is the SPISTE signal polarity. //! //! This function sets the polarity of the slave select (SPISTE) signal. The //! two modes to choose from for the \e polarity parameter are //! \b SPI_STE_ACTIVE_LOW for active-low polarity (typical) and //! \b SPI_STE_ACTIVE_HIGH for active-high polarity (considered inverted). //! //! \note This has no effect on the STE signal when in master mode. It is only //! applicable to slave mode. //! //! \return None. // //***************************************************************************** static inline void SPI_setSTESignalPolarity(uint32_t base, SPI_STEPolarity polarity) { // // Check the arguments. // ; // // Write the polarity of the SPISTE signal to the register. // (*((volatile uint16_t *)(base + 0xFU))) = ((*((volatile uint16_t *)(base + 0xFU))) & ~0x2U) | (uint16_t)polarity; } //***************************************************************************** // //! Enables SPI high speed mode. //! //! \param base is the base address of the SPI port. //! //! This function enables high speed mode. //! //! \return None. // //***************************************************************************** static inline void SPI_enableHighSpeedMode(uint32_t base) { // // Check the arguments. // ; // // Set the bit that enables high speed mode. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x20U; } //***************************************************************************** // //! Disables SPI high speed mode. //! //! \param base is the base address of the SPI port. //! //! This function disables high speed mode. High speed mode is disabled by //! default after reset. //! //! \return None. // //***************************************************************************** static inline void SPI_disableHighSpeedMode(uint32_t base) { // // Check the arguments. // ; // // Clear the bit that enables high speed mode. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x20U; } //***************************************************************************** // //! Sets SPI emulation mode. //! //! \param base is the base address of the SPI port. //! \param mode is the emulation mode. //! //! This function sets the behavior of the SPI operation when an emulation //! suspend occurs. The \e mode parameter can be one of the following: //! //! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit //! stream. The rest of the bits will be transmitting after the suspend is //! deasserted. //! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the //! first SPICLK pulse, the transmission will not start. If it occurs later, //! the transmission will be completed. //! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a //! the suspend. //! //! \return None. // //***************************************************************************** static inline void SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode) { // // Check the arguments. // ; // // Write the desired emulation mode to the register. // (*((volatile uint16_t *)(base + 0xFU))) = ((*((volatile uint16_t *)(base + 0xFU))) & ~(0x10U | 0x20U)) | (uint16_t)mode; } //***************************************************************************** // //! Configures the serial peripheral interface. //! //! \param base specifies the SPI module base address. //! \param lspclkHz is the rate of the clock supplied to the SPI module //! (LSPCLK) in Hz. //! \param protocol specifies the data transfer protocol. //! \param mode specifies the mode of operation. //! \param bitRate specifies the clock rate in Hz. //! \param dataWidth specifies number of bits transferred per frame. //! //! This function configures the serial peripheral interface. It sets the SPI //! protocol, mode of operation, bit rate, and data width. //! //! The \e protocol parameter defines the data frame format. The \e protocol //! parameter can be one of the following values: \b SPI_PROT_POL0PHA0, //! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or //! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity //! and phase configurations: //! //! 
//! Polarity Phase       Mode
//!   0       0   SPI_PROT_POL0PHA0
//!   0       1   SPI_PROT_POL0PHA1
//!   1       0   SPI_PROT_POL1PHA0
//!   1       1   SPI_PROT_POL1PHA1
//!
//! //! The \e mode parameter defines the operating mode of the SPI module. The //! SPI module can operate as a master or slave; the SPI can also be be //! configured to disable output on its serial output line. The \e mode //! parameter can be one of the following values: \b SPI_MODE_MASTER, //! \b SPI_MODE_SLAVE, \b SPI_MODE_MASTER_OD or \b SPI_MODE_SLAVE_OD ("OD" //! indicates "output disabled"). //! //! The \e bitRate parameter defines the bit rate for the SPI. This bit rate //! must satisfy the following clock ratio criteria: //! //! - \e bitRate can be no greater than lspclkHz divided by 4. //! - \e lspclkHz / \e bitRate cannot be greater than 128. //! //! The \e dataWidth parameter defines the width of the data transfers and //! can be a value between 1 and 16, inclusive. //! //! The peripheral clock is the low speed peripheral clock. This value is //! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded //! if it is constant and known (to save the code/execution overhead of a call //! to SysCtl_getLowSpeedClock()). //! //! \note SPI operation should be disabled via SPI_disableModule() before any //! changes to its configuration. //! //! \return None. // //***************************************************************************** extern void SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth); //***************************************************************************** // //! Configures the baud rate of the serial peripheral interface. //! //! \param base specifies the SPI module base address. //! \param lspclkHz is the rate of the clock supplied to the SPI module //! (LSPCLK) in Hz. //! \param bitRate specifies the clock rate in Hz. //! //! This function configures the SPI baud rate. The \e bitRate parameter //! defines the bit rate for the SPI. This bit rate must satisfy the following //! clock ratio criteria: //! //! - \e bitRate can be no greater than \e lspclkHz divided by 4. //! - \e lspclkHz / \e bitRate cannot be greater than 128. //! //! The peripheral clock is the low speed peripheral clock. This value is //! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded //! if it is constant and known (to save the code/execution overhead of a call //! to SysCtl_getLowSpeedClock()). //! //! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate() //! if you wish to configure it separately from protocol and mode. //! //! \return None. // //***************************************************************************** extern void SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate); //***************************************************************************** // //! Enables individual SPI interrupt sources. //! //! \param base specifies the SPI module base address. //! \param intFlags is a bit mask of the interrupt sources to be enabled. //! //! This function enables the indicated SPI interrupt sources. Only the sources //! that are enabled can be reflected to the processor interrupt; disabled //! sources have no effect on the processor. The \e intFlags parameter can be //! any of the following values: //! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt //! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty //! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level //! interrupt (and RX FIFO overflow) //! - \b SPI_INT_TXFF - TX FIFO level interrupt //! //! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, //! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with //! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. //! //! \return None. // //***************************************************************************** extern void SPI_enableInterrupt(uint32_t base, uint32_t intFlags); //***************************************************************************** // //! Disables individual SPI interrupt sources. //! //! \param base specifies the SPI module base address. //! \param intFlags is a bit mask of the interrupt sources to be disabled. //! //! This function disables the indicated SPI interrupt sources. The //! \e intFlags parameter can be any of the following values: //! - \b SPI_INT_RX_OVERRUN //! - \b SPI_INT_RX_DATA_TX_EMPTY //! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW) //! - \b SPI_INT_TXFF //! //! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, //! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with //! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. //! //! \return None. // //***************************************************************************** extern void SPI_disableInterrupt(uint32_t base, uint32_t intFlags); //***************************************************************************** // //! Gets the current interrupt status. //! //! \param base specifies the SPI module base address. //! //! This function returns the interrupt status for the SPI module. //! //! \return The current interrupt status, enumerated as a bit field of the //! following values: //! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt //! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty //! - \b SPI_INT_RXFF - RX FIFO level interrupt //! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow //! - \b SPI_INT_TXFF - TX FIFO level interrupt // //***************************************************************************** extern uint32_t SPI_getInterruptStatus(uint32_t base); //***************************************************************************** // //! Clears SPI interrupt sources. //! //! \param base specifies the SPI module base address. //! \param intFlags is a bit mask of the interrupt sources to be cleared. //! //! This function clears the specified SPI interrupt sources so that they no //! longer assert. This function must be called in the interrupt handler to //! keep the interrupts from being triggered again immediately upon exit. The //! \e intFlags parameter can consist of a bit field of the following values: //! - \b SPI_INT_RX_OVERRUN //! - \b SPI_INT_RX_DATA_TX_EMPTY //! - \b SPI_INT_RXFF //! - \b SPI_INT_RXFF_OVERFLOW //! - \b SPI_INT_TXFF //! //! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive //! receive buffer, so it usually doesn't need to be cleared using this //! function. //! //! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, //! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with //! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. //! //! \return None. // //***************************************************************************** extern void SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: version.h // // TITLE: API to return the version number of the driverlib.lib in use. // //########################################################################### // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup version_api Version //! @{ // //***************************************************************************** //! Version number to be returned by Version_getLibVersion() //! //***************************************************************************** // //! Returns the driverlib version number //! //! This function can be used to check the version number of the driverlib.lib //! that is in use. The version number will take the format x.xx.xx.xx, so for //! example, if the function returns 2100200, the driverlib version being used //! is 2.10.02.00. //! //! \return Returns an integer value indicating the driverlib version. // //***************************************************************************** extern uint32_t Version_getLibVersion(void); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //############################################################################# // // FILE: device.h // // TITLE: Device setup for examples. // //############################################################################# // $TI Release: F28004x Support Library v1.05.00.00 $ // $Release Date: Thu Oct 18 15:43:57 CDT 2018 $ // $Copyright: // Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# // // Included Files // //***************************************************************************** // // Defines for pin numbers and other GPIO configuration // //***************************************************************************** // // ControlCARD // // // LEDs // // // CANA // // // CAN External Loopback // // // LINA // // // FSI // // // SPI // // // I2C // // // eQEP // // // EPWM // // // SCI for USB-to-UART adapter on FTDI chip // //***************************************************************************** // // Defines related to clock configuration // //***************************************************************************** // // 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). // // // Define to pass to SysCtl_setClock(). Will configure the clock as follows: // PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) // // // 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the // code below if a different clock configuration is used! // // // 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default // low speed peripheral clock divider of 4. Update the code below if a // different LSPCLK divider is used! // //***************************************************************************** // // Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro // will convert the desired delay in microseconds to the count value expected // by the function. \b x is the number of microseconds to delay. // //***************************************************************************** //***************************************************************************** // // Defines, Globals, and Header Includes related to Flash Support // //***************************************************************************** //***************************************************************************** // // Function Prototypes // //***************************************************************************** extern void Device_init(void); extern void Device_enableAllPeripherals(void); extern void Device_initGPIO(void); extern void __error__(char *filename, uint32_t line); /* * Copyright (c) 2015-2015 Texas Instruments Incorporated * * ==================================================== * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this * software is freely granted, provided that this notice * is preserved. * ==================================================== */ /* * from: @(#)fdlibm.h 5.1 93/09/24 * $FreeBSD$ */ #pragma diag_push #pragma CHECK_MISRA("-6.3") /* standard types required for standard headers */ #pragma CHECK_MISRA("-12.7") /* bitwise operators not allowed on signed ints */ #pragma CHECK_MISRA("-16.4") /* identifiers in fn defn/decl identical??? fabs/fabsf */ #pragma CHECK_MISRA("-19.1") /* only comments and preproc before #include */ #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ /*****************************************************************************/ /* _ti_config.h */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") #pragma CHECK_MISRA("-19.1") /* Common definitions */ /* C */ /* C89/C99 */ /* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It is intended to be used for functions like abort and atexit that are supposed to be declared noexcept only in C++14 mode. */ /* Target-specific definitions */ /*****************************************************************************/ /* linkage.h */ /* */ /* Copyright (c) 1998 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ /* No modifiers needed to access code */ /*--------------------------------------------------------------------------*/ /* Define _DATA_ACCESS ==> how to access RTS global or static data */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _IDECL ==> how inline functions are declared */ /*--------------------------------------------------------------------------*/ #pragma diag_pop #pragma diag_pop /*****************************************************************************/ /* _defs.h */ /* */ /* Copyright (c) 2015 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-8.1") /* visible prototypes */ #pragma CHECK_MISRA("-8.5") /* functions in header files */ #pragma CHECK_MISRA("-8.11") /* use static on fns with internal linkage */ #pragma CHECK_MISRA("-10.1") /* implicit conversion ... bool to int??? */ #pragma CHECK_MISRA("-12.1") /* operator precedence */ #pragma CHECK_MISRA("-12.2") /* different order of operations??? */ #pragma CHECK_MISRA("-12.4") /* RHS of &&/|| has side effects??? */ #pragma CHECK_MISRA("-12.7") /* Bitwise operators on signed types */ #pragma CHECK_MISRA("-14.7") /* single point of return */ #pragma CHECK_MISRA("-14.9") /* only compound statement after if/else */ #pragma CHECK_MISRA("-19.1") /* only comments and preproc before #include??? */ #pragma CHECK_MISRA("-19.4") /* macro expands to unparenthesized */ #pragma diag_suppress 1558 /* --float_operations_allowed checks */ /* This file is included in other user header files; take care not to pollute the namespace */ typedef unsigned long long __uint64_t; typedef unsigned long __uint32_t; /* normalize target-specific intrinsics */ /* always inline these functions so that calls to them don't appear in an object file and become part of the ABI. */ __inline int __isfinite(double d) { return (((((unsigned int)(__f32_bits_as_u32(d) >> 16)) & 0x7f80u) == 0x7f80u)) == 0; } __inline int __isfinitef(float f) { return (((((unsigned int)(__f32_bits_as_u32(f) >> 16)) & 0x7f80u) == 0x7f80u)) == 0; } __inline int __isfinitel(long double e) { return (((((unsigned int)(__f64_bits_as_u64(e) >> 48)) & 0x7ff0u) == 0x7ff0u)) == 0; } __inline int __isnan(double d) { return (((((unsigned int)(__f32_bits_as_u32(d) >> 16)) & 0x7f80u) == 0x7f80u)) && ((((__f32_bits_as_u32(d) & (((__uint32_t)(1) << (24-1)) - 1)) == 0)) == 0); } __inline int __isnanf(float f) { return (((((unsigned int)(__f32_bits_as_u32(f) >> 16)) & 0x7f80u) == 0x7f80u)) && ((((__f32_bits_as_u32(f) & (((__uint32_t)(1) << (24-1)) - 1)) == 0)) == 0); } __inline int __isnanl(long double e) { return (((((unsigned int)(__f64_bits_as_u64(e) >> 48)) & 0x7ff0u) == 0x7ff0u)) && ((((__f64_bits_as_u64(e) & (((__uint64_t)(1) << (53-1)) - 1)) == 0)) == 0); } __inline int __isnormal(double d) { return ((((((unsigned int)(__f32_bits_as_u32(d) >> (24-1))) & ((128u * 2) - 1)) == 0)) == 0) && ((((((unsigned int)(__f32_bits_as_u32(d) >> 16)) & 0x7f80u) == 0x7f80u)) == 0); } __inline int __isnormalf(float f) { return ((((((unsigned int)(__f32_bits_as_u32(f) >> (24-1))) & ((128u * 2) - 1)) == 0)) == 0) && ((((((unsigned int)(__f32_bits_as_u32(f) >> 16)) & 0x7f80u) == 0x7f80u)) == 0); } __inline int __isnormall(long double e) { return (((((__f64_bits_as_u64(e) >> (53-1)) & ((1024u * 2) - 1)) == 0)) == 0) && ((((((unsigned int)(__f64_bits_as_u64(e) >> 48)) & 0x7ff0u) == 0x7ff0u)) == 0); } __inline int __signbit(double d) { return (((__f32_bits_as_u32(d) & ((__uint32_t)(1) << (32-1))) == 0)) == 0; } __inline int __signbitf(float f) { return (((__f32_bits_as_u32(f) & ((__uint32_t)(1) << (32-1))) == 0)) == 0; } __inline int __signbitl(long double e) { return (((__f64_bits_as_u64(e) & ((__uint64_t)(1) << (64-1))) == 0)) == 0; } /* FreeBSD lib/libc/gen/isinf.c says "These routines belong in libm, but they must remain in libc for binary compat until we can bump libm's major version number" */ __inline int __isinff(float f) { return (((((unsigned int)(__f32_bits_as_u32(f) >> 16)) & 0x7f80u) == 0x7f80u)) && (((__f32_bits_as_u32(f) & (((__uint32_t)(1) << (24-1)) - 1)) == 0)); } __inline int __isinf (double d) { return (((((unsigned int)(__f32_bits_as_u32(d) >> 16)) & 0x7f80u) == 0x7f80u)) && (((__f32_bits_as_u32(d) & (((__uint32_t)(1) << (24-1)) - 1)) == 0)); } __inline int __isinfl(long double e) { return (((((unsigned int)(__f64_bits_as_u64(e) >> 48)) & 0x7ff0u) == 0x7ff0u)) && (((__f64_bits_as_u64(e) & (((__uint64_t)(1) << (53-1)) - 1)) == 0)); } /* Symbolic constants to classify floating point numbers. */ __inline int __fpclassifyf(float f) { if ((((((unsigned int)(__f32_bits_as_u32(f) >> 16)) & 0x7f80u) == 0x7f80u))) { if ((((__f32_bits_as_u32(f) & (((__uint32_t)(1) << (24-1)) - 1)) == 0))) return 1; else return 2; } if ((((((unsigned int)(__f32_bits_as_u32(f) >> (24-1))) & ((128u * 2) - 1)) == 0))) { if ((((__f32_bits_as_u32(f) & (((__uint32_t)(1) << (24-1)) - 1)) == 0))) return 0; else return (-2); } return (-1); } __inline int __fpclassify (double d) { if ((((((unsigned int)(__f32_bits_as_u32(d) >> 16)) & 0x7f80u) == 0x7f80u))) { if ((((__f32_bits_as_u32(d) & (((__uint32_t)(1) << (24-1)) - 1)) == 0))) return 1; else return 2; } if ((((((unsigned int)(__f32_bits_as_u32(d) >> (24-1))) & ((128u * 2) - 1)) == 0))) { if ((((__f32_bits_as_u32(d) & (((__uint32_t)(1) << (24-1)) - 1)) == 0))) return 0; else return (-2); } return (-1); } __inline int __fpclassifyl(long double e) { if ((((((unsigned int)(__f64_bits_as_u64(e) >> 48)) & 0x7ff0u) == 0x7ff0u))) { if ((((__f64_bits_as_u64(e) & (((__uint64_t)(1) << (53-1)) - 1)) == 0))) return 1; else return 2; } if (((((__f64_bits_as_u64(e) >> (53-1)) & ((1024u * 2) - 1)) == 0))) { if ((((__f64_bits_as_u64(e) & (((__uint64_t)(1) << (53-1)) - 1)) == 0))) return 0; else return (-2); } return (-1); } /* * Relevant target macros indicating hardware float support * * all * __TI_STRICT_FP_MODE__ * ARM * __ARM_FP * C2000 * __TMS320C28XX_FPU32__ * __TMS320C28XX_FPU64__ * __TMS320C28XX_TMU__ adds div, sqrt, sin, cos, atan, atan2 * C6000 * _TMS320C6700 indicates C67x or later */ #pragma diag_pop /* * ANSI/POSIX */ /* Symbolic constants to classify floating point numbers. */ /* * XOPEN/SVID */ /*---------------------------------------------------------------------------*/ /* If --fp_mode=relaxed is used and VFP is enabled, use the hardware square */ /* root directly instead of calling the sqrtx routine. This will not set */ /* errno if the argument is negative. */ /* */ /* This is done by defining sqrt to _relaxed_sqrt to allow other translation */ /* units to use the normal sqrt routine under strict mode. */ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /* TMU SUPPORT AND RELAXED MODE: USE INSTRINSICS. */ /*---------------------------------------------------------------------------*/ /* Disable double_t and float_t for C28x because of Motorware (AY 2015) */ double acos(double x); float acosf(float x); long double acosl(long double x); double asin(double x); float asinf(float x); long double asinl(long double x); double atan(double x); float atanf(float x); long double atanl(long double x); double atan2(double y, double x); float atan2f(float y, float x); long double atan2l(long double y, long double x); double cos(double x); float cosf(float x); long double cosl(long double x); double sin(double x); float sinf(float x); long double sinl(long double x); double tan(double x); float tanf(float x); long double tanl(long double x); double acosh(double x); float acoshf(float x); long double acoshl(long double x); double asinh(double x); float asinhf(float x); long double asinhl(long double x); double atanh(double x); float atanhf(float x); long double atanhl(long double x); double cosh(double x); float coshf(float x); long double coshl(long double x); double sinh(double x); float sinhf(float x); long double sinhl(long double x); double tanh(double x); float tanhf(float x); long double tanhl(long double x); double exp(double x); float expf(float x); long double expl(long double x); double exp2(double x); float exp2f(float x); long double exp2l(long double x); double expm1(double x); float expm1f(float x); long double expm1l(long double x); double frexp(double val, int *e); float frexpf(float val, int *e); long double frexpl(long double val, int *e); int ilogb(double x); int ilogbf(float x); int ilogbl(long double x); double ldexp(double x, int e); float ldexpf(float x, int e); long double ldexpl(long double x, int e); double log(double x); float logf(float x); long double logl(long double x); double log10(double x); float log10f(float x); long double log10l(long double x); double log1p(double x); float log1pf(float x); long double log1pl(long double x); double log2(double x); float log2f(float x); long double log2l(long double x); double logb(double x); float logbf(float x); long double logbl(long double x); double modf(double val, double *iptr); float modff(float val, float *iptr); long double modfl(long double val, long double *iptr); double scalbn(double x, int n); float scalbnf(float x, int n); long double scalbnl(long double x, int n); double scalbln(double x, long n); float scalblnf(float x, long n); long double scalblnl(long double x, long n); double cbrt(double x); float cbrtf(float x); long double cbrtl(long double x); double fabs(double x); float fabsf(float x); long double fabsl(long double x); double hypot(double x, double y); float hypotf(float x, float y); long double hypotl(long double x, long double y); double pow(double x, double y); float powf(float x, float y); long double powl(long double x, long double y); double sqrt(double x); float sqrtf(float x); long double sqrtl(long double x); double erf(double x); float erff(float x); long double erfl(long double x); double erfc(double x); float erfcf(float x); long double erfcl(long double x); double lgamma(double x); float lgammaf(float x); long double lgammal(long double x); double tgamma(double x); float tgammaf(float x); long double tgammal(long double x); double ceil(double x); float ceilf(float x); long double ceill(long double x); double floor(double x); float floorf(float x); long double floorl(long double x); double nearbyint(double x); float nearbyintf(float x); long double nearbyintl(long double x); double rint(double x); float rintf(float x); long double rintl(long double x); long lrint(double x); long lrintf(float x); long lrintl(long double x); long long llrint(double x); long long llrintf(float x); long long llrintl(long double x); double round(double x); float roundf(float x); long double roundl(long double x); long lround(double x); long lroundf(float x); long lroundl(long double x); long long llround(double x); long long llroundf(float x); long long llroundl(long double x); double trunc(double x); float truncf(float x); long double truncl(long double x); double fmod(double x, double y); float fmodf(float x, float y); long double fmodl(long double x, long double y); double remainder(double x, double y); float remainderf(float x, float y); long double remainderl(long double x, long double y); double remquo(double x, double y, int *quo); float remquof(float x, float y, int *quo); long double remquol(long double x, long double y, int *quo); double copysign(double x, double y); float copysignf(float x, float y); long double copysignl(long double x, long double y); double nan(const char *tagp); float nanf(const char *tagp); long double nanl(const char *tagp); double nextafter(double x, double y); float nextafterf(float x, float y); long double nextafterl(long double x, long double y); double nexttoward(double x, long double y); float nexttowardf(float x, long double y); long double nexttowardl(long double x, long double y); double fdim(double x, double y); float fdimf(float x, float y); long double fdiml(long double x, long double y); double fmax(double x, double y); float fmaxf(float x, float y); long double fmaxl(long double x, long double y); double fmin(double x, double y); float fminf(float x, float y); long double fminl(long double x, long double y); double fma(double x, double y, double z); float fmaf(float x, float y, float z); long double fmal(long double x, long double y, long double z); #pragma diag_pop /* ================================================================================= File name: RMP_CNTL.H ===================================================================================*/ typedef struct { float32_t TargetValue; // Input: Target input (pu) uint32_t RampDelayMax; // Parameter: Maximum delay rate (Q0) - independently with global Q float32_t RampLowLimit; // Parameter: Minimum limit (pu) float32_t RampHighLimit; // Parameter: Maximum limit (pu) uint32_t RampDelayCount; // Variable: Incremental delay (Q0) - independently with global Q float32_t SetpointValue; // Output: Target output (pu) uint32_t EqualFlag; // Output: Flag output (Q0) - independently with global Q float32_t Tmp; // Variable: Temp variable } RMPCNTL; /*----------------------------------------------------------------------------- Default initalizer for the RMPCNTL object. -----------------------------------------------------------------------------*/ /*------------------------------------------------------------------------------ RAMP Controller Macro Definition ------------------------------------------------------------------------------*/ static inline void fclRampControl(RMPCNTL rc1) { rc1.Tmp = (rc1.TargetValue) - (rc1.SetpointValue); if(fabs(rc1.Tmp) >= 0.0000305) { rc1.RampDelayCount++; if((rc1.RampDelayCount) >= (rc1.RampDelayMax)) { if(rc1.TargetValue >= rc1.SetpointValue) { rc1.SetpointValue += 0.0000305; } else { rc1.SetpointValue -= 0.0000305; } rc1.SetpointValue = __fmax((__fmin(rc1.SetpointValue, rc1.RampHighLimit)), rc1.RampLowLimit); rc1.RampDelayCount = 0; } } else { rc1.EqualFlag = 0x7FFFFFFF; } } /* ================================================================================= File name: SVGEN_MF_SIVA.H ===================================================================================*/ typedef struct { float32_t Gain; // Input: reference gain voltage (pu) float32_t Offset; // Input: reference offset voltage (pu) float32_t Freq; // Input: reference frequency (pu) float32_t FreqMax; // Parameter: Maximum step angle = 6*base_freq*T (pu) float32_t Alpha; // History: Sector angle (pu) float32_t NewEntry; // History: Sine (angular) look-up pointer (pu) uint32_t SectorPointer; // History: Sector number (Q0) - independently with global Q float32_t Ta; // Output: reference phase-a switching function (pu) float32_t Tb; // Output: reference phase-b switching function (pu) float32_t Tc; // Output: reference phase-c switching function (pu) float32_t StepAngle; // Variable float32_t EntryOld; // Variable float32_t dx; // Variable float32_t dy; // Variable } SVGENMF; /*----------------------------------------------------------------------------- Default initalizer for the SVGENMF object. -----------------------------------------------------------------------------*/ /*------------------------------------------------------------------------------ SVGENMF Macro Definitions ------------------------------------------------------------------------------*/ static inline void SVGenMF(SVGENMF svgenmf1) { /* Normalise the freq input to appropriate step angle */ /* Here, 1 pu. = 60 degree */ svgenmf1.StepAngle = svgenmf1.Freq * svgenmf1.FreqMax; /* Calculate new angle alpha */ svgenmf1.EntryOld = svgenmf1.NewEntry; svgenmf1.Alpha = svgenmf1.Alpha + svgenmf1.StepAngle; if (svgenmf1.Alpha >= 1.0) svgenmf1.Alpha = svgenmf1.Alpha - 1.0; svgenmf1.NewEntry = svgenmf1.Alpha; svgenmf1.dy = sinf(svgenmf1.NewEntry * 1.04719755119660); /* v.dy = sin(NewEntry) */ svgenmf1.dx = sinf(1.04719755119660 - (svgenmf1.NewEntry * 1.04719755119660)); /* v.dx = sin(60-NewEntry) */ /* Determine which sector */ if (svgenmf1.NewEntry - svgenmf1.EntryOld < 0) { if (svgenmf1.SectorPointer == 5) svgenmf1.SectorPointer = 0; else svgenmf1.SectorPointer = svgenmf1.SectorPointer + 1; } if (svgenmf1.SectorPointer == 0) /* Sector 1 calculations - a,b,c -. a,b,c*/ { svgenmf1.Ta = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tb = svgenmf1.Ta + svgenmf1.dx; svgenmf1.Tc = 1.0 - svgenmf1.Ta; } else if (svgenmf1.SectorPointer == 1) /* Sector 2 calculations - a,b,c -. b,a,c & v.dx <-. v.dy*/ { svgenmf1.Tb = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Ta = svgenmf1.Tb + svgenmf1.dy; svgenmf1.Tc = 1.0 - svgenmf1.Tb; } else if (svgenmf1.SectorPointer == 2) /* Sector 3 calculations - a,b,c -. b,c,a */ { svgenmf1.Tb = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tc = svgenmf1.Tb + svgenmf1.dx; svgenmf1.Ta = 1.0 - svgenmf1.Tb; } else if (svgenmf1.SectorPointer == 3) /* Sector 4 calculations - a,b,c -. c,b,a & v.dx <-. v.dy*/ { svgenmf1.Tc = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tb = svgenmf1.Tc + svgenmf1.dy; svgenmf1.Ta = 1.0 - svgenmf1.Tc; } else if (svgenmf1.SectorPointer == 4) /* Sector 5 calculations - a,b,c -. c,a,b */ { svgenmf1.Tc = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Ta = svgenmf1.Tc + svgenmf1.dx; svgenmf1.Tb = 1.0 - svgenmf1.Tc; } else if (svgenmf1.SectorPointer == 5) /* Sector 6 calculations - a,b,c -. a,c,b & v.dx <-. v.dy*/ { svgenmf1.Ta = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tc = svgenmf1.Ta + svgenmf1.dy; svgenmf1.Tb = 1.0 - svgenmf1.Ta; } /* Convert the unsigned GLOBAL_Q format (ranged (0,1)) . signed GLOBAL_Q format (ranged (-1,1)) */ /* Then, multiply with a gain and add an offset. */ svgenmf1.Ta = (svgenmf1.Ta - 0.5) * 2.0; svgenmf1.Ta = (svgenmf1.Gain * svgenmf1.Ta) + svgenmf1.Offset; svgenmf1.Tb = (svgenmf1.Tb - 0.5) * 2.0; svgenmf1.Tb = (svgenmf1.Gain * svgenmf1.Tb) + svgenmf1.Offset; svgenmf1.Tc = (svgenmf1.Tc - 0.5) * 2.0; svgenmf1.Tc = (svgenmf1.Gain * svgenmf1.Tc) + svgenmf1.Offset; } // // Defines // // // Function Prototypes // void initEPWM1(void); void initEPWM2(void); void initEPWM3(void); __interrupt void epwm1ISR(void); // Variables float32_t EPWM_Freq = 25.0; // PWM frequency in kHz float32_t Max_Speed = 50.0; // Max motor speed in Hz float32_t Speed_Ref = 50.0; // Motor reference speed in Hz float32_t Speed_Ref_pu = 0.0; // Motor reference speed in pu float32_t Step_Angle_Max = 0.0; // Maximum step angle for space vector generation float32_t Ramp_Time = 20.0; // Motor ramp up time to full speed(50Hz) in s float32_t Ramp_Slope = 0.0; uint16_t EPWM_Prd = 0; // EPWM Timer Base Period uint16_t EnableFlag = 0; // Enable/disable PWM operation uint16_t TripFlag = 0; // EPWM trip status uint32_t DeadTime = 200; // Deadband time in ns uint16_t EdgeDelay = 0; // Rising and Falling edge delay count uint16_t CompareA = 0; // Compare value for Phase A PWM uint16_t CompareB = 0; // Compare value for Phase B PWM uint16_t CompareC = 0; // Compare value for Phase C PWM uint32_t Delay = 500000; // Delay in us uint32_t IsrTicker = 0; // Ramp control to smoothly vary the reference speed RMPCNTL rc1 = { 0, 5, -1, 1, 0, 0, 0, 0 }; SVGENMF svgenmf1 = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0 }; void main(void) { // Initialize device clock and peripherals Device_init(); // Initialize GPIO and configure the GPIO pin as a push-pull output Device_initGPIO(); GPIO_setPadConfig(31U, 0x0000U); GPIO_setDirectionMode(31U, GPIO_DIR_MODE_OUT); // Initialize PIE and clear PIE registers. Disables CPU interrupts. Interrupt_initModule(); // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). Interrupt_initVectorTable(); // Configure GPIO0/1 , GPIO2/3 and GPIO4/5 as ePWM1A/1B, ePWM2A/2B and // ePWM3A/3B pins respectively GPIO_setPadConfig(0, 0x0000U); GPIO_setPinConfig(0x00060001U); GPIO_setPadConfig(1, 0x0000U); GPIO_setPinConfig(0x00060201U); GPIO_setPadConfig(2, 0x0000U); GPIO_setPinConfig(0x00060401U); GPIO_setPadConfig(3, 0x0000U); GPIO_setPinConfig(0x00060601U); GPIO_setPadConfig(4, 0x0000U); GPIO_setPinConfig(0x00060801U); GPIO_setPadConfig(5, 0x0000U); GPIO_setPinConfig(0x00060A01U); // // Assign the interrupt service routines to ePWM interrupts // Interrupt_register(0x00300301U, &epwm1ISR); // Initialize variables EPWM_Prd = (uint16_t)(((float32_t)(100) / (2.0* EPWM_Freq)) * 1000U); EdgeDelay = (uint16_t)((float32_t) DeadTime * (float32_t) 100 * (0.001)) ; Step_Angle_Max = 6.0 * Max_Speed *(1 / EPWM_Freq) * 0.001; Ramp_Slope = 1.0 / (EPWM_Freq * 1000.0 * Ramp_Time); rc1.RampLowLimit = 0.0; svgenmf1.FreqMax = Step_Angle_Max; // // Disable sync(Freeze clock to PWM as well) // SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); initEPWM1(); initEPWM2(); initEPWM3(); // // Enable sync and clock to PWM // SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); // // Enable ePWM interrupts // Interrupt_enable(0x00300301U); // Enable Global Interrupt (INTM) and realtime interrupt (DBGM) __asm(" clrc INTM"); __asm(" clrc DBGM"); // Loop Forever for (;;) {/* // Turn on LED GPIO_writePin(DEVICE_GPIO_PIN_LED1, 0); // Delay for a bit. DEVICE_DELAY_US(Delay); // Turn off LED GPIO_writePin(DEVICE_GPIO_PIN_LED1, 1); // Delay for a bit. DEVICE_DELAY_US(Delay);*/ } } __interrupt void epwm1ISR(void) { IsrTicker++; if (Speed_Ref > Max_Speed) { Speed_Ref = Max_Speed; } if (EnableFlag == 1) { Speed_Ref_pu = Speed_Ref / 50.0; rc1.TargetValue = Speed_Ref_pu; /* rc1.Tmp = (rc1.TargetValue) - (rc1.SetpointValue); if (fabs(rc1.Tmp) >= 0.0000305) { if (rc1.TargetValue >= rc1.SetpointValue) { rc1.SetpointValue += Ramp_Slope; } else { rc1.SetpointValue -= Ramp_Slope; } rc1.SetpointValue = __fmax((__fmin(rc1.SetpointValue, rc1.RampHighLimit)), rc1.RampLowLimit); } else { rc1.EqualFlag = 0x7FFFFFFF; } */ fclRampControl(rc1); svgenmf1.Gain = rc1.SetpointValue; if(svgenmf1.Gain > 0.95) { svgenmf1.Gain = 0.95; } svgenmf1.Freq = rc1.SetpointValue; SVGenMF(svgenmf1); /* // Normalise the freq input to appropriate step angle // Here, 1 pu. = 60 degree svgenmf1.StepAngle = svgenmf1.Freq * svgenmf1.FreqMax; // Calculate new angle alpha svgenmf1.EntryOld = svgenmf1.NewEntry; svgenmf1.Alpha = svgenmf1.Alpha + svgenmf1.StepAngle; if (svgenmf1.Alpha >= 1.0) svgenmf1.Alpha = svgenmf1.Alpha - 1.0; svgenmf1.NewEntry = svgenmf1.Alpha; svgenmf1.dy = sin(svgenmf1.NewEntry * PI_THIRD); // v.dy = sin(NewEntry) svgenmf1.dx = sin(PI_THIRD - (svgenmf1.NewEntry * PI_THIRD)); // v.dx = sin(60-NewEntry) // Determine which sector if (svgenmf1.NewEntry - svgenmf1.EntryOld < 0) { if (svgenmf1.SectorPointer == 5) svgenmf1.SectorPointer = 0; else svgenmf1.SectorPointer = svgenmf1.SectorPointer + 1; } if (svgenmf1.SectorPointer == 0) // Sector 1 calculations - a,b,c -. a,b,c { svgenmf1.Ta = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tb = svgenmf1.Ta + svgenmf1.dx; svgenmf1.Tc = 1.0 - svgenmf1.Ta; } else if (svgenmf1.SectorPointer == 1) // Sector 2 calculations - a,b,c -. b,a,c & v.dx <-. v.dy { svgenmf1.Tb = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Ta = svgenmf1.Tb + svgenmf1.dy; svgenmf1.Tc = 1.0 - svgenmf1.Tb; } else if (svgenmf1.SectorPointer == 2) // Sector 3 calculations - a,b,c -. b,c,a { svgenmf1.Tb = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tc = svgenmf1.Tb + svgenmf1.dx; svgenmf1.Ta = 1.0 - svgenmf1.Tb; } else if (svgenmf1.SectorPointer == 3) // Sector 4 calculations - a,b,c -. c,b,a & v.dx <-. v.dy { svgenmf1.Tc = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tb = svgenmf1.Tc + svgenmf1.dy; svgenmf1.Ta = 1.0 - svgenmf1.Tc; } else if (svgenmf1.SectorPointer == 4) // Sector 5 calculations - a,b,c -. c,a,b { svgenmf1.Tc = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Ta = svgenmf1.Tc + svgenmf1.dx; svgenmf1.Tb = 1.0 - svgenmf1.Tc; } else if (svgenmf1.SectorPointer == 5) // Sector 6 calculations - a,b,c -. a,c,b & v.dx <-. v.dy { svgenmf1.Ta = (1.0 - svgenmf1.dx - svgenmf1.dy) / 2.0; svgenmf1.Tc = svgenmf1.Ta + svgenmf1.dy; svgenmf1.Tb = 1.0 - svgenmf1.Ta; } // Convert the unsigned GLOBAL_Q format (ranged (0,1)) . signed GLOBAL_Q format (ranged (-1,1)) // Then, multiply with a gain and add an offset. svgenmf1.Ta = (svgenmf1.Ta - 0.5) * 2; svgenmf1.Ta = (svgenmf1.Gain * svgenmf1.Ta) + svgenmf1.Offset; svgenmf1.Tb = (svgenmf1.Tb - 0.5) * 2; svgenmf1.Tb = (svgenmf1.Gain * svgenmf1.Tb) + svgenmf1.Offset; svgenmf1.Tc = (svgenmf1.Tc - 0.5) * 2; svgenmf1.Tc = (svgenmf1.Gain * svgenmf1.Tc) + svgenmf1.Offset; */ CompareA = (uint16_t) (svgenmf1.Ta * ((float32_t)(EPWM_Prd) / 2.0) + ((float32_t)(EPWM_Prd) / 2.0)); CompareB = (uint16_t) (svgenmf1.Tb * ((float32_t)(EPWM_Prd) / 2.0) + ((float32_t)(EPWM_Prd) / 2.0)); CompareC = (uint16_t) (svgenmf1.Tc * ((float32_t)(EPWM_Prd) / 2.0) + ((float32_t)(EPWM_Prd) / 2.0)); EPWM_setCounterCompareValue(0x00004000U, EPWM_COUNTER_COMPARE_A, CompareA); EPWM_setCounterCompareValue(0x00004100U, EPWM_COUNTER_COMPARE_A, CompareB); EPWM_setCounterCompareValue(0x00004200U, EPWM_COUNTER_COMPARE_A, CompareC); if (TripFlag == 1) { EPWM_clearTripZoneFlag(0x00004000U, 0x4U); EPWM_clearTripZoneFlag(0x00004100U, 0x4U); EPWM_clearTripZoneFlag(0x00004200U, 0x4U); TripFlag = 0; } } else { if (TripFlag == 0) { EPWM_forceTripZoneEvent(0x00004000U, 0x4U); EPWM_forceTripZoneEvent(0x00004000U, 0x4U); EPWM_forceTripZoneEvent(0x00004000U, 0x4U); TripFlag = 1; rc1.TargetValue = 0.0; rc1.SetpointValue = 0.0; } } // // Clear INT flag for this timer // EPWM_clearEventTriggerInterruptFlag(0x00004000U); // // Acknowledge interrupt group // Interrupt_clearACKGroup(0x4U); } // // initEPWM1 - Configure ePWM1 // void initEPWM1() { // // Set-up TBCLK // EPWM_setTimeBasePeriod(0x00004000U, EPWM_Prd); EPWM_setPhaseShift(0x00004000U, 0U); EPWM_setTimeBaseCounter(0x00004000U, 0U); // // Set up counter mode // EPWM_setTimeBaseCounterMode(0x00004000U, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(0x00004000U); EPWM_setClockPrescaler(0x00004000U, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); // // Set up shadowing // EPWM_setCounterCompareShadowLoadMode(0x00004000U, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareShadowLoadMode(0x00004000U, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Set actions // EPWM_setActionQualifierAction(0x00004000U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(0x00004000U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); // Set dead band control actions EPWM_setDeadBandDelayMode(0x00004000U, EPWM_DB_RED, 1); EPWM_setDeadBandDelayMode(0x00004000U, EPWM_DB_FED, 1); EPWM_setDeadBandDelayPolarity(0x00004000U, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); EPWM_setDeadBandDelayPolarity(0x00004000U, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); EPWM_setRisingEdgeDelayCount(0x00004000U, EdgeDelay); EPWM_setFallingEdgeDelayCount(0x00004000U, EdgeDelay); // Set trip zone actions EPWM_setTripZoneAction(0x00004000U, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(0x00004000U, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_forceTripZoneEvent(0x00004000U, 0x4U); // Interrupt where we will change the Compare Values // Select INT on Time base counter zero event, // Enable INT, generate INT on 3rd event // EPWM_setInterruptSource(0x00004000U, 1U); EPWM_enableInterrupt(0x00004000U); EPWM_setInterruptEventCount(0x00004000U, 1U); } // // initEPWM2 - Configure ePWM2 // void initEPWM2() { // // Set-up TBCLK // EPWM_setTimeBasePeriod(0x00004100U, EPWM_Prd); EPWM_setPhaseShift(0x00004100U, 0U); EPWM_setTimeBaseCounter(0x00004100U, 0U); // // Set up counter mode // EPWM_setTimeBaseCounterMode(0x00004100U, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(0x00004100U); EPWM_setClockPrescaler(0x00004100U, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); // // Set up shadowing // EPWM_setCounterCompareShadowLoadMode(0x00004100U, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareShadowLoadMode(0x00004100U, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Set actions // EPWM_setActionQualifierAction(0x00004100U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(0x00004100U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); // Set dead band control actions EPWM_setDeadBandDelayMode(0x00004100U, EPWM_DB_RED, 1); EPWM_setDeadBandDelayMode(0x00004100U, EPWM_DB_FED, 1); EPWM_setDeadBandDelayPolarity(0x00004100U, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); EPWM_setDeadBandDelayPolarity(0x00004100U, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); EPWM_setRisingEdgeDelayCount(0x00004100U, EdgeDelay); EPWM_setFallingEdgeDelayCount(0x00004100U, EdgeDelay); // Set trip zone actions EPWM_setTripZoneAction(0x00004100U, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(0x00004100U, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_forceTripZoneEvent(0x00004100U, 0x4U); } // // initEPWM3 - Configure ePWM3 // void initEPWM3(void) { // // Set-up TBCLK // EPWM_setTimeBasePeriod(0x00004200U, EPWM_Prd); EPWM_setPhaseShift(0x00004200U, 0U); EPWM_setTimeBaseCounter(0x00004200U, 0U); // // Set up counter mode // EPWM_setTimeBaseCounterMode(0x00004200U, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(0x00004200U); EPWM_setClockPrescaler(0x00004200U, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); // // Set up shadowing // EPWM_setCounterCompareShadowLoadMode(0x00004200U, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareShadowLoadMode(0x00004200U, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Set actions // EPWM_setActionQualifierAction(0x00004200U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(0x00004200U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); // Set dead band control actions EPWM_setDeadBandDelayMode(0x00004200U, EPWM_DB_RED, 1); EPWM_setDeadBandDelayMode(0x00004200U, EPWM_DB_FED, 1); EPWM_setDeadBandDelayPolarity(0x00004200U, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); EPWM_setDeadBandDelayPolarity(0x00004200U, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); EPWM_setRisingEdgeDelayCount(0x00004200U, EdgeDelay); EPWM_setFallingEdgeDelayCount(0x00004200U, EdgeDelay); // Set trip zone actions EPWM_setTripZoneAction(0x00004200U, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(0x00004200U, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_forceTripZoneEvent(0x00004200U, 0x4U); }