//########################################################################### // // FILE: F2837xD_Adc.c // // TITLE: F2837xD Adc Support Functions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Included Files // //########################################################################### // // FILE: F2837xD_device.h // // TITLE: F2837xD Device Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 (Patch) $ // $Release Date: March 3 2017 $ // $Copyright: Copyright (C) 2014-2017 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // User To Select Target Device: // // // Common CPU Definitions: // extern __cregister volatile unsigned int IFR; extern __cregister volatile unsigned int IER; // // For Portability, User Is Recommended To Use the C99 Standard integer types // /*****************************************************************************/ /* assert.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* _ti_config.h */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*Unsupported pragmas are omitted */ # pragma diag_push # pragma CHECK_MISRA("-19.7") # pragma CHECK_MISRA("-19.4") # pragma CHECK_MISRA("-19.1") # pragma CHECK_MISRA("-19.15") # pragma diag_pop _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") _Pragma("CHECK_MISRA(\"-19.1\")") _Pragma("CHECK_MISRA(\"-19.6\")") /* Hide uses of the TI proprietary macros behind other macros. Implementations that don't implement these features should leave these macros undefined. */ /* Common definitions */ /* C */ /* C89/C99 */ /* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It is intended to be used for functions like abort and atexit that are supposed to be declared noexcept only in C++14 mode. */ /* Target-specific definitions */ /*****************************************************************************/ /* linkage.h */ /* */ /* Copyright (c) 1998 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ /* No modifiers needed to access code */ /*--------------------------------------------------------------------------*/ /* Define _DATA_ACCESS ==> how to access RTS global or static data */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _IDECL ==> how inline functions are declared */ /*--------------------------------------------------------------------------*/ #pragma diag_pop _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ _Pragma("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-19.13\")") /* # and ## required for implementation */ extern void _abort_msg(const char *msg); _Pragma("diag_pop") /*****************************************************************************/ /* stdarg.h */ /* */ /* Copyright (c) 1996 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-19.10") /* need types as macro arguments */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2002 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1991, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Berkeley Software Design, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 * $FreeBSD$ */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"none\")") /* * Testing against Clang-specific extensions. */ /* * This code has been put in place to help reduce the addition of * compiler specific defines in FreeBSD code. It helps to aid in * having a compiler-agnostic source tree. */ /* * Macro to test if we're using a specific version of gcc or later. */ /* * The __CONCAT macro is used to concatenate parts of symbol names, e.g. * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI * mode -- there must be no spaces between its arguments, and for nested * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also * concatenate double-quoted strings produced by the __STRING macro, but * this only works with ANSI C. * * __XSTRING is like __STRING, but it expands any macros in its argument * first. It is only available with ANSI C. */ /* * Compiler-dependent macros to help declare dead (non-returning) and * pure (no side effects) functions, and unused variables. They are * null except for versions of gcc that are known to support the features * properly (old versions of gcc-2 supported the dead and pure features * in a different (wrong) way). If we do not provide an implementation * for a given compiler, let the compile fail if it is told to use * a feature that we cannot live without. */ /* * TI ADD - check that __GNUC__ is defined before referencing it to avoid * generating an error when __GNUC__ treated as zero warning is * promoted to an error via -pdse195 option. */ /* * Keywords added in C11. */ /* * No native support for _Atomic(). Place object in structure to prevent * most forms of direct non-atomic access. */ /* * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode * without actually supporting the thread_local keyword. Don't check for * the presence of C++11 when defining _Thread_local. */ /* * Emulation of C11 _Generic(). Unlike the previously defined C11 * keywords, it is not possible to implement this using exactly the same * syntax. Therefore implement something similar under the name * __generic(). Unlike _Generic(), this macro can only distinguish * between a single type, so it requires nested invocations to * distinguish multiple cases. */ /* * C99 Static array indices in function parameter declarations. Syntax such as: * void bar(int myArray[static 10]); * is allowed in C99 but not in C++. Define __min_size appropriately so * headers using it can be compiled in either language. Use like this: * void bar(int myArray[__min_size(10)]); */ /* XXX: should use `#if __STDC_VERSION__ < 199901'. */ /* C++11 exposes a load of C99 stuff */ /* * GCC 2.95 provides `__restrict' as an extension to C90 to support the * C99-specific `restrict' type qualifier. We happen to use `__restrict' as * a way to define the `restrict' type qualifier without disturbing older * software that is unaware of C99 keywords. * The TI compiler supports __restrict in all compilation modes. */ /* * GNU C version 2.96 adds explicit branch prediction so that * the CPU back-end can hint the processor and also so that * code blocks can be reordered such that the predicted path * sees a more linear flow, thus improving cache behavior, etc. * * The following two macros provide us with a way to utilize this * compiler feature. Use __predict_true() if you expect the expression * to evaluate to true, and __predict_false() if you expect the * expression to evaluate to false. * * A few notes about usage: * * * Generally, __predict_false() error condition checks (unless * you have some _strong_ reason to do otherwise, in which case * document it), and/or __predict_true() `no-error' condition * checks, assuming you want to optimize for the no-error case. * * * Other than that, if you don't know the likelihood of a test * succeeding from empirical or other `hard' evidence, don't * make predictions. * * * These are meant to be used in places that are run `a lot'. * It is wasteful to make predictions in code that is run * seldomly (e.g. at subsystem initialization time) as the * basic block reordering that this affects can often generate * larger code. */ /* * We define this here since , , and * require it. */ /* * Given the pointer x to the member m of the struct s, return * a pointer to the containing structure. When using GCC, we first * assign pointer x to a local variable, to check that its type is * compatible with member m. */ /* * Compiler-dependent macros to declare that functions take printf-like * or scanf-like arguments. They are null except for versions of gcc * that are known to support the features properly (old versions of gcc-2 * didn't permit keeping the keywords out of the application namespace). */ /* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ /* * The following definition might not work well if used in header files, * but it should be better than nothing. If you want a "do nothing" * version, then it should generate some harmless declaration, such as: * #define __IDSTRING(name,string) struct __hack */ /* * Embed the rcs id of a source file in the resulting library. Note that in * more recent ELF binutils, we use .ident allowing the ID to be stripped. * Usage: * __FBSDID("$FreeBSD$"); */ /*- * The following definitions are an extension of the behavior originally * implemented in , but with a different level of granularity. * POSIX.1 requires that the macros we test be defined before any standard * header file is included. * * Here's a quick run-down of the versions: * defined(_POSIX_SOURCE) 1003.1-1988 * _POSIX_C_SOURCE == 1 1003.1-1990 * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option * _POSIX_C_SOURCE == 199309 1003.1b-1993 * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, * and the omnibus ISO/IEC 9945-1: 1996 * _POSIX_C_SOURCE == 200112 1003.1-2001 * _POSIX_C_SOURCE == 200809 1003.1-2008 * * In addition, the X/Open Portability Guide, which is now the Single UNIX * Specification, defines a feature-test macro which indicates the version of * that specification, and which subsumes _POSIX_C_SOURCE. * * Our macros begin with two underscores to avoid namespace screwage. */ /* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ /* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ /* Deal with various X/Open Portability Guides and Single UNIX Spec. */ /* * Deal with all versions of POSIX. The ordering relative to the tests above is * important. */ /*- * Deal with _ANSI_SOURCE: * If it is defined, and no other compilation environment is explicitly * requested, then define our internal feature-test macros to zero. This * makes no difference to the preprocessor (undefined symbols in preprocessing * expressions are defined to have value zero), but makes it more convenient for * a test program to print out the values. * * If a program mistakenly defines _ANSI_SOURCE and some other macro such as * _POSIX_C_SOURCE, we will assume that it wants the broader compilation * environment (and in fact we will never get here). */ /* User override __EXT1_VISIBLE */ /* * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h * translates them to __ARM_ARCH and the modern feature symbols defined by ARM. */ /* * Nullability qualifiers: currently only supported by Clang. */ /* * Type Safety Checking * * Clang provides additional attributes to enable checking type safety * properties that cannot be enforced by the C type system. */ /* * Lock annotations. * * Clang provides support for doing basic thread-safety tests at * compile-time, by marking which locks will/should be held when * entering/leaving a functions. * * Furthermore, it is also possible to annotate variables and structure * members to enforce that they are only accessed when certain locks are * held. */ /* Structure implements a lock. */ /* Function acquires an exclusive or shared lock. */ /* Function attempts to acquire an exclusive or shared lock. */ /* Function releases a lock. */ /* Function asserts that an exclusive or shared lock is held. */ /* Function requires that an exclusive or shared lock is or is not held. */ /* Function should not be analyzed. */ /* Guard variables and structure members by lock. */ _Pragma("diag_pop") /*****************************************************************************/ /* _TYPES.H */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push /* This file is required to use base types */ #pragma CHECK_MISRA("-6.3") /* * Basic types upon which most other types are built. */ typedef int __int16_t; typedef unsigned int __uint16_t; typedef long __int32_t; typedef unsigned long __uint32_t; /* LONGLONG */ typedef long long __int64_t; /* LONGLONG */ typedef unsigned long long __uint64_t; /* * Standard type definitions. */ typedef __uint32_t __clock_t; /* clock()... */ typedef __int32_t __critical_t; typedef double __double_t; typedef float __float_t; typedef __int32_t __intfptr_t; typedef __int64_t __intmax_t; typedef __int32_t __intptr_t; typedef __int16_t __int_fast8_t; typedef __int16_t __int_fast16_t; typedef __int32_t __int_fast32_t; typedef __int64_t __int_fast64_t; typedef __int16_t __int_least8_t; typedef __int16_t __int_least16_t; typedef __int32_t __int_least32_t; typedef __int64_t __int_least64_t; typedef long __ptrdiff_t; /* ptr1 - ptr2 */ typedef __int16_t __register_t; typedef __int32_t __segsz_t; /* segment size (in pages) */ typedef unsigned long __size_t; /* sizeof() */ typedef __int32_t __ssize_t; /* byte count or error */ typedef __int64_t __time_t; /* time()... */ typedef __uint32_t __uintfptr_t; typedef __uint64_t __uintmax_t; typedef __uint32_t __uintptr_t; typedef __uint16_t __uint_fast8_t; typedef __uint16_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; typedef __uint64_t __uint_fast64_t; typedef __uint16_t __uint_least8_t; typedef __uint16_t __uint_least16_t; typedef __uint32_t __uint_least32_t; typedef __uint64_t __uint_least64_t; typedef __uint16_t __u_register_t; typedef __uint32_t __vm_offset_t; typedef __uint32_t __vm_paddr_t; typedef __uint32_t __vm_size_t; typedef unsigned long ___wchar_t; /* * POSIX target specific _off_t type definition */ typedef long int _off_t; /* * Unusual type definitions. */ typedef char* __va_list; #pragma diag_pop _Pragma("diag_push") /* This file is required to use types without size and signedness */ _Pragma("CHECK_MISRA(\"-6.3\")") /* * Standard type definitions. */ typedef __int32_t __blksize_t; /* file block size */ typedef __int64_t __blkcnt_t; /* file block count */ typedef __int32_t __clockid_t; /* clock_gettime()... */ typedef __uint32_t __fflags_t; /* file flags */ typedef __uint64_t __fsblkcnt_t; typedef __uint64_t __fsfilcnt_t; typedef __uint32_t __gid_t; typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ typedef __uint64_t __ino_t; /* inode number */ typedef long __key_t; /* IPC key (for Sys V IPC) */ typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ typedef __uint16_t __mode_t; /* permissions */ typedef int __accmode_t; /* access permissions */ typedef int __nl_item; typedef __uint64_t __nlink_t; /* link count */ typedef _off_t __off_t; /* file offset (target-specific) */ typedef __int64_t __off64_t; /* file offset (always 64-bit) */ typedef __int32_t __pid_t; /* process [group] */ typedef __int64_t __rlim_t; /* resource limit - intentionally */ /* signed, because of legacy code */ /* that uses -1 for RLIM_INFINITY */ typedef __uint16_t __sa_family_t; typedef __uint32_t __socklen_t; typedef long __suseconds_t; /* microseconds (signed) */ typedef struct __timer *__timer_t; /* timer_gettime()... */ typedef struct __mq *__mqd_t; /* mq_open()... */ typedef __uint32_t __uid_t; typedef unsigned int __useconds_t; /* microseconds (unsigned) */ typedef int __cpuwhich_t; /* which parameter for cpuset. */ typedef int __cpulevel_t; /* level parameter for cpuset. */ typedef int __cpusetid_t; /* cpuset identifier. */ /* * Unusual type definitions. */ /* * rune_t is declared to be an ``int'' instead of the more natural * ``unsigned long'' or ``long''. Two things are happening here. It is not * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, * it looks like 10646 will be a 31 bit standard. This means that if your * ints cannot hold 32 bits, you will be in trouble. The reason an int was * chosen over a long is that the is*() and to*() routines take ints (says * ANSI C), but they use __ct_rune_t instead of int. * * NOTE: rune_t is not covered by ANSI nor other standards, and should not * be instantiated outside of lib/libc/locale. Use wchar_t. wint_t and * rune_t must be the same type. Also, wint_t should be able to hold all * members of the largest character set plus one extra value (WEOF), and * must be at least 16 bits. */ typedef unsigned long __ct_rune_t; /* arg type for ctype funcs */ typedef __ct_rune_t __rune_t; /* rune_t (see above) */ typedef __ct_rune_t __wint_t; /* wint_t (see above) */ /* Clang already provides these types as built-ins, but only in C++ mode. */ typedef __uint_least16_t __char16_t; typedef __uint_least32_t __char32_t; /* In C++11, char16_t and char32_t are built-in types. */ typedef struct { long long __max_align1 __attribute__((aligned(__alignof__(long long)))); long double __max_align2 __attribute__((aligned(__alignof__(long double)))); } __max_align_t; typedef __uint64_t __dev_t; /* device number */ typedef __uint32_t __fixpt_t; /* fixed point number */ /* * mbstate_t is an opaque object to keep conversion state during multibyte * stream conversions. */ typedef int _Mbstatet; typedef _Mbstatet __mbstate_t; typedef __uintmax_t __rman_res_t; /* * When the following macro is defined, the system uses 64-bit inode numbers. * Programs can use this to avoid including , with its associated * namespace pollution. */ _Pragma("diag_pop") typedef __va_list va_list; /****************************************************************************/ /* RETURN THE NEXT VALUE ON THE STACK ... */ /* */ /* (, ) BECOMES ... */ /* */ /* ap -= 1 (stack grows toward high addresses) */ /* ap -= 1 more if type is long or float */ /* ap -= 1 more if type is long or float and to account for alignment */ /* if necessary */ /* */ /* if () return **ap; */ /* else if () return *ap; */ /* */ /* LONG/FLOATS ARE ALWAYS ALIGNED ON AN EVEN WORD BOUNDARY, EVEN WHEN */ /* PASSED AS PARAMETERS, THUS ap MUST BE ALIGNED FOR THOSE ACCESSES. */ /****************************************************************************/ #pragma diag_pop /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /* If this file is included in C99 mode, _Bool is a builtin, so no definition. */ /* If this is C89 mode and this file is included, _Bool is pre-defined in C89 */ /* relaxed mode by the EDG parser, so it needs to be defined in strict mode. */ /*****************************************************************************/ /* stddef.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ _Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ typedef long ptrdiff_t; typedef unsigned long size_t; typedef unsigned long wchar_t; /*----------------------------------------------------------------------------*/ /* C++11 and C11 required max_align_t to be defined. The libc++ cstddef */ /* header expects the macro __DEFINED_max_align_t to be defined if it is to */ /* use the definintion of max_align_t from stddef.h. Only define it if */ /* compiling for C11 or we're in non strict ansi mode. */ /*----------------------------------------------------------------------------*/ typedef long double max_align_t; _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.10\")") /* need types as macro arguments */ _Pragma("diag_pop") _Pragma("diag_pop") /*****************************************************************************/ /* STDINT.H */ /* */ /* Copyright (c) 2002 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* _STDINT40.H */ /* */ /* Copyright (c) 2018 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*****************************************************************************/ /* _STDINT.H */ /* */ /* Copyright (c) 2019 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*- * SPDX-License-Identifier: BSD-2-Clause-NetBSD * * Copyright (c) 2001, 2002 Mike Barcroft * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #pragma diag_push /* 19.4 is issued for macros that are defined in terms of other macros. */ #pragma CHECK_MISRA("-19.4") /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types */ /* Minimum values of exact-width signed integer types. */ /* Maximum values of exact-width signed integer types. */ /* Maximum values of exact-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.2 Limits of minimum-width integer types */ /* Minimum values of minimum-width signed integer types. */ /* Maximum values of minimum-width signed integer types. */ /* Maximum values of minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.3 Limits of fastest minimum-width integer types */ /* Minimum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.4 Limits of integer types capable of holding object pointers */ /* * ISO/IEC 9899:1999 * 7.18.2.5 Limits of greatest-width integer types */ /* * ISO/IEC 9899:1999 * 7.18.3 Limits of other integer types */ /* Limits of ptrdiff_t. */ /* Limits of sig_atomic_t. */ /* Limit of size_t. */ /* Limits of wint_t. */ #pragma diag_pop /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 David E. O'Brien * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ typedef __int16_t int16_t; typedef __int32_t int32_t; typedef __int64_t int64_t; typedef __uint16_t uint16_t; typedef __uint32_t uint32_t; typedef __uint64_t uint64_t; typedef __intptr_t intptr_t; typedef __uintptr_t uintptr_t; typedef __intmax_t intmax_t; typedef __uintmax_t uintmax_t; typedef __int_least8_t int_least8_t; typedef __int_least16_t int_least16_t; typedef __int_least32_t int_least32_t; typedef __int_least64_t int_least64_t; typedef __uint_least8_t uint_least8_t; typedef __uint_least16_t uint_least16_t; typedef __uint_least32_t uint_least32_t; typedef __uint_least64_t uint_least64_t; typedef __int_fast8_t int_fast8_t; typedef __int_fast16_t int_fast16_t; typedef __int_fast32_t int_fast32_t; typedef __int_fast64_t int_fast64_t; typedef __uint_fast8_t uint_fast8_t; typedef __uint_fast16_t uint_fast16_t; typedef __uint_fast32_t uint_fast32_t; typedef __uint_fast64_t uint_fast64_t; _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-10.1\")") /* GNU and Darwin define this and people seem to think it's portable */ _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") /* Limits of wchar_t. */ _Pragma("diag_pop") /* ISO/IEC 9899:2011 K.3.4.4 */ // // C++ Bool Compatibility // // // C99 defines boolean type to be _Bool, but this doesn't match the format of // the other standard integer types. bool_t has been defined to fill this gap. // typedef _Bool bool_t; // //used for a bool function return status // typedef _Bool status_t; // // The following data types are included for compatibility with legacy code, // they are not recommended for use in new software. Please use the C99 // types included above // typedef int int16; typedef long int32; typedef long long int64; typedef unsigned int Uint16; typedef unsigned long Uint32; typedef unsigned long long Uint64; typedef float float32; typedef long double float64; // // The following data types are for use with byte addressable peripherals. // See compiler documentation on the byte_peripheral type attribute. // typedef unsigned int bp_16 __attribute__((byte_peripheral)); typedef unsigned long bp_32 __attribute__((byte_peripheral)); // // Include All Peripheral Header Files: // //########################################################################### // // FILE: F2837xD_adc.h // // TITLE: F2837xD Device ADC Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // ADC Individual Register Bit Definitions: struct ADCCTL1_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position Uint16 rsvd2:4; // 6:3 Reserved Uint16 ADCPWDNZ:1; // 7 ADC Power Down Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel Uint16 rsvd3:1; // 12 Reserved Uint16 ADCBSY:1; // 13 ADC Busy Uint16 rsvd4:2; // 15:14 Reserved }; union ADCCTL1_REG { Uint16 all; struct ADCCTL1_BITS bit; }; struct ADCCTL2_BITS { // bits description Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler Uint16 rsvd1:2; // 5:4 Reserved Uint16 RESOLUTION:1; // 6 SOC Conversion Resolution Uint16 SIGNALMODE:1; // 7 SOC Signaling Mode Uint16 rsvd2:5; // 12:8 Reserved Uint16 rsvd3:3; // 15:13 Reserved }; union ADCCTL2_REG { Uint16 all; struct ADCCTL2_BITS bit; }; struct ADCBURSTCTL_BITS { // bits description Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select Uint16 rsvd1:2; // 7:6 Reserved Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select Uint16 rsvd2:3; // 14:12 Reserved Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable }; union ADCBURSTCTL_REG { Uint16 all; struct ADCBURSTCTL_BITS bit; }; struct ADCINTFLG_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTFLG_REG { Uint16 all; struct ADCINTFLG_BITS bit; }; struct ADCINTFLGCLR_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTFLGCLR_REG { Uint16 all; struct ADCINTFLGCLR_BITS bit; }; struct ADCINTOVF_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTOVF_REG { Uint16 all; struct ADCINTOVF_BITS bit; }; struct ADCINTOVFCLR_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTOVFCLR_REG { Uint16 all; struct ADCINTOVFCLR_BITS bit; }; struct ADCINTSEL1N2_BITS { // bits description Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select Uint16 rsvd1:1; // 4 Reserved Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable Uint16 rsvd2:1; // 7 Reserved Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select Uint16 rsvd3:1; // 12 Reserved Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCINTSEL1N2_REG { Uint16 all; struct ADCINTSEL1N2_BITS bit; }; struct ADCINTSEL3N4_BITS { // bits description Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select Uint16 rsvd1:1; // 4 Reserved Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable Uint16 rsvd2:1; // 7 Reserved Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select Uint16 rsvd3:1; // 12 Reserved Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCINTSEL3N4_REG { Uint16 all; struct ADCINTSEL3N4_BITS bit; }; struct ADCSOCPRICTL_BITS { // bits description Uint16 SOCPRIORITY:5; // 4:0 SOC Priority Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer Uint16 rsvd1:6; // 15:10 Reserved }; union ADCSOCPRICTL_REG { Uint16 all; struct ADCSOCPRICTL_BITS bit; }; struct ADCINTSOCSEL1_BITS { // bits description Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select }; union ADCINTSOCSEL1_REG { Uint16 all; struct ADCINTSOCSEL1_BITS bit; }; struct ADCINTSOCSEL2_BITS { // bits description Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select }; union ADCINTSOCSEL2_REG { Uint16 all; struct ADCINTSOCSEL2_BITS bit; }; struct ADCSOCFLG1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag }; union ADCSOCFLG1_REG { Uint16 all; struct ADCSOCFLG1_BITS bit; }; struct ADCSOCFRC1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit }; union ADCSOCFRC1_REG { Uint16 all; struct ADCSOCFRC1_BITS bit; }; struct ADCSOCOVF1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag }; union ADCSOCOVF1_REG { Uint16 all; struct ADCSOCOVF1_BITS bit; }; struct ADCSOCOVFCLR1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit }; union ADCSOCOVFCLR1_REG { Uint16 all; struct ADCSOCOVFCLR1_BITS bit; }; struct ADCSOC0CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC0CTL_REG { Uint32 all; struct ADCSOC0CTL_BITS bit; }; struct ADCSOC1CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC1CTL_REG { Uint32 all; struct ADCSOC1CTL_BITS bit; }; struct ADCSOC2CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC2CTL_REG { Uint32 all; struct ADCSOC2CTL_BITS bit; }; struct ADCSOC3CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC3CTL_REG { Uint32 all; struct ADCSOC3CTL_BITS bit; }; struct ADCSOC4CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC4CTL_REG { Uint32 all; struct ADCSOC4CTL_BITS bit; }; struct ADCSOC5CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC5CTL_REG { Uint32 all; struct ADCSOC5CTL_BITS bit; }; struct ADCSOC6CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC6CTL_REG { Uint32 all; struct ADCSOC6CTL_BITS bit; }; struct ADCSOC7CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC7CTL_REG { Uint32 all; struct ADCSOC7CTL_BITS bit; }; struct ADCSOC8CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC8CTL_REG { Uint32 all; struct ADCSOC8CTL_BITS bit; }; struct ADCSOC9CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC9CTL_REG { Uint32 all; struct ADCSOC9CTL_BITS bit; }; struct ADCSOC10CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC10CTL_REG { Uint32 all; struct ADCSOC10CTL_BITS bit; }; struct ADCSOC11CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC11CTL_REG { Uint32 all; struct ADCSOC11CTL_BITS bit; }; struct ADCSOC12CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC12CTL_REG { Uint32 all; struct ADCSOC12CTL_BITS bit; }; struct ADCSOC13CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC13CTL_REG { Uint32 all; struct ADCSOC13CTL_BITS bit; }; struct ADCSOC14CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC14CTL_REG { Uint32 all; struct ADCSOC14CTL_BITS bit; }; struct ADCSOC15CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC15CTL_REG { Uint32 all; struct ADCSOC15CTL_BITS bit; }; struct ADCEVTSTAT_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTSTAT_REG { Uint16 all; struct ADCEVTSTAT_BITS bit; }; struct ADCEVTCLR_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTCLR_REG { Uint16 all; struct ADCEVTCLR_BITS bit; }; struct ADCEVTSEL_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTSEL_REG { Uint16 all; struct ADCEVTSEL_BITS bit; }; struct ADCEVTINTSEL_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTINTSEL_REG { Uint16 all; struct ADCEVTINTSEL_BITS bit; }; struct ADCCOUNTER_BITS { // bits description Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value Uint16 rsvd1:4; // 15:12 Reserved }; union ADCCOUNTER_REG { Uint16 all; struct ADCCOUNTER_BITS bit; }; struct ADCREV_BITS { // bits description Uint16 TYPE:8; // 7:0 ADC Type Uint16 REV:8; // 15:8 ADC Revision }; union ADCREV_REG { Uint16 all; struct ADCREV_BITS bit; }; struct ADCOFFTRIM_BITS { // bits description Uint16 OFFTRIM:8; // 7:0 ADC Offset Trim Uint16 rsvd1:8; // 15:8 Reserved }; union ADCOFFTRIM_REG { Uint16 all; struct ADCOFFTRIM_BITS bit; }; struct ADCPPB1CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 rsvd1:11; // 15:5 Reserved }; union ADCPPB1CONFIG_REG { Uint16 all; struct ADCPPB1CONFIG_BITS bit; }; struct ADCPPB1STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB1STAMP_REG { Uint16 all; struct ADCPPB1STAMP_BITS bit; }; struct ADCPPB1OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB1OFFCAL_REG { Uint16 all; struct ADCPPB1OFFCAL_BITS bit; }; struct ADCPPB1TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB1TRIPHI_REG { Uint32 all; struct ADCPPB1TRIPHI_BITS bit; }; struct ADCPPB1TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB1TRIPLO_REG { Uint32 all; struct ADCPPB1TRIPLO_BITS bit; }; struct ADCPPB2CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 rsvd1:11; // 15:5 Reserved }; union ADCPPB2CONFIG_REG { Uint16 all; struct ADCPPB2CONFIG_BITS bit; }; struct ADCPPB2STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB2STAMP_REG { Uint16 all; struct ADCPPB2STAMP_BITS bit; }; struct ADCPPB2OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB2OFFCAL_REG { Uint16 all; struct ADCPPB2OFFCAL_BITS bit; }; struct ADCPPB2TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB2TRIPHI_REG { Uint32 all; struct ADCPPB2TRIPHI_BITS bit; }; struct ADCPPB2TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB2TRIPLO_REG { Uint32 all; struct ADCPPB2TRIPLO_BITS bit; }; struct ADCPPB3CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 rsvd1:11; // 15:5 Reserved }; union ADCPPB3CONFIG_REG { Uint16 all; struct ADCPPB3CONFIG_BITS bit; }; struct ADCPPB3STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB3STAMP_REG { Uint16 all; struct ADCPPB3STAMP_BITS bit; }; struct ADCPPB3OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB3OFFCAL_REG { Uint16 all; struct ADCPPB3OFFCAL_BITS bit; }; struct ADCPPB3TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB3TRIPHI_REG { Uint32 all; struct ADCPPB3TRIPHI_BITS bit; }; struct ADCPPB3TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB3TRIPLO_REG { Uint32 all; struct ADCPPB3TRIPLO_BITS bit; }; struct ADCPPB4CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 rsvd1:11; // 15:5 Reserved }; union ADCPPB4CONFIG_REG { Uint16 all; struct ADCPPB4CONFIG_BITS bit; }; struct ADCPPB4STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB4STAMP_REG { Uint16 all; struct ADCPPB4STAMP_BITS bit; }; struct ADCPPB4OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB4OFFCAL_REG { Uint16 all; struct ADCPPB4OFFCAL_BITS bit; }; struct ADCPPB4TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB4TRIPHI_REG { Uint32 all; struct ADCPPB4TRIPHI_BITS bit; }; struct ADCPPB4TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB4TRIPLO_REG { Uint32 all; struct ADCPPB4TRIPLO_BITS bit; }; struct ADC_REGS { union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register Uint16 rsvd1; // Reserved union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register Uint16 rsvd2; // Reserved union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register Uint16 rsvd3; // Reserved union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register Uint16 rsvd4[2]; // Reserved union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register union ADCREV_REG ADCREV; // ADC Revision Register union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register Uint16 rsvd5[4]; // Reserved union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register Uint16 rsvd6[16]; // Reserved Uint32 ADCINLTRIM1; // ADC Linearity Trim 1 Register Uint32 ADCINLTRIM2; // ADC Linearity Trim 2 Register Uint32 ADCINLTRIM3; // ADC Linearity Trim 3 Register Uint32 ADCINLTRIM4; // ADC Linearity Trim 4 Register Uint32 ADCINLTRIM5; // ADC Linearity Trim 5 Register Uint32 ADCINLTRIM6; // ADC Linearity Trim 6 Register Uint16 rsvd7[4]; // Reserved }; struct ADCPPB1RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB1RESULT_REG { Uint32 all; struct ADCPPB1RESULT_BITS bit; }; struct ADCPPB2RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB2RESULT_REG { Uint32 all; struct ADCPPB2RESULT_BITS bit; }; struct ADCPPB3RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB3RESULT_REG { Uint32 all; struct ADCPPB3RESULT_BITS bit; }; struct ADCPPB4RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB4RESULT_REG { Uint32 all; struct ADCPPB4RESULT_BITS bit; }; struct ADC_RESULT_REGS { Uint16 ADCRESULT0; // ADC Result 0 Register Uint16 ADCRESULT1; // ADC Result 1 Register Uint16 ADCRESULT2; // ADC Result 2 Register Uint16 ADCRESULT3; // ADC Result 3 Register Uint16 ADCRESULT4; // ADC Result 4 Register Uint16 ADCRESULT5; // ADC Result 5 Register Uint16 ADCRESULT6; // ADC Result 6 Register Uint16 ADCRESULT7; // ADC Result 7 Register Uint16 ADCRESULT8; // ADC Result 8 Register Uint16 ADCRESULT9; // ADC Result 9 Register Uint16 ADCRESULT10; // ADC Result 10 Register Uint16 ADCRESULT11; // ADC Result 11 Register Uint16 ADCRESULT12; // ADC Result 12 Register Uint16 ADCRESULT13; // ADC Result 13 Register Uint16 ADCRESULT14; // ADC Result 14 Register Uint16 ADCRESULT15; // ADC Result 15 Register union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register }; //--------------------------------------------------------------------------- // ADC External References & Function Declarations: // extern volatile struct ADC_RESULT_REGS AdcaResultRegs; extern volatile struct ADC_RESULT_REGS AdcbResultRegs; extern volatile struct ADC_RESULT_REGS AdccResultRegs; extern volatile struct ADC_RESULT_REGS AdcdResultRegs; extern volatile struct ADC_REGS AdcaRegs; extern volatile struct ADC_REGS AdcbRegs; extern volatile struct ADC_REGS AdccRegs; extern volatile struct ADC_REGS AdcdRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_analogsubsys.h // // TITLE: F2837xD Device ANALOGSUBSYS Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // ANALOGSUBSYS Individual Register Bit Definitions: struct INTOSC1TRIM_BITS { // bits description Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:8; // 23:16 Reserved Uint16 rsvd3:8; // 31:24 Reserved }; union INTOSC1TRIM_REG { Uint32 all; struct INTOSC1TRIM_BITS bit; }; struct INTOSC2TRIM_BITS { // bits description Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:8; // 23:16 Reserved Uint16 rsvd3:8; // 31:24 Reserved }; union INTOSC2TRIM_REG { Uint32 all; struct INTOSC2TRIM_BITS bit; }; struct TSNSCTL_BITS { // bits description Uint16 ENABLE:1; // 0 Temperature Sensor Enable Uint16 rsvd1:15; // 15:1 Reserved }; union TSNSCTL_REG { Uint16 all; struct TSNSCTL_BITS bit; }; struct LOCK_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:1; // 6 Reserved Uint32 rsvd7:12; // 18:7 Reserved Uint16 rsvd8:1; // 19 Reserved Uint16 rsvd9:1; // 20 Reserved Uint16 rsvd10:1; // 21 Reserved Uint16 rsvd11:1; // 22 Reserved Uint16 rsvd12:1; // 23 Reserved Uint16 rsvd13:1; // 24 Reserved Uint16 rsvd14:1; // 25 Reserved Uint16 rsvd15:1; // 26 Reserved Uint16 rsvd16:1; // 27 Reserved Uint16 rsvd17:1; // 28 Reserved Uint16 rsvd18:1; // 29 Reserved Uint16 rsvd19:1; // 30 Reserved Uint16 rsvd20:1; // 31 Reserved }; union LOCK_REG { Uint32 all; struct LOCK_BITS bit; }; struct ANAREFTRIMA_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMA_REG { Uint32 all; struct ANAREFTRIMA_BITS bit; }; struct ANAREFTRIMB_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMB_REG { Uint32 all; struct ANAREFTRIMB_BITS bit; }; struct ANAREFTRIMC_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMC_REG { Uint32 all; struct ANAREFTRIMC_BITS bit; }; struct ANAREFTRIMD_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMD_REG { Uint32 all; struct ANAREFTRIMD_BITS bit; }; struct ANALOG_SUBSYS_REGS { Uint16 rsvd1[32]; // Reserved union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register Uint16 rsvd2[2]; // Reserved union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register Uint16 rsvd3[7]; // Reserved union LOCK_REG LOCK; // Lock Register Uint16 rsvd4[6]; // Reserved union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register Uint16 rsvd5[10]; // Reserved }; //--------------------------------------------------------------------------- // ANALOGSUBSYS External References & Function Declarations: // extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_cla.h // // TITLE: F2837xD Device CLA Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // CLA Individual Register Bit Definitions: struct MCTL_BITS { // bits description Uint16 HARDRESET:1; // 0 Hard Reset Uint16 SOFTRESET:1; // 1 Soft Reset Uint16 IACKE:1; // 2 IACK enable Uint16 rsvd1:13; // 15:3 Reserved }; union MCTL_REG { Uint16 all; struct MCTL_BITS bit; }; struct MIFR_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Flag Uint16 INT2:1; // 1 Task 2 Interrupt Flag Uint16 INT3:1; // 2 Task 3 Interrupt Flag Uint16 INT4:1; // 3 Task 4 Interrupt Flag Uint16 INT5:1; // 4 Task 5 Interrupt Flag Uint16 INT6:1; // 5 Task 6 Interrupt Flag Uint16 INT7:1; // 6 Task 7 Interrupt Flag Uint16 INT8:1; // 7 Task 8 Interrupt Flag Uint16 rsvd1:8; // 15:8 Reserved }; union MIFR_REG { Uint16 all; struct MIFR_BITS bit; }; struct MIOVF_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Uint16 rsvd1:8; // 15:8 Reserved }; union MIOVF_REG { Uint16 all; struct MIOVF_BITS bit; }; struct MIFRC_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Force Uint16 INT2:1; // 1 Task 2 Interrupt Force Uint16 INT3:1; // 2 Task 3 Interrupt Force Uint16 INT4:1; // 3 Task 4 Interrupt Force Uint16 INT5:1; // 4 Task 5 Interrupt Force Uint16 INT6:1; // 5 Task 6 Interrupt Force Uint16 INT7:1; // 6 Task 7 Interrupt Force Uint16 INT8:1; // 7 Task 8 Interrupt Force Uint16 rsvd1:8; // 15:8 Reserved }; union MIFRC_REG { Uint16 all; struct MIFRC_BITS bit; }; struct MICLR_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear Uint16 rsvd1:8; // 15:8 Reserved }; union MICLR_REG { Uint16 all; struct MICLR_BITS bit; }; struct MICLROVF_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear Uint16 rsvd1:8; // 15:8 Reserved }; union MICLROVF_REG { Uint16 all; struct MICLROVF_BITS bit; }; struct MIER_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Enable Uint16 INT2:1; // 1 Task 2 Interrupt Enable Uint16 INT3:1; // 2 Task 3 Interrupt Enable Uint16 INT4:1; // 3 Task 4 Interrupt Enable Uint16 INT5:1; // 4 Task 5 Interrupt Enable Uint16 INT6:1; // 5 Task 6 Interrupt Enable Uint16 INT7:1; // 6 Task 7 Interrupt Enable Uint16 INT8:1; // 7 Task 8 Interrupt Enable Uint16 rsvd1:8; // 15:8 Reserved }; union MIER_REG { Uint16 all; struct MIER_BITS bit; }; struct MIRUN_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Run Status Uint16 INT2:1; // 1 Task 2 Run Status Uint16 INT3:1; // 2 Task 3 Run Status Uint16 INT4:1; // 3 Task 4 Run Status Uint16 INT5:1; // 4 Task 5 Run Status Uint16 INT6:1; // 5 Task 6 Run Status Uint16 INT7:1; // 6 Task 7 Run Status Uint16 INT8:1; // 7 Task 8 Run Status Uint16 rsvd1:8; // 15:8 Reserved }; union MIRUN_REG { Uint16 all; struct MIRUN_BITS bit; }; struct _MSTF_BITS { // bits description Uint16 LVF:1; // 0 Latched Overflow Flag Uint16 LUF:1; // 1 Latched Underflow Flag Uint16 NF:1; // 2 Negative Float Flag Uint16 ZF:1; // 3 Zero Float Flag Uint16 rsvd1:2; // 5:4 Reserved Uint16 TF:1; // 6 Test Flag Uint16 rsvd2:2; // 8:7 Reserved Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode Uint16 rsvd3:1; // 10 Reserved Uint16 MEALLOW:1; // 11 MEALLOW Status Uint32 _RPC:16; // 27:12 Return PC Uint16 rsvd4:4; // 31:28 Reserved }; union _MSTF_REG { Uint32 all; struct _MSTF_BITS bit; }; union MR_REG { Uint32 i32; float f32; }; struct CLA_REGS { Uint16 MVECT1; // Task Interrupt Vector Uint16 MVECT2; // Task Interrupt Vector Uint16 MVECT3; // Task Interrupt Vector Uint16 MVECT4; // Task Interrupt Vector Uint16 MVECT5; // Task Interrupt Vector Uint16 MVECT6; // Task Interrupt Vector Uint16 MVECT7; // Task Interrupt Vector Uint16 MVECT8; // Task Interrupt Vector Uint16 rsvd1[8]; // Reserved union MCTL_REG MCTL; // Control Register Uint16 rsvd2[15]; // Reserved union MIFR_REG MIFR; // Interrupt Flag Register union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register union MIFRC_REG MIFRC; // Interrupt Force Register union MICLR_REG MICLR; // Interrupt Flag Clear Register union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register union MIER_REG MIER; // Interrupt Enable Register union MIRUN_REG MIRUN; // Interrupt Run Status Register Uint16 rsvd3; // Reserved Uint16 _MPC; // CLA Program Counter Uint16 rsvd4; // Reserved Uint16 _MAR0; // CLA Auxiliary Register 0 Uint16 _MAR1; // CLA Auxiliary Register 1 Uint16 rsvd5[2]; // Reserved union _MSTF_REG _MSTF; // CLA Floating-Point Status Register union MR_REG _MR0; // CLA Floating-Point Result Register 0 Uint16 rsvd6[2]; // Reserved union MR_REG _MR1; // CLA Floating-Point Result Register 1 Uint16 rsvd7[2]; // Reserved union MR_REG _MR2; // CLA Floating-Point Result Register 2 Uint16 rsvd8[2]; // Reserved union MR_REG _MR3; // CLA Floating-Point Result Register 3 }; struct SOFTINTEN_BITS { // bits description Uint16 TASK1:1; // 0 Task 1 Software Interrupt Enable Uint16 TASK2:1; // 1 Task 2 Software Interrupt Enable Uint16 TASK3:1; // 2 Task 3 Software Interrupt Enable Uint16 TASK4:1; // 3 Task 4 Software Interrupt Enable Uint16 TASK5:1; // 4 Task 5 Software Interrupt Enable Uint16 TASK6:1; // 5 Task 6 Software Interrupt Enable Uint16 TASK7:1; // 6 Task 7 Software Interrupt Enable Uint16 TASK8:1; // 7 Task 8 Software Interrupt Enable Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTINTEN_REG { Uint32 all; struct SOFTINTEN_BITS bit; }; struct SOFTINTFRC_BITS { // bits description Uint16 TASK1:1; // 0 Task 1 Software Interrupt Force Uint16 TASK2:1; // 1 Task 2 Software Interrupt Force Uint16 TASK3:1; // 2 Task 3 Software Interrupt Force Uint16 TASK4:1; // 3 Task 4 Software Interrupt Force Uint16 TASK5:1; // 4 Task 5 Software Interrupt Force Uint16 TASK6:1; // 5 Task 6 Software Interrupt Force Uint16 TASK7:1; // 6 Task 7 Software Interrupt Force Uint16 TASK8:1; // 7 Task 8 Software Interrupt Force Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTINTFRC_REG { Uint32 all; struct SOFTINTFRC_BITS bit; }; struct CLA_SOFTINT_REGS { union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register }; //--------------------------------------------------------------------------- // CLA External References & Function Declarations: // extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; extern volatile struct CLA_REGS Cla1Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_cmpss.h // // TITLE: F2837xD Device CMPSS Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // CMPSS Individual Register Bit Definitions: struct COMPCTL_BITS { // bits description Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select Uint16 COMPHINV:1; // 1 High Comparator Invert Select Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable Uint16 rsvd1:1; // 7 Reserved Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select Uint16 COMPLINV:1; // 9 Low Comparator Invert Select Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable Uint16 COMPDACE:1; // 15 Comparator/DAC Enable }; union COMPCTL_REG { Uint16 all; struct COMPCTL_BITS bit; }; struct COMPHYSCTL_BITS { // bits description Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim Uint16 rsvd1:13; // 15:3 Reserved }; union COMPHYSCTL_REG { Uint16 all; struct COMPHYSCTL_BITS bit; }; struct COMPSTS_BITS { // bits description Uint16 COMPHSTS:1; // 0 High Comparator Status Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status Uint16 rsvd1:6; // 7:2 Reserved Uint16 COMPLSTS:1; // 8 Low Comparator Status Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status Uint16 rsvd2:6; // 15:10 Reserved }; union COMPSTS_REG { Uint16 all; struct COMPSTS_BITS bit; }; struct COMPSTSCLR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear Uint16 HSYNCCLREN:1; // 2 High Comparator PWMSYNC Clear Enable Uint16 rsvd2:6; // 8:3 Reserved Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear Uint16 LSYNCCLREN:1; // 10 Low Comparator PWMSYNC Clear Enable Uint16 rsvd3:5; // 15:11 Reserved }; union COMPSTSCLR_REG { Uint16 all; struct COMPSTSCLR_BITS bit; }; struct COMPDACCTL_BITS { // bits description Uint16 DACSOURCE:1; // 0 DAC Source Control Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control Uint16 SELREF:1; // 5 DAC Reference Select Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select Uint16 SWLOADSEL:1; // 7 Software Load Select Uint16 rsvd1:6; // 13:8 Reserved Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits }; union COMPDACCTL_REG { Uint16 all; struct COMPDACCTL_BITS bit; }; struct DACHVALS_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACHVALS_REG { Uint16 all; struct DACHVALS_BITS bit; }; struct DACHVALA_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACHVALA_REG { Uint16 all; struct DACHVALA_BITS bit; }; struct DACLVALS_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACLVALS_REG { Uint16 all; struct DACLVALS_BITS bit; }; struct DACLVALA_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACLVALA_REG { Uint16 all; struct DACLVALA_BITS bit; }; struct RAMPDLYA_BITS { // bits description Uint16 DELAY:13; // 12:0 Ramp Delay Value Uint16 rsvd1:3; // 15:13 Reserved }; union RAMPDLYA_REG { Uint16 all; struct RAMPDLYA_BITS bit; }; struct RAMPDLYS_BITS { // bits description Uint16 DELAY:13; // 12:0 Ramp Delay Value Uint16 rsvd1:3; // 15:13 Reserved }; union RAMPDLYS_REG { Uint16 all; struct RAMPDLYS_BITS bit; }; struct CTRIPLFILCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union CTRIPLFILCTL_REG { Uint16 all; struct CTRIPLFILCTL_BITS bit; }; struct CTRIPLFILCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union CTRIPLFILCLKCTL_REG { Uint16 all; struct CTRIPLFILCLKCTL_BITS bit; }; struct CTRIPHFILCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union CTRIPHFILCTL_REG { Uint16 all; struct CTRIPHFILCTL_BITS bit; }; struct CTRIPHFILCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union CTRIPHFILCLKCTL_REG { Uint16 all; struct CTRIPHFILCLKCTL_BITS bit; }; struct COMPLOCK_BITS { // bits description Uint16 COMPCTL:1; // 0 COMPCTL Lock Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock Uint16 DACCTL:1; // 2 DACCTL Lock Uint16 CTRIP:1; // 3 CTRIP Lock Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:11; // 15:5 Reserved }; union COMPLOCK_REG { Uint16 all; struct COMPLOCK_BITS bit; }; struct CMPSS_REGS { union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register Uint16 rsvd1; // Reserved union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register Uint16 rsvd2; // Reserved Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register Uint16 rsvd3; // Reserved Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register Uint16 rsvd4; // Reserved Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register Uint16 rsvd5; // Reserved Uint16 RAMPSTS; // CMPSS Ramp Status Register Uint16 rsvd6; // Reserved union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register Uint16 rsvd7[5]; // Reserved }; //--------------------------------------------------------------------------- // CMPSS External References & Function Declarations: // extern volatile struct CMPSS_REGS Cmpss1Regs; extern volatile struct CMPSS_REGS Cmpss2Regs; extern volatile struct CMPSS_REGS Cmpss3Regs; extern volatile struct CMPSS_REGS Cmpss4Regs; extern volatile struct CMPSS_REGS Cmpss5Regs; extern volatile struct CMPSS_REGS Cmpss6Regs; extern volatile struct CMPSS_REGS Cmpss7Regs; extern volatile struct CMPSS_REGS Cmpss8Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_cputimer.h // // TITLE: F2837xD Device CPUTIMER Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // CPUTIMER Individual Register Bit Definitions: struct TIM_BITS { // bits description Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High }; union TIM_REG { Uint32 all; struct TIM_BITS bit; }; struct PRD_BITS { // bits description Uint16 LSW:16; // 15:0 CPU-Timer Period Registers Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High }; union PRD_REG { Uint32 all; struct PRD_BITS bit; }; struct TCR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 TSS:1; // 4 CPU-Timer stop status bit. Uint16 TRB:1; // 5 Timer reload Uint16 rsvd2:4; // 9:6 Reserved Uint16 SOFT:1; // 10 Emulation modes Uint16 FREE:1; // 11 Emulation modes Uint16 rsvd3:2; // 13:12 Reserved Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. }; union TCR_REG { Uint16 all; struct TCR_BITS bit; }; struct TPR_BITS { // bits description Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. }; union TPR_REG { Uint16 all; struct TPR_BITS bit; }; struct TPRH_BITS { // bits description Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. }; union TPRH_REG { Uint16 all; struct TPRH_BITS bit; }; struct CPUTIMER_REGS { union TIM_REG TIM; // CPU-Timer, Counter Register union PRD_REG PRD; // CPU-Timer, Period Register union TCR_REG TCR; // CPU-Timer, Control Register Uint16 rsvd1; // Reserved union TPR_REG TPR; // CPU-Timer, Prescale Register union TPRH_REG TPRH; // CPU-Timer, Prescale Register High }; //--------------------------------------------------------------------------- // CPUTIMER External References & Function Declarations: // extern volatile struct CPUTIMER_REGS CpuTimer0Regs; extern volatile struct CPUTIMER_REGS CpuTimer1Regs; extern volatile struct CPUTIMER_REGS CpuTimer2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_dac.h // // TITLE: F2837xD Device DAC Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // DAC Individual Register Bit Definitions: struct DACREV_BITS { // bits description Uint16 REV:8; // 7:0 DAC Revision Register Uint16 rsvd1:8; // 15:8 Reserved }; union DACREV_REG { Uint16 all; struct DACREV_BITS bit; }; struct DACCTL_BITS { // bits description Uint16 DACREFSEL:1; // 0 DAC Reference Select Uint16 rsvd1:1; // 1 Reserved Uint16 LOADMODE:1; // 2 DACVALA Load Mode Uint16 rsvd2:1; // 3 Reserved Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select Uint16 rsvd3:8; // 15:8 Reserved }; union DACCTL_REG { Uint16 all; struct DACCTL_BITS bit; }; struct DACVALA_BITS { // bits description Uint16 DACVALA:12; // 11:0 DAC Active Output Code Uint16 rsvd1:4; // 15:12 Reserved }; union DACVALA_REG { Uint16 all; struct DACVALA_BITS bit; }; struct DACVALS_BITS { // bits description Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code Uint16 rsvd1:4; // 15:12 Reserved }; union DACVALS_REG { Uint16 all; struct DACVALS_BITS bit; }; struct DACOUTEN_BITS { // bits description Uint16 DACOUTEN:1; // 0 DAC Output Code Uint16 rsvd1:15; // 15:1 Reserved }; union DACOUTEN_REG { Uint16 all; struct DACOUTEN_BITS bit; }; struct DACLOCK_BITS { // bits description Uint16 DACCTL:1; // 0 DAC Control Register Lock Uint16 DACVAL:1; // 1 DAC Value Register Lock Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock Uint16 rsvd1:13; // 15:3 Reserved }; union DACLOCK_REG { Uint16 all; struct DACLOCK_BITS bit; }; struct DACTRIM_BITS { // bits description Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim Uint16 rsvd1:4; // 11:8 Reserved Uint16 rsvd2:4; // 15:12 Reserved }; union DACTRIM_REG { Uint16 all; struct DACTRIM_BITS bit; }; struct DAC_REGS { union DACREV_REG DACREV; // DAC Revision Register union DACCTL_REG DACCTL; // DAC Control Register union DACVALA_REG DACVALA; // DAC Value Register - Active union DACVALS_REG DACVALS; // DAC Value Register - Shadow union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register union DACLOCK_REG DACLOCK; // DAC Lock Register union DACTRIM_REG DACTRIM; // DAC Trim Register Uint16 rsvd1; // Reserved }; //--------------------------------------------------------------------------- // DAC External References & Function Declarations: // extern volatile struct DAC_REGS DacaRegs; extern volatile struct DAC_REGS DacbRegs; extern volatile struct DAC_REGS DaccRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_dcsm.h // // TITLE: F2837xD Device DCSM Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // DCSM Individual Register Bit Definitions: struct DCSM_Z1_OTP { Uint32 Z1OTP_LINKPOINTER1; // Zone 1 Link Pointer1 in Z1 OTP Uint16 rsvd1[2]; // Reserved Uint32 Z1OTP_LINKPOINTER2; // Zone 1 Link Pointer2 in Z1 OTP Uint16 rsvd2[2]; // Reserved Uint32 Z1OTP_LINKPOINTER3; // Zone 1 Link Pointer3 in Z1 OTP Uint16 rsvd3[6]; // Reserved Uint32 Z1OTP_PSWDLOCK; // Secure Password Lock in Z1 OTP Uint16 rsvd4[2]; // Reserved Uint32 Z1OTP_CRCLOCK; // Secure CRC Lock in Z1 OTP Uint16 rsvd5[8]; // Reserved Uint32 Z1OTP_BOOTCTRL; // Boot Mode in Z1 OTP }; struct DCSM_Z2_OTP { Uint32 Z2OTP_LINKPOINTER1; // Zone 2 Link Pointer1 in Z2 OTP Uint16 rsvd1[2]; // Reserved Uint32 Z2OTP_LINKPOINTER2; // Zone 2 Link Pointer2 in Z2 OTP Uint16 rsvd2[2]; // Reserved Uint32 Z2OTP_LINKPOINTER3; // Zone 2 Link Pointer3 in Z2 OTP Uint16 rsvd3[6]; // Reserved Uint32 Z2OTP_PSWDLOCK; // Secure Password Lock in Z2 OTP Uint16 rsvd4[2]; // Reserved Uint32 Z2OTP_CRCLOCK; // Secure CRC Lock in Z2 OTP Uint16 rsvd5[8]; // Reserved Uint32 Z2OTP_BOOTCTRL; // Boot Mode in Z2 OTP }; struct Z1_LINKPOINTER_BITS { // bits description Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer. Uint16 rsvd1:3; // 31:29 Reserved }; union Z1_LINKPOINTER_REG { Uint32 all; struct Z1_LINKPOINTER_BITS bit; }; struct Z1_OTPSECLOCK_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union Z1_OTPSECLOCK_REG { Uint32 all; struct Z1_OTPSECLOCK_BITS bit; }; struct Z1_BOOTCTRL_BITS { // bits description Uint16 KEY:8; // 7:0 OTP Boot Key Uint16 BMODE:8; // 15:8 OTP Boot Mode Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping }; union Z1_BOOTCTRL_REG { Uint32 all; struct Z1_BOOTCTRL_BITS bit; }; struct Z1_CR_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros Uint16 ALLONE:1; // 4 CSMPSWD All Ones Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY Uint16 ARMED:1; // 6 CSM Armed Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:7; // 14:8 Reserved Uint16 FORCESEC:1; // 15 Force Secure }; union Z1_CR_REG { Uint16 all; struct Z1_CR_BITS bit; }; struct Z1_GRABSECTR_BITS { // bits description Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N Uint16 rsvd1:2; // 29:28 Reserved Uint16 rsvd2:2; // 31:30 Reserved }; union Z1_GRABSECTR_REG { Uint32 all; struct Z1_GRABSECTR_BITS bit; }; struct Z1_GRABRAMR_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 Uint16 rsvd1:12; // 27:16 Reserved Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 Uint16 rsvd2:2; // 31:30 Reserved }; union Z1_GRABRAMR_REG { Uint32 all; struct Z1_GRABRAMR_BITS bit; }; struct Z1_EXEONLYSECTR_BITS { // bits description Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N Uint16 rsvd1:1; // 14 Reserved Uint16 rsvd2:1; // 15 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union Z1_EXEONLYSECTR_REG { Uint32 all; struct Z1_EXEONLYSECTR_BITS bit; }; struct Z1_EXEONLYRAMR_BITS { // bits description Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_EXEONLYRAMR_REG { Uint32 all; struct Z1_EXEONLYRAMR_BITS bit; }; struct DCSM_Z1_REGS { union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock union Z1_BOOTCTRL_REG Z1_BOOTCTRL; // Boot Mode Uint32 Z1_LINKPOINTERERR; // Link Pointer Error Uint16 rsvd1[8]; // Reserved Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 Uint16 rsvd2; // Reserved union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register union Z1_GRABSECTR_REG Z1_GRABSECTR; // Zone 1 Grab Flash Sectors Register union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register union Z1_EXEONLYSECTR_REG Z1_EXEONLYSECTR; // Zone 1 Flash Execute_Only Sector Register union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register Uint16 rsvd3; // Reserved }; struct Z2_LINKPOINTER_BITS { // bits description Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer. Uint16 rsvd1:3; // 31:29 Reserved }; union Z2_LINKPOINTER_REG { Uint32 all; struct Z2_LINKPOINTER_BITS bit; }; struct Z2_OTPSECLOCK_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union Z2_OTPSECLOCK_REG { Uint32 all; struct Z2_OTPSECLOCK_BITS bit; }; struct Z2_BOOTCTRL_BITS { // bits description Uint16 KEY:8; // 7:0 OTP Boot Key Uint16 BMODE:8; // 15:8 OTP Boot Mode Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping }; union Z2_BOOTCTRL_REG { Uint32 all; struct Z2_BOOTCTRL_BITS bit; }; struct Z2_CR_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros Uint16 ALLONE:1; // 4 CSMPSWD All Ones Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY Uint16 ARMED:1; // 6 CSM Armed Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:7; // 14:8 Reserved Uint16 FORCESEC:1; // 15 Force Secure }; union Z2_CR_REG { Uint16 all; struct Z2_CR_BITS bit; }; struct Z2_GRABSECTR_BITS { // bits description Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N Uint16 rsvd1:2; // 29:28 Reserved Uint16 rsvd2:2; // 31:30 Reserved }; union Z2_GRABSECTR_REG { Uint32 all; struct Z2_GRABSECTR_BITS bit; }; struct Z2_GRABRAMR_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 Uint16 rsvd1:12; // 27:16 Reserved Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 Uint16 rsvd2:2; // 31:30 Reserved }; union Z2_GRABRAMR_REG { Uint32 all; struct Z2_GRABRAMR_BITS bit; }; struct Z2_EXEONLYSECTR_BITS { // bits description Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N Uint16 rsvd1:1; // 14 Reserved Uint16 rsvd2:1; // 15 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union Z2_EXEONLYSECTR_REG { Uint32 all; struct Z2_EXEONLYSECTR_BITS bit; }; struct Z2_EXEONLYRAMR_BITS { // bits description Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z2_EXEONLYRAMR_REG { Uint32 all; struct Z2_EXEONLYRAMR_BITS bit; }; struct DCSM_Z2_REGS { union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock union Z2_BOOTCTRL_REG Z2_BOOTCTRL; // Boot Mode Uint32 Z2_LINKPOINTERERR; // Link Pointer Error Uint16 rsvd1[8]; // Reserved Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 Uint16 rsvd2; // Reserved union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register union Z2_GRABSECTR_REG Z2_GRABSECTR; // Zone 2 Grab Flash Sectors Register union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register union Z2_EXEONLYSECTR_REG Z2_EXEONLYSECTR; // Zone 2 Flash Execute_Only Sector Register union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register Uint16 rsvd3; // Reserved }; struct FLSEM_BITS { // bits description Uint16 SEM:2; // 1:0 Flash Semaphore Bit Uint16 rsvd1:6; // 7:2 Reserved Uint16 KEY:8; // 15:8 Semaphore Key Uint16 rsvd2:16; // 31:16 Reserved }; union FLSEM_REG { Uint32 all; struct FLSEM_BITS bit; }; struct SECTSTAT_BITS { // bits description Uint16 STATUS_SECTA:2; // 1:0 Zone Status Flash Sector A Uint16 STATUS_SECTB:2; // 3:2 Zone Status Flash Sector B Uint16 STATUS_SECTC:2; // 5:4 Zone Status Flash Sector C Uint16 STATUS_SECTD:2; // 7:6 Zone Status Flash Sector D Uint16 STATUS_SECTE:2; // 9:8 Zone Status Flash Sector E Uint16 STATUS_SECTF:2; // 11:10 Zone Status Flash Sector F Uint16 STATUS_SECTG:2; // 13:12 Zone Status Flash Sector G Uint16 STATUS_SECTH:2; // 15:14 Zone Status Flash Sector H Uint16 STATUS_SECTI:2; // 17:16 Zone Status Flash Sector I Uint16 STATUS_SECTJ:2; // 19:18 Zone Status Flash Sector J Uint16 STATUS_SECTK:2; // 21:20 Zone Status Flash Sector K Uint16 STATUS_SECTL:2; // 23:22 Zone Status Flash Sector L Uint16 STATUS_SECTM:2; // 25:24 Zone Status Flash Sector M Uint16 STATUS_SECTN:2; // 27:26 Zone Status Flash Sector N Uint16 rsvd1:2; // 29:28 Reserved Uint16 rsvd2:2; // 31:30 Reserved }; union SECTSTAT_REG { Uint32 all; struct SECTSTAT_BITS bit; }; struct RAMSTAT_BITS { // bits description Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM D0 Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM D1 Uint16 rsvd1:12; // 27:16 Reserved Uint16 STATUS_CLA1:2; // 29:28 Zone Status CLA1 Uint16 rsvd2:2; // 31:30 Reserved }; union RAMSTAT_REG { Uint32 all; struct RAMSTAT_BITS bit; }; struct DCSM_COMMON_REGS { union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register union SECTSTAT_REG SECTSTAT; // Sectors Status Register union RAMSTAT_REG RAMSTAT; // RAM Status Register Uint16 rsvd1[2]; // Reserved }; //--------------------------------------------------------------------------- // DCSM External References & Function Declarations: // extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_dma.h // // TITLE: F2837xD Device DMA Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // DMA Individual Register Bit Definitions: struct MODE_BITS { // bits description Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Uint16 rsvd1:2; // 6:5 Reserved Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Uint16 ONESHOT:1; // 10 One Shot Mode Bit Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit Uint16 rsvd2:2; // 13:12 Reserved Uint16 DATASIZE:1; // 14 Data Size Mode Bit Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit }; union MODE_REG { Uint16 all; struct MODE_BITS bit; }; struct CONTROL_BITS { // bits description Uint16 RUN:1; // 0 Run Bit Uint16 HALT:1; // 1 Halt Bit Uint16 SOFTRESET:1; // 2 Soft Reset Bit Uint16 PERINTFRC:1; // 3 Interrupt Force Bit Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit Uint16 rsvd2:2; // 6:5 Reserved Uint16 ERRCLR:1; // 7 Error Clear Bit Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit Uint16 SYNCFLG:1; // 9 Sync Flag Bit Uint16 SYNCERR:1; // 10 Sync Error Flag Bit Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit Uint16 BURSTSTS:1; // 12 Burst Status Bit Uint16 RUNSTS:1; // 13 Run Status Bit Uint16 OVRFLG:1; // 14 Overflow Flag Bit Uint16 rsvd1:1; // 15 Reserved }; union CONTROL_REG { Uint16 all; struct CONTROL_BITS bit; }; struct DMACTRL_BITS { // bits description Uint16 HARDRESET:1; // 0 Hard Reset Bit Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit Uint16 rsvd1:14; // 15:2 Reserved }; union DMACTRL_REG { Uint16 all; struct DMACTRL_BITS bit; }; struct DEBUGCTRL_BITS { // bits description Uint16 rsvd1:15; // 14:0 Reserved Uint16 FREE:1; // 15 Debug Mode Bit }; union DEBUGCTRL_REG { Uint16 all; struct DEBUGCTRL_BITS bit; }; struct PRIORITYCTRL1_BITS { // bits description Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit Uint16 rsvd1:15; // 15:1 Reserved }; union PRIORITYCTRL1_REG { Uint16 all; struct PRIORITYCTRL1_BITS bit; }; struct PRIORITYSTAT_BITS { // bits description Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits Uint16 rsvd1:1; // 3 Reserved Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits Uint16 rsvd2:9; // 15:7 Reserved }; union PRIORITYSTAT_REG { Uint16 all; struct PRIORITYSTAT_BITS bit; }; struct BURST_SIZE_BITS { // bits description Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size Uint16 rsvd1:11; // 15:5 Reserved }; union BURST_SIZE_REG { Uint16 all; struct BURST_SIZE_BITS bit; }; struct BURST_COUNT_BITS { // bits description Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count Uint16 rsvd1:11; // 15:5 Reserved }; union BURST_COUNT_REG { Uint16 all; struct BURST_COUNT_BITS bit; }; struct CH_REGS { union MODE_REG MODE; // Mode Register union CONTROL_REG CONTROL; // Control Register union BURST_SIZE_REG BURST_SIZE; // Burst Size Register union BURST_COUNT_REG BURST_COUNT; // Burst Count Register int16 SRC_BURST_STEP; // Source Burst Step Register int16 DST_BURST_STEP; // Destination Burst Step Register Uint16 TRANSFER_SIZE; // Transfer Size Register Uint16 TRANSFER_COUNT; // Transfer Count Register int16 SRC_TRANSFER_STEP; // Source Transfer Step Register int16 DST_TRANSFER_STEP; // Destination Transfer Step Register Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register int16 SRC_WRAP_STEP; // Source Wrap Step Register Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register int16 DST_WRAP_STEP; // Destination Wrap Step Register Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register }; struct DMA_REGS { union DMACTRL_REG DMACTRL; // DMA Control Register union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register Uint16 rsvd0; // Reserved Uint16 rsvd1; // Reserved union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register Uint16 rsvd2; // Reserved union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register Uint16 rsvd3[25]; // Reserved struct CH_REGS CH1; // DMA Channel 1 Registers struct CH_REGS CH2; // DMA Channel 2 Registers struct CH_REGS CH3; // DMA Channel 3 Registers struct CH_REGS CH4; // DMA Channel 4 Registers struct CH_REGS CH5; // DMA Channel 5 Registers struct CH_REGS CH6; // DMA Channel 6 Registers }; //--------------------------------------------------------------------------- // DMA External References & Function Declarations: // extern volatile struct DMA_REGS DmaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_ecap.h // // TITLE: F2837xD Device ECAP Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // ECAP Individual Register Bit Definitions: struct ECCTL1_BITS { // bits description Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event Uint16 PRESCALE:5; // 13:9 Event Filter prescale select Uint16 FREE_SOFT:2; // 15:14 Emulation mode }; union ECCTL1_REG { Uint16 all; struct ECCTL1_BITS bit; }; struct ECCTL2_BITS { // bits description Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous Uint16 REARM:1; // 3 One-shot re-arm Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop Uint16 SYNCI_EN:1; // 5 Counter sync-in select Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode Uint16 SWSYNC:1; // 8 SW forced counter sync Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select Uint16 APWMPOL:1; // 10 APWM output polarity select Uint16 rsvd1:5; // 15:11 Reserved }; union ECCTL2_REG { Uint16 all; struct ECCTL2_BITS bit; }; struct ECEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable Uint16 rsvd2:8; // 15:8 Reserved }; union ECEINT_REG { Uint16 all; struct ECEINT_BITS bit; }; struct ECFLG_BITS { // bits description Uint16 INT:1; // 0 Global Flag Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag Uint16 rsvd1:8; // 15:8 Reserved }; union ECFLG_REG { Uint16 all; struct ECFLG_BITS bit; }; struct ECCLR_BITS { // bits description Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear Uint16 CTROVF:1; // 5 Counter Overflow Status Clear Uint16 CTR_PRD:1; // 6 Period Equal Status Clear Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear Uint16 rsvd1:8; // 15:8 Reserved }; union ECCLR_REG { Uint16 all; struct ECCLR_BITS bit; }; struct ECFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt Uint16 rsvd2:8; // 15:8 Reserved }; union ECFRC_REG { Uint16 all; struct ECFRC_BITS bit; }; struct ECAP_REGS { Uint32 TSCTR; // Time-Stamp Counter Uint32 CTRPHS; // Counter Phase Offset Value Register Uint32 CAP1; // Capture 1 Register Uint32 CAP2; // Capture 2 Register Uint32 CAP3; // Capture 3 Register Uint32 CAP4; // Capture 4 Register Uint16 rsvd1[8]; // Reserved union ECCTL1_REG ECCTL1; // Capture Control Register 1 union ECCTL2_REG ECCTL2; // Capture Control Register 2 union ECEINT_REG ECEINT; // Capture Interrupt Enable Register union ECFLG_REG ECFLG; // Capture Interrupt Flag Register union ECCLR_REG ECCLR; // Capture Interrupt Clear Register union ECFRC_REG ECFRC; // Capture Interrupt Force Register Uint16 rsvd2[6]; // Reserved }; //--------------------------------------------------------------------------- // ECAP External References & Function Declarations: // extern volatile struct ECAP_REGS ECap1Regs; extern volatile struct ECAP_REGS ECap2Regs; extern volatile struct ECAP_REGS ECap3Regs; extern volatile struct ECAP_REGS ECap4Regs; extern volatile struct ECAP_REGS ECap5Regs; extern volatile struct ECAP_REGS ECap6Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_emif.h // // TITLE: F2837xD Device EMIF Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // EMIF Individual Register Bit Definitions: struct RCSR_BITS { // bits description Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. Uint16 MODULE_ID:14; // 29:16 EMIF module ID. Uint16 FR:1; // 30 EMIF is running in full rate or half rate. Uint16 BE:1; // 31 EMIF endian mode. }; union RCSR_REG { Uint32 all; struct RCSR_BITS bit; }; struct ASYNC_WCCR_BITS { // bits description Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:2; // 17:16 Reserved Uint16 rsvd3:2; // 19:18 Reserved Uint16 rsvd4:2; // 21:20 Reserved Uint16 rsvd5:2; // 23:22 Reserved Uint16 rsvd6:4; // 27:24 Reserved Uint16 WP0:1; // 28 Polarity for EMxWAIT. Uint16 rsvd7:1; // 29 Reserved Uint16 rsvd8:1; // 30 Reserved Uint16 rsvd9:1; // 31 Reserved }; union ASYNC_WCCR_REG { Uint32 all; struct ASYNC_WCCR_BITS bit; }; struct SDRAM_CR_BITS { // bits description Uint16 PAGESIGE:3; // 2:0 Page Size. Uint16 rsvd1:1; // 3 Reserved Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. Uint16 rsvd2:1; // 7 Reserved Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. Uint16 CL:3; // 11:9 CAS Latency. Uint16 rsvd3:1; // 12 Reserved Uint16 rsvd4:1; // 13 Reserved Uint16 NM:1; // 14 Narrow Mode. Uint16 rsvd5:1; // 15 Reserved Uint16 rsvd6:1; // 16 Reserved Uint16 rsvd7:2; // 18:17 Reserved Uint16 rsvd8:1; // 19 Reserved Uint16 rsvd9:3; // 22:20 Reserved Uint16 rsvd10:3; // 25:23 Reserved Uint16 rsvd11:3; // 28:26 Reserved Uint16 PDWR:1; // 29 Perform refreshes during Power Down. Uint16 PD:1; // 30 Power Down. Uint16 SR:1; // 31 Self Refresh. }; union SDRAM_CR_REG { Uint32 all; struct SDRAM_CR_BITS bit; }; struct SDRAM_RCR_BITS { // bits description Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. Uint16 rsvd1:3; // 15:13 Reserved Uint16 rsvd2:3; // 18:16 Reserved Uint16 rsvd3:13; // 31:19 Reserved }; union SDRAM_RCR_REG { Uint32 all; struct SDRAM_RCR_BITS bit; }; struct ASYNC_CS2_CR_BITS { // bits description Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. Uint16 TA:2; // 3:2 Turn Around cycles. Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. Uint16 EW:1; // 30 Extend Wait mode. Uint16 SS:1; // 31 Select Strobe mode. }; union ASYNC_CS2_CR_REG { Uint32 all; struct ASYNC_CS2_CR_BITS bit; }; struct ASYNC_CS3_CR_BITS { // bits description Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. Uint16 TA:2; // 3:2 Turn Around cycles. Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. Uint16 EW:1; // 30 Extend Wait mode. Uint16 SS:1; // 31 Select Strobe mode. }; union ASYNC_CS3_CR_REG { Uint32 all; struct ASYNC_CS3_CR_BITS bit; }; struct ASYNC_CS4_CR_BITS { // bits description Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. Uint16 TA:2; // 3:2 Turn Around cycles. Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. Uint16 EW:1; // 30 Extend Wait mode. Uint16 SS:1; // 31 Select Strobe mode. }; union ASYNC_CS4_CR_REG { Uint32 all; struct ASYNC_CS4_CR_BITS bit; }; struct SDRAM_TR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. Uint16 rsvd2:1; // 7 Reserved Uint16 T_RC:4; // 11:8 Activate to Activate timing . Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. Uint16 rsvd3:1; // 19 Reserved Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. Uint16 rsvd4:1; // 23 Reserved Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing }; union SDRAM_TR_REG { Uint32 all; struct SDRAM_TR_BITS bit; }; struct SDR_EXT_TMNG_BITS { // bits description Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. Uint16 rsvd1:11; // 15:5 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SDR_EXT_TMNG_REG { Uint32 all; struct SDR_EXT_TMNG_BITS bit; }; struct INT_RAW_BITS { // bits description Uint16 AT:1; // 0 Asynchronous Timeout. Uint16 LT:1; // 1 Line Trap. Uint16 WR:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_RAW_REG { Uint32 all; struct INT_RAW_BITS bit; }; struct INT_MSK_BITS { // bits description Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. Uint16 LT_MASKED:1; // 1 Line Trap. Uint16 WR_MASKED:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_MSK_REG { Uint32 all; struct INT_MSK_BITS bit; }; struct INT_MSK_SET_BITS { // bits description Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. Uint16 LT_MASK_SET:1; // 1 Line Trap. Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_MSK_SET_REG { Uint32 all; struct INT_MSK_SET_BITS bit; }; struct INT_MSK_CLR_BITS { // bits description Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. Uint16 LT_MASK_CLR:1; // 1 Line Trap. Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_MSK_CLR_REG { Uint32 all; struct INT_MSK_CLR_BITS bit; }; struct EMIF_REGS { union RCSR_REG RCSR; // Revision Code and Status Register union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register Uint16 rsvd1[2]; // Reserved union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register Uint16 rsvd2[6]; // Reserved Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register Uint16 rsvd3[2]; // Reserved union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register union INT_RAW_REG INT_RAW; // Interrupt Raw Register union INT_MSK_REG INT_MSK; // Interrupt Masked Register union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register Uint16 rsvd4[72]; // Reserved }; //--------------------------------------------------------------------------- // EMIF External References & Function Declarations: // extern volatile struct EMIF_REGS Emif1Regs; extern volatile struct EMIF_REGS Emif2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_epwm.h // // TITLE: F2837xD Device EPWM Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // EPWM Individual Register Bit Definitions: struct TBCTL_BITS { // bits description Uint16 CTRMODE:2; // 1:0 Counter Mode Uint16 PHSEN:1; // 2 Phase Load Enable Uint16 PRDLD:1; // 3 Active Period Load Uint16 SYNCOSEL:2; // 5:4 Sync Output Select Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler Uint16 PHSDIR:1; // 13 Phase Direction Bit Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits }; union TBCTL_REG { Uint16 all; struct TBCTL_BITS bit; }; struct TBCTL2_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 SELFCLRTRREM:1; // 5 Self clear Translator reminder Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode Uint16 OSHTSYNC:1; // 7 One shot sync Uint16 rsvd2:4; // 11:8 Reserved Uint16 SYNCOSELX:2; // 13:12 Syncout selection Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event }; union TBCTL2_REG { Uint16 all; struct TBCTL2_BITS bit; }; struct TBSTS_BITS { // bits description Uint16 CTRDIR:1; // 0 Counter Direction Status Uint16 SYNCI:1; // 1 External Input Sync Status Uint16 CTRMAX:1; // 2 Counter Max Latched Status Uint16 rsvd1:13; // 15:3 Reserved }; union TBSTS_REG { Uint16 all; struct TBSTS_BITS bit; }; struct CMPCTL_BITS { // bits description Uint16 LOADAMODE:2; // 1:0 Active Compare A Load Uint16 LOADBMODE:2; // 3:2 Active Compare B Load Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode Uint16 rsvd2:1; // 7 Reserved Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC Uint16 rsvd3:2; // 15:14 Reserved }; union CMPCTL_REG { Uint16 all; struct CMPCTL_BITS bit; }; struct CMPCTL2_BITS { // bits description Uint16 LOADCMODE:2; // 1:0 Active Compare C Load Uint16 LOADDMODE:2; // 3:2 Active Compare D load Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode Uint16 rsvd2:3; // 9:7 Reserved Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC Uint16 rsvd3:2; // 15:14 Reserved }; union CMPCTL2_REG { Uint16 all; struct CMPCTL2_BITS bit; }; struct DBCTL_BITS { // bits description Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control Uint16 POLSEL:2; // 3:2 Polarity Select Control Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable }; union DBCTL_REG { Uint16 all; struct DBCTL_BITS bit; }; struct DBCTL2_BITS { // bits description Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select Uint16 rsvd1:13; // 15:3 Reserved }; union DBCTL2_REG { Uint16 all; struct DBCTL2_BITS bit; }; struct AQCTL_BITS { // bits description Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode Uint16 rsvd2:1; // 7 Reserved Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC Uint16 rsvd3:4; // 15:12 Reserved }; union AQCTL_REG { Uint16 all; struct AQCTL_BITS bit; }; struct AQTSRCSEL_BITS { // bits description Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits Uint16 rsvd1:8; // 15:8 Reserved }; union AQTSRCSEL_REG { Uint16 all; struct AQTSRCSEL_BITS bit; }; struct PCCTL_BITS { // bits description Uint16 CHPEN:1; // 0 PWM chopping enable Uint16 OSHTWTH:4; // 4:1 One-shot pulse width Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle Uint16 rsvd1:5; // 15:11 Reserved }; union PCCTL_REG { Uint16 all; struct PCCTL_BITS bit; }; struct HRCNFG_BITS { // bits description Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit Uint16 AUTOCONV:1; // 6 Autoconversion Bit Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits Uint16 rsvd1:1; // 13 Reserved Uint16 rsvd2:2; // 15:14 Reserved }; union HRCNFG_REG { Uint16 all; struct HRCNFG_BITS bit; }; struct HRPWR_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:4; // 9:6 Reserved Uint16 rsvd7:5; // 14:10 Reserved Uint16 CALPWRON:1; // 15 Calibration Power On }; union HRPWR_REG { Uint16 all; struct HRPWR_BITS bit; }; struct HRMSTEP_BITS { // bits description Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value Uint16 rsvd1:8; // 15:8 Reserved }; union HRMSTEP_REG { Uint16 all; struct HRMSTEP_BITS bit; }; struct HRCNFG2_BITS { // bits description Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits Uint16 rsvd1:8; // 13:6 Reserved Uint16 rsvd2:1; // 14 Reserved Uint16 rsvd3:1; // 15 Reserved }; union HRCNFG2_REG { Uint16 all; struct HRCNFG2_BITS bit; }; struct HRPCTL_BITS { // bits description Uint16 HRPE:1; // 0 High Resolution Period Enable Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: Uint16 rsvd2:9; // 15:7 Reserved }; union HRPCTL_REG { Uint16 all; struct HRPCTL_BITS bit; }; struct TRREM_BITS { // bits description Uint16 TRREM:11; // 10:0 Translator Remainder Bits Uint16 rsvd1:5; // 15:11 Reserved }; union TRREM_REG { Uint16 all; struct TRREM_BITS bit; }; struct GLDCTL_BITS { // bits description Uint16 GLD:1; // 0 Global Shadow to Active load event control Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit Uint16 rsvd1:1; // 6 Reserved Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register Uint16 rsvd2:3; // 15:13 Reserved }; union GLDCTL_REG { Uint16 all; struct GLDCTL_BITS bit; }; struct GLDCFG_BITS { // bits description Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR Uint16 CMPC:1; // 3 Global load event configuration for CMPC Uint16 CMPD:1; // 4 Global load event configuration for CMPD Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC Uint16 rsvd1:5; // 15:11 Reserved }; union GLDCFG_REG { Uint16 all; struct GLDCFG_BITS bit; }; struct EPWMXLINK_BITS { // bits description Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link Uint16 CMPCLINK:4; // 15:12 CMPC Link Uint16 CMPDLINK:4; // 19:16 CMPD Link Uint16 rsvd1:8; // 27:20 Reserved Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link }; union EPWMXLINK_REG { Uint32 all; struct EPWMXLINK_BITS bit; }; struct AQCTLA_BITS { // bits description Uint16 ZRO:2; // 1:0 Action Counter = Zero Uint16 PRD:2; // 3:2 Action Counter = Period Uint16 CAU:2; // 5:4 Action Counter = Compare A Up Uint16 CAD:2; // 7:6 Action Counter = Compare A Down Uint16 CBU:2; // 9:8 Action Counter = Compare B Up Uint16 CBD:2; // 11:10 Action Counter = Compare B Down Uint16 rsvd1:4; // 15:12 Reserved }; union AQCTLA_REG { Uint16 all; struct AQCTLA_BITS bit; }; struct AQCTLA2_BITS { // bits description Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count Uint16 rsvd1:8; // 15:8 Reserved }; union AQCTLA2_REG { Uint16 all; struct AQCTLA2_BITS bit; }; struct AQCTLB_BITS { // bits description Uint16 ZRO:2; // 1:0 Action Counter = Zero Uint16 PRD:2; // 3:2 Action Counter = Period Uint16 CAU:2; // 5:4 Action Counter = Compare A Up Uint16 CAD:2; // 7:6 Action Counter = Compare A Down Uint16 CBU:2; // 9:8 Action Counter = Compare B Up Uint16 CBD:2; // 11:10 Action Counter = Compare B Down Uint16 rsvd1:4; // 15:12 Reserved }; union AQCTLB_REG { Uint16 all; struct AQCTLB_BITS bit; }; struct AQCTLB2_BITS { // bits description Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count Uint16 rsvd1:8; // 15:8 Reserved }; union AQCTLB2_REG { Uint16 all; struct AQCTLB2_BITS bit; }; struct AQSFRC_BITS { // bits description Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked Uint16 OTSFA:1; // 2 One-time SW Force A Output Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked Uint16 OTSFB:1; // 5 One-time SW Force A Output Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options Uint16 rsvd1:8; // 15:8 Reserved }; union AQSFRC_REG { Uint16 all; struct AQSFRC_BITS bit; }; struct AQCSFRC_BITS { // bits description Uint16 CSFA:2; // 1:0 Continuous Software Force on output A Uint16 CSFB:2; // 3:2 Continuous Software Force on output B Uint16 rsvd1:12; // 15:4 Reserved }; union AQCSFRC_REG { Uint16 all; struct AQCSFRC_BITS bit; }; struct DBREDHR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:7; // 7:1 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits }; union DBREDHR_REG { Uint16 all; struct DBREDHR_BITS bit; }; struct DBRED_BITS { // bits description Uint16 DBRED:14; // 13:0 Rising edge delay value Uint16 rsvd1:2; // 15:14 Reserved }; union DBRED_REG { Uint16 all; struct DBRED_BITS bit; }; struct DBFEDHR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:7; // 7:1 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits }; union DBFEDHR_REG { Uint16 all; struct DBFEDHR_BITS bit; }; struct DBFED_BITS { // bits description Uint16 DBFED:14; // 13:0 Falling edge delay value Uint16 rsvd1:2; // 15:14 Reserved }; union DBFED_REG { Uint16 all; struct DBFED_BITS bit; }; struct TBPHS_BITS { // bits description Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) Uint16 TBPHS:16; // 31:16 Phase Offset Register }; union TBPHS_REG { Uint32 all; struct TBPHS_BITS bit; }; struct CMPA_BITS { // bits description Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register Uint16 CMPA:16; // 31:16 Compare A Register }; union CMPA_REG { Uint32 all; struct CMPA_BITS bit; }; struct CMPB_BITS { // bits description Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits Uint16 CMPB:16; // 31:16 Compare B Register }; union CMPB_REG { Uint32 all; struct CMPB_BITS bit; }; struct GLDCTL2_BITS { // bits description Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode Uint16 GFRCLD:1; // 1 Force reload event in one shot mode Uint16 rsvd1:14; // 15:2 Reserved }; union GLDCTL2_REG { Uint16 all; struct GLDCTL2_BITS bit; }; struct TZSEL_BITS { // bits description Uint16 CBC1:1; // 0 TZ1 CBC select Uint16 CBC2:1; // 1 TZ2 CBC select Uint16 CBC3:1; // 2 TZ3 CBC select Uint16 CBC4:1; // 3 TZ4 CBC select Uint16 CBC5:1; // 4 TZ5 CBC select Uint16 CBC6:1; // 5 TZ6 CBC select Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select Uint16 OSHT1:1; // 8 One-shot TZ1 select Uint16 OSHT2:1; // 9 One-shot TZ2 select Uint16 OSHT3:1; // 10 One-shot TZ3 select Uint16 OSHT4:1; // 11 One-shot TZ4 select Uint16 OSHT5:1; // 12 One-shot TZ5 select Uint16 OSHT6:1; // 13 One-shot TZ6 select Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select }; union TZSEL_REG { Uint16 all; struct TZSEL_BITS bit; }; struct TZDCSEL_BITS { // bits description Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 Uint16 rsvd1:4; // 15:12 Reserved }; union TZDCSEL_REG { Uint16 all; struct TZDCSEL_BITS bit; }; struct TZCTL_BITS { // bits description Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTL_REG { Uint16 all; struct TZCTL_BITS bit; }; struct TZCTL2_BITS { // bits description Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN Uint16 rsvd1:3; // 14:12 Reserved Uint16 ETZE:1; // 15 TZCTL2 Enable }; union TZCTL2_REG { Uint16 all; struct TZCTL2_BITS bit; }; struct TZCTLDCA_BITS { // bits description Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTLDCA_REG { Uint16 all; struct TZCTLDCA_BITS bit; }; struct TZCTLDCB_BITS { // bits description Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTLDCB_REG { Uint16 all; struct TZCTLDCB_BITS bit; }; struct TZEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable Uint16 OST:1; // 2 Trip Zones One Shot Int Enable Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable Uint16 rsvd2:9; // 15:7 Reserved }; union TZEINT_REG { Uint16 all; struct TZEINT_BITS bit; }; struct TZFLG_BITS { // bits description Uint16 INT:1; // 0 Global Int Status Flag Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag Uint16 OST:1; // 2 Trip Zones One Shot Flag Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag Uint16 rsvd1:9; // 15:7 Reserved }; union TZFLG_REG { Uint16 all; struct TZFLG_BITS bit; }; struct TZCBCFLG_BITS { // bits description Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 Uint16 rsvd1:8; // 15:8 Reserved }; union TZCBCFLG_REG { Uint16 all; struct TZCBCFLG_BITS bit; }; struct TZOSTFLG_BITS { // bits description Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 Uint16 rsvd1:8; // 15:8 Reserved }; union TZOSTFLG_REG { Uint16 all; struct TZOSTFLG_BITS bit; }; struct TZCLR_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt Clear Flag Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear Uint16 OST:1; // 2 One-Shot Flag Clear Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear Uint16 rsvd1:7; // 13:7 Reserved Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch }; union TZCLR_REG { Uint16 all; struct TZCLR_BITS bit; }; struct TZCBCCLR_BITS { // bits description Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC Uint16 rsvd1:8; // 15:8 Reserved }; union TZCBCCLR_REG { Uint16 all; struct TZCBCCLR_BITS bit; }; struct TZOSTCLR_BITS { // bits description Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST Uint16 rsvd1:8; // 15:8 Reserved }; union TZOSTCLR_REG { Uint16 all; struct TZOSTCLR_BITS bit; }; struct TZFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event Uint16 OST:1; // 2 Force Trip Zones One Shot Event Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 Uint16 rsvd2:9; // 15:7 Reserved }; union TZFRC_REG { Uint16 all; struct TZFRC_BITS bit; }; struct ETSEL_BITS { // bits description Uint16 INTSEL:3; // 2:0 EPWMxINTn Select Uint16 INTEN:1; // 3 EPWMxINTn Enable Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select Uint16 rsvd1:1; // 7 Reserved Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select Uint16 SOCAEN:1; // 11 Start of Conversion A Enable Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select Uint16 SOCBEN:1; // 15 Start of Conversion B Enable }; union ETSEL_REG { Uint16 all; struct ETSEL_BITS bit; }; struct ETPS_BITS { // bits description Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits Uint16 rsvd1:2; // 7:6 Reserved Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter }; union ETPS_REG { Uint16 all; struct ETPS_BITS bit; }; struct ETFLG_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Flag Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Flag Uint16 SOCB:1; // 3 EPWMxSOCB Flag Uint16 rsvd2:12; // 15:4 Reserved }; union ETFLG_REG { Uint16 all; struct ETFLG_BITS bit; }; struct ETCLR_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Clear Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Clear Uint16 SOCB:1; // 3 EPWMxSOCB Clear Uint16 rsvd2:12; // 15:4 Reserved }; union ETCLR_REG { Uint16 all; struct ETCLR_BITS bit; }; struct ETFRC_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Force Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Force Uint16 SOCB:1; // 3 EPWMxSOCB Force Uint16 rsvd2:12; // 15:4 Reserved }; union ETFRC_REG { Uint16 all; struct ETFRC_BITS bit; }; struct ETINTPS_BITS { // bits description Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register Uint16 rsvd1:8; // 15:8 Reserved }; union ETINTPS_REG { Uint16 all; struct ETINTPS_BITS bit; }; struct ETSOCPS_BITS { // bits description Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register }; union ETSOCPS_REG { Uint16 all; struct ETSOCPS_BITS bit; }; struct ETCNTINITCTL_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable }; union ETCNTINITCTL_REG { Uint16 all; struct ETCNTINITCTL_BITS bit; }; struct ETCNTINIT_BITS { // bits description Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits Uint16 rsvd1:4; // 15:12 Reserved }; union ETCNTINIT_REG { Uint16 all; struct ETCNTINIT_BITS bit; }; struct DCTRIPSEL_BITS { // bits description Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select }; union DCTRIPSEL_REG { Uint16 all; struct DCTRIPSEL_BITS bit; }; struct DCACTL_BITS { // bits description Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable Uint16 rsvd1:4; // 7:4 Reserved Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal Uint16 rsvd2:6; // 15:10 Reserved }; union DCACTL_REG { Uint16 all; struct DCACTL_BITS bit; }; struct DCBCTL_BITS { // bits description Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable Uint16 rsvd1:4; // 7:4 Reserved Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal Uint16 rsvd2:6; // 15:10 Reserved }; union DCBCTL_REG { Uint16 all; struct DCBCTL_BITS bit; }; struct DCFCTL_BITS { // bits description Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select Uint16 BLANKE:1; // 2 Blanking Enable/Disable Uint16 BLANKINV:1; // 3 Blanking Window Inversion Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment Uint16 rsvd1:1; // 6 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:2; // 9:8 Reserved Uint16 rsvd4:3; // 12:10 Reserved Uint16 rsvd5:3; // 15:13 Reserved }; union DCFCTL_REG { Uint16 all; struct DCFCTL_BITS bit; }; struct DCCAPCTL_BITS { // bits description Uint16 CAPE:1; // 0 Counter Capture Enable Uint16 SHDWMODE:1; // 1 Counter Capture Mode Uint16 rsvd1:11; // 12:2 Reserved Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag Uint16 CAPMODE:1; // 15 Counter Capture Mode }; union DCCAPCTL_REG { Uint16 all; struct DCCAPCTL_BITS bit; }; struct DCAHTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux Uint16 rsvd2:1; // 15 Reserved }; union DCAHTRIPSEL_REG { Uint16 all; struct DCAHTRIPSEL_BITS bit; }; struct DCALTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux Uint16 rsvd2:1; // 15 Reserved }; union DCALTRIPSEL_REG { Uint16 all; struct DCALTRIPSEL_BITS bit; }; struct DCBHTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux Uint16 rsvd2:1; // 15 Reserved }; union DCBHTRIPSEL_REG { Uint16 all; struct DCBHTRIPSEL_BITS bit; }; struct DCBLTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux Uint16 rsvd2:1; // 15 Reserved }; union DCBLTRIPSEL_REG { Uint16 all; struct DCBLTRIPSEL_BITS bit; }; struct EPWM_REGS { union TBCTL_REG TBCTL; // Time Base Control Register union TBCTL2_REG TBCTL2; // Time Base Control Register 2 Uint16 rsvd1[2]; // Reserved Uint16 TBCTR; // Time Base Counter Register union TBSTS_REG TBSTS; // Time Base Status Register Uint16 rsvd2[2]; // Reserved union CMPCTL_REG CMPCTL; // Counter Compare Control Register union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 Uint16 rsvd3[2]; // Reserved union DBCTL_REG DBCTL; // Dead-Band Generator Control Register union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 Uint16 rsvd4[2]; // Reserved union AQCTL_REG AQCTL; // Action Qualifier Control Register union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register Uint16 rsvd5[2]; // Reserved union PCCTL_REG PCCTL; // PWM Chopper Control Register Uint16 rsvd6[11]; // Reserved union HRCNFG_REG HRCNFG; // HRPWM Configuration Register union HRPWR_REG HRPWR; // HRPWM Power Register Uint16 rsvd7[4]; // Reserved union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register Uint16 rsvd8[5]; // Reserved union HRPCTL_REG HRPCTL; // High Resolution Period Control Register union TRREM_REG TRREM; // Translator High Resolution Remainder Register Uint16 rsvd9[5]; // Reserved union GLDCTL_REG GLDCTL; // Global PWM Load Control Register union GLDCFG_REG GLDCFG; // Global PWM Load Config Register Uint16 rsvd10[2]; // Reserved union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register Uint16 rsvd11[6]; // Reserved union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B Uint16 rsvd12[3]; // Reserved union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register Uint16 rsvd13; // Reserved union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register Uint16 rsvd14[6]; // Reserved union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register Uint16 rsvd15[12]; // Reserved union TBPHS_REG TBPHS; // Time Base Phase High Uint16 TBPRDHR; // Time Base Period High Resolution Register Uint16 TBPRD; // Time Base Period Register Uint16 rsvd16[6]; // Reserved union CMPA_REG CMPA; // Counter Compare A Register union CMPB_REG CMPB; // Compare B Register Uint16 rsvd17; // Reserved Uint16 CMPC; // Counter Compare C Register Uint16 rsvd18; // Reserved Uint16 CMPD; // Counter Compare D Register Uint16 rsvd19[2]; // Reserved union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 Uint16 rsvd20[11]; // Reserved union TZSEL_REG TZSEL; // Trip Zone Select Register Uint16 rsvd21; // Reserved union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register Uint16 rsvd22; // Reserved union TZCTL_REG TZCTL; // Trip Zone Control Register union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B Uint16 rsvd23[5]; // Reserved union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register Uint16 rsvd24[5]; // Reserved union TZFLG_REG TZFLG; // Trip Zone Flag Register union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register Uint16 rsvd25; // Reserved union TZCLR_REG TZCLR; // Trip Zone Clear Register union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register Uint16 rsvd26; // Reserved union TZFRC_REG TZFRC; // Trip Zone Force Register Uint16 rsvd27[8]; // Reserved union ETSEL_REG ETSEL; // Event Trigger Selection Register Uint16 rsvd28; // Reserved union ETPS_REG ETPS; // Event Trigger Pre-Scale Register Uint16 rsvd29; // Reserved union ETFLG_REG ETFLG; // Event Trigger Flag Register Uint16 rsvd30; // Reserved union ETCLR_REG ETCLR; // Event Trigger Clear Register Uint16 rsvd31; // Reserved union ETFRC_REG ETFRC; // Event Trigger Force Register Uint16 rsvd32; // Reserved union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register Uint16 rsvd33; // Reserved union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register Uint16 rsvd34; // Reserved union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register Uint16 rsvd35; // Reserved union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register Uint16 rsvd36[11]; // Reserved union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register Uint16 rsvd37[2]; // Reserved union DCACTL_REG DCACTL; // Digital Compare A Control Register union DCBCTL_REG DCBCTL; // Digital Compare B Control Register Uint16 rsvd38[2]; // Reserved union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register Uint16 DCFOFFSET; // Digital Compare Filter Offset Register Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register Uint16 DCFWINDOW; // Digital Compare Filter Window Register Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register Uint16 rsvd39[2]; // Reserved Uint16 DCCAP; // Digital Compare Counter Capture Register Uint16 rsvd40[2]; // Reserved union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select Uint16 rsvd41[42]; // Reserved }; //--------------------------------------------------------------------------- // EPWM External References & Function Declarations: // extern volatile struct EPWM_REGS EPwm1Regs; extern volatile struct EPWM_REGS EPwm2Regs; extern volatile struct EPWM_REGS EPwm3Regs; extern volatile struct EPWM_REGS EPwm4Regs; extern volatile struct EPWM_REGS EPwm5Regs; extern volatile struct EPWM_REGS EPwm6Regs; extern volatile struct EPWM_REGS EPwm7Regs; extern volatile struct EPWM_REGS EPwm8Regs; extern volatile struct EPWM_REGS EPwm9Regs; extern volatile struct EPWM_REGS EPwm10Regs; extern volatile struct EPWM_REGS EPwm11Regs; extern volatile struct EPWM_REGS EPwm12Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_epwm_xbar.h // // TITLE: F2837xD Device EPWM_XBAR Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // EPWM_XBAR Individual Register Bit Definitions: struct TRIP4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR }; union TRIP4MUX0TO15CFG_REG { Uint32 all; struct TRIP4MUX0TO15CFG_BITS bit; }; struct TRIP4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR }; union TRIP4MUX16TO31CFG_REG { Uint32 all; struct TRIP4MUX16TO31CFG_BITS bit; }; struct TRIP5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR }; union TRIP5MUX0TO15CFG_REG { Uint32 all; struct TRIP5MUX0TO15CFG_BITS bit; }; struct TRIP5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR }; union TRIP5MUX16TO31CFG_REG { Uint32 all; struct TRIP5MUX16TO31CFG_BITS bit; }; struct TRIP7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR }; union TRIP7MUX0TO15CFG_REG { Uint32 all; struct TRIP7MUX0TO15CFG_BITS bit; }; struct TRIP7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR }; union TRIP7MUX16TO31CFG_REG { Uint32 all; struct TRIP7MUX16TO31CFG_BITS bit; }; struct TRIP8MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR }; union TRIP8MUX0TO15CFG_REG { Uint32 all; struct TRIP8MUX0TO15CFG_BITS bit; }; struct TRIP8MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR }; union TRIP8MUX16TO31CFG_REG { Uint32 all; struct TRIP8MUX16TO31CFG_BITS bit; }; struct TRIP9MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR }; union TRIP9MUX0TO15CFG_REG { Uint32 all; struct TRIP9MUX0TO15CFG_BITS bit; }; struct TRIP9MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR }; union TRIP9MUX16TO31CFG_REG { Uint32 all; struct TRIP9MUX16TO31CFG_BITS bit; }; struct TRIP10MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR }; union TRIP10MUX0TO15CFG_REG { Uint32 all; struct TRIP10MUX0TO15CFG_BITS bit; }; struct TRIP10MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR }; union TRIP10MUX16TO31CFG_REG { Uint32 all; struct TRIP10MUX16TO31CFG_BITS bit; }; struct TRIP11MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR }; union TRIP11MUX0TO15CFG_REG { Uint32 all; struct TRIP11MUX0TO15CFG_BITS bit; }; struct TRIP11MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR }; union TRIP11MUX16TO31CFG_REG { Uint32 all; struct TRIP11MUX16TO31CFG_BITS bit; }; struct TRIP12MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR }; union TRIP12MUX0TO15CFG_REG { Uint32 all; struct TRIP12MUX0TO15CFG_BITS bit; }; struct TRIP12MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR }; union TRIP12MUX16TO31CFG_REG { Uint32 all; struct TRIP12MUX16TO31CFG_BITS bit; }; struct TRIP4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR }; union TRIP4MUXENABLE_REG { Uint32 all; struct TRIP4MUXENABLE_BITS bit; }; struct TRIP5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR }; union TRIP5MUXENABLE_REG { Uint32 all; struct TRIP5MUXENABLE_BITS bit; }; struct TRIP7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR }; union TRIP7MUXENABLE_REG { Uint32 all; struct TRIP7MUXENABLE_BITS bit; }; struct TRIP8MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR }; union TRIP8MUXENABLE_REG { Uint32 all; struct TRIP8MUXENABLE_BITS bit; }; struct TRIP9MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR }; union TRIP9MUXENABLE_REG { Uint32 all; struct TRIP9MUXENABLE_BITS bit; }; struct TRIP10MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR }; union TRIP10MUXENABLE_REG { Uint32 all; struct TRIP10MUXENABLE_BITS bit; }; struct TRIP11MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR }; union TRIP11MUXENABLE_REG { Uint32 all; struct TRIP11MUXENABLE_BITS bit; }; struct TRIP12MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR }; union TRIP12MUXENABLE_REG { Uint32 all; struct TRIP12MUXENABLE_BITS bit; }; struct TRIPOUTINV_BITS { // bits description Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union TRIPOUTINV_REG { Uint32 all; struct TRIPOUTINV_BITS bit; }; struct TRIPLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write protection KEY }; union TRIPLOCK_REG { Uint32 all; struct TRIPLOCK_BITS bit; }; struct EPWM_XBAR_REGS { union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 Uint16 rsvd1[8]; // Reserved union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register Uint16 rsvd2[4]; // Reserved union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register }; //--------------------------------------------------------------------------- // EPWM_XBAR External References & Function Declarations: // extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_eqep.h // // TITLE: F2837xD Device EQEP Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // EQEP Individual Register Bit Definitions: struct QDECCTL_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 QSP:1; // 5 QEPS input polarity Uint16 QIP:1; // 6 QEPI input polarity Uint16 QBP:1; // 7 QEPB input polarity Uint16 QAP:1; // 8 QEPA input polarity Uint16 IGATE:1; // 9 Index pulse gating option Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter Uint16 XCR:1; // 11 External Clock Rate Uint16 SPSEL:1; // 12 Sync output pin selection Uint16 SOEN:1; // 13 Sync output-enable Uint16 QSRC:2; // 15:14 Position-counter source selection }; union QDECCTL_REG { Uint16 all; struct QDECCTL_BITS bit; }; struct QEPCTL_BITS { // bits description Uint16 WDE:1; // 0 QEP watchdog enable Uint16 UTE:1; // 1 QEP unit timer enable Uint16 QCLM:1; // 2 QEP capture latch mode Uint16 QPEN:1; // 3 Quadrature postotion counter enable Uint16 IEL:2; // 5:4 Index event latch Uint16 SEL:1; // 6 Strobe event latch Uint16 SWI:1; // 7 Software init position counter Uint16 IEI:2; // 9:8 Index event init of position count Uint16 SEI:2; // 11:10 Strobe event init Uint16 PCRM:2; // 13:12 Postion counter reset Uint16 FREE_SOFT:2; // 15:14 Emulation mode }; union QEPCTL_REG { Uint16 all; struct QEPCTL_BITS bit; }; struct QCAPCTL_BITS { // bits description Uint16 UPPS:4; // 3:0 Unit position event prescaler Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler Uint16 rsvd1:8; // 14:7 Reserved Uint16 CEN:1; // 15 Enable eQEP capture }; union QCAPCTL_REG { Uint16 all; struct QCAPCTL_BITS bit; }; struct QPOSCTL_BITS { // bits description Uint16 PCSPW:12; // 11:0 Position compare sync pulse width Uint16 PCE:1; // 12 Position compare enable/disable Uint16 PCPOL:1; // 13 Polarity of sync output Uint16 PCLOAD:1; // 14 Position compare of shadow load Uint16 PCSHDW:1; // 15 Position compare of shadow enable }; union QPOSCTL_REG { Uint16 all; struct QPOSCTL_BITS bit; }; struct QEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PCE:1; // 1 Position counter error interrupt enable Uint16 QPE:1; // 2 Quadrature phase error interrupt enable Uint16 QDC:1; // 3 Quadrature direction change interrupt enable Uint16 WTO:1; // 4 Watchdog time out interrupt enable Uint16 PCU:1; // 5 Position counter underflow interrupt enable Uint16 PCO:1; // 6 Position counter overflow interrupt enable Uint16 PCR:1; // 7 Position-compare ready interrupt enable Uint16 PCM:1; // 8 Position-compare match interrupt enable Uint16 SEL:1; // 9 Strobe event latch interrupt enable Uint16 IEL:1; // 10 Index event latch interrupt enable Uint16 UTO:1; // 11 Unit time out interrupt enable Uint16 rsvd2:4; // 15:12 Reserved }; union QEINT_REG { Uint16 all; struct QEINT_BITS bit; }; struct QFLG_BITS { // bits description Uint16 INT:1; // 0 Global interrupt status flag Uint16 PCE:1; // 1 Position counter error interrupt flag Uint16 PHE:1; // 2 Quadrature phase error interrupt flag Uint16 QDC:1; // 3 Quadrature direction change interrupt flag Uint16 WTO:1; // 4 Watchdog timeout interrupt flag Uint16 PCU:1; // 5 Position counter underflow interrupt flag Uint16 PCO:1; // 6 Position counter overflow interrupt flag Uint16 PCR:1; // 7 Position-compare ready interrupt flag Uint16 PCM:1; // 8 eQEP compare match event interrupt flag Uint16 SEL:1; // 9 Strobe event latch interrupt flag Uint16 IEL:1; // 10 Index event latch interrupt flag Uint16 UTO:1; // 11 Unit time out interrupt flag Uint16 rsvd1:4; // 15:12 Reserved }; union QFLG_REG { Uint16 all; struct QFLG_BITS bit; }; struct QCLR_BITS { // bits description Uint16 INT:1; // 0 Global interrupt clear flag Uint16 PCE:1; // 1 Clear position counter error interrupt flag Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag Uint16 IEL:1; // 10 Clear index event latch interrupt flag Uint16 UTO:1; // 11 Clear unit time out interrupt flag Uint16 rsvd1:4; // 15:12 Reserved }; union QCLR_REG { Uint16 all; struct QCLR_BITS bit; }; struct QFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PCE:1; // 1 Force position counter error interrupt Uint16 PHE:1; // 2 Force quadrature phase error interrupt Uint16 QDC:1; // 3 Force quadrature direction change interrupt Uint16 WTO:1; // 4 Force watchdog time out interrupt Uint16 PCU:1; // 5 Force position counter underflow interrupt Uint16 PCO:1; // 6 Force position counter overflow interrupt Uint16 PCR:1; // 7 Force position-compare ready interrupt Uint16 PCM:1; // 8 Force position-compare match interrupt Uint16 SEL:1; // 9 Force strobe event latch interrupt Uint16 IEL:1; // 10 Force index event latch interrupt Uint16 UTO:1; // 11 Force unit time out interrupt Uint16 rsvd2:4; // 15:12 Reserved }; union QFRC_REG { Uint16 all; struct QFRC_BITS bit; }; struct QEPSTS_BITS { // bits description Uint16 PCEF:1; // 0 Position counter error flag. Uint16 FIMF:1; // 1 First index marker flag Uint16 CDEF:1; // 2 Capture direction error flag Uint16 COEF:1; // 3 Capture overflow error flag Uint16 QDLF:1; // 4 eQEP direction latch flag Uint16 QDF:1; // 5 Quadrature direction flag Uint16 FIDF:1; // 6 The first index marker Uint16 UPEVNT:1; // 7 Unit position event flag Uint16 rsvd1:8; // 15:8 Reserved }; union QEPSTS_REG { Uint16 all; struct QEPSTS_BITS bit; }; struct EQEP_REGS { Uint32 QPOSCNT; // Position Counter Uint32 QPOSINIT; // Position Counter Init Uint32 QPOSMAX; // Maximum Position Count Uint32 QPOSCMP; // Position Compare Uint32 QPOSILAT; // Index Position Latch Uint32 QPOSSLAT; // Strobe Position Latch Uint32 QPOSLAT; // Position Latch Uint32 QUTMR; // QEP Unit Timer Uint32 QUPRD; // QEP Unit Period Uint16 QWDTMR; // QEP Watchdog Timer Uint16 QWDPRD; // QEP Watchdog Period union QDECCTL_REG QDECCTL; // Quadrature Decoder Control union QEPCTL_REG QEPCTL; // QEP Control union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control union QPOSCTL_REG QPOSCTL; // Position Compare Control union QEINT_REG QEINT; // QEP Interrupt Control union QFLG_REG QFLG; // QEP Interrupt Flag union QCLR_REG QCLR; // QEP Interrupt Clear union QFRC_REG QFRC; // QEP Interrupt Force union QEPSTS_REG QEPSTS; // QEP Status Uint16 QCTMR; // QEP Capture Timer Uint16 QCPRD; // QEP Capture Period Uint16 QCTMRLAT; // QEP Capture Latch Uint16 QCPRDLAT; // QEP Capture Period Latch Uint16 rsvd1; // Reserved }; //--------------------------------------------------------------------------- // EQEP External References & Function Declarations: // extern volatile struct EQEP_REGS EQep1Regs; extern volatile struct EQEP_REGS EQep2Regs; extern volatile struct EQEP_REGS EQep3Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_flash.h // // TITLE: F2837xD Device FLASH Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // FLASH Individual Register Bit Definitions: struct FRDCNTL_BITS { // bits description Uint16 rsvd1:8; // 7:0 Reserved Uint16 RWAIT:4; // 11:8 Random Read Waitstate Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union FRDCNTL_REG { Uint32 all; struct FRDCNTL_BITS bit; }; struct FBAC_BITS { // bits description Uint16 VREADST:8; // 7:0 VREAD Setup Time Count Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FBAC_REG { Uint32 all; struct FBAC_BITS bit; }; struct FBFALLBACK_BITS { // bits description Uint16 BNKPWR0:2; // 1:0 Bank Power Mode Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FBFALLBACK_REG { Uint32 all; struct FBFALLBACK_BITS bit; }; struct FBPRDY_BITS { // bits description Uint16 BANKRDY:1; // 0 Flash Bank Active Power State Uint16 rsvd1:14; // 14:1 Reserved Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode Uint16 rsvd2:16; // 31:16 Reserved }; union FBPRDY_REG { Uint32 all; struct FBPRDY_BITS bit; }; struct FPAC1_BITS { // bits description Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode Uint16 rsvd1:15; // 15:1 Reserved Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count Uint16 rsvd2:4; // 31:28 Reserved }; union FPAC1_REG { Uint32 all; struct FPAC1_BITS bit; }; struct FMSTAT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status Uint16 CSTAT:1; // 4 Command Fail Status Uint16 INVDAT:1; // 5 Invalid Data Uint16 PGM:1; // 6 Program Operation Status Uint16 ERS:1; // 7 Erase Operation Status Uint16 BUSY:1; // 8 Busy Bit Uint16 rsvd4:1; // 9 Reserved Uint16 EV:1; // 10 Erase Verify Status Uint16 rsvd5:1; // 11 Reserved Uint16 PGV:1; // 12 Programming Verify Status Uint16 rsvd6:1; // 13 Reserved Uint16 ILA:1; // 14 Illegal Address Detected Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:14; // 31:18 Reserved }; union FMSTAT_REG { Uint32 all; struct FMSTAT_BITS bit; }; struct FRD_INTF_CTRL_BITS { // bits description Uint16 PREFETCH_EN:1; // 0 Prefetch Enable Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FRD_INTF_CTRL_REG { Uint32 all; struct FRD_INTF_CTRL_BITS bit; }; struct FLASH_CTRL_REGS { union FRDCNTL_REG FRDCNTL; // Flash Read Control Register Uint16 rsvd1[28]; // Reserved union FBAC_REG FBAC; // Flash Bank Access Control Register union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 Uint16 rsvd2[4]; // Reserved union FMSTAT_REG FMSTAT; // Flash Module Status Register Uint16 rsvd3[340]; // Reserved union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register }; struct ECC_ENABLE_BITS { // bits description Uint16 ENABLE:4; // 3:0 Enable ECC Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECC_ENABLE_REG { Uint32 all; struct ECC_ENABLE_BITS bit; }; struct ERR_STATUS_BITS { // bits description Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred Uint16 rsvd1:13; // 15:3 Reserved Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred Uint16 rsvd2:13; // 31:19 Reserved }; union ERR_STATUS_REG { Uint32 all; struct ERR_STATUS_BITS bit; }; struct ERR_POS_BITS { // bits description Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits Uint16 rsvd1:2; // 7:6 Reserved Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits Uint16 rsvd2:7; // 15:9 Reserved Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits Uint16 rsvd3:2; // 23:22 Reserved Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits Uint16 rsvd4:7; // 31:25 Reserved }; union ERR_POS_REG { Uint32 all; struct ERR_POS_BITS bit; }; struct ERR_STATUS_CLR_BITS { // bits description Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear Uint16 rsvd1:13; // 15:3 Reserved Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear Uint16 rsvd2:13; // 31:19 Reserved }; union ERR_STATUS_CLR_REG { Uint32 all; struct ERR_STATUS_CLR_BITS bit; }; struct ERR_CNT_BITS { // bits description Uint16 ERR_CNT:16; // 15:0 Error counter Uint16 rsvd1:16; // 31:16 Reserved }; union ERR_CNT_REG { Uint32 all; struct ERR_CNT_BITS bit; }; struct ERR_THRESHOLD_BITS { // bits description Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold Uint16 rsvd1:16; // 31:16 Reserved }; union ERR_THRESHOLD_REG { Uint32 all; struct ERR_THRESHOLD_BITS bit; }; struct ERR_INTFLG_BITS { // bits description Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ERR_INTFLG_REG { Uint32 all; struct ERR_INTFLG_BITS bit; }; struct ERR_INTCLR_BITS { // bits description Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ERR_INTCLR_REG { Uint32 all; struct ERR_INTCLR_BITS bit; }; struct FADDR_TEST_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ADDRL:13; // 15:3 ECC Address Low Uint16 ADDRH:6; // 21:16 ECC Address High Uint16 rsvd2:10; // 31:22 Reserved }; union FADDR_TEST_REG { Uint32 all; struct FADDR_TEST_BITS bit; }; struct FECC_TEST_BITS { // bits description Uint16 ECC:8; // 7:0 ECC Control Bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_TEST_REG { Uint32 all; struct FECC_TEST_BITS bit; }; struct FECC_CTRL_BITS { // bits description Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic Uint16 ECC_SELECT:1; // 1 ECC Bit Select Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_CTRL_REG { Uint32 all; struct FECC_CTRL_BITS bit; }; struct FECC_STATUS_BITS { // bits description Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error Uint16 rsvd1:7; // 15:9 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_STATUS_REG { Uint32 all; struct FECC_STATUS_BITS bit; }; struct FLASH_ECC_REGS { union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High union ERR_STATUS_REG ERR_STATUS; // Error Status union ERR_POS_REG ERR_POS; // Error Position union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear union ERR_CNT_REG ERR_CNT; // Error Control union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear Uint32 FDATAH_TEST; // Data High Test Uint32 FDATAL_TEST; // Data Low Test union FADDR_TEST_REG FADDR_TEST; // ECC Test Address union FECC_TEST_REG FECC_TEST; // ECC Test Address union FECC_CTRL_REG FECC_CTRL; // ECC Control Uint32 FOUTH_TEST; // Test Data Out High Uint32 FOUTL_TEST; // Test Data Out Low union FECC_STATUS_REG FECC_STATUS; // ECC Status }; struct PUMPREQUEST_BITS { // bits description Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2 Uint16 rsvd1:14; // 15:2 Reserved Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register }; union PUMPREQUEST_REG { Uint32 all; struct PUMPREQUEST_BITS bit; }; struct FLASH_PUMP_SEMAPHORE_REGS { union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register }; //--------------------------------------------------------------------------- // FLASH External References & Function Declarations: // extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; extern volatile struct FLASH_ECC_REGS Flash0EccRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_gpio.h // // TITLE: F2837xD Device GPIO Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // GPIO Individual Register Bit Definitions: struct GPACTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 }; union GPACTRL_REG { Uint32 all; struct GPACTRL_BITS bit; }; struct GPAQSEL1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 }; union GPAQSEL1_REG { Uint32 all; struct GPAQSEL1_BITS bit; }; struct GPAQSEL2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 }; union GPAQSEL2_REG { Uint32 all; struct GPAQSEL2_BITS bit; }; struct GPAMUX1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 }; union GPAMUX1_REG { Uint32 all; struct GPAMUX1_BITS bit; }; struct GPAMUX2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 }; union GPAMUX2_REG { Uint32 all; struct GPAMUX2_BITS bit; }; struct GPADIR_BITS { // bits description Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode }; union GPADIR_REG { Uint32 all; struct GPADIR_BITS bit; }; struct GPAPUD_BITS { // bits description Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin }; union GPAPUD_REG { Uint32 all; struct GPAPUD_BITS bit; }; struct GPAINV_BITS { // bits description Uint16 GPIO0:1; // 0 Input inversion control for this pin Uint16 GPIO1:1; // 1 Input inversion control for this pin Uint16 GPIO2:1; // 2 Input inversion control for this pin Uint16 GPIO3:1; // 3 Input inversion control for this pin Uint16 GPIO4:1; // 4 Input inversion control for this pin Uint16 GPIO5:1; // 5 Input inversion control for this pin Uint16 GPIO6:1; // 6 Input inversion control for this pin Uint16 GPIO7:1; // 7 Input inversion control for this pin Uint16 GPIO8:1; // 8 Input inversion control for this pin Uint16 GPIO9:1; // 9 Input inversion control for this pin Uint16 GPIO10:1; // 10 Input inversion control for this pin Uint16 GPIO11:1; // 11 Input inversion control for this pin Uint16 GPIO12:1; // 12 Input inversion control for this pin Uint16 GPIO13:1; // 13 Input inversion control for this pin Uint16 GPIO14:1; // 14 Input inversion control for this pin Uint16 GPIO15:1; // 15 Input inversion control for this pin Uint16 GPIO16:1; // 16 Input inversion control for this pin Uint16 GPIO17:1; // 17 Input inversion control for this pin Uint16 GPIO18:1; // 18 Input inversion control for this pin Uint16 GPIO19:1; // 19 Input inversion control for this pin Uint16 GPIO20:1; // 20 Input inversion control for this pin Uint16 GPIO21:1; // 21 Input inversion control for this pin Uint16 GPIO22:1; // 22 Input inversion control for this pin Uint16 GPIO23:1; // 23 Input inversion control for this pin Uint16 GPIO24:1; // 24 Input inversion control for this pin Uint16 GPIO25:1; // 25 Input inversion control for this pin Uint16 GPIO26:1; // 26 Input inversion control for this pin Uint16 GPIO27:1; // 27 Input inversion control for this pin Uint16 GPIO28:1; // 28 Input inversion control for this pin Uint16 GPIO29:1; // 29 Input inversion control for this pin Uint16 GPIO30:1; // 30 Input inversion control for this pin Uint16 GPIO31:1; // 31 Input inversion control for this pin }; union GPAINV_REG { Uint32 all; struct GPAINV_BITS bit; }; struct GPAODR_BITS { // bits description Uint16 GPIO0:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO1:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO2:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO3:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO4:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO5:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO6:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO7:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO8:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO9:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO10:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO11:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO12:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO13:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO14:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO15:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO16:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO17:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO18:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO19:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO20:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO21:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO22:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO23:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO24:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO25:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO26:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO27:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO28:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO29:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO30:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO31:1; // 31 Outpout Open-Drain control for this pin }; union GPAODR_REG { Uint32 all; struct GPAODR_BITS bit; }; struct GPAGMUX1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 }; union GPAGMUX1_REG { Uint32 all; struct GPAGMUX1_BITS bit; }; struct GPAGMUX2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 }; union GPAGMUX2_REG { Uint32 all; struct GPAGMUX2_BITS bit; }; struct GPACSEL1_BITS { // bits description Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select }; union GPACSEL1_REG { Uint32 all; struct GPACSEL1_BITS bit; }; struct GPACSEL2_BITS { // bits description Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select }; union GPACSEL2_REG { Uint32 all; struct GPACSEL2_BITS bit; }; struct GPACSEL3_BITS { // bits description Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select }; union GPACSEL3_REG { Uint32 all; struct GPACSEL3_BITS bit; }; struct GPACSEL4_BITS { // bits description Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select }; union GPACSEL4_REG { Uint32 all; struct GPACSEL4_BITS bit; }; struct GPALOCK_BITS { // bits description Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin }; union GPALOCK_REG { Uint32 all; struct GPALOCK_BITS bit; }; struct GPACR_BITS { // bits description Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin }; union GPACR_REG { Uint32 all; struct GPACR_BITS bit; }; struct GPBCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 }; union GPBCTRL_REG { Uint32 all; struct GPBCTRL_BITS bit; }; struct GPBQSEL1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 Uint16 GPIO36:2; // 9:8 Select input qualification type for GPIO36 Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 Uint16 GPIO38:2; // 13:12 Select input qualification type for GPIO38 Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 }; union GPBQSEL1_REG { Uint32 all; struct GPBQSEL1_BITS bit; }; struct GPBQSEL2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 Uint16 GPIO60:2; // 25:24 Select input qualification type for GPIO60 Uint16 GPIO61:2; // 27:26 Select input qualification type for GPIO61 Uint16 GPIO62:2; // 29:28 Select input qualification type for GPIO62 Uint16 GPIO63:2; // 31:30 Select input qualification type for GPIO63 }; union GPBQSEL2_REG { Uint32 all; struct GPBQSEL2_BITS bit; }; struct GPBMUX1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 }; union GPBMUX1_REG { Uint32 all; struct GPBMUX1_BITS bit; }; struct GPBMUX2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 }; union GPBMUX2_REG { Uint32 all; struct GPBMUX2_BITS bit; }; struct GPBDIR_BITS { // bits description Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO36:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO38:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO60:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO61:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO62:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO63:1; // 31 Defines direction for this pin in GPIO mode }; union GPBDIR_REG { Uint32 all; struct GPBDIR_BITS bit; }; struct GPBPUD_BITS { // bits description Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO36:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO38:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO60:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO61:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO62:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO63:1; // 31 Pull-Up Disable control for this pin }; union GPBPUD_REG { Uint32 all; struct GPBPUD_BITS bit; }; struct GPBINV_BITS { // bits description Uint16 GPIO32:1; // 0 Input inversion control for this pin Uint16 GPIO33:1; // 1 Input inversion control for this pin Uint16 GPIO34:1; // 2 Input inversion control for this pin Uint16 GPIO35:1; // 3 Input inversion control for this pin Uint16 GPIO36:1; // 4 Input inversion control for this pin Uint16 GPIO37:1; // 5 Input inversion control for this pin Uint16 GPIO38:1; // 6 Input inversion control for this pin Uint16 GPIO39:1; // 7 Input inversion control for this pin Uint16 GPIO40:1; // 8 Input inversion control for this pin Uint16 GPIO41:1; // 9 Input inversion control for this pin Uint16 GPIO42:1; // 10 Input inversion control for this pin Uint16 GPIO43:1; // 11 Input inversion control for this pin Uint16 GPIO44:1; // 12 Input inversion control for this pin Uint16 GPIO45:1; // 13 Input inversion control for this pin Uint16 GPIO46:1; // 14 Input inversion control for this pin Uint16 GPIO47:1; // 15 Input inversion control for this pin Uint16 GPIO48:1; // 16 Input inversion control for this pin Uint16 GPIO49:1; // 17 Input inversion control for this pin Uint16 GPIO50:1; // 18 Input inversion control for this pin Uint16 GPIO51:1; // 19 Input inversion control for this pin Uint16 GPIO52:1; // 20 Input inversion control for this pin Uint16 GPIO53:1; // 21 Input inversion control for this pin Uint16 GPIO54:1; // 22 Input inversion control for this pin Uint16 GPIO55:1; // 23 Input inversion control for this pin Uint16 GPIO56:1; // 24 Input inversion control for this pin Uint16 GPIO57:1; // 25 Input inversion control for this pin Uint16 GPIO58:1; // 26 Input inversion control for this pin Uint16 GPIO59:1; // 27 Input inversion control for this pin Uint16 GPIO60:1; // 28 Input inversion control for this pin Uint16 GPIO61:1; // 29 Input inversion control for this pin Uint16 GPIO62:1; // 30 Input inversion control for this pin Uint16 GPIO63:1; // 31 Input inversion control for this pin }; union GPBINV_REG { Uint32 all; struct GPBINV_BITS bit; }; struct GPBODR_BITS { // bits description Uint16 GPIO32:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO33:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO34:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO35:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO36:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO37:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO38:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO39:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO40:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO41:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO42:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO43:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO44:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO45:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO46:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO47:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO48:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO49:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO50:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO51:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO52:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO53:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO54:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO55:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO56:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO57:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO58:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO59:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO60:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO61:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO62:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO63:1; // 31 Outpout Open-Drain control for this pin }; union GPBODR_REG { Uint32 all; struct GPBODR_BITS bit; }; struct GPBAMSEL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:1; // 4 Reserved Uint16 rsvd6:1; // 5 Reserved Uint16 rsvd7:1; // 6 Reserved Uint16 rsvd8:1; // 7 Reserved Uint16 rsvd9:1; // 8 Reserved Uint16 rsvd10:1; // 9 Reserved Uint16 GPIO42:1; // 10 Analog Mode select for this pin Uint16 GPIO43:1; // 11 Analog Mode select for this pin Uint16 rsvd11:1; // 12 Reserved Uint16 rsvd12:1; // 13 Reserved Uint16 rsvd13:1; // 14 Reserved Uint16 rsvd14:1; // 15 Reserved Uint16 rsvd15:1; // 16 Reserved Uint16 rsvd16:1; // 17 Reserved Uint16 rsvd17:1; // 18 Reserved Uint16 rsvd18:1; // 19 Reserved Uint16 rsvd19:1; // 20 Reserved Uint16 rsvd20:1; // 21 Reserved Uint16 rsvd21:1; // 22 Reserved Uint16 rsvd22:1; // 23 Reserved Uint16 rsvd23:1; // 24 Reserved Uint16 rsvd24:1; // 25 Reserved Uint16 rsvd25:1; // 26 Reserved Uint16 rsvd26:1; // 27 Reserved Uint16 rsvd27:1; // 28 Reserved Uint16 rsvd28:1; // 29 Reserved Uint16 rsvd29:1; // 30 Reserved Uint16 rsvd30:1; // 31 Reserved }; union GPBAMSEL_REG { Uint32 all; struct GPBAMSEL_BITS bit; }; struct GPBGMUX1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 }; union GPBGMUX1_REG { Uint32 all; struct GPBGMUX1_BITS bit; }; struct GPBGMUX2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 }; union GPBGMUX2_REG { Uint32 all; struct GPBGMUX2_BITS bit; }; struct GPBCSEL1_BITS { // bits description Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select Uint16 GPIO36:4; // 19:16 GPIO36 Master CPU Select Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select Uint16 GPIO38:4; // 27:24 GPIO38 Master CPU Select Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select }; union GPBCSEL1_REG { Uint32 all; struct GPBCSEL1_BITS bit; }; struct GPBCSEL2_BITS { // bits description Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select }; union GPBCSEL2_REG { Uint32 all; struct GPBCSEL2_BITS bit; }; struct GPBCSEL3_BITS { // bits description Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select }; union GPBCSEL3_REG { Uint32 all; struct GPBCSEL3_BITS bit; }; struct GPBCSEL4_BITS { // bits description Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select Uint16 GPIO60:4; // 19:16 GPIO60 Master CPU Select Uint16 GPIO61:4; // 23:20 GPIO61 Master CPU Select Uint16 GPIO62:4; // 27:24 GPIO62 Master CPU Select Uint16 GPIO63:4; // 31:28 GPIO63 Master CPU Select }; union GPBCSEL4_REG { Uint32 all; struct GPBCSEL4_BITS bit; }; struct GPBLOCK_BITS { // bits description Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin Uint16 GPIO36:1; // 4 Configuration Lock bit for this pin Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin Uint16 GPIO38:1; // 6 Configuration Lock bit for this pin Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin Uint16 GPIO60:1; // 28 Configuration Lock bit for this pin Uint16 GPIO61:1; // 29 Configuration Lock bit for this pin Uint16 GPIO62:1; // 30 Configuration Lock bit for this pin Uint16 GPIO63:1; // 31 Configuration Lock bit for this pin }; union GPBLOCK_REG { Uint32 all; struct GPBLOCK_BITS bit; }; struct GPBCR_BITS { // bits description Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO36:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO38:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO60:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO61:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO62:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO63:1; // 31 Configuration lock commit bit for this pin }; union GPBCR_REG { Uint32 all; struct GPBCR_BITS bit; }; struct GPCCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO64 to GPIO71 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO72 to GPIO79 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO80 to GPIO87 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO88 to GPIO95 }; union GPCCTRL_REG { Uint32 all; struct GPCCTRL_BITS bit; }; struct GPCQSEL1_BITS { // bits description Uint16 GPIO64:2; // 1:0 Select input qualification type for GPIO64 Uint16 GPIO65:2; // 3:2 Select input qualification type for GPIO65 Uint16 GPIO66:2; // 5:4 Select input qualification type for GPIO66 Uint16 GPIO67:2; // 7:6 Select input qualification type for GPIO67 Uint16 GPIO68:2; // 9:8 Select input qualification type for GPIO68 Uint16 GPIO69:2; // 11:10 Select input qualification type for GPIO69 Uint16 GPIO70:2; // 13:12 Select input qualification type for GPIO70 Uint16 GPIO71:2; // 15:14 Select input qualification type for GPIO71 Uint16 GPIO72:2; // 17:16 Select input qualification type for GPIO72 Uint16 GPIO73:2; // 19:18 Select input qualification type for GPIO73 Uint16 GPIO74:2; // 21:20 Select input qualification type for GPIO74 Uint16 GPIO75:2; // 23:22 Select input qualification type for GPIO75 Uint16 GPIO76:2; // 25:24 Select input qualification type for GPIO76 Uint16 GPIO77:2; // 27:26 Select input qualification type for GPIO77 Uint16 GPIO78:2; // 29:28 Select input qualification type for GPIO78 Uint16 GPIO79:2; // 31:30 Select input qualification type for GPIO79 }; union GPCQSEL1_REG { Uint32 all; struct GPCQSEL1_BITS bit; }; struct GPCQSEL2_BITS { // bits description Uint16 GPIO80:2; // 1:0 Select input qualification type for GPIO80 Uint16 GPIO81:2; // 3:2 Select input qualification type for GPIO81 Uint16 GPIO82:2; // 5:4 Select input qualification type for GPIO82 Uint16 GPIO83:2; // 7:6 Select input qualification type for GPIO83 Uint16 GPIO84:2; // 9:8 Select input qualification type for GPIO84 Uint16 GPIO85:2; // 11:10 Select input qualification type for GPIO85 Uint16 GPIO86:2; // 13:12 Select input qualification type for GPIO86 Uint16 GPIO87:2; // 15:14 Select input qualification type for GPIO87 Uint16 GPIO88:2; // 17:16 Select input qualification type for GPIO88 Uint16 GPIO89:2; // 19:18 Select input qualification type for GPIO89 Uint16 GPIO90:2; // 21:20 Select input qualification type for GPIO90 Uint16 GPIO91:2; // 23:22 Select input qualification type for GPIO91 Uint16 GPIO92:2; // 25:24 Select input qualification type for GPIO92 Uint16 GPIO93:2; // 27:26 Select input qualification type for GPIO93 Uint16 GPIO94:2; // 29:28 Select input qualification type for GPIO94 Uint16 GPIO95:2; // 31:30 Select input qualification type for GPIO95 }; union GPCQSEL2_REG { Uint32 all; struct GPCQSEL2_BITS bit; }; struct GPCMUX1_BITS { // bits description Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 }; union GPCMUX1_REG { Uint32 all; struct GPCMUX1_BITS bit; }; struct GPCMUX2_BITS { // bits description Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 }; union GPCMUX2_REG { Uint32 all; struct GPCMUX2_BITS bit; }; struct GPCDIR_BITS { // bits description Uint16 GPIO64:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO65:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO66:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO67:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO68:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO69:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO70:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO71:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO72:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO73:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO74:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO75:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO76:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO77:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO78:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO79:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO80:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO81:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO82:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO83:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO84:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO85:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO86:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO87:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO88:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO89:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO90:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO91:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO92:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO93:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO94:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO95:1; // 31 Defines direction for this pin in GPIO mode }; union GPCDIR_REG { Uint32 all; struct GPCDIR_BITS bit; }; struct GPCPUD_BITS { // bits description Uint16 GPIO64:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO65:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO66:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO67:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO68:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO69:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO70:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO71:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO72:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO73:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO74:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO75:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO76:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO77:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO78:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO79:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO80:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO81:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO82:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO83:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO84:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO85:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO86:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO87:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO88:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO89:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO90:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO91:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO92:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO93:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO94:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO95:1; // 31 Pull-Up Disable control for this pin }; union GPCPUD_REG { Uint32 all; struct GPCPUD_BITS bit; }; struct GPCINV_BITS { // bits description Uint16 GPIO64:1; // 0 Input inversion control for this pin Uint16 GPIO65:1; // 1 Input inversion control for this pin Uint16 GPIO66:1; // 2 Input inversion control for this pin Uint16 GPIO67:1; // 3 Input inversion control for this pin Uint16 GPIO68:1; // 4 Input inversion control for this pin Uint16 GPIO69:1; // 5 Input inversion control for this pin Uint16 GPIO70:1; // 6 Input inversion control for this pin Uint16 GPIO71:1; // 7 Input inversion control for this pin Uint16 GPIO72:1; // 8 Input inversion control for this pin Uint16 GPIO73:1; // 9 Input inversion control for this pin Uint16 GPIO74:1; // 10 Input inversion control for this pin Uint16 GPIO75:1; // 11 Input inversion control for this pin Uint16 GPIO76:1; // 12 Input inversion control for this pin Uint16 GPIO77:1; // 13 Input inversion control for this pin Uint16 GPIO78:1; // 14 Input inversion control for this pin Uint16 GPIO79:1; // 15 Input inversion control for this pin Uint16 GPIO80:1; // 16 Input inversion control for this pin Uint16 GPIO81:1; // 17 Input inversion control for this pin Uint16 GPIO82:1; // 18 Input inversion control for this pin Uint16 GPIO83:1; // 19 Input inversion control for this pin Uint16 GPIO84:1; // 20 Input inversion control for this pin Uint16 GPIO85:1; // 21 Input inversion control for this pin Uint16 GPIO86:1; // 22 Input inversion control for this pin Uint16 GPIO87:1; // 23 Input inversion control for this pin Uint16 GPIO88:1; // 24 Input inversion control for this pin Uint16 GPIO89:1; // 25 Input inversion control for this pin Uint16 GPIO90:1; // 26 Input inversion control for this pin Uint16 GPIO91:1; // 27 Input inversion control for this pin Uint16 GPIO92:1; // 28 Input inversion control for this pin Uint16 GPIO93:1; // 29 Input inversion control for this pin Uint16 GPIO94:1; // 30 Input inversion control for this pin Uint16 GPIO95:1; // 31 Input inversion control for this pin }; union GPCINV_REG { Uint32 all; struct GPCINV_BITS bit; }; struct GPCODR_BITS { // bits description Uint16 GPIO64:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO65:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO66:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO67:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO68:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO69:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO70:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO71:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO72:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO73:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO74:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO75:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO76:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO77:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO78:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO79:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO80:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO81:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO82:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO83:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO84:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO85:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO86:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO87:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO88:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO89:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO90:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO91:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO92:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO93:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO94:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO95:1; // 31 Outpout Open-Drain control for this pin }; union GPCODR_REG { Uint32 all; struct GPCODR_BITS bit; }; struct GPCGMUX1_BITS { // bits description Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 }; union GPCGMUX1_REG { Uint32 all; struct GPCGMUX1_BITS bit; }; struct GPCGMUX2_BITS { // bits description Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 }; union GPCGMUX2_REG { Uint32 all; struct GPCGMUX2_BITS bit; }; struct GPCCSEL1_BITS { // bits description Uint16 GPIO64:4; // 3:0 GPIO64 Master CPU Select Uint16 GPIO65:4; // 7:4 GPIO65 Master CPU Select Uint16 GPIO66:4; // 11:8 GPIO66 Master CPU Select Uint16 GPIO67:4; // 15:12 GPIO67 Master CPU Select Uint16 GPIO68:4; // 19:16 GPIO68 Master CPU Select Uint16 GPIO69:4; // 23:20 GPIO69 Master CPU Select Uint16 GPIO70:4; // 27:24 GPIO70 Master CPU Select Uint16 GPIO71:4; // 31:28 GPIO71 Master CPU Select }; union GPCCSEL1_REG { Uint32 all; struct GPCCSEL1_BITS bit; }; struct GPCCSEL2_BITS { // bits description Uint16 GPIO72:4; // 3:0 GPIO72 Master CPU Select Uint16 GPIO73:4; // 7:4 GPIO73 Master CPU Select Uint16 GPIO74:4; // 11:8 GPIO74 Master CPU Select Uint16 GPIO75:4; // 15:12 GPIO75 Master CPU Select Uint16 GPIO76:4; // 19:16 GPIO76 Master CPU Select Uint16 GPIO77:4; // 23:20 GPIO77 Master CPU Select Uint16 GPIO78:4; // 27:24 GPIO78 Master CPU Select Uint16 GPIO79:4; // 31:28 GPIO79 Master CPU Select }; union GPCCSEL2_REG { Uint32 all; struct GPCCSEL2_BITS bit; }; struct GPCCSEL3_BITS { // bits description Uint16 GPIO80:4; // 3:0 GPIO80 Master CPU Select Uint16 GPIO81:4; // 7:4 GPIO81 Master CPU Select Uint16 GPIO82:4; // 11:8 GPIO82 Master CPU Select Uint16 GPIO83:4; // 15:12 GPIO83 Master CPU Select Uint16 GPIO84:4; // 19:16 GPIO84 Master CPU Select Uint16 GPIO85:4; // 23:20 GPIO85 Master CPU Select Uint16 GPIO86:4; // 27:24 GPIO86 Master CPU Select Uint16 GPIO87:4; // 31:28 GPIO87 Master CPU Select }; union GPCCSEL3_REG { Uint32 all; struct GPCCSEL3_BITS bit; }; struct GPCCSEL4_BITS { // bits description Uint16 GPIO88:4; // 3:0 GPIO88 Master CPU Select Uint16 GPIO89:4; // 7:4 GPIO89 Master CPU Select Uint16 GPIO90:4; // 11:8 GPIO90 Master CPU Select Uint16 GPIO91:4; // 15:12 GPIO91 Master CPU Select Uint16 GPIO92:4; // 19:16 GPIO92 Master CPU Select Uint16 GPIO93:4; // 23:20 GPIO93 Master CPU Select Uint16 GPIO94:4; // 27:24 GPIO94 Master CPU Select Uint16 GPIO95:4; // 31:28 GPIO95 Master CPU Select }; union GPCCSEL4_REG { Uint32 all; struct GPCCSEL4_BITS bit; }; struct GPCLOCK_BITS { // bits description Uint16 GPIO64:1; // 0 Configuration Lock bit for this pin Uint16 GPIO65:1; // 1 Configuration Lock bit for this pin Uint16 GPIO66:1; // 2 Configuration Lock bit for this pin Uint16 GPIO67:1; // 3 Configuration Lock bit for this pin Uint16 GPIO68:1; // 4 Configuration Lock bit for this pin Uint16 GPIO69:1; // 5 Configuration Lock bit for this pin Uint16 GPIO70:1; // 6 Configuration Lock bit for this pin Uint16 GPIO71:1; // 7 Configuration Lock bit for this pin Uint16 GPIO72:1; // 8 Configuration Lock bit for this pin Uint16 GPIO73:1; // 9 Configuration Lock bit for this pin Uint16 GPIO74:1; // 10 Configuration Lock bit for this pin Uint16 GPIO75:1; // 11 Configuration Lock bit for this pin Uint16 GPIO76:1; // 12 Configuration Lock bit for this pin Uint16 GPIO77:1; // 13 Configuration Lock bit for this pin Uint16 GPIO78:1; // 14 Configuration Lock bit for this pin Uint16 GPIO79:1; // 15 Configuration Lock bit for this pin Uint16 GPIO80:1; // 16 Configuration Lock bit for this pin Uint16 GPIO81:1; // 17 Configuration Lock bit for this pin Uint16 GPIO82:1; // 18 Configuration Lock bit for this pin Uint16 GPIO83:1; // 19 Configuration Lock bit for this pin Uint16 GPIO84:1; // 20 Configuration Lock bit for this pin Uint16 GPIO85:1; // 21 Configuration Lock bit for this pin Uint16 GPIO86:1; // 22 Configuration Lock bit for this pin Uint16 GPIO87:1; // 23 Configuration Lock bit for this pin Uint16 GPIO88:1; // 24 Configuration Lock bit for this pin Uint16 GPIO89:1; // 25 Configuration Lock bit for this pin Uint16 GPIO90:1; // 26 Configuration Lock bit for this pin Uint16 GPIO91:1; // 27 Configuration Lock bit for this pin Uint16 GPIO92:1; // 28 Configuration Lock bit for this pin Uint16 GPIO93:1; // 29 Configuration Lock bit for this pin Uint16 GPIO94:1; // 30 Configuration Lock bit for this pin Uint16 GPIO95:1; // 31 Configuration Lock bit for this pin }; union GPCLOCK_REG { Uint32 all; struct GPCLOCK_BITS bit; }; struct GPCCR_BITS { // bits description Uint16 GPIO64:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO65:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO66:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO67:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO68:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO69:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO70:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO71:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO72:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO73:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO74:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO75:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO76:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO77:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO78:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO79:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO80:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO81:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO82:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO83:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO84:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO85:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO86:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO87:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO88:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO89:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO90:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO91:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO92:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO93:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO94:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO95:1; // 31 Configuration lock commit bit for this pin }; union GPCCR_REG { Uint32 all; struct GPCCR_BITS bit; }; struct GPDCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO96 to GPIO103 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO104 to GPIO111 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO112 to GPIO119 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO120 to GPIO127 }; union GPDCTRL_REG { Uint32 all; struct GPDCTRL_BITS bit; }; struct GPDQSEL1_BITS { // bits description Uint16 GPIO96:2; // 1:0 Select input qualification type for GPIO96 Uint16 GPIO97:2; // 3:2 Select input qualification type for GPIO97 Uint16 GPIO98:2; // 5:4 Select input qualification type for GPIO98 Uint16 GPIO99:2; // 7:6 Select input qualification type for GPIO99 Uint16 GPIO100:2; // 9:8 Select input qualification type for GPIO100 Uint16 GPIO101:2; // 11:10 Select input qualification type for GPIO101 Uint16 GPIO102:2; // 13:12 Select input qualification type for GPIO102 Uint16 GPIO103:2; // 15:14 Select input qualification type for GPIO103 Uint16 GPIO104:2; // 17:16 Select input qualification type for GPIO104 Uint16 GPIO105:2; // 19:18 Select input qualification type for GPIO105 Uint16 GPIO106:2; // 21:20 Select input qualification type for GPIO106 Uint16 GPIO107:2; // 23:22 Select input qualification type for GPIO107 Uint16 GPIO108:2; // 25:24 Select input qualification type for GPIO108 Uint16 GPIO109:2; // 27:26 Select input qualification type for GPIO109 Uint16 GPIO110:2; // 29:28 Select input qualification type for GPIO110 Uint16 GPIO111:2; // 31:30 Select input qualification type for GPIO111 }; union GPDQSEL1_REG { Uint32 all; struct GPDQSEL1_BITS bit; }; struct GPDQSEL2_BITS { // bits description Uint16 GPIO112:2; // 1:0 Select input qualification type for GPIO112 Uint16 GPIO113:2; // 3:2 Select input qualification type for GPIO113 Uint16 GPIO114:2; // 5:4 Select input qualification type for GPIO114 Uint16 GPIO115:2; // 7:6 Select input qualification type for GPIO115 Uint16 GPIO116:2; // 9:8 Select input qualification type for GPIO116 Uint16 GPIO117:2; // 11:10 Select input qualification type for GPIO117 Uint16 GPIO118:2; // 13:12 Select input qualification type for GPIO118 Uint16 GPIO119:2; // 15:14 Select input qualification type for GPIO119 Uint16 GPIO120:2; // 17:16 Select input qualification type for GPIO120 Uint16 GPIO121:2; // 19:18 Select input qualification type for GPIO121 Uint16 GPIO122:2; // 21:20 Select input qualification type for GPIO122 Uint16 GPIO123:2; // 23:22 Select input qualification type for GPIO123 Uint16 GPIO124:2; // 25:24 Select input qualification type for GPIO124 Uint16 GPIO125:2; // 27:26 Select input qualification type for GPIO125 Uint16 GPIO126:2; // 29:28 Select input qualification type for GPIO126 Uint16 GPIO127:2; // 31:30 Select input qualification type for GPIO127 }; union GPDQSEL2_REG { Uint32 all; struct GPDQSEL2_BITS bit; }; struct GPDMUX1_BITS { // bits description Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 }; union GPDMUX1_REG { Uint32 all; struct GPDMUX1_BITS bit; }; struct GPDMUX2_BITS { // bits description Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 }; union GPDMUX2_REG { Uint32 all; struct GPDMUX2_BITS bit; }; struct GPDDIR_BITS { // bits description Uint16 GPIO96:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO97:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO98:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO99:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO100:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO101:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO102:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO103:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO104:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO105:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO106:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO107:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO108:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO109:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO110:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO111:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO112:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO113:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO114:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO115:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO116:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO117:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO118:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO119:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO120:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO121:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO122:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO123:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO124:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO125:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO126:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO127:1; // 31 Defines direction for this pin in GPIO mode }; union GPDDIR_REG { Uint32 all; struct GPDDIR_BITS bit; }; struct GPDPUD_BITS { // bits description Uint16 GPIO96:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO97:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO98:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO99:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO100:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO101:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO102:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO103:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO104:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO105:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO106:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO107:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO108:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO109:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO110:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO111:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO112:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO113:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO114:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO115:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO116:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO117:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO118:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO119:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO120:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO121:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO122:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO123:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO124:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO125:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO126:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO127:1; // 31 Pull-Up Disable control for this pin }; union GPDPUD_REG { Uint32 all; struct GPDPUD_BITS bit; }; struct GPDINV_BITS { // bits description Uint16 GPIO96:1; // 0 Input inversion control for this pin Uint16 GPIO97:1; // 1 Input inversion control for this pin Uint16 GPIO98:1; // 2 Input inversion control for this pin Uint16 GPIO99:1; // 3 Input inversion control for this pin Uint16 GPIO100:1; // 4 Input inversion control for this pin Uint16 GPIO101:1; // 5 Input inversion control for this pin Uint16 GPIO102:1; // 6 Input inversion control for this pin Uint16 GPIO103:1; // 7 Input inversion control for this pin Uint16 GPIO104:1; // 8 Input inversion control for this pin Uint16 GPIO105:1; // 9 Input inversion control for this pin Uint16 GPIO106:1; // 10 Input inversion control for this pin Uint16 GPIO107:1; // 11 Input inversion control for this pin Uint16 GPIO108:1; // 12 Input inversion control for this pin Uint16 GPIO109:1; // 13 Input inversion control for this pin Uint16 GPIO110:1; // 14 Input inversion control for this pin Uint16 GPIO111:1; // 15 Input inversion control for this pin Uint16 GPIO112:1; // 16 Input inversion control for this pin Uint16 GPIO113:1; // 17 Input inversion control for this pin Uint16 GPIO114:1; // 18 Input inversion control for this pin Uint16 GPIO115:1; // 19 Input inversion control for this pin Uint16 GPIO116:1; // 20 Input inversion control for this pin Uint16 GPIO117:1; // 21 Input inversion control for this pin Uint16 GPIO118:1; // 22 Input inversion control for this pin Uint16 GPIO119:1; // 23 Input inversion control for this pin Uint16 GPIO120:1; // 24 Input inversion control for this pin Uint16 GPIO121:1; // 25 Input inversion control for this pin Uint16 GPIO122:1; // 26 Input inversion control for this pin Uint16 GPIO123:1; // 27 Input inversion control for this pin Uint16 GPIO124:1; // 28 Input inversion control for this pin Uint16 GPIO125:1; // 29 Input inversion control for this pin Uint16 GPIO126:1; // 30 Input inversion control for this pin Uint16 GPIO127:1; // 31 Input inversion control for this pin }; union GPDINV_REG { Uint32 all; struct GPDINV_BITS bit; }; struct GPDODR_BITS { // bits description Uint16 GPIO96:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO97:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO98:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO99:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO100:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO101:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO102:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO103:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO104:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO105:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO106:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO107:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO108:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO109:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO110:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO111:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO112:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO113:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO114:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO115:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO116:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO117:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO118:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO119:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO120:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO121:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO122:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO123:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO124:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO125:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO126:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO127:1; // 31 Outpout Open-Drain control for this pin }; union GPDODR_REG { Uint32 all; struct GPDODR_BITS bit; }; struct GPDGMUX1_BITS { // bits description Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 }; union GPDGMUX1_REG { Uint32 all; struct GPDGMUX1_BITS bit; }; struct GPDGMUX2_BITS { // bits description Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 }; union GPDGMUX2_REG { Uint32 all; struct GPDGMUX2_BITS bit; }; struct GPDCSEL1_BITS { // bits description Uint16 GPIO96:4; // 3:0 GPIO96 Master CPU Select Uint16 GPIO97:4; // 7:4 GPIO97 Master CPU Select Uint16 GPIO98:4; // 11:8 GPIO98 Master CPU Select Uint16 GPIO99:4; // 15:12 GPIO99 Master CPU Select Uint16 GPIO100:4; // 19:16 GPIO100 Master CPU Select Uint16 GPIO101:4; // 23:20 GPIO101 Master CPU Select Uint16 GPIO102:4; // 27:24 GPIO102 Master CPU Select Uint16 GPIO103:4; // 31:28 GPIO103 Master CPU Select }; union GPDCSEL1_REG { Uint32 all; struct GPDCSEL1_BITS bit; }; struct GPDCSEL2_BITS { // bits description Uint16 GPIO104:4; // 3:0 GPIO104 Master CPU Select Uint16 GPIO105:4; // 7:4 GPIO105 Master CPU Select Uint16 GPIO106:4; // 11:8 GPIO106 Master CPU Select Uint16 GPIO107:4; // 15:12 GPIO107 Master CPU Select Uint16 GPIO108:4; // 19:16 GPIO108 Master CPU Select Uint16 GPIO109:4; // 23:20 GPIO109 Master CPU Select Uint16 GPIO110:4; // 27:24 GPIO110 Master CPU Select Uint16 GPIO111:4; // 31:28 GPIO111 Master CPU Select }; union GPDCSEL2_REG { Uint32 all; struct GPDCSEL2_BITS bit; }; struct GPDCSEL3_BITS { // bits description Uint16 GPIO112:4; // 3:0 GPIO112 Master CPU Select Uint16 GPIO113:4; // 7:4 GPIO113 Master CPU Select Uint16 GPIO114:4; // 11:8 GPIO114 Master CPU Select Uint16 GPIO115:4; // 15:12 GPIO115 Master CPU Select Uint16 GPIO116:4; // 19:16 GPIO116 Master CPU Select Uint16 GPIO117:4; // 23:20 GPIO117 Master CPU Select Uint16 GPIO118:4; // 27:24 GPIO118 Master CPU Select Uint16 GPIO119:4; // 31:28 GPIO119 Master CPU Select }; union GPDCSEL3_REG { Uint32 all; struct GPDCSEL3_BITS bit; }; struct GPDCSEL4_BITS { // bits description Uint16 GPIO120:4; // 3:0 GPIO120 Master CPU Select Uint16 GPIO121:4; // 7:4 GPIO121 Master CPU Select Uint16 GPIO122:4; // 11:8 GPIO122 Master CPU Select Uint16 GPIO123:4; // 15:12 GPIO123 Master CPU Select Uint16 GPIO124:4; // 19:16 GPIO124 Master CPU Select Uint16 GPIO125:4; // 23:20 GPIO125 Master CPU Select Uint16 GPIO126:4; // 27:24 GPIO126 Master CPU Select Uint16 GPIO127:4; // 31:28 GPIO127 Master CPU Select }; union GPDCSEL4_REG { Uint32 all; struct GPDCSEL4_BITS bit; }; struct GPDLOCK_BITS { // bits description Uint16 GPIO96:1; // 0 Configuration Lock bit for this pin Uint16 GPIO97:1; // 1 Configuration Lock bit for this pin Uint16 GPIO98:1; // 2 Configuration Lock bit for this pin Uint16 GPIO99:1; // 3 Configuration Lock bit for this pin Uint16 GPIO100:1; // 4 Configuration Lock bit for this pin Uint16 GPIO101:1; // 5 Configuration Lock bit for this pin Uint16 GPIO102:1; // 6 Configuration Lock bit for this pin Uint16 GPIO103:1; // 7 Configuration Lock bit for this pin Uint16 GPIO104:1; // 8 Configuration Lock bit for this pin Uint16 GPIO105:1; // 9 Configuration Lock bit for this pin Uint16 GPIO106:1; // 10 Configuration Lock bit for this pin Uint16 GPIO107:1; // 11 Configuration Lock bit for this pin Uint16 GPIO108:1; // 12 Configuration Lock bit for this pin Uint16 GPIO109:1; // 13 Configuration Lock bit for this pin Uint16 GPIO110:1; // 14 Configuration Lock bit for this pin Uint16 GPIO111:1; // 15 Configuration Lock bit for this pin Uint16 GPIO112:1; // 16 Configuration Lock bit for this pin Uint16 GPIO113:1; // 17 Configuration Lock bit for this pin Uint16 GPIO114:1; // 18 Configuration Lock bit for this pin Uint16 GPIO115:1; // 19 Configuration Lock bit for this pin Uint16 GPIO116:1; // 20 Configuration Lock bit for this pin Uint16 GPIO117:1; // 21 Configuration Lock bit for this pin Uint16 GPIO118:1; // 22 Configuration Lock bit for this pin Uint16 GPIO119:1; // 23 Configuration Lock bit for this pin Uint16 GPIO120:1; // 24 Configuration Lock bit for this pin Uint16 GPIO121:1; // 25 Configuration Lock bit for this pin Uint16 GPIO122:1; // 26 Configuration Lock bit for this pin Uint16 GPIO123:1; // 27 Configuration Lock bit for this pin Uint16 GPIO124:1; // 28 Configuration Lock bit for this pin Uint16 GPIO125:1; // 29 Configuration Lock bit for this pin Uint16 GPIO126:1; // 30 Configuration Lock bit for this pin Uint16 GPIO127:1; // 31 Configuration Lock bit for this pin }; union GPDLOCK_REG { Uint32 all; struct GPDLOCK_BITS bit; }; struct GPDCR_BITS { // bits description Uint16 GPIO96:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO97:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO98:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO99:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO100:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO101:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO102:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO103:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO104:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO105:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO106:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO107:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO108:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO109:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO110:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO111:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO112:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO113:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO114:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO115:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO116:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO117:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO118:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO119:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO120:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO121:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO122:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO123:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO124:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO125:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO126:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO127:1; // 31 Configuration lock commit bit for this pin }; union GPDCR_REG { Uint32 all; struct GPDCR_BITS bit; }; struct GPECTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO128 to GPIO135 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO136 to GPIO143 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO144 to GPIO151 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO152 to GPIO159 }; union GPECTRL_REG { Uint32 all; struct GPECTRL_BITS bit; }; struct GPEQSEL1_BITS { // bits description Uint16 GPIO128:2; // 1:0 Select input qualification type for GPIO128 Uint16 GPIO129:2; // 3:2 Select input qualification type for GPIO129 Uint16 GPIO130:2; // 5:4 Select input qualification type for GPIO130 Uint16 GPIO131:2; // 7:6 Select input qualification type for GPIO131 Uint16 GPIO132:2; // 9:8 Select input qualification type for GPIO132 Uint16 GPIO133:2; // 11:10 Select input qualification type for GPIO133 Uint16 GPIO134:2; // 13:12 Select input qualification type for GPIO134 Uint16 GPIO135:2; // 15:14 Select input qualification type for GPIO135 Uint16 GPIO136:2; // 17:16 Select input qualification type for GPIO136 Uint16 GPIO137:2; // 19:18 Select input qualification type for GPIO137 Uint16 GPIO138:2; // 21:20 Select input qualification type for GPIO138 Uint16 GPIO139:2; // 23:22 Select input qualification type for GPIO139 Uint16 GPIO140:2; // 25:24 Select input qualification type for GPIO140 Uint16 GPIO141:2; // 27:26 Select input qualification type for GPIO141 Uint16 GPIO142:2; // 29:28 Select input qualification type for GPIO142 Uint16 GPIO143:2; // 31:30 Select input qualification type for GPIO143 }; union GPEQSEL1_REG { Uint32 all; struct GPEQSEL1_BITS bit; }; struct GPEQSEL2_BITS { // bits description Uint16 GPIO144:2; // 1:0 Select input qualification type for GPIO144 Uint16 GPIO145:2; // 3:2 Select input qualification type for GPIO145 Uint16 GPIO146:2; // 5:4 Select input qualification type for GPIO146 Uint16 GPIO147:2; // 7:6 Select input qualification type for GPIO147 Uint16 GPIO148:2; // 9:8 Select input qualification type for GPIO148 Uint16 GPIO149:2; // 11:10 Select input qualification type for GPIO149 Uint16 GPIO150:2; // 13:12 Select input qualification type for GPIO150 Uint16 GPIO151:2; // 15:14 Select input qualification type for GPIO151 Uint16 GPIO152:2; // 17:16 Select input qualification type for GPIO152 Uint16 GPIO153:2; // 19:18 Select input qualification type for GPIO153 Uint16 GPIO154:2; // 21:20 Select input qualification type for GPIO154 Uint16 GPIO155:2; // 23:22 Select input qualification type for GPIO155 Uint16 GPIO156:2; // 25:24 Select input qualification type for GPIO156 Uint16 GPIO157:2; // 27:26 Select input qualification type for GPIO157 Uint16 GPIO158:2; // 29:28 Select input qualification type for GPIO158 Uint16 GPIO159:2; // 31:30 Select input qualification type for GPIO159 }; union GPEQSEL2_REG { Uint32 all; struct GPEQSEL2_BITS bit; }; struct GPEMUX1_BITS { // bits description Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 }; union GPEMUX1_REG { Uint32 all; struct GPEMUX1_BITS bit; }; struct GPEMUX2_BITS { // bits description Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 }; union GPEMUX2_REG { Uint32 all; struct GPEMUX2_BITS bit; }; struct GPEDIR_BITS { // bits description Uint16 GPIO128:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO129:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO130:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO131:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO132:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO133:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO134:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO135:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO136:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO137:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO138:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO139:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO140:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO141:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO142:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO143:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO144:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO145:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO146:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO147:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO148:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO149:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO150:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO151:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO152:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO153:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO154:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO155:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO156:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO157:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO158:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO159:1; // 31 Defines direction for this pin in GPIO mode }; union GPEDIR_REG { Uint32 all; struct GPEDIR_BITS bit; }; struct GPEPUD_BITS { // bits description Uint16 GPIO128:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO129:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO130:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO131:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO132:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO133:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO134:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO135:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO136:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO137:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO138:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO139:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO140:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO141:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO142:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO143:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO144:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO145:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO146:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO147:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO148:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO149:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO150:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO151:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO152:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO153:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO154:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO155:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO156:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO157:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO158:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO159:1; // 31 Pull-Up Disable control for this pin }; union GPEPUD_REG { Uint32 all; struct GPEPUD_BITS bit; }; struct GPEINV_BITS { // bits description Uint16 GPIO128:1; // 0 Input inversion control for this pin Uint16 GPIO129:1; // 1 Input inversion control for this pin Uint16 GPIO130:1; // 2 Input inversion control for this pin Uint16 GPIO131:1; // 3 Input inversion control for this pin Uint16 GPIO132:1; // 4 Input inversion control for this pin Uint16 GPIO133:1; // 5 Input inversion control for this pin Uint16 GPIO134:1; // 6 Input inversion control for this pin Uint16 GPIO135:1; // 7 Input inversion control for this pin Uint16 GPIO136:1; // 8 Input inversion control for this pin Uint16 GPIO137:1; // 9 Input inversion control for this pin Uint16 GPIO138:1; // 10 Input inversion control for this pin Uint16 GPIO139:1; // 11 Input inversion control for this pin Uint16 GPIO140:1; // 12 Input inversion control for this pin Uint16 GPIO141:1; // 13 Input inversion control for this pin Uint16 GPIO142:1; // 14 Input inversion control for this pin Uint16 GPIO143:1; // 15 Input inversion control for this pin Uint16 GPIO144:1; // 16 Input inversion control for this pin Uint16 GPIO145:1; // 17 Input inversion control for this pin Uint16 GPIO146:1; // 18 Input inversion control for this pin Uint16 GPIO147:1; // 19 Input inversion control for this pin Uint16 GPIO148:1; // 20 Input inversion control for this pin Uint16 GPIO149:1; // 21 Input inversion control for this pin Uint16 GPIO150:1; // 22 Input inversion control for this pin Uint16 GPIO151:1; // 23 Input inversion control for this pin Uint16 GPIO152:1; // 24 Input inversion control for this pin Uint16 GPIO153:1; // 25 Input inversion control for this pin Uint16 GPIO154:1; // 26 Input inversion control for this pin Uint16 GPIO155:1; // 27 Input inversion control for this pin Uint16 GPIO156:1; // 28 Input inversion control for this pin Uint16 GPIO157:1; // 29 Input inversion control for this pin Uint16 GPIO158:1; // 30 Input inversion control for this pin Uint16 GPIO159:1; // 31 Input inversion control for this pin }; union GPEINV_REG { Uint32 all; struct GPEINV_BITS bit; }; struct GPEODR_BITS { // bits description Uint16 GPIO128:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO129:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO130:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO131:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO132:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO133:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO134:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO135:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO136:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO137:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO138:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO139:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO140:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO141:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO142:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO143:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO144:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO145:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO146:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO147:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO148:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO149:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO150:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO151:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO152:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO153:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO154:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO155:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO156:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO157:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO158:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO159:1; // 31 Outpout Open-Drain control for this pin }; union GPEODR_REG { Uint32 all; struct GPEODR_BITS bit; }; struct GPEGMUX1_BITS { // bits description Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 }; union GPEGMUX1_REG { Uint32 all; struct GPEGMUX1_BITS bit; }; struct GPEGMUX2_BITS { // bits description Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 }; union GPEGMUX2_REG { Uint32 all; struct GPEGMUX2_BITS bit; }; struct GPECSEL1_BITS { // bits description Uint16 GPIO128:4; // 3:0 GPIO128 Master CPU Select Uint16 GPIO129:4; // 7:4 GPIO129 Master CPU Select Uint16 GPIO130:4; // 11:8 GPIO130 Master CPU Select Uint16 GPIO131:4; // 15:12 GPIO131 Master CPU Select Uint16 GPIO132:4; // 19:16 GPIO132 Master CPU Select Uint16 GPIO133:4; // 23:20 GPIO133 Master CPU Select Uint16 GPIO134:4; // 27:24 GPIO134 Master CPU Select Uint16 GPIO135:4; // 31:28 GPIO135 Master CPU Select }; union GPECSEL1_REG { Uint32 all; struct GPECSEL1_BITS bit; }; struct GPECSEL2_BITS { // bits description Uint16 GPIO136:4; // 3:0 GPIO136 Master CPU Select Uint16 GPIO137:4; // 7:4 GPIO137 Master CPU Select Uint16 GPIO138:4; // 11:8 GPIO138 Master CPU Select Uint16 GPIO139:4; // 15:12 GPIO139 Master CPU Select Uint16 GPIO140:4; // 19:16 GPIO140 Master CPU Select Uint16 GPIO141:4; // 23:20 GPIO141 Master CPU Select Uint16 GPIO142:4; // 27:24 GPIO142 Master CPU Select Uint16 GPIO143:4; // 31:28 GPIO143 Master CPU Select }; union GPECSEL2_REG { Uint32 all; struct GPECSEL2_BITS bit; }; struct GPECSEL3_BITS { // bits description Uint16 GPIO144:4; // 3:0 GPIO144 Master CPU Select Uint16 GPIO145:4; // 7:4 GPIO145 Master CPU Select Uint16 GPIO146:4; // 11:8 GPIO146 Master CPU Select Uint16 GPIO147:4; // 15:12 GPIO147 Master CPU Select Uint16 GPIO148:4; // 19:16 GPIO148 Master CPU Select Uint16 GPIO149:4; // 23:20 GPIO149 Master CPU Select Uint16 GPIO150:4; // 27:24 GPIO150 Master CPU Select Uint16 GPIO151:4; // 31:28 GPIO151 Master CPU Select }; union GPECSEL3_REG { Uint32 all; struct GPECSEL3_BITS bit; }; struct GPECSEL4_BITS { // bits description Uint16 GPIO152:4; // 3:0 GPIO152 Master CPU Select Uint16 GPIO153:4; // 7:4 GPIO153 Master CPU Select Uint16 GPIO154:4; // 11:8 GPIO154 Master CPU Select Uint16 GPIO155:4; // 15:12 GPIO155 Master CPU Select Uint16 GPIO156:4; // 19:16 GPIO156 Master CPU Select Uint16 GPIO157:4; // 23:20 GPIO157 Master CPU Select Uint16 GPIO158:4; // 27:24 GPIO158 Master CPU Select Uint16 GPIO159:4; // 31:28 GPIO159 Master CPU Select }; union GPECSEL4_REG { Uint32 all; struct GPECSEL4_BITS bit; }; struct GPELOCK_BITS { // bits description Uint16 GPIO128:1; // 0 Configuration Lock bit for this pin Uint16 GPIO129:1; // 1 Configuration Lock bit for this pin Uint16 GPIO130:1; // 2 Configuration Lock bit for this pin Uint16 GPIO131:1; // 3 Configuration Lock bit for this pin Uint16 GPIO132:1; // 4 Configuration Lock bit for this pin Uint16 GPIO133:1; // 5 Configuration Lock bit for this pin Uint16 GPIO134:1; // 6 Configuration Lock bit for this pin Uint16 GPIO135:1; // 7 Configuration Lock bit for this pin Uint16 GPIO136:1; // 8 Configuration Lock bit for this pin Uint16 GPIO137:1; // 9 Configuration Lock bit for this pin Uint16 GPIO138:1; // 10 Configuration Lock bit for this pin Uint16 GPIO139:1; // 11 Configuration Lock bit for this pin Uint16 GPIO140:1; // 12 Configuration Lock bit for this pin Uint16 GPIO141:1; // 13 Configuration Lock bit for this pin Uint16 GPIO142:1; // 14 Configuration Lock bit for this pin Uint16 GPIO143:1; // 15 Configuration Lock bit for this pin Uint16 GPIO144:1; // 16 Configuration Lock bit for this pin Uint16 GPIO145:1; // 17 Configuration Lock bit for this pin Uint16 GPIO146:1; // 18 Configuration Lock bit for this pin Uint16 GPIO147:1; // 19 Configuration Lock bit for this pin Uint16 GPIO148:1; // 20 Configuration Lock bit for this pin Uint16 GPIO149:1; // 21 Configuration Lock bit for this pin Uint16 GPIO150:1; // 22 Configuration Lock bit for this pin Uint16 GPIO151:1; // 23 Configuration Lock bit for this pin Uint16 GPIO152:1; // 24 Configuration Lock bit for this pin Uint16 GPIO153:1; // 25 Configuration Lock bit for this pin Uint16 GPIO154:1; // 26 Configuration Lock bit for this pin Uint16 GPIO155:1; // 27 Configuration Lock bit for this pin Uint16 GPIO156:1; // 28 Configuration Lock bit for this pin Uint16 GPIO157:1; // 29 Configuration Lock bit for this pin Uint16 GPIO158:1; // 30 Configuration Lock bit for this pin Uint16 GPIO159:1; // 31 Configuration Lock bit for this pin }; union GPELOCK_REG { Uint32 all; struct GPELOCK_BITS bit; }; struct GPECR_BITS { // bits description Uint16 GPIO128:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO129:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO130:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO131:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO132:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO133:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO134:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO135:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO136:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO137:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO138:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO139:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO140:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO141:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO142:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO143:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO144:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO145:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO146:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO147:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO148:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO149:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO150:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO151:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO152:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO153:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO154:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO155:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO156:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO157:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO158:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO159:1; // 31 Configuration lock commit bit for this pin }; union GPECR_REG { Uint32 all; struct GPECR_BITS bit; }; struct GPFCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO160 to GPIO167 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO168 Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union GPFCTRL_REG { Uint32 all; struct GPFCTRL_BITS bit; }; struct GPFQSEL1_BITS { // bits description Uint16 GPIO160:2; // 1:0 Select input qualification type for GPIO160 Uint16 GPIO161:2; // 3:2 Select input qualification type for GPIO161 Uint16 GPIO162:2; // 5:4 Select input qualification type for GPIO162 Uint16 GPIO163:2; // 7:6 Select input qualification type for GPIO163 Uint16 GPIO164:2; // 9:8 Select input qualification type for GPIO164 Uint16 GPIO165:2; // 11:10 Select input qualification type for GPIO165 Uint16 GPIO166:2; // 13:12 Select input qualification type for GPIO166 Uint16 GPIO167:2; // 15:14 Select input qualification type for GPIO167 Uint16 GPIO168:2; // 17:16 Select input qualification type for GPIO168 Uint16 rsvd1:2; // 19:18 Reserved Uint16 rsvd2:2; // 21:20 Reserved Uint16 rsvd3:2; // 23:22 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:2; // 27:26 Reserved Uint16 rsvd6:2; // 29:28 Reserved Uint16 rsvd7:2; // 31:30 Reserved }; union GPFQSEL1_REG { Uint32 all; struct GPFQSEL1_BITS bit; }; struct GPFMUX1_BITS { // bits description Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 Uint16 rsvd1:2; // 19:18 Reserved Uint16 rsvd2:2; // 21:20 Reserved Uint16 rsvd3:2; // 23:22 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:2; // 27:26 Reserved Uint16 rsvd6:2; // 29:28 Reserved Uint16 rsvd7:2; // 31:30 Reserved }; union GPFMUX1_REG { Uint32 all; struct GPFMUX1_BITS bit; }; struct GPFDIR_BITS { // bits description Uint16 GPIO160:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO161:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO162:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO163:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO164:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO165:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO166:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO167:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO168:1; // 8 Defines direction for this pin in GPIO mode Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFDIR_REG { Uint32 all; struct GPFDIR_BITS bit; }; struct GPFPUD_BITS { // bits description Uint16 GPIO160:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO161:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO162:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO163:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO164:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO165:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO166:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO167:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO168:1; // 8 Pull-Up Disable control for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFPUD_REG { Uint32 all; struct GPFPUD_BITS bit; }; struct GPFINV_BITS { // bits description Uint16 GPIO160:1; // 0 Input inversion control for this pin Uint16 GPIO161:1; // 1 Input inversion control for this pin Uint16 GPIO162:1; // 2 Input inversion control for this pin Uint16 GPIO163:1; // 3 Input inversion control for this pin Uint16 GPIO164:1; // 4 Input inversion control for this pin Uint16 GPIO165:1; // 5 Input inversion control for this pin Uint16 GPIO166:1; // 6 Input inversion control for this pin Uint16 GPIO167:1; // 7 Input inversion control for this pin Uint16 GPIO168:1; // 8 Input inversion control for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFINV_REG { Uint32 all; struct GPFINV_BITS bit; }; struct GPFODR_BITS { // bits description Uint16 GPIO160:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO161:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO162:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO163:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO164:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO165:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO166:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO167:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO168:1; // 8 Outpout Open-Drain control for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFODR_REG { Uint32 all; struct GPFODR_BITS bit; }; struct GPFGMUX1_BITS { // bits description Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 Uint16 rsvd1:2; // 19:18 Reserved Uint16 rsvd2:2; // 21:20 Reserved Uint16 rsvd3:2; // 23:22 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:2; // 27:26 Reserved Uint16 rsvd6:2; // 29:28 Reserved Uint16 rsvd7:2; // 31:30 Reserved }; union GPFGMUX1_REG { Uint32 all; struct GPFGMUX1_BITS bit; }; struct GPFCSEL1_BITS { // bits description Uint16 GPIO160:4; // 3:0 GPIO160 Master CPU Select Uint16 GPIO161:4; // 7:4 GPIO161 Master CPU Select Uint16 GPIO162:4; // 11:8 GPIO162 Master CPU Select Uint16 GPIO163:4; // 15:12 GPIO163 Master CPU Select Uint16 GPIO164:4; // 19:16 GPIO164 Master CPU Select Uint16 GPIO165:4; // 23:20 GPIO165 Master CPU Select Uint16 GPIO166:4; // 27:24 GPIO166 Master CPU Select Uint16 GPIO167:4; // 31:28 GPIO167 Master CPU Select }; union GPFCSEL1_REG { Uint32 all; struct GPFCSEL1_BITS bit; }; struct GPFCSEL2_BITS { // bits description Uint16 GPIO168:4; // 3:0 GPIO168 Master CPU Select Uint16 rsvd1:4; // 7:4 Reserved Uint16 rsvd2:4; // 11:8 Reserved Uint16 rsvd3:4; // 15:12 Reserved Uint16 rsvd4:4; // 19:16 Reserved Uint16 rsvd5:4; // 23:20 Reserved Uint16 rsvd6:4; // 27:24 Reserved Uint16 rsvd7:4; // 31:28 Reserved }; union GPFCSEL2_REG { Uint32 all; struct GPFCSEL2_BITS bit; }; struct GPFLOCK_BITS { // bits description Uint16 GPIO160:1; // 0 Configuration Lock bit for this pin Uint16 GPIO161:1; // 1 Configuration Lock bit for this pin Uint16 GPIO162:1; // 2 Configuration Lock bit for this pin Uint16 GPIO163:1; // 3 Configuration Lock bit for this pin Uint16 GPIO164:1; // 4 Configuration Lock bit for this pin Uint16 GPIO165:1; // 5 Configuration Lock bit for this pin Uint16 GPIO166:1; // 6 Configuration Lock bit for this pin Uint16 GPIO167:1; // 7 Configuration Lock bit for this pin Uint16 GPIO168:1; // 8 Configuration Lock bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFLOCK_REG { Uint32 all; struct GPFLOCK_BITS bit; }; struct GPFCR_BITS { // bits description Uint16 GPIO160:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO161:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO162:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO163:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO164:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO165:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO166:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO167:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO168:1; // 8 Configuration lock commit bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFCR_REG { Uint32 all; struct GPFCR_BITS bit; }; struct GPIO_CTRL_REGS { union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period Control (GPIO0 to 31) union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) union GPAMUX1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) union GPAMUX2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) union GPADIR_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) union GPAPUD_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) Uint16 rsvd1[2]; // Reserved union GPAINV_REG GPAINV; // GPIO A Input Polarity Invert Registers (GPIO0 to 31) union GPAODR_REG GPAODR; // GPIO A Open Drain Output Register (GPIO0 to GPIO31) Uint16 rsvd2[12]; // Reserved union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15) union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31) Uint16 rsvd3[4]; // Reserved union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7) union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15) union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23) union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31) Uint16 rsvd4[12]; // Reserved union GPALOCK_REG GPALOCK; // GPIO A Lock Configuration Register (GPIO0 to 31) union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to 31) union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period Control (GPIO32 to 63) union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) union GPBMUX1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) union GPBMUX2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) union GPBDIR_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) Uint16 rsvd5[2]; // Reserved union GPBINV_REG GPBINV; // GPIO B Input Polarity Invert Registers (GPIO32 to 63) union GPBODR_REG GPBODR; // GPIO B Open Drain Output Register (GPIO32 to GPIO63) union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63) Uint16 rsvd6[10]; // Reserved union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47) union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63) Uint16 rsvd7[4]; // Reserved union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39) union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47) union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55) union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63) Uint16 rsvd8[12]; // Reserved union GPBLOCK_REG GPBLOCK; // GPIO B Lock Configuration Register (GPIO32 to 63) union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to 63) union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 95) union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79) union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80 to 95) union GPCMUX1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) union GPCMUX2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) union GPCDIR_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) union GPCPUD_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) Uint16 rsvd9[2]; // Reserved union GPCINV_REG GPCINV; // GPIO C Input Polarity Invert Registers (GPIO64 to 95) union GPCODR_REG GPCODR; // GPIO C Open Drain Output Register (GPIO64 to GPIO95) Uint16 rsvd10[12]; // Reserved union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79) union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80 to 95) Uint16 rsvd11[4]; // Reserved union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71) union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79) union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80 to 87) union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 95) Uint16 rsvd12[12]; // Reserved union GPCLOCK_REG GPCLOCK; // GPIO C Lock Configuration Register (GPIO64 to 95) union GPCCR_REG GPCCR; // GPIO C Lock Commit Register (GPIO64 to 95) union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO96 to 127) union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO96 to 111) union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register (GPIO112 to 127) union GPDMUX1_REG GPDMUX1; // GPIO D Mux 1 Register (GPIO96 to 111) union GPDMUX2_REG GPDMUX2; // GPIO D Mux 2 Register (GPIO112 to 127) union GPDDIR_REG GPDDIR; // GPIO D Direction Register (GPIO96 to 127) union GPDPUD_REG GPDPUD; // GPIO D Pull Up Disable Register (GPIO96 to 127) Uint16 rsvd13[2]; // Reserved union GPDINV_REG GPDINV; // GPIO D Input Polarity Invert Registers (GPIO96 to 127) union GPDODR_REG GPDODR; // GPIO D Open Drain Output Register (GPIO96 to GPIO127) Uint16 rsvd14[12]; // Reserved union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO96 to 111) union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux (GPIO112 to 127) Uint16 rsvd15[4]; // Reserved union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO96 to 103) union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 111) union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register (GPIO112 to 119) union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register (GPIO120 to 127) Uint16 rsvd16[12]; // Reserved union GPDLOCK_REG GPDLOCK; // GPIO D Lock Configuration Register (GPIO96 to 127) union GPDCR_REG GPDCR; // GPIO D Lock Commit Register (GPIO96 to 127) union GPECTRL_REG GPECTRL; // GPIO E Qualification Sampling Period Control (GPIO128 to 159) union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO128 to 143) union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register (GPIO144 to 159) union GPEMUX1_REG GPEMUX1; // GPIO E Mux 1 Register (GPIO128 to 143) union GPEMUX2_REG GPEMUX2; // GPIO E Mux 2 Register (GPIO144 to 159) union GPEDIR_REG GPEDIR; // GPIO E Direction Register (GPIO128 to 159) union GPEPUD_REG GPEPUD; // GPIO E Pull Up Disable Register (GPIO128 to 159) Uint16 rsvd17[2]; // Reserved union GPEINV_REG GPEINV; // GPIO E Input Polarity Invert Registers (GPIO128 to 159) union GPEODR_REG GPEODR; // GPIO E Open Drain Output Register (GPIO128 to GPIO159) Uint16 rsvd18[12]; // Reserved union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO128 to 143) union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux (GPIO144 to 159) Uint16 rsvd19[4]; // Reserved union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO128 to 135) union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register (GPIO136 to 143) union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register (GPIO144 to 151) union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register (GPIO152 to 159) Uint16 rsvd20[12]; // Reserved union GPELOCK_REG GPELOCK; // GPIO E Lock Configuration Register (GPIO128 to 159) union GPECR_REG GPECR; // GPIO E Lock Commit Register (GPIO128 to 159) union GPFCTRL_REG GPFCTRL; // GPIO F Qualification Sampling Period Control (GPIO160 to 168) union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register (GPIO160 to 168) Uint16 rsvd21[2]; // Reserved union GPFMUX1_REG GPFMUX1; // GPIO F Mux 1 Register (GPIO160 to 168) Uint16 rsvd22[2]; // Reserved union GPFDIR_REG GPFDIR; // GPIO F Direction Register (GPIO160 to 168) union GPFPUD_REG GPFPUD; // GPIO F Pull Up Disable Register (GPIO160 to 168) Uint16 rsvd23[2]; // Reserved union GPFINV_REG GPFINV; // GPIO F Input Polarity Invert Registers (GPIO160 to 168) union GPFODR_REG GPFODR; // GPIO F Open Drain Output Register (GPIO160 to GPIO168) Uint16 rsvd24[12]; // Reserved union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux (GPIO160 to 168) Uint16 rsvd25[6]; // Reserved union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register (GPIO160 to 167) union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register (GPIO168) Uint16 rsvd26[16]; // Reserved union GPFLOCK_REG GPFLOCK; // GPIO F Lock Configuration Register (GPIO160 to 168) union GPFCR_REG GPFCR; // GPIO F Lock Commit Register (GPIO160 to 168) }; struct GPADAT_BITS { // bits description Uint16 GPIO0:1; // 0 Data Register for this pin Uint16 GPIO1:1; // 1 Data Register for this pin Uint16 GPIO2:1; // 2 Data Register for this pin Uint16 GPIO3:1; // 3 Data Register for this pin Uint16 GPIO4:1; // 4 Data Register for this pin Uint16 GPIO5:1; // 5 Data Register for this pin Uint16 GPIO6:1; // 6 Data Register for this pin Uint16 GPIO7:1; // 7 Data Register for this pin Uint16 GPIO8:1; // 8 Data Register for this pin Uint16 GPIO9:1; // 9 Data Register for this pin Uint16 GPIO10:1; // 10 Data Register for this pin Uint16 GPIO11:1; // 11 Data Register for this pin Uint16 GPIO12:1; // 12 Data Register for this pin Uint16 GPIO13:1; // 13 Data Register for this pin Uint16 GPIO14:1; // 14 Data Register for this pin Uint16 GPIO15:1; // 15 Data Register for this pin Uint16 GPIO16:1; // 16 Data Register for this pin Uint16 GPIO17:1; // 17 Data Register for this pin Uint16 GPIO18:1; // 18 Data Register for this pin Uint16 GPIO19:1; // 19 Data Register for this pin Uint16 GPIO20:1; // 20 Data Register for this pin Uint16 GPIO21:1; // 21 Data Register for this pin Uint16 GPIO22:1; // 22 Data Register for this pin Uint16 GPIO23:1; // 23 Data Register for this pin Uint16 GPIO24:1; // 24 Data Register for this pin Uint16 GPIO25:1; // 25 Data Register for this pin Uint16 GPIO26:1; // 26 Data Register for this pin Uint16 GPIO27:1; // 27 Data Register for this pin Uint16 GPIO28:1; // 28 Data Register for this pin Uint16 GPIO29:1; // 29 Data Register for this pin Uint16 GPIO30:1; // 30 Data Register for this pin Uint16 GPIO31:1; // 31 Data Register for this pin }; union GPADAT_REG { Uint32 all; struct GPADAT_BITS bit; }; struct GPASET_BITS { // bits description Uint16 GPIO0:1; // 0 Output Set bit for this pin Uint16 GPIO1:1; // 1 Output Set bit for this pin Uint16 GPIO2:1; // 2 Output Set bit for this pin Uint16 GPIO3:1; // 3 Output Set bit for this pin Uint16 GPIO4:1; // 4 Output Set bit for this pin Uint16 GPIO5:1; // 5 Output Set bit for this pin Uint16 GPIO6:1; // 6 Output Set bit for this pin Uint16 GPIO7:1; // 7 Output Set bit for this pin Uint16 GPIO8:1; // 8 Output Set bit for this pin Uint16 GPIO9:1; // 9 Output Set bit for this pin Uint16 GPIO10:1; // 10 Output Set bit for this pin Uint16 GPIO11:1; // 11 Output Set bit for this pin Uint16 GPIO12:1; // 12 Output Set bit for this pin Uint16 GPIO13:1; // 13 Output Set bit for this pin Uint16 GPIO14:1; // 14 Output Set bit for this pin Uint16 GPIO15:1; // 15 Output Set bit for this pin Uint16 GPIO16:1; // 16 Output Set bit for this pin Uint16 GPIO17:1; // 17 Output Set bit for this pin Uint16 GPIO18:1; // 18 Output Set bit for this pin Uint16 GPIO19:1; // 19 Output Set bit for this pin Uint16 GPIO20:1; // 20 Output Set bit for this pin Uint16 GPIO21:1; // 21 Output Set bit for this pin Uint16 GPIO22:1; // 22 Output Set bit for this pin Uint16 GPIO23:1; // 23 Output Set bit for this pin Uint16 GPIO24:1; // 24 Output Set bit for this pin Uint16 GPIO25:1; // 25 Output Set bit for this pin Uint16 GPIO26:1; // 26 Output Set bit for this pin Uint16 GPIO27:1; // 27 Output Set bit for this pin Uint16 GPIO28:1; // 28 Output Set bit for this pin Uint16 GPIO29:1; // 29 Output Set bit for this pin Uint16 GPIO30:1; // 30 Output Set bit for this pin Uint16 GPIO31:1; // 31 Output Set bit for this pin }; union GPASET_REG { Uint32 all; struct GPASET_BITS bit; }; struct GPACLEAR_BITS { // bits description Uint16 GPIO0:1; // 0 Output Clear bit for this pin Uint16 GPIO1:1; // 1 Output Clear bit for this pin Uint16 GPIO2:1; // 2 Output Clear bit for this pin Uint16 GPIO3:1; // 3 Output Clear bit for this pin Uint16 GPIO4:1; // 4 Output Clear bit for this pin Uint16 GPIO5:1; // 5 Output Clear bit for this pin Uint16 GPIO6:1; // 6 Output Clear bit for this pin Uint16 GPIO7:1; // 7 Output Clear bit for this pin Uint16 GPIO8:1; // 8 Output Clear bit for this pin Uint16 GPIO9:1; // 9 Output Clear bit for this pin Uint16 GPIO10:1; // 10 Output Clear bit for this pin Uint16 GPIO11:1; // 11 Output Clear bit for this pin Uint16 GPIO12:1; // 12 Output Clear bit for this pin Uint16 GPIO13:1; // 13 Output Clear bit for this pin Uint16 GPIO14:1; // 14 Output Clear bit for this pin Uint16 GPIO15:1; // 15 Output Clear bit for this pin Uint16 GPIO16:1; // 16 Output Clear bit for this pin Uint16 GPIO17:1; // 17 Output Clear bit for this pin Uint16 GPIO18:1; // 18 Output Clear bit for this pin Uint16 GPIO19:1; // 19 Output Clear bit for this pin Uint16 GPIO20:1; // 20 Output Clear bit for this pin Uint16 GPIO21:1; // 21 Output Clear bit for this pin Uint16 GPIO22:1; // 22 Output Clear bit for this pin Uint16 GPIO23:1; // 23 Output Clear bit for this pin Uint16 GPIO24:1; // 24 Output Clear bit for this pin Uint16 GPIO25:1; // 25 Output Clear bit for this pin Uint16 GPIO26:1; // 26 Output Clear bit for this pin Uint16 GPIO27:1; // 27 Output Clear bit for this pin Uint16 GPIO28:1; // 28 Output Clear bit for this pin Uint16 GPIO29:1; // 29 Output Clear bit for this pin Uint16 GPIO30:1; // 30 Output Clear bit for this pin Uint16 GPIO31:1; // 31 Output Clear bit for this pin }; union GPACLEAR_REG { Uint32 all; struct GPACLEAR_BITS bit; }; struct GPATOGGLE_BITS { // bits description Uint16 GPIO0:1; // 0 Output Toggle bit for this pin Uint16 GPIO1:1; // 1 Output Toggle bit for this pin Uint16 GPIO2:1; // 2 Output Toggle bit for this pin Uint16 GPIO3:1; // 3 Output Toggle bit for this pin Uint16 GPIO4:1; // 4 Output Toggle bit for this pin Uint16 GPIO5:1; // 5 Output Toggle bit for this pin Uint16 GPIO6:1; // 6 Output Toggle bit for this pin Uint16 GPIO7:1; // 7 Output Toggle bit for this pin Uint16 GPIO8:1; // 8 Output Toggle bit for this pin Uint16 GPIO9:1; // 9 Output Toggle bit for this pin Uint16 GPIO10:1; // 10 Output Toggle bit for this pin Uint16 GPIO11:1; // 11 Output Toggle bit for this pin Uint16 GPIO12:1; // 12 Output Toggle bit for this pin Uint16 GPIO13:1; // 13 Output Toggle bit for this pin Uint16 GPIO14:1; // 14 Output Toggle bit for this pin Uint16 GPIO15:1; // 15 Output Toggle bit for this pin Uint16 GPIO16:1; // 16 Output Toggle bit for this pin Uint16 GPIO17:1; // 17 Output Toggle bit for this pin Uint16 GPIO18:1; // 18 Output Toggle bit for this pin Uint16 GPIO19:1; // 19 Output Toggle bit for this pin Uint16 GPIO20:1; // 20 Output Toggle bit for this pin Uint16 GPIO21:1; // 21 Output Toggle bit for this pin Uint16 GPIO22:1; // 22 Output Toggle bit for this pin Uint16 GPIO23:1; // 23 Output Toggle bit for this pin Uint16 GPIO24:1; // 24 Output Toggle bit for this pin Uint16 GPIO25:1; // 25 Output Toggle bit for this pin Uint16 GPIO26:1; // 26 Output Toggle bit for this pin Uint16 GPIO27:1; // 27 Output Toggle bit for this pin Uint16 GPIO28:1; // 28 Output Toggle bit for this pin Uint16 GPIO29:1; // 29 Output Toggle bit for this pin Uint16 GPIO30:1; // 30 Output Toggle bit for this pin Uint16 GPIO31:1; // 31 Output Toggle bit for this pin }; union GPATOGGLE_REG { Uint32 all; struct GPATOGGLE_BITS bit; }; struct GPBDAT_BITS { // bits description Uint16 GPIO32:1; // 0 Data Register for this pin Uint16 GPIO33:1; // 1 Data Register for this pin Uint16 GPIO34:1; // 2 Data Register for this pin Uint16 GPIO35:1; // 3 Data Register for this pin Uint16 GPIO36:1; // 4 Data Register for this pin Uint16 GPIO37:1; // 5 Data Register for this pin Uint16 GPIO38:1; // 6 Data Register for this pin Uint16 GPIO39:1; // 7 Data Register for this pin Uint16 GPIO40:1; // 8 Data Register for this pin Uint16 GPIO41:1; // 9 Data Register for this pin Uint16 GPIO42:1; // 10 Data Register for this pin Uint16 GPIO43:1; // 11 Data Register for this pin Uint16 GPIO44:1; // 12 Data Register for this pin Uint16 GPIO45:1; // 13 Data Register for this pin Uint16 GPIO46:1; // 14 Data Register for this pin Uint16 GPIO47:1; // 15 Data Register for this pin Uint16 GPIO48:1; // 16 Data Register for this pin Uint16 GPIO49:1; // 17 Data Register for this pin Uint16 GPIO50:1; // 18 Data Register for this pin Uint16 GPIO51:1; // 19 Data Register for this pin Uint16 GPIO52:1; // 20 Data Register for this pin Uint16 GPIO53:1; // 21 Data Register for this pin Uint16 GPIO54:1; // 22 Data Register for this pin Uint16 GPIO55:1; // 23 Data Register for this pin Uint16 GPIO56:1; // 24 Data Register for this pin Uint16 GPIO57:1; // 25 Data Register for this pin Uint16 GPIO58:1; // 26 Data Register for this pin Uint16 GPIO59:1; // 27 Data Register for this pin Uint16 GPIO60:1; // 28 Data Register for this pin Uint16 GPIO61:1; // 29 Data Register for this pin Uint16 GPIO62:1; // 30 Data Register for this pin Uint16 GPIO63:1; // 31 Data Register for this pin }; union GPBDAT_REG { Uint32 all; struct GPBDAT_BITS bit; }; struct GPBSET_BITS { // bits description Uint16 GPIO32:1; // 0 Output Set bit for this pin Uint16 GPIO33:1; // 1 Output Set bit for this pin Uint16 GPIO34:1; // 2 Output Set bit for this pin Uint16 GPIO35:1; // 3 Output Set bit for this pin Uint16 GPIO36:1; // 4 Output Set bit for this pin Uint16 GPIO37:1; // 5 Output Set bit for this pin Uint16 GPIO38:1; // 6 Output Set bit for this pin Uint16 GPIO39:1; // 7 Output Set bit for this pin Uint16 GPIO40:1; // 8 Output Set bit for this pin Uint16 GPIO41:1; // 9 Output Set bit for this pin Uint16 GPIO42:1; // 10 Output Set bit for this pin Uint16 GPIO43:1; // 11 Output Set bit for this pin Uint16 GPIO44:1; // 12 Output Set bit for this pin Uint16 GPIO45:1; // 13 Output Set bit for this pin Uint16 GPIO46:1; // 14 Output Set bit for this pin Uint16 GPIO47:1; // 15 Output Set bit for this pin Uint16 GPIO48:1; // 16 Output Set bit for this pin Uint16 GPIO49:1; // 17 Output Set bit for this pin Uint16 GPIO50:1; // 18 Output Set bit for this pin Uint16 GPIO51:1; // 19 Output Set bit for this pin Uint16 GPIO52:1; // 20 Output Set bit for this pin Uint16 GPIO53:1; // 21 Output Set bit for this pin Uint16 GPIO54:1; // 22 Output Set bit for this pin Uint16 GPIO55:1; // 23 Output Set bit for this pin Uint16 GPIO56:1; // 24 Output Set bit for this pin Uint16 GPIO57:1; // 25 Output Set bit for this pin Uint16 GPIO58:1; // 26 Output Set bit for this pin Uint16 GPIO59:1; // 27 Output Set bit for this pin Uint16 GPIO60:1; // 28 Output Set bit for this pin Uint16 GPIO61:1; // 29 Output Set bit for this pin Uint16 GPIO62:1; // 30 Output Set bit for this pin Uint16 GPIO63:1; // 31 Output Set bit for this pin }; union GPBSET_REG { Uint32 all; struct GPBSET_BITS bit; }; struct GPBCLEAR_BITS { // bits description Uint16 GPIO32:1; // 0 Output Clear bit for this pin Uint16 GPIO33:1; // 1 Output Clear bit for this pin Uint16 GPIO34:1; // 2 Output Clear bit for this pin Uint16 GPIO35:1; // 3 Output Clear bit for this pin Uint16 GPIO36:1; // 4 Output Clear bit for this pin Uint16 GPIO37:1; // 5 Output Clear bit for this pin Uint16 GPIO38:1; // 6 Output Clear bit for this pin Uint16 GPIO39:1; // 7 Output Clear bit for this pin Uint16 GPIO40:1; // 8 Output Clear bit for this pin Uint16 GPIO41:1; // 9 Output Clear bit for this pin Uint16 GPIO42:1; // 10 Output Clear bit for this pin Uint16 GPIO43:1; // 11 Output Clear bit for this pin Uint16 GPIO44:1; // 12 Output Clear bit for this pin Uint16 GPIO45:1; // 13 Output Clear bit for this pin Uint16 GPIO46:1; // 14 Output Clear bit for this pin Uint16 GPIO47:1; // 15 Output Clear bit for this pin Uint16 GPIO48:1; // 16 Output Clear bit for this pin Uint16 GPIO49:1; // 17 Output Clear bit for this pin Uint16 GPIO50:1; // 18 Output Clear bit for this pin Uint16 GPIO51:1; // 19 Output Clear bit for this pin Uint16 GPIO52:1; // 20 Output Clear bit for this pin Uint16 GPIO53:1; // 21 Output Clear bit for this pin Uint16 GPIO54:1; // 22 Output Clear bit for this pin Uint16 GPIO55:1; // 23 Output Clear bit for this pin Uint16 GPIO56:1; // 24 Output Clear bit for this pin Uint16 GPIO57:1; // 25 Output Clear bit for this pin Uint16 GPIO58:1; // 26 Output Clear bit for this pin Uint16 GPIO59:1; // 27 Output Clear bit for this pin Uint16 GPIO60:1; // 28 Output Clear bit for this pin Uint16 GPIO61:1; // 29 Output Clear bit for this pin Uint16 GPIO62:1; // 30 Output Clear bit for this pin Uint16 GPIO63:1; // 31 Output Clear bit for this pin }; union GPBCLEAR_REG { Uint32 all; struct GPBCLEAR_BITS bit; }; struct GPBTOGGLE_BITS { // bits description Uint16 GPIO32:1; // 0 Output Toggle bit for this pin Uint16 GPIO33:1; // 1 Output Toggle bit for this pin Uint16 GPIO34:1; // 2 Output Toggle bit for this pin Uint16 GPIO35:1; // 3 Output Toggle bit for this pin Uint16 GPIO36:1; // 4 Output Toggle bit for this pin Uint16 GPIO37:1; // 5 Output Toggle bit for this pin Uint16 GPIO38:1; // 6 Output Toggle bit for this pin Uint16 GPIO39:1; // 7 Output Toggle bit for this pin Uint16 GPIO40:1; // 8 Output Toggle bit for this pin Uint16 GPIO41:1; // 9 Output Toggle bit for this pin Uint16 GPIO42:1; // 10 Output Toggle bit for this pin Uint16 GPIO43:1; // 11 Output Toggle bit for this pin Uint16 GPIO44:1; // 12 Output Toggle bit for this pin Uint16 GPIO45:1; // 13 Output Toggle bit for this pin Uint16 GPIO46:1; // 14 Output Toggle bit for this pin Uint16 GPIO47:1; // 15 Output Toggle bit for this pin Uint16 GPIO48:1; // 16 Output Toggle bit for this pin Uint16 GPIO49:1; // 17 Output Toggle bit for this pin Uint16 GPIO50:1; // 18 Output Toggle bit for this pin Uint16 GPIO51:1; // 19 Output Toggle bit for this pin Uint16 GPIO52:1; // 20 Output Toggle bit for this pin Uint16 GPIO53:1; // 21 Output Toggle bit for this pin Uint16 GPIO54:1; // 22 Output Toggle bit for this pin Uint16 GPIO55:1; // 23 Output Toggle bit for this pin Uint16 GPIO56:1; // 24 Output Toggle bit for this pin Uint16 GPIO57:1; // 25 Output Toggle bit for this pin Uint16 GPIO58:1; // 26 Output Toggle bit for this pin Uint16 GPIO59:1; // 27 Output Toggle bit for this pin Uint16 GPIO60:1; // 28 Output Toggle bit for this pin Uint16 GPIO61:1; // 29 Output Toggle bit for this pin Uint16 GPIO62:1; // 30 Output Toggle bit for this pin Uint16 GPIO63:1; // 31 Output Toggle bit for this pin }; union GPBTOGGLE_REG { Uint32 all; struct GPBTOGGLE_BITS bit; }; struct GPCDAT_BITS { // bits description Uint16 GPIO64:1; // 0 Data Register for this pin Uint16 GPIO65:1; // 1 Data Register for this pin Uint16 GPIO66:1; // 2 Data Register for this pin Uint16 GPIO67:1; // 3 Data Register for this pin Uint16 GPIO68:1; // 4 Data Register for this pin Uint16 GPIO69:1; // 5 Data Register for this pin Uint16 GPIO70:1; // 6 Data Register for this pin Uint16 GPIO71:1; // 7 Data Register for this pin Uint16 GPIO72:1; // 8 Data Register for this pin Uint16 GPIO73:1; // 9 Data Register for this pin Uint16 GPIO74:1; // 10 Data Register for this pin Uint16 GPIO75:1; // 11 Data Register for this pin Uint16 GPIO76:1; // 12 Data Register for this pin Uint16 GPIO77:1; // 13 Data Register for this pin Uint16 GPIO78:1; // 14 Data Register for this pin Uint16 GPIO79:1; // 15 Data Register for this pin Uint16 GPIO80:1; // 16 Data Register for this pin Uint16 GPIO81:1; // 17 Data Register for this pin Uint16 GPIO82:1; // 18 Data Register for this pin Uint16 GPIO83:1; // 19 Data Register for this pin Uint16 GPIO84:1; // 20 Data Register for this pin Uint16 GPIO85:1; // 21 Data Register for this pin Uint16 GPIO86:1; // 22 Data Register for this pin Uint16 GPIO87:1; // 23 Data Register for this pin Uint16 GPIO88:1; // 24 Data Register for this pin Uint16 GPIO89:1; // 25 Data Register for this pin Uint16 GPIO90:1; // 26 Data Register for this pin Uint16 GPIO91:1; // 27 Data Register for this pin Uint16 GPIO92:1; // 28 Data Register for this pin Uint16 GPIO93:1; // 29 Data Register for this pin Uint16 GPIO94:1; // 30 Data Register for this pin Uint16 GPIO95:1; // 31 Data Register for this pin }; union GPCDAT_REG { Uint32 all; struct GPCDAT_BITS bit; }; struct GPCSET_BITS { // bits description Uint16 GPIO64:1; // 0 Output Set bit for this pin Uint16 GPIO65:1; // 1 Output Set bit for this pin Uint16 GPIO66:1; // 2 Output Set bit for this pin Uint16 GPIO67:1; // 3 Output Set bit for this pin Uint16 GPIO68:1; // 4 Output Set bit for this pin Uint16 GPIO69:1; // 5 Output Set bit for this pin Uint16 GPIO70:1; // 6 Output Set bit for this pin Uint16 GPIO71:1; // 7 Output Set bit for this pin Uint16 GPIO72:1; // 8 Output Set bit for this pin Uint16 GPIO73:1; // 9 Output Set bit for this pin Uint16 GPIO74:1; // 10 Output Set bit for this pin Uint16 GPIO75:1; // 11 Output Set bit for this pin Uint16 GPIO76:1; // 12 Output Set bit for this pin Uint16 GPIO77:1; // 13 Output Set bit for this pin Uint16 GPIO78:1; // 14 Output Set bit for this pin Uint16 GPIO79:1; // 15 Output Set bit for this pin Uint16 GPIO80:1; // 16 Output Set bit for this pin Uint16 GPIO81:1; // 17 Output Set bit for this pin Uint16 GPIO82:1; // 18 Output Set bit for this pin Uint16 GPIO83:1; // 19 Output Set bit for this pin Uint16 GPIO84:1; // 20 Output Set bit for this pin Uint16 GPIO85:1; // 21 Output Set bit for this pin Uint16 GPIO86:1; // 22 Output Set bit for this pin Uint16 GPIO87:1; // 23 Output Set bit for this pin Uint16 GPIO88:1; // 24 Output Set bit for this pin Uint16 GPIO89:1; // 25 Output Set bit for this pin Uint16 GPIO90:1; // 26 Output Set bit for this pin Uint16 GPIO91:1; // 27 Output Set bit for this pin Uint16 GPIO92:1; // 28 Output Set bit for this pin Uint16 GPIO93:1; // 29 Output Set bit for this pin Uint16 GPIO94:1; // 30 Output Set bit for this pin Uint16 GPIO95:1; // 31 Output Set bit for this pin }; union GPCSET_REG { Uint32 all; struct GPCSET_BITS bit; }; struct GPCCLEAR_BITS { // bits description Uint16 GPIO64:1; // 0 Output Clear bit for this pin Uint16 GPIO65:1; // 1 Output Clear bit for this pin Uint16 GPIO66:1; // 2 Output Clear bit for this pin Uint16 GPIO67:1; // 3 Output Clear bit for this pin Uint16 GPIO68:1; // 4 Output Clear bit for this pin Uint16 GPIO69:1; // 5 Output Clear bit for this pin Uint16 GPIO70:1; // 6 Output Clear bit for this pin Uint16 GPIO71:1; // 7 Output Clear bit for this pin Uint16 GPIO72:1; // 8 Output Clear bit for this pin Uint16 GPIO73:1; // 9 Output Clear bit for this pin Uint16 GPIO74:1; // 10 Output Clear bit for this pin Uint16 GPIO75:1; // 11 Output Clear bit for this pin Uint16 GPIO76:1; // 12 Output Clear bit for this pin Uint16 GPIO77:1; // 13 Output Clear bit for this pin Uint16 GPIO78:1; // 14 Output Clear bit for this pin Uint16 GPIO79:1; // 15 Output Clear bit for this pin Uint16 GPIO80:1; // 16 Output Clear bit for this pin Uint16 GPIO81:1; // 17 Output Clear bit for this pin Uint16 GPIO82:1; // 18 Output Clear bit for this pin Uint16 GPIO83:1; // 19 Output Clear bit for this pin Uint16 GPIO84:1; // 20 Output Clear bit for this pin Uint16 GPIO85:1; // 21 Output Clear bit for this pin Uint16 GPIO86:1; // 22 Output Clear bit for this pin Uint16 GPIO87:1; // 23 Output Clear bit for this pin Uint16 GPIO88:1; // 24 Output Clear bit for this pin Uint16 GPIO89:1; // 25 Output Clear bit for this pin Uint16 GPIO90:1; // 26 Output Clear bit for this pin Uint16 GPIO91:1; // 27 Output Clear bit for this pin Uint16 GPIO92:1; // 28 Output Clear bit for this pin Uint16 GPIO93:1; // 29 Output Clear bit for this pin Uint16 GPIO94:1; // 30 Output Clear bit for this pin Uint16 GPIO95:1; // 31 Output Clear bit for this pin }; union GPCCLEAR_REG { Uint32 all; struct GPCCLEAR_BITS bit; }; struct GPCTOGGLE_BITS { // bits description Uint16 GPIO64:1; // 0 Output Toggle bit for this pin Uint16 GPIO65:1; // 1 Output Toggle bit for this pin Uint16 GPIO66:1; // 2 Output Toggle bit for this pin Uint16 GPIO67:1; // 3 Output Toggle bit for this pin Uint16 GPIO68:1; // 4 Output Toggle bit for this pin Uint16 GPIO69:1; // 5 Output Toggle bit for this pin Uint16 GPIO70:1; // 6 Output Toggle bit for this pin Uint16 GPIO71:1; // 7 Output Toggle bit for this pin Uint16 GPIO72:1; // 8 Output Toggle bit for this pin Uint16 GPIO73:1; // 9 Output Toggle bit for this pin Uint16 GPIO74:1; // 10 Output Toggle bit for this pin Uint16 GPIO75:1; // 11 Output Toggle bit for this pin Uint16 GPIO76:1; // 12 Output Toggle bit for this pin Uint16 GPIO77:1; // 13 Output Toggle bit for this pin Uint16 GPIO78:1; // 14 Output Toggle bit for this pin Uint16 GPIO79:1; // 15 Output Toggle bit for this pin Uint16 GPIO80:1; // 16 Output Toggle bit for this pin Uint16 GPIO81:1; // 17 Output Toggle bit for this pin Uint16 GPIO82:1; // 18 Output Toggle bit for this pin Uint16 GPIO83:1; // 19 Output Toggle bit for this pin Uint16 GPIO84:1; // 20 Output Toggle bit for this pin Uint16 GPIO85:1; // 21 Output Toggle bit for this pin Uint16 GPIO86:1; // 22 Output Toggle bit for this pin Uint16 GPIO87:1; // 23 Output Toggle bit for this pin Uint16 GPIO88:1; // 24 Output Toggle bit for this pin Uint16 GPIO89:1; // 25 Output Toggle bit for this pin Uint16 GPIO90:1; // 26 Output Toggle bit for this pin Uint16 GPIO91:1; // 27 Output Toggle bit for this pin Uint16 GPIO92:1; // 28 Output Toggle bit for this pin Uint16 GPIO93:1; // 29 Output Toggle bit for this pin Uint16 GPIO94:1; // 30 Output Toggle bit for this pin Uint16 GPIO95:1; // 31 Output Toggle bit for this pin }; union GPCTOGGLE_REG { Uint32 all; struct GPCTOGGLE_BITS bit; }; struct GPDDAT_BITS { // bits description Uint16 GPIO96:1; // 0 Data Register for this pin Uint16 GPIO97:1; // 1 Data Register for this pin Uint16 GPIO98:1; // 2 Data Register for this pin Uint16 GPIO99:1; // 3 Data Register for this pin Uint16 GPIO100:1; // 4 Data Register for this pin Uint16 GPIO101:1; // 5 Data Register for this pin Uint16 GPIO102:1; // 6 Data Register for this pin Uint16 GPIO103:1; // 7 Data Register for this pin Uint16 GPIO104:1; // 8 Data Register for this pin Uint16 GPIO105:1; // 9 Data Register for this pin Uint16 GPIO106:1; // 10 Data Register for this pin Uint16 GPIO107:1; // 11 Data Register for this pin Uint16 GPIO108:1; // 12 Data Register for this pin Uint16 GPIO109:1; // 13 Data Register for this pin Uint16 GPIO110:1; // 14 Data Register for this pin Uint16 GPIO111:1; // 15 Data Register for this pin Uint16 GPIO112:1; // 16 Data Register for this pin Uint16 GPIO113:1; // 17 Data Register for this pin Uint16 GPIO114:1; // 18 Data Register for this pin Uint16 GPIO115:1; // 19 Data Register for this pin Uint16 GPIO116:1; // 20 Data Register for this pin Uint16 GPIO117:1; // 21 Data Register for this pin Uint16 GPIO118:1; // 22 Data Register for this pin Uint16 GPIO119:1; // 23 Data Register for this pin Uint16 GPIO120:1; // 24 Data Register for this pin Uint16 GPIO121:1; // 25 Data Register for this pin Uint16 GPIO122:1; // 26 Data Register for this pin Uint16 GPIO123:1; // 27 Data Register for this pin Uint16 GPIO124:1; // 28 Data Register for this pin Uint16 GPIO125:1; // 29 Data Register for this pin Uint16 GPIO126:1; // 30 Data Register for this pin Uint16 GPIO127:1; // 31 Data Register for this pin }; union GPDDAT_REG { Uint32 all; struct GPDDAT_BITS bit; }; struct GPDSET_BITS { // bits description Uint16 GPIO96:1; // 0 Output Set bit for this pin Uint16 GPIO97:1; // 1 Output Set bit for this pin Uint16 GPIO98:1; // 2 Output Set bit for this pin Uint16 GPIO99:1; // 3 Output Set bit for this pin Uint16 GPIO100:1; // 4 Output Set bit for this pin Uint16 GPIO101:1; // 5 Output Set bit for this pin Uint16 GPIO102:1; // 6 Output Set bit for this pin Uint16 GPIO103:1; // 7 Output Set bit for this pin Uint16 GPIO104:1; // 8 Output Set bit for this pin Uint16 GPIO105:1; // 9 Output Set bit for this pin Uint16 GPIO106:1; // 10 Output Set bit for this pin Uint16 GPIO107:1; // 11 Output Set bit for this pin Uint16 GPIO108:1; // 12 Output Set bit for this pin Uint16 GPIO109:1; // 13 Output Set bit for this pin Uint16 GPIO110:1; // 14 Output Set bit for this pin Uint16 GPIO111:1; // 15 Output Set bit for this pin Uint16 GPIO112:1; // 16 Output Set bit for this pin Uint16 GPIO113:1; // 17 Output Set bit for this pin Uint16 GPIO114:1; // 18 Output Set bit for this pin Uint16 GPIO115:1; // 19 Output Set bit for this pin Uint16 GPIO116:1; // 20 Output Set bit for this pin Uint16 GPIO117:1; // 21 Output Set bit for this pin Uint16 GPIO118:1; // 22 Output Set bit for this pin Uint16 GPIO119:1; // 23 Output Set bit for this pin Uint16 GPIO120:1; // 24 Output Set bit for this pin Uint16 GPIO121:1; // 25 Output Set bit for this pin Uint16 GPIO122:1; // 26 Output Set bit for this pin Uint16 GPIO123:1; // 27 Output Set bit for this pin Uint16 GPIO124:1; // 28 Output Set bit for this pin Uint16 GPIO125:1; // 29 Output Set bit for this pin Uint16 GPIO126:1; // 30 Output Set bit for this pin Uint16 GPIO127:1; // 31 Output Set bit for this pin }; union GPDSET_REG { Uint32 all; struct GPDSET_BITS bit; }; struct GPDCLEAR_BITS { // bits description Uint16 GPIO96:1; // 0 Output Clear bit for this pin Uint16 GPIO97:1; // 1 Output Clear bit for this pin Uint16 GPIO98:1; // 2 Output Clear bit for this pin Uint16 GPIO99:1; // 3 Output Clear bit for this pin Uint16 GPIO100:1; // 4 Output Clear bit for this pin Uint16 GPIO101:1; // 5 Output Clear bit for this pin Uint16 GPIO102:1; // 6 Output Clear bit for this pin Uint16 GPIO103:1; // 7 Output Clear bit for this pin Uint16 GPIO104:1; // 8 Output Clear bit for this pin Uint16 GPIO105:1; // 9 Output Clear bit for this pin Uint16 GPIO106:1; // 10 Output Clear bit for this pin Uint16 GPIO107:1; // 11 Output Clear bit for this pin Uint16 GPIO108:1; // 12 Output Clear bit for this pin Uint16 GPIO109:1; // 13 Output Clear bit for this pin Uint16 GPIO110:1; // 14 Output Clear bit for this pin Uint16 GPIO111:1; // 15 Output Clear bit for this pin Uint16 GPIO112:1; // 16 Output Clear bit for this pin Uint16 GPIO113:1; // 17 Output Clear bit for this pin Uint16 GPIO114:1; // 18 Output Clear bit for this pin Uint16 GPIO115:1; // 19 Output Clear bit for this pin Uint16 GPIO116:1; // 20 Output Clear bit for this pin Uint16 GPIO117:1; // 21 Output Clear bit for this pin Uint16 GPIO118:1; // 22 Output Clear bit for this pin Uint16 GPIO119:1; // 23 Output Clear bit for this pin Uint16 GPIO120:1; // 24 Output Clear bit for this pin Uint16 GPIO121:1; // 25 Output Clear bit for this pin Uint16 GPIO122:1; // 26 Output Clear bit for this pin Uint16 GPIO123:1; // 27 Output Clear bit for this pin Uint16 GPIO124:1; // 28 Output Clear bit for this pin Uint16 GPIO125:1; // 29 Output Clear bit for this pin Uint16 GPIO126:1; // 30 Output Clear bit for this pin Uint16 GPIO127:1; // 31 Output Clear bit for this pin }; union GPDCLEAR_REG { Uint32 all; struct GPDCLEAR_BITS bit; }; struct GPDTOGGLE_BITS { // bits description Uint16 GPIO96:1; // 0 Output Toggle bit for this pin Uint16 GPIO97:1; // 1 Output Toggle bit for this pin Uint16 GPIO98:1; // 2 Output Toggle bit for this pin Uint16 GPIO99:1; // 3 Output Toggle bit for this pin Uint16 GPIO100:1; // 4 Output Toggle bit for this pin Uint16 GPIO101:1; // 5 Output Toggle bit for this pin Uint16 GPIO102:1; // 6 Output Toggle bit for this pin Uint16 GPIO103:1; // 7 Output Toggle bit for this pin Uint16 GPIO104:1; // 8 Output Toggle bit for this pin Uint16 GPIO105:1; // 9 Output Toggle bit for this pin Uint16 GPIO106:1; // 10 Output Toggle bit for this pin Uint16 GPIO107:1; // 11 Output Toggle bit for this pin Uint16 GPIO108:1; // 12 Output Toggle bit for this pin Uint16 GPIO109:1; // 13 Output Toggle bit for this pin Uint16 GPIO110:1; // 14 Output Toggle bit for this pin Uint16 GPIO111:1; // 15 Output Toggle bit for this pin Uint16 GPIO112:1; // 16 Output Toggle bit for this pin Uint16 GPIO113:1; // 17 Output Toggle bit for this pin Uint16 GPIO114:1; // 18 Output Toggle bit for this pin Uint16 GPIO115:1; // 19 Output Toggle bit for this pin Uint16 GPIO116:1; // 20 Output Toggle bit for this pin Uint16 GPIO117:1; // 21 Output Toggle bit for this pin Uint16 GPIO118:1; // 22 Output Toggle bit for this pin Uint16 GPIO119:1; // 23 Output Toggle bit for this pin Uint16 GPIO120:1; // 24 Output Toggle bit for this pin Uint16 GPIO121:1; // 25 Output Toggle bit for this pin Uint16 GPIO122:1; // 26 Output Toggle bit for this pin Uint16 GPIO123:1; // 27 Output Toggle bit for this pin Uint16 GPIO124:1; // 28 Output Toggle bit for this pin Uint16 GPIO125:1; // 29 Output Toggle bit for this pin Uint16 GPIO126:1; // 30 Output Toggle bit for this pin Uint16 GPIO127:1; // 31 Output Toggle bit for this pin }; union GPDTOGGLE_REG { Uint32 all; struct GPDTOGGLE_BITS bit; }; struct GPEDAT_BITS { // bits description Uint16 GPIO128:1; // 0 Data Register for this pin Uint16 GPIO129:1; // 1 Data Register for this pin Uint16 GPIO130:1; // 2 Data Register for this pin Uint16 GPIO131:1; // 3 Data Register for this pin Uint16 GPIO132:1; // 4 Data Register for this pin Uint16 GPIO133:1; // 5 Data Register for this pin Uint16 GPIO134:1; // 6 Data Register for this pin Uint16 GPIO135:1; // 7 Data Register for this pin Uint16 GPIO136:1; // 8 Data Register for this pin Uint16 GPIO137:1; // 9 Data Register for this pin Uint16 GPIO138:1; // 10 Data Register for this pin Uint16 GPIO139:1; // 11 Data Register for this pin Uint16 GPIO140:1; // 12 Data Register for this pin Uint16 GPIO141:1; // 13 Data Register for this pin Uint16 GPIO142:1; // 14 Data Register for this pin Uint16 GPIO143:1; // 15 Data Register for this pin Uint16 GPIO144:1; // 16 Data Register for this pin Uint16 GPIO145:1; // 17 Data Register for this pin Uint16 GPIO146:1; // 18 Data Register for this pin Uint16 GPIO147:1; // 19 Data Register for this pin Uint16 GPIO148:1; // 20 Data Register for this pin Uint16 GPIO149:1; // 21 Data Register for this pin Uint16 GPIO150:1; // 22 Data Register for this pin Uint16 GPIO151:1; // 23 Data Register for this pin Uint16 GPIO152:1; // 24 Data Register for this pin Uint16 GPIO153:1; // 25 Data Register for this pin Uint16 GPIO154:1; // 26 Data Register for this pin Uint16 GPIO155:1; // 27 Data Register for this pin Uint16 GPIO156:1; // 28 Data Register for this pin Uint16 GPIO157:1; // 29 Data Register for this pin Uint16 GPIO158:1; // 30 Data Register for this pin Uint16 GPIO159:1; // 31 Data Register for this pin }; union GPEDAT_REG { Uint32 all; struct GPEDAT_BITS bit; }; struct GPESET_BITS { // bits description Uint16 GPIO128:1; // 0 Output Set bit for this pin Uint16 GPIO129:1; // 1 Output Set bit for this pin Uint16 GPIO130:1; // 2 Output Set bit for this pin Uint16 GPIO131:1; // 3 Output Set bit for this pin Uint16 GPIO132:1; // 4 Output Set bit for this pin Uint16 GPIO133:1; // 5 Output Set bit for this pin Uint16 GPIO134:1; // 6 Output Set bit for this pin Uint16 GPIO135:1; // 7 Output Set bit for this pin Uint16 GPIO136:1; // 8 Output Set bit for this pin Uint16 GPIO137:1; // 9 Output Set bit for this pin Uint16 GPIO138:1; // 10 Output Set bit for this pin Uint16 GPIO139:1; // 11 Output Set bit for this pin Uint16 GPIO140:1; // 12 Output Set bit for this pin Uint16 GPIO141:1; // 13 Output Set bit for this pin Uint16 GPIO142:1; // 14 Output Set bit for this pin Uint16 GPIO143:1; // 15 Output Set bit for this pin Uint16 GPIO144:1; // 16 Output Set bit for this pin Uint16 GPIO145:1; // 17 Output Set bit for this pin Uint16 GPIO146:1; // 18 Output Set bit for this pin Uint16 GPIO147:1; // 19 Output Set bit for this pin Uint16 GPIO148:1; // 20 Output Set bit for this pin Uint16 GPIO149:1; // 21 Output Set bit for this pin Uint16 GPIO150:1; // 22 Output Set bit for this pin Uint16 GPIO151:1; // 23 Output Set bit for this pin Uint16 GPIO152:1; // 24 Output Set bit for this pin Uint16 GPIO153:1; // 25 Output Set bit for this pin Uint16 GPIO154:1; // 26 Output Set bit for this pin Uint16 GPIO155:1; // 27 Output Set bit for this pin Uint16 GPIO156:1; // 28 Output Set bit for this pin Uint16 GPIO157:1; // 29 Output Set bit for this pin Uint16 GPIO158:1; // 30 Output Set bit for this pin Uint16 GPIO159:1; // 31 Output Set bit for this pin }; union GPESET_REG { Uint32 all; struct GPESET_BITS bit; }; struct GPECLEAR_BITS { // bits description Uint16 GPIO128:1; // 0 Output Clear bit for this pin Uint16 GPIO129:1; // 1 Output Clear bit for this pin Uint16 GPIO130:1; // 2 Output Clear bit for this pin Uint16 GPIO131:1; // 3 Output Clear bit for this pin Uint16 GPIO132:1; // 4 Output Clear bit for this pin Uint16 GPIO133:1; // 5 Output Clear bit for this pin Uint16 GPIO134:1; // 6 Output Clear bit for this pin Uint16 GPIO135:1; // 7 Output Clear bit for this pin Uint16 GPIO136:1; // 8 Output Clear bit for this pin Uint16 GPIO137:1; // 9 Output Clear bit for this pin Uint16 GPIO138:1; // 10 Output Clear bit for this pin Uint16 GPIO139:1; // 11 Output Clear bit for this pin Uint16 GPIO140:1; // 12 Output Clear bit for this pin Uint16 GPIO141:1; // 13 Output Clear bit for this pin Uint16 GPIO142:1; // 14 Output Clear bit for this pin Uint16 GPIO143:1; // 15 Output Clear bit for this pin Uint16 GPIO144:1; // 16 Output Clear bit for this pin Uint16 GPIO145:1; // 17 Output Clear bit for this pin Uint16 GPIO146:1; // 18 Output Clear bit for this pin Uint16 GPIO147:1; // 19 Output Clear bit for this pin Uint16 GPIO148:1; // 20 Output Clear bit for this pin Uint16 GPIO149:1; // 21 Output Clear bit for this pin Uint16 GPIO150:1; // 22 Output Clear bit for this pin Uint16 GPIO151:1; // 23 Output Clear bit for this pin Uint16 GPIO152:1; // 24 Output Clear bit for this pin Uint16 GPIO153:1; // 25 Output Clear bit for this pin Uint16 GPIO154:1; // 26 Output Clear bit for this pin Uint16 GPIO155:1; // 27 Output Clear bit for this pin Uint16 GPIO156:1; // 28 Output Clear bit for this pin Uint16 GPIO157:1; // 29 Output Clear bit for this pin Uint16 GPIO158:1; // 30 Output Clear bit for this pin Uint16 GPIO159:1; // 31 Output Clear bit for this pin }; union GPECLEAR_REG { Uint32 all; struct GPECLEAR_BITS bit; }; struct GPETOGGLE_BITS { // bits description Uint16 GPIO128:1; // 0 Output Toggle bit for this pin Uint16 GPIO129:1; // 1 Output Toggle bit for this pin Uint16 GPIO130:1; // 2 Output Toggle bit for this pin Uint16 GPIO131:1; // 3 Output Toggle bit for this pin Uint16 GPIO132:1; // 4 Output Toggle bit for this pin Uint16 GPIO133:1; // 5 Output Toggle bit for this pin Uint16 GPIO134:1; // 6 Output Toggle bit for this pin Uint16 GPIO135:1; // 7 Output Toggle bit for this pin Uint16 GPIO136:1; // 8 Output Toggle bit for this pin Uint16 GPIO137:1; // 9 Output Toggle bit for this pin Uint16 GPIO138:1; // 10 Output Toggle bit for this pin Uint16 GPIO139:1; // 11 Output Toggle bit for this pin Uint16 GPIO140:1; // 12 Output Toggle bit for this pin Uint16 GPIO141:1; // 13 Output Toggle bit for this pin Uint16 GPIO142:1; // 14 Output Toggle bit for this pin Uint16 GPIO143:1; // 15 Output Toggle bit for this pin Uint16 GPIO144:1; // 16 Output Toggle bit for this pin Uint16 GPIO145:1; // 17 Output Toggle bit for this pin Uint16 GPIO146:1; // 18 Output Toggle bit for this pin Uint16 GPIO147:1; // 19 Output Toggle bit for this pin Uint16 GPIO148:1; // 20 Output Toggle bit for this pin Uint16 GPIO149:1; // 21 Output Toggle bit for this pin Uint16 GPIO150:1; // 22 Output Toggle bit for this pin Uint16 GPIO151:1; // 23 Output Toggle bit for this pin Uint16 GPIO152:1; // 24 Output Toggle bit for this pin Uint16 GPIO153:1; // 25 Output Toggle bit for this pin Uint16 GPIO154:1; // 26 Output Toggle bit for this pin Uint16 GPIO155:1; // 27 Output Toggle bit for this pin Uint16 GPIO156:1; // 28 Output Toggle bit for this pin Uint16 GPIO157:1; // 29 Output Toggle bit for this pin Uint16 GPIO158:1; // 30 Output Toggle bit for this pin Uint16 GPIO159:1; // 31 Output Toggle bit for this pin }; union GPETOGGLE_REG { Uint32 all; struct GPETOGGLE_BITS bit; }; struct GPFDAT_BITS { // bits description Uint16 GPIO160:1; // 0 Data Register for this pin Uint16 GPIO161:1; // 1 Data Register for this pin Uint16 GPIO162:1; // 2 Data Register for this pin Uint16 GPIO163:1; // 3 Data Register for this pin Uint16 GPIO164:1; // 4 Data Register for this pin Uint16 GPIO165:1; // 5 Data Register for this pin Uint16 GPIO166:1; // 6 Data Register for this pin Uint16 GPIO167:1; // 7 Data Register for this pin Uint16 GPIO168:1; // 8 Data Register for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFDAT_REG { Uint32 all; struct GPFDAT_BITS bit; }; struct GPFSET_BITS { // bits description Uint16 GPIO160:1; // 0 Output Set bit for this pin Uint16 GPIO161:1; // 1 Output Set bit for this pin Uint16 GPIO162:1; // 2 Output Set bit for this pin Uint16 GPIO163:1; // 3 Output Set bit for this pin Uint16 GPIO164:1; // 4 Output Set bit for this pin Uint16 GPIO165:1; // 5 Output Set bit for this pin Uint16 GPIO166:1; // 6 Output Set bit for this pin Uint16 GPIO167:1; // 7 Output Set bit for this pin Uint16 GPIO168:1; // 8 Output Set bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFSET_REG { Uint32 all; struct GPFSET_BITS bit; }; struct GPFCLEAR_BITS { // bits description Uint16 GPIO160:1; // 0 Output Clear bit for this pin Uint16 GPIO161:1; // 1 Output Clear bit for this pin Uint16 GPIO162:1; // 2 Output Clear bit for this pin Uint16 GPIO163:1; // 3 Output Clear bit for this pin Uint16 GPIO164:1; // 4 Output Clear bit for this pin Uint16 GPIO165:1; // 5 Output Clear bit for this pin Uint16 GPIO166:1; // 6 Output Clear bit for this pin Uint16 GPIO167:1; // 7 Output Clear bit for this pin Uint16 GPIO168:1; // 8 Output Clear bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFCLEAR_REG { Uint32 all; struct GPFCLEAR_BITS bit; }; struct GPFTOGGLE_BITS { // bits description Uint16 GPIO160:1; // 0 Output Toggle bit for this pin Uint16 GPIO161:1; // 1 Output Toggle bit for this pin Uint16 GPIO162:1; // 2 Output Toggle bit for this pin Uint16 GPIO163:1; // 3 Output Toggle bit for this pin Uint16 GPIO164:1; // 4 Output Toggle bit for this pin Uint16 GPIO165:1; // 5 Output Toggle bit for this pin Uint16 GPIO166:1; // 6 Output Toggle bit for this pin Uint16 GPIO167:1; // 7 Output Toggle bit for this pin Uint16 GPIO168:1; // 8 Output Toggle bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFTOGGLE_REG { Uint32 all; struct GPFTOGGLE_BITS bit; }; struct GPIO_DATA_REGS { union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to 31) union GPASET_REG GPASET; // GPIO A Data Set Register (GPIO0 to 31) union GPACLEAR_REG GPACLEAR; // GPIO A Data Clear Register (GPIO0 to 31) union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31) union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to 63) union GPBSET_REG GPBSET; // GPIO B Data Set Register (GPIO32 to 63) union GPBCLEAR_REG GPBCLEAR; // GPIO B Data Clear Register (GPIO32 to 63) union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63) union GPCDAT_REG GPCDAT; // GPIO C Data Register (GPIO64 to 95) union GPCSET_REG GPCSET; // GPIO C Data Set Register (GPIO64 to 95) union GPCCLEAR_REG GPCCLEAR; // GPIO C Data Clear Register (GPIO64 to 95) union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 95) union GPDDAT_REG GPDDAT; // GPIO D Data Register (GPIO96 to 127) union GPDSET_REG GPDSET; // GPIO D Data Set Register (GPIO96 to 127) union GPDCLEAR_REG GPDCLEAR; // GPIO D Data Clear Register (GPIO96 to 127) union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127) union GPEDAT_REG GPEDAT; // GPIO E Data Register (GPIO128 to 159) union GPESET_REG GPESET; // GPIO E Data Set Register (GPIO128 to 159) union GPECLEAR_REG GPECLEAR; // GPIO E Data Clear Register (GPIO128 to 159) union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO128 to 159) union GPFDAT_REG GPFDAT; // GPIO F Data Register (GPIO160 to 168) union GPFSET_REG GPFSET; // GPIO F Data Set Register (GPIO160 to 168) union GPFCLEAR_REG GPFCLEAR; // GPIO F Data Clear Register (GPIO160 to 168) union GPFTOGGLE_REG GPFTOGGLE; // GPIO F Data Toggle Register (GPIO160 to 168) }; //--------------------------------------------------------------------------- // GPIO External References & Function Declarations: // extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; extern volatile struct GPIO_DATA_REGS GpioDataRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_i2c.h // // TITLE: F2837xD Device I2C Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // I2C Individual Register Bit Definitions: struct I2COAR_BITS { // bits description Uint16 OAR:10; // 9:0 I2C Own address Uint16 rsvd1:6; // 15:10 Reserved }; union I2COAR_REG { Uint16 all; struct I2COAR_BITS bit; }; struct I2CIER_BITS { // bits description Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable Uint16 NACK:1; // 1 No-acknowledgment interrupt enable Uint16 ARDY:1; // 2 Register-access-ready interrupt enable Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable Uint16 SCD:1; // 5 Stop condition detected interrupt enable Uint16 AAS:1; // 6 Addressed as slave interrupt enable Uint16 rsvd1:9; // 15:7 Reserved }; union I2CIER_REG { Uint16 all; struct I2CIER_BITS bit; }; struct I2CSTR_BITS { // bits description Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. Uint16 SCD:1; // 5 Stop condition detected bit. Uint16 rsvd1:2; // 7:6 Reserved Uint16 AD0:1; // 8 Address 0 bits Uint16 AAS:1; // 9 Addressed-as-slave bit Uint16 XSMT:1; // 10 Transmit shift register empty bit. Uint16 RSFULL:1; // 11 Receive shift register full bit. Uint16 BB:1; // 12 Bus busy bit. Uint16 NACKSNT:1; // 13 NACK sent bit. Uint16 SDIR:1; // 14 Slave direction bit Uint16 rsvd2:1; // 15 Reserved }; union I2CSTR_REG { Uint16 all; struct I2CSTR_BITS bit; }; struct I2CDRR_BITS { // bits description Uint16 DATA:8; // 7:0 Receive data Uint16 rsvd1:8; // 15:8 Reserved }; union I2CDRR_REG { Uint16 all; struct I2CDRR_BITS bit; }; struct I2CSAR_BITS { // bits description Uint16 SAR:10; // 9:0 Slave Address Uint16 rsvd1:6; // 15:10 Reserved }; union I2CSAR_REG { Uint16 all; struct I2CSAR_BITS bit; }; struct I2CDXR_BITS { // bits description Uint16 DATA:8; // 7:0 Transmit data Uint16 rsvd1:8; // 15:8 Reserved }; union I2CDXR_REG { Uint16 all; struct I2CDXR_BITS bit; }; struct I2CMDR_BITS { // bits description Uint16 BC:3; // 2:0 Bit count bits. Uint16 FDF:1; // 3 Free Data Format Uint16 STB:1; // 4 START Byte Mode Uint16 IRS:1; // 5 I2C Module Reset Uint16 DLB:1; // 6 Digital Loopback Mode Uint16 RM:1; // 7 Repeat Mode Uint16 XA:1; // 8 Expanded Address Mode Uint16 TRX:1; // 9 Transmitter Mode Uint16 MST:1; // 10 Master Mode Uint16 STP:1; // 11 STOP Condition Uint16 rsvd1:1; // 12 Reserved Uint16 STT:1; // 13 START condition bit Uint16 FREE:1; // 14 Debug Action Uint16 NACKMOD:1; // 15 NACK mode bit }; union I2CMDR_REG { Uint16 all; struct I2CMDR_BITS bit; }; struct I2CISRC_BITS { // bits description Uint16 INTCODE:3; // 2:0 Interrupt code bits. Uint16 rsvd1:5; // 7:3 Reserved Uint16 WRITE_ZEROS:4; // 11:8 Reserved Uint16 rsvd2:4; // 15:12 Reserved }; union I2CISRC_REG { Uint16 all; struct I2CISRC_BITS bit; }; struct I2CEMDR_BITS { // bits description Uint16 BC:1; // 0 Backwards compatibility mode Uint16 rsvd1:15; // 15:1 Reserved }; union I2CEMDR_REG { Uint16 all; struct I2CEMDR_BITS bit; }; struct I2CPSC_BITS { // bits description Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down Uint16 rsvd1:8; // 15:8 Reserved }; union I2CPSC_REG { Uint16 all; struct I2CPSC_BITS bit; }; struct I2CFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag Uint16 TXFFST:5; // 12:8 Transmit FIFO Status Uint16 TXFFRST:1; // 13 Transmit FIFO Reset Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable Uint16 rsvd1:1; // 15 Reserved }; union I2CFFTX_REG { Uint16 all; struct I2CFFTX_BITS bit; }; struct I2CFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag Uint16 RXFFST:5; // 12:8 Receive FIFO Status Uint16 RXFFRST:1; // 13 Receive FIFO Reset Uint16 rsvd1:2; // 15:14 Reserved }; union I2CFFRX_REG { Uint16 all; struct I2CFFRX_BITS bit; }; struct I2C_REGS { union I2COAR_REG I2COAR; // I2C Own address union I2CIER_REG I2CIER; // I2C Interrupt Enable union I2CSTR_REG I2CSTR; // I2C Status Uint16 I2CCLKL; // I2C Clock low-time divider Uint16 I2CCLKH; // I2C Clock high-time divider Uint16 I2CCNT; // I2C Data count union I2CDRR_REG I2CDRR; // I2C Data receive union I2CSAR_REG I2CSAR; // I2C Slave address union I2CDXR_REG I2CDXR; // I2C Data Transmit union I2CMDR_REG I2CMDR; // I2C Mode union I2CISRC_REG I2CISRC; // I2C Interrupt Source union I2CEMDR_REG I2CEMDR; // I2C Extended Mode union I2CPSC_REG I2CPSC; // I2C Prescaler Uint16 rsvd1[19]; // Reserved union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive }; //--------------------------------------------------------------------------- // I2C External References & Function Declarations: // extern volatile struct I2C_REGS I2caRegs; extern volatile struct I2C_REGS I2cbRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_input_xbar.h // // TITLE: F2837xD Device INPUT_XBAR Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // INPUT_XBAR Individual Register Bit Definitions: struct INPUTSELECTLOCK_BITS { // bits description Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register Uint16 rsvd1:16; // 31:16 Reserved }; union INPUTSELECTLOCK_REG { Uint32 all; struct INPUTSELECTLOCK_BITS bit; }; struct INPUT_XBAR_REGS { Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) Uint16 rsvd1[16]; // Reserved union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register }; //--------------------------------------------------------------------------- // INPUT_XBAR External References & Function Declarations: // extern volatile struct INPUT_XBAR_REGS InputXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_ipc.h // // TITLE: F2837xD Device IPC Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // IPC Individual Register Bit Definitions: struct IPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Local IPC Flag 0 Acknowledgement Uint16 IPC1:1; // 1 Local IPC Flag 1 Acknowledgement Uint16 IPC2:1; // 2 Local IPC Flag 2 Acknowledgement Uint16 IPC3:1; // 3 Local IPC Flag 3 Acknowledgement Uint16 IPC4:1; // 4 Local IPC Flag 4 Acknowledgement Uint16 IPC5:1; // 5 Local IPC Flag 5 Acknowledgement Uint16 IPC6:1; // 6 Local IPC Flag 6 Acknowledgement Uint16 IPC7:1; // 7 Local IPC Flag 7 Acknowledgement Uint16 IPC8:1; // 8 Local IPC Flag 8 Acknowledgement Uint16 IPC9:1; // 9 Local IPC Flag 9 Acknowledgement Uint16 IPC10:1; // 10 Local IPC Flag 10 Acknowledgement Uint16 IPC11:1; // 11 Local IPC Flag 11 Acknowledgement Uint16 IPC12:1; // 12 Local IPC Flag 12 Acknowledgement Uint16 IPC13:1; // 13 Local IPC Flag 13 Acknowledgement Uint16 IPC14:1; // 14 Local IPC Flag 14 Acknowledgement Uint16 IPC15:1; // 15 Local IPC Flag 15 Acknowledgement Uint16 IPC16:1; // 16 Local IPC Flag 16 Acknowledgement Uint16 IPC17:1; // 17 Local IPC Flag 17 Acknowledgement Uint16 IPC18:1; // 18 Local IPC Flag 18 Acknowledgement Uint16 IPC19:1; // 19 Local IPC Flag 19 Acknowledgement Uint16 IPC20:1; // 20 Local IPC Flag 20 Acknowledgement Uint16 IPC21:1; // 21 Local IPC Flag 21 Acknowledgement Uint16 IPC22:1; // 22 Local IPC Flag 22 Acknowledgement Uint16 IPC23:1; // 23 Local IPC Flag 23 Acknowledgement Uint16 IPC24:1; // 24 Local IPC Flag 24 Acknowledgement Uint16 IPC25:1; // 25 Local IPC Flag 25 Acknowledgement Uint16 IPC26:1; // 26 Local IPC Flag 26 Acknowledgement Uint16 IPC27:1; // 27 Local IPC Flag 27 Acknowledgement Uint16 IPC28:1; // 28 Local IPC Flag 28 Acknowledgement Uint16 IPC29:1; // 29 Local IPC Flag 29 Acknowledgement Uint16 IPC30:1; // 30 Local IPC Flag 30 Acknowledgement Uint16 IPC31:1; // 31 Local IPC Flag 31 Acknowledgement }; union IPCACK_REG { Uint32 all; struct IPCACK_BITS bit; }; struct IPCSTS_BITS { // bits description Uint16 IPC0:1; // 0 Local IPC Flag 0 Status Uint16 IPC1:1; // 1 Local IPC Flag 1 Status Uint16 IPC2:1; // 2 Local IPC Flag 2 Status Uint16 IPC3:1; // 3 Local IPC Flag 3 Status Uint16 IPC4:1; // 4 Local IPC Flag 4 Status Uint16 IPC5:1; // 5 Local IPC Flag 5 Status Uint16 IPC6:1; // 6 Local IPC Flag 6 Status Uint16 IPC7:1; // 7 Local IPC Flag 7 Status Uint16 IPC8:1; // 8 Local IPC Flag 8 Status Uint16 IPC9:1; // 9 Local IPC Flag 9 Status Uint16 IPC10:1; // 10 Local IPC Flag 10 Status Uint16 IPC11:1; // 11 Local IPC Flag 11 Status Uint16 IPC12:1; // 12 Local IPC Flag 12 Status Uint16 IPC13:1; // 13 Local IPC Flag 13 Status Uint16 IPC14:1; // 14 Local IPC Flag 14 Status Uint16 IPC15:1; // 15 Local IPC Flag 15 Status Uint16 IPC16:1; // 16 Local IPC Flag 16 Status Uint16 IPC17:1; // 17 Local IPC Flag 17 Status Uint16 IPC18:1; // 18 Local IPC Flag 18 Status Uint16 IPC19:1; // 19 Local IPC Flag 19 Status Uint16 IPC20:1; // 20 Local IPC Flag 20 Status Uint16 IPC21:1; // 21 Local IPC Flag 21 Status Uint16 IPC22:1; // 22 Local IPC Flag 22 Status Uint16 IPC23:1; // 23 Local IPC Flag 23 Status Uint16 IPC24:1; // 24 Local IPC Flag 24 Status Uint16 IPC25:1; // 25 Local IPC Flag 25 Status Uint16 IPC26:1; // 26 Local IPC Flag 26 Status Uint16 IPC27:1; // 27 Local IPC Flag 27 Status Uint16 IPC28:1; // 28 Local IPC Flag 28 Status Uint16 IPC29:1; // 29 Local IPC Flag 29 Status Uint16 IPC30:1; // 30 Local IPC Flag 30 Status Uint16 IPC31:1; // 31 Local IPC Flag 31 Status }; union IPCSTS_REG { Uint32 all; struct IPCSTS_BITS bit; }; struct IPCSET_BITS { // bits description Uint16 IPC0:1; // 0 Set Remote IPC0 Flag Uint16 IPC1:1; // 1 Set Remote IPC1 Flag Uint16 IPC2:1; // 2 Set Remote IPC2 Flag Uint16 IPC3:1; // 3 Set Remote IPC3 Flag Uint16 IPC4:1; // 4 Set Remote IPC4 Flag Uint16 IPC5:1; // 5 Set Remote IPC5 Flag Uint16 IPC6:1; // 6 Set Remote IPC6 Flag Uint16 IPC7:1; // 7 Set Remote IPC7 Flag Uint16 IPC8:1; // 8 Set Remote IPC8 Flag Uint16 IPC9:1; // 9 Set Remote IPC9 Flag Uint16 IPC10:1; // 10 Set Remote IPC10 Flag Uint16 IPC11:1; // 11 Set Remote IPC11 Flag Uint16 IPC12:1; // 12 Set Remote IPC12 Flag Uint16 IPC13:1; // 13 Set Remote IPC13 Flag Uint16 IPC14:1; // 14 Set Remote IPC14 Flag Uint16 IPC15:1; // 15 Set Remote IPC15 Flag Uint16 IPC16:1; // 16 Set Remote IPC16 Flag Uint16 IPC17:1; // 17 Set Remote IPC17 Flag Uint16 IPC18:1; // 18 Set Remote IPC18 Flag Uint16 IPC19:1; // 19 Set Remote IPC19 Flag Uint16 IPC20:1; // 20 Set Remote IPC20 Flag Uint16 IPC21:1; // 21 Set Remote IPC21 Flag Uint16 IPC22:1; // 22 Set Remote IPC22 Flag Uint16 IPC23:1; // 23 Set Remote IPC23 Flag Uint16 IPC24:1; // 24 Set Remote IPC24 Flag Uint16 IPC25:1; // 25 Set Remote IPC25 Flag Uint16 IPC26:1; // 26 Set Remote IPC26 Flag Uint16 IPC27:1; // 27 Set Remote IPC27 Flag Uint16 IPC28:1; // 28 Set Remote IPC28 Flag Uint16 IPC29:1; // 29 Set Remote IPC29 Flag Uint16 IPC30:1; // 30 Set Remote IPC30 Flag Uint16 IPC31:1; // 31 Set Remote IPC31 Flag }; union IPCSET_REG { Uint32 all; struct IPCSET_BITS bit; }; struct IPCCLR_BITS { // bits description Uint16 IPC0:1; // 0 Clear Remote IPC0 Flag Uint16 IPC1:1; // 1 Clear Remote IPC1 Flag Uint16 IPC2:1; // 2 Clear Remote IPC2 Flag Uint16 IPC3:1; // 3 Clear Remote IPC3 Flag Uint16 IPC4:1; // 4 Clear Remote IPC4 Flag Uint16 IPC5:1; // 5 Clear Remote IPC5 Flag Uint16 IPC6:1; // 6 Clear Remote IPC6 Flag Uint16 IPC7:1; // 7 Clear Remote IPC7 Flag Uint16 IPC8:1; // 8 Clear Remote IPC8 Flag Uint16 IPC9:1; // 9 Clear Remote IPC9 Flag Uint16 IPC10:1; // 10 Clear Remote IPC10 Flag Uint16 IPC11:1; // 11 Clear Remote IPC11 Flag Uint16 IPC12:1; // 12 Clear Remote IPC12 Flag Uint16 IPC13:1; // 13 Clear Remote IPC13 Flag Uint16 IPC14:1; // 14 Clear Remote IPC14 Flag Uint16 IPC15:1; // 15 Clear Remote IPC15 Flag Uint16 IPC16:1; // 16 Clear Remote IPC16 Flag Uint16 IPC17:1; // 17 Clear Remote IPC17 Flag Uint16 IPC18:1; // 18 Clear Remote IPC18 Flag Uint16 IPC19:1; // 19 Clear Remote IPC19 Flag Uint16 IPC20:1; // 20 Clear Remote IPC20 Flag Uint16 IPC21:1; // 21 Clear Remote IPC21 Flag Uint16 IPC22:1; // 22 Clear Remote IPC22 Flag Uint16 IPC23:1; // 23 Clear Remote IPC23 Flag Uint16 IPC24:1; // 24 Clear Remote IPC24 Flag Uint16 IPC25:1; // 25 Clear Remote IPC25 Flag Uint16 IPC26:1; // 26 Clear Remote IPC26 Flag Uint16 IPC27:1; // 27 Clear Remote IPC27 Flag Uint16 IPC28:1; // 28 Clear Remote IPC28 Flag Uint16 IPC29:1; // 29 Clear Remote IPC29 Flag Uint16 IPC30:1; // 30 Clear Remote IPC30 Flag Uint16 IPC31:1; // 31 Clear Remote IPC31 Flag }; union IPCCLR_REG { Uint32 all; struct IPCCLR_BITS bit; }; struct IPCFLG_BITS { // bits description Uint16 IPC0:1; // 0 Remote IPC0 Flag Status Uint16 IPC1:1; // 1 Remote IPC1 Flag Status Uint16 IPC2:1; // 2 Remote IPC2 Flag Status Uint16 IPC3:1; // 3 Remote IPC3 Flag Status Uint16 IPC4:1; // 4 Remote IPC4 Flag Status Uint16 IPC5:1; // 5 Remote IPC5 Flag Status Uint16 IPC6:1; // 6 Remote IPC6 Flag Status Uint16 IPC7:1; // 7 Remote IPC7 Flag Status Uint16 IPC8:1; // 8 Remote IPC8 Flag Status Uint16 IPC9:1; // 9 Remote IPC9 Flag Status Uint16 IPC10:1; // 10 Remote IPC10 Flag Status Uint16 IPC11:1; // 11 Remote IPC11 Flag Status Uint16 IPC12:1; // 12 Remote IPC12 Flag Status Uint16 IPC13:1; // 13 Remote IPC13 Flag Status Uint16 IPC14:1; // 14 Remote IPC14 Flag Status Uint16 IPC15:1; // 15 Remote IPC15 Flag Status Uint16 IPC16:1; // 16 Remote IPC16 Flag Status Uint16 IPC17:1; // 17 Remote IPC17 Flag Status Uint16 IPC18:1; // 18 Remote IPC18 Flag Status Uint16 IPC19:1; // 19 Remote IPC19 Flag Status Uint16 IPC20:1; // 20 Remote IPC20 Flag Status Uint16 IPC21:1; // 21 Remote IPC21 Flag Status Uint16 IPC22:1; // 22 Remote IPC22 Flag Status Uint16 IPC23:1; // 23 Remote IPC23 Flag Status Uint16 IPC24:1; // 24 Remote IPC24 Flag Status Uint16 IPC25:1; // 25 Remote IPC25 Flag Status Uint16 IPC26:1; // 26 Remote IPC26 Flag Status Uint16 IPC27:1; // 27 Remote IPC27 Flag Status Uint16 IPC28:1; // 28 Remote IPC28 Flag Status Uint16 IPC29:1; // 29 Remote IPC29 Flag Status Uint16 IPC30:1; // 30 Remote IPC30 Flag Status Uint16 IPC31:1; // 31 Remote IPC31 Flag Status }; union IPCFLG_REG { Uint32 all; struct IPCFLG_BITS bit; }; struct IPC_REGS_CPU1 { union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register union IPCSTS_REG IPCSTS; // IPC incoming flag status register union IPCSET_REG IPCSET; // IPC remote flag set register union IPCCLR_REG IPCCLR; // IPC remote flag clear register union IPCFLG_REG IPCFLG; // IPC remote flag status register Uint16 rsvd1[2]; // Reserved Uint32 IPCCOUNTERL; // IPC Counter Low Register Uint32 IPCCOUNTERH; // IPC Counter High Register Uint32 IPCSENDCOM; // Local to Remote IPC Command Register Uint32 IPCSENDADDR; // Local to Remote IPC Address Register Uint32 IPCSENDDATA; // Local to Remote IPC Data Register Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register Uint32 IPCRECVCOM; // Remote to Local IPC Command Register Uint32 IPCRECVADDR; // Remote to Local IPC Address Register Uint32 IPCRECVDATA; // Remote to Local IPC Data Register Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register }; struct IPC_REGS_CPU2 { union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register union IPCSTS_REG IPCSTS; // IPC incoming flag status register union IPCSET_REG IPCSET; // IPC remote flag set register union IPCCLR_REG IPCCLR; // IPC remote flag clear register union IPCFLG_REG IPCFLG; // IPC remote flag status register Uint16 rsvd1[2]; // Reserved Uint32 IPCCOUNTERL; // IPC Counter Low Register Uint32 IPCCOUNTERH; // IPC Counter High Register Uint32 IPCRECVCOM; // Remote to Local IPC Command Register Uint32 IPCRECVADDR; // Remote to Local IPC Address Register Uint32 IPCRECVDATA; // Remote to Local IPC Data Register Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register Uint32 IPCSENDCOM; // Local to Remote IPC Command Register Uint32 IPCSENDADDR; // Local to Remote IPC Address Register Uint32 IPCSENDDATA; // Local to Remote IPC Data Register Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register }; //--------------------------------------------------------------------------- // IPC External References & Function Declarations: // extern volatile struct IPC_REGS_CPU1 IpcRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_mcbsp.h // // TITLE: F2837xD Device MCBSP Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // MCBSP Individual Register Bit Definitions: struct DRR2_BITS { // bits description Uint16 HWLB:8; // 7:0 High word low byte Uint16 HWHB:8; // 15:8 High word high byte }; union DRR2_REG { Uint16 all; struct DRR2_BITS bit; }; struct DRR1_BITS { // bits description Uint16 LWLB:8; // 7:0 Low word low byte Uint16 LWHB:8; // 15:8 Low word high byte }; union DRR1_REG { Uint16 all; struct DRR1_BITS bit; }; struct DXR2_BITS { // bits description Uint16 HWLB:8; // 7:0 High word low byte Uint16 HWHB:8; // 15:8 High word high byte }; union DXR2_REG { Uint16 all; struct DXR2_BITS bit; }; struct DXR1_BITS { // bits description Uint16 LWLB:8; // 7:0 Low word low byte Uint16 LWHB:8; // 15:8 Low word high byte }; union DXR1_REG { Uint16 all; struct DXR1_BITS bit; }; struct SPCR2_BITS { // bits description Uint16 XRST:1; // 0 Transmitter reset Uint16 XRDY:1; // 1 Transmitter ready Uint16 XEMPTY:1; // 2 Transmitter empty Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits Uint16 GRST:1; // 6 Sample rate generator reset Uint16 FRST:1; // 7 Frame sync logic reset Uint16 SOFT:1; // 8 SOFT bit Uint16 FREE:1; // 9 FREE bit Uint16 rsvd1:6; // 15:10 Reserved }; union SPCR2_REG { Uint16 all; struct SPCR2_BITS bit; }; struct SPCR1_BITS { // bits description Uint16 RRST:1; // 0 Receiver reset Uint16 RRDY:1; // 1 Receiver ready Uint16 RFULL:1; // 2 Receiver full Uint16 RSYNCERR:1; // 3 Receive sync error INT flag Uint16 RINTM:2; // 5:4 Receive Interupt mode bits Uint16 rsvd1:1; // 6 Reserved Uint16 DXENA:1; // 7 DX delay enable Uint16 rsvd2:3; // 10:8 Reserved Uint16 CLKSTP:2; // 12:11 Clock stop mode Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode Uint16 DLB:1; // 15 Digital loopback }; union SPCR1_REG { Uint16 all; struct SPCR1_BITS bit; }; struct RCR2_BITS { // bits description Uint16 RDATDLY:2; // 1:0 Receive data delay Uint16 RFIG:1; // 2 Receive frame sync ignore Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects Uint16 RWDLEN2:3; // 7:5 Receive word length 2 Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 Uint16 RPHASE:1; // 15 Receive Phase }; union RCR2_REG { Uint16 all; struct RCR2_BITS bit; }; struct RCR1_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 RWDLEN1:3; // 7:5 Receive word length 1 Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 Uint16 rsvd2:1; // 15 Reserved }; union RCR1_REG { Uint16 all; struct RCR1_BITS bit; }; struct XCR2_BITS { // bits description Uint16 XDATDLY:2; // 1:0 Transmit data delay Uint16 XFIG:1; // 2 Transmit frame sync ignore Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 Uint16 XPHASE:1; // 15 Transmit Phase }; union XCR2_REG { Uint16 all; struct XCR2_BITS bit; }; struct XCR1_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 Uint16 rsvd2:1; // 15 Reserved }; union XCR1_REG { Uint16 all; struct XCR1_BITS bit; }; struct SRGR2_BITS { // bits description Uint16 FPER:12; // 11:0 Frame-sync period Uint16 FSGM:1; // 12 Frame sync generator mode Uint16 CLKSM:1; // 13 Sample rate generator mode Uint16 rsvd1:1; // 14 Reserved Uint16 GSYNC:1; // 15 CLKG sync }; union SRGR2_REG { Uint16 all; struct SRGR2_BITS bit; }; struct SRGR1_BITS { // bits description Uint16 CLKGDV:8; // 7:0 CLKG divider Uint16 FWID:8; // 15:8 Frame width }; union SRGR1_REG { Uint16 all; struct SRGR1_BITS bit; }; struct MCR2_BITS { // bits description Uint16 XMCM:2; // 1:0 Transmit data delay Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects Uint16 XPBBLK:2; // 8:7 Transmit word length 2 Uint16 XMCME:1; // 9 Transmit Frame length 2 Uint16 rsvd1:6; // 15:10 Reserved }; union MCR2_REG { Uint16 all; struct MCR2_BITS bit; }; struct MCR1_BITS { // bits description Uint16 RMCM:1; // 0 Receive multichannel mode Uint16 rsvd1:1; // 1 Reserved Uint16 RCBLK:3; // 4:2 eceive current block Uint16 RPABLK:2; // 6:5 Receive partition A Block Uint16 RPBBLK:2; // 8:7 Receive partition B Block Uint16 RMCME:1; // 9 Receive multi-channel enhance mode Uint16 rsvd2:6; // 15:10 Reserved }; union MCR1_REG { Uint16 all; struct MCR1_BITS bit; }; struct PCR_BITS { // bits description Uint16 CLKRP:1; // 0 Receive Clock polarity Uint16 CLKXP:1; // 1 Transmit clock polarity Uint16 FSRP:1; // 2 Receive Frame synchronization polarity Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 SCLKME:1; // 7 Sample clock mode selection Uint16 CLKRM:1; // 8 Receiver Clock Mode Uint16 CLKXM:1; // 9 Transmit Clock Mode. Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode Uint16 rsvd4:4; // 15:12 Reserved }; union PCR_REG { Uint16 all; struct PCR_BITS bit; }; struct MFFINT_BITS { // bits description Uint16 XINT:1; // 0 Enable for Receive Interrupt Uint16 rsvd1:1; // 1 Reserved Uint16 RINT:1; // 2 Enable for transmit Interrupt Uint16 rsvd2:13; // 15:3 Reserved }; union MFFINT_REG { Uint16 all; struct MFFINT_BITS bit; }; struct McBSP_REGS { union DRR2_REG DRR2; // Data receive register bits 31-16 union DRR1_REG DRR1; // Data receive register bits 15-0 union DXR2_REG DXR2; // Data transmit register bits 31-16 union DXR1_REG DXR1; // Data transmit register bits 15-0 union SPCR2_REG SPCR2; // Control register 2 union SPCR1_REG SPCR1; // Control register 1 union RCR2_REG RCR2; // Receive Control register 2 union RCR1_REG RCR1; // Receive Control register 1 union XCR2_REG XCR2; // Transmit Control register 2 union XCR1_REG XCR1; // Transmit Control register 1 union SRGR2_REG SRGR2; // Sample rate generator register 2 union SRGR1_REG SRGR1; // Sample rate generator register 1 union MCR2_REG MCR2; // Multi-channel register 2 union MCR1_REG MCR1; // Multi-channel register 1 Uint16 RCERA; // Receive channel enable partition A Uint16 RCERB; // Receive channel enable partition B Uint16 XCERA; // Transmit channel enable partition A Uint16 XCERB; // Transmit channel enable partition B union PCR_REG PCR; // Pin Control register Uint16 RCERC; // Receive channel enable partition C Uint16 RCERD; // Receive channel enable partition D Uint16 XCERC; // Transmit channel enable partition C Uint16 XCERD; // Transmit channel enable partition D Uint16 RCERE; // Receive channel enable partition E Uint16 RCERF; // Receive channel enable partition F Uint16 XCERE; // Transmit channel enable partition E Uint16 XCERF; // Transmit channel enable partition F Uint16 RCERG; // Receive channel enable partition G Uint16 RCERH; // Receive channel enable partition H Uint16 XCERG; // Transmit channel enable partition G Uint16 XCERH; // Transmit channel enable partition H Uint16 rsvd1[4]; // Reserved union MFFINT_REG MFFINT; // Interrupt enable }; //--------------------------------------------------------------------------- // MCBSP External References & Function Declarations: // extern volatile struct McBSP_REGS McbspaRegs; extern volatile struct McBSP_REGS McbspbRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_memconfig.h // // TITLE: F2837xD Device MEMCONFIG Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // MEMCONFIG Individual Register Bit Definitions: struct DxLOCK_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 LOCK_D0:1; // 2 D0 RAM access protection and master select fields lock bit Uint16 LOCK_D1:1; // 3 D1 RAM access protection and master select fields lock bit Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union DxLOCK_REG { Uint32 all; struct DxLOCK_BITS bit; }; struct DxCOMMIT_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 COMMIT_D0:1; // 2 D0 RAM access protection and master select permanent lock Uint16 COMMIT_D1:1; // 3 D1 RAM access protection and master select permanent lock Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union DxCOMMIT_REG { Uint32 all; struct DxCOMMIT_BITS bit; }; struct DxACCPROT0_BITS { // bits description Uint16 rsvd1:16; // 15:0 Reserved Uint16 FETCHPROT_D0:1; // 16 Fetch Protection For D0 RAM Uint16 CPUWRPROT_D0:1; // 17 CPU WR Protection For D0 RAM Uint16 rsvd2:6; // 23:18 Reserved Uint16 FETCHPROT_D1:1; // 24 Fetch Protection For D1 RAM Uint16 CPUWRPROT_D1:1; // 25 CPU WR Protection For D1 RAM Uint16 rsvd3:6; // 31:26 Reserved }; union DxACCPROT0_REG { Uint32 all; struct DxACCPROT0_BITS bit; }; struct DxTEST_BITS { // bits description Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM Uint16 TEST_D0:2; // 5:4 Selects the different modes for D0 RAM Uint16 TEST_D1:2; // 7:6 Selects the different modes for D1 RAM Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxTEST_REG { Uint32 all; struct DxTEST_BITS bit; }; struct DxINIT_BITS { // bits description Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. Uint16 INIT_D0:1; // 2 RAM Initialization control for D0 RAM. Uint16 INIT_D1:1; // 3 RAM Initialization control for D1 RAM. Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxINIT_REG { Uint32 all; struct DxINIT_BITS bit; }; struct DxINITDONE_BITS { // bits description Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. Uint16 INITDONE_D0:1; // 2 RAM Initialization status for D0 RAM. Uint16 INITDONE_D1:1; // 3 RAM Initialization status for D1 RAM. Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxINITDONE_REG { Uint32 all; struct DxINITDONE_BITS bit; }; struct LSxLOCK_BITS { // bits description Uint16 LOCK_LS0:1; // 0 LS0 RAM access protection and master select fields lock bit Uint16 LOCK_LS1:1; // 1 LS1 RAM access protection and master select fields lock bit Uint16 LOCK_LS2:1; // 2 LS2 RAM access protection and master select fields lock bit Uint16 LOCK_LS3:1; // 3 LS3 RAM access protection and master select fields lock bit Uint16 LOCK_LS4:1; // 4 LS4 RAM access protection and master select fields lock bit Uint16 LOCK_LS5:1; // 5 LS5 RAM access protection and master select fields lock bit Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxLOCK_REG { Uint32 all; struct LSxLOCK_BITS bit; }; struct LSxCOMMIT_BITS { // bits description Uint16 COMMIT_LS0:1; // 0 LS0 RAM access protection and master select permanent lock Uint16 COMMIT_LS1:1; // 1 LS1 RAM access protection and master select permanent lock Uint16 COMMIT_LS2:1; // 2 LS2 RAM access protection and master select permanent lock Uint16 COMMIT_LS3:1; // 3 LS3 RAM access protection and master select permanent lock Uint16 COMMIT_LS4:1; // 4 LS4 RAM access protection and master select permanent lock Uint16 COMMIT_LS5:1; // 5 LS5 RAM access protection and master select permanent lock Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxCOMMIT_REG { Uint32 all; struct LSxCOMMIT_BITS bit; }; struct LSxMSEL_BITS { // bits description Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxMSEL_REG { Uint32 all; struct LSxMSEL_BITS bit; }; struct LSxCLAPGM_BITS { // bits description Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxCLAPGM_REG { Uint32 all; struct LSxCLAPGM_BITS bit; }; struct LSxACCPROT0_BITS { // bits description Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM Uint16 rsvd3:6; // 23:18 Reserved Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM Uint16 rsvd4:6; // 31:26 Reserved }; union LSxACCPROT0_REG { Uint32 all; struct LSxACCPROT0_BITS bit; }; struct LSxACCPROT1_BITS { // bits description Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union LSxACCPROT1_REG { Uint32 all; struct LSxACCPROT1_BITS bit; }; struct LSxTEST_BITS { // bits description Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxTEST_REG { Uint32 all; struct LSxTEST_BITS bit; }; struct LSxINIT_BITS { // bits description Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxINIT_REG { Uint32 all; struct LSxINIT_BITS bit; }; struct LSxINITDONE_BITS { // bits description Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxINITDONE_REG { Uint32 all; struct LSxINITDONE_BITS bit; }; struct GSxLOCK_BITS { // bits description Uint16 LOCK_GS0:1; // 0 GS0 RAM access protection and master select fields lock bit Uint16 LOCK_GS1:1; // 1 GS1 RAM access protection and master select fields lock bit Uint16 LOCK_GS2:1; // 2 GS2 RAM access protection and master select fields lock bit Uint16 LOCK_GS3:1; // 3 GS3 RAM access protection and master select fields lock bit Uint16 LOCK_GS4:1; // 4 GS4 RAM access protection and master select fields lock bit Uint16 LOCK_GS5:1; // 5 GS5 RAM access protection and master select fields lock bit Uint16 LOCK_GS6:1; // 6 GS6 RAM access protection and master select fields lock bit Uint16 LOCK_GS7:1; // 7 GS7 RAM access protection and master select fields lock bit Uint16 LOCK_GS8:1; // 8 GS8 RAM access protection and master select fields lock bit Uint16 LOCK_GS9:1; // 9 GS9 RAM access protection and master select fields lock bit Uint16 LOCK_GS10:1; // 10 GS10 RAM access protection and master select fields lock bit Uint16 LOCK_GS11:1; // 11 GS11 RAM access protection and master select fields lock bit Uint16 LOCK_GS12:1; // 12 GS12 RAM access protection and master select fields lock bit Uint16 LOCK_GS13:1; // 13 GS13 RAM access protection and master select fields lock bit Uint16 LOCK_GS14:1; // 14 GS14 RAM access protection and master select fields lock bit Uint16 LOCK_GS15:1; // 15 GS15 RAM access protection and master select fields lock bit Uint16 rsvd1:16; // 31:16 Reserved }; union GSxLOCK_REG { Uint32 all; struct GSxLOCK_BITS bit; }; struct GSxCOMMIT_BITS { // bits description Uint16 COMMIT_GS0:1; // 0 GS0 RAM access protection and master select permanent lock Uint16 COMMIT_GS1:1; // 1 GS1 RAM access protection and master select permanent lock Uint16 COMMIT_GS2:1; // 2 GS2 RAM access protection and master select permanent lock Uint16 COMMIT_GS3:1; // 3 GS3 RAM access protection and master select permanent lock Uint16 COMMIT_GS4:1; // 4 GS4 RAM access protection and master select permanent lock Uint16 COMMIT_GS5:1; // 5 GS5 RAM access protection and master select permanent lock Uint16 COMMIT_GS6:1; // 6 GS6 RAM access protection and master select permanent lock Uint16 COMMIT_GS7:1; // 7 GS7 RAM access protection and master select permanent lock Uint16 COMMIT_GS8:1; // 8 GS8 RAM access protection and master select permanent lock Uint16 COMMIT_GS9:1; // 9 GS9 RAM access protection and master select permanent lock Uint16 COMMIT_GS10:1; // 10 GS10 RAM access protection and master select permanent lock Uint16 COMMIT_GS11:1; // 11 GS11 RAM access protection and master select permanent lock Uint16 COMMIT_GS12:1; // 12 GS12 RAM access protection and master select permanent lock Uint16 COMMIT_GS13:1; // 13 GS13 RAM access protection and master select permanent lock Uint16 COMMIT_GS14:1; // 14 GS14 RAM access protection and master select permanent lock Uint16 COMMIT_GS15:1; // 15 GS15 RAM access protection and master select permanent lock Uint16 rsvd1:16; // 31:16 Reserved }; union GSxCOMMIT_REG { Uint32 all; struct GSxCOMMIT_BITS bit; }; struct GSxMSEL_BITS { // bits description Uint16 MSEL_GS0:1; // 0 Master Select for GS0 RAM Uint16 MSEL_GS1:1; // 1 Master Select for GS1 RAM Uint16 MSEL_GS2:1; // 2 Master Select for GS2 RAM Uint16 MSEL_GS3:1; // 3 Master Select for GS3 RAM Uint16 MSEL_GS4:1; // 4 Master Select for GS4 RAM Uint16 MSEL_GS5:1; // 5 Master Select for GS5 RAM Uint16 MSEL_GS6:1; // 6 Master Select for GS6 RAM Uint16 MSEL_GS7:1; // 7 Master Select for GS7 RAM Uint16 MSEL_GS8:1; // 8 Master Select for GS8 RAM Uint16 MSEL_GS9:1; // 9 Master Select for GS9 RAM Uint16 MSEL_GS10:1; // 10 Master Select for GS10 RAM Uint16 MSEL_GS11:1; // 11 Master Select for GS11 RAM Uint16 MSEL_GS12:1; // 12 Master Select for GS12 RAM Uint16 MSEL_GS13:1; // 13 Master Select for GS13 RAM Uint16 MSEL_GS14:1; // 14 Master Select for GS14 RAM Uint16 MSEL_GS15:1; // 15 Master Select for GS15 RAM Uint16 rsvd1:16; // 31:16 Reserved }; union GSxMSEL_REG { Uint32 all; struct GSxMSEL_BITS bit; }; struct GSxACCPROT0_BITS { // bits description Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT0_REG { Uint32 all; struct GSxACCPROT0_BITS bit; }; struct GSxACCPROT1_BITS { // bits description Uint16 FETCHPROT_GS4:1; // 0 Fetch Protection For GS4 RAM Uint16 CPUWRPROT_GS4:1; // 1 CPU WR Protection For GS4 RAM Uint16 DMAWRPROT_GS4:1; // 2 DMA WR Protection For GS4 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS5:1; // 8 Fetch Protection For GS5 RAM Uint16 CPUWRPROT_GS5:1; // 9 CPU WR Protection For GS5 RAM Uint16 DMAWRPROT_GS5:1; // 10 DMA WR Protection For GS5RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS6:1; // 16 Fetch Protection For GS6 RAM Uint16 CPUWRPROT_GS6:1; // 17 CPU WR Protection For GS6 RAM Uint16 DMAWRPROT_GS6:1; // 18 DMA WR Protection For GS6RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS7:1; // 24 Fetch Protection For GS7 RAM Uint16 CPUWRPROT_GS7:1; // 25 CPU WR Protection For GS7 RAM Uint16 DMAWRPROT_GS7:1; // 26 DMA WR Protection For GS7RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT1_REG { Uint32 all; struct GSxACCPROT1_BITS bit; }; struct GSxACCPROT2_BITS { // bits description Uint16 FETCHPROT_GS8:1; // 0 Fetch Protection For GS8 RAM Uint16 CPUWRPROT_GS8:1; // 1 CPU WR Protection For GS8 RAM Uint16 DMAWRPROT_GS8:1; // 2 DMA WR Protection For GS8 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS9:1; // 8 Fetch Protection For GS9 RAM Uint16 CPUWRPROT_GS9:1; // 9 CPU WR Protection For GS9 RAM Uint16 DMAWRPROT_GS9:1; // 10 DMA WR Protection For GS9RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS10:1; // 16 Fetch Protection For GS10 RAM Uint16 CPUWRPROT_GS10:1; // 17 CPU WR Protection For GS10 RAM Uint16 DMAWRPROT_GS10:1; // 18 DMA WR Protection For GS10RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS11:1; // 24 Fetch Protection For GS11 RAM Uint16 CPUWRPROT_GS11:1; // 25 CPU WR Protection For GS11 RAM Uint16 DMAWRPROT_GS11:1; // 26 DMA WR Protection For GS11RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT2_REG { Uint32 all; struct GSxACCPROT2_BITS bit; }; struct GSxACCPROT3_BITS { // bits description Uint16 FETCHPROT_GS12:1; // 0 Fetch Protection For GS12 RAM Uint16 CPUWRPROT_GS12:1; // 1 CPU WR Protection For GS12 RAM Uint16 DMAWRPROT_GS12:1; // 2 DMA WR Protection For GS12 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS13:1; // 8 Fetch Protection For GS13 RAM Uint16 CPUWRPROT_GS13:1; // 9 CPU WR Protection For GS13 RAM Uint16 DMAWRPROT_GS13:1; // 10 DMA WR Protection For GS13RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS14:1; // 16 Fetch Protection For GS14 RAM Uint16 CPUWRPROT_GS14:1; // 17 CPU WR Protection For GS14 RAM Uint16 DMAWRPROT_GS14:1; // 18 DMA WR Protection For GS14RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS15:1; // 24 Fetch Protection For GS15 RAM Uint16 CPUWRPROT_GS15:1; // 25 CPU WR Protection For GS15 RAM Uint16 DMAWRPROT_GS15:1; // 26 DMA WR Protection For GS15RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT3_REG { Uint32 all; struct GSxACCPROT3_BITS bit; }; struct GSxTEST_BITS { // bits description Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM Uint16 TEST_GS4:2; // 9:8 Selects the different modes for GS4 RAM Uint16 TEST_GS5:2; // 11:10 Selects the different modes for GS5 RAM Uint16 TEST_GS6:2; // 13:12 Selects the different modes for GS6 RAM Uint16 TEST_GS7:2; // 15:14 Selects the different modes for GS7 RAM Uint16 TEST_GS8:2; // 17:16 Selects the different modes for GS8 RAM Uint16 TEST_GS9:2; // 19:18 Selects the different modes for GS9 RAM Uint16 TEST_GS10:2; // 21:20 Selects the different modes for GS10 RAM Uint16 TEST_GS11:2; // 23:22 Selects the different modes for GS11 RAM Uint16 TEST_GS12:2; // 25:24 Selects the different modes for GS12 RAM Uint16 TEST_GS13:2; // 27:26 Selects the different modes for GS13 RAM Uint16 TEST_GS14:2; // 29:28 Selects the different modes for GS14 RAM Uint16 TEST_GS15:2; // 31:30 Selects the different modes for GS15 RAM }; union GSxTEST_REG { Uint32 all; struct GSxTEST_BITS bit; }; struct GSxINIT_BITS { // bits description Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. Uint16 INIT_GS4:1; // 4 RAM Initialization control for GS4 RAM. Uint16 INIT_GS5:1; // 5 RAM Initialization control for GS5 RAM. Uint16 INIT_GS6:1; // 6 RAM Initialization control for GS6 RAM. Uint16 INIT_GS7:1; // 7 RAM Initialization control for GS7 RAM. Uint16 INIT_GS8:1; // 8 RAM Initialization control for GS8 RAM. Uint16 INIT_GS9:1; // 9 RAM Initialization control for GS9 RAM. Uint16 INIT_GS10:1; // 10 RAM Initialization control for GS10 RAM. Uint16 INIT_GS11:1; // 11 RAM Initialization control for GS11 RAM. Uint16 INIT_GS12:1; // 12 RAM Initialization control for GS12 RAM. Uint16 INIT_GS13:1; // 13 RAM Initialization control for GS13 RAM. Uint16 INIT_GS14:1; // 14 RAM Initialization control for GS14 RAM. Uint16 INIT_GS15:1; // 15 RAM Initialization control for GS15 RAM. Uint16 rsvd1:16; // 31:16 Reserved }; union GSxINIT_REG { Uint32 all; struct GSxINIT_BITS bit; }; struct GSxINITDONE_BITS { // bits description Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. Uint16 INITDONE_GS4:1; // 4 RAM Initialization status for GS4 RAM. Uint16 INITDONE_GS5:1; // 5 RAM Initialization status for GS5 RAM. Uint16 INITDONE_GS6:1; // 6 RAM Initialization status for GS6 RAM. Uint16 INITDONE_GS7:1; // 7 RAM Initialization status for GS7 RAM. Uint16 INITDONE_GS8:1; // 8 RAM Initialization status for GS8 RAM. Uint16 INITDONE_GS9:1; // 9 RAM Initialization status for GS9 RAM. Uint16 INITDONE_GS10:1; // 10 RAM Initialization status for GS10 RAM. Uint16 INITDONE_GS11:1; // 11 RAM Initialization status for GS11 RAM. Uint16 INITDONE_GS12:1; // 12 RAM Initialization status for GS12 RAM. Uint16 INITDONE_GS13:1; // 13 RAM Initialization status for GS13 RAM. Uint16 INITDONE_GS14:1; // 14 RAM Initialization status for GS14 RAM. Uint16 INITDONE_GS15:1; // 15 RAM Initialization status for GS15 RAM. Uint16 rsvd1:16; // 31:16 Reserved }; union GSxINITDONE_REG { Uint32 all; struct GSxINITDONE_BITS bit; }; struct MSGxTEST_BITS { // bits description Uint16 TEST_CPUTOCPU:2; // 1:0 CPU to CPU Mode Select Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select Uint16 rsvd1:2; // 7:6 Reserved Uint16 rsvd2:2; // 9:8 Reserved Uint16 rsvd3:6; // 15:10 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union MSGxTEST_REG { Uint32 all; struct MSGxTEST_BITS bit; }; struct MSGxINIT_BITS { // bits description Uint16 INIT_CPUTOCPU:1; // 0 Initialization control for CPU to CPU MSG RAM Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 rsvd3:11; // 15:5 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union MSGxINIT_REG { Uint32 all; struct MSGxINIT_BITS bit; }; struct MSGxINITDONE_BITS { // bits description Uint16 INITDONE_CPUTOCPU:1; // 0 Initialization status for CPU to CPU MSG RAM Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 rsvd3:11; // 15:5 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union MSGxINITDONE_REG { Uint32 all; struct MSGxINITDONE_BITS bit; }; struct MEM_CFG_REGS { union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register Uint16 rsvd1[4]; // Reserved union DxACCPROT0_REG DxACCPROT0; // Dedicated RAM Config Register Uint16 rsvd2[6]; // Reserved union DxTEST_REG DxTEST; // Dedicated RAM TEST Register union DxINIT_REG DxINIT; // Dedicated RAM Init Register union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register Uint16 rsvd3[10]; // Reserved union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 Uint16 rsvd4[4]; // Reserved union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register Uint16 rsvd5[10]; // Reserved union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register union GSxMSEL_REG GSxMSEL; // Global Shared RAM Master Sel Register Uint16 rsvd6[2]; // Reserved union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 union GSxACCPROT1_REG GSxACCPROT1; // Global Shared RAM Config Register 1 union GSxACCPROT2_REG GSxACCPROT2; // Global Shared RAM Config Register 2 union GSxACCPROT3_REG GSxACCPROT3; // Global Shared RAM Config Register 3 union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register Uint16 rsvd7[26]; // Reserved union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register union MSGxINIT_REG MSGxINIT; // Message RAM Init Register union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register Uint16 rsvd8[10]; // Reserved }; struct EMIF1LOCK_BITS { // bits description Uint16 LOCK_EMIF1:1; // 0 EMIF1 access protection and master select fields lock bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF1LOCK_REG { Uint32 all; struct EMIF1LOCK_BITS bit; }; struct EMIF1COMMIT_BITS { // bits description Uint16 COMMIT_EMIF1:1; // 0 EMIF1 access protection and master select permanent lock Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF1COMMIT_REG { Uint32 all; struct EMIF1COMMIT_BITS bit; }; struct EMIF1MSEL_BITS { // bits description Uint16 MSEL_EMIF1:2; // 1:0 Master Select for EMIF1. Uint16 rsvd1:2; // 3:2 Reserved Uint32 KEY:28; // 31:4 KEY to enable the write into MSEL_EMIF1 bits }; union EMIF1MSEL_REG { Uint32 all; struct EMIF1MSEL_BITS bit; }; struct EMIF1ACCPROT0_BITS { // bits description Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF1 Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF1 Uint16 DMAWRPROT_EMIF1:1; // 2 DMA WR Protection For EMIF1 Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF1ACCPROT0_REG { Uint32 all; struct EMIF1ACCPROT0_BITS bit; }; struct EMIF1_CONFIG_REGS { union EMIF1LOCK_REG EMIF1LOCK; // EMIF1 Config Lock Register union EMIF1COMMIT_REG EMIF1COMMIT; // EMIF1 Config Lock Commit Register union EMIF1MSEL_REG EMIF1MSEL; // EMIF1 Master Sel Register Uint16 rsvd1[2]; // Reserved union EMIF1ACCPROT0_REG EMIF1ACCPROT0; // EMIF1 Config Register 0 Uint16 rsvd2[22]; // Reserved }; struct EMIF2LOCK_BITS { // bits description Uint16 LOCK_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF2LOCK_REG { Uint32 all; struct EMIF2LOCK_BITS bit; }; struct EMIF2COMMIT_BITS { // bits description Uint16 COMMIT_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF2COMMIT_REG { Uint32 all; struct EMIF2COMMIT_BITS bit; }; struct EMIF2ACCPROT0_BITS { // bits description Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF2 Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF2 Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF2ACCPROT0_REG { Uint32 all; struct EMIF2ACCPROT0_BITS bit; }; struct EMIF2_CONFIG_REGS { union EMIF2LOCK_REG EMIF2LOCK; // EMIF2 Config Lock Register union EMIF2COMMIT_REG EMIF2COMMIT; // EMIF2 Config Lock Commit Register Uint16 rsvd1[4]; // Reserved union EMIF2ACCPROT0_REG EMIF2ACCPROT0; // EMIF2 Config Register 0 Uint16 rsvd2[22]; // Reserved }; struct NMAVFLG_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVFLG_REG { Uint32 all; struct NMAVFLG_BITS bit; }; struct NMAVSET_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVSET_REG { Uint32 all; struct NMAVSET_BITS bit; }; struct NMAVCLR_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVCLR_REG { Uint32 all; struct NMAVCLR_BITS bit; }; struct NMAVINTEN_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Interrupt Enable Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVINTEN_REG { Uint32 all; struct NMAVINTEN_BITS bit; }; struct MAVFLG_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVFLG_REG { Uint32 all; struct MAVFLG_BITS bit; }; struct MAVSET_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVSET_REG { Uint32 all; struct MAVSET_BITS bit; }; struct MAVCLR_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVCLR_REG { Uint32 all; struct MAVCLR_BITS bit; }; struct MAVINTEN_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVINTEN_REG { Uint32 all; struct MAVINTEN_BITS bit; }; struct ACCESS_PROTECTION_REGS { union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address Uint32 NMDMAWRAVADDR; // Non-Master DMA Write Access Violation Address Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address Uint16 rsvd1[10]; // Reserved union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address Uint16 rsvd2[18]; // Reserved }; struct UCERRFLG_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRFLG_REG { Uint32 all; struct UCERRFLG_BITS bit; }; struct UCERRSET_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRSET_REG { Uint32 all; struct UCERRSET_BITS bit; }; struct UCERRCLR_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRCLR_REG { Uint32 all; struct UCERRCLR_BITS bit; }; struct CERRFLG_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRFLG_REG { Uint32 all; struct CERRFLG_BITS bit; }; struct CERRSET_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRSET_REG { Uint32 all; struct CERRSET_BITS bit; }; struct CERRCLR_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRCLR_REG { Uint32 all; struct CERRCLR_BITS bit; }; struct CEINTFLG_BITS { // bits description Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTFLG_REG { Uint32 all; struct CEINTFLG_BITS bit; }; struct CEINTCLR_BITS { // bits description Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTCLR_REG { Uint32 all; struct CEINTCLR_BITS bit; }; struct CEINTSET_BITS { // bits description Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTSET_REG { Uint32 all; struct CEINTSET_BITS bit; }; struct CEINTEN_BITS { // bits description Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTEN_REG { Uint32 all; struct CEINTEN_BITS bit; }; struct MEMORY_ERROR_REGS { union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address Uint16 rsvd1[20]; // Reserved union CERRFLG_REG CERRFLG; // Correctable Error Flag Register union CERRSET_REG CERRSET; // Correctable Error Flag Set Register union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register Uint32 CCPUREADDR; // Correctable CPU Read Error Address Uint16 rsvd2[6]; // Reserved Uint32 CERRCNT; // Correctable Error Count Register Uint32 CERRTHRES; // Correctable Error Threshold Value Register union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register Uint16 rsvd3[6]; // Reserved }; struct ROMWAITSTATE_BITS { // bits description Uint16 WSDISABLE:1; // 0 ROM Wait State Enable/Disable Control Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ROMWAITSTATE_REG { Uint32 all; struct ROMWAITSTATE_BITS bit; }; struct ROM_WAIT_STATE_REGS { union ROMWAITSTATE_REG ROMWAITSTATE; // ROM Wait State Configuration Register }; struct ROMPREFETCH_BITS { // bits description Uint16 PFENABLE:1; // 0 ROM Prefetch Enable/Disable Control Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ROMPREFETCH_REG { Uint32 all; struct ROMPREFETCH_BITS bit; }; struct ROM_PREFETCH_REGS { union ROMPREFETCH_REG ROMPREFETCH; // ROM Prefetch Configuration Register }; //--------------------------------------------------------------------------- // MEMCONFIG External References & Function Declarations: // extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; extern volatile struct MEM_CFG_REGS MemCfgRegs; extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; extern volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_nmiintrupt.h // // TITLE: F2837xD Device NMIINTRUPT Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // NMIINTRUPT Individual Register Bit Definitions: struct NMICFG_BITS { // bits description Uint16 NMIE:1; // 0 Global NMI Enable Uint16 rsvd1:15; // 15:1 Reserved }; union NMICFG_REG { Uint16 all; struct NMICFG_BITS bit; }; struct NMIFLG_BITS { // bits description Uint16 NMIINT:1; // 0 NMI Interrupt Flag Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:4; // 15:12 Reserved }; union NMIFLG_REG { Uint16 all; struct NMIFLG_BITS bit; }; struct NMIFLGCLR_BITS { // bits description Uint16 NMIINT:1; // 0 NMIINT Flag Clear Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear Uint16 OVF:1; // 11 OVF Flag Clear Uint16 rsvd3:4; // 15:12 Reserved }; union NMIFLGCLR_REG { Uint16 all; struct NMIFLGCLR_BITS bit; }; struct NMIFLGFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force Uint16 OVF:1; // 11 OVF Flag Force Uint16 rsvd4:4; // 15:12 Reserved }; union NMIFLGFRC_REG { Uint16 all; struct NMIFLGFRC_BITS bit; }; struct NMISHDFLG_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag Uint16 OVF:1; // 11 Shadow OVF Flag Uint16 rsvd4:4; // 15:12 Reserved }; union NMISHDFLG_REG { Uint16 all; struct NMISHDFLG_BITS bit; }; struct NMI_INTRUPT_REGS { union NMICFG_REG NMICFG; // NMI Configuration Register union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear) union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register Uint16 NMIWDCNT; // NMI Watchdog Counter Register Uint16 NMIWDPRD; // NMI Watchdog Period Register union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register }; //--------------------------------------------------------------------------- // NMIINTRUPT External References & Function Declarations: // extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_output_xbar.h // // TITLE: F2837xD Device OUTPUT_XBAR Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // OUTPUT_XBAR Individual Register Bit Definitions: struct OUTPUT1MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUX0TO15CFG_REG { Uint32 all; struct OUTPUT1MUX0TO15CFG_BITS bit; }; struct OUTPUT1MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUX16TO31CFG_REG { Uint32 all; struct OUTPUT1MUX16TO31CFG_BITS bit; }; struct OUTPUT2MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUX0TO15CFG_REG { Uint32 all; struct OUTPUT2MUX0TO15CFG_BITS bit; }; struct OUTPUT2MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUX16TO31CFG_REG { Uint32 all; struct OUTPUT2MUX16TO31CFG_BITS bit; }; struct OUTPUT3MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUX0TO15CFG_REG { Uint32 all; struct OUTPUT3MUX0TO15CFG_BITS bit; }; struct OUTPUT3MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUX16TO31CFG_REG { Uint32 all; struct OUTPUT3MUX16TO31CFG_BITS bit; }; struct OUTPUT4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUX0TO15CFG_REG { Uint32 all; struct OUTPUT4MUX0TO15CFG_BITS bit; }; struct OUTPUT4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUX16TO31CFG_REG { Uint32 all; struct OUTPUT4MUX16TO31CFG_BITS bit; }; struct OUTPUT5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUX0TO15CFG_REG { Uint32 all; struct OUTPUT5MUX0TO15CFG_BITS bit; }; struct OUTPUT5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUX16TO31CFG_REG { Uint32 all; struct OUTPUT5MUX16TO31CFG_BITS bit; }; struct OUTPUT6MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUX0TO15CFG_REG { Uint32 all; struct OUTPUT6MUX0TO15CFG_BITS bit; }; struct OUTPUT6MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUX16TO31CFG_REG { Uint32 all; struct OUTPUT6MUX16TO31CFG_BITS bit; }; struct OUTPUT7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUX0TO15CFG_REG { Uint32 all; struct OUTPUT7MUX0TO15CFG_BITS bit; }; struct OUTPUT7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUX16TO31CFG_REG { Uint32 all; struct OUTPUT7MUX16TO31CFG_BITS bit; }; struct OUTPUT8MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUX0TO15CFG_REG { Uint32 all; struct OUTPUT8MUX0TO15CFG_BITS bit; }; struct OUTPUT8MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUX16TO31CFG_REG { Uint32 all; struct OUTPUT8MUX16TO31CFG_BITS bit; }; struct OUTPUT1MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUXENABLE_REG { Uint32 all; struct OUTPUT1MUXENABLE_BITS bit; }; struct OUTPUT2MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUXENABLE_REG { Uint32 all; struct OUTPUT2MUXENABLE_BITS bit; }; struct OUTPUT3MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUXENABLE_REG { Uint32 all; struct OUTPUT3MUXENABLE_BITS bit; }; struct OUTPUT4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUXENABLE_REG { Uint32 all; struct OUTPUT4MUXENABLE_BITS bit; }; struct OUTPUT5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUXENABLE_REG { Uint32 all; struct OUTPUT5MUXENABLE_BITS bit; }; struct OUTPUT6MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUXENABLE_REG { Uint32 all; struct OUTPUT6MUXENABLE_BITS bit; }; struct OUTPUT7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUXENABLE_REG { Uint32 all; struct OUTPUT7MUXENABLE_BITS bit; }; struct OUTPUT8MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUXENABLE_REG { Uint32 all; struct OUTPUT8MUXENABLE_BITS bit; }; struct OUTPUTLATCH_BITS { // bits description Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCH_REG { Uint32 all; struct OUTPUTLATCH_BITS bit; }; struct OUTPUTLATCHCLR_BITS { // bits description Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHCLR_REG { Uint32 all; struct OUTPUTLATCHCLR_BITS bit; }; struct OUTPUTLATCHFRC_BITS { // bits description Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHFRC_REG { Uint32 all; struct OUTPUTLATCHFRC_BITS bit; }; struct OUTPUTLATCHENABLE_BITS { // bits description Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Selects the output latch to drive output1 for OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Selects the output latch to drive output2 for OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Selects the output latch to drive output3 for OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Selects the output latch to drive output4 for OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Selects the output latch to drive output5 for OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Selects the output latch to drive output6 for OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Selects the output latch to drive output7 for OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHENABLE_REG { Uint32 all; struct OUTPUTLATCHENABLE_BITS bit; }; struct OUTPUTINV_BITS { // bits description Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTINV_REG { Uint32 all; struct OUTPUTINV_BITS bit; }; struct OUTPUTLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write Protection KEY }; union OUTPUTLOCK_REG { Uint32 all; struct OUTPUTLOCK_BITS bit; }; struct OUTPUT_XBAR_REGS { union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion Uint16 rsvd1[4]; // Reserved union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register }; //--------------------------------------------------------------------------- // OUTPUT_XBAR External References & Function Declarations: // extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_piectrl.h // // TITLE: F2837xD Device PIECTRL Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // PIECTRL Individual Register Bit Definitions: struct PIECTRL_BITS { // bits description Uint16 ENPIE:1; // 0 PIE Enable Uint16 PIEVECT:15; // 15:1 PIE Vector Address }; union PIECTRL_REG { Uint16 all; struct PIECTRL_BITS bit; }; struct PIEACK_BITS { // bits description Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 Uint16 rsvd1:4; // 15:12 Reserved }; union PIEACK_REG { Uint16 all; struct PIEACK_BITS bit; }; struct PIEIER1_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 }; union PIEIER1_REG { Uint16 all; struct PIEIER1_BITS bit; }; struct PIEIFR1_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 }; union PIEIFR1_REG { Uint16 all; struct PIEIFR1_BITS bit; }; struct PIEIER2_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 }; union PIEIER2_REG { Uint16 all; struct PIEIER2_BITS bit; }; struct PIEIFR2_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 }; union PIEIFR2_REG { Uint16 all; struct PIEIFR2_BITS bit; }; struct PIEIER3_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 }; union PIEIER3_REG { Uint16 all; struct PIEIER3_BITS bit; }; struct PIEIFR3_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 }; union PIEIFR3_REG { Uint16 all; struct PIEIFR3_BITS bit; }; struct PIEIER4_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 }; union PIEIER4_REG { Uint16 all; struct PIEIER4_BITS bit; }; struct PIEIFR4_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 }; union PIEIFR4_REG { Uint16 all; struct PIEIFR4_BITS bit; }; struct PIEIER5_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 }; union PIEIER5_REG { Uint16 all; struct PIEIER5_BITS bit; }; struct PIEIFR5_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 }; union PIEIFR5_REG { Uint16 all; struct PIEIFR5_BITS bit; }; struct PIEIER6_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 }; union PIEIER6_REG { Uint16 all; struct PIEIER6_BITS bit; }; struct PIEIFR6_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 }; union PIEIFR6_REG { Uint16 all; struct PIEIFR6_BITS bit; }; struct PIEIER7_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 }; union PIEIER7_REG { Uint16 all; struct PIEIER7_BITS bit; }; struct PIEIFR7_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 }; union PIEIFR7_REG { Uint16 all; struct PIEIFR7_BITS bit; }; struct PIEIER8_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 }; union PIEIER8_REG { Uint16 all; struct PIEIER8_BITS bit; }; struct PIEIFR8_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 }; union PIEIFR8_REG { Uint16 all; struct PIEIFR8_BITS bit; }; struct PIEIER9_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 }; union PIEIER9_REG { Uint16 all; struct PIEIER9_BITS bit; }; struct PIEIFR9_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 }; union PIEIFR9_REG { Uint16 all; struct PIEIFR9_BITS bit; }; struct PIEIER10_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 }; union PIEIER10_REG { Uint16 all; struct PIEIER10_BITS bit; }; struct PIEIFR10_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 }; union PIEIFR10_REG { Uint16 all; struct PIEIFR10_BITS bit; }; struct PIEIER11_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 }; union PIEIER11_REG { Uint16 all; struct PIEIER11_BITS bit; }; struct PIEIFR11_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 }; union PIEIFR11_REG { Uint16 all; struct PIEIFR11_BITS bit; }; struct PIEIER12_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 }; union PIEIER12_REG { Uint16 all; struct PIEIER12_BITS bit; }; struct PIEIFR12_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 }; union PIEIFR12_REG { Uint16 all; struct PIEIFR12_BITS bit; }; struct PIE_CTRL_REGS { union PIECTRL_REG PIECTRL; // ePIE Control Register union PIEACK_REG PIEACK; // Interrupt Acknowledge Register union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register }; //--------------------------------------------------------------------------- // PIECTRL External References & Function Declarations: // extern volatile struct PIE_CTRL_REGS PieCtrlRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_pievect.h // // TITLE: F2837xD Device PIE Vector Table Definitions // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // PIE Interrupt Vector Table Definition: // Create a user type called PINT (pointer to interrupt): typedef __interrupt void (*PINT)(void); // Define Vector Table: struct PIE_VECT_TABLE { PINT PIE1_RESERVED_INT; // Reserved PINT PIE2_RESERVED_INT; // Reserved PINT PIE3_RESERVED_INT; // Reserved PINT PIE4_RESERVED_INT; // Reserved PINT PIE5_RESERVED_INT; // Reserved PINT PIE6_RESERVED_INT; // Reserved PINT PIE7_RESERVED_INT; // Reserved PINT PIE8_RESERVED_INT; // Reserved PINT PIE9_RESERVED_INT; // Reserved PINT PIE10_RESERVED_INT; // Reserved PINT PIE11_RESERVED_INT; // Reserved PINT PIE12_RESERVED_INT; // Reserved PINT PIE13_RESERVED_INT; // Reserved PINT TIMER1_INT; // CPU Timer 1 Interrupt PINT TIMER2_INT; // CPU Timer 2 Interrupt PINT DATALOG_INT; // Datalogging Interrupt PINT RTOS_INT; // RTOS Interrupt PINT EMU_INT; // Emulation Interrupt PINT NMI_INT; // Non-Maskable Interrupt PINT ILLEGAL_INT; // Illegal Operation Trap PINT USER1_INT; // User Defined Trap 1 PINT USER2_INT; // User Defined Trap 2 PINT USER3_INT; // User Defined Trap 3 PINT USER4_INT; // User Defined Trap 4 PINT USER5_INT; // User Defined Trap 5 PINT USER6_INT; // User Defined Trap 6 PINT USER7_INT; // User Defined Trap 7 PINT USER8_INT; // User Defined Trap 8 PINT USER9_INT; // User Defined Trap 9 PINT USER10_INT; // User Defined Trap 10 PINT USER11_INT; // User Defined Trap 11 PINT USER12_INT; // User Defined Trap 12 PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 PINT XINT1_INT; // 1.4 - XINT1 Interrupt PINT XINT2_INT; // 1.5 - XINT2 Interrupt PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt PINT PIE14_RESERVED_INT; // 4.7 - Reserved PINT PIE15_RESERVED_INT; // 4.8 - Reserved PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt PINT PIE16_RESERVED_INT; // 5.4 - Reserved PINT PIE17_RESERVED_INT; // 5.5 - Reserved PINT PIE18_RESERVED_INT; // 5.6 - Reserved PINT PIE19_RESERVED_INT; // 5.7 - Reserved PINT PIE20_RESERVED_INT; // 5.8 - Reserved PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt PINT PIE21_RESERVED_INT; // 7.7 - Reserved PINT PIE22_RESERVED_INT; // 7.8 - Reserved PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt PINT CANA0_INT; // 9.5 - CANA Interrupt 0 PINT CANA1_INT; // 9.6 - CANA Interrupt 1 PINT CANB0_INT; // 9.7 - CANB Interrupt 0 PINT CANB1_INT; // 9.8 - CANB Interrupt 1 PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 PINT XINT3_INT; // 12.1 - XINT3 Interrupt PINT XINT4_INT; // 12.2 - XINT4 Interrupt PINT XINT5_INT; // 12.3 - XINT5 Interrupt PINT PIE23_RESERVED_INT; // 12.4 - Reserved PINT PIE24_RESERVED_INT; // 12.5 - Reserved PINT VCU_INT; // 12.6 - VCU Interrupt PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt PINT PIE25_RESERVED_INT; // 1.9 - Reserved PINT PIE26_RESERVED_INT; // 1.10 - Reserved PINT PIE27_RESERVED_INT; // 1.11 - Reserved PINT PIE28_RESERVED_INT; // 1.12 - Reserved PINT IPC0_INT; // 1.13 - IPC Interrupt 0 PINT IPC1_INT; // 1.14 - IPC Interrupt 1 PINT IPC2_INT; // 1.15 - IPC Interrupt 2 PINT IPC3_INT; // 1.16 - IPC Interrupt 3 PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt PINT PIE29_RESERVED_INT; // 2.13 - Reserved PINT PIE30_RESERVED_INT; // 2.14 - Reserved PINT PIE31_RESERVED_INT; // 2.15 - Reserved PINT PIE32_RESERVED_INT; // 2.16 - Reserved PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt PINT PIE33_RESERVED_INT; // 3.13 - Reserved PINT PIE34_RESERVED_INT; // 3.14 - Reserved PINT PIE35_RESERVED_INT; // 3.15 - Reserved PINT PIE36_RESERVED_INT; // 3.16 - Reserved PINT PIE37_RESERVED_INT; // 4.9 - Reserved PINT PIE38_RESERVED_INT; // 4.10 - Reserved PINT PIE39_RESERVED_INT; // 4.11 - Reserved PINT PIE40_RESERVED_INT; // 4.12 - Reserved PINT PIE41_RESERVED_INT; // 4.13 - Reserved PINT PIE42_RESERVED_INT; // 4.14 - Reserved PINT PIE43_RESERVED_INT; // 4.15 - Reserved PINT PIE44_RESERVED_INT; // 4.16 - Reserved PINT SD1_INT; // 5.9 - SD1 Interrupt PINT SD2_INT; // 5.10 - SD2 Interrupt PINT PIE45_RESERVED_INT; // 5.11 - Reserved PINT PIE46_RESERVED_INT; // 5.12 - Reserved PINT PIE47_RESERVED_INT; // 5.13 - Reserved PINT PIE48_RESERVED_INT; // 5.14 - Reserved PINT PIE49_RESERVED_INT; // 5.15 - Reserved PINT PIE50_RESERVED_INT; // 5.16 - Reserved PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt PINT PIE51_RESERVED_INT; // 6.11 - Reserved PINT PIE52_RESERVED_INT; // 6.12 - Reserved PINT PIE53_RESERVED_INT; // 6.13 - Reserved PINT PIE54_RESERVED_INT; // 6.14 - Reserved PINT PIE55_RESERVED_INT; // 6.15 - Reserved PINT PIE56_RESERVED_INT; // 6.16 - Reserved PINT PIE57_RESERVED_INT; // 7.9 - Reserved PINT PIE58_RESERVED_INT; // 7.10 - Reserved PINT PIE59_RESERVED_INT; // 7.11 - Reserved PINT PIE60_RESERVED_INT; // 7.12 - Reserved PINT PIE61_RESERVED_INT; // 7.13 - Reserved PINT PIE62_RESERVED_INT; // 7.14 - Reserved PINT PIE63_RESERVED_INT; // 7.15 - Reserved PINT PIE64_RESERVED_INT; // 7.16 - Reserved PINT PIE65_RESERVED_INT; // 8.9 - Reserved PINT PIE66_RESERVED_INT; // 8.10 - Reserved PINT PIE67_RESERVED_INT; // 8.11 - Reserved PINT PIE68_RESERVED_INT; // 8.12 - Reserved PINT PIE69_RESERVED_INT; // 8.13 - Reserved PINT PIE70_RESERVED_INT; // 8.14 - Reserved PINT UPPA_INT; // 8.15 - uPPA Interrupt PINT PIE72_RESERVED_INT; // 8.16 - Reserved PINT PIE73_RESERVED_INT; // 9.9 - Reserved PINT PIE74_RESERVED_INT; // 9.10 - Reserved PINT PIE75_RESERVED_INT; // 9.11 - Reserved PINT PIE76_RESERVED_INT; // 9.12 - Reserved PINT PIE77_RESERVED_INT; // 9.13 - Reserved PINT PIE78_RESERVED_INT; // 9.14 - Reserved PINT USBA_INT; // 9.15 - USBA Interrupt PINT PIE80_RESERVED_INT; // 9.16 - Reserved PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 PINT PIE81_RESERVED_INT; // 11.9 - Reserved PINT PIE82_RESERVED_INT; // 11.10 - Reserved PINT PIE83_RESERVED_INT; // 11.11 - Reserved PINT PIE84_RESERVED_INT; // 11.12 - Reserved PINT PIE85_RESERVED_INT; // 11.13 - Reserved PINT PIE86_RESERVED_INT; // 11.14 - Reserved PINT PIE87_RESERVED_INT; // 11.15 - Reserved PINT PIE88_RESERVED_INT; // 11.16 - Reserved PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt }; //--------------------------------------------------------------------------- // PieVect External References & Function Declarations: // extern volatile struct PIE_VECT_TABLE PieVectTable; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_sci.h // // TITLE: F2837xD Device SCI Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // SCI Individual Register Bit Definitions: struct SCICCR_BITS { // bits description Uint16 SCICHAR:3; // 2:0 Character length control Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control Uint16 LOOPBKENA:1; // 4 Loop Back enable Uint16 PARITYENA:1; // 5 Parity enable Uint16 PARITY:1; // 6 Even or Odd Parity Uint16 STOPBITS:1; // 7 Number of Stop Bits Uint16 rsvd1:8; // 15:8 Reserved }; union SCICCR_REG { Uint16 all; struct SCICCR_BITS bit; }; struct SCICTL1_BITS { // bits description Uint16 RXENA:1; // 0 SCI receiver enable Uint16 TXENA:1; // 1 SCI transmitter enable Uint16 SLEEP:1; // 2 SCI sleep Uint16 TXWAKE:1; // 3 Transmitter wakeup method Uint16 rsvd1:1; // 4 Reserved Uint16 SWRESET:1; // 5 Software reset Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable Uint16 rsvd2:9; // 15:7 Reserved }; union SCICTL1_REG { Uint16 all; struct SCICTL1_BITS bit; }; struct SCIHBAUD_BITS { // bits description Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD Uint16 rsvd1:8; // 15:8 Reserved }; union SCIHBAUD_REG { Uint16 all; struct SCIHBAUD_BITS bit; }; struct SCILBAUD_BITS { // bits description Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD Uint16 rsvd1:8; // 15:8 Reserved }; union SCILBAUD_REG { Uint16 all; struct SCILBAUD_BITS bit; }; struct SCICTL2_BITS { // bits description Uint16 TXINTENA:1; // 0 Transmit __interrupt enable Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable Uint16 rsvd1:4; // 5:2 Reserved Uint16 TXEMPTY:1; // 6 Transmitter empty flag Uint16 TXRDY:1; // 7 Transmitter ready flag Uint16 rsvd2:8; // 15:8 Reserved }; union SCICTL2_REG { Uint16 all; struct SCICTL2_BITS bit; }; struct SCIRXST_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag Uint16 PE:1; // 2 Parity error flag Uint16 OE:1; // 3 Overrun error flag Uint16 FE:1; // 4 Framing error flag Uint16 BRKDT:1; // 5 Break-detect flag Uint16 RXRDY:1; // 6 Receiver ready flag Uint16 RXERROR:1; // 7 Receiver error flag Uint16 rsvd2:8; // 15:8 Reserved }; union SCIRXST_REG { Uint16 all; struct SCIRXST_BITS bit; }; struct SCIRXEMU_BITS { // bits description Uint16 ERXDT:8; // 7:0 Receive emulation buffer data Uint16 rsvd1:8; // 15:8 Reserved }; union SCIRXEMU_REG { Uint16 all; struct SCIRXEMU_BITS bit; }; struct SCIRXBUF_BITS { // bits description Uint16 SAR:8; // 7:0 Receive Character bits Uint16 rsvd1:6; // 13:8 Reserved Uint16 SCIFFPE:1; // 14 Receiver error flag Uint16 SCIFFFE:1; // 15 Receiver error flag }; union SCIRXBUF_REG { Uint16 all; struct SCIRXBUF_BITS bit; }; struct SCITXBUF_BITS { // bits description Uint16 TXDT:8; // 7:0 Transmit data buffer Uint16 rsvd1:8; // 15:8 Reserved }; union SCITXBUF_REG { Uint16 all; struct SCITXBUF_BITS bit; }; struct SCIFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 Interrupt level Uint16 TXFFIENA:1; // 5 Interrupt enable Uint16 TXFFINTCLR:1; // 6 Clear INT flag Uint16 TXFFINT:1; // 7 INT flag Uint16 TXFFST:5; // 12:8 FIFO status Uint16 TXFIFORESET:1; // 13 FIFO reset Uint16 SCIFFENA:1; // 14 Enhancement enable Uint16 SCIRST:1; // 15 SCI reset rx/tx channels }; union SCIFFTX_REG { Uint16 all; struct SCIFFTX_BITS bit; }; struct SCIFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 Interrupt level Uint16 RXFFIENA:1; // 5 Interrupt enable Uint16 RXFFINTCLR:1; // 6 Clear INT flag Uint16 RXFFINT:1; // 7 INT flag Uint16 RXFFST:5; // 12:8 FIFO status Uint16 RXFIFORESET:1; // 13 FIFO reset Uint16 RXFFOVRCLR:1; // 14 Clear overflow Uint16 RXFFOVF:1; // 15 FIFO overflow }; union SCIFFRX_REG { Uint16 all; struct SCIFFRX_BITS bit; }; struct SCIFFCT_BITS { // bits description Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay Uint16 rsvd1:5; // 12:8 Reserved Uint16 CDC:1; // 13 Auto baud mode enable Uint16 ABDCLR:1; // 14 Auto baud clear Uint16 ABD:1; // 15 Auto baud detect }; union SCIFFCT_REG { Uint16 all; struct SCIFFCT_BITS bit; }; struct SCIPRI_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 FREESOFT:2; // 4:3 Emulation modes Uint16 rsvd2:3; // 7:5 Reserved Uint16 rsvd3:8; // 15:8 Reserved }; union SCIPRI_REG { Uint16 all; struct SCIPRI_BITS bit; }; struct SCI_REGS { union SCICCR_REG SCICCR; // Communications control register union SCICTL1_REG SCICTL1; // Control register 1 union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register union SCILBAUD_REG SCILBAUD; // Baud rate (low) register union SCICTL2_REG SCICTL2; // Control register 2 union SCIRXST_REG SCIRXST; // Recieve status register union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer Uint16 rsvd1; // Reserved union SCITXBUF_REG SCITXBUF; // Transmit data buffer union SCIFFTX_REG SCIFFTX; // FIFO transmit register union SCIFFRX_REG SCIFFRX; // FIFO recieve register union SCIFFCT_REG SCIFFCT; // FIFO control register Uint16 rsvd2[2]; // Reserved union SCIPRI_REG SCIPRI; // SCI Priority control }; //--------------------------------------------------------------------------- // SCI External References & Function Declarations: // extern volatile struct SCI_REGS SciaRegs; extern volatile struct SCI_REGS ScibRegs; extern volatile struct SCI_REGS ScicRegs; extern volatile struct SCI_REGS ScidRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_sdfm.h // // TITLE: F2837xD Device SDFM Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // SDFM Individual Register Bit Definitions: struct SDIFLG_BITS { // bits description Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 Uint16 rsvd1:15; // 30:16 Reserved Uint16 MIF:1; // 31 Master Interrupt Flag }; union SDIFLG_REG { Uint32 all; struct SDIFLG_BITS bit; }; struct SDIFLGCLR_BITS { // bits description Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 Uint16 rsvd1:15; // 30:16 Reserved Uint16 MIF:1; // 31 Master Interrupt Flag }; union SDIFLGCLR_REG { Uint32 all; struct SDIFLGCLR_BITS bit; }; struct SDCTL_BITS { // bits description Uint16 rsvd1:13; // 12:0 Reserved Uint16 MIE:1; // 13 Master Interrupt enable Uint16 rsvd2:1; // 14 Reserved Uint16 rsvd3:1; // 15 Reserved }; union SDCTL_REG { Uint16 all; struct SDCTL_BITS bit; }; struct SDMFILEN_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 rsvd2:3; // 6:4 Reserved Uint16 rsvd3:2; // 8:7 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:1; // 10 Reserved Uint16 MFE:1; // 11 Master Filter Enable. Uint16 rsvd6:1; // 12 Reserved Uint16 rsvd7:3; // 15:13 Reserved }; union SDMFILEN_REG { Uint16 all; struct SDMFILEN_BITS bit; }; struct SDCTLPARM1_BITS { // bits description Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM1_REG { Uint16 all; struct SDCTLPARM1_BITS bit; }; struct SDDFPARM1_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3) Uint16 FILRESEN:1; // 12 Data FILTER Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM1_REG { Uint16 all; struct SDDFPARM1_BITS bit; }; struct SDIPARM1_BITS { // bits description Uint16 rsvd1:7; // 6:0 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDIPARM1_REG { Uint16 all; struct SDIPARM1_BITS bit; }; struct SDCMPH1_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH1_REG { Uint16 all; struct SDCMPH1_BITS bit; }; struct SDCMPL1_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL1_REG { Uint16 all; struct SDCMPL1_BITS bit; }; struct SDCPARM1_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 Uint16 IEH:1; // 5 High-level interrupt enable Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 rsvd1:6; // 15:10 Reserved }; union SDCPARM1_REG { Uint16 all; struct SDCPARM1_BITS bit; }; struct SDDATA1_BITS { // bits description Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode }; union SDDATA1_REG { Uint32 all; struct SDDATA1_BITS bit; }; struct SDCTLPARM2_BITS { // bits description Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM2_REG { Uint16 all; struct SDCTLPARM2_BITS bit; }; struct SDDFPARM2_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3) Uint16 FILRESEN:1; // 12 Data FILTER Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM2_REG { Uint16 all; struct SDDFPARM2_BITS bit; }; struct SDIPARM2_BITS { // bits description Uint16 rsvd1:7; // 6:0 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDIPARM2_REG { Uint16 all; struct SDIPARM2_BITS bit; }; struct SDCMPH2_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH2_REG { Uint16 all; struct SDCMPH2_BITS bit; }; struct SDCMPL2_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL2_REG { Uint16 all; struct SDCMPL2_BITS bit; }; struct SDCPARM2_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 Uint16 IEH:1; // 5 High-level interrupt enable Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 rsvd1:6; // 15:10 Reserved }; union SDCPARM2_REG { Uint16 all; struct SDCPARM2_BITS bit; }; struct SDDATA2_BITS { // bits description Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode }; union SDDATA2_REG { Uint32 all; struct SDDATA2_BITS bit; }; struct SDCTLPARM3_BITS { // bits description Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM3_REG { Uint16 all; struct SDCTLPARM3_BITS bit; }; struct SDDFPARM3_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) Uint16 FILRESEN:1; // 12 Data FILTER Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM3_REG { Uint16 all; struct SDDFPARM3_BITS bit; }; struct SDIPARM3_BITS { // bits description Uint16 rsvd1:7; // 6:0 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDIPARM3_REG { Uint16 all; struct SDIPARM3_BITS bit; }; struct SDCMPH3_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH3_REG { Uint16 all; struct SDCMPH3_BITS bit; }; struct SDCMPL3_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL3_REG { Uint16 all; struct SDCMPL3_BITS bit; }; struct SDCPARM3_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 Uint16 IEH:1; // 5 High-level interrupt enable Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 rsvd1:6; // 15:10 Reserved }; union SDCPARM3_REG { Uint16 all; struct SDCPARM3_BITS bit; }; struct SDDATA3_BITS { // bits description Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode }; union SDDATA3_REG { Uint32 all; struct SDDATA3_BITS bit; }; struct SDCTLPARM4_BITS { // bits description Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM4_REG { Uint16 all; struct SDCTLPARM4_BITS bit; }; struct SDDFPARM4_BITS { // bits description Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) Uint16 FILRESEN:1; // 12 SINC FILTER Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM4_REG { Uint16 all; struct SDDFPARM4_BITS bit; }; struct SDIPARM4_BITS { // bits description Uint16 rsvd1:7; // 6:0 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDIPARM4_REG { Uint16 all; struct SDIPARM4_BITS bit; }; struct SDCMPH4_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH4_REG { Uint16 all; struct SDCMPH4_BITS bit; }; struct SDCMPL4_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL4_REG { Uint16 all; struct SDCMPL4_BITS bit; }; struct SDCPARM4_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 Uint16 IEH:1; // 5 High-level interrupt enable Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 rsvd1:6; // 15:10 Reserved }; union SDCPARM4_REG { Uint16 all; struct SDCPARM4_BITS bit; }; struct SDDATA4_BITS { // bits description Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode }; union SDDATA4_REG { Uint32 all; struct SDDATA4_BITS bit; }; struct SDFM_REGS { union SDIFLG_REG SDIFLG; // Interrupt Flag Register union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register union SDCTL_REG SDCTL; // SD Control Register Uint16 rsvd1; // Reserved union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable Uint16 rsvd2[9]; // Reserved union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 union SDIPARM1_REG SDIPARM1; // Integer Parameter Register for Ch1 union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1 union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1 Uint16 rsvd3[8]; // Reserved union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 union SDIPARM2_REG SDIPARM2; // Integer Parameter Register for Ch2 union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2 union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2 Uint16 rsvd4[8]; // Reserved union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 union SDIPARM3_REG SDIPARM3; // Integer Parameter Register for Ch3 union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3 union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3 Uint16 rsvd5[8]; // Reserved union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 union SDIPARM4_REG SDIPARM4; // Integer Parameter Register for Ch4 union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4 union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4 Uint16 rsvd6[56]; // Reserved }; //--------------------------------------------------------------------------- // SDFM External References & Function Declarations: // extern volatile struct SDFM_REGS Sdfm1Regs; extern volatile struct SDFM_REGS Sdfm2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_spi.h // // TITLE: F2837xD Device SPI Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // SPI Individual Register Bit Definitions: struct SPICCR_BITS { // bits description Uint16 SPICHAR:4; // 3:0 Character Length Control Uint16 SPILBK:1; // 4 SPI Loopback Uint16 HS_MODE:1; // 5 High Speed mode control Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity Uint16 SPISWRESET:1; // 7 SPI Software Reset Uint16 rsvd1:8; // 15:8 Reserved }; union SPICCR_REG { Uint16 all; struct SPICCR_BITS bit; }; struct SPICTL_BITS { // bits description Uint16 SPIINTENA:1; // 0 SPI Interupt Enable Uint16 TALK:1; // 1 Master/Slave Transmit Enable Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control Uint16 CLK_PHASE:1; // 3 SPI Clock Phase Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable Uint16 rsvd1:11; // 15:5 Reserved }; union SPICTL_REG { Uint16 all; struct SPICTL_BITS bit; }; struct SPISTS_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag Uint16 rsvd2:8; // 15:8 Reserved }; union SPISTS_REG { Uint16 all; struct SPISTS_BITS bit; }; struct SPIBRR_BITS { // bits description Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control Uint16 rsvd1:9; // 15:7 Reserved }; union SPIBRR_REG { Uint16 all; struct SPIBRR_BITS bit; }; struct SPIFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag Uint16 TXFFST:5; // 12:8 Transmit FIFO Status Uint16 TXFIFO:1; // 13 TXFIFO Reset Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable Uint16 SPIRST:1; // 15 SPI Reset }; union SPIFFTX_REG { Uint16 all; struct SPIFFTX_BITS bit; }; struct SPIFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag Uint16 RXFFST:5; // 12:8 Receive FIFO Status Uint16 RXFIFORESET:1; // 13 RXFIFO Reset Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag }; union SPIFFRX_REG { Uint16 all; struct SPIFFRX_BITS bit; }; struct SPIFFCT_BITS { // bits description Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits Uint16 rsvd1:8; // 15:8 Reserved }; union SPIFFCT_REG { Uint16 all; struct SPIFFCT_BITS bit; }; struct SPIPRI_BITS { // bits description Uint16 TRIWIRE:1; // 0 3-wire mode select bit Uint16 STEINV:1; // 1 SPISTE inversion bit Uint16 rsvd1:2; // 3:2 Reserved Uint16 FREE:1; // 4 Free emulation mode Uint16 SOFT:1; // 5 Soft emulation mode Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:9; // 15:7 Reserved }; union SPIPRI_REG { Uint16 all; struct SPIPRI_BITS bit; }; struct SPI_REGS { union SPICCR_REG SPICCR; // SPI Configuration Control Register union SPICTL_REG SPICTL; // SPI Operation Control Register union SPISTS_REG SPISTS; // SPI Status Register Uint16 rsvd1; // Reserved union SPIBRR_REG SPIBRR; // SPI Baud Rate Register Uint16 rsvd2; // Reserved Uint16 SPIRXEMU; // SPI Emulation Buffer Register Uint16 SPIRXBUF; // SPI Serial Input Buffer Register Uint16 SPITXBUF; // SPI Serial Output Buffer Register Uint16 SPIDAT; // SPI Serial Data Register union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register Uint16 rsvd3[2]; // Reserved union SPIPRI_REG SPIPRI; // SPI Priority Control Register }; //--------------------------------------------------------------------------- // SPI External References & Function Declarations: // extern volatile struct SPI_REGS SpiaRegs; extern volatile struct SPI_REGS SpibRegs; extern volatile struct SPI_REGS SpicRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_sysctrl.h // // TITLE: F2837xD Device SYSCTRL Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // SYSCTRL Individual Register Bit Definitions: struct DEVCFGLOCK1_BITS { // bits description Uint16 CPUSEL0:1; // 0 Lock bit for CPUSEL0 register Uint16 CPUSEL1:1; // 1 Lock bit for CPUSEL1 register Uint16 CPUSEL2:1; // 2 Lock bit for CPUSEL2 register Uint16 CPUSEL3:1; // 3 Lock bit for CPUSEL3 register Uint16 CPUSEL4:1; // 4 Lock bit for CPUSEL4 register Uint16 CPUSEL5:1; // 5 Lock bit for CPUSEL5 register Uint16 CPUSEL6:1; // 6 Lock bit for CPUSEL6 register Uint16 CPUSEL7:1; // 7 Lock bit for CPUSEL7 register Uint16 CPUSEL8:1; // 8 Lock bit for CPUSEL8 register Uint16 CPUSEL9:1; // 9 Lock bit for CPUSEL9 register Uint16 CPUSEL10:1; // 10 Lock bit for CPUSEL10 register Uint16 CPUSEL11:1; // 11 Lock bit for CPUSEL11 register Uint16 CPUSEL12:1; // 12 Lock bit for CPUSEL12 register Uint16 CPUSEL13:1; // 13 Lock bit for CPUSEL13 register Uint16 CPUSEL14:1; // 14 Lock bit for CPUSEL14 register Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DEVCFGLOCK1_REG { Uint32 all; struct DEVCFGLOCK1_BITS bit; }; struct PARTIDL_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 rsvd2:2; // 4:3 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 QUAL:2; // 7:6 Qualification Status Uint16 PIN_COUNT:3; // 10:8 Device Pin Count Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 INSTASPIN:2; // 14:13 Motorware feature set Uint16 rsvd6:1; // 15 Reserved Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB Uint16 rsvd7:4; // 27:24 Reserved Uint16 PARTID_FORMAT_REVISION:4; // 31:28 Revision of the PARTID format }; union PARTIDL_REG { Uint32 all; struct PARTIDL_BITS bit; }; struct PARTIDH_BITS { // bits description Uint16 rsvd1:8; // 7:0 Reserved Uint16 FAMILY:8; // 15:8 Device family Uint16 PARTNO:8; // 23:16 Device part number Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID }; union PARTIDH_REG { Uint32 all; struct PARTIDH_BITS bit; }; struct DC0_BITS { // bits description Uint16 SINGLE_CORE:1; // 0 Single Core vs Dual Core Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC0_REG { Uint32 all; struct DC0_BITS bit; }; struct DC1_BITS { // bits description Uint16 CPU1_FPU_TMU:1; // 0 CPU1's FPU1+TMU1 Uint16 CPU2_FPU_TMU:1; // 1 CPU2's FPU2+TMU2 Uint16 CPU1_VCU:1; // 2 CPU1's VCU Uint16 CPU2_VCU:1; // 3 CPU2's VCU Uint16 rsvd1:2; // 5:4 Reserved Uint16 CPU1_CLA1:1; // 6 CPU1.CLA1 Uint16 rsvd2:1; // 7 Reserved Uint16 CPU2_CLA1:1; // 8 CPU2.CLA1 Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union DC1_REG { Uint32 all; struct DC1_BITS bit; }; struct DC2_BITS { // bits description Uint16 EMIF1:1; // 0 EMIF1 Uint16 EMIF2:1; // 1 EMIF2 Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC2_REG { Uint32 all; struct DC2_BITS bit; }; struct DC3_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 Uint16 EPWM2:1; // 1 EPWM2 Uint16 EPWM3:1; // 2 EPWM3 Uint16 EPWM4:1; // 3 EPWM4 Uint16 EPWM5:1; // 4 EPWM5 Uint16 EPWM6:1; // 5 EPWM6 Uint16 EPWM7:1; // 6 EPWM7 Uint16 EPWM8:1; // 7 EPWM8 Uint16 EPWM9:1; // 8 EPWM9 Uint16 EPWM10:1; // 9 EPWM10 Uint16 EPWM11:1; // 10 EPWM11 Uint16 EPWM12:1; // 11 EPWM12 Uint16 rsvd1:1; // 12 Reserved Uint16 rsvd2:1; // 13 Reserved Uint16 rsvd3:1; // 14 Reserved Uint16 rsvd4:1; // 15 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union DC3_REG { Uint32 all; struct DC3_BITS bit; }; struct DC4_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 Uint16 ECAP2:1; // 1 ECAP2 Uint16 ECAP3:1; // 2 ECAP3 Uint16 ECAP4:1; // 3 ECAP4 Uint16 ECAP5:1; // 4 ECAP5 Uint16 ECAP6:1; // 5 ECAP6 Uint16 rsvd1:1; // 6 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:8; // 15:8 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DC4_REG { Uint32 all; struct DC4_BITS bit; }; struct DC5_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 Uint16 EQEP2:1; // 1 EQEP2 Uint16 EQEP3:1; // 2 EQEP3 Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union DC5_REG { Uint32 all; struct DC5_BITS bit; }; struct DC7_BITS { // bits description Uint16 SD1:1; // 0 SD1 Uint16 SD2:1; // 1 SD2 Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union DC7_REG { Uint32 all; struct DC7_BITS bit; }; struct DC8_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A Uint16 SCI_B:1; // 1 SCI_B Uint16 SCI_C:1; // 2 SCI_C Uint16 SCI_D:1; // 3 SCI_D Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC8_REG { Uint32 all; struct DC8_BITS bit; }; struct DC9_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A Uint16 SPI_B:1; // 1 SPI_B Uint16 SPI_C:1; // 2 SPI_C Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:1; // 16 Reserved Uint16 rsvd4:1; // 17 Reserved Uint16 rsvd5:14; // 31:18 Reserved }; union DC9_REG { Uint32 all; struct DC9_BITS bit; }; struct DC10_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A Uint16 I2C_B:1; // 1 I2C_B Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union DC10_REG { Uint32 all; struct DC10_BITS bit; }; struct DC11_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A Uint16 CAN_B:1; // 1 CAN_B Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DC11_REG { Uint32 all; struct DC11_BITS bit; }; struct DC12_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A Uint16 McBSP_B:1; // 1 McBSP_B Uint16 rsvd1:14; // 15:2 Reserved Uint16 USB_A:2; // 17:16 Decides the capability of the USB_A Module Uint16 rsvd2:2; // 19:18 Reserved Uint16 rsvd3:12; // 31:20 Reserved }; union DC12_REG { Uint32 all; struct DC12_BITS bit; }; struct DC13_BITS { // bits description Uint16 uPP_A:1; // 0 uPP_A Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union DC13_REG { Uint32 all; struct DC13_BITS bit; }; struct DC14_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A Uint16 ADC_B:1; // 1 ADC_B Uint16 ADC_C:1; // 2 ADC_C Uint16 ADC_D:1; // 3 ADC_D Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC14_REG { Uint32 all; struct DC14_BITS bit; }; struct DC15_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 Uint16 CMPSS2:1; // 1 CMPSS2 Uint16 CMPSS3:1; // 2 CMPSS3 Uint16 CMPSS4:1; // 3 CMPSS4 Uint16 CMPSS5:1; // 4 CMPSS5 Uint16 CMPSS6:1; // 5 CMPSS6 Uint16 CMPSS7:1; // 6 CMPSS7 Uint16 CMPSS8:1; // 7 CMPSS8 Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC15_REG { Uint32 all; struct DC15_BITS bit; }; struct DC17_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 DAC_A:1; // 16 Buffered-DAC_A Uint16 DAC_B:1; // 17 Buffered-DAC_B Uint16 DAC_C:1; // 18 Buffered-DAC_C Uint16 rsvd6:1; // 19 Reserved Uint16 rsvd7:12; // 31:20 Reserved }; union DC17_REG { Uint32 all; struct DC17_BITS bit; }; struct DC18_BITS { // bits description Uint16 LS0_1:1; // 0 LS0_1 Uint16 LS1_1:1; // 1 LS1_1 Uint16 LS2_1:1; // 2 LS2_1 Uint16 LS3_1:1; // 3 LS3_1 Uint16 LS4_1:1; // 4 LS4_1 Uint16 LS5_1:1; // 5 LS5_1 Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC18_REG { Uint32 all; struct DC18_BITS bit; }; struct DC19_BITS { // bits description Uint16 LS0_2:1; // 0 LS0_2 Uint16 LS1_2:1; // 1 LS1_2 Uint16 LS2_2:1; // 2 LS2_2 Uint16 LS3_2:1; // 3 LS3_2 Uint16 LS4_2:1; // 4 LS4_2 Uint16 LS5_2:1; // 5 LS5_2 Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DC19_REG { Uint32 all; struct DC19_BITS bit; }; struct DC20_BITS { // bits description Uint16 GS0:1; // 0 GS0 Uint16 GS1:1; // 1 GS1 Uint16 GS2:1; // 2 GS2 Uint16 GS3:1; // 3 GS3 Uint16 GS4:1; // 4 GS4 Uint16 GS5:1; // 5 GS5 Uint16 GS6:1; // 6 GS6 Uint16 GS7:1; // 7 GS7 Uint16 GS8:1; // 8 GS8 Uint16 GS9:1; // 9 GS9 Uint16 GS10:1; // 10 GS10 Uint16 GS11:1; // 11 GS11 Uint16 GS12:1; // 12 GS12 Uint16 GS13:1; // 13 GS13 Uint16 GS14:1; // 14 GS14 Uint16 GS15:1; // 15 GS15 Uint16 rsvd1:16; // 31:16 Reserved }; union DC20_REG { Uint32 all; struct DC20_BITS bit; }; struct PERCNF1_BITS { // bits description Uint16 ADC_A_MODE:1; // 0 ADC_A mode setting bit Uint16 ADC_B_MODE:1; // 1 ADC_B mode setting bit Uint16 ADC_C_MODE:1; // 2 ADC_C mode setting bit Uint16 ADC_D_MODE:1; // 3 ADC_D mode setting bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 USB_A_PHY:1; // 16 USB_A_PHY Uint16 rsvd2:1; // 17 Reserved Uint16 rsvd3:14; // 31:18 Reserved }; union PERCNF1_REG { Uint32 all; struct PERCNF1_BITS bit; }; struct FUSEERR_BITS { // bits description Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status Uint16 ERR:1; // 5 Efuse Self Test Error Status Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FUSEERR_REG { Uint32 all; struct FUSEERR_BITS bit; }; struct SOFTPRES0_BITS { // bits description Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 CPU2_CLA1:1; // 2 CPU2_CLA1 software reset bit Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union SOFTPRES0_REG { Uint32 all; struct SOFTPRES0_BITS bit; }; struct SOFTPRES1_BITS { // bits description Uint16 EMIF1:1; // 0 EMIF1 software reset bit Uint16 EMIF2:1; // 1 EMIF2 software reset bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES1_REG { Uint32 all; struct SOFTPRES1_BITS bit; }; struct SOFTPRES2_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 software reset bit Uint16 EPWM2:1; // 1 EPWM2 software reset bit Uint16 EPWM3:1; // 2 EPWM3 software reset bit Uint16 EPWM4:1; // 3 EPWM4 software reset bit Uint16 EPWM5:1; // 4 EPWM5 software reset bit Uint16 EPWM6:1; // 5 EPWM6 software reset bit Uint16 EPWM7:1; // 6 EPWM7 software reset bit Uint16 EPWM8:1; // 7 EPWM8 software reset bit Uint16 EPWM9:1; // 8 EPWM9 software reset bit Uint16 EPWM10:1; // 9 EPWM10 software reset bit Uint16 EPWM11:1; // 10 EPWM11 software reset bit Uint16 EPWM12:1; // 11 EPWM12 software reset bit Uint16 rsvd1:1; // 12 Reserved Uint16 rsvd2:1; // 13 Reserved Uint16 rsvd3:1; // 14 Reserved Uint16 rsvd4:1; // 15 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union SOFTPRES2_REG { Uint32 all; struct SOFTPRES2_BITS bit; }; struct SOFTPRES3_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 software reset bit Uint16 ECAP2:1; // 1 ECAP2 software reset bit Uint16 ECAP3:1; // 2 ECAP3 software reset bit Uint16 ECAP4:1; // 3 ECAP4 software reset bit Uint16 ECAP5:1; // 4 ECAP5 software reset bit Uint16 ECAP6:1; // 5 ECAP6 software reset bit Uint16 rsvd1:1; // 6 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:8; // 15:8 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union SOFTPRES3_REG { Uint32 all; struct SOFTPRES3_BITS bit; }; struct SOFTPRES4_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 software reset bit Uint16 EQEP2:1; // 1 EQEP2 software reset bit Uint16 EQEP3:1; // 2 EQEP3 software reset bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES4_REG { Uint32 all; struct SOFTPRES4_BITS bit; }; struct SOFTPRES6_BITS { // bits description Uint16 SD1:1; // 0 SD1 software reset bit Uint16 SD2:1; // 1 SD2 software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union SOFTPRES6_REG { Uint32 all; struct SOFTPRES6_BITS bit; }; struct SOFTPRES7_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A software reset bit Uint16 SCI_B:1; // 1 SCI_B software reset bit Uint16 SCI_C:1; // 2 SCI_C software reset bit Uint16 SCI_D:1; // 3 SCI_D software reset bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES7_REG { Uint32 all; struct SOFTPRES7_BITS bit; }; struct SOFTPRES8_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A software reset bit Uint16 SPI_B:1; // 1 SPI_B software reset bit Uint16 SPI_C:1; // 2 SPI_C software reset bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:1; // 16 Reserved Uint16 rsvd4:1; // 17 Reserved Uint16 rsvd5:14; // 31:18 Reserved }; union SOFTPRES8_REG { Uint32 all; struct SOFTPRES8_BITS bit; }; struct SOFTPRES9_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A software reset bit Uint16 I2C_B:1; // 1 I2C_B software reset bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union SOFTPRES9_REG { Uint32 all; struct SOFTPRES9_BITS bit; }; struct SOFTPRES11_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A software reset bit Uint16 McBSP_B:1; // 1 McBSP_B software reset bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 USB_A:1; // 16 USB_A software reset bit Uint16 rsvd2:1; // 17 Reserved Uint16 rsvd3:14; // 31:18 Reserved }; union SOFTPRES11_REG { Uint32 all; struct SOFTPRES11_BITS bit; }; struct SOFTPRES13_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A software reset bit Uint16 ADC_B:1; // 1 ADC_B software reset bit Uint16 ADC_C:1; // 2 ADC_C software reset bit Uint16 ADC_D:1; // 3 ADC_D software reset bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES13_REG { Uint32 all; struct SOFTPRES13_BITS bit; }; struct SOFTPRES14_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit Uint16 CMPSS8:1; // 7 CMPSS8 software reset bit Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES14_REG { Uint32 all; struct SOFTPRES14_BITS bit; }; struct SOFTPRES16_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit Uint16 DAC_C:1; // 18 Buffered_DAC_C software reset bit Uint16 rsvd6:1; // 19 Reserved Uint16 rsvd7:12; // 31:20 Reserved }; union SOFTPRES16_REG { Uint32 all; struct SOFTPRES16_BITS bit; }; struct CPUSEL0_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 CPU select bit Uint16 EPWM2:1; // 1 EPWM2 CPU select bit Uint16 EPWM3:1; // 2 EPWM3 CPU select bit Uint16 EPWM4:1; // 3 EPWM4 CPU select bit Uint16 EPWM5:1; // 4 EPWM5 CPU select bit Uint16 EPWM6:1; // 5 EPWM6 CPU select bit Uint16 EPWM7:1; // 6 EPWM7 CPU select bit Uint16 EPWM8:1; // 7 EPWM8 CPU select bit Uint16 EPWM9:1; // 8 EPWM9 CPU select bit Uint16 EPWM10:1; // 9 EPWM10 CPU select bit Uint16 EPWM11:1; // 10 EPWM11 CPU select bit Uint16 EPWM12:1; // 11 EPWM12 CPU select bit Uint16 rsvd1:1; // 12 Reserved Uint16 rsvd2:1; // 13 Reserved Uint16 rsvd3:1; // 14 Reserved Uint16 rsvd4:1; // 15 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union CPUSEL0_REG { Uint32 all; struct CPUSEL0_BITS bit; }; struct CPUSEL1_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 CPU select bit Uint16 ECAP2:1; // 1 ECAP2 CPU select bit Uint16 ECAP3:1; // 2 ECAP3 CPU select bit Uint16 ECAP4:1; // 3 ECAP4 CPU select bit Uint16 ECAP5:1; // 4 ECAP5 CPU select bit Uint16 ECAP6:1; // 5 ECAP6 CPU select bit Uint16 rsvd1:1; // 6 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:8; // 15:8 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CPUSEL1_REG { Uint32 all; struct CPUSEL1_BITS bit; }; struct CPUSEL2_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 CPU select bit Uint16 EQEP2:1; // 1 EQEP2 CPU select bit Uint16 EQEP3:1; // 2 EQEP3 CPU select bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CPUSEL2_REG { Uint32 all; struct CPUSEL2_BITS bit; }; struct CPUSEL4_BITS { // bits description Uint16 SD1:1; // 0 SD1 CPU select bit Uint16 SD2:1; // 1 SD2 CPU select bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union CPUSEL4_REG { Uint32 all; struct CPUSEL4_BITS bit; }; struct CPUSEL5_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A CPU select bit Uint16 SCI_B:1; // 1 SCI_B CPU select bit Uint16 SCI_C:1; // 2 SCI_C CPU select bit Uint16 SCI_D:1; // 3 SCI_D CPU select bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL5_REG { Uint32 all; struct CPUSEL5_BITS bit; }; struct CPUSEL6_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A CPU select bit Uint16 SPI_B:1; // 1 SPI_B CPU select bit Uint16 SPI_C:1; // 2 SPI_C CPU select bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:1; // 16 Reserved Uint16 rsvd4:1; // 17 Reserved Uint16 rsvd5:14; // 31:18 Reserved }; union CPUSEL6_REG { Uint32 all; struct CPUSEL6_BITS bit; }; struct CPUSEL7_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A CPU select bit Uint16 I2C_B:1; // 1 I2C_B CPU select bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union CPUSEL7_REG { Uint32 all; struct CPUSEL7_BITS bit; }; struct CPUSEL8_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A CPU select bit Uint16 CAN_B:1; // 1 CAN_B CPU select bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CPUSEL8_REG { Uint32 all; struct CPUSEL8_BITS bit; }; struct CPUSEL9_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A CPU select bit Uint16 McBSP_B:1; // 1 McBSP_B CPU select bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL9_REG { Uint32 all; struct CPUSEL9_BITS bit; }; struct CPUSEL11_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A CPU select bit Uint16 ADC_B:1; // 1 ADC_B CPU select bit Uint16 ADC_C:1; // 2 ADC_C CPU select bit Uint16 ADC_D:1; // 3 ADC_D CPU select bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL11_REG { Uint32 all; struct CPUSEL11_BITS bit; }; struct CPUSEL12_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 CPU select bit Uint16 CMPSS2:1; // 1 CMPSS2 CPU select bit Uint16 CMPSS3:1; // 2 CMPSS3 CPU select bit Uint16 CMPSS4:1; // 3 CMPSS4 CPU select bit Uint16 CMPSS5:1; // 4 CMPSS5 CPU select bit Uint16 CMPSS6:1; // 5 CMPSS6 CPU select bit Uint16 CMPSS7:1; // 6 CMPSS7 CPU select bit Uint16 CMPSS8:1; // 7 CMPSS8 CPU select bit Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL12_REG { Uint32 all; struct CPUSEL12_BITS bit; }; struct CPUSEL14_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC_A CPU select bit Uint16 DAC_B:1; // 17 Buffered_DAC_B CPU select bit Uint16 DAC_C:1; // 18 Buffered_DAC_C CPU select bit Uint16 rsvd6:1; // 19 Reserved Uint16 rsvd7:12; // 31:20 Reserved }; union CPUSEL14_REG { Uint32 all; struct CPUSEL14_BITS bit; }; struct CPU2RESCTL_BITS { // bits description Uint16 RESET:1; // 0 CPU2 Reset Control bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register }; union CPU2RESCTL_REG { Uint32 all; struct CPU2RESCTL_BITS bit; }; struct RSTSTAT_BITS { // bits description Uint16 CPU2RES:1; // 0 CPU2 Reset Status bit Uint16 CPU2NMIWDRST:1; // 1 Indicates whether a CPU2.NMIWD reset was issued to CPU2 Uint16 CPU2HWBISTRST0:1; // 2 Indicates whether a HWBIST reset was issued to CPU2 Uint16 CPU2HWBISTRST1:1; // 3 Indicates whether a HWBIST reset was issued to CPU2 Uint16 rsvd1:12; // 15:4 Reserved }; union RSTSTAT_REG { Uint16 all; struct RSTSTAT_BITS bit; }; struct LPMSTAT_BITS { // bits description Uint16 CPU2LPMSTAT:2; // 1:0 CPU2 LPM Status Uint16 rsvd1:14; // 15:2 Reserved }; union LPMSTAT_REG { Uint16 all; struct LPMSTAT_BITS bit; }; struct SYSDBGCTL_BITS { // bits description Uint16 BIT_0:1; // 0 Used in PLL startup. Only reset by POR. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSDBGCTL_REG { Uint32 all; struct SYSDBGCTL_BITS bit; }; struct DEV_CFG_REGS { union DEVCFGLOCK1_REG DEVCFGLOCK1; // Lock bit for CPUSELx registers Uint16 rsvd1[6]; // Reserved union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number Uint32 REVID; // Device Revision Number Uint16 rsvd2[2]; // Reserved union DC0_REG DC0; // Device Capability: Device Information union DC1_REG DC1; // Device Capability: Processing Block Customization union DC2_REG DC2; // Device Capability: EMIF Customization union DC3_REG DC3; // Device Capability: Peripheral Customization union DC4_REG DC4; // Device Capability: Peripheral Customization union DC5_REG DC5; // Device Capability: Peripheral Customization Uint16 rsvd3[2]; // Reserved union DC7_REG DC7; // Device Capability: Peripheral Customization union DC8_REG DC8; // Device Capability: Peripheral Customization union DC9_REG DC9; // Device Capability: Peripheral Customization union DC10_REG DC10; // Device Capability: Peripheral Customization union DC11_REG DC11; // Device Capability: Peripheral Customization union DC12_REG DC12; // Device Capability: Peripheral Customization union DC13_REG DC13; // Device Capability: Peripheral Customization union DC14_REG DC14; // Device Capability: Analog Modules Customization union DC15_REG DC15; // Device Capability: Analog Modules Customization Uint16 rsvd4[2]; // Reserved union DC17_REG DC17; // Device Capability: Analog Modules Customization union DC18_REG DC18; // Device Capability: CPU1 Lx SRAM Customization union DC19_REG DC19; // Device Capability: CPU2 Lx SRAM Customization union DC20_REG DC20; // Device Capability: GSx SRAM Customization Uint16 rsvd5[38]; // Reserved union PERCNF1_REG PERCNF1; // Peripheral Configuration register Uint16 rsvd6[18]; // Reserved union FUSEERR_REG FUSEERR; // e-Fuse error Status register Uint16 rsvd7[12]; // Reserved union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register union SOFTPRES1_REG SOFTPRES1; // EMIF Software Reset register union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register Uint16 rsvd8[2]; // Reserved union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register Uint16 rsvd9[2]; // Reserved union SOFTPRES11_REG SOFTPRES11; // Peripheral Software Reset register Uint16 rsvd10[2]; // Reserved union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register Uint16 rsvd11[2]; // Reserved union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register Uint16 rsvd12[50]; // Reserved union CPUSEL0_REG CPUSEL0; // CPU Select register for common peripherals union CPUSEL1_REG CPUSEL1; // CPU Select register for common peripherals union CPUSEL2_REG CPUSEL2; // CPU Select register for common peripherals Uint16 rsvd13[2]; // Reserved union CPUSEL4_REG CPUSEL4; // CPU Select register for common peripherals union CPUSEL5_REG CPUSEL5; // CPU Select register for common peripherals union CPUSEL6_REG CPUSEL6; // CPU Select register for common peripherals union CPUSEL7_REG CPUSEL7; // CPU Select register for common peripherals union CPUSEL8_REG CPUSEL8; // CPU Select register for common peripherals union CPUSEL9_REG CPUSEL9; // CPU Select register for common peripherals Uint16 rsvd14[2]; // Reserved union CPUSEL11_REG CPUSEL11; // CPU Select register for common peripherals union CPUSEL12_REG CPUSEL12; // CPU Select register for common peripherals Uint16 rsvd15[2]; // Reserved union CPUSEL14_REG CPUSEL14; // CPU Select register for common peripherals Uint16 rsvd16[46]; // Reserved union CPU2RESCTL_REG CPU2RESCTL; // CPU2 Reset Control Register union RSTSTAT_REG RSTSTAT; // Reset Status register for secondary C28x CPUs union LPMSTAT_REG LPMSTAT; // LPM Status Register for secondary C28x CPUs Uint16 rsvd17[6]; // Reserved union SYSDBGCTL_REG SYSDBGCTL; // System Debug Control register }; struct CLKSEM_BITS { // bits description Uint16 SEM:2; // 1:0 Semaphore for CLKCFG Ownership by CPU1 or CPU2 Uint16 rsvd1:14; // 15:2 Reserved Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register }; union CLKSEM_REG { Uint32 all; struct CLKSEM_BITS bit; }; struct CLKCFGLOCK1_BITS { // bits description Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register Uint16 SYSPLLCTL2:1; // 4 Lock bit for SYSPLLCTL2 register Uint16 SYSPLLCTL3:1; // 5 Lock bit for SYSPLLCTL3 register Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register Uint16 AUXPLLCTL1:1; // 7 Lock bit for AUXPLLCTL1 register Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 AUXPLLMULT:1; // 10 Lock bit for AUXPLLMULT register Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register Uint16 AUXCLKDIVSEL:1; // 12 Lock bit for AUXCLKDIVSEL register Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register Uint16 rsvd3:1; // 14 Reserved Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register Uint16 rsvd4:16; // 31:16 Reserved }; union CLKCFGLOCK1_REG { Uint32 all; struct CLKCFGLOCK1_BITS bit; }; struct CLKSRCCTL1_BITS { // bits description Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit Uint16 rsvd1:1; // 2 Reserved Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit Uint16 XTALOFF:1; // 4 Crystal (External) Oscillator Off Bit Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLKSRCCTL1_REG { Uint32 all; struct CLKSRCCTL1_BITS bit; }; struct CLKSRCCTL2_BITS { // bits description Uint16 AUXOSCCLKSRCSEL:2; // 1:0 AUXOSCCLK Source Select Bit Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit Uint16 rsvd1:2; // 7:6 Reserved Uint16 rsvd2:2; // 9:8 Reserved Uint16 rsvd3:6; // 15:10 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CLKSRCCTL2_REG { Uint32 all; struct CLKSRCCTL2_BITS bit; }; struct CLKSRCCTL3_BITS { // bits description Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLKSRCCTL3_REG { Uint32 all; struct CLKSRCCTL3_BITS bit; }; struct SYSPLLCTL1_BITS { // bits description Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSPLLCTL1_REG { Uint32 all; struct SYSPLLCTL1_BITS bit; }; struct SYSPLLMULT_BITS { // bits description Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier Uint16 rsvd1:1; // 7 Reserved Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier Uint16 rsvd2:6; // 15:10 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SYSPLLMULT_REG { Uint32 all; struct SYSPLLMULT_BITS bit; }; struct SYSPLLSTS_BITS { // bits description Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSPLLSTS_REG { Uint32 all; struct SYSPLLSTS_BITS bit; }; struct AUXPLLCTL1_BITS { // bits description Uint16 PLLEN:1; // 0 AUXPLL enable/disable bit Uint16 PLLCLKEN:1; // 1 AUXPLL bypassed or included in the AUXPLLCLK path Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union AUXPLLCTL1_REG { Uint32 all; struct AUXPLLCTL1_BITS bit; }; struct AUXPLLMULT_BITS { // bits description Uint16 IMULT:7; // 6:0 AUXPLL Integer Multiplier Uint16 rsvd1:1; // 7 Reserved Uint16 FMULT:2; // 9:8 AUXPLL Fractional Multiplier Uint16 rsvd2:6; // 15:10 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union AUXPLLMULT_REG { Uint32 all; struct AUXPLLMULT_BITS bit; }; struct AUXPLLSTS_BITS { // bits description Uint16 LOCKS:1; // 0 AUXPLL Lock Status Bit Uint16 SLIPS:1; // 1 AUXPLL Slip Status Bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union AUXPLLSTS_REG { Uint32 all; struct AUXPLLSTS_BITS bit; }; struct SYSCLKDIVSEL_BITS { // bits description Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSCLKDIVSEL_REG { Uint32 all; struct SYSCLKDIVSEL_BITS bit; }; struct AUXCLKDIVSEL_BITS { // bits description Uint16 AUXPLLDIV:2; // 1:0 AUXPLLCLK Divide Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union AUXCLKDIVSEL_REG { Uint32 all; struct AUXCLKDIVSEL_BITS bit; }; struct PERCLKDIVSEL_BITS { // bits description Uint16 EPWMCLKDIV:2; // 1:0 EPWM Clock Divide Select Uint16 rsvd1:2; // 3:2 Reserved Uint16 EMIF1CLKDIV:1; // 4 EMIF1 Clock Divide Select Uint16 rsvd2:1; // 5 Reserved Uint16 EMIF2CLKDIV:1; // 6 EMIF2 Clock Divide Select Uint16 rsvd3:9; // 15:7 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PERCLKDIVSEL_REG { Uint32 all; struct PERCLKDIVSEL_BITS bit; }; struct XCLKOUTDIVSEL_BITS { // bits description Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union XCLKOUTDIVSEL_REG { Uint32 all; struct XCLKOUTDIVSEL_BITS bit; }; struct LOSPCP_BITS { // bits description Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LOSPCP_REG { Uint32 all; struct LOSPCP_BITS bit; }; struct MCDCR_BITS { // bits description Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCDCR_REG { Uint32 all; struct MCDCR_BITS bit; }; struct X1CNT_BITS { // bits description Uint16 X1CNT:10; // 9:0 X1 Counter Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union X1CNT_REG { Uint32 all; struct X1CNT_BITS bit; }; struct CLK_CFG_REGS { union CLKSEM_REG CLKSEM; // Clock Control Semaphore Register union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers Uint16 rsvd1[4]; // Reserved union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 Uint16 rsvd2[4]; // Reserved union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register union AUXPLLCTL1_REG AUXPLLCTL1; // AUXPLL Control register-1 Uint16 rsvd3[4]; // Reserved union AUXPLLMULT_REG AUXPLLMULT; // AUXPLL Multiplier register union AUXPLLSTS_REG AUXPLLSTS; // AUXPLL Status register union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register union AUXCLKDIVSEL_REG AUXCLKDIVSEL; // Auxillary Clock Divider Select register union PERCLKDIVSEL_REG PERCLKDIVSEL; // Peripheral Clock Divider Selet register union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register Uint16 rsvd4[2]; // Reserved union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar union MCDCR_REG MCDCR; // Missing Clock Detect Control Register union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock }; struct CPUSYSLOCK1_BITS { // bits description Uint16 HIBBOOTMODE:1; // 0 Lock bit for HIBBOOTMODE register Uint16 IORESTOREADDR:1; // 1 Lock bit for IORESTOREADDR Register Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register Uint16 PCLKCR1:1; // 4 Lock bit for PCLKCR1 Register Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register Uint16 PCLKCR5:1; // 8 Lock bit for PCLKCR5 Register Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register Uint16 PCLKCR11:1; // 14 Lock bit for PCLKCR11 Register Uint16 PCLKCR12:1; // 15 Lock bit for PCLKCR12 Register Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register Uint16 SECMSEL:1; // 20 Lock bit for SECMSEL Register Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register Uint16 rsvd1:8; // 31:24 Reserved }; union CPUSYSLOCK1_REG { Uint32 all; struct CPUSYSLOCK1_BITS bit; }; struct IORESTOREADDR_BITS { // bits description Uint32 ADDR:22; // 21:0 restoreIO() routine address Uint16 rsvd1:10; // 31:22 Reserved }; union IORESTOREADDR_REG { Uint32 all; struct IORESTOREADDR_BITS bit; }; struct PIEVERRADDR_BITS { // bits description Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address Uint16 rsvd1:10; // 31:22 Reserved }; union PIEVERRADDR_REG { Uint32 all; struct PIEVERRADDR_BITS bit; }; struct PCLKCR0_BITS { // bits description Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit Uint16 rsvd1:1; // 1 Reserved Uint16 DMA:1; // 2 DMA Clock Enable bit Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit Uint16 rsvd2:10; // 15:6 Reserved Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit Uint16 rsvd3:1; // 17 Reserved Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync Uint16 GTBCLKSYNC:1; // 19 EPWM Time Base Clock Global sync Uint16 rsvd4:12; // 31:20 Reserved }; union PCLKCR0_REG { Uint32 all; struct PCLKCR0_BITS bit; }; struct PCLKCR1_BITS { // bits description Uint16 EMIF1:1; // 0 EMIF1 Clock Enable bit Uint16 EMIF2:1; // 1 EMIF2 Clock Enable bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR1_REG { Uint32 all; struct PCLKCR1_BITS bit; }; struct PCLKCR2_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit Uint16 EPWM9:1; // 8 EPWM9 Clock Enable bit Uint16 EPWM10:1; // 9 EPWM10 Clock Enable bit Uint16 EPWM11:1; // 10 EPWM11 Clock Enable bit Uint16 EPWM12:1; // 11 EPWM12 Clock Enable bit Uint16 rsvd1:1; // 12 Reserved Uint16 rsvd2:1; // 13 Reserved Uint16 rsvd3:1; // 14 Reserved Uint16 rsvd4:1; // 15 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union PCLKCR2_REG { Uint32 all; struct PCLKCR2_BITS bit; }; struct PCLKCR3_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit Uint16 rsvd1:1; // 6 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:8; // 15:8 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PCLKCR3_REG { Uint32 all; struct PCLKCR3_BITS bit; }; struct PCLKCR4_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit Uint16 EQEP3:1; // 2 EQEP3 Clock Enable bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR4_REG { Uint32 all; struct PCLKCR4_BITS bit; }; struct PCLKCR6_BITS { // bits description Uint16 SD1:1; // 0 SD1 Clock Enable bit Uint16 SD2:1; // 1 SD2 Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union PCLKCR6_REG { Uint32 all; struct PCLKCR6_BITS bit; }; struct PCLKCR7_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit Uint16 SCI_C:1; // 2 SCI_C Clock Enable bit Uint16 SCI_D:1; // 3 SCI_D Clock Enable bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR7_REG { Uint32 all; struct PCLKCR7_BITS bit; }; struct PCLKCR8_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit Uint16 SPI_C:1; // 2 SPI_C Clock Enable bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:1; // 16 Reserved Uint16 rsvd4:1; // 17 Reserved Uint16 rsvd5:14; // 31:18 Reserved }; union PCLKCR8_REG { Uint32 all; struct PCLKCR8_BITS bit; }; struct PCLKCR9_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit Uint16 I2C_B:1; // 1 I2C_B Clock Enable bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union PCLKCR9_REG { Uint32 all; struct PCLKCR9_BITS bit; }; struct PCLKCR10_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PCLKCR10_REG { Uint32 all; struct PCLKCR10_BITS bit; }; struct PCLKCR11_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A Clock Enable bit Uint16 McBSP_B:1; // 1 McBSP_B Clock Enable bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 USB_A:1; // 16 USB_A Clock Enable bit Uint16 rsvd2:1; // 17 Reserved Uint16 rsvd3:14; // 31:18 Reserved }; union PCLKCR11_REG { Uint32 all; struct PCLKCR11_BITS bit; }; struct PCLKCR12_BITS { // bits description Uint16 uPP_A:1; // 0 uPP_A Clock Enable bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR12_REG { Uint32 all; struct PCLKCR12_BITS bit; }; struct PCLKCR13_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit Uint16 ADC_D:1; // 3 ADC_D Clock Enable bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR13_REG { Uint32 all; struct PCLKCR13_BITS bit; }; struct PCLKCR14_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit Uint16 CMPSS8:1; // 7 CMPSS8 Clock Enable bit Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR14_REG { Uint32 all; struct PCLKCR14_BITS bit; }; struct PCLKCR16_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit Uint16 DAC_C:1; // 18 Buffered_DAC_C Clock Enable Bit Uint16 rsvd6:1; // 19 Reserved Uint16 rsvd7:12; // 31:20 Reserved }; union PCLKCR16_REG { Uint32 all; struct PCLKCR16_BITS bit; }; struct SECMSEL_BITS { // bits description Uint16 PF1SEL:2; // 1:0 Secondary Master Select for VBUS32_1 Bridge Uint16 PF2SEL:2; // 3:2 Secondary Master Select for VBUS32_2 Bridge Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:2; // 7:6 Reserved Uint16 rsvd3:2; // 9:8 Reserved Uint16 rsvd4:2; // 11:10 Reserved Uint16 rsvd5:2; // 13:12 Reserved Uint16 rsvd6:2; // 15:14 Reserved Uint16 rsvd7:16; // 31:16 Reserved }; union SECMSEL_REG { Uint32 all; struct SECMSEL_BITS bit; }; struct LPMCR_BITS { // bits description Uint16 LPM:2; // 1:0 Low Power Mode setting Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting Uint16 rsvd1:7; // 14:8 Reserved Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY Uint16 M0M1MODE:2; // 17:16 Configuration for M0 and M1 mode during HIB Uint16 rsvd2:13; // 30:18 Reserved Uint16 IOISODIS:1; // 31 IO Isolation Disable }; union LPMCR_REG { Uint32 all; struct LPMCR_BITS bit; }; struct GPIOLPMSEL0_BITS { // bits description Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup }; union GPIOLPMSEL0_REG { Uint32 all; struct GPIOLPMSEL0_BITS bit; }; struct GPIOLPMSEL1_BITS { // bits description Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup }; union GPIOLPMSEL1_REG { Uint32 all; struct GPIOLPMSEL1_BITS bit; }; struct TMR2CLKCTL_BITS { // bits description Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union TMR2CLKCTL_REG { Uint32 all; struct TMR2CLKCTL_BITS bit; }; struct RESC_BITS { // bits description Uint16 POR:1; // 0 POR Reset Cause Indication Bit Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit Uint16 rsvd1:1; // 4 Reserved Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit Uint16 HIBRESETn:1; // 6 HIBRESETn Reset Cause Indication Bit Uint16 rsvd2:1; // 7 Reserved Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit Uint16 rsvd3:7; // 15:9 Reserved Uint16 rsvd4:14; // 29:16 Reserved Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status Uint16 TRSTn_pin_status:1; // 31 TRSTn Status }; union RESC_REG { Uint32 all; struct RESC_BITS bit; }; struct CPU_SYS_REGS { union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers Uint16 rsvd1[4]; // Reserved Uint32 HIBBOOTMODE; // HIB Boot Mode Register union IORESTOREADDR_REG IORESTOREADDR; // IORestore() routine Address Register union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register Uint16 rsvd2[22]; // Reserved union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers union PCLKCR1_REG PCLKCR1; // Peripheral Clock Gating Registers union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers Uint16 rsvd3[2]; // Reserved union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers union PCLKCR11_REG PCLKCR11; // Peripheral Clock Gating Registers union PCLKCR12_REG PCLKCR12; // Peripheral Clock Gating Registers union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers Uint16 rsvd4[2]; // Reserved union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers Uint16 rsvd5[48]; // Reserved union SECMSEL_REG SECMSEL; // Secondary Master Select register for common peripherals: Selects between CLA & DMA union LPMCR_REG LPMCR; // LPM Control Register union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register Uint16 rsvd6[2]; // Reserved union RESC_REG RESC; // Reset Cause register }; struct SCSR_BITS { // bits description Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit Uint16 WDENINT:1; // 1 WD Interrupt Enable Uint16 WDINTS:1; // 2 WD Interrupt Status Uint16 rsvd1:13; // 15:3 Reserved }; union SCSR_REG { Uint16 all; struct SCSR_BITS bit; }; struct WDCNTR_BITS { // bits description Uint16 WDCNTR:8; // 7:0 WD Counter Uint16 rsvd1:8; // 15:8 Reserved }; union WDCNTR_REG { Uint16 all; struct WDCNTR_BITS bit; }; struct WDKEY_BITS { // bits description Uint16 WDKEY:8; // 7:0 WD KEY Uint16 rsvd1:8; // 15:8 Reserved }; union WDKEY_REG { Uint16 all; struct WDKEY_BITS bit; }; struct WDCR_BITS { // bits description Uint16 WDPS:3; // 2:0 WD Clock Prescalar Uint16 WDCHK:3; // 5:3 WD Check Bits Uint16 WDDIS:1; // 6 WD Disable Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved }; union WDCR_REG { Uint16 all; struct WDCR_BITS bit; }; struct WDWCR_BITS { // bits description Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality Uint16 FIRSTKEY:1; // 8 First Key Detect Flag Uint16 rsvd1:7; // 15:9 Reserved }; union WDWCR_REG { Uint16 all; struct WDWCR_BITS bit; }; struct WD_REGS { Uint16 rsvd1[34]; // Reserved union SCSR_REG SCSR; // System Control & Status Register union WDCNTR_REG WDCNTR; // Watchdog Counter Register Uint16 rsvd2; // Reserved union WDKEY_REG WDKEY; // Watchdog Reset Key Register Uint16 rsvd3[3]; // Reserved union WDCR_REG WDCR; // Watchdog Control Register union WDWCR_REG WDWCR; // Watchdog Windowed Control Register }; struct CLA1TASKSRCSELLOCK_BITS { // bits description Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLA1TASKSRCSELLOCK_REG { Uint32 all; struct CLA1TASKSRCSELLOCK_BITS bit; }; struct DMACHSRCSELLOCK_BITS { // bits description Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DMACHSRCSELLOCK_REG { Uint32 all; struct DMACHSRCSELLOCK_BITS bit; }; struct CLA1TASKSRCSEL1_BITS { // bits description Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 }; union CLA1TASKSRCSEL1_REG { Uint32 all; struct CLA1TASKSRCSEL1_BITS bit; }; struct CLA1TASKSRCSEL2_BITS { // bits description Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 }; union CLA1TASKSRCSEL2_REG { Uint32 all; struct CLA1TASKSRCSEL2_BITS bit; }; struct DMACHSRCSEL1_BITS { // bits description Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA }; union DMACHSRCSEL1_REG { Uint32 all; struct DMACHSRCSEL1_BITS bit; }; struct DMACHSRCSEL2_BITS { // bits description Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA Uint16 rsvd1:16; // 31:16 Reserved }; union DMACHSRCSEL2_REG { Uint32 all; struct DMACHSRCSEL2_BITS bit; }; struct DMA_CLA_SRC_SEL_REGS { union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register Uint16 rsvd1[2]; // Reserved union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 Uint16 rsvd2[12]; // Reserved union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 }; struct SYNCSELECT_BITS { // bits description Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 Uint16 EPWM10SYNCIN:3; // 8:6 Selects Sync Input Source for EPWM10 Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:11; // 26:16 Reserved Uint16 SYNCOUT:2; // 28:27 Select Syncout Source Uint16 rsvd3:3; // 31:29 Reserved }; union SYNCSELECT_REG { Uint32 all; struct SYNCSELECT_BITS bit; }; struct ADCSOCOUTSELECT_BITS { // bits description Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAO Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAO Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAO Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAO Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAO Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAO Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAO Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAO Uint16 PWM9SOCAEN:1; // 8 PWM9SOCAEN Enable for ADCSOCAO Uint16 PWM10SOCAEN:1; // 9 PWM10SOCAEN Enable for ADCSOCAO Uint16 PWM11SOCAEN:1; // 10 PWM11SOCAEN Enable for ADCSOCAO Uint16 PWM12SOCAEN:1; // 11 PWM12SOCAEN Enable for ADCSOCAO Uint16 rsvd1:4; // 15:12 Reserved Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBO Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBO Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBO Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBO Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBO Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBO Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBO Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBO Uint16 PWM9SOCBEN:1; // 24 PWM9SOCBEN Enable for ADCSOCBO Uint16 PWM10SOCBEN:1; // 25 PWM10SOCBEN Enable for ADCSOCBO Uint16 PWM11SOCBEN:1; // 26 PWM11SOCBEN Enable for ADCSOCBO Uint16 PWM12SOCBEN:1; // 27 PWM12SOCBEN Enable for ADCSOCBO Uint16 rsvd2:4; // 31:28 Reserved }; union ADCSOCOUTSELECT_REG { Uint32 all; struct ADCSOCOUTSELECT_BITS bit; }; struct SYNCSOCLOCK_BITS { // bits description Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYNCSOCLOCK_REG { Uint32 all; struct SYNCSOCLOCK_BITS bit; }; struct SYNC_SOC_REGS { union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADC (Off Chip) SOC Select Register union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register }; //--------------------------------------------------------------------------- // SYSCTRL External References & Function Declarations: // extern volatile struct WD_REGS WdRegs; extern volatile struct SYNC_SOC_REGS SyncSocRegs; extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; extern volatile struct DEV_CFG_REGS DevCfgRegs; extern volatile struct CLK_CFG_REGS ClkCfgRegs; extern volatile struct CPU_SYS_REGS CpuSysRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_upp.h // // TITLE: F2837xD Device UPP Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // UPP Individual Register Bit Definitions: struct PERCTL_BITS { // bits description Uint16 FREE:1; // 0 Emulation control. Uint16 SOFT:1; // 1 Emulation control. Uint16 RTEMU:1; // 2 Realtime emulation control. Uint16 PEREN:1; // 3 Peripheral Enable Uint16 SOFTRST:1; // 4 Software Reset Uint16 rsvd1:2; // 6:5 Reserved Uint16 DMAST:1; // 7 DMA Burst transaction status Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PERCTL_REG { Uint32 all; struct PERCTL_BITS bit; }; struct CHCTL_BITS { // bits description Uint16 MODE:2; // 1:0 Operating mode Uint16 rsvd1:1; // 2 Reserved Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode Uint16 rsvd2:11; // 15:5 Reserved Uint16 DRA:1; // 16 Data rate Uint16 rsvd3:14; // 30:17 Reserved Uint16 rsvd4:1; // 31 Reserved }; union CHCTL_REG { Uint32 all; struct CHCTL_BITS bit; }; struct IFCFG_BITS { // bits description Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal. Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal Uint16 WAITA:1; // 5 Enable Usage of WAIT signal Uint16 rsvd1:2; // 7:6 Reserved Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode Uint16 CLKINVA:1; // 12 Clock inversion Uint16 TRISENA:1; // 13 Pin Tri-state Control Uint16 rsvd2:2; // 15:14 Reserved Uint16 rsvd3:6; // 21:16 Reserved Uint16 rsvd4:2; // 23:22 Reserved Uint16 rsvd5:6; // 29:24 Reserved Uint16 rsvd6:2; // 31:30 Reserved }; union IFCFG_REG { Uint32 all; struct IFCFG_BITS bit; }; struct IFIVAL_BITS { // bits description Uint16 VALA:9; // 8:0 Idle Value Uint16 rsvd1:7; // 15:9 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union IFIVAL_REG { Uint32 all; struct IFIVAL_BITS bit; }; struct THCFG_BITS { // bits description Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I Uint16 rsvd1:6; // 7:2 Reserved Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q Uint16 rsvd2:6; // 15:10 Reserved Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value Uint16 rsvd3:6; // 23:18 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:6; // 31:26 Reserved }; union THCFG_REG { Uint32 all; struct THCFG_BITS bit; }; struct RAWINTST_BITS { // bits description Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run Uint16 rsvd1:1; // 2 Reserved Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition Uint16 rsvd2:3; // 7:5 Reserved Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run Uint16 rsvd3:1; // 10 Reserved Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition Uint16 rsvd4:3; // 15:13 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union RAWINTST_REG { Uint32 all; struct RAWINTST_BITS bit; }; struct ENINTST_BITS { // bits description Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run Uint16 rsvd1:1; // 2 Reserved Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition Uint16 rsvd2:3; // 7:5 Reserved Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run Uint16 rsvd3:1; // 10 Reserved Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition Uint16 rsvd4:3; // 15:13 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union ENINTST_REG { Uint32 all; struct ENINTST_BITS bit; }; struct INTENSET_BITS { // bits description Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run Uint16 rsvd1:1; // 2 Reserved Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition Uint16 rsvd2:3; // 7:5 Reserved Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run Uint16 rsvd3:1; // 10 Reserved Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition Uint16 rsvd4:3; // 15:13 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union INTENSET_REG { Uint32 all; struct INTENSET_BITS bit; }; struct INTENCLR_BITS { // bits description Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run Uint16 rsvd1:1; // 2 Reserved Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition Uint16 rsvd2:3; // 7:5 Reserved Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run Uint16 rsvd3:1; // 10 Reserved Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition Uint16 rsvd4:3; // 15:13 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union INTENCLR_REG { Uint32 all; struct INTENCLR_BITS bit; }; struct CHIDESC1_BITS { // bits description Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer. Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer. }; union CHIDESC1_REG { Uint32 all; struct CHIDESC1_BITS bit; }; struct CHIDESC2_BITS { // bits description Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. Uint16 rsvd1:16; // 31:16 Reserved }; union CHIDESC2_REG { Uint32 all; struct CHIDESC2_BITS bit; }; struct CHIST1_BITS { // bits description Uint16 BCNT:16; // 15:0 Current byte number. Uint16 LCNT:16; // 31:16 Current line number. }; union CHIST1_REG { Uint32 all; struct CHIST1_BITS bit; }; struct CHIST2_BITS { // bits description Uint16 ACT:1; // 0 Status of DMA descriptor. Uint16 PEND:1; // 1 Status of DMA. Uint16 rsvd1:2; // 3:2 Reserved Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer. Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CHIST2_REG { Uint32 all; struct CHIST2_BITS bit; }; struct CHQDESC1_BITS { // bits description Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer. Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer. }; union CHQDESC1_REG { Uint32 all; struct CHQDESC1_BITS bit; }; struct CHQDESC2_BITS { // bits description Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. Uint16 rsvd1:16; // 31:16 Reserved }; union CHQDESC2_REG { Uint32 all; struct CHQDESC2_BITS bit; }; struct CHQST1_BITS { // bits description Uint16 BCNT:16; // 15:0 Current byte number. Uint16 LCNT:16; // 31:16 Current line number. }; union CHQST1_REG { Uint32 all; struct CHQST1_BITS bit; }; struct CHQST2_BITS { // bits description Uint16 ACT:1; // 0 Status of DMA descriptor. Uint16 PEND:1; // 1 Status of DMA. Uint16 rsvd1:2; // 3:2 Reserved Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer. Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CHQST2_REG { Uint32 all; struct CHQST2_BITS bit; }; struct GINTEN_BITS { // bits description Uint16 GINTEN:1; // 0 Global Interrupt Enable Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union GINTEN_REG { Uint32 all; struct GINTEN_BITS bit; }; struct GINTFLG_BITS { // bits description Uint16 GINTFLG:1; // 0 Global Interrupt Flag Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union GINTFLG_REG { Uint32 all; struct GINTFLG_BITS bit; }; struct GINTCLR_BITS { // bits description Uint16 GINTCLR:1; // 0 Global Interrupt Clear Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union GINTCLR_REG { Uint32 all; struct GINTCLR_BITS bit; }; struct DLYCTL_BITS { // bits description Uint16 DLYDIS:1; // 0 IO dealy control disable. Uint16 DLYCTL:2; // 2:1 IO delay control. Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DLYCTL_REG { Uint32 all; struct DLYCTL_BITS bit; }; struct UPP_REGS { Uint32 PID; // Peripheral ID Register union PERCTL_REG PERCTL; // Peripheral Control Register Uint16 rsvd1[4]; // Reserved union CHCTL_REG CHCTL; // General Control Register union IFCFG_REG IFCFG; // Interface Configuration Register union IFIVAL_REG IFIVAL; // Interface Idle Value Register union THCFG_REG THCFG; // Threshold Configuration Register union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register union ENINTST_REG ENINTST; // Enable Interrupt Status Register union INTENSET_REG INTENSET; // Interrupt Enable Set Register union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register Uint16 rsvd2[8]; // Reserved Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register Uint16 rsvd3[2]; // Reserved Uint32 CHIST0; // DMA Channel I Status 0 Register union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register Uint16 rsvd4[2]; // Reserved Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register Uint16 rsvd5[2]; // Reserved Uint32 CHQST0; // DMA Channel Q Status 0 Register union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register Uint16 rsvd6[2]; // Reserved union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register union DLYCTL_REG DLYCTL; // IO clock data skew control Register }; //--------------------------------------------------------------------------- // UPP External References & Function Declarations: // extern volatile struct UPP_REGS UppRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_xbar.h // // TITLE: F2837xD Device XBAR Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct XBARFLG1_BITS { // bits description Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal }; union XBARFLG1_REG { Uint32 all; struct XBARFLG1_BITS bit; }; struct XBARFLG2_BITS { // bits description Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal Uint16 INPUT7:1; // 5 Input Flag for INPUT7 Signal Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 rsvd6:1; // 13 Reserved Uint16 rsvd7:1; // 14 Reserved Uint16 rsvd8:1; // 15 Reserved Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal }; union XBARFLG2_REG { Uint32 all; struct XBARFLG2_BITS bit; }; struct XBARFLG3_BITS { // bits description Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal Uint16 rsvd1:9; // 31:23 Reserved }; union XBARFLG3_REG { Uint32 all; struct XBARFLG3_BITS bit; }; struct XBARCLR1_BITS { // bits description Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal }; union XBARCLR1_REG { Uint32 all; struct XBARCLR1_BITS bit; }; struct XBARCLR2_BITS { // bits description Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 rsvd6:1; // 13 Reserved Uint16 rsvd7:1; // 14 Reserved Uint16 rsvd8:1; // 15 Reserved Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal }; union XBARCLR2_REG { Uint32 all; struct XBARCLR2_BITS bit; }; struct XBARCLR3_BITS { // bits description Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal Uint16 rsvd1:9; // 31:23 Reserved }; union XBARCLR3_REG { Uint32 all; struct XBARCLR3_BITS bit; }; struct XBAR_REGS { union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 Uint16 rsvd1[2]; // Reserved union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 Uint16 rsvd2[18]; // Reserved }; //--------------------------------------------------------------------------- // XBAR External References & Function Declarations: // extern volatile struct XBAR_REGS XbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837xD_xint.h // // TITLE: F2837xD Device XINT Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // XINT Individual Register Bit Definitions: struct XINT1CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT1 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT1 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT1CR_REG { Uint16 all; struct XINT1CR_BITS bit; }; struct XINT2CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT2 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT2 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT2CR_REG { Uint16 all; struct XINT2CR_BITS bit; }; struct XINT3CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT3 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT3 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT3CR_REG { Uint16 all; struct XINT3CR_BITS bit; }; struct XINT4CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT4 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT4 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT4CR_REG { Uint16 all; struct XINT4CR_BITS bit; }; struct XINT5CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT5 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT5 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT5CR_REG { Uint16 all; struct XINT5CR_BITS bit; }; struct XINT_REGS { union XINT1CR_REG XINT1CR; // XINT1 configuration register union XINT2CR_REG XINT2CR; // XINT2 configuration register union XINT3CR_REG XINT3CR; // XINT3 configuration register union XINT4CR_REG XINT4CR; // XINT4 configuration register union XINT5CR_REG XINT5CR; // XINT5 configuration register Uint16 rsvd1[3]; // Reserved Uint16 XINT1CTR; // XINT1 counter register Uint16 XINT2CTR; // XINT2 counter register Uint16 XINT3CTR; // XINT3 counter register }; //--------------------------------------------------------------------------- // XINT External References & Function Declarations: // extern volatile struct XINT_REGS XintRegs; //=========================================================================== // End of file. //=========================================================================== // // byte_peripheral attribute is only supported on the C28 // //########################################################################### // // FILE: F2837xD_can.h // // TITLE: F2837xD Device CAN Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 (Patch) $ // $Release Date: March 3 2017 $ // $Copyright: Copyright (C) 2014-2017 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // CAN Individual Register Bit Definitions: struct CAN_CTL_BITS { // bits description bp_16 Init:1; // 0 Initialization bp_16 IE0:1; // 1 Interrupt line 0 Enable Disabled bp_16 SIE:1; // 2 Status Change Interrupt Enable Disabled bp_16 EIE:1; // 3 Error Interrupt Enable Disabled bp_16 rsvd1:1; // 4 Reserved bp_16 DAR:1; // 5 Disable Automatic Retransmission bp_16 CCE:1; // 6 Configuration Change Enable bp_16 Test:1; // 7 Test Mode Enable bp_16 IDS:1; // 8 Interruption Debug Support Enable bp_16 ABO:1; // 9 Auto-Bus-On Enable bp_16 PMD:4; // 13:10 Parity on/off bp_16 rsvd2:1; // 14 Reserved bp_16 SWR:1; // 15 SW Reset Enable bp_32 INITDBG:1; // 16 Debug Mode Status bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled bp_32 rsvd3:1; // 18 Reserved bp_32 rsvd4:1; // 19 Reserved bp_32 rsvd5:1; // 20 Reserved bp_32 rsvd6:3; // 23:21 Reserved bp_32 PDR:1; // 24 Power Down Request Mode bp_32 WUBA:1; // 25 Wake Up on Bus Activity bp_32 rsvd7:6; // 31:26 Reserved }; union CAN_CTL_REG { bp_32 all; struct CAN_CTL_BITS bit; }; struct CAN_ES_BITS { // bits description bp_16 LEC:3; // 2:0 Last Error Code bp_16 TxOk:1; // 3 Transmission status bp_16 RxOk:1; // 4 Reception status bp_16 EPass:1; // 5 Error Passive State bp_16 EWarn:1; // 6 Warning State bp_16 BOff:1; // 7 Bus-Off State bp_16 PER:1; // 8 Parity Error Detected bp_16 WakeUpPnd:1; // 9 Wake Up Pending bp_16 PDA:1; // 10 Power down mode acknowledge bp_16 rsvd1:5; // 15:11 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_ES_REG { bp_32 all; struct CAN_ES_BITS bit; }; struct CAN_ERRC_BITS { // bits description bp_16 TEC:8; // 7:0 Transmit Error Counter bp_16 REC:7; // 14:8 Receive Error Counter bp_16 RP:1; // 15 Receive Error Passive bp_32 rsvd1:16; // 31:16 Reserved }; union CAN_ERRC_REG { bp_32 all; struct CAN_ERRC_BITS bit; }; struct CAN_BTR_BITS { // bits description bp_16 BRP:6; // 5:0 Baud Rate Prescaler bp_16 SJW:2; // 7:6 Synchronization Jump Width bp_16 TSEG1:4; // 11:8 Time segment bp_16 TSEG2:3; // 14:12 Time segment bp_16 rsvd1:1; // 15 Reserved bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension bp_32 rsvd2:12; // 31:20 Reserved }; union CAN_BTR_REG { bp_32 all; struct CAN_BTR_BITS bit; }; struct CAN_INT_BITS { // bits description bp_16 INT0ID:16; // 15:0 Interrupt Identifier bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier bp_32 rsvd1:8; // 31:24 Reserved }; union CAN_INT_REG { bp_32 all; struct CAN_INT_BITS bit; }; struct CAN_TEST_BITS { // bits description bp_16 rsvd1:3; // 2:0 Reserved bp_16 SILENT:1; // 3 Silent Mode bp_16 LBACK:1; // 4 Loopback Mode bp_16 TX:2; // 6:5 CANTX Pin Control bp_16 RX:1; // 7 CANRX Pin Status bp_16 EXL:1; // 8 External Loopback Mode bp_16 RDA:1; // 9 RAM Direct Access Enable: bp_16 rsvd2:6; // 15:10 Reserved bp_32 rsvd3:16; // 31:16 Reserved }; union CAN_TEST_REG { bp_32 all; struct CAN_TEST_BITS bit; }; struct CAN_PERR_BITS { // bits description bp_16 MSG_NUM:8; // 7:0 Message Number bp_16 WORD_NUM:3; // 10:8 Word Number bp_16 rsvd1:5; // 15:11 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_PERR_REG { bp_32 all; struct CAN_PERR_BITS bit; }; struct CAN_REL_BITS { // bits description bp_16 DAY:8; // 7:0 Day bp_16 MON:8; // 15:8 Month bp_32 YEAR:4; // 19:16 Year bp_32 SUBSTEP:4; // 23:20 Substep bp_32 STEP:4; // 27:24 Step bp_32 REL:4; // 31:28 Release }; union CAN_REL_REG { bp_32 all; struct CAN_REL_BITS bit; }; struct CAN_RAM_INIT_BITS { // bits description bp_16 KEY0:1; // 0 KEY0 bp_16 KEY1:1; // 1 KEY1 bp_16 KEY2:1; // 2 KEY2 bp_16 KEY3:1; // 3 KEY3 bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete bp_16 rsvd1:10; // 15:6 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_RAM_INIT_REG { bp_32 all; struct CAN_RAM_INIT_BITS bit; }; struct CAN_GLB_INT_EN_BITS { // bits description bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 bp_16 rsvd1:14; // 15:2 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_GLB_INT_EN_REG { bp_32 all; struct CAN_GLB_INT_EN_BITS bit; }; struct CAN_GLB_INT_FLG_BITS { // bits description bp_16 Name:1; // 0 Global Interrupt Flag for CAN INT0 bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 bp_16 rsvd1:14; // 15:2 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_GLB_INT_FLG_REG { bp_32 all; struct CAN_GLB_INT_FLG_BITS bit; }; struct CAN_GLB_INT_CLR_BITS { // bits description bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 bp_16 rsvd1:14; // 15:2 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_GLB_INT_CLR_REG { bp_32 all; struct CAN_GLB_INT_CLR_BITS bit; }; struct CAN_TXRQ_X_BITS { // bits description bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_TXRQ_X_REG { bp_32 all; struct CAN_TXRQ_X_BITS bit; }; struct CAN_NDAT_X_BITS { // bits description bp_16 NewDatReg1:2; // 1:0 New Data Register 1 bp_16 NewDatReg2:2; // 3:2 New Data Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_NDAT_X_REG { bp_32 all; struct CAN_NDAT_X_BITS bit; }; struct CAN_IPEN_X_BITS { // bits description bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IPEN_X_REG { bp_32 all; struct CAN_IPEN_X_BITS bit; }; struct CAN_MVAL_X_BITS { // bits description bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_MVAL_X_REG { bp_32 all; struct CAN_MVAL_X_BITS bit; }; struct CAN_IF1CMD_BITS { // bits description bp_16 MSG_NUM:8; // 7:0 Message Number bp_16 rsvd1:6; // 13:8 Reserved bp_16 rsvd2:1; // 14 Reserved bp_16 Busy:1; // 15 Busy Flag bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 bp_32 TXRQST:1; // 18 Access Transmission Request Bit bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit bp_32 Control:1; // 20 Access Control Bits bp_32 Arb:1; // 21 Access Arbitration Bits bp_32 Mask:1; // 22 Access Mask Bits bp_32 DIR:1; // 23 Write/Read Direction bp_32 rsvd3:8; // 31:24 Reserved }; union CAN_IF1CMD_REG { bp_32 all; struct CAN_IF1CMD_BITS bit; }; struct CAN_IF1MSK_BITS { // bits description bp_32 Msk:29; // 28:0 Identifier Mask bp_32 rsvd1:1; // 29 Reserved bp_32 MDir:1; // 30 Mask Message Direction bp_32 MXtd:1; // 31 Mask Extended Identifier }; union CAN_IF1MSK_REG { bp_32 all; struct CAN_IF1MSK_BITS bit; }; struct CAN_IF1ARB_BITS { // bits description bp_32 ID:29; // 28:0 ` bp_32 Dir:1; // 29 Message Direction bp_32 Xtd:1; // 30 Extended Identifier bp_32 MsgVal:1; // 31 Message Valid }; union CAN_IF1ARB_REG { bp_32 all; struct CAN_IF1ARB_BITS bit; }; struct CAN_IF1MCTL_BITS { // bits description bp_16 DLC:4; // 3:0 Data length code bp_16 rsvd1:3; // 6:4 Reserved bp_16 EoB:1; // 7 End of Block bp_16 TxRqst:1; // 8 Transmit Request bp_16 RmtEn:1; // 9 Remote Enable bp_16 RxIE:1; // 10 Receive Interrupt Enable bp_16 TxIE:1; // 11 Transmit Interrupt Enable bp_16 UMask:1; // 12 Use Acceptance Mask bp_16 IntPnd:1; // 13 Interrupt Pending bp_16 MsgLst:1; // 14 Message Lost bp_16 NewDat:1; // 15 New Data bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IF1MCTL_REG { bp_32 all; struct CAN_IF1MCTL_BITS bit; }; struct CAN_IF1DATA_BITS { // bits description bp_16 Data_0:8; // 7:0 Data Byte 0 bp_16 Data_1:8; // 15:8 Data Byte 1 bp_32 Data_2:8; // 23:16 Data Byte 2 bp_32 Data_3:8; // 31:24 Data Byte 3 }; union CAN_IF1DATA_REG { bp_32 all; struct CAN_IF1DATA_BITS bit; }; struct CAN_IF1DATB_BITS { // bits description bp_16 Data_4:8; // 7:0 Data Byte 4 bp_16 Data_5:8; // 15:8 Data Byte 5 bp_32 Data_6:8; // 23:16 Data Byte 6 bp_32 Data_7:8; // 31:24 Data Byte 7 }; union CAN_IF1DATB_REG { bp_32 all; struct CAN_IF1DATB_BITS bit; }; struct CAN_IF2CMD_BITS { // bits description bp_16 MSG_NUM:8; // 7:0 Message Number bp_16 rsvd1:6; // 13:8 Reserved bp_16 rsvd2:1; // 14 Reserved bp_16 Busy:1; // 15 Busy Flag bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 bp_32 TxRqst:1; // 18 Access Transmission Request Bit bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit bp_32 Control:1; // 20 Access Control Bits bp_32 Arb:1; // 21 Access Arbitration Bits bp_32 Mask:1; // 22 Access Mask Bits bp_32 DIR:1; // 23 Write/Read Direction bp_32 rsvd3:8; // 31:24 Reserved }; union CAN_IF2CMD_REG { bp_32 all; struct CAN_IF2CMD_BITS bit; }; struct CAN_IF2MSK_BITS { // bits description bp_32 Msk:29; // 28:0 Identifier Mask bp_32 rsvd1:1; // 29 Reserved bp_32 MDir:1; // 30 Mask Message Direction bp_32 MXtd:1; // 31 Mask Extended Identifier }; union CAN_IF2MSK_REG { bp_32 all; struct CAN_IF2MSK_BITS bit; }; struct CAN_IF2ARB_BITS { // bits description bp_32 ID:29; // 28:0 Message Identifier bp_32 Dir:1; // 29 Message Direction bp_32 Xtd:1; // 30 Extended Identifier bp_32 MsgVal:1; // 31 Message Valid }; union CAN_IF2ARB_REG { bp_32 all; struct CAN_IF2ARB_BITS bit; }; struct CAN_IF2MCTL_BITS { // bits description bp_16 DLC:4; // 3:0 Data length code bp_16 rsvd1:3; // 6:4 Reserved bp_16 EoB:1; // 7 End of Block bp_16 TxRqst:1; // 8 Transmit Request bp_16 RmtEn:1; // 9 Remote Enable bp_16 RxIE:1; // 10 Receive Interrupt Enable bp_16 TxIE:1; // 11 Transmit Interrupt Enable bp_16 UMask:1; // 12 Use Acceptance Mask bp_16 IntPnd:1; // 13 Interrupt Pending bp_16 MsgLst:1; // 14 Message Lost bp_16 NewDat:1; // 15 New Data bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IF2MCTL_REG { bp_32 all; struct CAN_IF2MCTL_BITS bit; }; struct CAN_IF2DATA_BITS { // bits description bp_16 Data_0:8; // 7:0 Data Byte 0 bp_16 Data_1:8; // 15:8 Data Byte 1 bp_32 Data_2:8; // 23:16 Data Byte 2 bp_32 Data_3:8; // 31:24 Data Byte 3 }; union CAN_IF2DATA_REG { bp_32 all; struct CAN_IF2DATA_BITS bit; }; struct CAN_IF2DATB_BITS { // bits description bp_16 Data_4:8; // 7:0 Data Byte 4 bp_16 Data_5:8; // 15:8 Data Byte 5 bp_32 Data_6:8; // 23:16 Data Byte 6 bp_32 Data_7:8; // 31:24 Data Byte 7 }; union CAN_IF2DATB_REG { bp_32 all; struct CAN_IF2DATB_BITS bit; }; struct CAN_IF3OBS_BITS { // bits description bp_16 Mask:1; // 0 Mask data read observation bp_16 Arb:1; // 1 Arbitration data read observation bp_16 Ctrl:1; // 2 Ctrl read observation bp_16 Data_A:1; // 3 Data A read observation bp_16 Data_B:1; // 4 Data B read observation bp_16 rsvd1:3; // 7:5 Reserved bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access bp_16 rsvd2:2; // 14:13 Reserved bp_16 IF3Upd:1; // 15 IF3 Update Data bp_32 rsvd3:16; // 31:16 Reserved }; union CAN_IF3OBS_REG { bp_32 all; struct CAN_IF3OBS_BITS bit; }; struct CAN_IF3MSK_BITS { // bits description bp_32 Msk:29; // 28:0 Mask bp_32 rsvd1:1; // 29 Reserved bp_32 MDir:1; // 30 Mask Message Direction bp_32 MXtd:1; // 31 Mask Extended Identifier }; union CAN_IF3MSK_REG { bp_32 all; struct CAN_IF3MSK_BITS bit; }; struct CAN_IF3ARB_BITS { // bits description bp_32 ID:29; // 28:0 Message Identifier bp_32 Dir:1; // 29 Message Direction bp_32 Xtd:1; // 30 Extended Identifier bp_32 MsgVal:1; // 31 Message Valid }; union CAN_IF3ARB_REG { bp_32 all; struct CAN_IF3ARB_BITS bit; }; struct CAN_IF3MCTL_BITS { // bits description bp_16 DLC:4; // 3:0 Data length code bp_16 rsvd1:3; // 6:4 Reserved bp_16 EoB:1; // 7 End of Block bp_16 TxRqst:1; // 8 Transmit Request bp_16 RmtEn:1; // 9 Remote Enable bp_16 RxIE:1; // 10 Receive Interrupt Enable bp_16 TxIE:1; // 11 Transmit Interrupt Enable bp_16 UMask:1; // 12 Use Acceptance Mask bp_16 IntPnd:1; // 13 Interrupt Pending bp_16 MsgLst:1; // 14 Message Lost bp_16 NewDat:1; // 15 New Data bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IF3MCTL_REG { bp_32 all; struct CAN_IF3MCTL_BITS bit; }; struct CAN_IF3DATA_BITS { // bits description bp_16 Data_0:8; // 7:0 Data Byte 0 bp_16 Data_1:8; // 15:8 Data Byte 1 bp_32 Data_2:8; // 23:16 Data Byte 2 bp_32 Data_3:8; // 31:24 Data Byte 3 }; union CAN_IF3DATA_REG { bp_32 all; struct CAN_IF3DATA_BITS bit; }; struct CAN_IF3DATB_BITS { // bits description bp_16 Data_4:8; // 7:0 Data Byte 4 bp_16 Data_5:8; // 15:8 Data Byte 5 bp_32 Data_6:8; // 23:16 Data Byte 6 bp_32 Data_7:8; // 31:24 Data Byte 7 }; union CAN_IF3DATB_REG { bp_32 all; struct CAN_IF3DATB_BITS bit; }; struct CAN_REGS { union CAN_CTL_REG CAN_CTL; // CAN Control Register union CAN_ES_REG CAN_ES; // Error and Status Register union CAN_ERRC_REG CAN_ERRC; // Error Counter Register union CAN_BTR_REG CAN_BTR; // Bit Timing Register union CAN_INT_REG CAN_INT; // Interrupt Register union CAN_TEST_REG CAN_TEST; // Test Register uint32_t rsvd1[2]; // Reserved union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register union CAN_REL_REG CAN_REL; // CAN Core Release Register uint32_t rsvd2[14]; // Reserved union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register uint32_t rsvd3[6]; // Reserved union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register uint32_t rsvd4[18]; // Reserved bp_32 CAN_ABOTR; // Auto-Bus-On Time Register union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request X Register bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register uint32_t rsvd5[6]; // Reserved union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data X Register bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register uint32_t rsvd6[6]; // Reserved union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending X Register bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register uint32_t rsvd7[6]; // Reserved union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid X Register bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register uint32_t rsvd8[8]; // Reserved bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register uint32_t rsvd9[18]; // Reserved union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register uint32_t rsvd10[4]; // Reserved union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register uint32_t rsvd11[4]; // Reserved union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register uint32_t rsvd12[4]; // Reserved bp_32 CAN_IF3UPD; // IF3 Update Enable Register }; //--------------------------------------------------------------------------- // CAN External References & Function Declarations: // extern volatile struct CAN_REGS CanaRegs; extern volatile struct CAN_REGS CanbRegs; //=========================================================================== // End of file. //=========================================================================== // // End of file. // //########################################################################### // // FILE: F2837xD_Examples.h // // TITLE: F2837xD Device Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // The following are values that can be passed to the // InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier // // // The following are values that can be passed to the // InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier // // // The following are values that can be passed to the // InitSysPll() to select divsel for SYSPLL // // // The following are values that can be passed to the // InitAuxPll() to select divsel for AUXPLL // // // The following are values that can be passed to the // IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL // // // The following are values that can be passed to the // InitSysPll() & InitAuxPll() to select clock source // // // Specify the clock rate of the CPU (SYSCLKOUT) in nS. // // Take into account the input clock frequency and the PLL multiplier // selected in step 1. // // Use one of the values provided, or define your own. // The trailing L is required tells the compiler to treat // the number as a 64-bit value. // // Only one statement should be uncommented. // // Example: 200 MHz devices: // CLKIN is a 10 MHz crystal or internal 10 MHz oscillator // // In step 1 the user specified the PLL multiplier = 40 for a // 200 MHz CPU clock (SYSCLKOUT = 200 MHz). // // In this case, the CPU_RATE will be 5.000L // Uncomment the line: #define CPU_RATE 5.000L // //#define CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) // // The following pointer to a function call calibrates the ADC reference, // DAC offset, and internal oscillators // // // The following pointers to functions calibrate the ADC linearity. Use this // in the AdcSetMode(...) function only // // // The following pointer to a function call looks up the ADC offset trim for a // given condition. Use this in the AdcSetMode(...) function only. // // // Includes // //########################################################################### // // FILE: F2837xD_GlobalPrototypes.h // // TITLE: Global prototypes for F2837xD Examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Function Prototypes (Shared) // extern void EnableInterrupts(void); extern void InitAPwm1Gpio(void); extern void InitCAN(void); extern void InitECaps(void); extern void InitECapGpio(void); extern void InitECap1Gpio(Uint16 pin); extern void InitECap2Gpio(Uint16 pin); extern void InitECap3Gpio(Uint16 pin); extern void InitECap4Gpio(Uint16 pin); extern void InitECap5Gpio(Uint16 pin); extern void InitECap6Gpio(Uint16 pin); extern void InitEQep1Gpio(void); extern void InitEQep2Gpio(void); extern void InitEQep3Gpio(void); extern void InitEPwmGpio(void); extern void InitEPwm1Gpio(void); extern void InitEPwm2Gpio(void); extern void InitEPwm3Gpio(void); extern void InitEPwm4Gpio(void); extern void InitEPwm5Gpio(void); extern void InitEPwm6Gpio(void); extern void InitEPwm7Gpio(void); extern void InitEPwm8Gpio(void); extern void InitEPwm9Gpio(void); extern void InitEPwm10Gpio(void); extern void InitEPwm11Gpio(void); extern void InitEPwm12Gpio(void); extern void InitPeripheralClocks(void); extern void DisablePeripheralClocks(void); extern void InitPieCtrl(void); extern void InitPieVectTable(void); extern void InitSysCtrl(void); extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel); extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel); extern void ServiceDog(void); extern void DisableDog(void); extern Uint16 CsmUnlock(void); extern void SysIntOsc1Sel (void); extern void SysIntOsc2Sel (void); extern void SysXtalOscSel (void); extern void AuxIntOsc2Sel (void); extern void AuxXtalOscSel (void); extern void AuxAuxClkSel (void); extern void SetDBGIER(Uint16 dbgier); // // CAUTION // This function MUST be executed out of RAM. Executing it // out of OTP/Flash will yield unpredictable results // extern void InitFlash(void); extern void InitFlash_Bank0(void); extern void InitFlash_Bank1(void); extern void FlashOff(void); extern void FlashOff_Bank0(void); extern void FlashOff_Bank1(void); extern void SeizeFlashPump(void); extern void SeizeFlashPump_Bank0(void); extern void SeizeFlashPump_Bank1(void); extern void ReleaseFlashPump(void); // //LPM functions in F2837xD_SysCtrl.c // void IDLE(); void STANDBY(); void HALT(); void HIB(); // //ADC functions // extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode); extern void CalAdcINL(Uint16 adc); // // DMA Functions // extern void DMAInitialize(void); // // DMA Channel 1 // extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, volatile Uint16 *DMA_Source); extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, volatile Uint32 *DMA_Source); extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); extern void StartDMACH1(void); // // DMA Channel 2 // extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, volatile Uint16 *DMA_Source); extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, volatile Uint32 *DMA_Source); extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); extern void StartDMACH2(void); // // DMA Channel 3 // extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, volatile Uint16 *DMA_Source); extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, volatile Uint32 *DMA_Source); extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); extern void StartDMACH3(void); // // DMA Channel 4 // extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, volatile Uint16 *DMA_Source); extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, volatile Uint32 *DMA_Source); extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); extern void StartDMACH4(void); // // DMA Channel 5 // extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, volatile Uint16 *DMA_Source); extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, volatile Uint32 *DMA_Source); extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); extern void StartDMACH5(void); // // DMA Channel 6 // extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, volatile Uint16 *DMA_Source); extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, volatile Uint32 *DMA_Source); extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); extern void StartDMACH6(void); // //GPIO Functions // extern void InitGpio(); extern void GPIO_SetupPinMux(Uint16 pin, Uint16 cpu, Uint16 peripheral); extern void GPIO_SetupPinOptions(Uint16 pin, Uint16 output, Uint16 flags); extern void GPIO_SetupLock(Uint16 pin, Uint16 flags); extern void GPIO_SetupXINT1Gpio(Uint16 pin); extern void GPIO_SetupXINT2Gpio(Uint16 pin); extern void GPIO_SetupXINT3Gpio(Uint16 pin); extern void GPIO_SelectIpcInt(Uint16 newFlag); extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); extern void GPIO_EnableUnbondedIOPullups(void); Uint16 GPIO_ReadPin(Uint16 pin); void GPIO_WritePin(Uint16 pin, Uint16 outVal); // //IPC Functions // extern void InitIpc(); extern Uint64 ReadIpcTimer(); extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag); extern void RecvIpcData(void *recv_buf, Uint16 word_length); extern void FillIpcSendData(Uint16 fill_data); extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag); extern void SendIpcFlag(Uint16 flag); extern void AckIpcFlag(Uint16 flag); extern void CancelIpcFlag(Uint16 flag); extern void WaitForIpcFlag(Uint16 flag); extern void WaitForIpcAck(Uint16 flag); extern void IpcSync(Uint16 flag); // // CAN Functions // extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin); extern void CanAGpioConfig(Uint16 canaTxRxPin); extern void CanBGpioConfig(Uint16 canbTxRxPin); extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource); // // I2C Functions // extern void I2cAGpioConfig(Uint16 I2caDataClkPin); extern void I2cBGpioConfig(Uint16 I2cbDataClkPin); // // McBSP functions // McBSPA // extern void InitMcbspa(void); extern void InitMcbspaInt(void); extern void InitMcbspa8bit(void); extern void InitMcbspa12bit(void); extern void InitMcbspa16bit(void); extern void InitMcbspa20bit(void); extern void InitMcbspa24bit(void); extern void InitMcbspa32bit(void); extern void InitMcbspaGpio(void); extern void delay_loop(void); // // McBSPB // extern void InitMcbspb(void); extern void InitMcbspbInt(void); extern void InitMcbspb8bit(void); extern void InitMcbspb12bit(void); extern void InitMcbspb16bit(void); extern void InitMcbspb20bit(void); extern void InitMcbspb24bit(void); extern void InitMcbspb32bit(void); extern void InitMcbspbGpio(void); // //Temp Sensor Functions // extern void InitTempSensor(float32 vrefhi_voltage); extern int16 GetTemperatureC(int16 sensorSample); extern int16 GetTemperatureK(int16 sensorSample); // // External symbols created by the linker cmd file // DSP28 examples will use these to relocate code from one LOAD location // in Flash to a different RUN location in internal // RAM // extern Uint16 RamfuncsLoadStart; extern Uint16 RamfuncsLoadEnd; extern Uint16 RamfuncsLoadSize; extern Uint16 RamfuncsRunStart; extern Uint16 RamfuncsRunEnd; extern Uint16 RamfuncsRunSize; // // End of file // // within the .c files. //########################################################################### // // FILE: F2837xD_Cputimers.h // // TITLE: F2837xD Device CPUTIMERS Register Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Globals // struct CPUTIMER_VARS { volatile struct CPUTIMER_REGS *RegsAddr; Uint32 InterruptCount; float CPUFreqInMHz; float PeriodInUSec; }; extern struct CPUTIMER_VARS CpuTimer0; extern struct CPUTIMER_VARS CpuTimer1; extern struct CPUTIMER_VARS CpuTimer2; // // Defines // // // Start Timer: // // // Stop Timer: // // // Reload Timer With period Value: // // // Read 32-Bit Timer Value: // // // Read 32-Bit Period Value: // // // Start Timer: // // // Stop Timer: // // // Reload Timer With period Value: // // // Read 32-Bit Timer Value: // // // Read 32-Bit Period Value: // // // Function Prototypes // void InitCpuTimers(void); void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); // // End of file // //########################################################################### // // FILE: F2837xD_Cla_defines.h // // TITLE: #defines used in CLA examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // MCTL Register // // // MMEMCFG Register // // // MIER Interrupt Enable Register // // // Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register // // // End of file // //########################################################################### // // FILE: F2837xD_EPwm_defines.h // // TITLE: #defines used in EPwm examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // TBCTL (Time-Base Control) // // // CTRMODE bits // // // PHSEN bit // // // PRDLD bit // // // SYNCOSEL bits // // // HSPCLKDIV and CLKDIV bits // // // PHSDIR bit // // // CMPCTL (Compare Control) // // // LOADAMODE and LOADBMODE bits // // // SHDWAMODE and SHDWBMODE bits // // // AQCTLA and AQCTLB (Action Qualifier Control) // // // ZRO, PRD, CAU, CAD, CBU, CBD bits // // // DBCTL (Dead-Band Control) // // // OUT MODE bits // // // POLSEL bits // // // IN MODE // // // CHPCTL (chopper control) // // // CHPEN bit // // // CHPFREQ bits // // // CHPDUTY bits // // // TZSEL (Trip Zone Select) // // // CBCn and OSHTn bits // // // TZCTL (Trip Zone Control) // // // TZA and TZB bits // // // TZDCSEL (Trip Zone Digital Compare) // // // DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits // // // ETSEL (Event Trigger Select) // // // ETPS (Event Trigger Pre-scale) // // // INTPRD, SOCAPRD, SOCBPRD bits // // // HRPWM (High Resolution PWM) // // // HRCNFG // // // DC (Digital Compare) // // // DCTRIPSEL // // Reserved 0xC // // DCFCTL // // //DCACTL/DCBCTL // // // End of file // //########################################################################### // // FILE: F2837xD_Adc_defines.h // // TITLE: #defines used in ADC examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // //definitions for specifying an ADC // // //definitions for selecting ADC resolution // // //definitions for selecting ADC signal mode //(single-ended mode is only a valid mode for 12-bit resolution) // // // End of file // //########################################################################### // // FILE: F2837xD_Emif_defines.h // // TITLE: #defines used in EMIF examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // //cpu1 to cpu2 message for handshaking // // //cpu2_to_cpu1 message ram for handshaking // // //soft reset bit register // // //Device capability/EMIF customization register // // // Values for ASYNC_CSx_CR Registers // // // Values for ASYNC_WCCR Register // // // Read mask for the registers which has reserved bits. // // // End of file // //########################################################################### // // FILE: F2837xD_Gpio_defines.h // // TITLE: F2837xD GPIO support definitions // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // //CPU pin masters for GPIO_SelectPinMux() // // //Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, //QUAL6, and ASYNC) take up two bits and must be in the order specified. // // //Flags for GPIO_SetupLock(). // // //Commands for the CPU2->CPU1 GPIO configuration interrupt handler // // //Helpful constants for array-based access to GPIO registers // // // End of file // //########################################################################### // // FILE: F2837xD_I2c_defines.h // // TITLE: F2837xD I2C Common Definitions. // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // Error Messages // // // Clear Status Flags // // // Interrupt Source Messages // // // I2CMSG structure defines // // // I2C Slave State defines // // // I2C Slave Receiver messages defines // // // I2C State defines // // // I2C Message Commands for I2CMSG struct // // // Generic defines // // // These are the Defines to select I2C pin muxing when calling the functions // I2cAGpioConfig() & I2cBGpioConfig() in F2837xD_I2C.c // // // Globals // // // I2C Message Structure // struct I2CMSG { Uint16 MsgStatus; // Word stating what state msg is in: // I2C_MSGCMD_INACTIVE = do not send msg // I2C_MSGCMD_BUSY = msg start has been sent, // awaiting stop // I2C_MSGCMD_SEND_WITHSTOP = command to send // master trans msg complete with a stop bit // I2C_MSGCMD_SEND_NOSTOP = command to send // master trans msg without the stop bit // I2C_MSGCMD_RESTART = command to send a // restart as a master receiver with a // stop bit Uint16 SlaveAddress; // I2C address of slave msg is intended for Uint16 NumOfBytes; // Num of valid bytes in (or to be put // in MsgBuffer) Uint16 MemoryHighAddr; // EEPROM address of data associated with // msg (high byte) Uint16 MemoryLowAddr; // EEPROM address of data associated with // msg (low byte) Uint16 MsgBuffer[4]; // Array holding msg data - max that // MAX_BUFFER_SIZE can be is 16 due // to the FIFO's }; // // End of file // //########################################################################### // // FILE: F2837xD_Ipc_defines.h // // TITLE: F2837xD IPC support definitions // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // //Used with SendIpcData() and SendIpcCommand() to avoid setting a flag // // // End of file // //########################################################################### // // FILE: F2837xD_Pie_defines.h // // TITLE: #defines used in PIE examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // End of file // //########################################################################### // // FILE: F2837xD_Dma_defines.h // // TITLE: #defines used in DMA examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // PERINTSEL bits // // // OVERINTE bit // // // PERINTE bit // // // CHINTMODE bits // // // ONESHOT bits // // // CONTINOUS bit // // // SYNCE bit // // // SYNCSEL bit // // // DATASIZE bit // // // CHINTE bit // // // End of file // //########################################################################### // // FILE: F2837xD_SysCtrl_defines.h // // TITLE: F2837xD LPM support definitions // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // //Key value used for write access to the flash pump semaphore register // // // End of file // //########################################################################### // // FILE: F2837xD_Upp_defines.h // // TITLE: #defines used in Upp examples // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Defines // // // End of file // // // Include files not used with F/BIOS // //########################################################################### // // FILE: F2837xD_defaultisr.h // // TITLE: F2837xD Device Default Interrupt Service Routines Definitions // //########################################################################### // $TI Release: F2837xD Support Library v210 $ // $Release Date: Tue Nov 1 14:46:15 CDT 2016 $ // $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // Default Interrupt Service Routine Declarations: // The following function prototypes are for the // default ISR routines used with the default PIE vector table. // This default vector table is found in the F2837xD_pievect.h // file. // interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt interrupt void DATALOG_ISR(void); // Datalogging Interrupt interrupt void RTOS_ISR(void); // RTOS Interrupt interrupt void EMU_ISR(void); // Emulation Interrupt interrupt void NMI_ISR(void); // Non-Maskable Interrupt interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap interrupt void USER1_ISR(void); // User Defined Trap 1 interrupt void USER2_ISR(void); // User Defined Trap 2 interrupt void USER3_ISR(void); // User Defined Trap 3 interrupt void USER4_ISR(void); // User Defined Trap 4 interrupt void USER5_ISR(void); // User Defined Trap 5 interrupt void USER6_ISR(void); // User Defined Trap 6 interrupt void USER7_ISR(void); // User Defined Trap 7 interrupt void USER8_ISR(void); // User Defined Trap 8 interrupt void USER9_ISR(void); // User Defined Trap 9 interrupt void USER10_ISR(void); // User Defined Trap 10 interrupt void USER11_ISR(void); // User Defined Trap 11 interrupt void USER12_ISR(void); // User Defined Trap 12 interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1 interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1 interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2 interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0 interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1 interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2 interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3 interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2 interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3 interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4 interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable // Error Interrupt interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable // Error Interrupt interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access // Violation Interrupt interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip // Interrupt interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL // Slip Interrupt interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow // Interrupt interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow // Interrupt // // Catch-all for PIE Reserved Locations for testing purposes: // interrupt void PIE_RESERVED_ISR(void); // Reserved ISR interrupt void EMPTY_ISR(void); // Only does a return interrupt void NOTUSED_ISR(void); // Unused ISR // // End of file // extern void F28x_usDelay(long LoopCount); // // DO NOT MODIFY THIS LINE. // // // Timer Operations: // // // Start Timer: // // // Stop Timer: // // // Reload Timer With period Value: // // // Read 32-Bit Timer Value: // // // Read 32-Bit Period Value: // // // Start Timer: // // // Stop Timer: // // // Reload Timer With period Value: // // // Read 32-Bit Timer Value: // // // Read 32-Bit Period Value: // // // End of file // // // AdcSetMode - Set the resolution and signalmode for a given ADC. This will // ensure that the correct trim is loaded. // void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode) { Uint16 adcOffsetTrimOTPIndex; //index into OTP table of ADC offset trims Uint16 adcOffsetTrim; //temporary ADC offset trim // //re-populate INL trim // CalAdcINL(adc); if(0xFFFF != *((Uint16*)(Uint16 (*)(Uint16 OTPoffset))0x0703AC)) { // //offset trim function is programmed into OTP, so call it // // //calculate the index into OTP table of offset trims and call //function to return the correct offset trim // adcOffsetTrimOTPIndex = 4*adc + 2*resolution + 1*signalmode; adcOffsetTrim = (*(Uint16 (*)(Uint16 OTPoffset))0x0703AC)(adcOffsetTrimOTPIndex); } else { // //offset trim function is not populated, so set offset trim to 0 // adcOffsetTrim = 0; } // //Apply the resolution and signalmode to the specified ADC. //Also apply the offset trim and, if needed, linearity trim correction. // switch(adc) { case 0: AdcaRegs.ADCCTL2.bit.RESOLUTION = resolution; AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode; AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim; if(0 == resolution) { // //12-bit linearity trim workaround // AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000; AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000; AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000; AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000; } break; case 1: AdcbRegs.ADCCTL2.bit.RESOLUTION = resolution; AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode; AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim; if(0 == resolution) { // //12-bit linearity trim workaround // AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000; AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000; AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000; AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000; } break; case 2: AdccRegs.ADCCTL2.bit.RESOLUTION = resolution; AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode; AdccRegs.ADCOFFTRIM.all = adcOffsetTrim; if(0 == resolution) { // //12-bit linearity trim workaround // AdccRegs.ADCINLTRIM1 &= 0xFFFF0000; AdccRegs.ADCINLTRIM2 &= 0xFFFF0000; AdccRegs.ADCINLTRIM4 &= 0xFFFF0000; AdccRegs.ADCINLTRIM5 &= 0xFFFF0000; } break; case 3: AdcdRegs.ADCCTL2.bit.RESOLUTION = resolution; AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode; AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim; if(0 == resolution) { // //12-bit linearity trim workaround // AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000; AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000; AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000; AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000; } break; } } // // CalAdcINL - Loads INL trim values from OTP into the trim registers of the // specified ADC. Use only as part of AdcSetMode function, since // linearity trim correction is needed for some modes. // void CalAdcINL(Uint16 adc) { switch(adc) { case 0: if(0xFFFF != *((Uint16*)(void (*)(void))0x0703B4)) { // //trim function is programmed into OTP, so call it // (*(void (*)(void))0x0703B4)(); } else { // //do nothing, no INL trim function populated // } break; case 1: if(0xFFFF != *((Uint16*)(void (*)(void))0x0703B2)) { // //trim function is programmed into OTP, so call it // (*(void (*)(void))0x0703B2)(); } else { // //do nothing, no INL trim function populated // } break; case 2: if(0xFFFF != *((Uint16*)(void (*)(void))0x0703B0)) { // //trim function is programmed into OTP, so call it // (*(void (*)(void))0x0703B0)(); } else { // //do nothing, no INL trim function populated // } break; case 3: if(0xFFFF != *((Uint16*)(void (*)(void))0x0703AE)) { // //trim function is programmed into OTP, so call it // (*(void (*)(void))0x0703AE)(); } else { // //do nothing, no INL trim function populated // } break; } } // // End of file //