// TI File $Revision: /main/2 $
// Checkin $Date: April 29, 2005   11:08:24 $
//###########################################################################
//
// FILE:   DSP281x_Spi.c
//
// TITLE:  DSP281x SPI Initialization & Support Functions.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

//---------------------------------------------------------------------------
// InitSPI: 
//---------------------------------------------------------------------------
// This function initializes the SPI(s) to a known state.
//
void Spi_Init(void)
{

    SpiaRegs.SPICTL.bit.TALK = 1;			// enable talk
	SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Enable master mode
	SpiaRegs.SPICTL.bit.CLK_PHASE = 0;	// normal phase
	SpiaRegs.SPICTL.bit.SPIINTENA = 0;	// SPI int disabled
	SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0;//
  
 	SpiaRegs.SPIBRR = 0x007f;	//Baude Rate
 	
  	SpiaRegs.SPICCR.bit.SPICHAR = 0x07;	//Character length 16-bit
	SpiaRegs.SPICCR.bit.SPILBK = 0;	 	// Loop-back disable
	SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; 	// Clock polarity
	SpiaRegs.SPICCR.bit.SPISWRESET = 1;	//SPI SW Reset

    SpiaRegs.SPIPRI.bit.FREE = 1; 

// Initialize SPI FIFO registers
   SpiaRegs.SPIFFTX.bit.TXFFIL = 0x000;      // 4:0    Interrupt level
   SpiaRegs.SPIFFTX.bit.TXFFIENA = 0;        // 5      Interrupt enable
   SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;      // 6      Clear INT flag
   SpiaRegs.SPIFFTX.bit.TXFFINT = 0;         // 7      INT flag
   SpiaRegs.SPIFFTX.bit.TXFFST = 0x00;       // 12:8   FIFO status
   SpiaRegs.SPIFFTX.bit.TXFIFO = 1;          // 13     FIFO reset
   SpiaRegs.SPIFFTX.bit.SPIFFENA = 1;        // 14     Enhancement enable
   SpiaRegs.SPIFFTX.bit.SPIRST = 1;          // 15     Reset SPI

   SpiaRegs.SPIFFRX.bit.RXFFIL = 0x01;       // 4:0    Interrupt level
   SpiaRegs.SPIFFRX.bit.RXFFIENA = 0;        // 5      Interrupt enable
   SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1;      // 6      Clear INT flag
   SpiaRegs.SPIFFRX.bit.RXFFINT = 0;         // 7      INT flag
   SpiaRegs.SPIFFRX.bit.RXFFST = 0;          // 12:8   FIFO status
   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;     	 // 13     FIFO reset
   SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 0;      // 14     Clear overflow
   SpiaRegs.SPIFFRX.bit.RXFFOVF = 0;         // 15     FIFO overflow

   SpiaRegs.SPIFFCT.all = 0x0;

	EALLOW;
	GpioMuxRegs.GPFMUX.bit.SPISIMOA_GPIOF0 = 1;
	GpioMuxRegs.GPFMUX.bit.SPISOMIA_GPIOF1 = 1;
	GpioMuxRegs.GPFMUX.bit.SPICLKA_GPIOF2 = 1;
	EDIS;

}

void spi_xmit(Uint16 a)
{
    SpiaRegs.SPITXBUF = a;
}    

void spi_fifo_init(void)
{
// Initialize SPI FIFO registers
}  
void spi_msg(const char Spi_MsgPtr[])
{
    int Spi_MsgField = 0;

    while(Spi_MsgPtr[Spi_MsgField] != '\0')
    {
        spi_xmit(Spi_MsgPtr[Spi_MsgField]);
        Spi_MsgField++;
    }
}





//===========================================================================
// End of file.
//===========================================================================
