// TI File $Revision: /main/2 $
// Checkin $Date: April 29, 2005   11:11:45 $
//###########################################################################
//
// FILE:	DSP281x_Adc.c
//
// TITLE:	DSP281x ADC Initialization & Support Functions.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

extern void DSP28x_usDelay(Uint32 Count);

#define ADC_usDELAY  8000L
#define ADC_usDELAY2 20L

//---------------------------------------------------------------------------
// InitAdc: 
//---------------------------------------------------------------------------
// This function initializes ADC to a known state.
//
void InitAdc(void)
{
    // To powerup the ADC the ADCENCLK bit should be set first to enable
    // clocks, followed by powering up the bandgap and reference circuitry.
    // After a 5ms delay the rest of the ADC can be powered up. After ADC
    // powerup, another 20us delay is required before performing the first
    // ADC conversion. Please note that for the delay function below to
    // operate correctly the CPU_CLOCK_SPEED define statement in the
    // DSP28_Examples.h file must contain the correct CPU clock period in
    // nanoseconds. For example:
	AdcRegs.ADCTRL1.bit.RESET= 1; 				//Reset ADC
	asm(" RPT #10 || NOP");
	AdcRegs.ADCTRL3.bit.ADCEXTREF = 1;			// Внешняя референс точка
	asm(" RPT #10 || NOP");
	AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;		// Power up bandgap/reference circuitry
	AdcRegs.ADCTRL1.bit.CPS = 0;				// ADCTRL1[7]
	AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x7;			// HSPCLK/[6*(ADCTRL1[7] + 1)]
	AdcRegs.ADCTRL3.bit.SMODE_SEL = 0;			// Sequential sampling mode is selected.

 	DELAY_US(ADC_usDELAY);                  	// Delay before powering up rest of ADC
	AdcRegs.ADCTRL3.bit.ADCPWDN = 1;			// Power up rest of ADC
	DELAY_US(ADC_usDELAY2);

//Configure over registers

	AdcRegs.ADCMAXCONV.all = 0x000F;       // Setup 16 conv's on SEQ
	AdcRegs.ADCCHSELSEQ1.bit.CONV00 = ADCINB4;  // Uab +
	AdcRegs.ADCCHSELSEQ1.bit.CONV01 = ADCINB5;  // Uab -

	AdcRegs.ADCCHSELSEQ1.bit.CONV02 = ADCINB2;  // Ubc +
	AdcRegs.ADCCHSELSEQ1.bit.CONV03 = ADCINB3; 	// Ubc -

	AdcRegs.ADCCHSELSEQ2.bit.CONV04 = ADCINB0;	// Uca +
	AdcRegs.ADCCHSELSEQ2.bit.CONV05 = ADCINB1;	// Uca -

	AdcRegs.ADCCHSELSEQ2.bit.CONV06 = ADCINA1;	// P +
	AdcRegs.ADCCHSELSEQ2.bit.CONV07 = ADCINA0;	// P -

	AdcRegs.ADCCHSELSEQ3.bit.CONV08 = ADCINA6;	// Ia +
	AdcRegs.ADCCHSELSEQ3.bit.CONV09 = ADCINA7;	// Ia -

	AdcRegs.ADCCHSELSEQ3.bit.CONV10 = ADCINB6;	// Ib +
	AdcRegs.ADCCHSELSEQ3.bit.CONV11 = ADCINB7;	// Ib -

	AdcRegs.ADCCHSELSEQ4.bit.CONV12 = ADCINA3;	// T1 +
	AdcRegs.ADCCHSELSEQ4.bit.CONV13 = ADCINA2;	// T1 -

	AdcRegs.ADCCHSELSEQ4.bit.CONV14 = ADCINA5;	// T2 +
	AdcRegs.ADCCHSELSEQ4.bit.CONV15 = ADCINA4;	// T2 -

	AdcRegs.ADCTRL1.bit.SEQ_CASC 		= 1; //Setup cascaded sequencer mode
	AdcRegs.ADCTRL1.bit.ACQ_PS 			= 0x6;  //Acquisition window size. - 6 ADC-CLK

    AdcRegs.ADCTRL2.bit.EVB_SOC_SEQ 	= 1;  // Enable EVASOC to start SEQ1
 
    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 	= 1;  // Enable SEQ1 interrupt (every EOS)
 	AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 	= 1;

	//AdcRegs.ADCTRL1.bit.RESET
	AdcRegs.ADCTRL1.bit.SUSMOD 			= 0;	// Mode 0. Emulation suspend is ignored.
	AdcRegs.ADCTRL1.bit.ACQ_PS 			= 15;	// Acquisition window size. - 15 ADC-CLK
	AdcRegs.ADCTRL1.bit.CPS 			= 0;	// ADCTRL1[7]
	AdcRegs.ADCTRL1.bit.CONT_RUN 		= 0;	// 0Start-stop mode
	AdcRegs.ADCTRL1.bit.SEQ_OVRD 		= 0;	// 0Disabled
	AdcRegs.ADCTRL1.bit.SEQ_CASC 		= 1;	// Setup cascaded sequencer mode

	AdcRegs.ADCTRL2.bit.EVB_SOC_SEQ 	= 1;  // Enable EVASOC to start SEQ1

	AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 	= 1;  // Enable SEQ1 interrupt (every EOS)
	AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 	= 0;

	AdcRegs.ADCTRL3.bit.ADCCLKPS 		= 3;		// HSPCLK/[6*(ADCTRL1[7] + 1)] (20 MHz)
	AdcRegs.ADCTRL3.bit.SMODE_SEL 		= 0;		// Sequential sampling mode is selected.
}	

//===========================================================================
// No more.
//===========================================================================
