	.cpu cortex-r5
	.eabi_attribute 28, 1	@ Tag_ABI_VFP_args
	.eabi_attribute 20, 1	@ Tag_ABI_FP_denormal
	.eabi_attribute 21, 1	@ Tag_ABI_FP_exceptions
	.eabi_attribute 23, 3	@ Tag_ABI_FP_number_model
	.eabi_attribute 24, 1	@ Tag_ABI_align8_needed
	.eabi_attribute 25, 1	@ Tag_ABI_align8_preserved
	.eabi_attribute 26, 1	@ Tag_ABI_enum_size
	.eabi_attribute 30, 1	@ Tag_ABI_optimization_goals
	.eabi_attribute 34, 1	@ Tag_CPU_unaligned_access
	.eabi_attribute 18, 4	@ Tag_ABI_PCS_wchar_t
	.file	"HL_dcc.c"
@ GNU C11 (GNU Tools for Arm Embedded Processors 7-2017-q4-major) version 7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204] (arm-none-eabi)
@	compiled by GNU C version 4.8.4, GMP version 6.1.0, MPFR version 3.1.4, MPC version 1.0.3, isl version isl-0.15-GMP

@ GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
@ options passed:  -fpreprocessed HL_dcc.i -mcpu=cortex-r5 -mfloat-abi=hard
@ -mfpu=vfpv3-d16 -auxbase-strip source/HL_dcc.o -g -gdwarf-3
@ -gstrict-dwarf -Og -Wall -fverbose-asm
@ options enabled:  -faggressive-loop-optimizations -fauto-inc-dec
@ -fchkp-check-incomplete-type -fchkp-check-read -fchkp-check-write
@ -fchkp-instrument-calls -fchkp-narrow-bounds -fchkp-optimize
@ -fchkp-store-bounds -fchkp-use-static-bounds
@ -fchkp-use-static-const-bounds -fchkp-use-wrappers
@ -fcombine-stack-adjustments -fcommon -fcompare-elim -fcprop-registers
@ -fdefer-pop -fdelete-null-pointer-checks -fdwarf2-cfi-asm
@ -fearly-inlining -feliminate-unused-debug-types -fforward-propagate
@ -ffp-int-builtin-inexact -ffunction-cse -fgcse-lm -fgnu-runtime
@ -fgnu-unique -fguess-branch-probability -fident -finline -finline-atomics
@ -fipa-profile -fipa-pure-const -fipa-reference -fira-hoist-pressure
@ -fira-share-save-slots -fira-share-spill-slots -fivopts
@ -fkeep-static-consts -fleading-underscore -flifetime-dse
@ -flto-odr-type-merging -fmath-errno -fmerge-constants
@ -fmerge-debug-strings -fomit-frame-pointer -fpeephole -fplt
@ -fprefetch-loop-arrays -freg-struct-return -freorder-blocks
@ -fsched-critical-path-heuristic -fsched-dep-count-heuristic
@ -fsched-group-heuristic -fsched-interblock -fsched-last-insn-heuristic
@ -fsched-pressure -fsched-rank-heuristic -fsched-spec
@ -fsched-spec-insn-heuristic -fsched-stalled-insns-dep -fsection-anchors
@ -fsemantic-interposition -fshow-column -fshrink-wrap
@ -fshrink-wrap-separate -fsigned-zeros -fsplit-ivs-in-unroller
@ -fsplit-wide-types -fssa-backprop -fstdarg-opt
@ -fstrict-volatile-bitfields -fsync-libcalls -ftoplevel-reorder
@ -ftrapping-math -ftree-builtin-call-dce -ftree-ccp -ftree-ch
@ -ftree-coalesce-vars -ftree-copy-prop -ftree-cselim -ftree-dce
@ -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre
@ -ftree-loop-if-convert -ftree-loop-im -ftree-loop-ivcanon
@ -ftree-loop-optimize -ftree-parallelize-loops= -ftree-phiprop
@ -ftree-reassoc -ftree-scev-cprop -ftree-sink -ftree-slsr -ftree-ter
@ -funit-at-a-time -fvar-tracking -fvar-tracking-assignments -fverbose-asm
@ -fzero-initialized-in-bss -gstrict-dwarf -marm -mlittle-endian
@ -mpic-data-is-text-relative -msched-prolog -munaligned-access
@ -mvectorize-with-neon-quad

	.text
.Ltext0:
	.cfi_sections	.debug_frame
	.align	2
	.global	dccInit
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccInit, %function
dccInit:
.LFB0:
	.file 1 "../source/HL_dcc.c"
	.loc 1 61 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
@ ../source/HL_dcc.c:69:     dccREG1->CNT0SEED   = 39204U;
	.loc 1 69 0
	mvn	r3, #4864	@ tmp110,
	movw	r2, #39204	@ tmp111,
	str	r2, [r3, #-247]	@ tmp111, MEM[(volatile struct dccBASE_t *)4294962176B].CNT0SEED
@ ../source/HL_dcc.c:72:     dccREG1->VALID0SEED = 792U;          
	.loc 1 72 0
	mov	r2, #792	@ tmp113,
	str	r2, [r3, #-243]	@ tmp113, MEM[(volatile struct dccBASE_t *)4294962176B].VALID0SEED
@ ../source/HL_dcc.c:75:     dccREG1->CNT1SEED   = 742500U;
	.loc 1 75 0
	movw	r2, #21604	@ tmp115,
	movt	r2, 11	@ tmp115,
	str	r2, [r3, #-239]	@ tmp115, MEM[(volatile struct dccBASE_t *)4294962176B].CNT1SEED
@ ../source/HL_dcc.c:78:     dccREG1->CNT1CLKSRC = (uint32)((uint32)10U << 12U) |     /** DCC Enable / Disable Key */
	.loc 1 78 0
	mov	r2, #40960	@ tmp117,
	str	r2, [r3, #-219]	@ tmp117, MEM[(volatile struct dccBASE_t *)4294962176B].CNT1CLKSRC
@ ../source/HL_dcc.c:81:     dccREG1->CNT0CLKSRC = (uint32)DCC1_CNT0_OSCIN;  /** DCC1 Clock Source 0 */
	.loc 1 81 0
	mov	r0, #15	@ tmp119,
	str	r0, [r3, #-215]	@ tmp119, MEM[(volatile struct dccBASE_t *)4294962176B].CNT0CLKSRC
@ ../source/HL_dcc.c:84:     dccREG1->GCTRL      = (uint32)0xAU |       /** Enable / Disable DCC1 */
	.loc 1 84 0
	movw	r1, #42410	@ tmp121,
	str	r1, [r3, #-255]	@ tmp121, MEM[(volatile struct dccBASE_t *)4294962176B].GCTRL
@ ../source/HL_dcc.c:93:     dccREG2->CNT0SEED   = 0U;
	.loc 1 93 0
	mvn	r3, #2816	@ tmp122,
	mov	r2, #0	@ tmp123,
	str	r2, [r3, #-247]	@ tmp123, MEM[(volatile struct dccBASE_t *)4294964224B].CNT0SEED
@ ../source/HL_dcc.c:96:     dccREG2->VALID0SEED = 0U;          
	.loc 1 96 0
	str	r2, [r3, #-243]	@ tmp123, MEM[(volatile struct dccBASE_t *)4294964224B].VALID0SEED
@ ../source/HL_dcc.c:99:     dccREG2->CNT1SEED   = 0U;
	.loc 1 99 0
	str	r2, [r3, #-239]	@ tmp123, MEM[(volatile struct dccBASE_t *)4294964224B].CNT1SEED
@ ../source/HL_dcc.c:102:     dccREG2->CNT1CLKSRC = (uint32)((uint32)0xAU << 12U) |     /** DCC Enable Key */
	.loc 1 102 0
	movw	r2, #40968	@ tmp129,
	str	r2, [r3, #-219]	@ tmp129, MEM[(volatile struct dccBASE_t *)4294964224B].CNT1CLKSRC
@ ../source/HL_dcc.c:105:     dccREG2->CNT0CLKSRC = (uint32)DCC2_CNT0_OSCIN;  /** DCC2 Clock Source 0 */
	.loc 1 105 0
	str	r0, [r3, #-215]	@ tmp119, MEM[(volatile struct dccBASE_t *)4294964224B].CNT0CLKSRC
@ ../source/HL_dcc.c:108:     dccREG2->GCTRL      = (uint32)0xAU |       /** Enable DCC2 */
	.loc 1 108 0
	str	r1, [r3, #-255]	@ tmp121, MEM[(volatile struct dccBASE_t *)4294964224B].GCTRL
@ ../source/HL_dcc.c:116: }
	.loc 1 116 0
	bx	lr	@
	.cfi_endproc
.LFE0:
	.size	dccInit, .-dccInit
	.align	2
	.global	dccSetCounter0Seed
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccSetCounter0Seed, %function
dccSetCounter0Seed:
.LFB1:
	.loc 1 132 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL0:
@ ../source/HL_dcc.c:136:     dcc->CNT0SEED     = cnt0seed;
	.loc 1 136 0
	str	r1, [r0, #8]	@ cnt0seed, dcc_2(D)->CNT0SEED
@ ../source/HL_dcc.c:140: }
	.loc 1 140 0
	bx	lr	@
	.cfi_endproc
.LFE1:
	.size	dccSetCounter0Seed, .-dccSetCounter0Seed
	.align	2
	.global	dccSetTolerance
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccSetTolerance, %function
dccSetTolerance:
.LFB2:
	.loc 1 157 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL1:
@ ../source/HL_dcc.c:161:     dcc->VALID0SEED = valid0seed;
	.loc 1 161 0
	str	r1, [r0, #12]	@ valid0seed, dcc_2(D)->VALID0SEED
@ ../source/HL_dcc.c:165: }
	.loc 1 165 0
	bx	lr	@
	.cfi_endproc
.LFE2:
	.size	dccSetTolerance, .-dccSetTolerance
	.align	2
	.global	dccSetCounter1Seed
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccSetCounter1Seed, %function
dccSetCounter1Seed:
.LFB3:
	.loc 1 181 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL2:
@ ../source/HL_dcc.c:185:     dcc->CNT1SEED     = cnt1seed;
	.loc 1 185 0
	str	r1, [r0, #16]	@ cnt1seed, dcc_2(D)->CNT1SEED
@ ../source/HL_dcc.c:189: }
	.loc 1 189 0
	bx	lr	@
	.cfi_endproc
.LFE3:
	.size	dccSetCounter1Seed, .-dccSetCounter1Seed
	.align	2
	.global	dccSetSeed
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccSetSeed, %function
dccSetSeed:
.LFB4:
	.loc 1 208 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL3:
@ ../source/HL_dcc.c:212:     dcc->CNT0SEED   = cnt0seed;
	.loc 1 212 0
	str	r1, [r0, #8]	@ cnt0seed, dcc_2(D)->CNT0SEED
@ ../source/HL_dcc.c:213:     dcc->VALID0SEED = valid0seed;
	.loc 1 213 0
	str	r2, [r0, #12]	@ valid0seed, dcc_2(D)->VALID0SEED
@ ../source/HL_dcc.c:214:     dcc->CNT1SEED   = cnt1seed;
	.loc 1 214 0
	str	r3, [r0, #16]	@ cnt1seed, dcc_2(D)->CNT1SEED
@ ../source/HL_dcc.c:218: }
	.loc 1 218 0
	bx	lr	@
	.cfi_endproc
.LFE4:
	.size	dccSetSeed, .-dccSetSeed
	.align	2
	.global	dccSelectClockSource
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccSelectClockSource, %function
dccSelectClockSource:
.LFB5:
	.loc 1 236 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL4:
@ ../source/HL_dcc.c:241: 	                    (uint32)(cnt1_Clock_Source & 0x0000000FU));	/* Configure Clock source 1 */
	.loc 1 241 0
	and	r2, r2, #15	@ _1, cnt1_Clock_Source,
.LVL5:
@ ../source/HL_dcc.c:240:     dcc->CNT1CLKSRC  = ((uint32)((uint32)0xAU << 12U) |     		/** DCC Enable Key */
	.loc 1 240 0
	orr	r2, r2, #40960	@ _2, _1,
	str	r2, [r0, #36]	@ _2, dcc_5(D)->CNT1CLKSRC
@ ../source/HL_dcc.c:242:     dcc->CNT0CLKSRC  = cnt0_Clock_Source;  							/* Configure Clock source 0 */
	.loc 1 242 0
	str	r1, [r0, #40]	@ cnt0_Clock_Source, dcc_5(D)->CNT0CLKSRC
@ ../source/HL_dcc.c:246: }
	.loc 1 246 0
	bx	lr	@
	.cfi_endproc
.LFE5:
	.size	dccSelectClockSource, .-dccSelectClockSource
	.align	2
	.global	dccEnable
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccEnable, %function
dccEnable:
.LFB6:
	.loc 1 261 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL6:
@ ../source/HL_dcc.c:265:     dcc->GCTRL = (dcc->GCTRL & 0xFFFFFFF0U) | 0xAU; 
	.loc 1 265 0
	ldr	r3, [r0]	@ _1, dcc_5(D)->GCTRL
	bic	r3, r3, #15	@ _2, _1,
	orr	r3, r3, #10	@ _3, _2,
	str	r3, [r0]	@ _3, dcc_5(D)->GCTRL
@ ../source/HL_dcc.c:269: }
	.loc 1 269 0
	bx	lr	@
	.cfi_endproc
.LFE6:
	.size	dccEnable, .-dccEnable
	.align	2
	.global	dccDisable
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccDisable, %function
dccDisable:
.LFB7:
	.loc 1 284 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL7:
@ ../source/HL_dcc.c:288:     dcc->GCTRL = (dcc->GCTRL & 0xFFFFFFF0U) | 0x5U; 
	.loc 1 288 0
	ldr	r3, [r0]	@ _1, dcc_5(D)->GCTRL
	bic	r3, r3, #15	@ _2, _1,
	orr	r3, r3, #5	@ _3, _2,
	str	r3, [r0]	@ _3, dcc_5(D)->GCTRL
@ ../source/HL_dcc.c:292: }
	.loc 1 292 0
	bx	lr	@
	.cfi_endproc
.LFE7:
	.size	dccDisable, .-dccDisable
	.align	2
	.global	dccGetErrStatus
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccGetErrStatus, %function
dccGetErrStatus:
.LFB8:
	.loc 1 309 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL8:
@ ../source/HL_dcc.c:313:     return(dcc->STAT & 0x00000001U); 
	.loc 1 313 0
	ldr	r0, [r0, #20]	@ _1, dcc_3(D)->STAT
.LVL9:
@ ../source/HL_dcc.c:314: }
	.loc 1 314 0
	and	r0, r0, #1	@, _1,
	bx	lr	@
	.cfi_endproc
.LFE8:
	.size	dccGetErrStatus, .-dccGetErrStatus
	.align	2
	.global	dccEnableNotification
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccEnableNotification, %function
dccEnableNotification:
.LFB9:
	.loc 1 333 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL10:
@ ../source/HL_dcc.c:337:     dcc->GCTRL = ((dcc->GCTRL & 0xFFFF0F0FU) | notification); 
	.loc 1 337 0
	ldr	r3, [r0]	@ _1, dcc_5(D)->GCTRL
	bic	r3, r3, #61440	@ _2, _1,
	bic	r3, r3, #240	@ _2, _2,
	orr	r1, r3, r1	@ _3, _2, notification
.LVL11:
	str	r1, [r0]	@ _3, dcc_5(D)->GCTRL
@ ../source/HL_dcc.c:341: }
	.loc 1 341 0
	bx	lr	@
	.cfi_endproc
.LFE9:
	.size	dccEnableNotification, .-dccEnableNotification
	.align	2
	.global	dccDisableNotification
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dccDisableNotification, %function
dccDisableNotification:
.LFB10:
	.loc 1 360 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL12:
@ ../source/HL_dcc.c:364:     dcc->GCTRL = ((dcc->GCTRL & 0xFFFF0F0FU) | ((~notification) & 0x0000F0F0U));	
	.loc 1 364 0
	ldr	r3, [r0]	@ _1, dcc_7(D)->GCTRL
	bic	r3, r3, #61440	@ _2, _1,
	bic	r3, r3, #240	@ _2, _2,
	movw	r2, #61680	@ tmp118,
	bic	r1, r2, r1	@ _4, tmp118, notification
.LVL13:
	orr	r3, r3, r1	@ _5, _2, _4
	str	r3, [r0]	@ _5, dcc_7(D)->GCTRL
@ ../source/HL_dcc.c:368: }
	.loc 1 368 0
	bx	lr	@
	.cfi_endproc
.LFE10:
	.size	dccDisableNotification, .-dccDisableNotification
	.align	2
	.global	dcc1GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dcc1GetConfigValue, %function
dcc1GetConfigValue:
.LFB11:
	.loc 1 386 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL14:
@ ../source/HL_dcc.c:387:     if (type == InitialValue)
	.loc 1 387 0
	cmp	r1, #0	@ type,
	beq	.L15	@,
@ ../source/HL_dcc.c:399:         config_reg->CONFIG_GCTRL = dccREG1->GCTRL;
	.loc 1 399 0
	mvn	r3, #4864	@ tmp124,
	ldr	r2, [r3, #-255]	@ _1, MEM[(volatile struct dccBASE_t *)4294962176B].GCTRL
	str	r2, [r0]	@ _1, config_reg_10(D)->CONFIG_GCTRL
@ ../source/HL_dcc.c:400:         config_reg->CONFIG_CNT0SEED = dccREG1->CNT0SEED;
	.loc 1 400 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct dccBASE_t *)4294962176B].CNT0SEED
	str	r2, [r0, #4]	@ _2, config_reg_10(D)->CONFIG_CNT0SEED
@ ../source/HL_dcc.c:401:         config_reg->CONFIG_VALID0SEED = dccREG1->VALID0SEED;
	.loc 1 401 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct dccBASE_t *)4294962176B].VALID0SEED
	str	r2, [r0, #8]	@ _3, config_reg_10(D)->CONFIG_VALID0SEED
@ ../source/HL_dcc.c:402:         config_reg->CONFIG_CNT1SEED = dccREG1->CNT1SEED;
	.loc 1 402 0
	ldr	r2, [r3, #-239]	@ _4, MEM[(volatile struct dccBASE_t *)4294962176B].CNT1SEED
	str	r2, [r0, #12]	@ _4, config_reg_10(D)->CONFIG_CNT1SEED
@ ../source/HL_dcc.c:403:         config_reg->CONFIG_CNT1CLKSRC = dccREG1->CNT1CLKSRC;
	.loc 1 403 0
	ldr	r2, [r3, #-219]	@ _5, MEM[(volatile struct dccBASE_t *)4294962176B].CNT1CLKSRC
	str	r2, [r0, #16]	@ _5, config_reg_10(D)->CONFIG_CNT1CLKSRC
@ ../source/HL_dcc.c:404:         config_reg->CONFIG_CNT0CLKSRC = dccREG1->CNT0CLKSRC;
	.loc 1 404 0
	ldr	r3, [r3, #-215]	@ _6, MEM[(volatile struct dccBASE_t *)4294962176B].CNT0CLKSRC
	str	r3, [r0, #20]	@ _6, config_reg_10(D)->CONFIG_CNT0CLKSRC
@ ../source/HL_dcc.c:406: }
	.loc 1 406 0
	bx	lr	@
.L15:
@ ../source/HL_dcc.c:389:         config_reg->CONFIG_GCTRL = DCC1_GCTRL_CONFIGVALUE;
	.loc 1 389 0
	movw	r3, #42410	@ tmp118,
	str	r3, [r0]	@ tmp118, config_reg_10(D)->CONFIG_GCTRL
@ ../source/HL_dcc.c:390:         config_reg->CONFIG_CNT0SEED = DCC1_CNT0SEED_CONFIGVALUE;
	.loc 1 390 0
	movw	r3, #39204	@ tmp119,
	str	r3, [r0, #4]	@ tmp119, config_reg_10(D)->CONFIG_CNT0SEED
@ ../source/HL_dcc.c:391:         config_reg->CONFIG_VALID0SEED = DCC1_VALID0SEED_CONFIGVALUE;
	.loc 1 391 0
	mov	r3, #792	@ tmp120,
	str	r3, [r0, #8]	@ tmp120, config_reg_10(D)->CONFIG_VALID0SEED
@ ../source/HL_dcc.c:392:         config_reg->CONFIG_CNT1SEED = DCC1_CNT1SEED_CONFIGVALUE;
	.loc 1 392 0
	movw	r3, #21604	@ tmp121,
	movt	r3, 11	@ tmp121,
	str	r3, [r0, #12]	@ tmp121, config_reg_10(D)->CONFIG_CNT1SEED
@ ../source/HL_dcc.c:393:         config_reg->CONFIG_CNT1CLKSRC = DCC1_CNT1CLKSRC_CONFIGVALUE;
	.loc 1 393 0
	mov	r3, #40960	@ tmp122,
	str	r3, [r0, #16]	@ tmp122, config_reg_10(D)->CONFIG_CNT1CLKSRC
@ ../source/HL_dcc.c:394:         config_reg->CONFIG_CNT0CLKSRC = DCC1_CNT0CLKSRC_CONFIGVALUE;
	.loc 1 394 0
	mov	r3, #15	@ tmp123,
	str	r3, [r0, #20]	@ tmp123, config_reg_10(D)->CONFIG_CNT0CLKSRC
	bx	lr	@
	.cfi_endproc
.LFE11:
	.size	dcc1GetConfigValue, .-dcc1GetConfigValue
	.align	2
	.global	dcc2GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	dcc2GetConfigValue, %function
dcc2GetConfigValue:
.LFB12:
	.loc 1 423 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL15:
@ ../source/HL_dcc.c:424:     if (type == InitialValue)
	.loc 1 424 0
	cmp	r1, #0	@ type,
	beq	.L19	@,
@ ../source/HL_dcc.c:436:         config_reg->CONFIG_GCTRL = dccREG2->GCTRL;
	.loc 1 436 0
	mvn	r3, #2816	@ tmp124,
	ldr	r2, [r3, #-255]	@ _1, MEM[(volatile struct dccBASE_t *)4294964224B].GCTRL
	str	r2, [r0]	@ _1, config_reg_10(D)->CONFIG_GCTRL
@ ../source/HL_dcc.c:437:         config_reg->CONFIG_CNT0SEED = dccREG2->CNT0SEED;
	.loc 1 437 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct dccBASE_t *)4294964224B].CNT0SEED
	str	r2, [r0, #4]	@ _2, config_reg_10(D)->CONFIG_CNT0SEED
@ ../source/HL_dcc.c:438:         config_reg->CONFIG_VALID0SEED = dccREG2->VALID0SEED;
	.loc 1 438 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct dccBASE_t *)4294964224B].VALID0SEED
	str	r2, [r0, #8]	@ _3, config_reg_10(D)->CONFIG_VALID0SEED
@ ../source/HL_dcc.c:439:         config_reg->CONFIG_CNT1SEED = dccREG2->CNT1SEED;
	.loc 1 439 0
	ldr	r2, [r3, #-239]	@ _4, MEM[(volatile struct dccBASE_t *)4294964224B].CNT1SEED
	str	r2, [r0, #12]	@ _4, config_reg_10(D)->CONFIG_CNT1SEED
@ ../source/HL_dcc.c:440:         config_reg->CONFIG_CNT1CLKSRC = dccREG2->CNT1CLKSRC;
	.loc 1 440 0
	ldr	r2, [r3, #-219]	@ _5, MEM[(volatile struct dccBASE_t *)4294964224B].CNT1CLKSRC
	str	r2, [r0, #16]	@ _5, config_reg_10(D)->CONFIG_CNT1CLKSRC
@ ../source/HL_dcc.c:441:         config_reg->CONFIG_CNT0CLKSRC = dccREG2->CNT0CLKSRC;
	.loc 1 441 0
	ldr	r3, [r3, #-215]	@ _6, MEM[(volatile struct dccBASE_t *)4294964224B].CNT0CLKSRC
	str	r3, [r0, #20]	@ _6, config_reg_10(D)->CONFIG_CNT0CLKSRC
@ ../source/HL_dcc.c:443: }
	.loc 1 443 0
	bx	lr	@
.L19:
@ ../source/HL_dcc.c:426:         config_reg->CONFIG_GCTRL = DCC2_GCTRL_CONFIGVALUE;
	.loc 1 426 0
	movw	r3, #42410	@ tmp118,
	str	r3, [r0]	@ tmp118, config_reg_10(D)->CONFIG_GCTRL
@ ../source/HL_dcc.c:427:         config_reg->CONFIG_CNT0SEED = DCC2_CNT0SEED_CONFIGVALUE;
	.loc 1 427 0
	mov	r3, #0	@ tmp119,
	str	r3, [r0, #4]	@ tmp119, config_reg_10(D)->CONFIG_CNT0SEED
@ ../source/HL_dcc.c:428:         config_reg->CONFIG_VALID0SEED = DCC2_VALID0SEED_CONFIGVALUE;
	.loc 1 428 0
	str	r3, [r0, #8]	@ tmp119, config_reg_10(D)->CONFIG_VALID0SEED
@ ../source/HL_dcc.c:429:         config_reg->CONFIG_CNT1SEED = DCC2_CNT1SEED_CONFIGVALUE;
	.loc 1 429 0
	str	r3, [r0, #12]	@ tmp119, config_reg_10(D)->CONFIG_CNT1SEED
@ ../source/HL_dcc.c:430:         config_reg->CONFIG_CNT1CLKSRC = DCC2_CNT1CLKSRC_CONFIGVALUE;
	.loc 1 430 0
	movw	r3, #40968	@ tmp122,
	str	r3, [r0, #16]	@ tmp122, config_reg_10(D)->CONFIG_CNT1CLKSRC
@ ../source/HL_dcc.c:431:         config_reg->CONFIG_CNT0CLKSRC = DCC2_CNT0CLKSRC_CONFIGVALUE;
	.loc 1 431 0
	mov	r3, #15	@ tmp123,
	str	r3, [r0, #20]	@ tmp123, config_reg_10(D)->CONFIG_CNT0CLKSRC
	bx	lr	@
	.cfi_endproc
.LFE12:
	.size	dcc2GetConfigValue, .-dcc2GetConfigValue
.Letext0:
	.file 2 "/home/mr_halfword/ti/ccs901/ccs/tools/compiler/gcc-arm-none-eabi-7-2017-q4-major/arm-none-eabi/include/machine/_default_types.h"
	.file 3 "/home/mr_halfword/ti/ccs901/ccs/tools/compiler/gcc-arm-none-eabi-7-2017-q4-major/arm-none-eabi/include/sys/_stdint.h"
	.file 4 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_hal_stdtypes.h"
	.file 5 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_sys_common.h"
	.file 6 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_reg_dcc.h"
	.file 7 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_dcc.h"
	.section	.debug_info,"",%progbits
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	.4byte	.Ldebug_abbrev0
	.byte	0x4
	.uleb128 0x1
	.4byte	.LASF77
	.byte	0xc
	.4byte	.LASF78
	.4byte	.LASF79
	.4byte	.Ltext0
	.4byte	.Letext0
	.4byte	.Ldebug_line0
	.uleb128 0x2
	.byte	0x1
	.byte	0x6
	.4byte	.LASF0
	.uleb128 0x2
	.byte	0x1
	.byte	0x8
	.4byte	.LASF1
	.uleb128 0x2
	.byte	0x2
	.byte	0x5
	.4byte	.LASF2
	.uleb128 0x2
	.byte	0x2
	.byte	0x7
	.4byte	.LASF3
	.uleb128 0x2
	.byte	0x4
	.byte	0x5
	.4byte	.LASF4
	.uleb128 0x3
	.4byte	.LASF9
	.byte	0x2
	.byte	0x4f
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	.uleb128 0x2
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	.uleb128 0x2
	.byte	0x8
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	.uleb128 0x2
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	.ascii	"int\000"
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	.byte	0x6
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	.byte	0x28
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	.uleb128 0xa
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	.4byte	.LASF28
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	.uleb128 0x6
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	.uleb128 0x6
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	.byte	0x1
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	.uleb128 0xc
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	.uleb128 0xc
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	.uleb128 0xc
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	.byte	0x7
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	.byte	0x1
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	.uleb128 0xf
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	.byte	0x1
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	.byte	0x1
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	.4byte	.LFE11
	.byte	0x1
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	.uleb128 0xf
	.4byte	.LASF58
	.byte	0x1
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	.4byte	0x28f
	.byte	0x1
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	.uleb128 0xf
	.4byte	.LASF59
	.byte	0x1
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	.byte	0x1
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	.byte	0
	.uleb128 0xe
	.byte	0x1
	.4byte	.LASF62
	.byte	0x1
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	.byte	0x1
	.4byte	.LFB10
	.4byte	.LFE10
	.byte	0x1
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	.uleb128 0x11
	.ascii	"dcc\000"
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	.uleb128 0x12
	.4byte	.LASF63
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	.byte	0
	.uleb128 0x10
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	.uleb128 0xe
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	.uleb128 0x11
	.ascii	"dcc\000"
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	.uleb128 0x12
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	.uleb128 0x13
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	.byte	0x1
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	.byte	0x1
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	.uleb128 0x14
	.ascii	"dcc\000"
	.byte	0x1
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	.uleb128 0xe
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	.4byte	.LFB7
	.4byte	.LFE7
	.byte	0x1
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	.uleb128 0x11
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	.uleb128 0xe
	.byte	0x1
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	.uleb128 0x17
	.4byte	.LASF68
	.byte	0x1
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	.uleb128 0x18
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	.byte	0
	.uleb128 0x15
	.byte	0x1
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	.byte	0x1
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	.4byte	.LFB4
	.4byte	.LFE4
	.byte	0x1
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	.uleb128 0x16
	.ascii	"dcc\000"
	.byte	0x1
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	.byte	0x1
	.byte	0x50
	.uleb128 0x17
	.4byte	.LASF71
	.byte	0x1
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	.byte	0x1
	.byte	0x51
	.uleb128 0x17
	.4byte	.LASF72
	.byte	0x1
	.byte	0xcf
	.4byte	0x81
	.byte	0x1
	.byte	0x52
	.uleb128 0x17
	.4byte	.LASF73
	.byte	0x1
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	.4byte	0x81
	.byte	0x1
	.byte	0x53
	.byte	0
	.uleb128 0x15
	.byte	0x1
	.4byte	.LASF74
	.byte	0x1
	.byte	0xb4
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	.4byte	.LFB3
	.4byte	.LFE3
	.byte	0x1
	.byte	0x9c
	.4byte	0x478
	.uleb128 0x16
	.ascii	"dcc\000"
	.byte	0x1
	.byte	0xb4
	.4byte	0x301
	.byte	0x1
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	.uleb128 0x17
	.4byte	.LASF73
	.byte	0x1
	.byte	0xb4
	.4byte	0x81
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x15
	.byte	0x1
	.4byte	.LASF75
	.byte	0x1
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	.4byte	.LFB2
	.4byte	.LFE2
	.byte	0x1
	.byte	0x9c
	.4byte	0x4aa
	.uleb128 0x16
	.ascii	"dcc\000"
	.byte	0x1
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	.byte	0x1
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	.uleb128 0x17
	.4byte	.LASF72
	.byte	0x1
	.byte	0x9c
	.4byte	0x81
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x15
	.byte	0x1
	.4byte	.LASF76
	.byte	0x1
	.byte	0x83
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	.4byte	.LFB1
	.4byte	.LFE1
	.byte	0x1
	.byte	0x9c
	.4byte	0x4dc
	.uleb128 0x16
	.ascii	"dcc\000"
	.byte	0x1
	.byte	0x83
	.4byte	0x301
	.byte	0x1
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	.uleb128 0x17
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	.byte	0x1
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	.4byte	.LFB0
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	.section	.debug_abbrev,"",%progbits
.Ldebug_abbrev0:
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	.uleb128 0x1b
	.uleb128 0xe
	.uleb128 0x11
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	.uleb128 0x12
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	.uleb128 0xb
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	.uleb128 0x3e
	.uleb128 0xb
	.uleb128 0x3
	.uleb128 0xe
	.byte	0
	.byte	0
	.uleb128 0x3
	.uleb128 0x16
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	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
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	.uleb128 0x4
	.uleb128 0x24
	.byte	0
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3e
	.uleb128 0xb
	.uleb128 0x3
	.uleb128 0x8
	.byte	0
	.byte	0
	.uleb128 0x5
	.uleb128 0x4
	.byte	0x1
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x6
	.uleb128 0x28
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x1c
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0x7
	.uleb128 0x13
	.byte	0x1
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x8
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0x9
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0xa
	.uleb128 0x35
	.byte	0
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0xb
	.uleb128 0x13
	.byte	0x1
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0xc
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0xd
	.uleb128 0x16
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0xe
	.uleb128 0x2e
	.byte	0x1
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0xf
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x10
	.uleb128 0xf
	.byte	0
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x11
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x12
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x13
	.uleb128 0x2e
	.byte	0x1
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x14
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x15
	.uleb128 0x2e
	.byte	0x1
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x16
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x17
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x18
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x19
	.uleb128 0x2e
	.byte	0
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.byte	0
	.byte	0
	.byte	0
	.section	.debug_loc,"",%progbits
.Ldebug_loc0:
.LLST3:
	.4byte	.LVL12-.Ltext0
	.4byte	.LVL13-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST2:
	.4byte	.LVL10-.Ltext0
	.4byte	.LVL11-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST1:
	.4byte	.LVL8-.Ltext0
	.4byte	.LVL9-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST0:
	.4byte	.LVL4-.Ltext0
	.4byte	.LVL5-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	0
	.4byte	0
	.section	.debug_aranges,"",%progbits
	.4byte	0x1c
	.2byte	0x2
	.4byte	.Ldebug_info0
	.byte	0x4
	.byte	0
	.2byte	0
	.2byte	0
	.4byte	.Ltext0
	.4byte	.Letext0-.Ltext0
	.4byte	0
	.4byte	0
	.section	.debug_line,"",%progbits
.Ldebug_line0:
	.section	.debug_str,"MS",%progbits,1
.LASF63:
	.ascii	"notification\000"
.LASF48:
	.ascii	"DCC2_CNT1_N2HET2_0\000"
.LASF21:
	.ascii	"CNT1SEED\000"
.LASF59:
	.ascii	"type\000"
.LASF7:
	.ascii	"long long unsigned int\000"
.LASF72:
	.ascii	"valid0seed\000"
.LASF32:
	.ascii	"DCC1_CNT0_TCK\000"
.LASF44:
	.ascii	"DCC2_CNT0_TCK\000"
.LASF23:
	.ascii	"CNT0\000"
.LASF25:
	.ascii	"CNT1\000"
.LASF6:
	.ascii	"long long int\000"
.LASF0:
	.ascii	"signed char\000"
.LASF75:
	.ascii	"dccSetTolerance\000"
.LASF77:
	.ascii	"GNU C11 7.2.1 20170904 (release) [ARM/embedded-7-br"
	.ascii	"anch revision 255204] -mcpu=cortex-r5 -mfloat-abi=h"
	.ascii	"ard -mfpu=vfpv3-d16 -g -gdwarf-3 -gstrict-dwarf -Og"
	.ascii	"\000"
.LASF65:
	.ascii	"dccDisable\000"
.LASF4:
	.ascii	"long int\000"
.LASF80:
	.ascii	"dccGetErrStatus\000"
.LASF55:
	.ascii	"CONFIG_CNT1CLKSRC\000"
.LASF74:
	.ascii	"dccSetCounter1Seed\000"
.LASF14:
	.ascii	"double\000"
.LASF67:
	.ascii	"dccSelectClockSource\000"
.LASF26:
	.ascii	"CNT1CLKSRC\000"
.LASF42:
	.ascii	"dcc2clocksource\000"
.LASF11:
	.ascii	"uint32\000"
.LASF69:
	.ascii	"cnt1_Clock_Source\000"
.LASF53:
	.ascii	"CONFIG_VALID0SEED\000"
.LASF9:
	.ascii	"__uint32_t\000"
.LASF49:
	.ascii	"dccBase\000"
.LASF8:
	.ascii	"unsigned int\000"
.LASF17:
	.ascii	"config_value_type_t\000"
.LASF5:
	.ascii	"long unsigned int\000"
.LASF57:
	.ascii	"dcc_config_reg_t\000"
.LASF43:
	.ascii	"DCC2_CNT0_OSCIN\000"
.LASF52:
	.ascii	"CONFIG_CNT0SEED\000"
.LASF3:
	.ascii	"short unsigned int\000"
.LASF56:
	.ascii	"CONFIG_CNT0CLKSRC\000"
.LASF79:
	.ascii	"/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_hal"
	.ascii	"cogen/Debug\000"
.LASF68:
	.ascii	"cnt0_Clock_Source\000"
.LASF19:
	.ascii	"CNT0SEED\000"
.LASF15:
	.ascii	"InitialValue\000"
.LASF18:
	.ascii	"GCTRL\000"
.LASF47:
	.ascii	"DCC2_CNT1_ODCLK16\000"
.LASF64:
	.ascii	"dccEnableNotification\000"
.LASF36:
	.ascii	"DCC1_CNT1_LF_LPO\000"
.LASF61:
	.ascii	"dcc1GetConfigValue\000"
.LASF16:
	.ascii	"CurrentValue\000"
.LASF78:
	.ascii	"../source/HL_dcc.c\000"
.LASF73:
	.ascii	"cnt1seed\000"
.LASF66:
	.ascii	"dccEnable\000"
.LASF41:
	.ascii	"DCC1_CNT1_N2HET1_31\000"
.LASF76:
	.ascii	"dccSetCounter0Seed\000"
.LASF24:
	.ascii	"VALID0\000"
.LASF13:
	.ascii	"float\000"
.LASF20:
	.ascii	"VALID0SEED\000"
.LASF28:
	.ascii	"dccBASE_t\000"
.LASF12:
	.ascii	"_Bool\000"
.LASF1:
	.ascii	"unsigned char\000"
.LASF2:
	.ascii	"short int\000"
.LASF37:
	.ascii	"DCC1_CNT1_HF_LPO\000"
.LASF45:
	.ascii	"DCC2_CNT1_VCLK\000"
.LASF27:
	.ascii	"CNT0CLKSRC\000"
.LASF10:
	.ascii	"uint32_t\000"
.LASF50:
	.ascii	"dcc_config_reg\000"
.LASF29:
	.ascii	"config_value_type\000"
.LASF51:
	.ascii	"CONFIG_GCTRL\000"
.LASF46:
	.ascii	"DCC2_CNT1_ODCLK8\000"
.LASF62:
	.ascii	"dccDisableNotification\000"
.LASF70:
	.ascii	"dccSetSeed\000"
.LASF38:
	.ascii	"DCC1_CNT1_EXTCLKIN1\000"
.LASF39:
	.ascii	"DCC1_CNT1_EXTCLKIN2\000"
.LASF22:
	.ascii	"STAT\000"
.LASF81:
	.ascii	"dccInit\000"
.LASF30:
	.ascii	"dcc1clocksource\000"
.LASF58:
	.ascii	"config_reg\000"
.LASF71:
	.ascii	"cnt0seed\000"
.LASF34:
	.ascii	"DCC1_CNT1_PLL1\000"
.LASF35:
	.ascii	"DCC1_CNT1_PLL2\000"
.LASF40:
	.ascii	"DCC1_CNT1_VCLK\000"
.LASF60:
	.ascii	"dcc2GetConfigValue\000"
.LASF31:
	.ascii	"DCC1_CNT0_HF_LPO\000"
.LASF33:
	.ascii	"DCC1_CNT0_OSCIN\000"
.LASF54:
	.ascii	"CONFIG_CNT1SEED\000"
	.ident	"GCC: (GNU Tools for Arm Embedded Processors 7-2017-q4-major) 7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204]"
