	.cpu cortex-r5
	.eabi_attribute 28, 1	@ Tag_ABI_VFP_args
	.eabi_attribute 20, 1	@ Tag_ABI_FP_denormal
	.eabi_attribute 21, 1	@ Tag_ABI_FP_exceptions
	.eabi_attribute 23, 3	@ Tag_ABI_FP_number_model
	.eabi_attribute 24, 1	@ Tag_ABI_align8_needed
	.eabi_attribute 25, 1	@ Tag_ABI_align8_preserved
	.eabi_attribute 26, 1	@ Tag_ABI_enum_size
	.eabi_attribute 30, 1	@ Tag_ABI_optimization_goals
	.eabi_attribute 34, 1	@ Tag_CPU_unaligned_access
	.eabi_attribute 18, 4	@ Tag_ABI_PCS_wchar_t
	.file	"HL_mibspi.c"
@ GNU C11 (GNU Tools for Arm Embedded Processors 7-2017-q4-major) version 7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204] (arm-none-eabi)
@	compiled by GNU C version 4.8.4, GMP version 6.1.0, MPFR version 3.1.4, MPC version 1.0.3, isl version isl-0.15-GMP

@ GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
@ options passed:  -fpreprocessed HL_mibspi.i -mcpu=cortex-r5
@ -mfloat-abi=hard -mfpu=vfpv3-d16 -auxbase-strip source/HL_mibspi.o -g
@ -gdwarf-3 -gstrict-dwarf -Og -Wall -fverbose-asm
@ options enabled:  -faggressive-loop-optimizations -fauto-inc-dec
@ -fchkp-check-incomplete-type -fchkp-check-read -fchkp-check-write
@ -fchkp-instrument-calls -fchkp-narrow-bounds -fchkp-optimize
@ -fchkp-store-bounds -fchkp-use-static-bounds
@ -fchkp-use-static-const-bounds -fchkp-use-wrappers
@ -fcombine-stack-adjustments -fcommon -fcompare-elim -fcprop-registers
@ -fdefer-pop -fdelete-null-pointer-checks -fdwarf2-cfi-asm
@ -fearly-inlining -feliminate-unused-debug-types -fforward-propagate
@ -ffp-int-builtin-inexact -ffunction-cse -fgcse-lm -fgnu-runtime
@ -fgnu-unique -fguess-branch-probability -fident -finline -finline-atomics
@ -fipa-profile -fipa-pure-const -fipa-reference -fira-hoist-pressure
@ -fira-share-save-slots -fira-share-spill-slots -fivopts
@ -fkeep-static-consts -fleading-underscore -flifetime-dse
@ -flto-odr-type-merging -fmath-errno -fmerge-constants
@ -fmerge-debug-strings -fomit-frame-pointer -fpeephole -fplt
@ -fprefetch-loop-arrays -freg-struct-return -freorder-blocks
@ -fsched-critical-path-heuristic -fsched-dep-count-heuristic
@ -fsched-group-heuristic -fsched-interblock -fsched-last-insn-heuristic
@ -fsched-pressure -fsched-rank-heuristic -fsched-spec
@ -fsched-spec-insn-heuristic -fsched-stalled-insns-dep -fsection-anchors
@ -fsemantic-interposition -fshow-column -fshrink-wrap
@ -fshrink-wrap-separate -fsigned-zeros -fsplit-ivs-in-unroller
@ -fsplit-wide-types -fssa-backprop -fstdarg-opt
@ -fstrict-volatile-bitfields -fsync-libcalls -ftoplevel-reorder
@ -ftrapping-math -ftree-builtin-call-dce -ftree-ccp -ftree-ch
@ -ftree-coalesce-vars -ftree-copy-prop -ftree-cselim -ftree-dce
@ -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre
@ -ftree-loop-if-convert -ftree-loop-im -ftree-loop-ivcanon
@ -ftree-loop-optimize -ftree-parallelize-loops= -ftree-phiprop
@ -ftree-reassoc -ftree-scev-cprop -ftree-sink -ftree-slsr -ftree-ter
@ -funit-at-a-time -fvar-tracking -fvar-tracking-assignments -fverbose-asm
@ -fzero-initialized-in-bss -gstrict-dwarf -marm -mlittle-endian
@ -mpic-data-is-text-relative -msched-prolog -munaligned-access
@ -mvectorize-with-neon-quad

	.text
.Ltext0:
	.cfi_sections	.debug_frame
	.align	2
	.global	mibspiInit
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiInit, %function
mibspiInit:
.LFB0:
	.file 1 "../source/HL_mibspi.c"
	.loc 1 60 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
@ ../source/HL_mibspi.c:70:     mibspiREG1->GCR0 = 0U;
	.loc 1 70 0
	movw	r3, #62719	@ tmp215,
	movt	r3, 65527	@ tmp215,
	mov	r1, #0	@ tmp216,
	str	r1, [r3, #-255]	@ tmp216, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR0
@ ../source/HL_mibspi.c:71:     mibspiREG1->GCR0 = 1U;
	.loc 1 71 0
	mov	r2, #1	@ tmp218,
	str	r2, [r3, #-255]	@ tmp218, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR0
@ ../source/HL_mibspi.c:74:     mibspiREG1->MIBSPIE = (mibspiREG1->MIBSPIE & 0xFFFFFFFEU) | 1U;
	.loc 1 74 0
	ldr	r2, [r3, #-143]	@ _1, MEM[(volatile struct mibspiBASE_t *)4294439936B].MIBSPIE
	orr	r2, r2, #1	@ _2, _1,
	str	r2, [r3, #-143]	@ _2, MEM[(volatile struct mibspiBASE_t *)4294439936B].MIBSPIE
@ ../source/HL_mibspi.c:77:     mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
	.loc 1 77 0
	ldr	r2, [r3, #-251]	@ _3, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR1
	orr	r2, r2, #3	@ _4, _3,
	str	r2, [r3, #-251]	@ _4, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR1
@ ../source/HL_mibspi.c:81:     mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
	.loc 1 81 0
	ldr	r2, [r3, #-247]	@ _5, MEM[(volatile struct mibspiBASE_t *)4294439936B].INT0
	bic	r2, r2, #16777216	@ _6, _5,
	str	r2, [r3, #-247]	@ _6, MEM[(volatile struct mibspiBASE_t *)4294439936B].INT0
@ ../source/HL_mibspi.c:84:     mibspiREG1->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
	.loc 1 84 0
	str	r1, [r3, #-183]	@ tmp216, MEM[(volatile struct mibspiBASE_t *)4294439936B].DELAY
@ ../source/HL_mibspi.c:90:     mibspiREG1->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 90 0
	movw	r2, #18960	@ tmp228,
	str	r2, [r3, #-175]	@ tmp228, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT0
@ ../source/HL_mibspi.c:101:     mibspiREG1->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 101 0
	str	r2, [r3, #-171]	@ tmp228, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT1
@ ../source/HL_mibspi.c:112:     mibspiREG1->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 112 0
	str	r2, [r3, #-167]	@ tmp228, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT2
@ ../source/HL_mibspi.c:123:     mibspiREG1->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 123 0
	str	r2, [r3, #-163]	@ tmp228, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT3
@ ../source/HL_mibspi.c:134:     mibspiREG1->DEF = (uint32)(0xFFU);
	.loc 1 134 0
	mov	r2, #255	@ tmp236,
	str	r2, [r3, #-179]	@ tmp236, MEM[(volatile struct mibspiBASE_t *)4294439936B].DEF
.L2:
@ ../source/HL_mibspi.c:138:     while ((mibspiREG1->FLG & 0x01000000U) != 0U)
	.loc 1 138 0
	movw	r3, #62719	@ tmp237,
	movt	r3, 65527	@ tmp237,
	ldr	r3, [r3, #-239]	@ _7, MEM[(volatile struct mibspiBASE_t *)4294439936B].FLG
	tst	r3, #16777216	@ _7,
	bne	.L2	@,
@ ../source/HL_mibspi.c:143:     mibspiREG1->PAR_ECC_CTRL = (mibspiREG1->PAR_ECC_CTRL & 0xFFFFFFF0U) | (0x00000005U);
	.loc 1 143 0
	movw	r3, #62719	@ tmp238,
	movt	r3, 65527	@ tmp238,
	ldr	r2, [r3, #33]	@ _9, MEM[(volatile struct mibspiBASE_t *)4294439936B].PAR_ECC_CTRL
	bic	r2, r2, #15	@ _10, _9,
	orr	r2, r2, #5	@ _11, _10,
	str	r2, [r3, #33]	@ _11, MEM[(volatile struct mibspiBASE_t *)4294439936B].PAR_ECC_CTRL
@ ../source/HL_mibspi.c:146:     mibspiREG1->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 146 0
	mov	r2, #0	@ tmp241,
	movt	r2, 16496	@ tmp241,
	str	r2, [r3, #-103]	@ tmp241, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:152:     mibspiREG1->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 152 0
	mov	r2, #2048	@ tmp243,
	movt	r2, 16496	@ tmp243,
	str	r2, [r3, #-99]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:158:     mibspiREG1->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 158 0
	str	r2, [r3, #-95]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:164:     mibspiREG1->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 164 0
	str	r2, [r3, #-91]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:170:     mibspiREG1->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 170 0
	str	r2, [r3, #-87]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:176:     mibspiREG1->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 176 0
	str	r2, [r3, #-83]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:182:     mibspiREG1->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 182 0
	str	r2, [r3, #-79]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:188:     mibspiREG1->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 188 0
	str	r2, [r3, #-75]	@ tmp243, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:195:     mibspiREG1->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
	.loc 1 195 0
	mov	r2, #2048	@ tmp257,
	str	r2, [r3, #-71]	@ tmp257, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
@ ../source/HL_mibspi.c:197:     mibspiREG1->LTGPEND = (mibspiREG1->LTGPEND & 0xFFFF00FFU) | (uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
	.loc 1 197 0
	ldr	r2, [r3, #-107]	@ _12, MEM[(volatile struct mibspiBASE_t *)4294439936B].LTGPEND
	bic	r2, r2, #65280	@ _13, _12,
	orr	r2, r2, #1792	@ _14, _13,
	str	r2, [r3, #-107]	@ _14, MEM[(volatile struct mibspiBASE_t *)4294439936B].LTGPEND
.LVL0:
@ ../source/HL_mibspi.c:201:         i = 0U;
	.loc 1 201 0
	mov	r3, #0	@ i,
@ ../source/HL_mibspi.c:208:             while (i < (8U-1U))
	.loc 1 208 0
	b	.L3	@
.LVL1:
.L4:
@ ../source/HL_mibspi.c:210:                 mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 210 0
	lsl	r2, r3, #2	@ tmp261, i,
	sub	r2, r2, #15859712	@ tmp262, tmp261,
	movw	r1, #33022	@ tmp264,
	movt	r1, 65535	@ tmp264,
	strh	r1, [r2]	@ movhi	@ tmp264, MEM[(volatile struct mibspiRAM_t *)4279107584B].tx[i_101].control
.LVL2:
@ ../source/HL_mibspi.c:216:                 i++;
	.loc 1 216 0
	add	r3, r3, #1	@ i, i,
.LVL3:
.L3:
@ ../source/HL_mibspi.c:208:             while (i < (8U-1U))
	.loc 1 208 0
	cmp	r3, #6	@ i,
	bls	.L4	@,
@ ../source/HL_mibspi.c:219:             mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 219 0
	lsl	r3, r3, #2	@ tmp266, i,
	sub	r3, r3, #15859712	@ tmp267, tmp266,
	movw	r2, #33022	@ tmp269,
	movt	r2, 65535	@ tmp269,
	strh	r2, [r3]	@ movhi	@ tmp269, MEM[(volatile struct mibspiRAM_t *)4279107584B].tx[i_101].control
@ ../source/HL_mibspi.c:420:     mibspiREG1->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
	.loc 1 420 0
	movw	r3, #62719	@ tmp270,
	movt	r3, 65527	@ tmp270,
	mov	r2, #0	@ tmp271,
	str	r2, [r3, #-243]	@ tmp271, MEM[(volatile struct mibspiBASE_t *)4294439936B].LVL
@ ../source/HL_mibspi.c:430:     mibspiREG1->FLG |= 0xFFFFU;
	.loc 1 430 0
	ldr	r1, [r3, #-239]	@ _15, MEM[(volatile struct mibspiBASE_t *)4294439936B].FLG
	mvn	r1, r1, lsr #16	@ _16, _15,
	mvn	r1, r1, lsl #16	@ _16, _16,
	str	r1, [r3, #-239]	@ _16, MEM[(volatile struct mibspiBASE_t *)4294439936B].FLG
@ ../source/HL_mibspi.c:433:     mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFFFF0000U)
	.loc 1 433 0
	ldr	r1, [r3, #-247]	@ _17, MEM[(volatile struct mibspiBASE_t *)4294439936B].INT0
@ ../source/HL_mibspi.c:441:                      | (uint32)((uint32)0U << 0U); /* DLENERR */
	.loc 1 441 0
	lsr	r1, r1, #16	@ _18, _17,
	lsl	r1, r1, #16	@ _18, _18,
@ ../source/HL_mibspi.c:433:     mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFFFF0000U)
	.loc 1 433 0
	str	r1, [r3, #-247]	@ _18, MEM[(volatile struct mibspiBASE_t *)4294439936B].INT0
@ ../source/HL_mibspi.c:446:     mibspiREG1->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 446 0
	mov	r1, #63	@ tmp279,
	str	r1, [r3, #-223]	@ tmp279, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC3
@ ../source/HL_mibspi.c:460:     mibspiREG1->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 460 0
	movw	r1, #1599	@ tmp281,
	str	r1, [r3, #-231]	@ tmp281, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC1
@ ../source/HL_mibspi.c:474:     mibspiREG1->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 474 0
	str	r2, [r3, #-211]	@ tmp271, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC6
@ ../source/HL_mibspi.c:488:     mibspiREG1->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 488 0
	movw	r1, #3903	@ tmp285,
	movt	r1, 514	@ tmp285,
	str	r1, [r3, #-203]	@ tmp285, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC8
@ ../source/HL_mibspi.c:502:     mibspiREG1->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 502 0
	str	r2, [r3, #-207]	@ tmp271, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC7
@ ../source/HL_mibspi.c:516:     mibspiREG1->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 516 0
	movw	r1, #3841	@ tmp289,
	movt	r1, 514	@ tmp289,
	str	r1, [r3, #-235]	@ tmp289, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC0
@ ../source/HL_mibspi.c:530:     mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
	.loc 1 530 0
	ldr	r1, [r3, #-251]	@ _19, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR1
	orr	r1, r1, #16777216	@ _20, _19,
	str	r1, [r3, #-251]	@ _20, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR1
@ ../source/HL_mibspi.c:536:     mibspiREG2->GCR0 = 0U;
	.loc 1 536 0
	movw	r3, #63231	@ tmp292,
	movt	r3, 65527	@ tmp292,
	str	r2, [r3, #-255]	@ tmp271, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR0
@ ../source/HL_mibspi.c:537:     mibspiREG2->GCR0 = 1U;
	.loc 1 537 0
	mov	r1, #1	@ tmp295,
	str	r1, [r3, #-255]	@ tmp295, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR0
@ ../source/HL_mibspi.c:540:     mibspiREG2->MIBSPIE = (mibspiREG2->MIBSPIE & 0xFFFFFFFEU) | 1U;
	.loc 1 540 0
	ldr	r1, [r3, #-143]	@ _21, MEM[(volatile struct mibspiBASE_t *)4294440448B].MIBSPIE
	orr	r1, r1, #1	@ _22, _21,
	str	r1, [r3, #-143]	@ _22, MEM[(volatile struct mibspiBASE_t *)4294440448B].MIBSPIE
@ ../source/HL_mibspi.c:543:     mibspiREG2->GCR1 = (mibspiREG2->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
	.loc 1 543 0
	ldr	r1, [r3, #-251]	@ _23, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR1
	orr	r1, r1, #3	@ _24, _23,
	str	r1, [r3, #-251]	@ _24, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR1
@ ../source/HL_mibspi.c:547:     mibspiREG2->INT0 = (mibspiREG2->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
	.loc 1 547 0
	ldr	r1, [r3, #-247]	@ _25, MEM[(volatile struct mibspiBASE_t *)4294440448B].INT0
	bic	r1, r1, #16777216	@ _26, _25,
	str	r1, [r3, #-247]	@ _26, MEM[(volatile struct mibspiBASE_t *)4294440448B].INT0
@ ../source/HL_mibspi.c:550:     mibspiREG2->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
	.loc 1 550 0
	str	r2, [r3, #-183]	@ tmp271, MEM[(volatile struct mibspiBASE_t *)4294440448B].DELAY
@ ../source/HL_mibspi.c:556:     mibspiREG2->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 556 0
	movw	r2, #18960	@ tmp305,
	str	r2, [r3, #-175]	@ tmp305, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT0
@ ../source/HL_mibspi.c:567:     mibspiREG2->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 567 0
	str	r2, [r3, #-171]	@ tmp305, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT1
@ ../source/HL_mibspi.c:578:     mibspiREG2->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 578 0
	str	r2, [r3, #-167]	@ tmp305, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT2
@ ../source/HL_mibspi.c:589:     mibspiREG2->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 589 0
	str	r2, [r3, #-163]	@ tmp305, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT3
@ ../source/HL_mibspi.c:600:     mibspiREG2->DEF = (uint32)(0xFFU);
	.loc 1 600 0
	mov	r2, #255	@ tmp313,
	str	r2, [r3, #-179]	@ tmp313, MEM[(volatile struct mibspiBASE_t *)4294440448B].DEF
.L5:
@ ../source/HL_mibspi.c:604:     while ((mibspiREG2->FLG & 0x01000000U) != 0U)
	.loc 1 604 0
	movw	r3, #63231	@ tmp314,
	movt	r3, 65527	@ tmp314,
	ldr	r3, [r3, #-239]	@ _27, MEM[(volatile struct mibspiBASE_t *)4294440448B].FLG
	tst	r3, #16777216	@ _27,
	bne	.L5	@,
@ ../source/HL_mibspi.c:609:     mibspiREG2->PAR_ECC_CTRL = (mibspiREG2->PAR_ECC_CTRL & 0xFFFFFFF0U) | (0x00000005U);
	.loc 1 609 0
	movw	r3, #63231	@ tmp315,
	movt	r3, 65527	@ tmp315,
	ldr	r2, [r3, #33]	@ _29, MEM[(volatile struct mibspiBASE_t *)4294440448B].PAR_ECC_CTRL
	bic	r2, r2, #15	@ _30, _29,
	orr	r2, r2, #5	@ _31, _30,
	str	r2, [r3, #33]	@ _31, MEM[(volatile struct mibspiBASE_t *)4294440448B].PAR_ECC_CTRL
@ ../source/HL_mibspi.c:612:     mibspiREG2->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 612 0
	mov	r2, #0	@ tmp318,
	movt	r2, 16496	@ tmp318,
	str	r2, [r3, #-103]	@ tmp318, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:618:     mibspiREG2->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 618 0
	mov	r2, #2048	@ tmp320,
	movt	r2, 16496	@ tmp320,
	str	r2, [r3, #-99]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:624:     mibspiREG2->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 624 0
	str	r2, [r3, #-95]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:630:     mibspiREG2->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 630 0
	str	r2, [r3, #-91]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:636:     mibspiREG2->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 636 0
	str	r2, [r3, #-87]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:642:     mibspiREG2->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 642 0
	str	r2, [r3, #-83]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:648:     mibspiREG2->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 648 0
	str	r2, [r3, #-79]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:654:     mibspiREG2->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 654 0
	str	r2, [r3, #-75]	@ tmp320, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:661:     mibspiREG2->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
	.loc 1 661 0
	mov	r2, #2048	@ tmp334,
	str	r2, [r3, #-71]	@ tmp334, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
@ ../source/HL_mibspi.c:663:     mibspiREG2->LTGPEND = (mibspiREG2->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
	.loc 1 663 0
	ldr	r2, [r3, #-107]	@ _32, MEM[(volatile struct mibspiBASE_t *)4294440448B].LTGPEND
	bic	r2, r2, #65280	@ _33, _32,
	orr	r2, r2, #1792	@ _34, _33,
	str	r2, [r3, #-107]	@ _34, MEM[(volatile struct mibspiBASE_t *)4294440448B].LTGPEND
.LVL4:
@ ../source/HL_mibspi.c:667:         i = 0U;
	.loc 1 667 0
	mov	r3, #0	@ i,
@ ../source/HL_mibspi.c:674:             while (i < (8U-1U))
	.loc 1 674 0
	b	.L6	@
.LVL5:
.L7:
@ ../source/HL_mibspi.c:676:                 mibspiRAM2->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 676 0
	lsl	r2, r3, #2	@ tmp338, i,
	sub	r2, r2, #16252928	@ tmp339, tmp338,
	movw	r1, #33022	@ tmp341,
	movt	r1, 65535	@ tmp341,
	strh	r1, [r2]	@ movhi	@ tmp341, MEM[(volatile struct mibspiRAM_t *)4278714368B].tx[i_102].control
.LVL6:
@ ../source/HL_mibspi.c:682:                 i++;
	.loc 1 682 0
	add	r3, r3, #1	@ i, i,
.LVL7:
.L6:
@ ../source/HL_mibspi.c:674:             while (i < (8U-1U))
	.loc 1 674 0
	cmp	r3, #6	@ i,
	bls	.L7	@,
@ ../source/HL_mibspi.c:685:             mibspiRAM2->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 685 0
	lsl	r3, r3, #2	@ tmp343, i,
	sub	r3, r3, #16252928	@ tmp344, tmp343,
	movw	r2, #33022	@ tmp346,
	movt	r2, 65535	@ tmp346,
	strh	r2, [r3]	@ movhi	@ tmp346, MEM[(volatile struct mibspiRAM_t *)4278714368B].tx[i_102].control
@ ../source/HL_mibspi.c:886:     mibspiREG2->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
	.loc 1 886 0
	movw	r3, #63231	@ tmp347,
	movt	r3, 65527	@ tmp347,
	mov	r2, #0	@ tmp348,
	str	r2, [r3, #-243]	@ tmp348, MEM[(volatile struct mibspiBASE_t *)4294440448B].LVL
@ ../source/HL_mibspi.c:896:     mibspiREG2->FLG |= 0xFFFFU;
	.loc 1 896 0
	ldr	r1, [r3, #-239]	@ _35, MEM[(volatile struct mibspiBASE_t *)4294440448B].FLG
	mvn	r1, r1, lsr #16	@ _36, _35,
	mvn	r1, r1, lsl #16	@ _36, _36,
	str	r1, [r3, #-239]	@ _36, MEM[(volatile struct mibspiBASE_t *)4294440448B].FLG
@ ../source/HL_mibspi.c:899:     mibspiREG2->INT0 = (mibspiREG2->INT0 & 0xFFFF0000U)
	.loc 1 899 0
	ldr	r1, [r3, #-247]	@ _37, MEM[(volatile struct mibspiBASE_t *)4294440448B].INT0
@ ../source/HL_mibspi.c:907:                      | (uint32)((uint32)0U << 0U); /* DLENERR */
	.loc 1 907 0
	lsr	r1, r1, #16	@ _38, _37,
	lsl	r1, r1, #16	@ _38, _38,
@ ../source/HL_mibspi.c:899:     mibspiREG2->INT0 = (mibspiREG2->INT0 & 0xFFFF0000U)
	.loc 1 899 0
	str	r1, [r3, #-247]	@ _38, MEM[(volatile struct mibspiBASE_t *)4294440448B].INT0
@ ../source/HL_mibspi.c:912:     mibspiREG2->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 912 0
	mov	r1, #3	@ tmp356,
	str	r1, [r3, #-223]	@ tmp356, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC3
@ ../source/HL_mibspi.c:920:     mibspiREG2->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 920 0
	movw	r1, #1539	@ tmp358,
	str	r1, [r3, #-231]	@ tmp358, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC1
@ ../source/HL_mibspi.c:928:     mibspiREG2->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 928 0
	str	r2, [r3, #-211]	@ tmp348, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC6
@ ../source/HL_mibspi.c:937:     mibspiREG2->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 937 0
	movw	r1, #3843	@ tmp362,
	str	r1, [r3, #-203]	@ tmp362, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC8
@ ../source/HL_mibspi.c:946:     mibspiREG2->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 946 0
	str	r2, [r3, #-207]	@ tmp348, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC7
@ ../source/HL_mibspi.c:955:     mibspiREG2->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 955 0
	movw	r1, #3841	@ tmp366,
	str	r1, [r3, #-235]	@ tmp366, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC0
@ ../source/HL_mibspi.c:963:     mibspiREG2->GCR1 = (mibspiREG2->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
	.loc 1 963 0
	ldr	r1, [r3, #-251]	@ _39, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR1
	orr	r1, r1, #16777216	@ _40, _39,
	str	r1, [r3, #-251]	@ _40, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR1
@ ../source/HL_mibspi.c:970:     mibspiREG3->GCR0 = 0U;
	.loc 1 970 0
	movw	r3, #63743	@ tmp369,
	movt	r3, 65527	@ tmp369,
	str	r2, [r3, #-255]	@ tmp348, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR0
@ ../source/HL_mibspi.c:971:     mibspiREG3->GCR0 = 1U;
	.loc 1 971 0
	mov	r1, #1	@ tmp372,
	str	r1, [r3, #-255]	@ tmp372, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR0
@ ../source/HL_mibspi.c:974:     mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U;
	.loc 1 974 0
	ldr	r1, [r3, #-143]	@ _41, MEM[(volatile struct mibspiBASE_t *)4294440960B].MIBSPIE
	orr	r1, r1, #1	@ _42, _41,
	str	r1, [r3, #-143]	@ _42, MEM[(volatile struct mibspiBASE_t *)4294440960B].MIBSPIE
@ ../source/HL_mibspi.c:977:     mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
	.loc 1 977 0
	ldr	r1, [r3, #-251]	@ _43, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR1
	orr	r1, r1, #3	@ _44, _43,
	str	r1, [r3, #-251]	@ _44, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR1
@ ../source/HL_mibspi.c:981:     mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
	.loc 1 981 0
	ldr	r1, [r3, #-247]	@ _45, MEM[(volatile struct mibspiBASE_t *)4294440960B].INT0
	bic	r1, r1, #16777216	@ _46, _45,
	str	r1, [r3, #-247]	@ _46, MEM[(volatile struct mibspiBASE_t *)4294440960B].INT0
@ ../source/HL_mibspi.c:984:     mibspiREG3->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
	.loc 1 984 0
	str	r2, [r3, #-183]	@ tmp348, MEM[(volatile struct mibspiBASE_t *)4294440960B].DELAY
@ ../source/HL_mibspi.c:990:     mibspiREG3->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 990 0
	movw	r2, #18960	@ tmp382,
	str	r2, [r3, #-175]	@ tmp382, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT0
@ ../source/HL_mibspi.c:1001:     mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1001 0
	str	r2, [r3, #-171]	@ tmp382, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT1
@ ../source/HL_mibspi.c:1012:     mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1012 0
	str	r2, [r3, #-167]	@ tmp382, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT2
@ ../source/HL_mibspi.c:1023:     mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1023 0
	str	r2, [r3, #-163]	@ tmp382, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT3
@ ../source/HL_mibspi.c:1034:     mibspiREG3->DEF = (uint32)(0xFFU);
	.loc 1 1034 0
	mov	r2, #255	@ tmp390,
	str	r2, [r3, #-179]	@ tmp390, MEM[(volatile struct mibspiBASE_t *)4294440960B].DEF
.L8:
@ ../source/HL_mibspi.c:1038:     while ((mibspiREG3->FLG & 0x01000000U) != 0U)
	.loc 1 1038 0
	movw	r3, #63743	@ tmp391,
	movt	r3, 65527	@ tmp391,
	ldr	r3, [r3, #-239]	@ _47, MEM[(volatile struct mibspiBASE_t *)4294440960B].FLG
	tst	r3, #16777216	@ _47,
	bne	.L8	@,
@ ../source/HL_mibspi.c:1043:     mibspiREG3->PAR_ECC_CTRL = (mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0U) | (0x00000005U);
	.loc 1 1043 0
	movw	r3, #63743	@ tmp392,
	movt	r3, 65527	@ tmp392,
	ldr	r2, [r3, #33]	@ _49, MEM[(volatile struct mibspiBASE_t *)4294440960B].PAR_ECC_CTRL
	bic	r2, r2, #15	@ _50, _49,
	orr	r2, r2, #5	@ _51, _50,
	str	r2, [r3, #33]	@ _51, MEM[(volatile struct mibspiBASE_t *)4294440960B].PAR_ECC_CTRL
@ ../source/HL_mibspi.c:1046:     mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1046 0
	mov	r2, #0	@ tmp395,
	movt	r2, 16496	@ tmp395,
	str	r2, [r3, #-103]	@ tmp395, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1052:     mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1052 0
	mov	r2, #2048	@ tmp397,
	movt	r2, 16496	@ tmp397,
	str	r2, [r3, #-99]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1058:     mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1058 0
	str	r2, [r3, #-95]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1064:     mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1064 0
	str	r2, [r3, #-91]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1070:     mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1070 0
	str	r2, [r3, #-87]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1076:     mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1076 0
	str	r2, [r3, #-83]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1082:     mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1082 0
	str	r2, [r3, #-79]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1088:     mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1088 0
	str	r2, [r3, #-75]	@ tmp397, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1095:     mibspiREG3->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
	.loc 1 1095 0
	mov	r2, #2048	@ tmp411,
	str	r2, [r3, #-71]	@ tmp411, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
@ ../source/HL_mibspi.c:1097:     mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
	.loc 1 1097 0
	ldr	r2, [r3, #-107]	@ _52, MEM[(volatile struct mibspiBASE_t *)4294440960B].LTGPEND
	bic	r2, r2, #65280	@ _53, _52,
	orr	r2, r2, #1792	@ _54, _53,
	str	r2, [r3, #-107]	@ _54, MEM[(volatile struct mibspiBASE_t *)4294440960B].LTGPEND
.LVL8:
@ ../source/HL_mibspi.c:1101:         i = 0U;
	.loc 1 1101 0
	mov	r3, #0	@ i,
@ ../source/HL_mibspi.c:1108:             while (i < (8U-1U))
	.loc 1 1108 0
	b	.L9	@
.LVL9:
.L10:
@ ../source/HL_mibspi.c:1110:                 mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 1110 0
	lsl	r2, r3, #2	@ tmp415, i,
	sub	r2, r2, #15990784	@ tmp416, tmp415,
	movw	r1, #33022	@ tmp418,
	movt	r1, 65535	@ tmp418,
	strh	r1, [r2]	@ movhi	@ tmp418, MEM[(volatile struct mibspiRAM_t *)4278976512B].tx[i_103].control
.LVL10:
@ ../source/HL_mibspi.c:1116:                 i++;
	.loc 1 1116 0
	add	r3, r3, #1	@ i, i,
.LVL11:
.L9:
@ ../source/HL_mibspi.c:1108:             while (i < (8U-1U))
	.loc 1 1108 0
	cmp	r3, #6	@ i,
	bls	.L10	@,
@ ../source/HL_mibspi.c:1119:             mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 1119 0
	lsl	r3, r3, #2	@ tmp420, i,
	sub	r3, r3, #15990784	@ tmp421, tmp420,
	movw	r2, #33022	@ tmp423,
	movt	r2, 65535	@ tmp423,
	strh	r2, [r3]	@ movhi	@ tmp423, MEM[(volatile struct mibspiRAM_t *)4278976512B].tx[i_103].control
@ ../source/HL_mibspi.c:1320:     mibspiREG3->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
	.loc 1 1320 0
	movw	r3, #63743	@ tmp424,
	movt	r3, 65527	@ tmp424,
	mov	r2, #0	@ tmp425,
	str	r2, [r3, #-243]	@ tmp425, MEM[(volatile struct mibspiBASE_t *)4294440960B].LVL
@ ../source/HL_mibspi.c:1330:     mibspiREG3->FLG |= 0xFFFFU;
	.loc 1 1330 0
	ldr	r1, [r3, #-239]	@ _55, MEM[(volatile struct mibspiBASE_t *)4294440960B].FLG
	mvn	r1, r1, lsr #16	@ _56, _55,
	mvn	r1, r1, lsl #16	@ _56, _56,
	str	r1, [r3, #-239]	@ _56, MEM[(volatile struct mibspiBASE_t *)4294440960B].FLG
@ ../source/HL_mibspi.c:1333:     mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
	.loc 1 1333 0
	ldr	r1, [r3, #-247]	@ _57, MEM[(volatile struct mibspiBASE_t *)4294440960B].INT0
@ ../source/HL_mibspi.c:1341:                      | (uint32)((uint32)0U << 0U); /* DLENERR */
	.loc 1 1341 0
	lsr	r1, r1, #16	@ _58, _57,
	lsl	r1, r1, #16	@ _58, _58,
@ ../source/HL_mibspi.c:1333:     mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
	.loc 1 1333 0
	str	r1, [r3, #-247]	@ _58, MEM[(volatile struct mibspiBASE_t *)4294440960B].INT0
@ ../source/HL_mibspi.c:1346:     mibspiREG3->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1346 0
	mov	r1, #63	@ tmp433,
	str	r1, [r3, #-223]	@ tmp433, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC3
@ ../source/HL_mibspi.c:1358:     mibspiREG3->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1358 0
	movw	r1, #1599	@ tmp435,
	str	r1, [r3, #-231]	@ tmp435, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC1
@ ../source/HL_mibspi.c:1370:     mibspiREG3->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 1370 0
	str	r2, [r3, #-211]	@ tmp425, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC6
@ ../source/HL_mibspi.c:1383:     mibspiREG3->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1383 0
	movw	r1, #3903	@ tmp439,
	str	r1, [r3, #-203]	@ tmp439, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC8
@ ../source/HL_mibspi.c:1396:     mibspiREG3->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 1396 0
	str	r2, [r3, #-207]	@ tmp425, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC7
@ ../source/HL_mibspi.c:1409:     mibspiREG3->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1409 0
	movw	r1, #3841	@ tmp443,
	str	r1, [r3, #-235]	@ tmp443, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC0
@ ../source/HL_mibspi.c:1421:     mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
	.loc 1 1421 0
	ldr	r1, [r3, #-251]	@ _59, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR1
	orr	r1, r1, #16777216	@ _60, _59,
	str	r1, [r3, #-251]	@ _60, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR1
@ ../source/HL_mibspi.c:1428:     mibspiREG4->GCR0 = 0U;
	.loc 1 1428 0
	movw	r3, #64255	@ tmp446,
	movt	r3, 65527	@ tmp446,
	str	r2, [r3, #-255]	@ tmp425, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR0
@ ../source/HL_mibspi.c:1429:     mibspiREG4->GCR0 = 1U;
	.loc 1 1429 0
	mov	r1, #1	@ tmp449,
	str	r1, [r3, #-255]	@ tmp449, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR0
@ ../source/HL_mibspi.c:1432:     mibspiREG4->MIBSPIE = (mibspiREG4->MIBSPIE & 0xFFFFFFFEU) | 1U;
	.loc 1 1432 0
	ldr	r1, [r3, #-143]	@ _61, MEM[(volatile struct mibspiBASE_t *)4294441472B].MIBSPIE
	orr	r1, r1, #1	@ _62, _61,
	str	r1, [r3, #-143]	@ _62, MEM[(volatile struct mibspiBASE_t *)4294441472B].MIBSPIE
@ ../source/HL_mibspi.c:1435:     mibspiREG4->GCR1 = (mibspiREG4->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
	.loc 1 1435 0
	ldr	r1, [r3, #-251]	@ _63, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR1
	orr	r1, r1, #3	@ _64, _63,
	str	r1, [r3, #-251]	@ _64, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR1
@ ../source/HL_mibspi.c:1439:     mibspiREG4->INT0 = (mibspiREG4->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
	.loc 1 1439 0
	ldr	r1, [r3, #-247]	@ _65, MEM[(volatile struct mibspiBASE_t *)4294441472B].INT0
	bic	r1, r1, #16777216	@ _66, _65,
	str	r1, [r3, #-247]	@ _66, MEM[(volatile struct mibspiBASE_t *)4294441472B].INT0
@ ../source/HL_mibspi.c:1442:     mibspiREG4->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
	.loc 1 1442 0
	str	r2, [r3, #-183]	@ tmp425, MEM[(volatile struct mibspiBASE_t *)4294441472B].DELAY
@ ../source/HL_mibspi.c:1448:     mibspiREG4->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1448 0
	movw	r2, #18960	@ tmp459,
	str	r2, [r3, #-175]	@ tmp459, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT0
@ ../source/HL_mibspi.c:1459:     mibspiREG4->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1459 0
	str	r2, [r3, #-171]	@ tmp459, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT1
@ ../source/HL_mibspi.c:1470:     mibspiREG4->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1470 0
	str	r2, [r3, #-167]	@ tmp459, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT2
@ ../source/HL_mibspi.c:1481:     mibspiREG4->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1481 0
	str	r2, [r3, #-163]	@ tmp459, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT3
@ ../source/HL_mibspi.c:1492:     mibspiREG4->DEF = (uint32)(0xFFU);
	.loc 1 1492 0
	mov	r2, #255	@ tmp467,
	str	r2, [r3, #-179]	@ tmp467, MEM[(volatile struct mibspiBASE_t *)4294441472B].DEF
.L11:
@ ../source/HL_mibspi.c:1496:     while ((mibspiREG4->FLG & 0x01000000U) != 0U)
	.loc 1 1496 0
	movw	r3, #64255	@ tmp468,
	movt	r3, 65527	@ tmp468,
	ldr	r3, [r3, #-239]	@ _67, MEM[(volatile struct mibspiBASE_t *)4294441472B].FLG
	tst	r3, #16777216	@ _67,
	bne	.L11	@,
@ ../source/HL_mibspi.c:1501:     mibspiREG4->PAR_ECC_CTRL = (mibspiREG4->PAR_ECC_CTRL & 0xFFFFFFF0U) | (0x00000005U);
	.loc 1 1501 0
	movw	r3, #64255	@ tmp469,
	movt	r3, 65527	@ tmp469,
	ldr	r2, [r3, #33]	@ _69, MEM[(volatile struct mibspiBASE_t *)4294441472B].PAR_ECC_CTRL
	bic	r2, r2, #15	@ _70, _69,
	orr	r2, r2, #5	@ _71, _70,
	str	r2, [r3, #33]	@ _71, MEM[(volatile struct mibspiBASE_t *)4294441472B].PAR_ECC_CTRL
@ ../source/HL_mibspi.c:1504:     mibspiREG4->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1504 0
	mov	r2, #0	@ tmp472,
	movt	r2, 16496	@ tmp472,
	str	r2, [r3, #-103]	@ tmp472, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1510:     mibspiREG4->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1510 0
	mov	r2, #2048	@ tmp474,
	movt	r2, 16496	@ tmp474,
	str	r2, [r3, #-99]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1516:     mibspiREG4->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1516 0
	str	r2, [r3, #-95]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1522:     mibspiREG4->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1522 0
	str	r2, [r3, #-91]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1528:     mibspiREG4->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1528 0
	str	r2, [r3, #-87]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1534:     mibspiREG4->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1534 0
	str	r2, [r3, #-83]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1540:     mibspiREG4->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1540 0
	str	r2, [r3, #-79]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1546:     mibspiREG4->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1546 0
	str	r2, [r3, #-75]	@ tmp474, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1553:     mibspiREG4->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
	.loc 1 1553 0
	mov	r2, #2048	@ tmp488,
	str	r2, [r3, #-71]	@ tmp488, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
@ ../source/HL_mibspi.c:1555:     mibspiREG4->LTGPEND = (mibspiREG4->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
	.loc 1 1555 0
	ldr	r2, [r3, #-107]	@ _72, MEM[(volatile struct mibspiBASE_t *)4294441472B].LTGPEND
	bic	r2, r2, #65280	@ _73, _72,
	orr	r2, r2, #1792	@ _74, _73,
	str	r2, [r3, #-107]	@ _74, MEM[(volatile struct mibspiBASE_t *)4294441472B].LTGPEND
.LVL12:
@ ../source/HL_mibspi.c:1559:         i = 0U;
	.loc 1 1559 0
	mov	r3, #0	@ i,
@ ../source/HL_mibspi.c:1566:             while (i < (8U-1U))
	.loc 1 1566 0
	b	.L12	@
.LVL13:
.L13:
@ ../source/HL_mibspi.c:1568:                 mibspiRAM4->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 1568 0
	lsl	r2, r3, #2	@ tmp492, i,
	sub	r2, r2, #16384000	@ tmp493, tmp492,
	movw	r1, #33022	@ tmp495,
	movt	r1, 65535	@ tmp495,
	strh	r1, [r2]	@ movhi	@ tmp495, MEM[(volatile struct mibspiRAM_t *)4278583296B].tx[i_104].control
.LVL14:
@ ../source/HL_mibspi.c:1574:                 i++;
	.loc 1 1574 0
	add	r3, r3, #1	@ i, i,
.LVL15:
.L12:
@ ../source/HL_mibspi.c:1566:             while (i < (8U-1U))
	.loc 1 1566 0
	cmp	r3, #6	@ i,
	bls	.L13	@,
@ ../source/HL_mibspi.c:1577:             mibspiRAM4->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 1577 0
	lsl	r3, r3, #2	@ tmp497, i,
	sub	r3, r3, #16384000	@ tmp498, tmp497,
	movw	r2, #33022	@ tmp500,
	movt	r2, 65535	@ tmp500,
	strh	r2, [r3]	@ movhi	@ tmp500, MEM[(volatile struct mibspiRAM_t *)4278583296B].tx[i_104].control
@ ../source/HL_mibspi.c:1778:     mibspiREG4->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
	.loc 1 1778 0
	movw	r3, #64255	@ tmp501,
	movt	r3, 65527	@ tmp501,
	mov	r2, #0	@ tmp502,
	str	r2, [r3, #-243]	@ tmp502, MEM[(volatile struct mibspiBASE_t *)4294441472B].LVL
@ ../source/HL_mibspi.c:1788:     mibspiREG4->FLG |= 0xFFFFU;
	.loc 1 1788 0
	ldr	r1, [r3, #-239]	@ _75, MEM[(volatile struct mibspiBASE_t *)4294441472B].FLG
	mvn	r1, r1, lsr #16	@ _76, _75,
	mvn	r1, r1, lsl #16	@ _76, _76,
	str	r1, [r3, #-239]	@ _76, MEM[(volatile struct mibspiBASE_t *)4294441472B].FLG
@ ../source/HL_mibspi.c:1791:     mibspiREG4->INT0 = (mibspiREG4->INT0 & 0xFFFF0000U)
	.loc 1 1791 0
	ldr	r1, [r3, #-247]	@ _77, MEM[(volatile struct mibspiBASE_t *)4294441472B].INT0
@ ../source/HL_mibspi.c:1799:                      | (uint32)((uint32)0U << 0U); /* DLENERR */
	.loc 1 1799 0
	lsr	r1, r1, #16	@ _78, _77,
	lsl	r1, r1, #16	@ _78, _78,
@ ../source/HL_mibspi.c:1791:     mibspiREG4->INT0 = (mibspiREG4->INT0 & 0xFFFF0000U)
	.loc 1 1791 0
	str	r1, [r3, #-247]	@ _78, MEM[(volatile struct mibspiBASE_t *)4294441472B].INT0
@ ../source/HL_mibspi.c:1804:     mibspiREG4->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1804 0
	mov	r1, #63	@ tmp510,
	str	r1, [r3, #-223]	@ tmp510, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC3
@ ../source/HL_mibspi.c:1816:     mibspiREG4->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1816 0
	movw	r1, #1599	@ tmp512,
	str	r1, [r3, #-231]	@ tmp512, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC1
@ ../source/HL_mibspi.c:1828:     mibspiREG4->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 1828 0
	str	r2, [r3, #-211]	@ tmp502, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC6
@ ../source/HL_mibspi.c:1841:     mibspiREG4->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1841 0
	movw	r1, #3903	@ tmp516,
	str	r1, [r3, #-203]	@ tmp516, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC8
@ ../source/HL_mibspi.c:1854:     mibspiREG4->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 1854 0
	str	r2, [r3, #-207]	@ tmp502, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC7
@ ../source/HL_mibspi.c:1867:     mibspiREG4->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 1867 0
	movw	r1, #3841	@ tmp520,
	str	r1, [r3, #-235]	@ tmp520, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC0
@ ../source/HL_mibspi.c:1879:     mibspiREG4->GCR1 = (mibspiREG4->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
	.loc 1 1879 0
	ldr	r1, [r3, #-251]	@ _79, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR1
	orr	r1, r1, #16777216	@ _80, _79,
	str	r1, [r3, #-251]	@ _80, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR1
@ ../source/HL_mibspi.c:1886:     mibspiREG5->GCR0 = 0U;
	.loc 1 1886 0
	movw	r3, #64767	@ tmp523,
	movt	r3, 65527	@ tmp523,
	str	r2, [r3, #-255]	@ tmp502, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR0
@ ../source/HL_mibspi.c:1887:     mibspiREG5->GCR0 = 1U;
	.loc 1 1887 0
	mov	r1, #1	@ tmp526,
	str	r1, [r3, #-255]	@ tmp526, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR0
@ ../source/HL_mibspi.c:1890:     mibspiREG5->MIBSPIE = (mibspiREG5->MIBSPIE & 0xFFFFFFFEU) | 1U;
	.loc 1 1890 0
	ldr	r1, [r3, #-143]	@ _81, MEM[(volatile struct mibspiBASE_t *)4294441984B].MIBSPIE
	orr	r1, r1, #1	@ _82, _81,
	str	r1, [r3, #-143]	@ _82, MEM[(volatile struct mibspiBASE_t *)4294441984B].MIBSPIE
@ ../source/HL_mibspi.c:1893:     mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
	.loc 1 1893 0
	ldr	r1, [r3, #-251]	@ _83, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR1
	orr	r1, r1, #3	@ _84, _83,
	str	r1, [r3, #-251]	@ _84, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR1
@ ../source/HL_mibspi.c:1897:     mibspiREG5->INT0 = (mibspiREG5->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
	.loc 1 1897 0
	ldr	r1, [r3, #-247]	@ _85, MEM[(volatile struct mibspiBASE_t *)4294441984B].INT0
	bic	r1, r1, #16777216	@ _86, _85,
	str	r1, [r3, #-247]	@ _86, MEM[(volatile struct mibspiBASE_t *)4294441984B].INT0
@ ../source/HL_mibspi.c:1900:     mibspiREG5->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
	.loc 1 1900 0
	str	r2, [r3, #-183]	@ tmp502, MEM[(volatile struct mibspiBASE_t *)4294441984B].DELAY
@ ../source/HL_mibspi.c:1906:     mibspiREG5->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1906 0
	movw	r2, #18960	@ tmp536,
	str	r2, [r3, #-175]	@ tmp536, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT0
@ ../source/HL_mibspi.c:1917:     mibspiREG5->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1917 0
	str	r2, [r3, #-171]	@ tmp536, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT1
@ ../source/HL_mibspi.c:1928:     mibspiREG5->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1928 0
	str	r2, [r3, #-167]	@ tmp536, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT2
@ ../source/HL_mibspi.c:1939:     mibspiREG5->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
	.loc 1 1939 0
	str	r2, [r3, #-163]	@ tmp536, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT3
@ ../source/HL_mibspi.c:1950:     mibspiREG5->DEF = (uint32)(0xFFU);
	.loc 1 1950 0
	mov	r2, #255	@ tmp544,
	str	r2, [r3, #-179]	@ tmp544, MEM[(volatile struct mibspiBASE_t *)4294441984B].DEF
.L14:
@ ../source/HL_mibspi.c:1954:     while ((mibspiREG5->FLG & 0x01000000U) != 0U)
	.loc 1 1954 0
	movw	r3, #64767	@ tmp545,
	movt	r3, 65527	@ tmp545,
	ldr	r3, [r3, #-239]	@ _87, MEM[(volatile struct mibspiBASE_t *)4294441984B].FLG
	tst	r3, #16777216	@ _87,
	bne	.L14	@,
@ ../source/HL_mibspi.c:1959:     mibspiREG5->PAR_ECC_CTRL = (mibspiREG5->PAR_ECC_CTRL & 0xFFFFFFF0U) | (0x00000005U);
	.loc 1 1959 0
	movw	r3, #64767	@ tmp546,
	movt	r3, 65527	@ tmp546,
	ldr	r2, [r3, #33]	@ _89, MEM[(volatile struct mibspiBASE_t *)4294441984B].PAR_ECC_CTRL
	bic	r2, r2, #15	@ _90, _89,
	orr	r2, r2, #5	@ _91, _90,
	str	r2, [r3, #33]	@ _91, MEM[(volatile struct mibspiBASE_t *)4294441984B].PAR_ECC_CTRL
@ ../source/HL_mibspi.c:1962:     mibspiREG5->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1962 0
	mov	r2, #0	@ tmp549,
	movt	r2, 16496	@ tmp549,
	str	r2, [r3, #-103]	@ tmp549, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:1968:     mibspiREG5->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1968 0
	mov	r2, #2048	@ tmp551,
	movt	r2, 16496	@ tmp551,
	str	r2, [r3, #-99]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:1974:     mibspiREG5->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1974 0
	str	r2, [r3, #-95]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:1980:     mibspiREG5->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1980 0
	str	r2, [r3, #-91]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:1986:     mibspiREG5->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1986 0
	str	r2, [r3, #-87]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:1992:     mibspiREG5->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1992 0
	str	r2, [r3, #-83]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:1998:     mibspiREG5->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 1998 0
	str	r2, [r3, #-79]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:2004:     mibspiREG5->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
	.loc 1 2004 0
	str	r2, [r3, #-75]	@ tmp551, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:2011:     mibspiREG5->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
	.loc 1 2011 0
	mov	r2, #2048	@ tmp565,
	str	r2, [r3, #-71]	@ tmp565, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
@ ../source/HL_mibspi.c:2013:     mibspiREG5->LTGPEND = (mibspiREG5->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
	.loc 1 2013 0
	ldr	r2, [r3, #-107]	@ _92, MEM[(volatile struct mibspiBASE_t *)4294441984B].LTGPEND
	bic	r2, r2, #65280	@ _93, _92,
	orr	r2, r2, #1792	@ _94, _93,
	str	r2, [r3, #-107]	@ _94, MEM[(volatile struct mibspiBASE_t *)4294441984B].LTGPEND
.LVL16:
@ ../source/HL_mibspi.c:2017:         i = 0U;
	.loc 1 2017 0
	mov	r3, #0	@ i,
@ ../source/HL_mibspi.c:2024:             while (i < (8U-1U))
	.loc 1 2024 0
	b	.L15	@
.LVL17:
.L16:
@ ../source/HL_mibspi.c:2026:                 mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 2026 0
	lsl	r2, r3, #2	@ tmp569, i,
	sub	r2, r2, #16121856	@ tmp570, tmp569,
	movw	r1, #33022	@ tmp572,
	movt	r1, 65535	@ tmp572,
	strh	r1, [r2]	@ movhi	@ tmp572, MEM[(volatile struct mibspiRAM_t *)4278845440B].tx[i_105].control
.LVL18:
@ ../source/HL_mibspi.c:2032:                 i++;
	.loc 1 2032 0
	add	r3, r3, #1	@ i, i,
.LVL19:
.L15:
@ ../source/HL_mibspi.c:2024:             while (i < (8U-1U))
	.loc 1 2024 0
	cmp	r3, #6	@ i,
	bls	.L16	@,
@ ../source/HL_mibspi.c:2035:             mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
	.loc 1 2035 0
	lsl	r3, r3, #2	@ tmp574, i,
	sub	r3, r3, #16121856	@ tmp575, tmp574,
	movw	r2, #33022	@ tmp577,
	movt	r2, 65535	@ tmp577,
	strh	r2, [r3]	@ movhi	@ tmp577, MEM[(volatile struct mibspiRAM_t *)4278845440B].tx[i_105].control
@ ../source/HL_mibspi.c:2236:     mibspiREG5->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
	.loc 1 2236 0
	movw	r3, #64767	@ tmp578,
	movt	r3, 65527	@ tmp578,
	mov	r1, #0	@ tmp579,
	str	r1, [r3, #-243]	@ tmp579, MEM[(volatile struct mibspiBASE_t *)4294441984B].LVL
@ ../source/HL_mibspi.c:2246:     mibspiREG5->FLG |= 0xFFFFU;
	.loc 1 2246 0
	ldr	r2, [r3, #-239]	@ _95, MEM[(volatile struct mibspiBASE_t *)4294441984B].FLG
	mvn	r2, r2, lsr #16	@ _96, _95,
	mvn	r2, r2, lsl #16	@ _96, _96,
	str	r2, [r3, #-239]	@ _96, MEM[(volatile struct mibspiBASE_t *)4294441984B].FLG
@ ../source/HL_mibspi.c:2249:     mibspiREG5->INT0 = (mibspiREG5->INT0 & 0xFFFF0000U)
	.loc 1 2249 0
	ldr	r2, [r3, #-247]	@ _97, MEM[(volatile struct mibspiBASE_t *)4294441984B].INT0
@ ../source/HL_mibspi.c:2257:                      | (uint32)((uint32)0U << 0U); /* DLENERR */
	.loc 1 2257 0
	lsr	r2, r2, #16	@ _98, _97,
	lsl	r2, r2, #16	@ _98, _98,
@ ../source/HL_mibspi.c:2249:     mibspiREG5->INT0 = (mibspiREG5->INT0 & 0xFFFF0000U)
	.loc 1 2249 0
	str	r2, [r3, #-247]	@ _98, MEM[(volatile struct mibspiBASE_t *)4294441984B].INT0
@ ../source/HL_mibspi.c:2262:     mibspiREG5->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 2262 0
	mov	r2, #15	@ tmp587,
	str	r2, [r3, #-223]	@ tmp587, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC3
@ ../source/HL_mibspi.c:2278:     mibspiREG5->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 2278 0
	movw	r2, #1551	@ tmp589,
	str	r2, [r3, #-231]	@ tmp589, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC1
@ ../source/HL_mibspi.c:2294:     mibspiREG5->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 2294 0
	str	r1, [r3, #-211]	@ tmp579, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC6
@ ../source/HL_mibspi.c:2310:     mibspiREG5->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 2310 0
	movw	r2, #3855	@ tmp593,
	movt	r2, 3598	@ tmp593,
	str	r2, [r3, #-203]	@ tmp593, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC8
@ ../source/HL_mibspi.c:2326:     mibspiREG5->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
	.loc 1 2326 0
	str	r1, [r3, #-207]	@ tmp579, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC7
@ ../source/HL_mibspi.c:2342:     mibspiREG5->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
	.loc 1 2342 0
	movw	r2, #3841	@ tmp597,
	movt	r2, 3598	@ tmp597,
	str	r2, [r3, #-235]	@ tmp597, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC0
@ ../source/HL_mibspi.c:2358:     mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
	.loc 1 2358 0
	ldr	r2, [r3, #-251]	@ _99, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR1
	orr	r2, r2, #16777216	@ _100, _99,
	str	r2, [r3, #-251]	@ _100, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR1
@ ../source/HL_mibspi.c:2363: }
	.loc 1 2363 0
	bx	lr	@
	.cfi_endproc
.LFE0:
	.size	mibspiInit, .-mibspiInit
	.align	2
	.global	mibspiIsBuffInitialized
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiIsBuffInitialized, %function
mibspiIsBuffInitialized:
.LFB1:
	.loc 1 2375 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL20:
	sub	sp, sp, #8	@,,
	.cfi_def_cfa_offset 8
@ ../source/HL_mibspi.c:2380: 	if((mibspi->FLG & 0x01000000U) != 0x01000000U)
	.loc 1 2380 0
	ldr	r3, [r0, #16]	@ _1, mibspi_5(D)->FLG
	tst	r3, #16777216	@ _1,
	beq	.L21	@,
@ ../source/HL_mibspi.c:2386: 		status = FALSE;
	.loc 1 2386 0
	mov	r3, #0	@ tmp116,
	strb	r3, [sp, #7]	@ tmp116, status
.L19:
@ ../source/HL_mibspi.c:2391:     return (status);
	.loc 1 2391 0
	ldrb	r0, [sp, #7]	@ zero_extendqisi2	@ status, status
.LVL21:
@ ../source/HL_mibspi.c:2392: }
	.loc 1 2392 0
	add	sp, sp, #8	@,,
	.cfi_remember_state
	.cfi_def_cfa_offset 0
	@ sp needed	@
	bx	lr	@
.LVL22:
.L21:
	.cfi_restore_state
@ ../source/HL_mibspi.c:2382: 		status = TRUE;
	.loc 1 2382 0
	mov	r3, #1	@ tmp114,
	strb	r3, [sp, #7]	@ tmp114, status
	b	.L19	@
	.cfi_endproc
.LFE1:
	.size	mibspiIsBuffInitialized, .-mibspiIsBuffInitialized
	.align	2
	.global	mibspiOutofReset
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiOutofReset, %function
mibspiOutofReset:
.LFB2:
	.loc 1 2404 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL23:
@ ../source/HL_mibspi.c:2408:     mibspi->GCR0 |= 0x1U;
	.loc 1 2408 0
	ldr	r3, [r0]	@ _1, mibspi_4(D)->GCR0
	orr	r3, r3, #1	@ _2, _1,
	str	r3, [r0]	@ _2, mibspi_4(D)->GCR0
@ ../source/HL_mibspi.c:2412: }
	.loc 1 2412 0
	bx	lr	@
	.cfi_endproc
.LFE2:
	.size	mibspiOutofReset, .-mibspiOutofReset
	.align	2
	.global	mibspiReset
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiReset, %function
mibspiReset:
.LFB3:
	.loc 1 2424 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL24:
@ ../source/HL_mibspi.c:2428:     mibspi->GCR0 = 0x0U;
	.loc 1 2428 0
	mov	r3, #0	@ tmp111,
	str	r3, [r0]	@ tmp111, mibspi_2(D)->GCR0
@ ../source/HL_mibspi.c:2432: }
	.loc 1 2432 0
	bx	lr	@
	.cfi_endproc
.LFE3:
	.size	mibspiReset, .-mibspiReset
	.align	2
	.global	mibspiSetFunctional
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiSetFunctional, %function
mibspiSetFunctional:
.LFB4:
	.loc 1 2447 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL25:
@ ../source/HL_mibspi.c:2451:     mibspi->PC0 = port;
	.loc 1 2451 0
	str	r1, [r0, #20]	@ port, mibspi_2(D)->PC0
@ ../source/HL_mibspi.c:2455: }
	.loc 1 2455 0
	bx	lr	@
	.cfi_endproc
.LFE4:
	.size	mibspiSetFunctional, .-mibspiSetFunctional
	.align	2
	.global	mibspiSetData
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiSetData, %function
mibspiSetData:
.LFB5:
	.loc 1 2470 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
.LVL26:
	str	lr, [sp, #-4]!	@,
	.cfi_def_cfa_offset 4
	.cfi_offset 14, -4
@ ../source/HL_mibspi.c:2474:     mibspiRAM_t *ram    = mibspi == mibspiREG1 ? mibspiRAM1 : 
	.loc 1 2474 0
	mov	r3, #62464	@ tmp125,
	movt	r3, 65527	@ tmp125,
	cmp	r0, r3	@ mibspi, tmp125
	beq	.L33	@,
@ ../source/HL_mibspi.c:2475: 	                     (mibspi == mibspiREG2 ? mibspiRAM2 : 
	.loc 1 2475 0
	mov	r3, #62976	@ tmp126,
	movt	r3, 65527	@ tmp126,
	cmp	r0, r3	@ mibspi, tmp126
	beq	.L34	@,
@ ../source/HL_mibspi.c:2476: 						 (mibspi == mibspiREG3 ? mibspiRAM3 : 
	.loc 1 2476 0
	mov	r3, #63488	@ tmp127,
	movt	r3, 65527	@ tmp127,
	cmp	r0, r3	@ mibspi, tmp127
	beq	.L35	@,
@ ../source/HL_mibspi.c:2477: 						 (mibspi == mibspiREG4 ? mibspiRAM4 : mibspiRAM5)));
	.loc 1 2477 0
	mov	r3, #64000	@ tmp128,
	movt	r3, 65527	@ tmp128,
	cmp	r0, r3	@ mibspi, tmp128
	movne	lr, #0	@ iftmp.0_12,
	movtne	lr, 65290	@ iftmp.0_12,
	bne	.L26	@
.L40:
	mov	lr, #0	@ iftmp.0_12,
	movt	lr, 65286	@ iftmp.0_12,
	b	.L26	@
.L33:
@ ../source/HL_mibspi.c:2474:     mibspiRAM_t *ram    = mibspi == mibspiREG1 ? mibspiRAM1 : 
	.loc 1 2474 0
	mov	lr, #0	@ iftmp.0_12,
	movt	lr, 65294	@ iftmp.0_12,
.L26:
.LVL27:
@ ../source/HL_mibspi.c:2478:     uint32 start  = (mibspi->TGCTRL[group] >> 8U) & 0xFFU;
	.loc 1 2478 0
	add	r3, r1, #38	@ tmp129, group,
	ldr	r3, [r0, r3, lsl #2]	@ _1, mibspi_15(D)->TGCTRL
	ubfx	r3, r3, #8, #8	@ start, _1,,
.LVL28:
@ ../source/HL_mibspi.c:2479:     uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
	.loc 1 2479 0
	cmp	r1, #7	@ group,
	beq	.L41	@,
@ ../source/HL_mibspi.c:2479:     uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
	.loc 1 2479 0 is_stmt 0
	add	r1, r1, #39	@ tmp131, group,
.LVL29:
	ldr	r1, [r0, r1, lsl #2]	@ _7, mibspi_15(D)->TGCTRL
.LVL30:
	ubfx	r1, r1, #8, #8	@ end, _7,,
.L28:
.LVL31:
@ ../source/HL_mibspi.c:2481:     if (end == 0U) {end = 128U;}
	.loc 1 2481 0 is_stmt 1
	cmp	r1, #0	@ end,
@ ../source/HL_mibspi.c:2481:     if (end == 0U) {end = 128U;}
	.loc 1 2481 0 is_stmt 0
	moveq	r1, #128	@ end,
.LVL32:
	b	.L31	@
.LVL33:
.L34:
@ ../source/HL_mibspi.c:2475: 	                     (mibspi == mibspiREG2 ? mibspiRAM2 : 
	.loc 1 2475 0 is_stmt 1
	mov	lr, #0	@ iftmp.0_12,
	movt	lr, 65288	@ iftmp.0_12,
	b	.L26	@
.L35:
@ ../source/HL_mibspi.c:2476: 						 (mibspi == mibspiREG3 ? mibspiRAM3 : 
	.loc 1 2476 0
	mov	lr, #0	@ iftmp.0_12,
	movt	lr, 65292	@ iftmp.0_12,
	b	.L26	@
.LVL34:
.L41:
@ ../source/HL_mibspi.c:2479:     uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
	.loc 1 2479 0
	ldr	r1, [r0, #148]	@ _3, mibspi_15(D)->LTGPEND
.LVL35:
	ubfx	r1, r1, #8, #7	@ _5, _3,,
	add	r1, r1, #1	@ end, _5,
	b	.L28	@
.LVL36:
.L42:
@ ../source/HL_mibspi.c:2486:         ram->tx[start].data = *data;
	.loc 1 2486 0
	ldrh	ip, [r2], #2	@ _9, *data_10
.LVL37:
	add	r0, lr, r3, lsl #2	@ tmp133, iftmp.0_12, start,
	strh	ip, [r0, #2]	@ movhi	@ _9, iftmp.0_12->tx[start_11].data
.LVL38:
@ ../source/HL_mibspi.c:2488:         start++;
	.loc 1 2488 0
	add	r3, r3, #1	@ start, start,
.LVL39:
.L31:
@ ../source/HL_mibspi.c:2483:     while (start < end)
	.loc 1 2483 0
	cmp	r3, r1	@ start, end
	bcc	.L42	@,
	ldr	pc, [sp], #4	@
	.cfi_endproc
.LFE5:
	.size	mibspiSetData, .-mibspiSetData
	.align	2
	.global	mibspiGetData
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiGetData, %function
mibspiGetData:
.LFB6:
	.loc 1 2512 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
.LVL40:
	push	{r4, lr}	@
	.cfi_def_cfa_offset 8
	.cfi_offset 4, -8
	.cfi_offset 14, -4
@ ../source/HL_mibspi.c:2516:     mibspiRAM_t *ram    = mibspi == mibspiREG1 ? mibspiRAM1 : 
	.loc 1 2516 0
	mov	r3, #62464	@ tmp130,
	movt	r3, 65527	@ tmp130,
	cmp	r0, r3	@ mibspi, tmp130
	beq	.L51	@,
@ ../source/HL_mibspi.c:2517: 	                     (mibspi == mibspiREG2 ? mibspiRAM2 : 
	.loc 1 2517 0
	mov	r3, #62976	@ tmp131,
	movt	r3, 65527	@ tmp131,
	cmp	r0, r3	@ mibspi, tmp131
	beq	.L52	@,
@ ../source/HL_mibspi.c:2518: 						 (mibspi == mibspiREG3 ? mibspiRAM3 : 
	.loc 1 2518 0
	mov	r3, #63488	@ tmp132,
	movt	r3, 65527	@ tmp132,
	cmp	r0, r3	@ mibspi, tmp132
	beq	.L53	@,
@ ../source/HL_mibspi.c:2519: 						 (mibspi == mibspiREG4 ? mibspiRAM4 : mibspiRAM5)));
	.loc 1 2519 0
	mov	r3, #64000	@ tmp133,
	movt	r3, 65527	@ tmp133,
	cmp	r0, r3	@ mibspi, tmp133
	movne	lr, #0	@ iftmp.5_14,
	movtne	lr, 65290	@ iftmp.5_14,
	bne	.L44	@
.L57:
	mov	lr, #0	@ iftmp.5_14,
	movt	lr, 65286	@ iftmp.5_14,
	b	.L44	@
.L51:
@ ../source/HL_mibspi.c:2516:     mibspiRAM_t *ram    = mibspi == mibspiREG1 ? mibspiRAM1 : 
	.loc 1 2516 0
	mov	lr, #0	@ iftmp.5_14,
	movt	lr, 65294	@ iftmp.5_14,
.L44:
.LVL41:
@ ../source/HL_mibspi.c:2520:     uint32 start  = (mibspi->TGCTRL[group] >> 8U) & 0xFFU;
	.loc 1 2520 0
	add	r3, r1, #38	@ tmp134, group,
	ldr	ip, [r0, r3, lsl #2]	@ _1, mibspi_17(D)->TGCTRL
	ubfx	ip, ip, #8, #8	@ start, _1,,
.LVL42:
@ ../source/HL_mibspi.c:2521:     uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
	.loc 1 2521 0
	cmp	r1, #7	@ group,
	beq	.L58	@,
@ ../source/HL_mibspi.c:2521:     uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
	.loc 1 2521 0 is_stmt 0
	add	r1, r1, #39	@ tmp136, group,
.LVL43:
	ldr	r1, [r0, r1, lsl #2]	@ _7, mibspi_17(D)->TGCTRL
.LVL44:
	ubfx	r1, r1, #8, #8	@ end, _7,,
.L46:
.LVL45:
@ ../source/HL_mibspi.c:2524:     if (end == 0U) {end = 128U;}
	.loc 1 2524 0 is_stmt 1
	cmp	r1, #0	@ end,
	beq	.L55	@,
.LVL46:
.L47:
@ ../source/HL_mibspi.c:2524:     if (end == 0U) {end = 128U;}
	.loc 1 2524 0 is_stmt 0
	mov	r0, #0	@ mibspiFlags,
.LVL47:
	b	.L49	@
.LVL48:
.L52:
@ ../source/HL_mibspi.c:2517: 	                     (mibspi == mibspiREG2 ? mibspiRAM2 : 
	.loc 1 2517 0 is_stmt 1
	mov	lr, #0	@ iftmp.5_14,
	movt	lr, 65288	@ iftmp.5_14,
	b	.L44	@
.L53:
@ ../source/HL_mibspi.c:2518: 						 (mibspi == mibspiREG3 ? mibspiRAM3 : 
	.loc 1 2518 0
	mov	lr, #0	@ iftmp.5_14,
	movt	lr, 65292	@ iftmp.5_14,
	b	.L44	@
.LVL49:
.L58:
@ ../source/HL_mibspi.c:2521:     uint32 end    = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU);
	.loc 1 2521 0
	ldr	r1, [r0, #148]	@ _3, mibspi_17(D)->LTGPEND
.LVL50:
	ubfx	r1, r1, #8, #7	@ _5, _3,,
	add	r1, r1, #1	@ end, _5,
	b	.L46	@
.LVL51:
.L50:
@ ../source/HL_mibspi.c:2528:         mibspiFlags  |= ram->rx[start].flags;
	.loc 1 2528 0
	add	r3, ip, #128	@ tmp137, start,
	lsl	r3, r3, #2	@ tmp138, tmp137,
	add	r4, lr, r3	@ tmp139, iftmp.5_14, tmp138
	ldrh	r3, [lr, r3]	@ iftmp.5_14->rx[start_12].flags, iftmp.5_14->rx[start_12].flags
	orr	r0, r3, r0	@ mibspiFlags, iftmp.5_14->rx[start_12].flags, mibspiFlags
.LVL52:
@ ../source/HL_mibspi.c:2530:         *data = ram->rx[start].data;
	.loc 1 2530 0
	ldrh	r3, [r4, #2]	@ iftmp.5_14->rx[start_12].data, iftmp.5_14->rx[start_12].data
	strh	r3, [r2], #2	@ movhi	@ iftmp.5_14->rx[start_12].data, *data_11
.LVL53:
@ ../source/HL_mibspi.c:2532:         start++;
	.loc 1 2532 0
	add	ip, ip, #1	@ start, start,
.LVL54:
.L49:
@ ../source/HL_mibspi.c:2526:     while (start < end)
	.loc 1 2526 0
	cmp	ip, r1	@ start, end
	bcc	.L50	@,
@ ../source/HL_mibspi.c:2535: 	ret = ((uint32)mibspiFlags >> 8U) & 0x5FU;
	.loc 1 2535 0
	lsr	r0, r0, #8	@ _10, mibspiFlags,
.LVL55:
@ ../source/HL_mibspi.c:2540: }
	.loc 1 2540 0
	and	r0, r0, #95	@, _10,
.LVL56:
	pop	{r4, pc}	@
.LVL57:
.L55:
@ ../source/HL_mibspi.c:2524:     if (end == 0U) {end = 128U;}
	.loc 1 2524 0
	mov	r1, #128	@ end,
.LVL58:
	b	.L47	@
	.cfi_endproc
.LFE6:
	.size	mibspiGetData, .-mibspiGetData
	.align	2
	.global	mibspiTransfer
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiTransfer, %function
mibspiTransfer:
.LFB7:
	.loc 1 2554 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL59:
@ ../source/HL_mibspi.c:2558:     mibspi->TGCTRL[group] |= 0x80000000U;
	.loc 1 2558 0
	add	r1, r1, #38	@ tmp114, group,
.LVL60:
	ldr	r3, [r0, r1, lsl #2]	@ _1, mibspi_4(D)->TGCTRL
	orr	r3, r3, #-2147483648	@ _2, _1,
	str	r3, [r0, r1, lsl #2]	@ _2, mibspi_4(D)->TGCTRL
@ ../source/HL_mibspi.c:2562: }
	.loc 1 2562 0
	bx	lr	@
	.cfi_endproc
.LFE7:
	.size	mibspiTransfer, .-mibspiTransfer
	.align	2
	.global	mibspiIsTransferComplete
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiIsTransferComplete, %function
mibspiIsTransferComplete:
.LFB8:
	.loc 1 2579 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL61:
@ ../source/HL_mibspi.c:2585:     if(((((mibspi->TGINTFLG & 0xFFFF0000U) >> 16U)>> group) & 1U) == 1U)
	.loc 1 2585 0
	ldr	r3, [r0, #132]	@ _1, mibspi_13(D)->TGINTFLG
	lsr	r3, r3, #16	@ _2, _1,
	lsr	r3, r3, r1	@ _3, _2, group
	tst	r3, #1	@ _3,
	beq	.L62	@,
@ ../source/HL_mibspi.c:2587:        mibspi->TGINTFLG = (mibspi->TGINTFLG & 0x0000FFFFU) | ((uint32)((uint32)1U << group) << 16U);
	.loc 1 2587 0
	ldr	r2, [r0, #132]	@ _5, mibspi_13(D)->TGINTFLG
	uxth	r2, r2	@ _6, _5
	mov	r3, #1	@ tmp122,
	lsl	r1, r3, r1	@ _7, tmp122, group
.LVL62:
	orr	r1, r2, r1, lsl #16	@ _9, _6, _7,
	str	r1, [r0, #132]	@ _9, mibspi_13(D)->TGINTFLG
.LVL63:
@ ../source/HL_mibspi.c:2588:        status = TRUE;
	.loc 1 2588 0
	mov	r0, r3	@ <retval>, tmp122
.LVL64:
	bx	lr	@
.LVL65:
.L62:
@ ../source/HL_mibspi.c:2592:        status = FALSE;
	.loc 1 2592 0
	mov	r0, #0	@ <retval>,
.LVL66:
@ ../source/HL_mibspi.c:2599: }
	.loc 1 2599 0
	bx	lr	@
	.cfi_endproc
.LFE8:
	.size	mibspiIsTransferComplete, .-mibspiIsTransferComplete
	.align	2
	.global	mibspiEnableLoopback
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiEnableLoopback, %function
mibspiEnableLoopback:
.LFB9:
	.loc 1 2613 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL67:
@ ../source/HL_mibspi.c:2618:     mibspi->IOLPKTSTCR = 0U;
	.loc 1 2618 0
	mov	r3, #0	@ tmp115,
	str	r3, [r0, #308]	@ tmp115, mibspi_5(D)->IOLPKTSTCR
@ ../source/HL_mibspi.c:2622:                        | (uint32)((uint32)Loopbacktype << 1U);
	.loc 1 2622 0
	lsl	r1, r1, #1	@ _2, Loopbacktype,
.LVL68:
	orr	r1, r1, #2560	@ _3, _2,
@ ../source/HL_mibspi.c:2621:     mibspi->IOLPKTSTCR = (uint32)0x00000A00U
	.loc 1 2621 0
	str	r1, [r0, #308]	@ _3, mibspi_5(D)->IOLPKTSTCR
@ ../source/HL_mibspi.c:2626: }
	.loc 1 2626 0
	bx	lr	@
	.cfi_endproc
.LFE9:
	.size	mibspiEnableLoopback, .-mibspiEnableLoopback
	.align	2
	.global	mibspiDisableLoopback
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiDisableLoopback, %function
mibspiDisableLoopback:
.LFB10:
	.loc 1 2638 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL69:
@ ../source/HL_mibspi.c:2643:     mibspi->IOLPKTSTCR = 0x00000500U;
	.loc 1 2643 0
	mov	r3, #1280	@ tmp111,
	str	r3, [r0, #308]	@ tmp111, mibspi_2(D)->IOLPKTSTCR
@ ../source/HL_mibspi.c:2647: }
	.loc 1 2647 0
	bx	lr	@
	.cfi_endproc
.LFE10:
	.size	mibspiDisableLoopback, .-mibspiDisableLoopback
	.align	2
	.global	mibspiPmodeSet
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiPmodeSet, %function
mibspiPmodeSet:
.LFB11:
	.loc 1 2669 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL70:
@ ../source/HL_mibspi.c:2672:     pmctrl_reg     = (mibspi->PMCTRL & (~(uint32)((uint32)0xFFU << (8U * DFMT))));
	.loc 1 2672 0
	ldr	r3, [r0, #108]	@ _1, mibspi_10(D)->PMCTRL
	lsl	r2, r2, #3	@ _3, DFMT,
.LVL71:
	mov	ip, #255	@ tmp122,
	bic	r3, r3, ip, lsl r2	@ pmctrl_reg, _1, tmp122,
.LVL72:
@ ../source/HL_mibspi.c:2673:     mibspi->PMCTRL = (pmctrl_reg | (uint32)((uint32)Pmode <<  ((8U * DFMT))));
	.loc 1 2673 0
	orr	r3, r3, r1, lsl r2	@ _8, pmctrl_reg, Pmode,
.LVL73:
	str	r3, [r0, #108]	@ _8, mibspi_10(D)->PMCTRL
@ ../source/HL_mibspi.c:2675: }
	.loc 1 2675 0
	bx	lr	@
	.cfi_endproc
.LFE11:
	.size	mibspiPmodeSet, .-mibspiPmodeSet
	.align	2
	.global	mibspiEnableGroupNotification
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiEnableGroupNotification, %function
mibspiEnableGroupNotification:
.LFB12:
	.loc 1 2689 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL74:
@ ../source/HL_mibspi.c:2693:     if (level != 0U)
	.loc 1 2693 0
	cmp	r2, #0	@ level,
	bne	.L69	@,
@ ../source/HL_mibspi.c:2699:         mibspi->TGITLVCR = (mibspi->TGITLVCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
	.loc 1 2699 0
	ldr	r3, [r0, #128]	@ _6, mibspi_19(D)->TGITLVCR
	uxth	r3, r3	@ _7, _6
	mov	r2, #1	@ tmp129,
.LVL75:
	lsl	r2, r2, r1	@ _8, tmp129, group
	orr	r3, r3, r2, lsl #16	@ _10, _7, _8,
	str	r3, [r0, #128]	@ _10, mibspi_19(D)->TGITLVCR
.L68:
@ ../source/HL_mibspi.c:2701:     mibspi->TGITENST = (mibspi->TGITENST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
	.loc 1 2701 0
	ldr	r3, [r0, #116]	@ _11, mibspi_19(D)->TGITENST
	uxth	r3, r3	@ _12, _11
	mov	r2, #1	@ tmp130,
	lsl	r1, r2, r1	@ _13, tmp130, group
.LVL76:
	orr	r1, r3, r1, lsl #16	@ _15, _12, _13,
	str	r1, [r0, #116]	@ _15, mibspi_19(D)->TGITENST
@ ../source/HL_mibspi.c:2705: }
	.loc 1 2705 0
	bx	lr	@
.LVL77:
.L69:
@ ../source/HL_mibspi.c:2695:         mibspi->TGITLVST = (mibspi->TGITLVST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
	.loc 1 2695 0
	ldr	r3, [r0, #124]	@ _1, mibspi_19(D)->TGITLVST
	uxth	r3, r3	@ _2, _1
	mov	r2, #1	@ tmp128,
.LVL78:
	lsl	r2, r2, r1	@ _3, tmp128, group
	orr	r3, r3, r2, lsl #16	@ _5, _2, _3,
	str	r3, [r0, #124]	@ _5, mibspi_19(D)->TGITLVST
	b	.L68	@
	.cfi_endproc
.LFE12:
	.size	mibspiEnableGroupNotification, .-mibspiEnableGroupNotification
	.align	2
	.global	mibspiDisableGroupNotification
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspiDisableGroupNotification, %function
mibspiDisableGroupNotification:
.LFB13:
	.loc 1 2718 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL79:
@ ../source/HL_mibspi.c:2722:     mibspi->TGITENCR = (mibspi->TGITENCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U);
	.loc 1 2722 0
	ldr	r3, [r0, #120]	@ _1, mibspi_7(D)->TGITENCR
	uxth	r3, r3	@ _2, _1
	mov	r2, #1	@ tmp117,
	lsl	r1, r2, r1	@ _3, tmp117, group
.LVL80:
	orr	r3, r3, r1, lsl #16	@ _5, _2, _3,
	str	r3, [r0, #120]	@ _5, mibspi_7(D)->TGITENCR
@ ../source/HL_mibspi.c:2726: }
	.loc 1 2726 0
	bx	lr	@
	.cfi_endproc
.LFE13:
	.size	mibspiDisableGroupNotification, .-mibspiDisableGroupNotification
	.align	2
	.global	mibspi1GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspi1GetConfigValue, %function
mibspi1GetConfigValue:
.LFB14:
	.loc 1 2747 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL81:
@ ../source/HL_mibspi.c:2748:     if (type == InitialValue)
	.loc 1 2748 0
	cmp	r1, #0	@ type,
	beq	.L74	@,
@ ../source/HL_mibspi.c:2778:         config_reg->CONFIG_GCR1       = mibspiREG1->GCR1;
	.loc 1 2778 0
	movw	r3, #62719	@ tmp160,
	movt	r3, 65527	@ tmp160,
	ldr	r2, [r3, #-251]	@ _1, MEM[(volatile struct mibspiBASE_t *)4294439936B].GCR1
	str	r2, [r0]	@ _1, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2779:         config_reg->CONFIG_INT0       = mibspiREG1->INT0;
	.loc 1 2779 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct mibspiBASE_t *)4294439936B].INT0
	str	r2, [r0, #4]	@ _2, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2780:         config_reg->CONFIG_LVL        = mibspiREG1->LVL;
	.loc 1 2780 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct mibspiBASE_t *)4294439936B].LVL
	str	r2, [r0, #8]	@ _3, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2781:         config_reg->CONFIG_PCFUN      = mibspiREG1->PC0;
	.loc 1 2781 0
	ldr	r2, [r3, #-235]	@ _4, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC0
	str	r2, [r0, #12]	@ _4, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2782:         config_reg->CONFIG_PCDIR      = mibspiREG1->PC1;
	.loc 1 2782 0
	ldr	r2, [r3, #-231]	@ _5, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC1
	str	r2, [r0, #16]	@ _5, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2783:         config_reg->CONFIG_PCPDR      = mibspiREG1->PC6;
	.loc 1 2783 0
	ldr	r2, [r3, #-211]	@ _6, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC6
	str	r2, [r0, #20]	@ _6, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2784:         config_reg->CONFIG_PCDIS      = mibspiREG1->PC7;
	.loc 1 2784 0
	ldr	r2, [r3, #-207]	@ _7, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC7
	str	r2, [r0, #24]	@ _7, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2785:         config_reg->CONFIG_PCPSL      = mibspiREG1->PC8;
	.loc 1 2785 0
	ldr	r2, [r3, #-203]	@ _8, MEM[(volatile struct mibspiBASE_t *)4294439936B].PC8
	str	r2, [r0, #28]	@ _8, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2786:         config_reg->CONFIG_DELAY      = mibspiREG1->DELAY;
	.loc 1 2786 0
	ldr	r2, [r3, #-183]	@ _9, MEM[(volatile struct mibspiBASE_t *)4294439936B].DELAY
	str	r2, [r0, #32]	@ _9, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2787:         config_reg->CONFIG_FMT0       = mibspiREG1->FMT0;
	.loc 1 2787 0
	ldr	r2, [r3, #-175]	@ _10, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT0
	str	r2, [r0, #36]	@ _10, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2788:         config_reg->CONFIG_FMT1       = mibspiREG1->FMT1;
	.loc 1 2788 0
	ldr	r2, [r3, #-171]	@ _11, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT1
	str	r2, [r0, #40]	@ _11, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2789:         config_reg->CONFIG_FMT2       = mibspiREG1->FMT2;
	.loc 1 2789 0
	ldr	r2, [r3, #-167]	@ _12, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT2
	str	r2, [r0, #44]	@ _12, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2790:         config_reg->CONFIG_FMT3       = mibspiREG1->FMT3;
	.loc 1 2790 0
	ldr	r2, [r3, #-163]	@ _13, MEM[(volatile struct mibspiBASE_t *)4294439936B].FMT3
	str	r2, [r0, #48]	@ _13, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2791:         config_reg->CONFIG_MIBSPIE    = mibspiREG1->MIBSPIE;
	.loc 1 2791 0
	ldr	r2, [r3, #-143]	@ _14, MEM[(volatile struct mibspiBASE_t *)4294439936B].MIBSPIE
	str	r2, [r0, #52]	@ _14, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2792:         config_reg->CONFIG_LTGPEND    = mibspiREG1->LTGPEND;
	.loc 1 2792 0
	ldr	r2, [r3, #-107]	@ _15, MEM[(volatile struct mibspiBASE_t *)4294439936B].LTGPEND
	str	r2, [r0, #56]	@ _15, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2793:         config_reg->CONFIG_TGCTRL[0U] = mibspiREG1->TGCTRL[0U];
	.loc 1 2793 0
	ldr	r2, [r3, #-103]	@ _16, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #60]	@ _16, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2794:         config_reg->CONFIG_TGCTRL[1U] = mibspiREG1->TGCTRL[1U];
	.loc 1 2794 0
	ldr	r2, [r3, #-99]	@ _17, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #64]	@ _17, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2795:         config_reg->CONFIG_TGCTRL[2U] = mibspiREG1->TGCTRL[2U];
	.loc 1 2795 0
	ldr	r2, [r3, #-95]	@ _18, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #68]	@ _18, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2796:         config_reg->CONFIG_TGCTRL[3U] = mibspiREG1->TGCTRL[3U];
	.loc 1 2796 0
	ldr	r2, [r3, #-91]	@ _19, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #72]	@ _19, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2797:         config_reg->CONFIG_TGCTRL[4U] = mibspiREG1->TGCTRL[4U];
	.loc 1 2797 0
	ldr	r2, [r3, #-87]	@ _20, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #76]	@ _20, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2798:         config_reg->CONFIG_TGCTRL[5U] = mibspiREG1->TGCTRL[5U];
	.loc 1 2798 0
	ldr	r2, [r3, #-83]	@ _21, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #80]	@ _21, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2799:         config_reg->CONFIG_TGCTRL[6U] = mibspiREG1->TGCTRL[6U];
	.loc 1 2799 0
	ldr	r2, [r3, #-79]	@ _22, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #84]	@ _22, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2800:         config_reg->CONFIG_TGCTRL[7U] = mibspiREG1->TGCTRL[7U];
	.loc 1 2800 0
	ldr	r2, [r3, #-75]	@ _23, MEM[(volatile struct mibspiBASE_t *)4294439936B].TGCTRL
	str	r2, [r0, #88]	@ _23, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2801:         config_reg->CONFIG_PAR_ECC_CTRL   = mibspiREG1->PAR_ECC_CTRL;
	.loc 1 2801 0
	ldr	r3, [r3, #33]	@ _24, MEM[(volatile struct mibspiBASE_t *)4294439936B].PAR_ECC_CTRL
	str	r3, [r0, #92]	@ _24, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
@ ../source/HL_mibspi.c:2803: }
	.loc 1 2803 0
	bx	lr	@
.L74:
@ ../source/HL_mibspi.c:2750:         config_reg->CONFIG_GCR1       = MIBSPI1_GCR1_CONFIGVALUE; 
	.loc 1 2750 0
	mov	r3, #3	@ tmp136,
	movt	r3, 256	@ tmp136,
	str	r3, [r0]	@ tmp136, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2751:         config_reg->CONFIG_INT0       = MIBSPI1_INT0_CONFIGVALUE; 
	.loc 1 2751 0
	mov	r3, #0	@ tmp137,
	str	r3, [r0, #4]	@ tmp137, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2752:         config_reg->CONFIG_LVL        = MIBSPI1_LVL_CONFIGVALUE; 
	.loc 1 2752 0
	str	r3, [r0, #8]	@ tmp137, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2753:         config_reg->CONFIG_PCFUN      = MIBSPI1_PCFUN_CONFIGVALUE; 
	.loc 1 2753 0
	movw	r2, #3841	@ tmp139,
	movt	r2, 771	@ tmp139,
	str	r2, [r0, #12]	@ tmp139, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2754:         config_reg->CONFIG_PCDIR      = MIBSPI1_PCDIR_CONFIGVALUE; 
	.loc 1 2754 0
	movw	r2, #1599	@ tmp140,
	movt	r2, 1	@ tmp140,
	str	r2, [r0, #16]	@ tmp140, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2755:         config_reg->CONFIG_PCPDR      = MIBSPI1_PCPDR_CONFIGVALUE; 
	.loc 1 2755 0
	str	r3, [r0, #20]	@ tmp137, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2756:         config_reg->CONFIG_PCDIS      = MIBSPI1_PCDIS_CONFIGVALUE; 
	.loc 1 2756 0
	str	r3, [r0, #24]	@ tmp137, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2757:         config_reg->CONFIG_PCPSL      = MIBSPI1_PCPSL_CONFIGVALUE; 
	.loc 1 2757 0
	movw	r2, #3903	@ tmp143,
	movt	r2, 771	@ tmp143,
	str	r2, [r0, #28]	@ tmp143, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2758:         config_reg->CONFIG_DELAY      = MIBSPI1_DELAY_CONFIGVALUE; 
	.loc 1 2758 0
	str	r3, [r0, #32]	@ tmp137, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2759:         config_reg->CONFIG_FMT0       = MIBSPI1_FMT0_CONFIGVALUE; 
	.loc 1 2759 0
	movw	r2, #18960	@ tmp145,
	str	r2, [r0, #36]	@ tmp145, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2760:         config_reg->CONFIG_FMT1       = MIBSPI1_FMT1_CONFIGVALUE; 
	.loc 1 2760 0
	str	r2, [r0, #40]	@ tmp145, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2761:         config_reg->CONFIG_FMT2       = MIBSPI1_FMT2_CONFIGVALUE; 
	.loc 1 2761 0
	str	r2, [r0, #44]	@ tmp145, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2762:         config_reg->CONFIG_FMT3       = MIBSPI1_FMT3_CONFIGVALUE; 
	.loc 1 2762 0
	str	r2, [r0, #48]	@ tmp145, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2763:         config_reg->CONFIG_MIBSPIE    = MIBSPI1_MIBSPIE_CONFIGVALUE; 
	.loc 1 2763 0
	movw	r2, #1281	@ tmp149,
	str	r2, [r0, #52]	@ tmp149, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2764:         config_reg->CONFIG_LTGPEND    = MIBSPI1_LTGPEND_CONFIGVALUE; 
	.loc 1 2764 0
	mov	r2, #1792	@ tmp150,
	str	r2, [r0, #56]	@ tmp150, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2765:         config_reg->CONFIG_TGCTRL[0U] = MIBSPI1_TGCTRL0_CONFIGVALUE;
	.loc 1 2765 0
	movt	r3, 16496	@ tmp151,
	str	r3, [r0, #60]	@ tmp151, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2766:         config_reg->CONFIG_TGCTRL[1U] = MIBSPI1_TGCTRL1_CONFIGVALUE;
	.loc 1 2766 0
	mov	r3, #2048	@ tmp152,
	movt	r3, 16496	@ tmp152,
	str	r3, [r0, #64]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2767:         config_reg->CONFIG_TGCTRL[2U] = MIBSPI1_TGCTRL2_CONFIGVALUE;
	.loc 1 2767 0
	str	r3, [r0, #68]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2768:         config_reg->CONFIG_TGCTRL[3U] = MIBSPI1_TGCTRL3_CONFIGVALUE;
	.loc 1 2768 0
	str	r3, [r0, #72]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2769:         config_reg->CONFIG_TGCTRL[4U] = MIBSPI1_TGCTRL4_CONFIGVALUE;
	.loc 1 2769 0
	str	r3, [r0, #76]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2770:         config_reg->CONFIG_TGCTRL[5U] = MIBSPI1_TGCTRL5_CONFIGVALUE;
	.loc 1 2770 0
	str	r3, [r0, #80]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2771:         config_reg->CONFIG_TGCTRL[6U] = MIBSPI1_TGCTRL6_CONFIGVALUE;
	.loc 1 2771 0
	str	r3, [r0, #84]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2772:         config_reg->CONFIG_TGCTRL[7U] = MIBSPI1_TGCTRL7_CONFIGVALUE;
	.loc 1 2772 0
	str	r3, [r0, #88]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2773:         config_reg->CONFIG_PAR_ECC_CTRL   = MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE; 
	.loc 1 2773 0
	mov	r3, #5	@ tmp159,
	movt	r3, 1290	@ tmp159,
	str	r3, [r0, #92]	@ tmp159, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
	bx	lr	@
	.cfi_endproc
.LFE14:
	.size	mibspi1GetConfigValue, .-mibspi1GetConfigValue
	.align	2
	.global	mibspi2GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspi2GetConfigValue, %function
mibspi2GetConfigValue:
.LFB15:
	.loc 1 2824 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL82:
@ ../source/HL_mibspi.c:2825:     if (type == InitialValue)
	.loc 1 2825 0
	cmp	r1, #0	@ type,
	beq	.L78	@,
@ ../source/HL_mibspi.c:2855:         config_reg->CONFIG_GCR1       = mibspiREG2->GCR1;
	.loc 1 2855 0
	movw	r3, #63231	@ tmp160,
	movt	r3, 65527	@ tmp160,
	ldr	r2, [r3, #-251]	@ _1, MEM[(volatile struct mibspiBASE_t *)4294440448B].GCR1
	str	r2, [r0]	@ _1, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2856:         config_reg->CONFIG_INT0       = mibspiREG2->INT0;
	.loc 1 2856 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct mibspiBASE_t *)4294440448B].INT0
	str	r2, [r0, #4]	@ _2, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2857:         config_reg->CONFIG_LVL        = mibspiREG2->LVL;
	.loc 1 2857 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct mibspiBASE_t *)4294440448B].LVL
	str	r2, [r0, #8]	@ _3, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2858:         config_reg->CONFIG_PCFUN      = mibspiREG2->PC0;
	.loc 1 2858 0
	ldr	r2, [r3, #-235]	@ _4, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC0
	str	r2, [r0, #12]	@ _4, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2859:         config_reg->CONFIG_PCDIR      = mibspiREG2->PC1;
	.loc 1 2859 0
	ldr	r2, [r3, #-231]	@ _5, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC1
	str	r2, [r0, #16]	@ _5, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2860:         config_reg->CONFIG_PCPDR      = mibspiREG2->PC6;
	.loc 1 2860 0
	ldr	r2, [r3, #-211]	@ _6, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC6
	str	r2, [r0, #20]	@ _6, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2861:         config_reg->CONFIG_PCDIS      = mibspiREG2->PC7;
	.loc 1 2861 0
	ldr	r2, [r3, #-207]	@ _7, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC7
	str	r2, [r0, #24]	@ _7, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2862:         config_reg->CONFIG_PCPSL      = mibspiREG2->PC8;
	.loc 1 2862 0
	ldr	r2, [r3, #-203]	@ _8, MEM[(volatile struct mibspiBASE_t *)4294440448B].PC8
	str	r2, [r0, #28]	@ _8, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2863:         config_reg->CONFIG_DELAY      = mibspiREG2->DELAY;
	.loc 1 2863 0
	ldr	r2, [r3, #-183]	@ _9, MEM[(volatile struct mibspiBASE_t *)4294440448B].DELAY
	str	r2, [r0, #32]	@ _9, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2864:         config_reg->CONFIG_FMT0       = mibspiREG2->FMT0;
	.loc 1 2864 0
	ldr	r2, [r3, #-175]	@ _10, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT0
	str	r2, [r0, #36]	@ _10, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2865:         config_reg->CONFIG_FMT1       = mibspiREG2->FMT1;
	.loc 1 2865 0
	ldr	r2, [r3, #-171]	@ _11, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT1
	str	r2, [r0, #40]	@ _11, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2866:         config_reg->CONFIG_FMT2       = mibspiREG2->FMT2;
	.loc 1 2866 0
	ldr	r2, [r3, #-167]	@ _12, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT2
	str	r2, [r0, #44]	@ _12, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2867:         config_reg->CONFIG_FMT3       = mibspiREG2->FMT3;
	.loc 1 2867 0
	ldr	r2, [r3, #-163]	@ _13, MEM[(volatile struct mibspiBASE_t *)4294440448B].FMT3
	str	r2, [r0, #48]	@ _13, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2868:         config_reg->CONFIG_MIBSPIE    = mibspiREG2->MIBSPIE;
	.loc 1 2868 0
	ldr	r2, [r3, #-143]	@ _14, MEM[(volatile struct mibspiBASE_t *)4294440448B].MIBSPIE
	str	r2, [r0, #52]	@ _14, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2869:         config_reg->CONFIG_LTGPEND    = mibspiREG2->LTGPEND;
	.loc 1 2869 0
	ldr	r2, [r3, #-107]	@ _15, MEM[(volatile struct mibspiBASE_t *)4294440448B].LTGPEND
	str	r2, [r0, #56]	@ _15, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2870:         config_reg->CONFIG_TGCTRL[0U] = mibspiREG2->TGCTRL[0U];
	.loc 1 2870 0
	ldr	r2, [r3, #-103]	@ _16, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #60]	@ _16, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2871:         config_reg->CONFIG_TGCTRL[1U] = mibspiREG2->TGCTRL[1U];
	.loc 1 2871 0
	ldr	r2, [r3, #-99]	@ _17, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #64]	@ _17, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2872:         config_reg->CONFIG_TGCTRL[2U] = mibspiREG2->TGCTRL[2U];
	.loc 1 2872 0
	ldr	r2, [r3, #-95]	@ _18, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #68]	@ _18, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2873:         config_reg->CONFIG_TGCTRL[3U] = mibspiREG2->TGCTRL[3U];
	.loc 1 2873 0
	ldr	r2, [r3, #-91]	@ _19, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #72]	@ _19, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2874:         config_reg->CONFIG_TGCTRL[4U] = mibspiREG2->TGCTRL[4U];
	.loc 1 2874 0
	ldr	r2, [r3, #-87]	@ _20, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #76]	@ _20, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2875:         config_reg->CONFIG_TGCTRL[5U] = mibspiREG2->TGCTRL[5U];
	.loc 1 2875 0
	ldr	r2, [r3, #-83]	@ _21, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #80]	@ _21, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2876:         config_reg->CONFIG_TGCTRL[6U] = mibspiREG2->TGCTRL[6U];
	.loc 1 2876 0
	ldr	r2, [r3, #-79]	@ _22, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #84]	@ _22, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2877:         config_reg->CONFIG_TGCTRL[7U] = mibspiREG2->TGCTRL[7U];
	.loc 1 2877 0
	ldr	r2, [r3, #-75]	@ _23, MEM[(volatile struct mibspiBASE_t *)4294440448B].TGCTRL
	str	r2, [r0, #88]	@ _23, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2878:         config_reg->CONFIG_PAR_ECC_CTRL   = mibspiREG2->PAR_ECC_CTRL;
	.loc 1 2878 0
	ldr	r3, [r3, #33]	@ _24, MEM[(volatile struct mibspiBASE_t *)4294440448B].PAR_ECC_CTRL
	str	r3, [r0, #92]	@ _24, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
@ ../source/HL_mibspi.c:2880: }
	.loc 1 2880 0
	bx	lr	@
.L78:
@ ../source/HL_mibspi.c:2827:         config_reg->CONFIG_GCR1       = MIBSPI2_GCR1_CONFIGVALUE; 
	.loc 1 2827 0
	mov	r3, #3	@ tmp136,
	movt	r3, 256	@ tmp136,
	str	r3, [r0]	@ tmp136, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2828:         config_reg->CONFIG_INT0       = MIBSPI2_INT0_CONFIGVALUE; 
	.loc 1 2828 0
	mov	r3, #0	@ tmp137,
	str	r3, [r0, #4]	@ tmp137, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2829:         config_reg->CONFIG_LVL        = MIBSPI2_LVL_CONFIGVALUE; 
	.loc 1 2829 0
	str	r3, [r0, #8]	@ tmp137, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2830:         config_reg->CONFIG_PCFUN      = MIBSPI2_PCFUN_CONFIGVALUE; 
	.loc 1 2830 0
	movw	r2, #3841	@ tmp139,
	movt	r2, 257	@ tmp139,
	str	r2, [r0, #12]	@ tmp139, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2831:         config_reg->CONFIG_PCDIR      = MIBSPI2_PCDIR_CONFIGVALUE; 
	.loc 1 2831 0
	movw	r2, #1539	@ tmp140,
	movt	r2, 1	@ tmp140,
	str	r2, [r0, #16]	@ tmp140, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2832:         config_reg->CONFIG_PCPDR      = MIBSPI2_PCPDR_CONFIGVALUE; 
	.loc 1 2832 0
	str	r3, [r0, #20]	@ tmp137, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2833:         config_reg->CONFIG_PCDIS      = MIBSPI2_PCDIS_CONFIGVALUE; 
	.loc 1 2833 0
	str	r3, [r0, #24]	@ tmp137, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2834:         config_reg->CONFIG_PCPSL      = MIBSPI2_PCPSL_CONFIGVALUE; 
	.loc 1 2834 0
	movw	r2, #3843	@ tmp143,
	movt	r2, 257	@ tmp143,
	str	r2, [r0, #28]	@ tmp143, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2835:         config_reg->CONFIG_DELAY      = MIBSPI2_DELAY_CONFIGVALUE; 
	.loc 1 2835 0
	str	r3, [r0, #32]	@ tmp137, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2836:         config_reg->CONFIG_FMT0       = MIBSPI2_FMT0_CONFIGVALUE; 
	.loc 1 2836 0
	movw	r2, #18960	@ tmp145,
	str	r2, [r0, #36]	@ tmp145, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2837:         config_reg->CONFIG_FMT1       = MIBSPI2_FMT1_CONFIGVALUE; 
	.loc 1 2837 0
	str	r2, [r0, #40]	@ tmp145, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2838:         config_reg->CONFIG_FMT2       = MIBSPI2_FMT2_CONFIGVALUE; 
	.loc 1 2838 0
	str	r2, [r0, #44]	@ tmp145, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2839:         config_reg->CONFIG_FMT3       = MIBSPI2_FMT3_CONFIGVALUE; 
	.loc 1 2839 0
	str	r2, [r0, #48]	@ tmp145, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2840:         config_reg->CONFIG_MIBSPIE    = MIBSPI2_MIBSPIE_CONFIGVALUE; 
	.loc 1 2840 0
	movw	r2, #1281	@ tmp149,
	str	r2, [r0, #52]	@ tmp149, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2841:         config_reg->CONFIG_LTGPEND    = MIBSPI2_LTGPEND_CONFIGVALUE; 
	.loc 1 2841 0
	mov	r2, #1792	@ tmp150,
	str	r2, [r0, #56]	@ tmp150, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2842:         config_reg->CONFIG_TGCTRL[0U] = MIBSPI2_TGCTRL0_CONFIGVALUE;
	.loc 1 2842 0
	movt	r3, 16496	@ tmp151,
	str	r3, [r0, #60]	@ tmp151, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2843:         config_reg->CONFIG_TGCTRL[1U] = MIBSPI2_TGCTRL1_CONFIGVALUE;
	.loc 1 2843 0
	mov	r3, #2048	@ tmp152,
	movt	r3, 16496	@ tmp152,
	str	r3, [r0, #64]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2844:         config_reg->CONFIG_TGCTRL[2U] = MIBSPI2_TGCTRL2_CONFIGVALUE;
	.loc 1 2844 0
	str	r3, [r0, #68]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2845:         config_reg->CONFIG_TGCTRL[3U] = MIBSPI2_TGCTRL3_CONFIGVALUE;
	.loc 1 2845 0
	str	r3, [r0, #72]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2846:         config_reg->CONFIG_TGCTRL[4U] = MIBSPI2_TGCTRL4_CONFIGVALUE;
	.loc 1 2846 0
	str	r3, [r0, #76]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2847:         config_reg->CONFIG_TGCTRL[5U] = MIBSPI2_TGCTRL5_CONFIGVALUE;
	.loc 1 2847 0
	str	r3, [r0, #80]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2848:         config_reg->CONFIG_TGCTRL[6U] = MIBSPI2_TGCTRL6_CONFIGVALUE;
	.loc 1 2848 0
	str	r3, [r0, #84]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2849:         config_reg->CONFIG_TGCTRL[7U] = MIBSPI2_TGCTRL7_CONFIGVALUE;
	.loc 1 2849 0
	str	r3, [r0, #88]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2850:         config_reg->CONFIG_PAR_ECC_CTRL   = MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE; 
	.loc 1 2850 0
	mov	r3, #5	@ tmp159,
	movt	r3, 1290	@ tmp159,
	str	r3, [r0, #92]	@ tmp159, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
	bx	lr	@
	.cfi_endproc
.LFE15:
	.size	mibspi2GetConfigValue, .-mibspi2GetConfigValue
	.align	2
	.global	mibspi3GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspi3GetConfigValue, %function
mibspi3GetConfigValue:
.LFB16:
	.loc 1 2901 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL83:
@ ../source/HL_mibspi.c:2902:     if (type == InitialValue)
	.loc 1 2902 0
	cmp	r1, #0	@ type,
	beq	.L82	@,
@ ../source/HL_mibspi.c:2932:         config_reg->CONFIG_GCR1       = mibspiREG3->GCR1;
	.loc 1 2932 0
	movw	r3, #63743	@ tmp160,
	movt	r3, 65527	@ tmp160,
	ldr	r2, [r3, #-251]	@ _1, MEM[(volatile struct mibspiBASE_t *)4294440960B].GCR1
	str	r2, [r0]	@ _1, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2933:         config_reg->CONFIG_INT0       = mibspiREG3->INT0;
	.loc 1 2933 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct mibspiBASE_t *)4294440960B].INT0
	str	r2, [r0, #4]	@ _2, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2934:         config_reg->CONFIG_LVL        = mibspiREG3->LVL;
	.loc 1 2934 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct mibspiBASE_t *)4294440960B].LVL
	str	r2, [r0, #8]	@ _3, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2935:         config_reg->CONFIG_PCFUN      = mibspiREG3->PC0;
	.loc 1 2935 0
	ldr	r2, [r3, #-235]	@ _4, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC0
	str	r2, [r0, #12]	@ _4, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2936:         config_reg->CONFIG_PCDIR      = mibspiREG3->PC1;
	.loc 1 2936 0
	ldr	r2, [r3, #-231]	@ _5, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC1
	str	r2, [r0, #16]	@ _5, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2937:         config_reg->CONFIG_PCPDR      = mibspiREG3->PC6;
	.loc 1 2937 0
	ldr	r2, [r3, #-211]	@ _6, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC6
	str	r2, [r0, #20]	@ _6, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2938:         config_reg->CONFIG_PCDIS      = mibspiREG3->PC7;
	.loc 1 2938 0
	ldr	r2, [r3, #-207]	@ _7, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC7
	str	r2, [r0, #24]	@ _7, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2939:         config_reg->CONFIG_PCPSL      = mibspiREG3->PC8;
	.loc 1 2939 0
	ldr	r2, [r3, #-203]	@ _8, MEM[(volatile struct mibspiBASE_t *)4294440960B].PC8
	str	r2, [r0, #28]	@ _8, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2940:         config_reg->CONFIG_DELAY      = mibspiREG3->DELAY;
	.loc 1 2940 0
	ldr	r2, [r3, #-183]	@ _9, MEM[(volatile struct mibspiBASE_t *)4294440960B].DELAY
	str	r2, [r0, #32]	@ _9, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2941:         config_reg->CONFIG_FMT0       = mibspiREG3->FMT0;
	.loc 1 2941 0
	ldr	r2, [r3, #-175]	@ _10, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT0
	str	r2, [r0, #36]	@ _10, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2942:         config_reg->CONFIG_FMT1       = mibspiREG3->FMT1;
	.loc 1 2942 0
	ldr	r2, [r3, #-171]	@ _11, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT1
	str	r2, [r0, #40]	@ _11, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2943:         config_reg->CONFIG_FMT2       = mibspiREG3->FMT2;
	.loc 1 2943 0
	ldr	r2, [r3, #-167]	@ _12, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT2
	str	r2, [r0, #44]	@ _12, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2944:         config_reg->CONFIG_FMT3       = mibspiREG3->FMT3;
	.loc 1 2944 0
	ldr	r2, [r3, #-163]	@ _13, MEM[(volatile struct mibspiBASE_t *)4294440960B].FMT3
	str	r2, [r0, #48]	@ _13, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2945:         config_reg->CONFIG_MIBSPIE    = mibspiREG3->MIBSPIE;
	.loc 1 2945 0
	ldr	r2, [r3, #-143]	@ _14, MEM[(volatile struct mibspiBASE_t *)4294440960B].MIBSPIE
	str	r2, [r0, #52]	@ _14, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2946:         config_reg->CONFIG_LTGPEND    = mibspiREG3->LTGPEND;
	.loc 1 2946 0
	ldr	r2, [r3, #-107]	@ _15, MEM[(volatile struct mibspiBASE_t *)4294440960B].LTGPEND
	str	r2, [r0, #56]	@ _15, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2947:         config_reg->CONFIG_TGCTRL[0U] = mibspiREG3->TGCTRL[0U];
	.loc 1 2947 0
	ldr	r2, [r3, #-103]	@ _16, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #60]	@ _16, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2948:         config_reg->CONFIG_TGCTRL[1U] = mibspiREG3->TGCTRL[1U];
	.loc 1 2948 0
	ldr	r2, [r3, #-99]	@ _17, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #64]	@ _17, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2949:         config_reg->CONFIG_TGCTRL[2U] = mibspiREG3->TGCTRL[2U];
	.loc 1 2949 0
	ldr	r2, [r3, #-95]	@ _18, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #68]	@ _18, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2950:         config_reg->CONFIG_TGCTRL[3U] = mibspiREG3->TGCTRL[3U];
	.loc 1 2950 0
	ldr	r2, [r3, #-91]	@ _19, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #72]	@ _19, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2951:         config_reg->CONFIG_TGCTRL[4U] = mibspiREG3->TGCTRL[4U];
	.loc 1 2951 0
	ldr	r2, [r3, #-87]	@ _20, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #76]	@ _20, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2952:         config_reg->CONFIG_TGCTRL[5U] = mibspiREG3->TGCTRL[5U];
	.loc 1 2952 0
	ldr	r2, [r3, #-83]	@ _21, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #80]	@ _21, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2953:         config_reg->CONFIG_TGCTRL[6U] = mibspiREG3->TGCTRL[6U];
	.loc 1 2953 0
	ldr	r2, [r3, #-79]	@ _22, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #84]	@ _22, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2954:         config_reg->CONFIG_TGCTRL[7U] = mibspiREG3->TGCTRL[7U];
	.loc 1 2954 0
	ldr	r2, [r3, #-75]	@ _23, MEM[(volatile struct mibspiBASE_t *)4294440960B].TGCTRL
	str	r2, [r0, #88]	@ _23, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2955:         config_reg->CONFIG_PAR_ECC_CTRL   = mibspiREG3->PAR_ECC_CTRL;
	.loc 1 2955 0
	ldr	r3, [r3, #33]	@ _24, MEM[(volatile struct mibspiBASE_t *)4294440960B].PAR_ECC_CTRL
	str	r3, [r0, #92]	@ _24, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
@ ../source/HL_mibspi.c:2957: }
	.loc 1 2957 0
	bx	lr	@
.L82:
@ ../source/HL_mibspi.c:2904:         config_reg->CONFIG_GCR1       = MIBSPI3_GCR1_CONFIGVALUE; 
	.loc 1 2904 0
	mov	r3, #3	@ tmp136,
	movt	r3, 256	@ tmp136,
	str	r3, [r0]	@ tmp136, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2905:         config_reg->CONFIG_INT0       = MIBSPI3_INT0_CONFIGVALUE; 
	.loc 1 2905 0
	mov	r3, #0	@ tmp137,
	str	r3, [r0, #4]	@ tmp137, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2906:         config_reg->CONFIG_LVL        = MIBSPI3_LVL_CONFIGVALUE; 
	.loc 1 2906 0
	str	r3, [r0, #8]	@ tmp137, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2907:         config_reg->CONFIG_PCFUN      = MIBSPI3_PCFUN_CONFIGVALUE; 
	.loc 1 2907 0
	movw	r2, #3841	@ tmp139,
	movt	r2, 257	@ tmp139,
	str	r2, [r0, #12]	@ tmp139, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2908:         config_reg->CONFIG_PCDIR      = MIBSPI3_PCDIR_CONFIGVALUE; 
	.loc 1 2908 0
	movw	r2, #1599	@ tmp140,
	movt	r2, 1	@ tmp140,
	str	r2, [r0, #16]	@ tmp140, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2909:         config_reg->CONFIG_PCPDR      = MIBSPI3_PCPDR_CONFIGVALUE; 
	.loc 1 2909 0
	str	r3, [r0, #20]	@ tmp137, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2910:         config_reg->CONFIG_PCDIS      = MIBSPI3_PCDIS_CONFIGVALUE; 
	.loc 1 2910 0
	str	r3, [r0, #24]	@ tmp137, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2911:         config_reg->CONFIG_PCPSL      = MIBSPI3_PCPSL_CONFIGVALUE; 
	.loc 1 2911 0
	movw	r2, #3903	@ tmp143,
	movt	r2, 257	@ tmp143,
	str	r2, [r0, #28]	@ tmp143, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2912:         config_reg->CONFIG_DELAY      = MIBSPI3_DELAY_CONFIGVALUE; 
	.loc 1 2912 0
	str	r3, [r0, #32]	@ tmp137, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2913:         config_reg->CONFIG_FMT0       = MIBSPI3_FMT0_CONFIGVALUE; 
	.loc 1 2913 0
	movw	r2, #18960	@ tmp145,
	str	r2, [r0, #36]	@ tmp145, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2914:         config_reg->CONFIG_FMT1       = MIBSPI3_FMT1_CONFIGVALUE; 
	.loc 1 2914 0
	str	r2, [r0, #40]	@ tmp145, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2915:         config_reg->CONFIG_FMT2       = MIBSPI3_FMT2_CONFIGVALUE; 
	.loc 1 2915 0
	str	r2, [r0, #44]	@ tmp145, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2916:         config_reg->CONFIG_FMT3       = MIBSPI3_FMT3_CONFIGVALUE; 
	.loc 1 2916 0
	str	r2, [r0, #48]	@ tmp145, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2917:         config_reg->CONFIG_MIBSPIE    = MIBSPI3_MIBSPIE_CONFIGVALUE; 
	.loc 1 2917 0
	movw	r2, #1281	@ tmp149,
	str	r2, [r0, #52]	@ tmp149, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2918:         config_reg->CONFIG_LTGPEND    = MIBSPI3_LTGPEND_CONFIGVALUE; 
	.loc 1 2918 0
	mov	r2, #1792	@ tmp150,
	str	r2, [r0, #56]	@ tmp150, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2919:         config_reg->CONFIG_TGCTRL[0U] = MIBSPI3_TGCTRL0_CONFIGVALUE;
	.loc 1 2919 0
	movt	r3, 16496	@ tmp151,
	str	r3, [r0, #60]	@ tmp151, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2920:         config_reg->CONFIG_TGCTRL[1U] = MIBSPI3_TGCTRL1_CONFIGVALUE;
	.loc 1 2920 0
	mov	r3, #2048	@ tmp152,
	movt	r3, 16496	@ tmp152,
	str	r3, [r0, #64]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2921:         config_reg->CONFIG_TGCTRL[2U] = MIBSPI3_TGCTRL2_CONFIGVALUE;
	.loc 1 2921 0
	str	r3, [r0, #68]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2922:         config_reg->CONFIG_TGCTRL[3U] = MIBSPI3_TGCTRL3_CONFIGVALUE;
	.loc 1 2922 0
	str	r3, [r0, #72]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2923:         config_reg->CONFIG_TGCTRL[4U] = MIBSPI3_TGCTRL4_CONFIGVALUE;
	.loc 1 2923 0
	str	r3, [r0, #76]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2924:         config_reg->CONFIG_TGCTRL[5U] = MIBSPI3_TGCTRL5_CONFIGVALUE;
	.loc 1 2924 0
	str	r3, [r0, #80]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2925:         config_reg->CONFIG_TGCTRL[6U] = MIBSPI3_TGCTRL6_CONFIGVALUE;
	.loc 1 2925 0
	str	r3, [r0, #84]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2926:         config_reg->CONFIG_TGCTRL[7U] = MIBSPI3_TGCTRL7_CONFIGVALUE;
	.loc 1 2926 0
	str	r3, [r0, #88]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2927:         config_reg->CONFIG_PAR_ECC_CTRL   = MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE; 
	.loc 1 2927 0
	mov	r3, #5	@ tmp159,
	movt	r3, 1290	@ tmp159,
	str	r3, [r0, #92]	@ tmp159, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
	bx	lr	@
	.cfi_endproc
.LFE16:
	.size	mibspi3GetConfigValue, .-mibspi3GetConfigValue
	.align	2
	.global	mibspi4GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspi4GetConfigValue, %function
mibspi4GetConfigValue:
.LFB17:
	.loc 1 2978 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL84:
@ ../source/HL_mibspi.c:2979:     if (type == InitialValue)
	.loc 1 2979 0
	cmp	r1, #0	@ type,
	beq	.L86	@,
@ ../source/HL_mibspi.c:3009:         config_reg->CONFIG_GCR1       = mibspiREG4->GCR1;
	.loc 1 3009 0
	movw	r3, #64255	@ tmp160,
	movt	r3, 65527	@ tmp160,
	ldr	r2, [r3, #-251]	@ _1, MEM[(volatile struct mibspiBASE_t *)4294441472B].GCR1
	str	r2, [r0]	@ _1, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:3010:         config_reg->CONFIG_INT0       = mibspiREG4->INT0;
	.loc 1 3010 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct mibspiBASE_t *)4294441472B].INT0
	str	r2, [r0, #4]	@ _2, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:3011:         config_reg->CONFIG_LVL        = mibspiREG4->LVL;
	.loc 1 3011 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct mibspiBASE_t *)4294441472B].LVL
	str	r2, [r0, #8]	@ _3, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:3012:         config_reg->CONFIG_PCFUN      = mibspiREG4->PC0;
	.loc 1 3012 0
	ldr	r2, [r3, #-235]	@ _4, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC0
	str	r2, [r0, #12]	@ _4, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:3013:         config_reg->CONFIG_PCDIR      = mibspiREG4->PC1;
	.loc 1 3013 0
	ldr	r2, [r3, #-231]	@ _5, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC1
	str	r2, [r0, #16]	@ _5, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:3014:         config_reg->CONFIG_PCPDR      = mibspiREG4->PC6;
	.loc 1 3014 0
	ldr	r2, [r3, #-211]	@ _6, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC6
	str	r2, [r0, #20]	@ _6, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:3015:         config_reg->CONFIG_PCDIS      = mibspiREG4->PC7;
	.loc 1 3015 0
	ldr	r2, [r3, #-207]	@ _7, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC7
	str	r2, [r0, #24]	@ _7, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:3016:         config_reg->CONFIG_PCPSL      = mibspiREG4->PC8;
	.loc 1 3016 0
	ldr	r2, [r3, #-203]	@ _8, MEM[(volatile struct mibspiBASE_t *)4294441472B].PC8
	str	r2, [r0, #28]	@ _8, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:3017:         config_reg->CONFIG_DELAY      = mibspiREG4->DELAY;
	.loc 1 3017 0
	ldr	r2, [r3, #-183]	@ _9, MEM[(volatile struct mibspiBASE_t *)4294441472B].DELAY
	str	r2, [r0, #32]	@ _9, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:3018:         config_reg->CONFIG_FMT0       = mibspiREG4->FMT0;
	.loc 1 3018 0
	ldr	r2, [r3, #-175]	@ _10, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT0
	str	r2, [r0, #36]	@ _10, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:3019:         config_reg->CONFIG_FMT1       = mibspiREG4->FMT1;
	.loc 1 3019 0
	ldr	r2, [r3, #-171]	@ _11, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT1
	str	r2, [r0, #40]	@ _11, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:3020:         config_reg->CONFIG_FMT2       = mibspiREG4->FMT2;
	.loc 1 3020 0
	ldr	r2, [r3, #-167]	@ _12, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT2
	str	r2, [r0, #44]	@ _12, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:3021:         config_reg->CONFIG_FMT3       = mibspiREG4->FMT3;
	.loc 1 3021 0
	ldr	r2, [r3, #-163]	@ _13, MEM[(volatile struct mibspiBASE_t *)4294441472B].FMT3
	str	r2, [r0, #48]	@ _13, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:3022:         config_reg->CONFIG_MIBSPIE    = mibspiREG4->MIBSPIE;
	.loc 1 3022 0
	ldr	r2, [r3, #-143]	@ _14, MEM[(volatile struct mibspiBASE_t *)4294441472B].MIBSPIE
	str	r2, [r0, #52]	@ _14, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:3023:         config_reg->CONFIG_LTGPEND    = mibspiREG4->LTGPEND;
	.loc 1 3023 0
	ldr	r2, [r3, #-107]	@ _15, MEM[(volatile struct mibspiBASE_t *)4294441472B].LTGPEND
	str	r2, [r0, #56]	@ _15, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:3024:         config_reg->CONFIG_TGCTRL[0U] = mibspiREG4->TGCTRL[0U];
	.loc 1 3024 0
	ldr	r2, [r3, #-103]	@ _16, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #60]	@ _16, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3025:         config_reg->CONFIG_TGCTRL[1U] = mibspiREG4->TGCTRL[1U];
	.loc 1 3025 0
	ldr	r2, [r3, #-99]	@ _17, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #64]	@ _17, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3026:         config_reg->CONFIG_TGCTRL[2U] = mibspiREG4->TGCTRL[2U];
	.loc 1 3026 0
	ldr	r2, [r3, #-95]	@ _18, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #68]	@ _18, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3027:         config_reg->CONFIG_TGCTRL[3U] = mibspiREG4->TGCTRL[3U];
	.loc 1 3027 0
	ldr	r2, [r3, #-91]	@ _19, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #72]	@ _19, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3028:         config_reg->CONFIG_TGCTRL[4U] = mibspiREG4->TGCTRL[4U];
	.loc 1 3028 0
	ldr	r2, [r3, #-87]	@ _20, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #76]	@ _20, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3029:         config_reg->CONFIG_TGCTRL[5U] = mibspiREG4->TGCTRL[5U];
	.loc 1 3029 0
	ldr	r2, [r3, #-83]	@ _21, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #80]	@ _21, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3030:         config_reg->CONFIG_TGCTRL[6U] = mibspiREG4->TGCTRL[6U];
	.loc 1 3030 0
	ldr	r2, [r3, #-79]	@ _22, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #84]	@ _22, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3031:         config_reg->CONFIG_TGCTRL[7U] = mibspiREG4->TGCTRL[7U];
	.loc 1 3031 0
	ldr	r2, [r3, #-75]	@ _23, MEM[(volatile struct mibspiBASE_t *)4294441472B].TGCTRL
	str	r2, [r0, #88]	@ _23, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3032:         config_reg->CONFIG_PAR_ECC_CTRL   = mibspiREG4->PAR_ECC_CTRL;
	.loc 1 3032 0
	ldr	r3, [r3, #33]	@ _24, MEM[(volatile struct mibspiBASE_t *)4294441472B].PAR_ECC_CTRL
	str	r3, [r0, #92]	@ _24, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
@ ../source/HL_mibspi.c:3034: }
	.loc 1 3034 0
	bx	lr	@
.L86:
@ ../source/HL_mibspi.c:2981:         config_reg->CONFIG_GCR1       = MIBSPI4_GCR1_CONFIGVALUE; 
	.loc 1 2981 0
	mov	r3, #3	@ tmp136,
	movt	r3, 256	@ tmp136,
	str	r3, [r0]	@ tmp136, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:2982:         config_reg->CONFIG_INT0       = MIBSPI4_INT0_CONFIGVALUE; 
	.loc 1 2982 0
	mov	r3, #0	@ tmp137,
	str	r3, [r0, #4]	@ tmp137, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:2983:         config_reg->CONFIG_LVL        = MIBSPI4_LVL_CONFIGVALUE; 
	.loc 1 2983 0
	str	r3, [r0, #8]	@ tmp137, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:2984:         config_reg->CONFIG_PCFUN      = MIBSPI4_PCFUN_CONFIGVALUE; 
	.loc 1 2984 0
	movw	r2, #3841	@ tmp139,
	movt	r2, 257	@ tmp139,
	str	r2, [r0, #12]	@ tmp139, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:2985:         config_reg->CONFIG_PCDIR      = MIBSPI4_PCDIR_CONFIGVALUE; 
	.loc 1 2985 0
	movw	r2, #1599	@ tmp140,
	movt	r2, 1	@ tmp140,
	str	r2, [r0, #16]	@ tmp140, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:2986:         config_reg->CONFIG_PCPDR      = MIBSPI4_PCPDR_CONFIGVALUE; 
	.loc 1 2986 0
	str	r3, [r0, #20]	@ tmp137, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:2987:         config_reg->CONFIG_PCDIS      = MIBSPI4_PCDIS_CONFIGVALUE; 
	.loc 1 2987 0
	str	r3, [r0, #24]	@ tmp137, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:2988:         config_reg->CONFIG_PCPSL      = MIBSPI4_PCPSL_CONFIGVALUE; 
	.loc 1 2988 0
	movw	r2, #3903	@ tmp143,
	movt	r2, 257	@ tmp143,
	str	r2, [r0, #28]	@ tmp143, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:2989:         config_reg->CONFIG_DELAY      = MIBSPI4_DELAY_CONFIGVALUE; 
	.loc 1 2989 0
	str	r3, [r0, #32]	@ tmp137, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:2990:         config_reg->CONFIG_FMT0       = MIBSPI4_FMT0_CONFIGVALUE; 
	.loc 1 2990 0
	movw	r2, #18960	@ tmp145,
	str	r2, [r0, #36]	@ tmp145, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:2991:         config_reg->CONFIG_FMT1       = MIBSPI4_FMT1_CONFIGVALUE; 
	.loc 1 2991 0
	str	r2, [r0, #40]	@ tmp145, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:2992:         config_reg->CONFIG_FMT2       = MIBSPI4_FMT2_CONFIGVALUE; 
	.loc 1 2992 0
	str	r2, [r0, #44]	@ tmp145, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:2993:         config_reg->CONFIG_FMT3       = MIBSPI4_FMT3_CONFIGVALUE; 
	.loc 1 2993 0
	str	r2, [r0, #48]	@ tmp145, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:2994:         config_reg->CONFIG_MIBSPIE    = MIBSPI4_MIBSPIE_CONFIGVALUE; 
	.loc 1 2994 0
	movw	r2, #1281	@ tmp149,
	str	r2, [r0, #52]	@ tmp149, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:2995:         config_reg->CONFIG_LTGPEND    = MIBSPI4_LTGPEND_CONFIGVALUE; 
	.loc 1 2995 0
	mov	r2, #1792	@ tmp150,
	str	r2, [r0, #56]	@ tmp150, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:2996:         config_reg->CONFIG_TGCTRL[0U] = MIBSPI4_TGCTRL0_CONFIGVALUE;
	.loc 1 2996 0
	movt	r3, 16496	@ tmp151,
	str	r3, [r0, #60]	@ tmp151, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2997:         config_reg->CONFIG_TGCTRL[1U] = MIBSPI4_TGCTRL1_CONFIGVALUE;
	.loc 1 2997 0
	mov	r3, #2048	@ tmp152,
	movt	r3, 16496	@ tmp152,
	str	r3, [r0, #64]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2998:         config_reg->CONFIG_TGCTRL[2U] = MIBSPI4_TGCTRL2_CONFIGVALUE;
	.loc 1 2998 0
	str	r3, [r0, #68]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:2999:         config_reg->CONFIG_TGCTRL[3U] = MIBSPI4_TGCTRL3_CONFIGVALUE;
	.loc 1 2999 0
	str	r3, [r0, #72]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3000:         config_reg->CONFIG_TGCTRL[4U] = MIBSPI4_TGCTRL4_CONFIGVALUE;
	.loc 1 3000 0
	str	r3, [r0, #76]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3001:         config_reg->CONFIG_TGCTRL[5U] = MIBSPI4_TGCTRL5_CONFIGVALUE;
	.loc 1 3001 0
	str	r3, [r0, #80]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3002:         config_reg->CONFIG_TGCTRL[6U] = MIBSPI4_TGCTRL6_CONFIGVALUE;
	.loc 1 3002 0
	str	r3, [r0, #84]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3003:         config_reg->CONFIG_TGCTRL[7U] = MIBSPI4_TGCTRL7_CONFIGVALUE;
	.loc 1 3003 0
	str	r3, [r0, #88]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3004:         config_reg->CONFIG_PAR_ECC_CTRL   = MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE; 
	.loc 1 3004 0
	mov	r3, #5	@ tmp159,
	movt	r3, 1290	@ tmp159,
	str	r3, [r0, #92]	@ tmp159, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
	bx	lr	@
	.cfi_endproc
.LFE17:
	.size	mibspi4GetConfigValue, .-mibspi4GetConfigValue
	.align	2
	.global	mibspi5GetConfigValue
	.syntax unified
	.arm
	.fpu vfpv3-d16
	.type	mibspi5GetConfigValue, %function
mibspi5GetConfigValue:
.LFB18:
	.loc 1 3055 0
	.cfi_startproc
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
.LVL85:
@ ../source/HL_mibspi.c:3056:     if (type == InitialValue)
	.loc 1 3056 0
	cmp	r1, #0	@ type,
	beq	.L90	@,
@ ../source/HL_mibspi.c:3086:         config_reg->CONFIG_GCR1       = mibspiREG5->GCR1;
	.loc 1 3086 0
	movw	r3, #64767	@ tmp160,
	movt	r3, 65527	@ tmp160,
	ldr	r2, [r3, #-251]	@ _1, MEM[(volatile struct mibspiBASE_t *)4294441984B].GCR1
	str	r2, [r0]	@ _1, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:3087:         config_reg->CONFIG_INT0       = mibspiREG5->INT0;
	.loc 1 3087 0
	ldr	r2, [r3, #-247]	@ _2, MEM[(volatile struct mibspiBASE_t *)4294441984B].INT0
	str	r2, [r0, #4]	@ _2, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:3088:         config_reg->CONFIG_LVL        = mibspiREG5->LVL;
	.loc 1 3088 0
	ldr	r2, [r3, #-243]	@ _3, MEM[(volatile struct mibspiBASE_t *)4294441984B].LVL
	str	r2, [r0, #8]	@ _3, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:3089:         config_reg->CONFIG_PCFUN      = mibspiREG5->PC0;
	.loc 1 3089 0
	ldr	r2, [r3, #-235]	@ _4, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC0
	str	r2, [r0, #12]	@ _4, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:3090:         config_reg->CONFIG_PCDIR      = mibspiREG5->PC1;
	.loc 1 3090 0
	ldr	r2, [r3, #-231]	@ _5, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC1
	str	r2, [r0, #16]	@ _5, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:3091:         config_reg->CONFIG_PCPDR      = mibspiREG5->PC6;
	.loc 1 3091 0
	ldr	r2, [r3, #-211]	@ _6, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC6
	str	r2, [r0, #20]	@ _6, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:3092:         config_reg->CONFIG_PCDIS      = mibspiREG5->PC7;
	.loc 1 3092 0
	ldr	r2, [r3, #-207]	@ _7, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC7
	str	r2, [r0, #24]	@ _7, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:3093:         config_reg->CONFIG_PCPSL      = mibspiREG5->PC8;
	.loc 1 3093 0
	ldr	r2, [r3, #-203]	@ _8, MEM[(volatile struct mibspiBASE_t *)4294441984B].PC8
	str	r2, [r0, #28]	@ _8, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:3094:         config_reg->CONFIG_DELAY      = mibspiREG5->DELAY;
	.loc 1 3094 0
	ldr	r2, [r3, #-183]	@ _9, MEM[(volatile struct mibspiBASE_t *)4294441984B].DELAY
	str	r2, [r0, #32]	@ _9, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:3095:         config_reg->CONFIG_FMT0       = mibspiREG5->FMT0;
	.loc 1 3095 0
	ldr	r2, [r3, #-175]	@ _10, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT0
	str	r2, [r0, #36]	@ _10, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:3096:         config_reg->CONFIG_FMT1       = mibspiREG5->FMT1;
	.loc 1 3096 0
	ldr	r2, [r3, #-171]	@ _11, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT1
	str	r2, [r0, #40]	@ _11, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:3097:         config_reg->CONFIG_FMT2       = mibspiREG5->FMT2;
	.loc 1 3097 0
	ldr	r2, [r3, #-167]	@ _12, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT2
	str	r2, [r0, #44]	@ _12, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:3098:         config_reg->CONFIG_FMT3       = mibspiREG5->FMT3;
	.loc 1 3098 0
	ldr	r2, [r3, #-163]	@ _13, MEM[(volatile struct mibspiBASE_t *)4294441984B].FMT3
	str	r2, [r0, #48]	@ _13, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:3099:         config_reg->CONFIG_MIBSPIE    = mibspiREG5->MIBSPIE;
	.loc 1 3099 0
	ldr	r2, [r3, #-143]	@ _14, MEM[(volatile struct mibspiBASE_t *)4294441984B].MIBSPIE
	str	r2, [r0, #52]	@ _14, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:3100:         config_reg->CONFIG_LTGPEND    = mibspiREG5->LTGPEND;
	.loc 1 3100 0
	ldr	r2, [r3, #-107]	@ _15, MEM[(volatile struct mibspiBASE_t *)4294441984B].LTGPEND
	str	r2, [r0, #56]	@ _15, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:3101:         config_reg->CONFIG_TGCTRL[0U] = mibspiREG5->TGCTRL[0U];
	.loc 1 3101 0
	ldr	r2, [r3, #-103]	@ _16, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #60]	@ _16, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3102:         config_reg->CONFIG_TGCTRL[1U] = mibspiREG5->TGCTRL[1U];
	.loc 1 3102 0
	ldr	r2, [r3, #-99]	@ _17, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #64]	@ _17, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3103:         config_reg->CONFIG_TGCTRL[2U] = mibspiREG5->TGCTRL[2U];
	.loc 1 3103 0
	ldr	r2, [r3, #-95]	@ _18, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #68]	@ _18, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3104:         config_reg->CONFIG_TGCTRL[3U] = mibspiREG5->TGCTRL[3U];
	.loc 1 3104 0
	ldr	r2, [r3, #-91]	@ _19, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #72]	@ _19, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3105:         config_reg->CONFIG_TGCTRL[4U] = mibspiREG5->TGCTRL[4U];
	.loc 1 3105 0
	ldr	r2, [r3, #-87]	@ _20, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #76]	@ _20, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3106:         config_reg->CONFIG_TGCTRL[5U] = mibspiREG5->TGCTRL[5U];
	.loc 1 3106 0
	ldr	r2, [r3, #-83]	@ _21, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #80]	@ _21, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3107:         config_reg->CONFIG_TGCTRL[6U] = mibspiREG5->TGCTRL[6U];
	.loc 1 3107 0
	ldr	r2, [r3, #-79]	@ _22, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #84]	@ _22, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3108:         config_reg->CONFIG_TGCTRL[7U] = mibspiREG5->TGCTRL[7U];
	.loc 1 3108 0
	ldr	r2, [r3, #-75]	@ _23, MEM[(volatile struct mibspiBASE_t *)4294441984B].TGCTRL
	str	r2, [r0, #88]	@ _23, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3109:         config_reg->CONFIG_PAR_ECC_CTRL   = mibspiREG5->PAR_ECC_CTRL;
	.loc 1 3109 0
	ldr	r3, [r3, #33]	@ _24, MEM[(volatile struct mibspiBASE_t *)4294441984B].PAR_ECC_CTRL
	str	r3, [r0, #92]	@ _24, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
@ ../source/HL_mibspi.c:3111: }
	.loc 1 3111 0
	bx	lr	@
.L90:
@ ../source/HL_mibspi.c:3058:         config_reg->CONFIG_GCR1       = MIBSPI5_GCR1_CONFIGVALUE; 
	.loc 1 3058 0
	mov	r3, #3	@ tmp136,
	movt	r3, 256	@ tmp136,
	str	r3, [r0]	@ tmp136, config_reg_28(D)->CONFIG_GCR1
@ ../source/HL_mibspi.c:3059:         config_reg->CONFIG_INT0       = MIBSPI5_INT0_CONFIGVALUE; 
	.loc 1 3059 0
	mov	r3, #0	@ tmp137,
	str	r3, [r0, #4]	@ tmp137, config_reg_28(D)->CONFIG_INT0
@ ../source/HL_mibspi.c:3060:         config_reg->CONFIG_LVL        = MIBSPI5_LVL_CONFIGVALUE; 
	.loc 1 3060 0
	str	r3, [r0, #8]	@ tmp137, config_reg_28(D)->CONFIG_LVL
@ ../source/HL_mibspi.c:3061:         config_reg->CONFIG_PCFUN      = MIBSPI5_PCFUN_CONFIGVALUE; 
	.loc 1 3061 0
	movw	r2, #3841	@ tmp139,
	movt	r2, 3855	@ tmp139,
	str	r2, [r0, #12]	@ tmp139, config_reg_28(D)->CONFIG_PCFUN
@ ../source/HL_mibspi.c:3062:         config_reg->CONFIG_PCDIR      = MIBSPI5_PCDIR_CONFIGVALUE; 
	.loc 1 3062 0
	movw	r2, #1551	@ tmp140,
	movt	r2, 1	@ tmp140,
	str	r2, [r0, #16]	@ tmp140, config_reg_28(D)->CONFIG_PCDIR
@ ../source/HL_mibspi.c:3063:         config_reg->CONFIG_PCPDR      = MIBSPI5_PCPDR_CONFIGVALUE; 
	.loc 1 3063 0
	str	r3, [r0, #20]	@ tmp137, config_reg_28(D)->CONFIG_PCPDR
@ ../source/HL_mibspi.c:3064:         config_reg->CONFIG_PCDIS      = MIBSPI5_PCDIS_CONFIGVALUE; 
	.loc 1 3064 0
	str	r3, [r0, #24]	@ tmp137, config_reg_28(D)->CONFIG_PCDIS
@ ../source/HL_mibspi.c:3065:         config_reg->CONFIG_PCPSL      = MIBSPI5_PCPSL_CONFIGVALUE; 
	.loc 1 3065 0
	movw	r2, #3855	@ tmp143,
	bfi	r2, r2, #16, #16	@ tmp143, tmp143,,
	str	r2, [r0, #28]	@ tmp143, config_reg_28(D)->CONFIG_PCPSL
@ ../source/HL_mibspi.c:3066:         config_reg->CONFIG_DELAY      = MIBSPI5_DELAY_CONFIGVALUE; 
	.loc 1 3066 0
	str	r3, [r0, #32]	@ tmp137, config_reg_28(D)->CONFIG_DELAY
@ ../source/HL_mibspi.c:3067:         config_reg->CONFIG_FMT0       = MIBSPI5_FMT0_CONFIGVALUE; 
	.loc 1 3067 0
	movw	r2, #18960	@ tmp145,
	str	r2, [r0, #36]	@ tmp145, config_reg_28(D)->CONFIG_FMT0
@ ../source/HL_mibspi.c:3068:         config_reg->CONFIG_FMT1       = MIBSPI5_FMT1_CONFIGVALUE; 
	.loc 1 3068 0
	str	r2, [r0, #40]	@ tmp145, config_reg_28(D)->CONFIG_FMT1
@ ../source/HL_mibspi.c:3069:         config_reg->CONFIG_FMT2       = MIBSPI5_FMT2_CONFIGVALUE; 
	.loc 1 3069 0
	str	r2, [r0, #44]	@ tmp145, config_reg_28(D)->CONFIG_FMT2
@ ../source/HL_mibspi.c:3070:         config_reg->CONFIG_FMT3       = MIBSPI5_FMT3_CONFIGVALUE; 
	.loc 1 3070 0
	str	r2, [r0, #48]	@ tmp145, config_reg_28(D)->CONFIG_FMT3
@ ../source/HL_mibspi.c:3071:         config_reg->CONFIG_MIBSPIE    = MIBSPI5_MIBSPIE_CONFIGVALUE; 
	.loc 1 3071 0
	movw	r2, #1281	@ tmp149,
	str	r2, [r0, #52]	@ tmp149, config_reg_28(D)->CONFIG_MIBSPIE
@ ../source/HL_mibspi.c:3072:         config_reg->CONFIG_LTGPEND    = MIBSPI5_LTGPEND_CONFIGVALUE; 
	.loc 1 3072 0
	mov	r2, #1792	@ tmp150,
	str	r2, [r0, #56]	@ tmp150, config_reg_28(D)->CONFIG_LTGPEND
@ ../source/HL_mibspi.c:3073:         config_reg->CONFIG_TGCTRL[0U] = MIBSPI5_TGCTRL0_CONFIGVALUE;
	.loc 1 3073 0
	movt	r3, 16496	@ tmp151,
	str	r3, [r0, #60]	@ tmp151, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3074:         config_reg->CONFIG_TGCTRL[1U] = MIBSPI5_TGCTRL1_CONFIGVALUE;
	.loc 1 3074 0
	mov	r3, #2048	@ tmp152,
	movt	r3, 16496	@ tmp152,
	str	r3, [r0, #64]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3075:         config_reg->CONFIG_TGCTRL[2U] = MIBSPI5_TGCTRL2_CONFIGVALUE;
	.loc 1 3075 0
	str	r3, [r0, #68]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3076:         config_reg->CONFIG_TGCTRL[3U] = MIBSPI5_TGCTRL3_CONFIGVALUE;
	.loc 1 3076 0
	str	r3, [r0, #72]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3077:         config_reg->CONFIG_TGCTRL[4U] = MIBSPI5_TGCTRL4_CONFIGVALUE;
	.loc 1 3077 0
	str	r3, [r0, #76]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3078:         config_reg->CONFIG_TGCTRL[5U] = MIBSPI5_TGCTRL5_CONFIGVALUE;
	.loc 1 3078 0
	str	r3, [r0, #80]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3079:         config_reg->CONFIG_TGCTRL[6U] = MIBSPI5_TGCTRL6_CONFIGVALUE;
	.loc 1 3079 0
	str	r3, [r0, #84]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3080:         config_reg->CONFIG_TGCTRL[7U] = MIBSPI5_TGCTRL7_CONFIGVALUE;
	.loc 1 3080 0
	str	r3, [r0, #88]	@ tmp152, config_reg_28(D)->CONFIG_TGCTRL
@ ../source/HL_mibspi.c:3081:         config_reg->CONFIG_PAR_ECC_CTRL   = MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE; 
	.loc 1 3081 0
	mov	r3, #5	@ tmp159,
	movt	r3, 1290	@ tmp159,
	str	r3, [r0, #92]	@ tmp159, config_reg_28(D)->CONFIG_PAR_ECC_CTRL
	bx	lr	@
	.cfi_endproc
.LFE18:
	.size	mibspi5GetConfigValue, .-mibspi5GetConfigValue
.Letext0:
	.file 2 "/home/mr_halfword/ti/ccs901/ccs/tools/compiler/gcc-arm-none-eabi-7-2017-q4-major/arm-none-eabi/include/machine/_default_types.h"
	.file 3 "/home/mr_halfword/ti/ccs901/ccs/tools/compiler/gcc-arm-none-eabi-7-2017-q4-major/arm-none-eabi/include/sys/_stdint.h"
	.file 4 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_hal_stdtypes.h"
	.file 5 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_sys_common.h"
	.file 6 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_reg_mibspi.h"
	.file 7 "/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_halcogen/include/HL_mibspi.h"
	.section	.debug_info,"",%progbits
.Ldebug_info0:
	.4byte	0xbdf
	.2byte	0x3
	.4byte	.Ldebug_abbrev0
	.byte	0x4
	.uleb128 0x1
	.4byte	.LASF175
	.byte	0xc
	.4byte	.LASF176
	.4byte	.LASF177
	.4byte	.Ltext0
	.4byte	.Letext0
	.4byte	.Ldebug_line0
	.uleb128 0x2
	.byte	0x1
	.byte	0x6
	.4byte	.LASF0
	.uleb128 0x3
	.4byte	.LASF3
	.byte	0x2
	.byte	0x2b
	.4byte	0x37
	.uleb128 0x2
	.byte	0x1
	.byte	0x8
	.4byte	.LASF1
	.uleb128 0x2
	.byte	0x2
	.byte	0x5
	.4byte	.LASF2
	.uleb128 0x3
	.4byte	.LASF4
	.byte	0x2
	.byte	0x39
	.4byte	0x50
	.uleb128 0x2
	.byte	0x2
	.byte	0x7
	.4byte	.LASF5
	.uleb128 0x2
	.byte	0x4
	.byte	0x5
	.4byte	.LASF6
	.uleb128 0x3
	.4byte	.LASF7
	.byte	0x2
	.byte	0x4f
	.4byte	0x69
	.uleb128 0x2
	.byte	0x4
	.byte	0x7
	.4byte	.LASF8
	.uleb128 0x2
	.byte	0x8
	.byte	0x5
	.4byte	.LASF9
	.uleb128 0x2
	.byte	0x8
	.byte	0x7
	.4byte	.LASF10
	.uleb128 0x4
	.byte	0x4
	.byte	0x5
	.ascii	"int\000"
	.uleb128 0x2
	.byte	0x4
	.byte	0x7
	.4byte	.LASF11
	.uleb128 0x3
	.4byte	.LASF12
	.byte	0x3
	.byte	0x18
	.4byte	0x2c
	.uleb128 0x3
	.4byte	.LASF13
	.byte	0x3
	.byte	0x24
	.4byte	0x45
	.uleb128 0x3
	.4byte	.LASF14
	.byte	0x3
	.byte	0x30
	.4byte	0x5e
	.uleb128 0x3
	.4byte	.LASF15
	.byte	0x4
	.byte	0x41
	.4byte	0xa2
	.uleb128 0x3
	.4byte	.LASF16
	.byte	0x4
	.byte	0x46
	.4byte	0x97
	.uleb128 0x3
	.4byte	.LASF17
	.byte	0x4
	.byte	0x4b
	.4byte	0x8c
	.uleb128 0x3
	.4byte	.LASF18
	.byte	0x4
	.byte	0x53
	.4byte	0xde
	.uleb128 0x5
	.4byte	0xce
	.uleb128 0x2
	.byte	0x1
	.byte	0x2
	.4byte	.LASF19
	.uleb128 0x2
	.byte	0x4
	.byte	0x4
	.4byte	.LASF20
	.uleb128 0x2
	.byte	0x8
	.byte	0x4
	.4byte	.LASF21
	.uleb128 0x6
	.4byte	.LASF25
	.byte	0x1
	.4byte	0x37
	.byte	0x5
	.byte	0x4c
	.4byte	0x110
	.uleb128 0x7
	.4byte	.LASF22
	.byte	0
	.uleb128 0x7
	.4byte	.LASF23
	.byte	0x1
	.byte	0
	.uleb128 0x3
	.4byte	.LASF24
	.byte	0x5
	.byte	0x50
	.4byte	0xf3
	.uleb128 0x6
	.4byte	.LASF26
	.byte	0x1
	.4byte	0x37
	.byte	0x5
	.byte	0x5a
	.4byte	0x138
	.uleb128 0x7
	.4byte	.LASF27
	.byte	0
	.uleb128 0x7
	.4byte	.LASF28
	.byte	0x1
	.byte	0
	.uleb128 0x3
	.4byte	.LASF29
	.byte	0x5
	.byte	0x5e
	.4byte	0x11b
	.uleb128 0x8
	.4byte	.LASF75
	.2byte	0x158
	.byte	0x6
	.byte	0x47
	.4byte	0x3f4
	.uleb128 0x9
	.4byte	.LASF30
	.byte	0x6
	.byte	0x49
	.4byte	0xad
	.byte	0
	.uleb128 0x9
	.4byte	.LASF31
	.byte	0x6
	.byte	0x4a
	.4byte	0xad
	.byte	0x4
	.uleb128 0x9
	.4byte	.LASF32
	.byte	0x6
	.byte	0x4b
	.4byte	0xad
	.byte	0x8
	.uleb128 0xa
	.ascii	"LVL\000"
	.byte	0x6
	.byte	0x4c
	.4byte	0xad
	.byte	0xc
	.uleb128 0xa
	.ascii	"FLG\000"
	.byte	0x6
	.byte	0x4d
	.4byte	0xad
	.byte	0x10
	.uleb128 0xa
	.ascii	"PC0\000"
	.byte	0x6
	.byte	0x4e
	.4byte	0xad
	.byte	0x14
	.uleb128 0xa
	.ascii	"PC1\000"
	.byte	0x6
	.byte	0x4f
	.4byte	0xad
	.byte	0x18
	.uleb128 0xa
	.ascii	"PC2\000"
	.byte	0x6
	.byte	0x50
	.4byte	0xad
	.byte	0x1c
	.uleb128 0xa
	.ascii	"PC3\000"
	.byte	0x6
	.byte	0x51
	.4byte	0xad
	.byte	0x20
	.uleb128 0xa
	.ascii	"PC4\000"
	.byte	0x6
	.byte	0x52
	.4byte	0xad
	.byte	0x24
	.uleb128 0xa
	.ascii	"PC5\000"
	.byte	0x6
	.byte	0x53
	.4byte	0xad
	.byte	0x28
	.uleb128 0xa
	.ascii	"PC6\000"
	.byte	0x6
	.byte	0x54
	.4byte	0xad
	.byte	0x2c
	.uleb128 0xa
	.ascii	"PC7\000"
	.byte	0x6
	.byte	0x55
	.4byte	0xad
	.byte	0x30
	.uleb128 0xa
	.ascii	"PC8\000"
	.byte	0x6
	.byte	0x56
	.4byte	0xad
	.byte	0x34
	.uleb128 0x9
	.4byte	.LASF33
	.byte	0x6
	.byte	0x57
	.4byte	0xad
	.byte	0x38
	.uleb128 0x9
	.4byte	.LASF34
	.byte	0x6
	.byte	0x58
	.4byte	0xad
	.byte	0x3c
	.uleb128 0xa
	.ascii	"BUF\000"
	.byte	0x6
	.byte	0x59
	.4byte	0xad
	.byte	0x40
	.uleb128 0xa
	.ascii	"EMU\000"
	.byte	0x6
	.byte	0x5a
	.4byte	0xad
	.byte	0x44
	.uleb128 0x9
	.4byte	.LASF35
	.byte	0x6
	.byte	0x5b
	.4byte	0xad
	.byte	0x48
	.uleb128 0xa
	.ascii	"DEF\000"
	.byte	0x6
	.byte	0x5c
	.4byte	0xad
	.byte	0x4c
	.uleb128 0x9
	.4byte	.LASF36
	.byte	0x6
	.byte	0x5d
	.4byte	0xad
	.byte	0x50
	.uleb128 0x9
	.4byte	.LASF37
	.byte	0x6
	.byte	0x5e
	.4byte	0xad
	.byte	0x54
	.uleb128 0x9
	.4byte	.LASF38
	.byte	0x6
	.byte	0x5f
	.4byte	0xad
	.byte	0x58
	.uleb128 0x9
	.4byte	.LASF39
	.byte	0x6
	.byte	0x60
	.4byte	0xad
	.byte	0x5c
	.uleb128 0x9
	.4byte	.LASF40
	.byte	0x6
	.byte	0x61
	.4byte	0xad
	.byte	0x60
	.uleb128 0x9
	.4byte	.LASF41
	.byte	0x6
	.byte	0x62
	.4byte	0xad
	.byte	0x64
	.uleb128 0x9
	.4byte	.LASF42
	.byte	0x6
	.byte	0x63
	.4byte	0xad
	.byte	0x68
	.uleb128 0x9
	.4byte	.LASF43
	.byte	0x6
	.byte	0x64
	.4byte	0xad
	.byte	0x6c
	.uleb128 0x9
	.4byte	.LASF44
	.byte	0x6
	.byte	0x65
	.4byte	0xad
	.byte	0x70
	.uleb128 0x9
	.4byte	.LASF45
	.byte	0x6
	.byte	0x66
	.4byte	0xad
	.byte	0x74
	.uleb128 0x9
	.4byte	.LASF46
	.byte	0x6
	.byte	0x67
	.4byte	0xad
	.byte	0x78
	.uleb128 0x9
	.4byte	.LASF47
	.byte	0x6
	.byte	0x68
	.4byte	0xad
	.byte	0x7c
	.uleb128 0x9
	.4byte	.LASF48
	.byte	0x6
	.byte	0x69
	.4byte	0xad
	.byte	0x80
	.uleb128 0x9
	.4byte	.LASF49
	.byte	0x6
	.byte	0x6a
	.4byte	0xad
	.byte	0x84
	.uleb128 0x9
	.4byte	.LASF50
	.byte	0x6
	.byte	0x6b
	.4byte	0x3f9
	.byte	0x88
	.uleb128 0x9
	.4byte	.LASF51
	.byte	0x6
	.byte	0x6c
	.4byte	0xad
	.byte	0x90
	.uleb128 0x9
	.4byte	.LASF52
	.byte	0x6
	.byte	0x6d
	.4byte	0xad
	.byte	0x94
	.uleb128 0x9
	.4byte	.LASF53
	.byte	0x6
	.byte	0x6e
	.4byte	0x409
	.byte	0x98
	.uleb128 0x9
	.4byte	.LASF54
	.byte	0x6
	.byte	0x6f
	.4byte	0x419
	.byte	0xd8
	.uleb128 0x9
	.4byte	.LASF55
	.byte	0x6
	.byte	0x70
	.4byte	0x419
	.byte	0xf8
	.uleb128 0xb
	.4byte	.LASF56
	.byte	0x6
	.byte	0x71
	.4byte	0xad
	.2byte	0x118
	.uleb128 0xb
	.4byte	.LASF57
	.byte	0x6
	.byte	0x72
	.4byte	0xad
	.2byte	0x11c
	.uleb128 0xb
	.4byte	.LASF58
	.byte	0x6
	.byte	0x73
	.4byte	0xad
	.2byte	0x120
	.uleb128 0xb
	.4byte	.LASF59
	.byte	0x6
	.byte	0x74
	.4byte	0xad
	.2byte	0x124
	.uleb128 0xb
	.4byte	.LASF60
	.byte	0x6
	.byte	0x75
	.4byte	0xad
	.2byte	0x128
	.uleb128 0xb
	.4byte	.LASF61
	.byte	0x6
	.byte	0x76
	.4byte	0xad
	.2byte	0x12c
	.uleb128 0xb
	.4byte	.LASF62
	.byte	0x6
	.byte	0x77
	.4byte	0xad
	.2byte	0x130
	.uleb128 0xb
	.4byte	.LASF63
	.byte	0x6
	.byte	0x78
	.4byte	0xad
	.2byte	0x134
	.uleb128 0xb
	.4byte	.LASF64
	.byte	0x6
	.byte	0x79
	.4byte	0xad
	.2byte	0x138
	.uleb128 0xb
	.4byte	.LASF65
	.byte	0x6
	.byte	0x7a
	.4byte	0xad
	.2byte	0x13c
	.uleb128 0xb
	.4byte	.LASF66
	.byte	0x6
	.byte	0x7b
	.4byte	0xad
	.2byte	0x140
	.uleb128 0xb
	.4byte	.LASF67
	.byte	0x6
	.byte	0x7c
	.4byte	0xad
	.2byte	0x144
	.uleb128 0xb
	.4byte	.LASF68
	.byte	0x6
	.byte	0x7d
	.4byte	0xad
	.2byte	0x148
	.uleb128 0xb
	.4byte	.LASF69
	.byte	0x6
	.byte	0x7e
	.4byte	0x429
	.2byte	0x14c
	.uleb128 0xb
	.4byte	.LASF70
	.byte	0x6
	.byte	0x7f
	.4byte	0xad
	.2byte	0x154
	.byte	0
	.uleb128 0x5
	.4byte	0x143
	.uleb128 0xc
	.4byte	0xad
	.4byte	0x409
	.uleb128 0xd
	.4byte	0x85
	.byte	0x1
	.byte	0
	.uleb128 0xc
	.4byte	0xad
	.4byte	0x419
	.uleb128 0xd
	.4byte	0x85
	.byte	0xf
	.byte	0
	.uleb128 0xc
	.4byte	0xad
	.4byte	0x429
	.uleb128 0xd
	.4byte	0x85
	.byte	0x7
	.byte	0
	.uleb128 0xc
	.4byte	0xc3
	.4byte	0x439
	.uleb128 0xd
	.4byte	0x85
	.byte	0x5
	.byte	0
	.uleb128 0x3
	.4byte	.LASF71
	.byte	0x6
	.byte	0x81
	.4byte	0x3f4
	.uleb128 0xe
	.byte	0x4
	.byte	0x6
	.byte	0xe3
	.4byte	0x465
	.uleb128 0x9
	.4byte	.LASF72
	.byte	0x6
	.byte	0xe9
	.4byte	0xb8
	.byte	0
	.uleb128 0x9
	.4byte	.LASF73
	.byte	0x6
	.byte	0xea
	.4byte	0xb8
	.byte	0x2
	.byte	0
	.uleb128 0xe
	.byte	0x4
	.byte	0x6
	.byte	0xed
	.4byte	0x486
	.uleb128 0x9
	.4byte	.LASF74
	.byte	0x6
	.byte	0xf3
	.4byte	0xb8
	.byte	0
	.uleb128 0x9
	.4byte	.LASF73
	.byte	0x6
	.byte	0xf4
	.4byte	0xb8
	.byte	0x2
	.byte	0
	.uleb128 0x8
	.4byte	.LASF76
	.2byte	0x400
	.byte	0x6
	.byte	0xe1
	.4byte	0x4ab
	.uleb128 0xa
	.ascii	"tx\000"
	.byte	0x6
	.byte	0xec
	.4byte	0x4b0
	.byte	0
	.uleb128 0xf
	.ascii	"rx\000"
	.byte	0x6
	.byte	0xf6
	.4byte	0x4c0
	.2byte	0x200
	.byte	0
	.uleb128 0x5
	.4byte	0x486
	.uleb128 0xc
	.4byte	0x444
	.4byte	0x4c0
	.uleb128 0xd
	.4byte	0x85
	.byte	0x7f
	.byte	0
	.uleb128 0xc
	.4byte	0x465
	.4byte	0x4d0
	.uleb128 0xd
	.4byte	0x85
	.byte	0x7f
	.byte	0
	.uleb128 0x3
	.4byte	.LASF77
	.byte	0x6
	.byte	0xf7
	.4byte	0x4ab
	.uleb128 0x6
	.4byte	.LASF78
	.byte	0x1
	.4byte	0x37
	.byte	0x7
	.byte	0x3b
	.4byte	0x516
	.uleb128 0x7
	.4byte	.LASF79
	.byte	0
	.uleb128 0x7
	.4byte	.LASF80
	.byte	0x1
	.uleb128 0x7
	.4byte	.LASF81
	.byte	0x2
	.uleb128 0x7
	.4byte	.LASF82
	.byte	0x3
	.uleb128 0x7
	.4byte	.LASF83
	.byte	0x5
	.uleb128 0x7
	.4byte	.LASF84
	.byte	0x6
	.uleb128 0x7
	.4byte	.LASF85
	.byte	0x7
	.byte	0
	.uleb128 0x6
	.4byte	.LASF86
	.byte	0x1
	.4byte	0x37
	.byte	0x7
	.byte	0x49
	.4byte	0x587
	.uleb128 0x7
	.4byte	.LASF87
	.byte	0
	.uleb128 0x7
	.4byte	.LASF88
	.byte	0x1
	.uleb128 0x7
	.4byte	.LASF89
	.byte	0x2
	.uleb128 0x7
	.4byte	.LASF90
	.byte	0x3
	.uleb128 0x7
	.4byte	.LASF91
	.byte	0x4
	.uleb128 0x7
	.4byte	.LASF92
	.byte	0x5
	.uleb128 0x7
	.4byte	.LASF93
	.byte	0x6
	.uleb128 0x7
	.4byte	.LASF94
	.byte	0x7
	.uleb128 0x7
	.4byte	.LASF95
	.byte	0x8
	.uleb128 0x7
	.4byte	.LASF96
	.byte	0x9
	.uleb128 0x7
	.4byte	.LASF97
	.byte	0xa
	.uleb128 0x7
	.4byte	.LASF98
	.byte	0xb
	.uleb128 0x7
	.4byte	.LASF99
	.byte	0xc
	.uleb128 0x7
	.4byte	.LASF100
	.byte	0xd
	.uleb128 0x7
	.4byte	.LASF101
	.byte	0xe
	.uleb128 0x7
	.4byte	.LASF102
	.byte	0xf
	.byte	0
	.uleb128 0x6
	.4byte	.LASF103
	.byte	0x1
	.4byte	0x37
	.byte	0x7
	.byte	0x83
	.4byte	0x5ce
	.uleb128 0x7
	.4byte	.LASF104
	.byte	0xff
	.uleb128 0x7
	.4byte	.LASF105
	.byte	0xfe
	.uleb128 0x7
	.4byte	.LASF106
	.byte	0xfd
	.uleb128 0x7
	.4byte	.LASF107
	.byte	0xfb
	.uleb128 0x7
	.4byte	.LASF108
	.byte	0xf7
	.uleb128 0x7
	.4byte	.LASF109
	.byte	0xef
	.uleb128 0x7
	.4byte	.LASF110
	.byte	0xdf
	.uleb128 0x7
	.4byte	.LASF111
	.byte	0xbf
	.uleb128 0x7
	.4byte	.LASF112
	.byte	0x7f
	.byte	0
	.uleb128 0x6
	.4byte	.LASF113
	.byte	0x1
	.4byte	0x37
	.byte	0x7
	.byte	0x95
	.4byte	0x5f7
	.uleb128 0x7
	.4byte	.LASF114
	.byte	0
	.uleb128 0x7
	.4byte	.LASF115
	.byte	0x1
	.uleb128 0x7
	.4byte	.LASF116
	.byte	0x2
	.uleb128 0x7
	.4byte	.LASF117
	.byte	0x3
	.byte	0
	.uleb128 0x3
	.4byte	.LASF118
	.byte	0x7
	.byte	0x9b
	.4byte	0x5ce
	.uleb128 0x6
	.4byte	.LASF119
	.byte	0x1
	.4byte	0x37
	.byte	0x7
	.byte	0xa2
	.4byte	0x62b
	.uleb128 0x7
	.4byte	.LASF120
	.byte	0
	.uleb128 0x7
	.4byte	.LASF121
	.byte	0x1
	.uleb128 0x7
	.4byte	.LASF122
	.byte	0x2
	.uleb128 0x7
	.4byte	.LASF123
	.byte	0x3
	.byte	0
	.uleb128 0x3
	.4byte	.LASF124
	.byte	0x7
	.byte	0xa8
	.4byte	0x602
	.uleb128 0x10
	.4byte	.LASF125
	.byte	0x60
	.byte	0x7
	.byte	0xaa
	.4byte	0x70f
	.uleb128 0x9
	.4byte	.LASF126
	.byte	0x7
	.byte	0xac
	.4byte	0xad
	.byte	0
	.uleb128 0x9
	.4byte	.LASF127
	.byte	0x7
	.byte	0xad
	.4byte	0xad
	.byte	0x4
	.uleb128 0x9
	.4byte	.LASF128
	.byte	0x7
	.byte	0xae
	.4byte	0xad
	.byte	0x8
	.uleb128 0x9
	.4byte	.LASF129
	.byte	0x7
	.byte	0xaf
	.4byte	0xad
	.byte	0xc
	.uleb128 0x9
	.4byte	.LASF130
	.byte	0x7
	.byte	0xb0
	.4byte	0xad
	.byte	0x10
	.uleb128 0x9
	.4byte	.LASF131
	.byte	0x7
	.byte	0xb1
	.4byte	0xad
	.byte	0x14
	.uleb128 0x9
	.4byte	.LASF132
	.byte	0x7
	.byte	0xb2
	.4byte	0xad
	.byte	0x18
	.uleb128 0x9
	.4byte	.LASF133
	.byte	0x7
	.byte	0xb3
	.4byte	0xad
	.byte	0x1c
	.uleb128 0x9
	.4byte	.LASF134
	.byte	0x7
	.byte	0xb4
	.4byte	0xad
	.byte	0x20
	.uleb128 0x9
	.4byte	.LASF135
	.byte	0x7
	.byte	0xb5
	.4byte	0xad
	.byte	0x24
	.uleb128 0x9
	.4byte	.LASF136
	.byte	0x7
	.byte	0xb6
	.4byte	0xad
	.byte	0x28
	.uleb128 0x9
	.4byte	.LASF137
	.byte	0x7
	.byte	0xb7
	.4byte	0xad
	.byte	0x2c
	.uleb128 0x9
	.4byte	.LASF138
	.byte	0x7
	.byte	0xb8
	.4byte	0xad
	.byte	0x30
	.uleb128 0x9
	.4byte	.LASF139
	.byte	0x7
	.byte	0xb9
	.4byte	0xad
	.byte	0x34
	.uleb128 0x9
	.4byte	.LASF140
	.byte	0x7
	.byte	0xba
	.4byte	0xad
	.byte	0x38
	.uleb128 0x9
	.4byte	.LASF141
	.byte	0x7
	.byte	0xbb
	.4byte	0x419
	.byte	0x3c
	.uleb128 0x9
	.4byte	.LASF142
	.byte	0x7
	.byte	0xbc
	.4byte	0xad
	.byte	0x5c
	.byte	0
	.uleb128 0x3
	.4byte	.LASF143
	.byte	0x7
	.byte	0xbd
	.4byte	0x636
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF146
	.byte	0x1
	.2byte	0xbee
	.byte	0x1
	.4byte	.LFB18
	.4byte	.LFE18
	.byte	0x1
	.byte	0x9c
	.4byte	0x74f
	.uleb128 0x12
	.4byte	.LASF144
	.byte	0x1
	.2byte	0xbee
	.4byte	0x74f
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF145
	.byte	0x1
	.2byte	0xbee
	.4byte	0x138
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x13
	.byte	0x4
	.4byte	0x70f
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF147
	.byte	0x1
	.2byte	0xba1
	.byte	0x1
	.4byte	.LFB17
	.4byte	.LFE17
	.byte	0x1
	.byte	0x9c
	.4byte	0x78a
	.uleb128 0x12
	.4byte	.LASF144
	.byte	0x1
	.2byte	0xba1
	.4byte	0x74f
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF145
	.byte	0x1
	.2byte	0xba1
	.4byte	0x138
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF148
	.byte	0x1
	.2byte	0xb54
	.byte	0x1
	.4byte	.LFB16
	.4byte	.LFE16
	.byte	0x1
	.byte	0x9c
	.4byte	0x7bf
	.uleb128 0x12
	.4byte	.LASF144
	.byte	0x1
	.2byte	0xb54
	.4byte	0x74f
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF145
	.byte	0x1
	.2byte	0xb54
	.4byte	0x138
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF149
	.byte	0x1
	.2byte	0xb07
	.byte	0x1
	.4byte	.LFB15
	.4byte	.LFE15
	.byte	0x1
	.byte	0x9c
	.4byte	0x7f4
	.uleb128 0x12
	.4byte	.LASF144
	.byte	0x1
	.2byte	0xb07
	.4byte	0x74f
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF145
	.byte	0x1
	.2byte	0xb07
	.4byte	0x138
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF150
	.byte	0x1
	.2byte	0xaba
	.byte	0x1
	.4byte	.LFB14
	.4byte	.LFE14
	.byte	0x1
	.byte	0x9c
	.4byte	0x829
	.uleb128 0x12
	.4byte	.LASF144
	.byte	0x1
	.2byte	0xaba
	.4byte	0x74f
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF145
	.byte	0x1
	.2byte	0xaba
	.4byte	0x138
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF151
	.byte	0x1
	.2byte	0xa9d
	.byte	0x1
	.4byte	.LFB13
	.4byte	.LFE13
	.byte	0x1
	.byte	0x9c
	.4byte	0x860
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0xa9d
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.uleb128 0x14
	.4byte	.LASF153
	.byte	0x1
	.2byte	0xa9d
	.4byte	0xad
	.4byte	.LLST24
	.byte	0
	.uleb128 0x13
	.byte	0x4
	.4byte	0x439
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF154
	.byte	0x1
	.2byte	0xa80
	.byte	0x1
	.4byte	.LFB12
	.4byte	.LFE12
	.byte	0x1
	.byte	0x9c
	.4byte	0x8ad
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0xa80
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.uleb128 0x14
	.4byte	.LASF153
	.byte	0x1
	.2byte	0xa80
	.4byte	0xad
	.4byte	.LLST22
	.uleb128 0x14
	.4byte	.LASF155
	.byte	0x1
	.2byte	0xa80
	.4byte	0xad
	.4byte	.LLST23
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF156
	.byte	0x1
	.2byte	0xa6c
	.byte	0x1
	.4byte	.LFB11
	.4byte	.LFE11
	.byte	0x1
	.byte	0x9c
	.4byte	0x902
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0xa6c
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF157
	.byte	0x1
	.2byte	0xa6c
	.4byte	0x5f7
	.byte	0x1
	.byte	0x51
	.uleb128 0x14
	.4byte	.LASF158
	.byte	0x1
	.2byte	0xa6c
	.4byte	0x62b
	.4byte	.LLST20
	.uleb128 0x15
	.4byte	.LASF162
	.byte	0x1
	.2byte	0xa6e
	.4byte	0xad
	.4byte	.LLST21
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF159
	.byte	0x1
	.2byte	0xa4d
	.byte	0x1
	.4byte	.LFB10
	.4byte	.LFE10
	.byte	0x1
	.byte	0x9c
	.4byte	0x929
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0xa4d
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF160
	.byte	0x1
	.2byte	0xa34
	.byte	0x1
	.4byte	.LFB9
	.4byte	.LFE9
	.byte	0x1
	.byte	0x9c
	.4byte	0x960
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0xa34
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.uleb128 0x14
	.4byte	.LASF161
	.byte	0x1
	.2byte	0xa34
	.4byte	0x110
	.4byte	.LLST19
	.byte	0
	.uleb128 0x16
	.byte	0x1
	.4byte	.LASF165
	.byte	0x1
	.2byte	0xa12
	.byte	0x1
	.4byte	0xce
	.4byte	.LFB8
	.4byte	.LFE8
	.byte	0x1
	.byte	0x9c
	.4byte	0x9ad
	.uleb128 0x14
	.4byte	.LASF152
	.byte	0x1
	.2byte	0xa12
	.4byte	0x860
	.4byte	.LLST16
	.uleb128 0x14
	.4byte	.LASF153
	.byte	0x1
	.2byte	0xa12
	.4byte	0xad
	.4byte	.LLST17
	.uleb128 0x15
	.4byte	.LASF163
	.byte	0x1
	.2byte	0xa14
	.4byte	0xce
	.4byte	.LLST18
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF164
	.byte	0x1
	.2byte	0x9f9
	.byte	0x1
	.4byte	.LFB7
	.4byte	.LFE7
	.byte	0x1
	.byte	0x9c
	.4byte	0x9e4
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x9f9
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.uleb128 0x14
	.4byte	.LASF153
	.byte	0x1
	.2byte	0x9f9
	.4byte	0xad
	.4byte	.LLST15
	.byte	0
	.uleb128 0x16
	.byte	0x1
	.4byte	.LASF166
	.byte	0x1
	.2byte	0x9cf
	.byte	0x1
	.4byte	0xad
	.4byte	.LFB6
	.4byte	.LFE6
	.byte	0x1
	.byte	0x9c
	.4byte	0xa81
	.uleb128 0x14
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x9cf
	.4byte	0x860
	.4byte	.LLST7
	.uleb128 0x14
	.4byte	.LASF153
	.byte	0x1
	.2byte	0x9cf
	.4byte	0xad
	.4byte	.LLST8
	.uleb128 0x14
	.4byte	.LASF73
	.byte	0x1
	.2byte	0x9cf
	.4byte	0xa81
	.4byte	.LLST9
	.uleb128 0x17
	.ascii	"ram\000"
	.byte	0x1
	.2byte	0x9d4
	.4byte	0xa87
	.4byte	.LLST10
	.uleb128 0x15
	.4byte	.LASF167
	.byte	0x1
	.2byte	0x9d8
	.4byte	0xad
	.4byte	.LLST11
	.uleb128 0x17
	.ascii	"end\000"
	.byte	0x1
	.2byte	0x9d9
	.4byte	0xad
	.4byte	.LLST12
	.uleb128 0x15
	.4byte	.LASF168
	.byte	0x1
	.2byte	0x9da
	.4byte	0xb8
	.4byte	.LLST13
	.uleb128 0x17
	.ascii	"ret\000"
	.byte	0x1
	.2byte	0x9db
	.4byte	0xad
	.4byte	.LLST14
	.byte	0
	.uleb128 0x13
	.byte	0x4
	.4byte	0xb8
	.uleb128 0x13
	.byte	0x4
	.4byte	0x4d0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF169
	.byte	0x1
	.2byte	0x9a5
	.byte	0x1
	.4byte	.LFB5
	.4byte	.LFE5
	.byte	0x1
	.byte	0x9c
	.4byte	0xb06
	.uleb128 0x14
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x9a5
	.4byte	0x860
	.4byte	.LLST1
	.uleb128 0x14
	.4byte	.LASF153
	.byte	0x1
	.2byte	0x9a5
	.4byte	0xad
	.4byte	.LLST2
	.uleb128 0x14
	.4byte	.LASF73
	.byte	0x1
	.2byte	0x9a5
	.4byte	0xa81
	.4byte	.LLST3
	.uleb128 0x17
	.ascii	"ram\000"
	.byte	0x1
	.2byte	0x9aa
	.4byte	0xa87
	.4byte	.LLST4
	.uleb128 0x15
	.4byte	.LASF167
	.byte	0x1
	.2byte	0x9ae
	.4byte	0xad
	.4byte	.LLST5
	.uleb128 0x17
	.ascii	"end\000"
	.byte	0x1
	.2byte	0x9af
	.4byte	0xad
	.4byte	.LLST6
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF170
	.byte	0x1
	.2byte	0x98e
	.byte	0x1
	.4byte	.LFB4
	.4byte	.LFE4
	.byte	0x1
	.byte	0x9c
	.4byte	0xb3b
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x98e
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.uleb128 0x12
	.4byte	.LASF171
	.byte	0x1
	.2byte	0x98e
	.4byte	0xad
	.byte	0x1
	.byte	0x51
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF172
	.byte	0x1
	.2byte	0x977
	.byte	0x1
	.4byte	.LFB3
	.4byte	.LFE3
	.byte	0x1
	.byte	0x9c
	.4byte	0xb62
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x977
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.byte	0
	.uleb128 0x11
	.byte	0x1
	.4byte	.LASF173
	.byte	0x1
	.2byte	0x963
	.byte	0x1
	.4byte	.LFB2
	.4byte	.LFE2
	.byte	0x1
	.byte	0x9c
	.4byte	0xb89
	.uleb128 0x12
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x963
	.4byte	0x860
	.byte	0x1
	.byte	0x50
	.byte	0
	.uleb128 0x16
	.byte	0x1
	.4byte	.LASF174
	.byte	0x1
	.2byte	0x946
	.byte	0x1
	.4byte	0xce
	.4byte	.LFB1
	.4byte	.LFE1
	.byte	0x1
	.byte	0x9c
	.4byte	0xbc5
	.uleb128 0x14
	.4byte	.LASF152
	.byte	0x1
	.2byte	0x946
	.4byte	0x860
	.4byte	.LLST0
	.uleb128 0x18
	.4byte	.LASF163
	.byte	0x1
	.2byte	0x948
	.4byte	0xd9
	.byte	0x2
	.byte	0x91
	.sleb128 -1
	.byte	0
	.uleb128 0x19
	.byte	0x1
	.4byte	.LASF178
	.byte	0x1
	.byte	0x3b
	.byte	0x1
	.4byte	.LFB0
	.4byte	.LFE0
	.byte	0x1
	.byte	0x9c
	.uleb128 0x1a
	.ascii	"i\000"
	.byte	0x1
	.byte	0x3d
	.4byte	0xad
	.byte	0
	.byte	0
	.section	.debug_abbrev,"",%progbits
.Ldebug_abbrev0:
	.uleb128 0x1
	.uleb128 0x11
	.byte	0x1
	.uleb128 0x25
	.uleb128 0xe
	.uleb128 0x13
	.uleb128 0xb
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x1b
	.uleb128 0xe
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x10
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x2
	.uleb128 0x24
	.byte	0
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3e
	.uleb128 0xb
	.uleb128 0x3
	.uleb128 0xe
	.byte	0
	.byte	0
	.uleb128 0x3
	.uleb128 0x16
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x4
	.uleb128 0x24
	.byte	0
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3e
	.uleb128 0xb
	.uleb128 0x3
	.uleb128 0x8
	.byte	0
	.byte	0
	.uleb128 0x5
	.uleb128 0x35
	.byte	0
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x6
	.uleb128 0x4
	.byte	0x1
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x7
	.uleb128 0x28
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x1c
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0x8
	.uleb128 0x13
	.byte	0x1
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0xb
	.uleb128 0x5
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x9
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0xa
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0xb
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0x5
	.byte	0
	.byte	0
	.uleb128 0xc
	.uleb128 0x1
	.byte	0x1
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0xd
	.uleb128 0x21
	.byte	0
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2f
	.uleb128 0xb
	.byte	0
	.byte	0
	.uleb128 0xe
	.uleb128 0x13
	.byte	0x1
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0xf
	.uleb128 0xd
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x38
	.uleb128 0x5
	.byte	0
	.byte	0
	.uleb128 0x10
	.uleb128 0x13
	.byte	0x1
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x11
	.uleb128 0x2e
	.byte	0x1
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x12
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x13
	.uleb128 0xf
	.byte	0
	.uleb128 0xb
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x14
	.uleb128 0x5
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x15
	.uleb128 0x34
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x16
	.uleb128 0x2e
	.byte	0x1
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.uleb128 0x1
	.uleb128 0x13
	.byte	0
	.byte	0
	.uleb128 0x17
	.uleb128 0x34
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0x6
	.byte	0
	.byte	0
	.uleb128 0x18
	.uleb128 0x34
	.byte	0
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0x5
	.uleb128 0x49
	.uleb128 0x13
	.uleb128 0x2
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x19
	.uleb128 0x2e
	.byte	0x1
	.uleb128 0x3f
	.uleb128 0xc
	.uleb128 0x3
	.uleb128 0xe
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x27
	.uleb128 0xc
	.uleb128 0x11
	.uleb128 0x1
	.uleb128 0x12
	.uleb128 0x1
	.uleb128 0x40
	.uleb128 0xa
	.byte	0
	.byte	0
	.uleb128 0x1a
	.uleb128 0x34
	.byte	0
	.uleb128 0x3
	.uleb128 0x8
	.uleb128 0x3a
	.uleb128 0xb
	.uleb128 0x3b
	.uleb128 0xb
	.uleb128 0x49
	.uleb128 0x13
	.byte	0
	.byte	0
	.byte	0
	.section	.debug_loc,"",%progbits
.Ldebug_loc0:
.LLST24:
	.4byte	.LVL79-.Ltext0
	.4byte	.LVL80-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST22:
	.4byte	.LVL74-.Ltext0
	.4byte	.LVL76-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	.LVL77-.Ltext0
	.4byte	.LFE12-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST23:
	.4byte	.LVL74-.Ltext0
	.4byte	.LVL75-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	.LVL77-.Ltext0
	.4byte	.LVL78-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	0
	.4byte	0
.LLST20:
	.4byte	.LVL70-.Ltext0
	.4byte	.LVL71-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	0
	.4byte	0
.LLST21:
	.4byte	.LVL72-.Ltext0
	.4byte	.LVL73-.Ltext0
	.2byte	0x1
	.byte	0x53
	.4byte	0
	.4byte	0
.LLST19:
	.4byte	.LVL67-.Ltext0
	.4byte	.LVL68-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST16:
	.4byte	.LVL61-.Ltext0
	.4byte	.LVL64-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	.LVL65-.Ltext0
	.4byte	.LVL66-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST17:
	.4byte	.LVL61-.Ltext0
	.4byte	.LVL62-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	.LVL65-.Ltext0
	.4byte	.LFE8-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST18:
	.4byte	.LVL66-.Ltext0
	.4byte	.LFE8-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST15:
	.4byte	.LVL59-.Ltext0
	.4byte	.LVL60-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST7:
	.4byte	.LVL40-.Ltext0
	.4byte	.LVL47-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	.LVL48-.Ltext0
	.4byte	.LVL51-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	.LVL57-.Ltext0
	.4byte	.LFE6-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST8:
	.4byte	.LVL40-.Ltext0
	.4byte	.LVL43-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	.LVL48-.Ltext0
	.4byte	.LVL50-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST9:
	.4byte	.LVL40-.Ltext0
	.4byte	.LVL53-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	.LVL53-.Ltext0
	.4byte	.LFE6-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	0
	.4byte	0
.LLST10:
	.4byte	.LVL41-.Ltext0
	.4byte	.LVL48-.Ltext0
	.2byte	0x1
	.byte	0x5e
	.4byte	.LVL49-.Ltext0
	.4byte	.LFE6-.Ltext0
	.2byte	0x1
	.byte	0x5e
	.4byte	0
	.4byte	0
.LLST11:
	.4byte	.LVL42-.Ltext0
	.4byte	.LVL48-.Ltext0
	.2byte	0x1
	.byte	0x5c
	.4byte	.LVL49-.Ltext0
	.4byte	.LFE6-.Ltext0
	.2byte	0x1
	.byte	0x5c
	.4byte	0
	.4byte	0
.LLST12:
	.4byte	.LVL45-.Ltext0
	.4byte	.LVL46-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	.LVL51-.Ltext0
	.4byte	.LVL58-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST13:
	.4byte	.LVL51-.Ltext0
	.4byte	.LVL55-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST14:
	.4byte	.LVL56-.Ltext0
	.4byte	.LVL57-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST1:
	.4byte	.LVL26-.Ltext0
	.4byte	.LVL36-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
.LLST2:
	.4byte	.LVL26-.Ltext0
	.4byte	.LVL29-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	.LVL33-.Ltext0
	.4byte	.LVL35-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST3:
	.4byte	.LVL26-.Ltext0
	.4byte	.LVL37-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	.LVL38-.Ltext0
	.4byte	.LFE5-.Ltext0
	.2byte	0x1
	.byte	0x52
	.4byte	0
	.4byte	0
.LLST4:
	.4byte	.LVL27-.Ltext0
	.4byte	.LVL33-.Ltext0
	.2byte	0x1
	.byte	0x5e
	.4byte	.LVL34-.Ltext0
	.4byte	.LFE5-.Ltext0
	.2byte	0x1
	.byte	0x5e
	.4byte	0
	.4byte	0
.LLST5:
	.4byte	.LVL28-.Ltext0
	.4byte	.LVL33-.Ltext0
	.2byte	0x1
	.byte	0x53
	.4byte	.LVL34-.Ltext0
	.4byte	.LFE5-.Ltext0
	.2byte	0x1
	.byte	0x53
	.4byte	0
	.4byte	0
.LLST6:
	.4byte	.LVL31-.Ltext0
	.4byte	.LVL32-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	.LVL36-.Ltext0
	.4byte	.LFE5-.Ltext0
	.2byte	0x1
	.byte	0x51
	.4byte	0
	.4byte	0
.LLST0:
	.4byte	.LVL20-.Ltext0
	.4byte	.LVL21-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	.LVL22-.Ltext0
	.4byte	.LFE1-.Ltext0
	.2byte	0x1
	.byte	0x50
	.4byte	0
	.4byte	0
	.section	.debug_aranges,"",%progbits
	.4byte	0x1c
	.2byte	0x2
	.4byte	.Ldebug_info0
	.byte	0x4
	.byte	0
	.2byte	0
	.2byte	0
	.4byte	.Ltext0
	.4byte	.Letext0-.Ltext0
	.4byte	0
	.4byte	0
	.section	.debug_line,"",%progbits
.Ldebug_line0:
	.section	.debug_str,"MS",%progbits,1
.LASF88:
	.ascii	"TRG_GIOA0\000"
.LASF89:
	.ascii	"TRG_GIOA1\000"
.LASF90:
	.ascii	"TRG_GIOA2\000"
.LASF91:
	.ascii	"TRG_GIOA3\000"
.LASF16:
	.ascii	"uint16\000"
.LASF93:
	.ascii	"TRG_GIOA5\000"
.LASF94:
	.ascii	"TRG_GIOA6\000"
.LASF95:
	.ascii	"TRG_GIOA7\000"
.LASF157:
	.ascii	"Pmode\000"
.LASF152:
	.ascii	"mibspi\000"
.LASF160:
	.ascii	"mibspiEnableLoopback\000"
.LASF166:
	.ascii	"mibspiGetData\000"
.LASF141:
	.ascii	"CONFIG_TGCTRL\000"
.LASF3:
	.ascii	"__uint8_t\000"
.LASF82:
	.ascii	"TRG_BOTH\000"
.LASF80:
	.ascii	"TRG_RISING\000"
.LASF145:
	.ascii	"type\000"
.LASF23:
	.ascii	"Analog_Lbk\000"
.LASF10:
	.ascii	"long long unsigned int\000"
.LASF132:
	.ascii	"CONFIG_PCDIS\000"
.LASF81:
	.ascii	"TRG_FALLING\000"
.LASF153:
	.ascii	"group\000"
.LASF86:
	.ascii	"triggerSource\000"
.LASF130:
	.ascii	"CONFIG_PCDIR\000"
.LASF146:
	.ascii	"mibspi5GetConfigValue\000"
.LASF44:
	.ascii	"MIBSPIE\000"
.LASF174:
	.ascii	"mibspiIsBuffInitialized\000"
.LASF154:
	.ascii	"mibspiEnableGroupNotification\000"
.LASF71:
	.ascii	"mibspiBASE_t\000"
.LASF48:
	.ascii	"TGITLVCR\000"
.LASF9:
	.ascii	"long long int\000"
.LASF0:
	.ascii	"signed char\000"
.LASF117:
	.ascii	"PMODE_8_DATALINE\000"
.LASF85:
	.ascii	"TRG_ALWAYS\000"
.LASF103:
	.ascii	"chipSelect\000"
.LASF176:
	.ascii	"../source/HL_mibspi.c\000"
.LASF43:
	.ascii	"PMCTRL\000"
.LASF161:
	.ascii	"Loopbacktype\000"
.LASF175:
	.ascii	"GNU C11 7.2.1 20170904 (release) [ARM/embedded-7-br"
	.ascii	"anch revision 255204] -mcpu=cortex-r5 -mfloat-abi=h"
	.ascii	"ard -mfpu=vfpv3-d16 -g -gdwarf-3 -gstrict-dwarf -Og"
	.ascii	"\000"
.LASF96:
	.ascii	"TRG_HET1_8\000"
.LASF79:
	.ascii	"TRG_NEVER\000"
.LASF53:
	.ascii	"TGCTRL\000"
.LASF6:
	.ascii	"long int\000"
.LASF169:
	.ascii	"mibspiSetData\000"
.LASF17:
	.ascii	"uint8\000"
.LASF66:
	.ascii	"ECCDIAG_CTRL\000"
.LASF70:
	.ascii	"SBERRADDR0\000"
.LASF13:
	.ascii	"uint16_t\000"
.LASF21:
	.ascii	"double\000"
.LASF147:
	.ascii	"mibspi4GetConfigValue\000"
.LASF172:
	.ascii	"mibspiReset\000"
.LASF47:
	.ascii	"TGITLVST\000"
.LASF113:
	.ascii	"mibspiPmode\000"
.LASF15:
	.ascii	"uint32\000"
.LASF52:
	.ascii	"LTGPEND\000"
.LASF7:
	.ascii	"__uint32_t\000"
.LASF60:
	.ascii	"UERRADDRRX\000"
.LASF139:
	.ascii	"CONFIG_MIBSPIE\000"
.LASF155:
	.ascii	"level\000"
.LASF56:
	.ascii	"DMACNTLEN\000"
.LASF171:
	.ascii	"port\000"
.LASF150:
	.ascii	"mibspi1GetConfigValue\000"
.LASF156:
	.ascii	"mibspiPmodeSet\000"
.LASF133:
	.ascii	"CONFIG_PCPSL\000"
.LASF11:
	.ascii	"unsigned int\000"
.LASF29:
	.ascii	"config_value_type_t\000"
.LASF142:
	.ascii	"CONFIG_PAR_ECC_CTRL\000"
.LASF135:
	.ascii	"CONFIG_FMT0\000"
.LASF136:
	.ascii	"CONFIG_FMT1\000"
.LASF137:
	.ascii	"CONFIG_FMT2\000"
.LASF138:
	.ascii	"CONFIG_FMT3\000"
.LASF125:
	.ascii	"mibspi_config_reg\000"
.LASF126:
	.ascii	"CONFIG_GCR1\000"
.LASF8:
	.ascii	"long unsigned int\000"
.LASF46:
	.ascii	"TGITENCR\000"
.LASF131:
	.ascii	"CONFIG_PCPDR\000"
.LASF164:
	.ascii	"mibspiTransfer\000"
.LASF33:
	.ascii	"DAT0\000"
.LASF34:
	.ascii	"DAT1\000"
.LASF73:
	.ascii	"data\000"
.LASF5:
	.ascii	"short unsigned int\000"
.LASF87:
	.ascii	"TRG_DISABLED\000"
.LASF129:
	.ascii	"CONFIG_PCFUN\000"
.LASF120:
	.ascii	"DATA_FORMAT0\000"
.LASF121:
	.ascii	"DATA_FORMAT1\000"
.LASF84:
	.ascii	"TRG_LOW\000"
.LASF62:
	.ascii	"RXOVRN_BUF_ADDR\000"
.LASF177:
	.ascii	"/home/mr_halfword/workspace_v9/TMS570LC4357_GCC_hal"
	.ascii	"cogen/Debug\000"
.LASF30:
	.ascii	"GCR0\000"
.LASF31:
	.ascii	"GCR1\000"
.LASF118:
	.ascii	"mibspiPmode_t\000"
.LASF27:
	.ascii	"InitialValue\000"
.LASF140:
	.ascii	"CONFIG_LTGPEND\000"
.LASF92:
	.ascii	"TRG_GIOA4\000"
.LASF45:
	.ascii	"TGITENST\000"
.LASF32:
	.ascii	"INT0\000"
.LASF55:
	.ascii	"DMACOUNT\000"
.LASF127:
	.ascii	"CONFIG_INT0\000"
.LASF28:
	.ascii	"CurrentValue\000"
.LASF116:
	.ascii	"PMODE_4_DATALINE\000"
.LASF104:
	.ascii	"CS_NONE\000"
.LASF49:
	.ascii	"TGINTFLG\000"
.LASF61:
	.ascii	"UERRADDRTX\000"
.LASF97:
	.ascii	"TRG_HET1_10\000"
.LASF98:
	.ascii	"TRG_HET1_12\000"
.LASF173:
	.ascii	"mibspiOutofReset\000"
.LASF99:
	.ascii	"TRG_HET1_14\000"
.LASF100:
	.ascii	"TRG_HET1_16\000"
.LASF101:
	.ascii	"TRG_HET1_18\000"
.LASF77:
	.ascii	"mibspiRAM_t\000"
.LASF35:
	.ascii	"DELAY\000"
.LASF51:
	.ascii	"TICKCNT\000"
.LASF67:
	.ascii	"ECCDIAG_STAT\000"
.LASF20:
	.ascii	"float\000"
.LASF76:
	.ascii	"mibspiRamBase\000"
.LASF64:
	.ascii	"EXT_PRESCALE1\000"
.LASF65:
	.ascii	"EXT_PRESCALE2\000"
.LASF68:
	.ascii	"SBERRADDR1\000"
.LASF148:
	.ascii	"mibspi3GetConfigValue\000"
.LASF158:
	.ascii	"DFMT\000"
.LASF19:
	.ascii	"_Bool\000"
.LASF1:
	.ascii	"unsigned char\000"
.LASF40:
	.ascii	"INTVECT0\000"
.LASF41:
	.ascii	"INTVECT1\000"
.LASF2:
	.ascii	"short int\000"
.LASF50:
	.ascii	"rsvd1\000"
.LASF57:
	.ascii	"rsvd2\000"
.LASF42:
	.ascii	"rsvd3\000"
.LASF69:
	.ascii	"rsvd4\000"
.LASF105:
	.ascii	"CS_0\000"
.LASF106:
	.ascii	"CS_1\000"
.LASF107:
	.ascii	"CS_2\000"
.LASF108:
	.ascii	"CS_3\000"
.LASF109:
	.ascii	"CS_4\000"
.LASF110:
	.ascii	"CS_5\000"
.LASF111:
	.ascii	"CS_6\000"
.LASF112:
	.ascii	"CS_7\000"
.LASF63:
	.ascii	"IOLPKTSTCR\000"
.LASF178:
	.ascii	"mibspiInit\000"
.LASF119:
	.ascii	"mibspiDFMT\000"
.LASF58:
	.ascii	"PAR_ECC_CTRL\000"
.LASF168:
	.ascii	"mibspiFlags\000"
.LASF72:
	.ascii	"control\000"
.LASF14:
	.ascii	"uint32_t\000"
.LASF162:
	.ascii	"pmctrl_reg\000"
.LASF170:
	.ascii	"mibspiSetFunctional\000"
.LASF143:
	.ascii	"mibspi_config_reg_t\000"
.LASF83:
	.ascii	"TRG_HIGH\000"
.LASF159:
	.ascii	"mibspiDisableLoopback\000"
.LASF4:
	.ascii	"__uint16_t\000"
.LASF18:
	.ascii	"boolean\000"
.LASF151:
	.ascii	"mibspiDisableGroupNotification\000"
.LASF149:
	.ascii	"mibspi2GetConfigValue\000"
.LASF22:
	.ascii	"Digital_Lbk\000"
.LASF115:
	.ascii	"PMODE_2_DATALINE\000"
.LASF128:
	.ascii	"CONFIG_LVL\000"
.LASF122:
	.ascii	"DATA_FORMAT2\000"
.LASF123:
	.ascii	"DATA_FORMAT3\000"
.LASF114:
	.ascii	"PMODE_NORMAL\000"
.LASF124:
	.ascii	"mibspiDFMT_t\000"
.LASF163:
	.ascii	"status\000"
.LASF59:
	.ascii	"UERRSTAT\000"
.LASF54:
	.ascii	"DMACTRL\000"
.LASF25:
	.ascii	"loopBackType\000"
.LASF12:
	.ascii	"uint8_t\000"
.LASF75:
	.ascii	"mibspiBase\000"
.LASF74:
	.ascii	"flags\000"
.LASF165:
	.ascii	"mibspiIsTransferComplete\000"
.LASF26:
	.ascii	"config_value_type\000"
.LASF144:
	.ascii	"config_reg\000"
.LASF102:
	.ascii	"TRG_TICK\000"
.LASF134:
	.ascii	"CONFIG_DELAY\000"
.LASF78:
	.ascii	"triggerEvent\000"
.LASF167:
	.ascii	"start\000"
.LASF24:
	.ascii	"loopBackType_t\000"
.LASF36:
	.ascii	"FMT0\000"
.LASF37:
	.ascii	"FMT1\000"
.LASF38:
	.ascii	"FMT2\000"
.LASF39:
	.ascii	"FMT3\000"
	.ident	"GCC: (GNU Tools for Arm Embedded Processors 7-2017-q4-major) 7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204]"
