/* ============================================================================ */ /* Copyright (c) 2015, Texas Instruments Incorporated */ /* All rights reserved. */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* * Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* * Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in the */ /* documentation and/or other materials provided with the distribution. */ /* */ /* * Neither the name of Texas Instruments Incorporated nor the names of */ /* its contributors may be used to endorse or promote products derived */ /* from this software without specific prior written permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ /* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ /* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ============================================================================ */ /******************************************************************** * * Standard register and bit definitions for the Texas Instruments * MSP430 microcontroller. * * This file supports assembler and C development for * MSP430FR2033 devices. * * Texas Instruments, Version 1.1 * * Rev. 1.0, Setup * Rev. 1.1, replaced UCSSEL__ACLK with UCSSEL__MODCLK * ********************************************************************/ /*----------------------------------------------------------------------------*/ /* PERIPHERAL FILE MAP */ /*----------------------------------------------------------------------------*/ /* External references resolved by a device-specific linker command file */ //#define SFR_20BIT(address) extern volatile unsigned int address typedef void (* __SFR_FARPTR)(); /************************************************************ * STANDARD BITS ************************************************************/ /************************************************************ * STATUS REGISTER BITS ************************************************************/ /* Low Power Modes coded with Bits 4-7 in SR */ /* ============================================================================ */ /* Copyright (c) 2013, Texas Instruments Incorporated */ /* All rights reserved. */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* * Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* * Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in the */ /* documentation and/or other materials provided with the distribution. */ /* */ /* * Neither the name of Texas Instruments Incorporated nor the names of */ /* its contributors may be used to endorse or promote products derived */ /* from this software without specific prior written permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ /* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ /* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ============================================================================ */ /*----------------------------------------------------------------------------*/ /* INTRINSIC MAPPING FOR IAR V1.XX */ /*----------------------------------------------------------------------------*/ /*****************************************************************************/ /* INTRINSICS.H v4.4.5 */ /* */ /* Copyright (c) 2005-2015 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*---------------------------------------------------------------------------*/ /* Handle legacy conflicts */ /*---------------------------------------------------------------------------*/ /*****************************************************************************/ /* INTRINSICS_LEGACY_UNDEFS.H v4.4.5 */ /* */ /* Copyright (c) 2005-2015 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*---------------------------------------------------------------------------*/ /* Handle in430.h conflicts with legacy intrinsic names */ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /* General MSP Intrinsics */ /*---------------------------------------------------------------------------*/ void __no_operation(void); unsigned short __bic_SR_register (unsigned short mask); unsigned short __bic_SR_register_on_exit (unsigned short mask); unsigned short __bis_SR_register (unsigned short mask); unsigned short __bis_SR_register_on_exit (unsigned short mask); unsigned short __get_SR_register (void); unsigned short __get_SR_register_on_exit (void); unsigned short __get_SP_register(void); void __set_SP_register(unsigned short value); void __delay_cycles(unsigned long cycles); unsigned int __even_in_range(unsigned int val, unsigned int range); void __op_code(unsigned short op); /*---------------------------------------------------------------------------*/ /* General MSP Macros */ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /* MSP430/430X Intrinsics */ /*---------------------------------------------------------------------------*/ void __disable_interrupt(void); void __enable_interrupt(void); void __set_interrupt_state(unsigned short state); unsigned short __get_R4_register(void); void __set_R4_register(unsigned short value); unsigned short __get_R5_register(void); void __set_R5_register(unsigned short value); unsigned short __bcd_add_short(unsigned short, unsigned short); unsigned long __bcd_add_long(unsigned long, unsigned long); /*---------------------------------------------------------------------------*/ /* MSP430/430X Macros */ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /* MSP430X Intrinsics */ /*---------------------------------------------------------------------------*/ void __data16_write_addr(unsigned short, unsigned long); unsigned long __data16_read_addr(unsigned short); void __data20_write_char(unsigned long, unsigned char); void __data20_write_short(unsigned long, unsigned short); void __data20_write_long(unsigned long, unsigned long); unsigned char __data20_read_char(unsigned long); unsigned short __data20_read_short(unsigned long); unsigned long __data20_read_long(unsigned long); /*---------------------------------------------------------------------------*/ /* Legacy Macros */ /*---------------------------------------------------------------------------*/ /************************************************************ * CPU ************************************************************/ /************************************************************ * PERIPHERAL FILE MAP ************************************************************/ /************************************************************ * ADC ************************************************************/ extern volatile unsigned int ADCCTL0; /* ADC Control 0 */ extern volatile unsigned char ADCCTL0_L; /* ADC Control 0 */ extern volatile unsigned char ADCCTL0_H; /* ADC Control 0 */ extern volatile unsigned int ADCCTL1; /* ADC Control 1 */ extern volatile unsigned char ADCCTL1_L; /* ADC Control 1 */ extern volatile unsigned char ADCCTL1_H; /* ADC Control 1 */ extern volatile unsigned int ADCCTL2; /* ADC Control 2 */ extern volatile unsigned char ADCCTL2_L; /* ADC Control 2 */ extern volatile unsigned char ADCCTL2_H; /* ADC Control 2 */ extern volatile unsigned int ADCLO; /* ADC Window Comparator High Threshold */ extern volatile unsigned char ADCLO_L; /* ADC Window Comparator High Threshold */ extern volatile unsigned char ADCLO_H; /* ADC Window Comparator High Threshold */ extern volatile unsigned int ADCHI; /* ADC Window Comparator High Threshold */ extern volatile unsigned char ADCHI_L; /* ADC Window Comparator High Threshold */ extern volatile unsigned char ADCHI_H; /* ADC Window Comparator High Threshold */ extern volatile unsigned int ADCMCTL0; /* ADC Memory Control 0 */ extern volatile unsigned char ADCMCTL0_L; /* ADC Memory Control 0 */ extern volatile unsigned char ADCMCTL0_H; /* ADC Memory Control 0 */ extern volatile unsigned int ADCMEM0; /* ADC Conversion Memory 0 */ extern volatile unsigned char ADCMEM0_L; /* ADC Conversion Memory 0 */ extern volatile unsigned char ADCMEM0_H; /* ADC Conversion Memory 0 */ extern volatile unsigned int ADCIE; /* ADC Interrupt Enable */ extern volatile unsigned char ADCIE_L; /* ADC Interrupt Enable */ extern volatile unsigned char ADCIE_H; /* ADC Interrupt Enable */ extern volatile unsigned int ADCIFG; /* ADC Interrupt Flag */ extern volatile unsigned char ADCIFG_L; /* ADC Interrupt Flag */ extern volatile unsigned char ADCIFG_H; /* ADC Interrupt Flag */ extern volatile unsigned int ADCIV; /* ADC Interrupt Vector Word */ extern volatile unsigned char ADCIV_L; /* ADC Interrupt Vector Word */ extern volatile unsigned char ADCIV_H; /* ADC Interrupt Vector Word */ /* ADCCTL0 Control Bits */ /* ADCCTL0 Control Bits */ /* ADCCTL0 Control Bits */ /* ADCCTL1 Control Bits */ /* ADCCTL1 Control Bits */ /* ADCCTL1 Control Bits */ /* ADCCTL2 Control Bits */ /* ADCCTL2 Control Bits */ /* ADCCTL2 Control Bits */ /* ADCMCTL0 Control Bits */ /* ADCMCTL0 Control Bits */ /* ADCIE Interrupt Enable Bits */ /* ADCIE Interrupt Enable Bits */ /* ADCIFG Interrupt Flag Bits */ /* ADCIFG Interrupt Flag Bits */ /* ADCIV Definitions */ /************************************************************* * Backup RAM Module *************************************************************/ extern volatile unsigned int BAKMEM0; /* Battery Backup Memory 0 */ extern volatile unsigned char BAKMEM0_L; /* Battery Backup Memory 0 */ extern volatile unsigned char BAKMEM0_H; /* Battery Backup Memory 0 */ extern volatile unsigned int BAKMEM1; /* Battery Backup Memory 1 */ extern volatile unsigned char BAKMEM1_L; /* Battery Backup Memory 1 */ extern volatile unsigned char BAKMEM1_H; /* Battery Backup Memory 1 */ extern volatile unsigned int BAKMEM2; /* Battery Backup Memory 2 */ extern volatile unsigned char BAKMEM2_L; /* Battery Backup Memory 2 */ extern volatile unsigned char BAKMEM2_H; /* Battery Backup Memory 2 */ extern volatile unsigned int BAKMEM3; /* Battery Backup Memory 3 */ extern volatile unsigned char BAKMEM3_L; /* Battery Backup Memory 3 */ extern volatile unsigned char BAKMEM3_H; /* Battery Backup Memory 3 */ extern volatile unsigned int BAKMEM4; /* Battery Backup Memory 4 */ extern volatile unsigned char BAKMEM4_L; /* Battery Backup Memory 4 */ extern volatile unsigned char BAKMEM4_H; /* Battery Backup Memory 4 */ extern volatile unsigned int BAKMEM5; /* Battery Backup Memory 5 */ extern volatile unsigned char BAKMEM5_L; /* Battery Backup Memory 5 */ extern volatile unsigned char BAKMEM5_H; /* Battery Backup Memory 5 */ extern volatile unsigned int BAKMEM6; /* Battery Backup Memory 6 */ extern volatile unsigned char BAKMEM6_L; /* Battery Backup Memory 6 */ extern volatile unsigned char BAKMEM6_H; /* Battery Backup Memory 6 */ extern volatile unsigned int BAKMEM7; /* Battery Backup Memory 7 */ extern volatile unsigned char BAKMEM7_L; /* Battery Backup Memory 7 */ extern volatile unsigned char BAKMEM7_H; /* Battery Backup Memory 7 */ extern volatile unsigned int BAKMEM8; /* Battery Backup Memory 8 */ extern volatile unsigned char BAKMEM8_L; /* Battery Backup Memory 8 */ extern volatile unsigned char BAKMEM8_H; /* Battery Backup Memory 8 */ extern volatile unsigned int BAKMEM9; /* Battery Backup Memory 9 */ extern volatile unsigned char BAKMEM9_L; /* Battery Backup Memory 9 */ extern volatile unsigned char BAKMEM9_H; /* Battery Backup Memory 9 */ extern volatile unsigned int BAKMEM10; /* Battery Backup Memory 10 */ extern volatile unsigned char BAKMEM10_L; /* Battery Backup Memory 10 */ extern volatile unsigned char BAKMEM10_H; /* Battery Backup Memory 10 */ extern volatile unsigned int BAKMEM11; /* Battery Backup Memory 11 */ extern volatile unsigned char BAKMEM11_L; /* Battery Backup Memory 11 */ extern volatile unsigned char BAKMEM11_H; /* Battery Backup Memory 11 */ extern volatile unsigned int BAKMEM12; /* Battery Backup Memory 12 */ extern volatile unsigned char BAKMEM12_L; /* Battery Backup Memory 12 */ extern volatile unsigned char BAKMEM12_H; /* Battery Backup Memory 12 */ extern volatile unsigned int BAKMEM13; /* Battery Backup Memory 13 */ extern volatile unsigned char BAKMEM13_L; /* Battery Backup Memory 13 */ extern volatile unsigned char BAKMEM13_H; /* Battery Backup Memory 13 */ extern volatile unsigned int BAKMEM14; /* Battery Backup Memory 14 */ extern volatile unsigned char BAKMEM14_L; /* Battery Backup Memory 14 */ extern volatile unsigned char BAKMEM14_H; /* Battery Backup Memory 14 */ extern volatile unsigned int BAKMEM15; /* Battery Backup Memory 15 */ extern volatile unsigned char BAKMEM15_L; /* Battery Backup Memory 15 */ extern volatile unsigned char BAKMEM15_H; /* Battery Backup Memory 15 */ /************************************************************ * Capacitive_Touch_IO 0 ************************************************************/ extern volatile unsigned int CAPTIO0CTL; /* Capacitive_Touch_IO 0 control register */ extern volatile unsigned char CAPTIO0CTL_L; /* Capacitive_Touch_IO 0 control register */ extern volatile unsigned char CAPTIO0CTL_H; /* Capacitive_Touch_IO 0 control register */ /* CAPTIOxCTL Control Bits */ /* CAPTIOxCTL Control Bits */ /* CAPTIOxCTL Control Bits */ /* Legacy defines */ /************************************************************* * CRC Module *************************************************************/ extern volatile unsigned int CRCDI; /* CRC Data In Register */ extern volatile unsigned char CRCDI_L; /* CRC Data In Register */ extern volatile unsigned char CRCDI_H; /* CRC Data In Register */ extern volatile unsigned int CRCDIRB; /* CRC data in reverse byte Register */ extern volatile unsigned char CRCDIRB_L; /* CRC data in reverse byte Register */ extern volatile unsigned char CRCDIRB_H; /* CRC data in reverse byte Register */ extern volatile unsigned int CRCINIRES; /* CRC Initialisation Register and Result Register */ extern volatile unsigned char CRCINIRES_L; /* CRC Initialisation Register and Result Register */ extern volatile unsigned char CRCINIRES_H; /* CRC Initialisation Register and Result Register */ extern volatile unsigned int CRCRESR; /* CRC reverse result Register */ extern volatile unsigned char CRCRESR_L; /* CRC reverse result Register */ extern volatile unsigned char CRCRESR_H; /* CRC reverse result Register */ /************************************************************ * CLOCK SYSTEM CONTROL ************************************************************/ extern volatile unsigned int CSCTL0; /* CS Control Register 0 */ extern volatile unsigned char CSCTL0_L; /* CS Control Register 0 */ extern volatile unsigned char CSCTL0_H; /* CS Control Register 0 */ extern volatile unsigned int CSCTL1; /* CS Control Register 1 */ extern volatile unsigned char CSCTL1_L; /* CS Control Register 1 */ extern volatile unsigned char CSCTL1_H; /* CS Control Register 1 */ extern volatile unsigned int CSCTL2; /* CS Control Register 2 */ extern volatile unsigned char CSCTL2_L; /* CS Control Register 2 */ extern volatile unsigned char CSCTL2_H; /* CS Control Register 2 */ extern volatile unsigned int CSCTL3; /* CS Control Register 3 */ extern volatile unsigned char CSCTL3_L; /* CS Control Register 3 */ extern volatile unsigned char CSCTL3_H; /* CS Control Register 3 */ extern volatile unsigned int CSCTL4; /* CS Control Register 4 */ extern volatile unsigned char CSCTL4_L; /* CS Control Register 4 */ extern volatile unsigned char CSCTL4_H; /* CS Control Register 4 */ extern volatile unsigned int CSCTL5; /* CS Control Register 5 */ extern volatile unsigned char CSCTL5_L; /* CS Control Register 5 */ extern volatile unsigned char CSCTL5_H; /* CS Control Register 5 */ extern volatile unsigned int CSCTL6; /* CS Control Register 6 */ extern volatile unsigned char CSCTL6_L; /* CS Control Register 6 */ extern volatile unsigned char CSCTL6_H; /* CS Control Register 6 */ extern volatile unsigned int CSCTL7; /* CS Control Register 7 */ extern volatile unsigned char CSCTL7_L; /* CS Control Register 7 */ extern volatile unsigned char CSCTL7_H; /* CS Control Register 7 */ extern volatile unsigned int CSCTL8; /* CS Control Register 8 */ extern volatile unsigned char CSCTL8_L; /* CS Control Register 8 */ extern volatile unsigned char CSCTL8_H; /* CS Control Register 8 */ /* CSCTL0 Control Bits */ /* CSCTL0 Control Bits */ /* CSCTL0 Control Bits */ /* CSCTL1 Control Bits */ /* CSCTL1 Control Bits */ /* CSCTL2 Control Bits */ /* CSCTL2 Control Bits */ /* CSCTL2 Control Bits */ /* CSCTL3 Control Bits */ /* CSCTL3 Control Bits */ /* CSCTL4 Control Bits */ /* CSCTL4 Control Bits */ /* CSCTL4 Control Bits */ /* CSCTL5 Control Bits */ /* CSCTL5 Control Bits */ /* CSCTL5 Control Bits */ /* CSCTL6 Control Bits */ /* CSCTL6 Control Bits */ /* CSCTL7 Control Bits */ /* CSCTL7 Control Bits */ /* CSCTL7 Control Bits */ /* CSCTL8 Control Bits */ /* CSCTL8 Control Bits */ /************************************************************* * FRAM Memory *************************************************************/ extern volatile unsigned int FRCTL0; /* FRAM Controller Control 0 */ extern volatile unsigned char FRCTL0_L; /* FRAM Controller Control 0 */ extern volatile unsigned char FRCTL0_H; /* FRAM Controller Control 0 */ extern volatile unsigned int GCCTL0; /* General Control 0 */ extern volatile unsigned char GCCTL0_L; /* General Control 0 */ extern volatile unsigned char GCCTL0_H; /* General Control 0 */ extern volatile unsigned int GCCTL1; /* General Control 1 */ extern volatile unsigned char GCCTL1_L; /* General Control 1 */ extern volatile unsigned char GCCTL1_H; /* General Control 1 */ /* FRCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0002) /* RESERVED */ //#define RESERVED (0x0004) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ /* FRCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0002) /* RESERVED */ //#define RESERVED (0x0004) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ /* GCCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0010) /* RESERVED */ /* GCCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0010) /* RESERVED */ /* GCCTL1 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ /* GCCTL1 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ /************************************************************ * PMM - Power Management System for FR2xx/FR4xx ************************************************************/ extern volatile unsigned int PMMCTL0; /* PMM Control 0 */ extern volatile unsigned char PMMCTL0_L; /* PMM Control 0 */ extern volatile unsigned char PMMCTL0_H; /* PMM Control 0 */ extern volatile unsigned int PMMCTL1; /* PMM Control 1 */ extern volatile unsigned char PMMCTL1_L; /* PMM Control 1 */ extern volatile unsigned char PMMCTL1_H; /* PMM Control 1 */ extern volatile unsigned int PMMCTL2; /* PMM Control 2 */ extern volatile unsigned char PMMCTL2_L; /* PMM Control 2 */ extern volatile unsigned char PMMCTL2_H; /* PMM Control 2 */ extern volatile unsigned int PMMIFG; /* PMM Interrupt Flag */ extern volatile unsigned char PMMIFG_L; /* PMM Interrupt Flag */ extern volatile unsigned char PMMIFG_H; /* PMM Interrupt Flag */ extern volatile unsigned int PMMIE; /* PMM Interrupt Enable */ extern volatile unsigned char PMMIE_L; /* PMM Interrupt Enable */ extern volatile unsigned char PMMIE_H; /* PMM Interrupt Enable */ extern volatile unsigned int PM5CTL0; /* PMM Power Mode 5 Control Register 0 */ extern volatile unsigned char PM5CTL0_L; /* PMM Power Mode 5 Control Register 0 */ extern volatile unsigned char PM5CTL0_H; /* PMM Power Mode 5 Control Register 0 */ /* PMMCTL0 Control Bits */ /* PMMCTL0 Control Bits */ /* PMMCTL1 Control Bits */ /* PMMCTL2 Control Bits */ /* PMMCTL2 Control Bits */ /* PMMCTL2 Control Bits */ /* PMMIFG Control Bits */ /* PMMIFG Control Bits */ /* PMMIE Control Bits */ /* PM5CTL0 Power Mode 5 Control Bits */ /* PM5CTL0 Power Mode 5 Control Bits */ /************************************************************ * DIGITAL I/O Port1/2 Pull up / Pull down Resistors ************************************************************/ extern volatile unsigned int PAIN; /* Port A Input */ extern volatile unsigned char PAIN_L; /* Port A Input */ extern volatile unsigned char PAIN_H; /* Port A Input */ extern volatile unsigned int PAOUT; /* Port A Output */ extern volatile unsigned char PAOUT_L; /* Port A Output */ extern volatile unsigned char PAOUT_H; /* Port A Output */ extern volatile unsigned int PADIR; /* Port A Direction */ extern volatile unsigned char PADIR_L; /* Port A Direction */ extern volatile unsigned char PADIR_H; /* Port A Direction */ extern volatile unsigned int PAREN; /* Port A Resistor Enable */ extern volatile unsigned char PAREN_L; /* Port A Resistor Enable */ extern volatile unsigned char PAREN_H; /* Port A Resistor Enable */ extern volatile unsigned int PASEL0; /* Port A Selection 0 */ extern volatile unsigned char PASEL0_L; /* Port A Selection 0 */ extern volatile unsigned char PASEL0_H; /* Port A Selection 0 */ extern volatile unsigned int PAIES; /* Port A Interrupt Edge Select */ extern volatile unsigned char PAIES_L; /* Port A Interrupt Edge Select */ extern volatile unsigned char PAIES_H; /* Port A Interrupt Edge Select */ extern volatile unsigned int PAIE; /* Port A Interrupt Enable */ extern volatile unsigned char PAIE_L; /* Port A Interrupt Enable */ extern volatile unsigned char PAIE_H; /* Port A Interrupt Enable */ extern volatile unsigned int PAIFG; /* Port A Interrupt Flag */ extern volatile unsigned char PAIFG_L; /* Port A Interrupt Flag */ extern volatile unsigned char PAIFG_H; /* Port A Interrupt Flag */ extern volatile unsigned int P1IV; /* Port 1 Interrupt Vector Word */ extern volatile unsigned int P2IV; /* Port 2 Interrupt Vector Word */ //Definitions for P1IV //Definitions for P2IV /************************************************************ * DIGITAL I/O Port3/4 Pull up / Pull down Resistors ************************************************************/ extern volatile unsigned int PBIN; /* Port B Input */ extern volatile unsigned char PBIN_L; /* Port B Input */ extern volatile unsigned char PBIN_H; /* Port B Input */ extern volatile unsigned int PBOUT; /* Port B Output */ extern volatile unsigned char PBOUT_L; /* Port B Output */ extern volatile unsigned char PBOUT_H; /* Port B Output */ extern volatile unsigned int PBDIR; /* Port B Direction */ extern volatile unsigned char PBDIR_L; /* Port B Direction */ extern volatile unsigned char PBDIR_H; /* Port B Direction */ extern volatile unsigned int PBREN; /* Port B Resistor Enable */ extern volatile unsigned char PBREN_L; /* Port B Resistor Enable */ extern volatile unsigned char PBREN_H; /* Port B Resistor Enable */ extern volatile unsigned int PBSEL0; /* Port B Selection 0 */ extern volatile unsigned char PBSEL0_L; /* Port B Selection 0 */ extern volatile unsigned char PBSEL0_H; /* Port B Selection 0 */ /************************************************************ * DIGITAL I/O Port5/6 Pull up / Pull down Resistors ************************************************************/ extern volatile unsigned int PCIN; /* Port C Input */ extern volatile unsigned char PCIN_L; /* Port C Input */ extern volatile unsigned char PCIN_H; /* Port C Input */ extern volatile unsigned int PCOUT; /* Port C Output */ extern volatile unsigned char PCOUT_L; /* Port C Output */ extern volatile unsigned char PCOUT_H; /* Port C Output */ extern volatile unsigned int PCDIR; /* Port C Direction */ extern volatile unsigned char PCDIR_L; /* Port C Direction */ extern volatile unsigned char PCDIR_H; /* Port C Direction */ extern volatile unsigned int PCREN; /* Port C Resistor Enable */ extern volatile unsigned char PCREN_L; /* Port C Resistor Enable */ extern volatile unsigned char PCREN_H; /* Port C Resistor Enable */ extern volatile unsigned int PCSEL0; /* Port C Selection 0 */ extern volatile unsigned char PCSEL0_L; /* Port C Selection 0 */ extern volatile unsigned char PCSEL0_H; /* Port C Selection 0 */ /************************************************************ * DIGITAL I/O Port7/8 Pull up / Pull down Resistors ************************************************************/ extern volatile unsigned int PDIN; /* Port D Input */ extern volatile unsigned char PDIN_L; /* Port D Input */ extern volatile unsigned char PDIN_H; /* Port D Input */ extern volatile unsigned int PDOUT; /* Port D Output */ extern volatile unsigned char PDOUT_L; /* Port D Output */ extern volatile unsigned char PDOUT_H; /* Port D Output */ extern volatile unsigned int PDDIR; /* Port D Direction */ extern volatile unsigned char PDDIR_L; /* Port D Direction */ extern volatile unsigned char PDDIR_H; /* Port D Direction */ extern volatile unsigned int PDREN; /* Port D Resistor Enable */ extern volatile unsigned char PDREN_L; /* Port D Resistor Enable */ extern volatile unsigned char PDREN_H; /* Port D Resistor Enable */ extern volatile unsigned int PDSEL0; /* Port D Selection 0 */ extern volatile unsigned char PDSEL0_L; /* Port D Selection 0 */ extern volatile unsigned char PDSEL0_H; /* Port D Selection 0 */ /************************************************************ * Real-Time Clock (RTC) Counter ************************************************************/ extern volatile unsigned int RTCCTL; /* RTC control Register */ extern volatile unsigned char RTCCTL_L; /* RTC control Register */ extern volatile unsigned char RTCCTL_H; /* RTC control Register */ extern volatile unsigned int RTCIV; /* RTC interrupt vector */ extern volatile unsigned char RTCIV_L; /* RTC interrupt vector */ extern volatile unsigned char RTCIV_H; /* RTC interrupt vector */ extern volatile unsigned int RTCMOD; /* RTC moduloRegister */ extern volatile unsigned char RTCMOD_L; /* RTC moduloRegister */ extern volatile unsigned char RTCMOD_H; /* RTC moduloRegister */ extern volatile unsigned int RTCCNT; /* RTC counter Register */ extern volatile unsigned char RTCCNT_L; /* RTC counter Register */ extern volatile unsigned char RTCCNT_H; /* RTC counter Register */ /* RTC control Register */ /* RTC control Register */ /* RTC control Register */ /* RTCIV Definitions */ /************************************************************ * SFR - Special Function Register Module ************************************************************/ extern volatile unsigned int SFRIE1; /* Interrupt Enable 1 */ extern volatile unsigned char SFRIE1_L; /* Interrupt Enable 1 */ extern volatile unsigned char SFRIE1_H; /* Interrupt Enable 1 */ /* SFRIE1 Control Bits */ //#define Reserved (0x0004) //#define Reserved (0x0004) extern volatile unsigned int SFRIFG1; /* Interrupt Flag 1 */ extern volatile unsigned char SFRIFG1_L; /* Interrupt Flag 1 */ extern volatile unsigned char SFRIFG1_H; /* Interrupt Flag 1 */ /* SFRIFG1 Control Bits */ //#define Reserved (0x0004) //#define Reserved (0x0020) //#define Reserved (0x0004) //#define Reserved (0x0020) extern volatile unsigned int SFRRPCR; /* RESET Pin Control Register */ extern volatile unsigned char SFRRPCR_L; /* RESET Pin Control Register */ extern volatile unsigned char SFRRPCR_H; /* RESET Pin Control Register */ /* SFRRPCR Control Bits */ /************************************************************ * SYS - System Module ************************************************************/ extern volatile unsigned int SYSCTL; /* System control */ extern volatile unsigned char SYSCTL_L; /* System control */ extern volatile unsigned char SYSCTL_H; /* System control */ extern volatile unsigned int SYSBSLC; /* Boot strap configuration area */ extern volatile unsigned char SYSBSLC_L; /* Boot strap configuration area */ extern volatile unsigned char SYSBSLC_H; /* Boot strap configuration area */ extern volatile unsigned int SYSJMBC; /* JTAG mailbox control */ extern volatile unsigned char SYSJMBC_L; /* JTAG mailbox control */ extern volatile unsigned char SYSJMBC_H; /* JTAG mailbox control */ extern volatile unsigned int SYSJMBI0; /* JTAG mailbox input 0 */ extern volatile unsigned char SYSJMBI0_L; /* JTAG mailbox input 0 */ extern volatile unsigned char SYSJMBI0_H; /* JTAG mailbox input 0 */ extern volatile unsigned int SYSJMBI1; /* JTAG mailbox input 1 */ extern volatile unsigned char SYSJMBI1_L; /* JTAG mailbox input 1 */ extern volatile unsigned char SYSJMBI1_H; /* JTAG mailbox input 1 */ extern volatile unsigned int SYSJMBO0; /* JTAG mailbox output 0 */ extern volatile unsigned char SYSJMBO0_L; /* JTAG mailbox output 0 */ extern volatile unsigned char SYSJMBO0_H; /* JTAG mailbox output 0 */ extern volatile unsigned int SYSJMBO1; /* JTAG mailbox output 1 */ extern volatile unsigned char SYSJMBO1_L; /* JTAG mailbox output 1 */ extern volatile unsigned char SYSJMBO1_H; /* JTAG mailbox output 1 */ extern volatile unsigned int SYSBERRIV; /* Bus Error vector generator */ extern volatile unsigned char SYSBERRIV_L; /* Bus Error vector generator */ extern volatile unsigned char SYSBERRIV_H; /* Bus Error vector generator */ extern volatile unsigned int SYSUNIV; /* User NMI vector generator */ extern volatile unsigned char SYSUNIV_L; /* User NMI vector generator */ extern volatile unsigned char SYSUNIV_H; /* User NMI vector generator */ extern volatile unsigned int SYSSNIV; /* System NMI vector generator */ extern volatile unsigned char SYSSNIV_L; /* System NMI vector generator */ extern volatile unsigned char SYSSNIV_H; /* System NMI vector generator */ extern volatile unsigned int SYSRSTIV; /* Reset vector generator */ extern volatile unsigned char SYSRSTIV_L; /* Reset vector generator */ extern volatile unsigned char SYSRSTIV_H; /* Reset vector generator */ extern volatile unsigned int SYSCFG0; /* System Configuration 0 */ extern volatile unsigned char SYSCFG0_L; /* System Configuration 0 */ extern volatile unsigned char SYSCFG0_H; /* System Configuration 0 */ extern volatile unsigned int SYSCFG1; /* System Configuration 1 */ extern volatile unsigned char SYSCFG1_L; /* System Configuration 1 */ extern volatile unsigned char SYSCFG1_H; /* System Configuration 1 */ extern volatile unsigned int SYSCFG2; /* System Configuration 2 */ extern volatile unsigned char SYSCFG2_L; /* System Configuration 2 */ extern volatile unsigned char SYSCFG2_H; /* System Configuration 2 */ /* SYSCTL Control Bits */ //#define RESERVED (0x0002) /* SYS - Reserved */ //#define RESERVED (0x0008) /* SYS - Reserved */ //#define RESERVED (0x0040) /* SYS - Reserved */ //#define RESERVED (0x0080) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ //#define RESERVED (0x4000) /* SYS - Reserved */ //#define RESERVED (0x8000) /* SYS - Reserved */ /* SYSCTL Control Bits */ //#define RESERVED (0x0002) /* SYS - Reserved */ //#define RESERVED (0x0008) /* SYS - Reserved */ //#define RESERVED (0x0040) /* SYS - Reserved */ //#define RESERVED (0x0080) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ //#define RESERVED (0x4000) /* SYS - Reserved */ //#define RESERVED (0x8000) /* SYS - Reserved */ /* SYSBSLC Control Bits */ //#define RESERVED (0x0008) /* SYS - Reserved */ //#define RESERVED (0x0010) /* SYS - Reserved */ //#define RESERVED (0x0020) /* SYS - Reserved */ //#define RESERVED (0x0040) /* SYS - Reserved */ //#define RESERVED (0x0080) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ /* SYSBSLC Control Bits */ //#define RESERVED (0x0008) /* SYS - Reserved */ //#define RESERVED (0x0010) /* SYS - Reserved */ //#define RESERVED (0x0020) /* SYS - Reserved */ //#define RESERVED (0x0040) /* SYS - Reserved */ //#define RESERVED (0x0080) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ /* SYSBSLC Control Bits */ //#define RESERVED (0x0008) /* SYS - Reserved */ //#define RESERVED (0x0010) /* SYS - Reserved */ //#define RESERVED (0x0020) /* SYS - Reserved */ //#define RESERVED (0x0040) /* SYS - Reserved */ //#define RESERVED (0x0080) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ /* SYSJMBC Control Bits */ //#define RESERVED (0x0020) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ //#define RESERVED (0x4000) /* SYS - Reserved */ //#define RESERVED (0x8000) /* SYS - Reserved */ /* SYSJMBC Control Bits */ //#define RESERVED (0x0020) /* SYS - Reserved */ //#define RESERVED (0x0100) /* SYS - Reserved */ //#define RESERVED (0x0200) /* SYS - Reserved */ //#define RESERVED (0x0400) /* SYS - Reserved */ //#define RESERVED (0x0800) /* SYS - Reserved */ //#define RESERVED (0x1000) /* SYS - Reserved */ //#define RESERVED (0x2000) /* SYS - Reserved */ //#define RESERVED (0x4000) /* SYS - Reserved */ //#define RESERVED (0x8000) /* SYS - Reserved */ /* SYSCFG0 Control Bits */ /* SYSCFG0 Control Bits */ /* SYSCFG1 Control Bits */ /* SYSCFG1 Control Bits */ /* SYSCFG2 Control Bits */ /* SYSCFG2 Control Bits */ /* SYSCFG2 Control Bits */ /* SYSUNIV Definitions */ /* SYSSNIV Definitions */ /* SYSRSTIV Definitions */ /************************************************************ * Timer0_A3 ************************************************************/ extern volatile unsigned int TA0CTL; /* Timer0_A3 Control */ extern volatile unsigned int TA0CCTL0; /* Timer0_A3 Capture/Compare Control 0 */ extern volatile unsigned int TA0CCTL1; /* Timer0_A3 Capture/Compare Control 1 */ extern volatile unsigned int TA0CCTL2; /* Timer0_A3 Capture/Compare Control 2 */ extern volatile unsigned int TA0R; /* Timer0_A3 */ extern volatile unsigned int TA0CCR0; /* Timer0_A3 Capture/Compare 0 */ extern volatile unsigned int TA0CCR1; /* Timer0_A3 Capture/Compare 1 */ extern volatile unsigned int TA0CCR2; /* Timer0_A3 Capture/Compare 2 */ extern volatile unsigned int TA0IV; /* Timer0_A3 Interrupt Vector Word */ extern volatile unsigned int TA0EX0; /* Timer0_A3 Expansion Register 0 */ /* TAxCTL Control Bits */ /* TAxCCTLx Control Bits */ /* TAxEX0 Control Bits */ /* T0A3IV Definitions */ /* Legacy Defines */ /************************************************************ * Timer1_A3 ************************************************************/ extern volatile unsigned int TA1CTL; /* Timer1_A3 Control */ extern volatile unsigned int TA1CCTL0; /* Timer1_A3 Capture/Compare Control 0 */ extern volatile unsigned int TA1CCTL1; /* Timer1_A3 Capture/Compare Control 1 */ extern volatile unsigned int TA1CCTL2; /* Timer1_A3 Capture/Compare Control 2 */ extern volatile unsigned int TA1R; /* Timer1_A3 */ extern volatile unsigned int TA1CCR0; /* Timer1_A3 Capture/Compare 0 */ extern volatile unsigned int TA1CCR1; /* Timer1_A3 Capture/Compare 1 */ extern volatile unsigned int TA1CCR2; /* Timer1_A3 Capture/Compare 2 */ extern volatile unsigned int TA1IV; /* Timer1_A3 Interrupt Vector Word */ extern volatile unsigned int TA1EX0; /* Timer1_A3 Expansion Register 0 */ /* Bits are already defined within the Timer0_Ax */ /* TA1IV Definitions */ /* Legacy Defines */ /************************************************************ * USCI A0 ************************************************************/ extern volatile unsigned int UCA0CTLW0; /* USCI A0 Control Word Register 0 */ extern volatile unsigned char UCA0CTLW0_L; /* USCI A0 Control Word Register 0 */ extern volatile unsigned char UCA0CTLW0_H; /* USCI A0 Control Word Register 0 */ extern volatile unsigned int UCA0CTLW1; /* USCI A0 Control Word Register 1 */ extern volatile unsigned char UCA0CTLW1_L; /* USCI A0 Control Word Register 1 */ extern volatile unsigned char UCA0CTLW1_H; /* USCI A0 Control Word Register 1 */ extern volatile unsigned int UCA0BRW; /* USCI A0 Baud Word Rate 0 */ extern volatile unsigned char UCA0BRW_L; /* USCI A0 Baud Word Rate 0 */ extern volatile unsigned char UCA0BRW_H; /* USCI A0 Baud Word Rate 0 */ extern volatile unsigned int UCA0MCTLW; /* USCI A0 Modulation Control */ extern volatile unsigned char UCA0MCTLW_L; /* USCI A0 Modulation Control */ extern volatile unsigned char UCA0MCTLW_H; /* USCI A0 Modulation Control */ extern volatile unsigned char UCA0STATW; /* USCI A0 Status Register */ extern volatile unsigned int UCA0RXBUF; /* USCI A0 Receive Buffer */ extern volatile unsigned char UCA0RXBUF_L; /* USCI A0 Receive Buffer */ extern volatile unsigned char UCA0RXBUF_H; /* USCI A0 Receive Buffer */ extern volatile unsigned int UCA0TXBUF; /* USCI A0 Transmit Buffer */ extern volatile unsigned char UCA0TXBUF_L; /* USCI A0 Transmit Buffer */ extern volatile unsigned char UCA0TXBUF_H; /* USCI A0 Transmit Buffer */ extern volatile unsigned char UCA0ABCTL; /* USCI A0 LIN Control */ extern volatile unsigned int UCA0IRCTL; /* USCI A0 IrDA Transmit Control */ extern volatile unsigned char UCA0IRCTL_L; /* USCI A0 IrDA Transmit Control */ extern volatile unsigned char UCA0IRCTL_H; /* USCI A0 IrDA Transmit Control */ extern volatile unsigned int UCA0IE; /* USCI A0 Interrupt Enable Register */ extern volatile unsigned char UCA0IE_L; /* USCI A0 Interrupt Enable Register */ extern volatile unsigned char UCA0IE_H; /* USCI A0 Interrupt Enable Register */ extern volatile unsigned int UCA0IFG; /* USCI A0 Interrupt Flags Register */ extern volatile unsigned char UCA0IFG_L; /* USCI A0 Interrupt Flags Register */ extern volatile unsigned char UCA0IFG_H; /* USCI A0 Interrupt Flags Register */ extern volatile unsigned int UCA0IV; /* USCI A0 Interrupt Vector Register */ /************************************************************ * USCI B0 ************************************************************/ extern volatile unsigned int UCB0CTLW0; /* USCI B0 Control Word Register 0 */ extern volatile unsigned char UCB0CTLW0_L; /* USCI B0 Control Word Register 0 */ extern volatile unsigned char UCB0CTLW0_H; /* USCI B0 Control Word Register 0 */ extern volatile unsigned int UCB0CTLW1; /* USCI B0 Control Word Register 1 */ extern volatile unsigned char UCB0CTLW1_L; /* USCI B0 Control Word Register 1 */ extern volatile unsigned char UCB0CTLW1_H; /* USCI B0 Control Word Register 1 */ extern volatile unsigned int UCB0BRW; /* USCI B0 Baud Word Rate 0 */ extern volatile unsigned char UCB0BRW_L; /* USCI B0 Baud Word Rate 0 */ extern volatile unsigned char UCB0BRW_H; /* USCI B0 Baud Word Rate 0 */ extern volatile unsigned int UCB0STATW; /* USCI B0 Status Word Register */ extern volatile unsigned char UCB0STATW_L; /* USCI B0 Status Word Register */ extern volatile unsigned char UCB0STATW_H; /* USCI B0 Status Word Register */ extern volatile unsigned int UCB0TBCNT; /* USCI B0 Byte Counter Threshold Register */ extern volatile unsigned char UCB0TBCNT_L; /* USCI B0 Byte Counter Threshold Register */ extern volatile unsigned char UCB0TBCNT_H; /* USCI B0 Byte Counter Threshold Register */ extern volatile unsigned int UCB0RXBUF; /* USCI B0 Receive Buffer */ extern volatile unsigned char UCB0RXBUF_L; /* USCI B0 Receive Buffer */ extern volatile unsigned char UCB0RXBUF_H; /* USCI B0 Receive Buffer */ extern volatile unsigned int UCB0TXBUF; /* USCI B0 Transmit Buffer */ extern volatile unsigned char UCB0TXBUF_L; /* USCI B0 Transmit Buffer */ extern volatile unsigned char UCB0TXBUF_H; /* USCI B0 Transmit Buffer */ extern volatile unsigned int UCB0I2COA0; /* USCI B0 I2C Own Address 0 */ extern volatile unsigned char UCB0I2COA0_L; /* USCI B0 I2C Own Address 0 */ extern volatile unsigned char UCB0I2COA0_H; /* USCI B0 I2C Own Address 0 */ extern volatile unsigned int UCB0I2COA1; /* USCI B0 I2C Own Address 1 */ extern volatile unsigned char UCB0I2COA1_L; /* USCI B0 I2C Own Address 1 */ extern volatile unsigned char UCB0I2COA1_H; /* USCI B0 I2C Own Address 1 */ extern volatile unsigned int UCB0I2COA2; /* USCI B0 I2C Own Address 2 */ extern volatile unsigned char UCB0I2COA2_L; /* USCI B0 I2C Own Address 2 */ extern volatile unsigned char UCB0I2COA2_H; /* USCI B0 I2C Own Address 2 */ extern volatile unsigned int UCB0I2COA3; /* USCI B0 I2C Own Address 3 */ extern volatile unsigned char UCB0I2COA3_L; /* USCI B0 I2C Own Address 3 */ extern volatile unsigned char UCB0I2COA3_H; /* USCI B0 I2C Own Address 3 */ extern volatile unsigned int UCB0ADDRX; /* USCI B0 Received Address Register */ extern volatile unsigned char UCB0ADDRX_L; /* USCI B0 Received Address Register */ extern volatile unsigned char UCB0ADDRX_H; /* USCI B0 Received Address Register */ extern volatile unsigned int UCB0ADDMASK; /* USCI B0 Address Mask Register */ extern volatile unsigned char UCB0ADDMASK_L; /* USCI B0 Address Mask Register */ extern volatile unsigned char UCB0ADDMASK_H; /* USCI B0 Address Mask Register */ extern volatile unsigned int UCB0I2CSA; /* USCI B0 I2C Slave Address */ extern volatile unsigned char UCB0I2CSA_L; /* USCI B0 I2C Slave Address */ extern volatile unsigned char UCB0I2CSA_H; /* USCI B0 I2C Slave Address */ extern volatile unsigned int UCB0IE; /* USCI B0 Interrupt Enable Register */ extern volatile unsigned char UCB0IE_L; /* USCI B0 Interrupt Enable Register */ extern volatile unsigned char UCB0IE_H; /* USCI B0 Interrupt Enable Register */ extern volatile unsigned int UCB0IFG; /* USCI B0 Interrupt Flags Register */ extern volatile unsigned char UCB0IFG_L; /* USCI B0 Interrupt Flags Register */ extern volatile unsigned char UCB0IFG_H; /* USCI B0 Interrupt Flags Register */ extern volatile unsigned int UCB0IV; /* USCI B0 Interrupt Vector Register */ // UCAxCTLW0 UART-Mode Control Bits // UCAxCTLW0 UART-Mode Control Bits // UCAxCTLW0 UART-Mode Control Bits // UCxxCTLW0 SPI-Mode Control Bits //#define res (0x0020) /* reserved */ //#define res (0x0010) /* reserved */ //#define res (0x0008) /* reserved */ //#define res (0x0004) /* reserved */ // UCBxCTLW0 I2C-Mode Control Bits //#define res (0x1000) /* reserved */ //#define res (0x0100) /* reserved */ // UCBxCTLW0 I2C-Mode Control Bits //#define res (0x1000) /* reserved */ //#define res (0x0100) /* reserved */ // UCBxCTLW0 I2C-Mode Control Bits //#define res (0x1000) /* reserved */ //#define res (0x0100) /* reserved */ // UCAxCTLW1 UART-Mode Control Bits // UCAxCTLW1 UART-Mode Control Bits // UCBxCTLW1 I2C-Mode Control Bits // UCBxCTLW1 I2C-Mode Control Bits // UCBxCTLW1 I2C-Mode Control Bits /* UCAxMCTLW Control Bits */ /* UCAxMCTLW Control Bits */ /* UCAxMCTLW Control Bits */ /* UCAxSTATW Control Bits */ /* UCBxSTATW I2C Control Bits */ /* UCBxTBCNT I2C Control Bits */ /* UCAxIRCTL Control Bits */ /* UCAxIRCTL Control Bits */ /* UCAxIRCTL Control Bits */ /* UCAxABCTL Control Bits */ //#define res (0x80) /* reserved */ //#define res (0x40) /* reserved */ //#define res (0x02) /* reserved */ /* UCBxI2COA0 Control Bits */ /* UCBxI2COA0 Control Bits */ /* UCBxI2COA0 Control Bits */ /* UCBxI2COAx Control Bits */ /* UCBxI2COAx Control Bits */ /* UCBxI2COAx Control Bits */ /* UCBxADDRX Control Bits */ /* UCBxADDRX Control Bits */ /* UCBxADDRX Control Bits */ /* UCBxADDMASK Control Bits */ /* UCBxADDMASK Control Bits */ /* UCBxADDMASK Control Bits */ /* UCBxI2CSA Control Bits */ /* UCBxI2CSA Control Bits */ /* UCBxI2CSA Control Bits */ /* UCAxIE UART Control Bits */ /* UCAxIE/UCBxIE SPI Control Bits */ /* UCBxIE I2C Control Bits */ /* UCAxIFG UART Control Bits */ /* UCAxIFG/UCBxIFG SPI Control Bits */ /* UCBxIFG Control Bits */ /* USCI UART Definitions */ /* USCI SPI Definitions */ /* USCI I2C Definitions */ /************************************************************ * WATCHDOG TIMER A ************************************************************/ extern volatile unsigned int WDTCTL; /* Watchdog Timer Control */ extern volatile unsigned char WDTCTL_L; /* Watchdog Timer Control */ extern volatile unsigned char WDTCTL_H; /* Watchdog Timer Control */ /* The bit names have been prefixed with "WDT" */ /* WDTCTL Control Bits */ /* WDTCTL Control Bits */ /* WDT-interval times [1ms] coded with Bits 0-2 */ /* WDT is clocked by fSMCLK (assumed 1MHz) */ /* WDT is clocked by fACLK (assumed 32KHz) */ /* Watchdog mode -> reset after expired time */ /* WDT is clocked by fSMCLK (assumed 1MHz) */ /* WDT is clocked by fACLK (assumed 32KHz) */ /************************************************************ * TLV Descriptors ************************************************************/ /************************************************************ * Interrupt Vectors (offset from 0xFF80 + 0x10 for Password) ************************************************************/ #pragma diag_suppress 1107 /************************************************************ * End of Modules ************************************************************/ //////////// CODEC ///////////////////// // Local address definitions // Exceptions //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// enum Messages {Locked,Limit,ANRBeep,AGCBeep,VOXBeep,RadioBeep,KeyPadLocked,KeyPadUnLocked,LowSens,LowVolume,HighSens,HighVolume,LowBatt,VeryLowBatt,MaxHearTrough,SuperNormal}; enum PairingMessage {NormalHear,PairingActivated,PairingCompleted,PairingFailed,Beeep,QO,Silynx,Beeep3,LowBeeep,KeyPadLockeddd,KeyPadUnLockeddd,InternalBatt,ANROfff,SystemOffff,WhisperOnn,WhisperOfff}; enum MenuStates {TalkTroughLevel,Stop}; enum KeyPadPress {NoKeyPress,UPPress,DownPress,MenuPress,OptionPress}; enum ProgrammerInputs {NA,EN,MutePrimary,MuteSecondary,VolumePlus,VolumeMinus,TTPlus,TTMinus, ChannelPrimaryPlus,ChannelPrimaryMinus,ChannelSecondaryPlus, ChannelSecondaryMinus,GroupsPlus,GroupsMinus,PTT2nd,EnterFunction,ANRFunction}; enum Calibrations {CalibrationANRQO,CalibrationANRInfantry,CalibrationTalkTrough,CalibrationVoice, CalibrationVOX,CalibrationPrimeVolume,Option1,Option2,Option3,LangugeOffset,AtOffPosition}; enum NewHeadSets {HS_ShortToGND,HS_PELTOR,HS_HybridSilynxBoom,HS_SilynxITE,HS_ClarusHybridBoom,HS_ClarusITE,HS_20M,HS_NotConnected}; enum HeadSetsCalibrationsData {RadioCalibrationNoPTT,RadioCalibrationPTT,CloseLeftEar,AGC_Filter,BoomMicHeadset}; enum RadioCalibrationParameters {RADIO_MicPTT,RADIO_Volume,RADIO_OpenMic}; enum NewPrimes {P_ShortToGND,P_10K,P_20K,P_30K,P_47K,P_PRRMarconi,P_68K,P_PNR500,P_MBITRSide,P_120K,P_Tad624,P_Kashap1783,P_240K, P_Jeday,P_33022AF,P_MBITRUp,P_510K,P_IPhone,P_Vered,P_MP3,P_NotConnected}; enum NewSecondarys {S_ShortToGND,S_10K,S_20K,S_30K,S_47K,S_PRRMarconi,S_68K,S_PNR500,S_MBITRSide,S_120K,S_Tad624,S_Kashap1783,S_240K, S_Jeday,S_33022AF,S_MBITRUp,S_510K,S_IPhone,S_Vered,S_MP3,S_NotConnected}; enum NewThirds {T_ShortToGND,T_10K,T_20K,T_30K,T_47K,T_PRRMarconi,T_68K,T_PNR500,T_MBITRSide,T_120K,T_Tad624,T_Kashap1783,T_240K, T_Jeday,T_33022AF,T_MBITRUp,T_510K,T_IPhone,T_Vered,T_MP3,T_NotConnected}; enum AGCModes {Normal,Attack,ReleasePre,ReleasePost,FirstAttack}; enum PTTStates {BothPTTPress,PTT5Press,PTT4Press,PTT3Press,PTT2Press,PTT1Press,NoPTTPress}; /* enum Primes {NoPrime,P_NotRecognize,P_MBITRSide,P_Jeday,P_MBITRUp,P_Tad624,P_KP2288,P_PRRMarconi,P_33022AF, P_Kashap1783,P_IPhone,P_Vered,P_MP3,P_XTS5000,P_PNR500,P_10K,P_20K,P_30K ,P_47K,P_68K}; enum Secondarys {NoSecondary,S_NotRecognize,S_MBITRSide,S_Jeday,S_MBITRUp,S_Tad624,S_KP2288,S_PRRMarconi, S_33022AF,S_Kashap1783,S_IPhone,S_Vered,S_MP3,S_XTS5000,S_PNR500,S_10K,S_20K,S_30K ,S_47K,S_68K}; enum Thirds {NoThird,T_NotRecognize,T_MBITRSide,T_Jeday,T_MBITRUp,T_Tad624,T_KP2288,T_PRRMarconi, T_33022AF,T_Kashap1783,T_IPhone,T_Vered,T_MP3,T_XTS5000,T_PNR500,T_10K,T_20K,T_30K ,T_47K,T_68K}; */ enum { PAIRING_MSG = 1, PAIRING_ACK_MSG, STATUS_UPDATE_ACK_REQUEST_MSG, STATUS_UPDATE_MSG, STATUS_ACK_MSG } ; //MBITR UP /* #define WRULowUSA3 1 //1.2 #define WRULowXTS5000 1 //2.26 #define WRULowUSA4 1 //2.74 #define WRULowUSA5 1 //3.6 */ int WRUValuesRadios[]={95,187,272,371,442,562,625,798,913,1108,1382,1555,1817,2042,2166,2467,2629,2810,2972,0xFFFF}; int WRUValuesHeadSets[]={10,850,1050,1500,2300,3250,0xFFFF}; extern char ADCLastSamplesResults[15]; extern void SetupNetMonitoring(char P2R,char P2L,char PS2R,char PS2L,char S2R,char S2L,char SS2R,char SS2L,char T2R,char T2L,char TS2R,char TS2L); extern char LastMicSelection; extern void AGC_ITE_FILTER(void); extern void AGC_20M_FILTER(void); extern void BoomMicSelection(void); extern void ITEMicSelection(void); extern void LastAmpDCP(char X); enum NewPrimes TheConnectPrime=P_NotConnected; enum NewSecondarys TheConnectSecondary=S_NotConnected; enum NewThirds TheConnectThird=T_NotConnected; enum NewHeadSets TheConnectHeadset=HS_NotConnected; int PrimeSample=0; int SecondarySample=0; unsigned int ThirdSample=0; int HeadSetSample=0; char HeadSetCalibrations[sizeof(enum NewHeadSets)][sizeof(enum HeadSetsCalibrationsData)]; char CloseEar=0; char RadioCalPTT=90; char RadioCalNoPTT=255; int abs(int i) { return (i < 0 ? -i : i); } /* char PrimeCalibrations[NoOfPrimes][NumberOfRadiosCalibrations]; */ void ChangePrimary(enum NewPrimes ThePrimary) { if (((ThePrimary!=P_NotConnected)&&(TheConnectPrime==P_NotConnected))||(ThePrimary==P_NotConnected)) { TheConnectPrime=ThePrimary; } } void ChangeSecondary(enum NewSecondarys TheSecondary) { if (((TheSecondary!=S_NotConnected)&&(TheConnectSecondary==S_NotConnected))||(TheSecondary==S_NotConnected)) { TheConnectSecondary=TheSecondary; } } void ChangeThird(enum NewThirds TheThird) { if (((TheThird!=T_NotConnected)&&(TheConnectThird==T_NotConnected))||(TheThird==T_NotConnected)) { TheConnectThird=TheThird; SetupNetMonitoring(1,1,1,1,1,1,1,1,1,1,1,1); } } void ChangeHeadSet(enum NewHeadSets TheHeadSet) { if (((TheHeadSet!=HS_NotConnected)&&(TheConnectHeadset==HS_NotConnected))||(TheHeadSet==HS_NotConnected)) { TheConnectHeadset=TheHeadSet; RadioCalPTT=HeadSetCalibrations[(char)TheHeadSet][(char)RadioCalibrationPTT]; RadioCalNoPTT=HeadSetCalibrations[(char)TheHeadSet][(char)RadioCalibrationNoPTT]; CloseEar=HeadSetCalibrations[(char)TheHeadSet][(char)CloseLeftEar]; if (HeadSetCalibrations[(char)TheHeadSet][(char)AGC_Filter]) { AGC_20M_FILTER(); LastAmpDCP(150); } else { AGC_ITE_FILTER(); LastAmpDCP(70); } if (HeadSetCalibrations[(char)TheHeadSet][(char)BoomMicHeadset]) { LastMicSelection = 1; } else { LastMicSelection = 0; } } } extern char ADCSampleQueue[30]; extern char ADCSAmpleIndex; char ADCSAmpleScan,ADCSAmpleStopScan; void CheckWRU(void) { char i; int TempDiff=0; ADCSAmpleScan=ADCSAmpleIndex; if (ADCSAmpleIndex>0) { ADCSAmpleStopScan=ADCSAmpleIndex-1; } else { ADCSAmpleStopScan=30-1; } while((ADCSampleQueue[ADCSAmpleScan]!=0)&&(ADCSAmpleScan!=ADCSAmpleStopScan)) { ADCSAmpleScan++; if (ADCSAmpleScan==30) { ADCSAmpleScan=0; } } if (ADCSAmpleScan!=ADCSAmpleStopScan) { for(i=5;i<=9;i++) { ADCSampleQueue[ADCSAmpleScan]=i; ADCSAmpleScan++; if (ADCSAmpleScan==30) { ADCSAmpleScan=0; } } ADCSampleQueue[ADCSAmpleScan]=0; } if (abs(ADCLastSamplesResults[8]-HeadSetSample)>30) { HeadSetSample=ADCLastSamplesResults[8]; char HeadsetIndex=0; while(WRUValuesHeadSets[HeadsetIndex]30) { PrimeSample=ADCLastSamplesResults[7]; char PrimaryIndex=0; while(WRUValuesRadios[PrimaryIndex]30) { SecondarySample=ADCLastSamplesResults[6]; char SecondaryIndex=0; while(WRUValuesRadios[SecondaryIndex]30) { ThirdSample=ADCLastSamplesResults[5]; char ThirdIndex=0; while(WRUValuesRadios[ThirdIndex]