/// \file DeviceInit.c
/// \brief This file contains source code for the Device_Init class.
/*
=============================================================================
* Copyright (C) 2020
* PNC Technologies Co., Ltd.
* All Rights Reserved
*
* The content of this file is copyrighted by PNC Technologies Co., Ltd. or
* its affiliated, associated or related companies. All copyrights and other
* associated intellectual property rights related thereto are expressly
* reserved by PNC Technologies Co., Ltd.
=============================================================================
* File Revision History (top to bottom: first revision to last revision)
=============================================================================
*
* Date          user    (Description on following lines: changes, etc.)
* ----------- --------
* 26-Mar-2020   BT Jung
* + Created initial version
*
*
*
=============================================================================
*/


/*=========================================================================*/
/*                   MODULES USED (#include statements)                    */
/*=========================================================================*/

#include <includes.h>
#include "DeviceInit.h"

#include "hw_syscfg0_OMAPL138.h"
#include "hw_syscfg1_OMAPL138.h"
#include "hw_pllc_OMAPL138.h"
#include "soc_OMAPL138.h"

#include "evmOMAPL138.h"

#include "hw_types.h"
#include "hw_ddr2_mddr.h"
#include "psc.h"

#include <ti/drv/spi/soc/SPI_soc.h> // for test, duplicated with "includes.h"
/*=========================================================================*/
/*                            COMPILER DIRECTIVES                          */
/*=========================================================================*/


/*=========================================================================*/
/*                                CONSTANTS                                */
/*=========================================================================*/



/*=========================================================================*/
/*                       MACROS  (inline functions)                        */
/*=========================================================================*/


/*=========================================================================*/
/*                                  TYPEDEFS                               */
/*=========================================================================*/


/*=========================================================================*/
/*           PROTOTYPES OF LOCAL FUNCTIONS (static functions)              */
/*=========================================================================*/

static void Init_PLL0();
static void PIN_Init(void);

static void Init_GpioPinMux(void);
static void Init_EmifPinMux();
static void Init_UartPinMux();
static void Init_SPIPinMux(void);
static void Init_I2CPinMux(void);
static void Init_ECAPPinMux(void);
static void Init_EPWMPinMux(void);
static void Init_EmacPinMux();
static void Init_LcdPinMux();

static void Init_Gpio(void);
static void Init_EMIFA (void);
static void Init_SPI();
static void Init_I2C();
static void Init_ECAP1(void);
static void Init_ECAP2(void);
static void LCDContrastSet(unsigned short val);
static void Init_ECAP(void);
static void Init_EPWM();
static void Board_initSPI(void);
static void Spi1_open();
static void Board_initI2C(void);
static void I2C0_open(void);
static void BSP_LED_Init(void);
static void BSP_SPI_Init(void);
static void BSP_I2C_Init(void);
static void Init_ECAP(void);
/*=========================================================================*/
/*                    CLASS VARIABLES   (static variables)                 */
/*=========================================================================*/

// Pointers to OMAPL1x Module Memory Mapped Registers
static CSL_SyscfgRegsOvly      sysRegs     = (CSL_SyscfgRegsOvly)  (CSL_SYSCFG_0_REGS);
static CSL_PscRegsOvly         psc0Regs    = (CSL_PscRegsOvly)     (CSL_PSC_0_REGS);
static CSL_PscRegsOvly         psc1Regs    = (CSL_PscRegsOvly)     (CSL_PSC_1_REGS);
static CSL_PllcRegsOvly        pll0Regs    = (CSL_PllcRegsOvly)    (CSL_PLLC_CFG_0_REGS);
static CSL_PllcRegsOvly        pll1Regs    = (CSL_PllcRegsOvly)    (CSL_PLLC_CFG_1_REGS);
static volatile CSL_GpioRegs     *gpioRegs  = (CSL_GpioRegs *)      (CSL_GPIO_0_REGS);
//CSL_I2cRegsOvly         i2c0Regs    = (CSL_I2cRegsOvly)     (CSL_I2C_0_REGS);
static volatile CSL_SpiRegs      *spi1Regs   = (CSL_SpiRegs *)       (CSL_SPI_1_SLV_REGS);
//CSL_TmrRegsOvly         tmr0Regs    = (CSL_TmrRegsOvly)     (CSL_TMR_0_REGS);
//CSL_TmrRegsOvly         tmr1Regs    = (CSL_TmrRegsOvly)     (CSL_TMR_1_REGS);
static CSL_UartRegsOvly        uartRegs[2]   = {(CSL_UartRegsOvly)    (CSL_UART_2_REGS), (CSL_UartRegsOvly) (CSL_UART_1_REGS)};
static CSL_UartRegsOvly        uart0Regs   = (CSL_UartRegsOvly)    (CSL_UART_0_REGS);
static CSL_UartRegsOvly        uart1Regs   = (CSL_UartRegsOvly)    (CSL_UART_1_REGS);
static CSL_UartRegsOvly        uart2Regs   = (CSL_UartRegsOvly)    (CSL_UART_2_REGS);
static CSL_EmifaRegsOvly       emifaRegs   = (CSL_EmifaRegsOvly)   (CSL_EMIFA_0_REGS);
static CSL_EcapRegs           *ecap1Regs   = (CSL_EcapRegs *)      (CSL_ECAP_1_REGS);
static CSL_EcapRegs           *ecap2Regs   = (CSL_EcapRegs *)      (CSL_ECAP_2_REGS);


SPI_Params      spiParams; /* SPI params structure */
bool            spiTestPassed;

SPI_Handle      spiHwHandle;  /* SPI handle */
uint32_t        spiXferEnable, spiLoop;
SPI_v0_HWAttrs spi_cfg;

uint32_t ui32SysClock;  /* SJeong */

extern I2C_Handle i2cHandle;

/*=========================================================================*/
/*                  LOCAL FUNCTIONS  (static functions)                    */
/*=========================================================================*/


static void PIN_Init(void)
{
    // initialize PIN_muxing
    Init_GpioPinMux();
    Init_EmifPinMux();
    Init_UartPinMux();
    Init_SPIPinMux();
    Init_I2CPinMux();
    Init_ECAPPinMux();
    Init_EPWMPinMux();
    Init_EmacPinMux();
    Init_LcdPinMux();

}

// GPIO1-15(APP_START), GPIO6-14(WD_CNT)
// LED  GP0[9], GP6[12], GP6[13]
// ADC_EOC     GPIO_0_02
// ADC_FSTDAT  GPIO_0_03
// LCD_BKLED   GPIO_0_7
// DIO         GPIO_0_15 ~ GPIO_0_10
// SPI         GPIO_8_15 ~ GPIO_8_12
// AD_CONST_CKH GPIO_3_9


static void Init_GpioPinMux(void)
{
    //////////////////////////////////////////////
    // D7: GPIO0[9]
    // D4: GPIO6[13], D5: GPIO6[12]

    /*
    // GPIO0_9
    sysRegs->PINMUX0 &= (~(CSL_SYSCFG_PINMUX0_PINMUX0_27_24_MASK));
    sysRegs->PINMUX0 |= 0x08000000;

    // GPIO6_12, GPIO6_13
    sysRegs->PINMUX13 &= (~(CSL_SYSCFG_PINMUX13_PINMUX13_15_12_MASK |
                           CSL_SYSCFG_PINMUX13_PINMUX13_11_8_MASK));
    sysRegs->PINMUX13 |= 0x00008800;    // GPIO6[8:15]
    */

    sysRegs->PINMUX0 &= (~(CSL_SYSCFG_PINMUX1_PINMUX1_31_28_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_27_24_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_23_20_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_19_16_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_15_12_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_11_8_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_7_4_MASK |
                           CSL_SYSCFG_PINMUX0_PINMUX0_3_0_MASK));
    sysRegs->PINMUX0 |= BOARD_PINMUX0_GPIO_ENABLE;

    sysRegs->PINMUX1 &= (~(CSL_SYSCFG_PINMUX1_PINMUX1_27_24_MASK |
                           CSL_SYSCFG_PINMUX1_PINMUX1_23_20_MASK |
                           CSL_SYSCFG_PINMUX1_PINMUX1_19_16_MASK |
                           CSL_SYSCFG_PINMUX1_PINMUX1_15_12_MASK |
                           CSL_SYSCFG_PINMUX1_PINMUX1_11_8_MASK  |
                           CSL_SYSCFG_PINMUX1_PINMUX1_3_0_MASK));

    sysRegs->PINMUX1 |= BOARD_PINMUX1_GPIO_ENABLE;

    sysRegs->PINMUX2 &= (~(CSL_SYSCFG_PINMUX2_PINMUX2_3_0_MASK));

    sysRegs->PINMUX2 |= BOARD_PINMUX2_GPIO_ENABLE;

    sysRegs->PINMUX5 &= (~(CSL_SYSCFG_PINMUX5_PINMUX5_15_12_MASK));
    sysRegs->PINMUX5 |= BOARD_PINMUX5_GPIO_ENABLE;

    sysRegs->PINMUX6 &= (~(CSL_SYSCFG_PINMUX6_PINMUX6_15_12_MASK |
                           CSL_SYSCFG_PINMUX6_PINMUX6_11_8_MASK  |
                           CSL_SYSCFG_PINMUX6_PINMUX6_7_4_MASK));
    sysRegs->PINMUX6 |= BOARD_PINMUX6_GPIO_ENABLE;

    sysRegs->PINMUX7 &= (~(CSL_SYSCFG_PINMUX7_PINMUX7_27_24_MASK));
    sysRegs->PINMUX7 |= BOARD_PINMUX7_GPIO_ENABLE;

    sysRegs->PINMUX13 &= (~(CSL_SYSCFG_PINMUX13_PINMUX13_31_28_MASK |
                           CSL_SYSCFG_PINMUX13_PINMUX13_27_24_MASK |
                           CSL_SYSCFG_PINMUX13_PINMUX13_23_20_MASK |
                           CSL_SYSCFG_PINMUX13_PINMUX13_19_16_MASK |
                           CSL_SYSCFG_PINMUX13_PINMUX13_15_12_MASK |
                           CSL_SYSCFG_PINMUX13_PINMUX13_11_8_MASK  |
                           CSL_SYSCFG_PINMUX13_PINMUX13_7_4_MASK   |
                           CSL_SYSCFG_PINMUX13_PINMUX13_3_0_MASK));
    sysRegs->PINMUX13 |= BOARD_PINMUX13_GPIO_ENABLE;

    sysRegs->PINMUX14 &= (~(CSL_SYSCFG_PINMUX14_PINMUX14_7_4_MASK   |
                           CSL_SYSCFG_PINMUX14_PINMUX14_3_0_MASK));
    sysRegs->PINMUX14 |= BOARD_PINMUX14_GPIO_ENABLE;

    sysRegs->PINMUX16 &= (~(CSL_SYSCFG_PINMUX16_PINMUX16_7_4_MASK));
    sysRegs->PINMUX16 |= BOARD_PINMUX16_GPIO_ENABLE;

    sysRegs->PINMUX18 &= (~(CSL_SYSCFG_PINMUX18_PINMUX18_31_28_MASK |
                           CSL_SYSCFG_PINMUX18_PINMUX18_23_20_MASK |
                           CSL_SYSCFG_PINMUX18_PINMUX18_19_16_MASK |
                           CSL_SYSCFG_PINMUX18_PINMUX18_15_12_MASK |
                           CSL_SYSCFG_PINMUX18_PINMUX18_11_8_MASK ));
    sysRegs->PINMUX18 |= BOARD_PINMUX18_GPIO_ENABLE;

    sysRegs->PINMUX19 &= (~(CSL_SYSCFG_PINMUX19_PINMUX19_23_20_MASK |
                           CSL_SYSCFG_PINMUX19_PINMUX19_19_16_MASK |
                           CSL_SYSCFG_PINMUX19_PINMUX19_15_12_MASK |
                           CSL_SYSCFG_PINMUX19_PINMUX19_11_8_MASK));
    sysRegs->PINMUX19 |= BOARD_PINMUX19_GPIO_ENABLE;
}


static void Init_EmifPinMux()
{
    sysRegs->PINMUX5 &= (~(CSL_SYSCFG_PINMUX5_PINMUX5_31_28_MASK |
                           CSL_SYSCFG_PINMUX5_PINMUX5_27_24_MASK));
    sysRegs->PINMUX5 |= BOARD_PINMUX5_EMIF_ENABLE;

    sysRegs->PINMUX6 &= (~(CSL_SYSCFG_PINMUX6_PINMUX6_31_28_MASK |
                           CSL_SYSCFG_PINMUX6_PINMUX6_27_24_MASK |
                           CSL_SYSCFG_PINMUX6_PINMUX6_23_20_MASK |
                           CSL_SYSCFG_PINMUX6_PINMUX6_19_16_MASK |
                           CSL_SYSCFG_PINMUX6_PINMUX6_3_0_MASK));
    sysRegs->PINMUX6 |= BOARD_PINMUX6_EMIF_ENABLE;

    sysRegs->PINMUX7 &= (~(CSL_SYSCFG_PINMUX7_PINMUX7_31_28_MASK |
                           CSL_SYSCFG_PINMUX7_PINMUX7_23_20_MASK |
                           CSL_SYSCFG_PINMUX7_PINMUX7_19_16_MASK |
                           CSL_SYSCFG_PINMUX7_PINMUX7_15_12_MASK |
                           CSL_SYSCFG_PINMUX7_PINMUX7_11_8_MASK  |
                           CSL_SYSCFG_PINMUX7_PINMUX7_7_4_MASK   |
                           CSL_SYSCFG_PINMUX7_PINMUX7_3_0_MASK));
    sysRegs->PINMUX7 |= BOARD_PINMUX7_EMIF_ENABLE;

    sysRegs->PINMUX8 &= (~(CSL_SYSCFG_PINMUX8_PINMUX8_31_28_MASK |
                           CSL_SYSCFG_PINMUX8_PINMUX8_27_24_MASK |
                           CSL_SYSCFG_PINMUX8_PINMUX8_23_20_MASK |
                           CSL_SYSCFG_PINMUX8_PINMUX8_19_16_MASK |
                           CSL_SYSCFG_PINMUX8_PINMUX8_15_12_MASK |
                           CSL_SYSCFG_PINMUX8_PINMUX8_11_8_MASK  |
                           CSL_SYSCFG_PINMUX8_PINMUX8_7_4_MASK   |
                           CSL_SYSCFG_PINMUX8_PINMUX8_3_0_MASK));
    sysRegs->PINMUX8 |= BOARD_PINMUX8_EMIF_ENABLE;

    sysRegs->PINMUX9 &= (~(CSL_SYSCFG_PINMUX9_PINMUX9_31_28_MASK |
                           CSL_SYSCFG_PINMUX9_PINMUX9_27_24_MASK |
                           CSL_SYSCFG_PINMUX9_PINMUX9_23_20_MASK |
                           CSL_SYSCFG_PINMUX9_PINMUX9_19_16_MASK |
                           CSL_SYSCFG_PINMUX9_PINMUX9_15_12_MASK |
                           CSL_SYSCFG_PINMUX9_PINMUX9_11_8_MASK  |
                           CSL_SYSCFG_PINMUX9_PINMUX9_7_4_MASK   |
                           CSL_SYSCFG_PINMUX9_PINMUX9_3_0_MASK));
    sysRegs->PINMUX9 |= BOARD_PINMUX9_EMIF_ENABLE;

    sysRegs->PINMUX10 &= (~(CSL_SYSCFG_PINMUX10_PINMUX10_31_28_MASK |
                           CSL_SYSCFG_PINMUX10_PINMUX10_27_24_MASK |
                           CSL_SYSCFG_PINMUX10_PINMUX10_23_20_MASK));
    sysRegs->PINMUX10 |= BOARD_PINMUX10_EMIF_ENABLE;

    sysRegs->PINMUX11 &= (~(CSL_SYSCFG_PINMUX11_PINMUX11_31_28_MASK |
                           CSL_SYSCFG_PINMUX11_PINMUX11_27_24_MASK |
                           CSL_SYSCFG_PINMUX11_PINMUX11_23_20_MASK |
                           CSL_SYSCFG_PINMUX11_PINMUX11_19_16_MASK |
                           CSL_SYSCFG_PINMUX11_PINMUX11_15_12_MASK |
                           CSL_SYSCFG_PINMUX11_PINMUX11_11_8_MASK  |
                           CSL_SYSCFG_PINMUX11_PINMUX11_7_4_MASK   |
                           CSL_SYSCFG_PINMUX11_PINMUX11_3_0_MASK));
    sysRegs->PINMUX11 |= BOARD_PINMUX11_EMIF_ENABLE;

    sysRegs->PINMUX12 &= (~(CSL_SYSCFG_PINMUX12_PINMUX12_31_28_MASK |
                           CSL_SYSCFG_PINMUX12_PINMUX12_27_24_MASK |
                           CSL_SYSCFG_PINMUX12_PINMUX12_23_20_MASK |
                           CSL_SYSCFG_PINMUX12_PINMUX12_19_16_MASK |
                           CSL_SYSCFG_PINMUX12_PINMUX12_15_12_MASK |
                           CSL_SYSCFG_PINMUX12_PINMUX12_11_8_MASK  |
                           CSL_SYSCFG_PINMUX12_PINMUX12_7_4_MASK   |
                           CSL_SYSCFG_PINMUX12_PINMUX12_3_0_MASK));
    sysRegs->PINMUX12 |= BOARD_PINMUX12_EMIF_ENABLE;

}


static void Init_UartPinMux()
{
    sysRegs->PINMUX4 &= (~(CSL_SYSCFG_PINMUX4_PINMUX4_31_28_MASK |
                           CSL_SYSCFG_PINMUX4_PINMUX4_27_24_MASK |
                           CSL_SYSCFG_PINMUX4_PINMUX4_23_20_MASK |
                           CSL_SYSCFG_PINMUX4_PINMUX4_19_16_MASK));
    sysRegs->PINMUX4 |= BOARD_PINMUX4_UART_ENABLE;
}


static void Init_SPIPinMux(void)
{
    // Enable the pinmux registers for SPI
    sysRegs->PINMUX5 &= (~(CSL_SYSCFG_PINMUX5_PINMUX5_23_20_MASK |  /* spi1_simo */
                           CSL_SYSCFG_PINMUX5_PINMUX5_19_16_MASK |  /* spi1_somi */
                           CSL_SYSCFG_PINMUX5_PINMUX5_11_8_MASK  |  /* spi1_clk  */
                           CSL_SYSCFG_PINMUX5_PINMUX5_7_4_MASK ));  /* spi1_cs0 */      //占쎈쐻占쎈짗占쎌굲 占쎈쐻占쎈짗占쎌굲占쎈쐻占쎈짗占쎌굲
                                                                    /* spi1_cs1 占쎈쐻占쎈짗占쎌굲 epwm1a占쎈쐻占쎈짗占쎌굲占쎈쐻占쎈짗占쎌굲 占쎈쐻占쎈짗占쎌굲占쎈쐻�뜝占�*/
    sysRegs->PINMUX5 |= BOARD_PINMUX5_SPI_ENABLE;
}


static void Init_I2CPinMux(void)
{
     // Enable the pinmux registers for I2c
    sysRegs->PINMUX4 &= (~(CSL_SYSCFG_PINMUX4_PINMUX4_15_12_MASK |
                           CSL_SYSCFG_PINMUX4_PINMUX4_11_8_MASK ));

    sysRegs->PINMUX4  |= BOARD_PINMUX4_I2C_ENABLE;  /* I2c0 */
}

static void Init_ECAPPinMux(void)
{
    // Enable the pinmux registers for ECAP1 / APWM2
    sysRegs->PINMUX1 &= (~(CSL_SYSCFG_PINMUX1_PINMUX1_31_28_MASK |
                           CSL_SYSCFG_PINMUX1_PINMUX1_3_0_MASK));   /* ecap1 */
    sysRegs->PINMUX1 |= BOARD_PINMUX1_ECAP_ENABLE;

    CSL_FINST(sysRegs->SUSPSRC, SYSCFG_SUSPSRC_ECAP1SRC, ARM);
    CSL_FINST(sysRegs->SUSPSRC, SYSCFG_SUSPSRC_ECAP2SRC, ARM);

}


static void Init_EPWMPinMux(void)
{
    // Enable the pinmux registers for SPI
    sysRegs->PINMUX5 &= (~(CSL_SYSCFG_PINMUX5_PINMUX5_3_0_MASK));   /* epwm1a */
    sysRegs->PINMUX5 |= BOARD_PINMUX5_EPWM_ENABLE;

}



static void Init_EmacPinMux()
{
    /* Enable the pinmux registers for EMAC Tx */
    sysRegs->PINMUX2 &= (~(CSL_SYSCFG_PINMUX2_PINMUX2_7_4_MASK |
                         CSL_SYSCFG_PINMUX2_PINMUX2_11_8_MASK  |
                         CSL_SYSCFG_PINMUX2_PINMUX2_15_12_MASK |
                         CSL_SYSCFG_PINMUX2_PINMUX2_19_16_MASK |
                         CSL_SYSCFG_PINMUX2_PINMUX2_23_20_MASK |
                         CSL_SYSCFG_PINMUX2_PINMUX2_27_24_MASK |
                         CSL_SYSCFG_PINMUX2_PINMUX2_31_28_MASK ));
    sysRegs->PINMUX2 |= BOARD_PINMUX2_EMAC_ENABLE;

    /* Enable the pinmux registers for EMAC Rx */
    sysRegs->PINMUX3 &= (~(CSL_SYSCFG_PINMUX3_PINMUX3_3_0_MASK |
                         CSL_SYSCFG_PINMUX3_PINMUX3_7_4_MASK   |
                         CSL_SYSCFG_PINMUX3_PINMUX3_11_8_MASK  |
                         CSL_SYSCFG_PINMUX3_PINMUX3_15_12_MASK |
                         CSL_SYSCFG_PINMUX3_PINMUX3_19_16_MASK |
                         CSL_SYSCFG_PINMUX3_PINMUX3_23_20_MASK |
                         CSL_SYSCFG_PINMUX3_PINMUX3_27_24_MASK |
                         CSL_SYSCFG_PINMUX3_PINMUX3_31_28_MASK ));
    sysRegs->PINMUX3 |= BOARD_PINMUX3_EMAC_ENABLE;

    /* Enable the pinmux registers for EMAC MDIO */
    sysRegs->PINMUX4 &= (~(CSL_SYSCFG_PINMUX4_PINMUX4_3_0_MASK |
                           CSL_SYSCFG_PINMUX4_PINMUX4_7_4_MASK));
    sysRegs->PINMUX4  |= BOARD_PINMUX4_EMAC_ENABLE;

    /* Select MII mode */
    sysRegs->CFGCHIP3 &= (~(CSL_SYSCFG_CFGCHIP3_RMII_SEL_MASK ));
    sysRegs->CFGCHIP3 |= 0x00u;
}


static void Init_LcdPinMux()
{
    sysRegs->PINMUX16 &= (~(CSL_SYSCFG_PINMUX16_PINMUX16_31_28_MASK |
                           CSL_SYSCFG_PINMUX16_PINMUX16_27_24_MASK |
                           CSL_SYSCFG_PINMUX16_PINMUX16_23_20_MASK |
                           CSL_SYSCFG_PINMUX16_PINMUX16_19_16_MASK |
                           CSL_SYSCFG_PINMUX16_PINMUX16_15_12_MASK |
                           CSL_SYSCFG_PINMUX16_PINMUX16_11_8_MASK));
    sysRegs->PINMUX16 |= BOARD_PINMUX16_LCD_ENABLE;

    sysRegs->PINMUX17 &= (~(CSL_SYSCFG_PINMUX17_PINMUX17_31_28_MASK |
                           CSL_SYSCFG_PINMUX17_PINMUX17_27_24_MASK |
                           CSL_SYSCFG_PINMUX17_PINMUX17_23_20_MASK |
                           CSL_SYSCFG_PINMUX17_PINMUX17_19_16_MASK |
                           CSL_SYSCFG_PINMUX17_PINMUX17_15_12_MASK |
                           CSL_SYSCFG_PINMUX17_PINMUX17_11_8_MASK  |
                           CSL_SYSCFG_PINMUX17_PINMUX17_7_4_MASK   |
                           CSL_SYSCFG_PINMUX17_PINMUX17_3_0_MASK));
    sysRegs->PINMUX17 |= BOARD_PINMUX17_LCD_ENABLE;

    sysRegs->PINMUX18 &= (~(CSL_SYSCFG_PINMUX18_PINMUX18_27_24_MASK |
                            CSL_SYSCFG_PINMUX18_PINMUX18_7_4_MASK   |
                            CSL_SYSCFG_PINMUX18_PINMUX18_3_0_MASK));
    sysRegs->PINMUX18 |= BOARD_PINMUX18_LCD_ENABLE;

    sysRegs->PINMUX19 &= (~(CSL_SYSCFG_PINMUX19_PINMUX19_27_24_MASK |
                            CSL_SYSCFG_PINMUX19_PINMUX19_7_4_MASK   |
                            CSL_SYSCFG_PINMUX19_PINMUX19_3_0_MASK));
    sysRegs->PINMUX19 |= BOARD_PINMUX19_LCD_ENABLE;

}


// LCDK : LED  GP0[9], GP6[12], GP6[13]
//  MFR : LED GP6[12], GP6[13]
// app_mode : gp6[15], // wd_cnt : gp6[14]
//  LCD_nRST    GPIO_2_04 (OUT)
//  E_INT       GPIO_2_06 (IN)
//  AI_RANGE    GPIO_2_07 (OUT)

//  CS_A0      GPIO_8_12
//  CS_A1      GPIO_8_13
//  CS_A2      GPIO_8_14
//  CS_A3      GPIO_8_15
//              -- PWM --
//  DO_WREN     GPIO_0_15  (OUT)
//  DO_RW       GPIO_0_14  (OUT)
//  DO_A2       GPIO_0_13  (OUT)
//  DO_A1       GPIO_0_12  (OUT)
//  DO_A0       GPIO_0_11  (OUT)
//  DO_CSn      GPIO_0_10  (OUT)

//  PWR_CHK     GPIO_0_09  (IN)
//  SYS_LIVE    GPIO_0_08  (OUT)
//  LCD_BKLED   GPIO_0_07  (OUT)

//  ADC_FSTDAT  GPIO_0_03  (IN)
//  ADC_EOC     GPIO_0_02  (IN)

static void Init_Gpio(void)
{
    // deassert GPIO local PSC reset and set NEXT state to ENABLE
    psc1Regs->MDCTL[CSL_PSC_GPIO-CSL_PSC_EDMA_CC1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
    // move UART PSC to Next state
    psc1Regs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
    // wait for transition
    while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_GPIO-CSL_PSC_EDMA_CC1], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );

    gpioRegs->BANK_REGISTERS[0].SET_DATA  = 0x8000fd00u;    // wdt_mode(1.15), DO_CTRL, LCD_BKLED
    gpioRegs->BANK_REGISTERS[0].CLR_DATA  = 0x000000a0u;    // test backlight off, do_nrst(0.5)

    // Set Direction (1:INPUT, 0: output)
    gpioRegs->BANK_REGISTERS[0].DIR &= ~(0x8000fda0u);      // wdt_mode(1.15), do_wren, do_rw, do_a2, do_a1, do_a0, do_csn, pwr_chk, sys_live, lcd_const, ADC_FRSTDATA, ADC_EOC, LCD_BKLED
    gpioRegs->BANK_REGISTERS[0].DIR |=  (0x0000024cu);      // ADC_FRSTDATA, ADC_EOC, PWR_CHK, PWR_UVD
    //
    #if SPI_USE_CS
    gpioRegs->BANK_REGISTERS[1].DIR &= ~(0x00001090u);      // ETH_nRST(2.12), LCD_nRST(2.4), AI_RANGE
    #else
    gpioRegs->BANK_REGISTERS[1].DIR &= ~(0x00004090u);      // LCD_nRST, AI_RANGE
    #endif
    gpioRegs->BANK_REGISTERS[1].DIR |=  (0x02000040u);      // AD_CONST_CHK(3.9), E_INT(2.6)
    //
    gpioRegs->BANK_REGISTERS[3].DIR &= ~(0x0000f000u);      // app_mode(6.15), wd_cnt(6.14), LED0(6.13), LED1(6.12)
    gpioRegs->BANK_REGISTERS[3].DIR |=  (0x00000e00u);      // uartintr1, uartintr0, rtcintr
    //
    gpioRegs->BANK_REGISTERS[4].DIR &= ~(0x0000f000u);      // sp_ex, spi_a2, spi_a1, spi_a0

    // Set Initial Data
    //gpioRegs->BANK_REGISTERS[0].SET_DATA  = 0x0000fd00u;     // DO_CTRL, LCD_BKLED
    //gpioRegs->BANK_REGISTERS[0].CLR_DATA  = 0x00000080u;     // test backlight off
    #if SPI_USE_CS
    gpioRegs->BANK_REGISTERS[1].SET_DATA  = 0x00001010u;     // ETH_nRST, LCD_nRST
    #else
    gpioRegs->BANK_REGISTERS[1].SET_DATA  = 0x00004010u;     // LCD_nRST
    #endif
    // clr Initial Data
    gpioRegs->BANK_REGISTERS[3].CLR_DATA = 0x000b000u;      // app_mode, LED

    // interrupt

    // Enable Bank 3 interrupts (AD_CONST_CHK)
    gpioRegs->BINTEN |= 0x08;

    // Clear Bank 0 Falling/Rising Edge Triggers
    gpioRegs->BANK_REGISTERS[1].CLR_FAL_TRIG |= 0xffff;
    gpioRegs->BANK_REGISTERS[1].CLR_RIS_TRIG |= 0xffff;

    // Enable Interrupt Trigger on GP3_9 Rising/Falling Edge
    gpioRegs->BANK_REGISTERS[1].SET_FAL_TRIG = (0x01<<25);

    // Enable Bank 6 interrupts (EUART)
    gpioRegs->BINTEN |= 0x40;

    // Clear Bank 6 Falling/Rising Edge Triggers
    gpioRegs->BANK_REGISTERS[3].CLR_FAL_TRIG |= 0xffff;
    gpioRegs->BANK_REGISTERS[3].CLR_RIS_TRIG |= 0xffff;

    // Enable Interrupt Trigger on GP6_10 GP6_11 Rising/Falling Edge (active high interrupt)
    gpioRegs->BANK_REGISTERS[3].SET_RIS_TRIG = (0x03<<10);
    //gpioRegs->BANK_REGISTERS[3].SET_FAL_TRIG = (0x03<<10);

}

// CS2 : HMI (8bit)     /* 0x60000000 - */
// CS3 : nand (16bit)   /* 0x62000000 - */
// CS4 : UART&DI (8bit) /* 0x64000000 - */
// CS5 : ADC (16bit)    /* 0x66000000 - */
// EMIF Clock is 38MHz / 26nsec

static void Init_EMIFA (void)
{
    // Open Permissions to SYSCFG Registers
    CSL_FINS(sysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK0_KEY);
    CSL_FINS(sysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK1_KEY);

    //[FREE(0) : PLLC1 MMRs are freely accessible]
    //[LOCK(1) : All PLLC1 MMRs are locked]
    //CSL_FINST(sysRegs->CFGCHIP3, SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK, FREE           );    //CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK
    //CSL_FINST(sysRegs->CFGCHIP3, SYSCFG_CFGCHIP3_EMA_CLKSRC      , PLLCTRL_SYSCLK3);    //CSL_SYSCFG_CFGCHIP3_EMA_CLKSRC_MASK
    //CSL_FINST(sysRegs->CFGCHIP3, SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK, LOCK           );    //CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK


    /**************************CS2 - HMI *****************************************************/
    //Select Strobe mode
    //[SELSTRB_DISABLE(0) : Normal Mode enabled]
    //[SELSTRB_ENABLE (1) : Select Strobe Mode enabled]
    CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_SS, SELSTRB_DISABLE);     //CSL_EMIFA_CE2CFG_SS_MASK

    //Extend Wait
    //[EXT_WAIT_DISABLE(0) : Extended wait cycles disabled]
    //[EXT_WAIT_ENABLE (1) : Extended wait cycles enabled]
    CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE2CFG_EW, EXT_WAIT_DISABLE);    //CSL_EMIFA_CE2CFG_EW_MASK

    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_SETUP , 0x01);           //CSL_EMIFA_CE2CFG_W_SETUP_MASK
    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_STROBE, 0x02);           //CSL_EMIFA_CE2CFG_W_STROBE_MASK
    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_W_HOLD  , 0x01);           //CSL_EMIFA_CE2CFG_W_HOLD_MASK
    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_SETUP , 0x01);           //CSL_EMIFA_CE2CFG_R_SETUP_MASK
    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_STROBE, 0x02);           //CSL_EMIFA_CE2CFG_R_STROBE_MASK
    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_R_HOLD  , 0x01);           //CSL_EMIFA_CE2CFG_R_HOLD_MASK
    CSL_FINS(emifaRegs->CE2CFG, EMIFA_CE2CFG_TA      , 0x01);           //CSL_EMIFA_CE2CFG_TA_MASK

    //Data Bus Width
    //[8BIT (0) : 8-bit data bus]
    //[16BIT(1) : 16-bit data bus]
    CSL_FINST(emifaRegs->CE2CFG, EMIFA_CE5CFG_ASIZE, 16BIT);            //CSL_EMIFA_CE2CFG_ASIZE_MASK

    /**************************CS3 - NAND *****************************************************/
    //Select Strobe mode
    //[SELSTRB_DISABLE(0) : Normal Mode enabled]
    //[SELSTRB_ENABLE (1) : Select Strobe Mode enabled]
    //CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_SS, SELSTRB_DISABLE);     //CSL_EMIFA_CE3CFG_SS_MASK

    //Extend Wait
    //[EXT_WAIT_DISABLE(0) : Extended wait cycles disabled]
    //[EXT_WAIT_ENABLE (1) : Extended wait cycles enabled]
    //CSL_FINST(emifaRegs->CE3CFG, EMIFA_CE3CFG_EW, EXT_WAIT_DISABLE);    //CSL_EMIFA_CE3CFG_EW_MASK

    /**************************CS4 - UART_DI *****************************************************/
    //Select Strobe mode
    //[SELSTRB_DISABLE(0) : Normal Mode enabled]
    //[SELSTRB_ENABLE (1) : Select Strobe Mode enabled]
    CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_SS, SELSTRB_DISABLE);     //CSL_EMIFA_CE4CFG_SS_MASK

    //Extend Wait
    //[EXT_WAIT_DISABLE(0) : Extended wait cycles disabled]
    //[EXT_WAIT_ENABLE (1) : Extended wait cycles enabled]
    CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_EW, EXT_WAIT_DISABLE);    //CSL_EMIFA_CE4CFG_EW_MASK

    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_W_SETUP , 0x01);           //CSL_EMIFA_CE4CFG_W_SETUP_MASK
    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_W_STROBE, 0x02);           //CSL_EMIFA_CE4CFG_W_STROBE_MASK
    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_W_HOLD  , 0x01);           //CSL_EMIFA_CE4CFG_W_HOLD_MASK
    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_SETUP , 0x01);           //CSL_EMIFA_CE4CFG_R_SETUP_MASK
    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_STROBE, 0x02);           //CSL_EMIFA_CE4CFG_R_STROBE_MASK
    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_R_HOLD  , 0x01);           //CSL_EMIFA_CE4CFG_R_HOLD_MASK
    CSL_FINS(emifaRegs->CE4CFG, EMIFA_CE4CFG_TA      , 0x01);           //CSL_EMIFA_CE4CFG_TA_MASK

    //Data Bus Width
    //[8BIT (0) : 8-bit data bus]
    //[16BIT(1) : 16-bit data bus]
    CSL_FINST(emifaRegs->CE4CFG, EMIFA_CE4CFG_ASIZE, 16BIT);            //CSL_EMIFA_CE4CFG_ASIZE_MASK

    /**************************CS5 - ADC *****************************************************/
    //Select Strobe mode
    //[SELSTRB_DISABLE(0) : Normal Mode enabled]
    //[SELSTRB_ENABLE (1) : Select Strobe Mode enabled]
    CSL_FINST(emifaRegs->CE5CFG, EMIFA_CE5CFG_SS, SELSTRB_DISABLE);     //CSL_EMIFA_CE5CFG_SS_MASK

    //Extend Wait
    //[EXT_WAIT_DISABLE(0) : Extended wait cycles disabled]
    //[EXT_WAIT_ENABLE (1) : Extended wait cycles enabled]
    CSL_FINST(emifaRegs->CE5CFG, EMIFA_CE5CFG_EW, EXT_WAIT_DISABLE);    //CSL_EMIFA_CE5CFG_EW_MASK

    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_W_SETUP , 0x01);           //CSL_EMIFA_CE5CFG_W_SETUP_MASK
    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_W_STROBE, 0x02);           //CSL_EMIFA_CE5CFG_W_STROBE_MASK
    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_W_HOLD  , 0x02);           //CSL_EMIFA_CE5CFG_W_HOLD_MASK
    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_R_SETUP , 0x01);           //CSL_EMIFA_CE5CFG_R_SETUP_MASK
    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_R_STROBE, 0x02);           //CSL_EMIFA_CE5CFG_R_STROBE_MASK
    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_R_HOLD  , 0x02);           //CSL_EMIFA_CE5CFG_R_HOLD_MASK
    CSL_FINS(emifaRegs->CE5CFG, EMIFA_CE5CFG_TA      , 0x02);           //CSL_EMIFA_CE5CFG_TA_MASK

    //Data Bus Width
    //[8BIT (0) : 8-bit data bus]
    //[16BIT(1) : 16-bit data bus]
    CSL_FINST(emifaRegs->CE5CFG, EMIFA_CE5CFG_ASIZE, 16BIT);            //CSL_EMIFA_CE5CFG_ASIZE_MASK

    // Open Permissions to SYSCFG Registers
    CSL_FINS(sysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK_LOCK);
    CSL_FINS(sysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK_LOCK);
}




static void BSP_LED_Init(void)
{

    /* LED On */
    CPU_RUN_LED_OFF;
    MPU_RUN_LED_OFF;
}

static void BSP_SPI_Init(void)
{
    Init_SPI();
    Board_initSPI();
    Spi1_open();
}

#ifdef ORIGINAL_PDK_SRC
void Board_initSPI(void)
{
    Board_initCfg boardCfg;

    SPI_v0_HWAttrs spi_cfg;
    Board_SoCInfo socInfo;

    /* Get the default SPI init configurations */
    SPI_socGetInitCfg(TEST_SPI_PORT, &spi_cfg);

    /* Modify the default SPI configurations if necessary */


    /* Update the SPI functional clock based on CPU clock*/
    Board_getSoCInfo(&socInfo);
    if(socInfo.sysClock != BOARD_SYS_CLK_DEFAULT)
    {
        spi_cfg.inputClkFreq = socInfo.sysClock/SPI_MODULE_CLOCK_DIVIDER;
    }

    /* Set the default SPI init configurations */
    SPI_socSetInitCfg(TEST_SPI_PORT, &spi_cfg);

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_UART_STDIO;

    Board_init(boardCfg);
}


/*
 *  ======== test function ========
 */
void spi_test(UArg arg0, UArg arg1)
{
    SPI_Params      spiParams; /* SPI params structure */
    bool            testPassed = true;
    SPI_Handle      hwHandle;  /* SPI handle */
    SPI_Transaction transaction;     /* SPI transaction structure */
    uint32_t        xferEnable,len,loop = 1;
#ifndef SPI_DMA_ENABLE
    uint32_t        txBuf, rxBuf;
#else
    uint32_t        count = 0;
#endif
    uint32_t        terminateXfer = 0;
    bool            retVal;


#ifdef BARE_METAL
    /* Call board init functions */
    Board_initSPI();
#endif

    SPI_v0_HWAttrs spi_cfg;

    /* Get the default UART init configurations */
    SPI_socGetInitCfg(SPI_INSTANCE, &spi_cfg);

    spi_cfg.enableIntr = false;
#ifdef SPI_DMA_ENABLE
    /* Set the DMA related init config */
    spi_cfg.edmaHandle = SPIApp_edmaInit();
    spi_cfg.dmaMode    = TRUE;
    spi_cfg.enableIntr = false;
#endif

    SPI_socSetInitCfg(SPI_INSTANCE, &spi_cfg);

    /* Open the Board flash NOR device with the test SPI port
       and use the default SPI configurations */
    SPI_Params_init(&spiParams);
    spiParams.frameFormat  = SPI_POL0_PHA1;

    /* Init SPI driver */
    SPI_init();

    hwHandle = (SPI_Handle)SPI_open(TEST_SPI_PORT, &spiParams);

    SPI_control(hwHandle,SPI_V0_CMD_LOOPBACK,(void *) &loop);


    if (!hwHandle)
    {
        testPassed = false;
        goto err;
    }

    /* Enable transfer */
    xferEnable = 1;
    SPI_control(hwHandle, SPI_V0_CMD_XFER_ACTIVATE, (void *)&xferEnable);

#ifdef SPI_DMA_ENABLE
    len = sizeof(txBuf);
    for (count = 0; count < len; count++)
    {
        txBuf[count] = 0xA5; /* Test data */
    }

    CacheP_wbInv((void *)txBuf, (int32_t)sizeof(txBuf));
    CacheP_wbInv((void *)rxBuf, (int32_t)sizeof(rxBuf));

    transaction.txBuf = (void *)&txBuf[0];
    transaction.rxBuf = (void *)&rxBuf[0];
#else
    /* Write Command */
    txBuf = 0xA5A5A5A5; /* Test data */
    len = sizeof(txBuf);

    transaction.txBuf = (uint8_t *) &txBuf;
    transaction.rxBuf = (uint8_t *) &rxBuf;
#endif
    transaction.count = len;
    transaction.arg = (void *)&terminateXfer;

    retVal = SPI_transfer(hwHandle, &transaction);

    if (retVal == false)
    {
        testPassed = false;
        goto err;
    }


#ifdef SPI_DMA_ENABLE
    for (count =0; count < len; count++)
    {
        if (txBuf[count] != rxBuf[count])
        {
            testPassed = false;
            break;
        }
    }
    if(false != testPassed)
    {
        SPI_log("\n Rx and Tx data matched. \n");
    }
    else
    {
        SPI_log("\n Rx and Tx data mismatched. \n");
    }
#else
    SPI_log("\n Received Data : %x. \n",rxBuf);
    if (txBuf != rxBuf)
        testPassed = false;
#endif

    SPI_close(hwHandle);



err:
    if(true == testPassed)
    {
        SPI_log("\n All tests have passed. \n");
    }
    else
    {
        SPI_log("\n Some tests have failed. \n");
    }

    while(1);
}

#endif


static void BSP_I2C_Init(void)
{
//    Init_I2C();
//    Board_initI2C();
//    I2C0_open();
}

static void Init_I2C()
{

    // Enable I2C0
    // i2c0�뜝�룞�삕 async2�뜝�룞�삕 �겢�뜝�룞�삕 �뜝�룞�삕�뜝�룞�삕�뜝�룞�삕�뜝�룞�삕�뜝�룞�삕 �겢�뜝�룞�삕�뜝�룞�삕�뜝�룜瑜� �뜝�룞�삕 �뜝�룞�삕 �뜝�룞�삕�뜝�룞�삕.
}

/**************************************************************************************************/
/***        ECAP1 Initialize : Frequecy Chechk                                                  ***/
/**************************************************************************************************/
static void Init_ECAP1(void)
{
    /* ECCTL1 */
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CAP1POL,     RE);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CTRRST1,     RESET);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CAP2POL,     RE);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CTRRST2,     RESET);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CAP3POL,     RE);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CTRRST3,     RESET);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CAP4POL,     RE);
    CSL_FINST(ecap1Regs->ECCTL1,ECAP_ECCTL1_CTRRST4,     RESET);
    CSL_FINS(ecap1Regs->ECCTL1,ECAP_ECCTL1_PRESCALE,     0);
    /* ECCTL2 */
    CSL_FINST(ecap1Regs->ECCTL2,ECAP_ECCTL2_CAP_APWM,    CAPTURE_MODE);          //CSL_ECAP_ECCTL2_CAP_APWM_MASK
    CSL_FINST(ecap1Regs->ECCTL2,ECAP_ECCTL2_CONT_ONESHT, CONTINUOUS);            //CSL_ECAP_ECCTL2_CAP_APWM_MASK
    CSL_FINST(ecap1Regs->ECCTL2,ECAP_ECCTL2_SYNCI_EN,    DISABLE);               //CSL_ECAP_ECCTL2_SYNCI_EN_MASK
    CSL_FINST(ecap1Regs->ECCTL2,ECAP_ECCTL2_SYNCO_SEL,   DISABLE1);              //CSL_ECAP_ECCTL2_SYNCO_SEL_MASK
    CSL_FINST(ecap1Regs->ECCTL2,ECAP_ECCTL2_TSCTRSTOP,   FREE_RUNNING);          //CSL_ECAP_ECCTL2_TSCTRSTOP_MASK
}

/**************************************************************************************************/
/***        ECAP2 Initialize : LCD Contrast                                                     ***/
/**************************************************************************************************/
static void Init_ECAP2(void)
{
    /* ECCTL2 */
    CSL_FINST(ecap2Regs->ECCTL2,ECAP_ECCTL2_CAP_APWM,   APWM_MODE);             //CSL_ECAP_ECCTL2_CAP_APWM_MASK
    CSL_FINST(ecap2Regs->ECCTL2,ECAP_ECCTL2_APWMPOL,    ACTIVE_HIGH);           //CSL_ECAP_ECAP_ECCTL2_APWMPOL_MASK
    CSL_FINST(ecap2Regs->ECCTL2,ECAP_ECCTL2_SYNCI_EN,   DISABLE);               //CSL_ECAP_ECCTL2_SYNCI_EN_MASK
    CSL_FINST(ecap2Regs->ECCTL2,ECAP_ECCTL2_SYNCO_SEL,  DISABLE1);              //CSL_ECAP_ECCTL2_SYNCO_SEL_MASK
    CSL_FINST(ecap2Regs->ECCTL2,ECAP_ECCTL2_TSCTRSTOP,  FREE_RUNNING);          //CSL_ECAP_ECCTL2_TSCTRSTOP_MASK

    /* CAP1 - 228Hz */
    ecap2Regs->CAP1   = LCD_CONTRAST_PWM_APRD;                  //CSL_ECAP_CAP1_CAP1_MASK
    /* CAP2 - duty  */
    ecap2Regs->CAP2   = 0 *LCD_CONTRAST_MUL;  //CSL_ECAP_CAP2_CAP2_MASK
    /* CTRPHS */
    ecap2Regs->CTRPHS = 0x0;                                      //CSL_ECAP_CTRPHS_CTRPHS_MASK
}

static void LCDContrastSet(unsigned short val)
{
    unsigned int    u32_SetVal;

    u32_SetVal = (((unsigned int)val)&0x0000FFFF) * LCD_CONTRAST_MUL;
    ecap2Regs->CAP2 = u32_SetVal;                               //CSL_ECAP_CAP4_CAP4_MASK
}

/**************************************************************************************************/
/***        ECAP2 Initialize : LCD Contrast                                                     ***/
/**************************************************************************************************/
static void Init_ECAP(void)
{
    // Enable ECAP
    psc1Regs->MDCTL[CSL_PSC_ECAP-CSL_PSC_EDMA_CC1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
    // move ECAP PSC to Next state
    psc1Regs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );  // Power group Always ON
    // wait for transition
    while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_ECAP-CSL_PSC_EDMA_CC1], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );

    Init_ECAP1();   /* ECAP */

    Init_ECAP2();   /* EPWM */
}

static void Init_EPWM()
{
    // Enable EPWM
    psc1Regs->MDCTL[CSL_PSC_EPWM-CSL_PSC_EDMA_CC1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
    // move EPWM PSC to Next state
    psc1Regs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );  // Power group Always ON
    // wait for transition
    while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_EPWM-CSL_PSC_EDMA_CC1], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );

    /* Enable PWM Clock in chip config reg 1 */
    CSL_FINST( sysRegs->CFGCHIP1, SYSCFG_CFGCHIP1_TBCLKSYNC, ENABLE);
    // Configure EPWM1 with the DSP CPU
    CSL_FINST( sysRegs->SUSPSRC, SYSCFG_SUSPSRC_EPWM1SRC, DSP);

}

static void Board_initI2C(void)
{
//    I2C_HwAttrs   i2c_cfg;

    /* Get the default I2C init configurations */
//    I2C_socGetInitCfg(I2C_TOUCH_INSTANCE, &i2c_cfg);

    /* Modify the default I2C configurations if necessary */
    //i2c_cfg.enableIntr = true;

    /* Set the default I2C init configurations */
//    I2C_socSetInitCfg(I2C_TOUCH_INSTANCE, &i2c_cfg);

    /* I2C open�뜝�룞�삕 Bios start�뜝�룞�삕�뜝�떇琉꾩삕 �뜝�떛�벝�삕 */
}


static void I2C0_open(void)
{
//    I2C_Params i2cParams;
    /* uint32_t i2cRecover; */

//    I2C_init();

//    I2C_Params_init(&i2cParams);
//    i2cParams.transferMode = I2C_MODE_BLOCKING;
//    i2cHandle = I2C_open(I2C_TOUCH_INSTANCE, &i2cParams);

    /*i2cRecover = 1;
    I2C_control (i2cHandle, I2C_CMD_RECOVER_BUS, &i2cRecover);*/
}


static void Init_SPI()
{

    // Enable DMA
    psc1Regs->MDCTL[CSL_PSC_EDMA_CC1-CSL_PSC_EDMA_CC1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
    // move UART PSC to Next state
    psc1Regs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
    // wait for transition
    while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_EDMA_CC1-CSL_PSC_EDMA_CC1], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );


    psc1Regs->MDCTL[CSL_PSC_EDMA_TC2-CSL_PSC_EDMA_CC1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
    // move UART PSC to Next state
    psc1Regs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
    // wait for transition
    while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_EDMA_TC2-CSL_PSC_EDMA_CC1], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );

    // Enable SPI1
    // deassert UART local PSC reset and set NEXT state to ENABLE
    psc1Regs->MDCTL[CSL_PSC_SPI1-CSL_PSC_EDMA_CC1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
    // move UART PSC to Next state
    psc1Regs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
    // wait for transition
    while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_SPI1-CSL_PSC_EDMA_CC1], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );
	
}


//Board_initCfg boardCfg;
static void Board_initSPI(void)
{
    SPI_v0_HWAttrs spi_cfg;
	
	
    /* Get the default SPI init configurations */
//    SPI_socGetInitCfg(SPI_PORT_USE, &spi_cfg); // from NX100
    SPI_socGetInitCfg(TEST_SPI_PORT, &spi_cfg);  // from PDK

    /* Modify the default SPI configurations if necessary */
    spi_cfg.enableIntr = false;
//    spi_cfg.inputClkFreq = 456000000U/2U;
    spi_cfg.inputClkFreq = XB100_SYS_CLOCK/SPI_MODULE_CLOCK_DIVIDER;  // PDK_OMAPL138 defines SPI_MODULE_CLOCK_DIVIDER as 6U

    /* Set the default SPI init configurations */
//    SPI_socSetInitCfg(SPI_PORT_USE, &spi_cfg);  // form NX100
    SPI_socSetInitCfg(TEST_SPI_PORT, &spi_cfg); // from PDK
    /* Init SPI driver */
//    SPI_init(); should be called after definition of SPI instance in main function

}

static void Spi1_open() 
{
/*
    //* Open the Board flash NOR device with the test SPI port
       and use the default SPI configurations 
    SPI_Params_init(&spiParams);
    spiParams.transferMode  = SPI_MODE_BLOCKING;
    spiParams.frameFormat  = SPI_POL1_PHA0;
    spiParams.bitRate = 1500000;

    spiHwHandle = (SPI_Handle)SPI_open(SPI_PORT_USE, &spiParams);

    if (!spiHwHandle)
    {
        printf ( "SPI open Error\n");
        return;
    }

    // Enable transfer 
    spiXferEnable = 1;
    SPI_control(spiHwHandle, SPI_V0_CMD_XFER_ACTIVATE, (void *)&spiXferEnable);
*/

}

static void Init_PLL0()
{
    volatile uint32_t delay = 0;
    uint32_t clkmode = 0;
    uint32_t pllm = 18;
    uint32_t postdiv = 0;   // 456MHz
    uint32_t plldiv1 = 0;   // 456MHz (DSP)
    uint32_t plldiv2 = 1;   // 228MHz (UART,EPWM,ECAP)
    uint32_t plldiv3 = 11;  // 38MHz (EMMIF)
    uint32_t plldiv7 = 5;   // 76Mhz (EMAC)

   /* Clear PLL lock bit */
   sysRegs->CFGCHIP0 &= ~(0x00000010);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   pll0Regs->PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   pll0Regs->PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   pll0Regs->PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(delay = 0; delay < PLLEN_MUX_SWITCH; delay++) {;}

   /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
   pll0Regs->PLLCTL &= 0xFFFFFEFF;
   pll0Regs->PLLCTL |= (clkmode << 8);

   /*Clear PLLRST bit to reset the PLL */
   pll0Regs->PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   pll0Regs->PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   pll0Regs->PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   pll0Regs->PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(delay = 0; delay < PLL_STABILIZATION_TIME; delay++) {;}

   /*Program the required multiplier value in PLLM*/
   pll0Regs->PLLM    = pllm;

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   pll0Regs->POSTDIV = 0x8000 | postdiv;

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while((pll0Regs->PLLSTAT & 0x1) == 1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   pll0Regs->PLLDIV1 = 0x8000 | plldiv1;             // Fixed Ratio /1
   pll0Regs->PLLDIV2 = 0x8000 | plldiv2;             // Fixed Ratio /2
   pll0Regs->PLLDIV4 = 0x8000 | (((plldiv1+1)*4)-1); // Fixed Ratio /4
   pll0Regs->PLLDIV6 = 0x8000 | plldiv1;             // Fixed Ratio /1
   pll0Regs->PLLDIV3 = 0x8000 | plldiv3;             // Variable Ratio (EMIF)
   pll0Regs->PLLDIV7 = 0x8000 | plldiv7;             // Variable Ratio (RMII)


   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   pll0Regs->PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while((pll0Regs->PLLSTAT & 0x1) == 1) { }

   /*Wait for PLL to reset properly.*/
   for(delay = 0; delay < PLL_RESET_TIME_CNT; delay++) {;}

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   pll0Regs->PLLCTL |= 0x8;

   /*Wait for PLL to lock.*/
   for(delay = 0; delay < PLL_LOCK_TIME_CNT; delay++) {;}

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   pll0Regs->PLLCTL |=  0x1;

}

/*=========================================================================*/
/*                             GLOBAL FUNCTIONS                            */
/*=========================================================================*/

void DeviceInit()
{
    // Open Permissions to SYSCFG Registers
    CSL_FINS(sysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK0_KEY);
    CSL_FINS(sysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK1_KEY);

    Init_PLL0();

    PIN_Init();   // initialize Pin_mux

    Peripheral_Init();  // initialize GPIO, EMIFA, LED, SPI, I2C, ECAP, Serial Port

}


void Peripheral_Init()
{
    Init_Gpio ();
    Init_EMIFA ();                        //     BSP_NandFlash_Init();    Initialize NandFlash
    //BSP_Reset_Init();                   // Initialize Reset Pin


    BSP_LED_Init();                       // Initialize the GPIOs for application
//    BSP_DIO_Init();                     //

    BSP_SPI_Init();                       // Initialize SPI Configuration Pin
    BSP_I2C_Init();                       // Initialize I2C Configuration Pin

    WD_OUT_HIGH;                          //    BSP_WD_Check_Init();      Initialize Watchdog Input & Output Pin
//    BSP_PwrFail_Init();                 // Initialize Power Fail Input Pin
    Init_ECAP();                          // Measure Frequency / LCD Backlight

}

