Schedule a Multi-Rate Controller for a Permanent Magnet Synchronous Machine
This example shows how to create a real-time executable for a Texas Instruments F28335 embedded target. You will build upon the algorithm specified in the Embedded Coder example "Field-Oriented Control of Permanent Magnet Synchronous Machine" by adding timing and peripheral specifications. You will learn a conventional technique for scheduling the multi-rate algorithm using a periodic rate initiated from the default base rate timer. You will also learn an advanced technique to schedule the algorithm based on the periodic end-of-conversion event for an ADC.
Required hardware:
- Spectrum Digital® F28335 eZdsp board
- Digital Motor Controller board: Spectrum Digital DM550
- Three-phase Permanent Magnet Synchronous Motor with quadrature encoder
Note: Match the characteristics of the power supply and the amplifier with the input characteristics of the selected motor.
Contents
Introduction
The goal is to create a real-time executable for a Spectrum Digital F28335 eZdsp and schedule controller execution using an ADC end-of-conversion interrupt. This goal will be achieved in three steps. First, you will learn how to configure the multi-rate controller model to create an archive library for an F28335 processor. Then, you will then learn how to create a model that specifies peripherals and schedules the algorithm using the base rate timer. Finally, you will learn an advanced technique in which you specify that the controller and peripherals are scheduled by a periodic ADC end-of-conversion interrupt.
This example builds upon the controller algorithm specified in the Embedded Coder example "Field-Oriented Control of Permanent Magnet Synchronous Machine". Refer to that example to explore how the controller algorithm behaves during system simulation with a model of a Permanent Magnet Synchronous Machine.
Configure Controller to Generate an Archive Library
To facilitate transitioning between simulation and code generation phases of a design, the controller algorithm is specified in its own model and referenced from a model which specifies embedded scheduling and peripherals. We introduced the controller algorithm in the example "Field-Oriented Control of Permanent Magnet Synchronous Machine". Because we are using the controller algorithm with an embedded target, we have configured the controller algorithm model for the target hardware and configured it to generate an archive library using the "Coder Target" pane of the model "Configuration Parameters" dialog.
Schedule Controller using Base Rate Timer
In this section, you will explore a model which shows a basic technique for connecting peripherals to a multi-rate controller algorithm. A hardware interrupt is used to detect an encoder index, then this signal is then fed into the controller which is specified in the Controller_And_Peripherals subsystem.
Within the Controller_And_Peripherals subsystem, the ePWM1 block is configured to trigger the ADC conversion so that sampling does not occur during a PWM edge transition (thus minimizing noise on the sampled signal). The controller model is referenced using a Model Block configured to c28335_pmsmfoc. The controller is scheduled using the default base rate timer for the F28335 (CPU Timer 0).
This model showed a basic technique for adding peripherals and scheduling the controller using the base rate timer interrupt.
Schedule Controller using ADC End-of-Conversion Interrupt
In the previous section, the ADC end-of-conversion and periodic reading of the ADC register are not synchronized. Although this is a good starting point for learning how to use the target, in many motor control applications it is desirable to synchronize the controller with the ADC end-of-interrupt conversion. This provides the shortest and most deterministic delay between the ADC conversion and the new values of PWM duty cycles. If the controller can execute properly with inherited sample times, the controller can be placed within a function called “subsystem" and attached to a Hardware Interrupt block configured to generate an interrupt at the ADC end-of-conversion. In this example, the controller algorithm is multi-rate and sample time dependent. It would require non-trivial effort to modify the model to be sample time independent. In this section, you will learn an advanced technique for scheduling the multi-rate controller algorithm using the ADC end-of-conversion interrupt instead of the base rate interrupt.
The model c28335_pmsmfoc_adcinterrupt uses custom code blocks to execute the controller and peripherals based on the ADC end-of-conversion interrupt. From the top level, the model appears structurally similar to the c28335_pmsmfoc_baseratetimer model with the addition of another function call trigger, ADC_INT, output from the Hardware Interrupt block. At this level, you will find a custom code block that will stop CPU timer 1 at startup on the F28335. CPU timer 1 is used by default to trigger the Simulink scheduler. The scheduler will be triggered by the ADC interrupt as described below.
The ADC_Interrupt_Service_Routine subsystem contains only a custom code block that calls rt_OneStep(). This function triggers to the main Simulink scheduler.
This model showed an advanced technique for scheduling a multi-rate controller algorithm using an ADC end-of-conversion interrupt. This technique is valid for this example because we have configured the model to generate the ADC end-of-conversion interrupt at the same periodic rate as the sample time specified in the controller algorithm. If you do not ensure this sampling consistency, the behavior of generated code will be different than that of simulation. This technique should only be applied when it is difficult or undesirable to convert the controller algorithm to be sample time independent.
Conclusion
This example showed how to create a real-time executable for a Texas Instruments F28335 embedded target. Two techniques for scheduling a multi-rate controller algorithm were presented. The first technique used a common timer-based approach, which is sufficient for applications where the controller can be associated with the default CPU Timer 0 base interrupt. The second technique used custom code blocks to associate a controller with a periodic hardware interrupt service routine. This technique requires that the designer has configured the hardware to generate a periodic interrupt with the same rate as the fastest rate specified in the controller.