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Data structure defines the MCAN Message RAM Configuration Parameters. Message RAM can contain following sections: Standard ID filters, Extended ID filters, TX FIFO(or TX Q), TX Buffers, TX EventFIFO, RX FIFO0, RX FIFO1, RX Buffer. Note: If particular section in the RAM is not used then it's size should be initialized to '0' (Number of buffers in case of Tx/Rx buffer). More...
#include <drivers/canfd/include/canfd_internal.h>
Data Fields | |
| uint32_t | flssa |
| uint32_t | lss |
| uint32_t | flesa |
| uint32_t | lse |
| uint32_t | txStartAddr |
| uint32_t | txBufNum |
| uint32_t | txFIFOSize |
| uint32_t | txBufMode |
| uint32_t | txBufElemSize |
| uint32_t | txEventFIFOStartAddr |
| uint32_t | txEventFIFOSize |
| uint32_t | txEventFIFOWaterMark |
| uint32_t | rxFIFO0startAddr |
| uint32_t | rxFIFO0size |
| uint32_t | rxFIFO0waterMark |
| uint32_t | rxFIFO0OpMode |
| uint32_t | rxFIFO1startAddr |
| uint32_t | rxFIFO1size |
| uint32_t | rxFIFO1waterMark |
| uint32_t | rxFIFO1OpMode |
| uint32_t | rxBufStartAddr |
| uint32_t | rxBufElemSize |
| uint32_t | rxFIFO0ElemSize |
| uint32_t | rxFIFO1ElemSize |
Data structure defines the MCAN Message RAM Configuration Parameters. Message RAM can contain following sections: Standard ID filters, Extended ID filters, TX FIFO(or TX Q), TX Buffers, TX EventFIFO, RX FIFO0, RX FIFO1, RX Buffer. Note: If particular section in the RAM is not used then it's size should be initialized to '0' (Number of buffers in case of Tx/Rx buffer).
| uint32_t MCAN_MsgRAMConfigParams_t::flesa |
Extended ID Filter List Start Address
| uint32_t MCAN_MsgRAMConfigParams_t::flssa |
Standard ID Filter List Start Address
| uint32_t MCAN_MsgRAMConfigParams_t::lse |
List Size: Extended ID 0 - No standard Message ID filter 1-64 - Number of standard Message ID filter elements others - Values greater than 64 are interpreted as 64
| uint32_t MCAN_MsgRAMConfigParams_t::lss |
List Size: Standard ID 0 - No standard Message ID filter 1-127 - Number of standard Message ID filter elements others - Values greater than 128 are interpreted as 128
| uint32_t MCAN_MsgRAMConfigParams_t::rxBufElemSize |
Rx Buffer Element Size
| uint32_t MCAN_MsgRAMConfigParams_t::rxBufStartAddr |
Rx Buffer Start Address
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO0ElemSize |
Rx FIFO0 Element Size
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO0OpMode |
Rx FIFO0 Operation Mode 0 - FIFO blocking mode 1 - FIFO overwrite mode
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO0size |
Rx FIFO0 Size 0 - No Rx FIFO 1-64 - Number of Rx FIFO elements others - Values greater than 64 are interpreted as 64
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO0startAddr |
Rx FIFO0 Start Address
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO0waterMark |
Rx FIFO0 Watermark 0 - Watermark interrupt disabled 1-63 - Level for Rx FIFO 0 watermark interrupt others - Watermark interrupt disabled
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO1ElemSize |
Rx FIFO1 Element Size
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO1OpMode |
Rx FIFO1 Operation Mode 0 - FIFO blocking mode 1 - FIFO overwrite mode
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO1size |
Rx FIFO1 Size 0 - No Rx FIFO 1-64 - Number of Rx FIFO elements others - Values greater than 64 are interpreted as 64
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO1startAddr |
Rx FIFO1 Start Address
| uint32_t MCAN_MsgRAMConfigParams_t::rxFIFO1waterMark |
Rx FIFO1 Watermark 0 - Watermark interrupt disabled 1-63 - Level for Rx FIFO 1 watermark interrupt others - Watermark interrupt disabled
| uint32_t MCAN_MsgRAMConfigParams_t::txBufElemSize |
Tx Buffer Element Size
| uint32_t MCAN_MsgRAMConfigParams_t::txBufMode |
Tx FIFO/Queue Mode 0 - Tx FIFO operation 1 - Tx Queue operation
| uint32_t MCAN_MsgRAMConfigParams_t::txBufNum |
Number of Dedicated Transmit Buffers 0 - No Dedicated Tx Buffers 1-32 - Number of Dedicated Tx Buffers others - Values greater than 32 are interpreted as 32
| uint32_t MCAN_MsgRAMConfigParams_t::txEventFIFOSize |
Event FIFO Size 0 - Tx Event FIFO disabled 1-32 - Number of Tx Event FIFO elements others - Values greater than 32 are interpreted as 32
| uint32_t MCAN_MsgRAMConfigParams_t::txEventFIFOStartAddr |
Tx Event FIFO Start Address
| uint32_t MCAN_MsgRAMConfigParams_t::txEventFIFOWaterMark |
Tx Event FIFO Watermark 0 - Watermark interrupt disabled 1-32 - Level for Tx Event FIFO watermark interrupt others - Watermark interrupt disabled
| uint32_t MCAN_MsgRAMConfigParams_t::txFIFOSize |
Transmit FIFO/Queue Size 0 - No Tx FIFO/Queue 1-32 - Number of Tx Buffers used for Tx FIFO/Queue others - Values greater than 32 are interpreted as 32
| uint32_t MCAN_MsgRAMConfigParams_t::txStartAddr |
Tx Buffers Start Address