/******************************************************************************* * File: cla_hv_task.cla *******************************************************************************/ /******************************************************************************* * File: cla_hal.h * * Purpose: Hardware Abstraction Layer for the CLA code. Because the CLA does * not support multiple functions for a single task, separating the * application from the hardware can only be done using #defines. * * History: 2017-Aug-30 PF Initial creation of this file. *******************************************************************************/ /******************************************************************************* * File: hardware_defs.h * * History: 2017-Aug-17 PF Initial creation of this file. * 2017-Aug-17 PF Added selection for SCR2 versus APM control. * 2017-Aug-21 PF Added more board and memory type controls. *******************************************************************************/ /****************************** * Defines for target system. *****************************/ /* 100MHz = 10nS per CPU clock cycle. This must match the PLL output (system clock). */ /* The C2000 development board and our OBC have some hardware differences, as follows. * * Main clock: * C2000 development board uses external 20MHz crystal. * OBC uses external 10MHz ceramic resonator. * * ADC reference: * C2000 development board uses internal 3.3V reference. * OBC uses external 3V reference. */ /* There are two different OBC boards: one (which is used twice) which has unidirectional * conversion and two possible AC input lines, and one (which is used once) which has * bidirectional conversion and one possible AC input line. ePWM channels 6 & 7 change * their definition depending on whether or not the board is uni- or bi- directional * conversion capable. Channel 7 is only used on the bidirectional board, channel 6 is * SCR control on the unidirectional board and paired with channel 7 on the bidirectional * board. In bidirectional mode channels 6 and 7 perform a DC-to-AC conversion, similar * to how channels 4 and 5 behave in unidirectional mode. */ /* The following defines the target memory. When using the TI debugger the code * is normally written directly to RAM for execution (Flash ROM is ignored). When * operating out of Flash ROM (whether for debugging or for normal execution) some * Flash to RAM copying of functions that cannot or should not be executed out of * ROM is required. IMPORTANT - This must match the linker command file selected * in the build settings. */ /* The following enables GPIO27 as an output so testing without external hardware can * be done. This pin is normally an input, and is the external trigger input for * PWM channels 1 and 4 (EXTSYNCIN1). */ /* The following changes GPIO16 to be XLCKOUT instead of PWM5A. This is * only used for diagnostics. */ /* The following enables the diagnostic test pins and LEDs. This is * only used for diagnostics. */ /* The following assigns test pins to the CLA. */ /******************* * Error checking. ******************/ /* Make sure #defines that drive what system we are on are defined. */ /* The following is for some legacy source code from TI. */ //########################################################################### // // FILE: F28004x_device.h // // TITLE: F28004x Device Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### // // Common CPU Definitions: // // // There are only two assembly instructions that can access the MSTF register // - MMOV32 mem32, MSTF // - MMOV32 mem32, MSTF // The CLA C compiler allows 'C' access to this control register through the __cregister // keyword. In order to access the register's contents, the user must copy it to the // shadow object defined below // Note that _MSTF is the only __cregister recognized by the CLA C compiler; IER and IFR // are not accessible (therefore not recognized), therefore __cregister must be redefined to // null to prevent a cla C compiler error // struct MSTF_SHADOW_BITS { // bits description unsigned short LVF:1; // 0 Latched Overflow Flag unsigned short LUF:1; // 1 Latched Underflow Flag unsigned short NF:1; // 2 Negative Float Flag unsigned short ZF:1; // 3 Zero Float Flag unsigned short rsvd1:2; // 5:4 Reserved unsigned short TF:1; // 6 Test Flag unsigned short rsvd2:2; // 8:7 Reserved unsigned short RNDF32:1; // 9 Rounding Mode unsigned short rsvd3:1; // 10 Reserved unsigned short MEALLOW:1; // 11 MEALLOW Status unsigned short RPCL:4; // 15:12 Return PC: Low Portion unsigned short RPCH:12; // 27:16 Return PC: High Portion unsigned short rsvd4:4; // 31:28 Reserved }; extern __cregister volatile unsigned int MSTF; extern volatile unsigned int IFR; extern volatile unsigned int IER; // // For Portability, User Is Recommended To Use the C99 Standard integer types // /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /*****************************************************************************/ /* stddef.h v16.9.3 */ /* */ /* Copyright (c) 1993-2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ typedef int ptrdiff_t; typedef unsigned int size_t; typedef unsigned short wchar_t; #pragma diag_push #pragma CHECK_MISRA("-19.10") /* need types as macro arguments */ #pragma diag_pop #pragma diag_push #pragma CHECK_MISRA("-19.15") /* code outside guard; see below comment */ /*-----------------------------------------------------------------------*/ /* Define _win_t, for compiling GCC libraries with the TI compiler. */ /* GCC's library (newlib) expects wint_t to be defined here, in stddef.h,*/ /* which is arguably incorrect, but we go along for compatibility. */ /* This is outside the _STDDEF guard in case this file has already */ /* been included without __need_wint_t. */ /*-----------------------------------------------------------------------*/ #pragma diag_pop /*****************************************************************************/ /* STDINT.H v16.9.3 */ /* */ /* Copyright (c) 2002-2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /* 7.18.1.1 Exact-width integer types */ typedef short int16_t; typedef unsigned short uint16_t; typedef int int32_t; typedef unsigned int uint32_t; /* 7.18.1.2 Minimum-width integer types */ typedef int16_t int_least8_t; typedef uint16_t uint_least8_t; typedef int16_t int_least16_t; typedef uint16_t uint_least16_t; typedef int32_t int_least32_t; typedef uint32_t uint_least32_t; /* sorry, [u]int_least64_t not implemented for C27X, CLA */ /* 7.18.1.3 Fastest minimum-width integer types */ typedef int32_t int_fast8_t; typedef uint32_t uint_fast8_t; typedef int32_t int_fast16_t; typedef uint32_t uint_fast16_t; typedef int32_t int_fast32_t; typedef uint32_t uint_fast32_t; /* sorry, [u]int_fast64_t not implemented for C27X, CLA */ /* 7.18.1.4 Integer types capable of holding object pointers */ typedef short intptr_t; typedef unsigned short uintptr_t; /* 7.18.1.5 Greatest-width integer types */ typedef long intmax_t; typedef unsigned long uintmax_t; /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ /* 7.18.2 Limits of specified width integer types */ /* 7.18.3 Limits of other integer types */ /* 7.18.4.1 Macros for minimum-width integer constants */ /* There is a defect report filed against the C99 standard concerning how the (U)INTN_C macros should be implemented. Please refer to -- http://wwwold.dkuug.dk/JTC1/SC22/WG14/www/docs/dr_209.htm for more information. These macros are implemented according to the suggestion given at this web site. */ /* 7.18.4.2 Macros for greatest-width integer constants */ // // C99 defines boolean type to be _Bool, but this doesn't match the format of // the other standard integer types. bool_t has been defined to fill this gap. // typedef _Bool bool_t; // // Used for a bool function return status // typedef _Bool status_t; // // The following data types are included for compatibility with legacy code, // they are not recommended for use in new software. Please use the C99 // types included above // typedef short int16; typedef long int32; typedef unsigned char Uint8; typedef unsigned short Uint16; typedef unsigned long Uint32; typedef float float32; typedef long double float64; typedef struct { Uint32 low32; Uint32 high32; } Uint64; typedef struct { int32 low32; int32 high32; } int64; // // The following data types are for use with byte addressable peripherals. // See compiler documentation on the byte_peripheral type attribute. // // // Include All Peripheral Header Files: // //########################################################################### // // FILE: f28004x_adc.h // // TITLE: ADC Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ADC Individual Register Bit Definitions: struct ADCCTL1_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position Uint16 rsvd2:4; // 6:3 Reserved Uint16 ADCPWDNZ:1; // 7 ADC Power Down Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel Uint16 rsvd3:1; // 12 Reserved Uint16 ADCBSY:1; // 13 ADC Busy Uint16 rsvd4:2; // 15:14 Reserved }; union ADCCTL1_REG { Uint16 all; struct ADCCTL1_BITS bit; }; struct ADCCTL2_BITS { // bits description Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:5; // 12:8 Reserved Uint16 rsvd5:3; // 15:13 Reserved }; union ADCCTL2_REG { Uint16 all; struct ADCCTL2_BITS bit; }; struct ADCBURSTCTL_BITS { // bits description Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select Uint16 rsvd1:2; // 7:6 Reserved Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select Uint16 rsvd2:3; // 14:12 Reserved Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable }; union ADCBURSTCTL_REG { Uint16 all; struct ADCBURSTCTL_BITS bit; }; struct ADCINTFLG_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTFLG_REG { Uint16 all; struct ADCINTFLG_BITS bit; }; struct ADCINTFLGCLR_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTFLGCLR_REG { Uint16 all; struct ADCINTFLGCLR_BITS bit; }; struct ADCINTOVF_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTOVF_REG { Uint16 all; struct ADCINTOVF_BITS bit; }; struct ADCINTOVFCLR_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTOVFCLR_REG { Uint16 all; struct ADCINTOVFCLR_BITS bit; }; struct ADCINTSEL1N2_BITS { // bits description Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select Uint16 rsvd1:1; // 4 Reserved Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable Uint16 rsvd2:1; // 7 Reserved Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select Uint16 rsvd3:1; // 12 Reserved Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCINTSEL1N2_REG { Uint16 all; struct ADCINTSEL1N2_BITS bit; }; struct ADCINTSEL3N4_BITS { // bits description Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select Uint16 rsvd1:1; // 4 Reserved Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable Uint16 rsvd2:1; // 7 Reserved Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select Uint16 rsvd3:1; // 12 Reserved Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCINTSEL3N4_REG { Uint16 all; struct ADCINTSEL3N4_BITS bit; }; struct ADCSOCPRICTL_BITS { // bits description Uint16 SOCPRIORITY:5; // 4:0 SOC Priority Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer Uint16 rsvd1:6; // 15:10 Reserved }; union ADCSOCPRICTL_REG { Uint16 all; struct ADCSOCPRICTL_BITS bit; }; struct ADCINTSOCSEL1_BITS { // bits description Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select }; union ADCINTSOCSEL1_REG { Uint16 all; struct ADCINTSOCSEL1_BITS bit; }; struct ADCINTSOCSEL2_BITS { // bits description Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select }; union ADCINTSOCSEL2_REG { Uint16 all; struct ADCINTSOCSEL2_BITS bit; }; struct ADCSOCFLG1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag }; union ADCSOCFLG1_REG { Uint16 all; struct ADCSOCFLG1_BITS bit; }; struct ADCSOCFRC1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit }; union ADCSOCFRC1_REG { Uint16 all; struct ADCSOCFRC1_BITS bit; }; struct ADCSOCOVF1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag }; union ADCSOCOVF1_REG { Uint16 all; struct ADCSOCOVF1_BITS bit; }; struct ADCSOCOVFCLR1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit }; union ADCSOCOVFCLR1_REG { Uint16 all; struct ADCSOCOVFCLR1_BITS bit; }; struct ADCSOC0CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC0CTL_REG { Uint32 all; struct ADCSOC0CTL_BITS bit; }; struct ADCSOC1CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC1CTL_REG { Uint32 all; struct ADCSOC1CTL_BITS bit; }; struct ADCSOC2CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC2CTL_REG { Uint32 all; struct ADCSOC2CTL_BITS bit; }; struct ADCSOC3CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC3CTL_REG { Uint32 all; struct ADCSOC3CTL_BITS bit; }; struct ADCSOC4CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC4CTL_REG { Uint32 all; struct ADCSOC4CTL_BITS bit; }; struct ADCSOC5CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC5CTL_REG { Uint32 all; struct ADCSOC5CTL_BITS bit; }; struct ADCSOC6CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC6CTL_REG { Uint32 all; struct ADCSOC6CTL_BITS bit; }; struct ADCSOC7CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC7CTL_REG { Uint32 all; struct ADCSOC7CTL_BITS bit; }; struct ADCSOC8CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC8CTL_REG { Uint32 all; struct ADCSOC8CTL_BITS bit; }; struct ADCSOC9CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC9CTL_REG { Uint32 all; struct ADCSOC9CTL_BITS bit; }; struct ADCSOC10CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC10CTL_REG { Uint32 all; struct ADCSOC10CTL_BITS bit; }; struct ADCSOC11CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC11CTL_REG { Uint32 all; struct ADCSOC11CTL_BITS bit; }; struct ADCSOC12CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC12CTL_REG { Uint32 all; struct ADCSOC12CTL_BITS bit; }; struct ADCSOC13CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC13CTL_REG { Uint32 all; struct ADCSOC13CTL_BITS bit; }; struct ADCSOC14CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC14CTL_REG { Uint32 all; struct ADCSOC14CTL_BITS bit; }; struct ADCSOC15CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:5; // 24:20 SOC Trigger Source Select Uint16 rsvd3:7; // 31:25 Reserved }; union ADCSOC15CTL_REG { Uint32 all; struct ADCSOC15CTL_BITS bit; }; struct ADCEVTSTAT_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTSTAT_REG { Uint16 all; struct ADCEVTSTAT_BITS bit; }; struct ADCEVTCLR_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTCLR_REG { Uint16 all; struct ADCEVTCLR_BITS bit; }; struct ADCEVTSEL_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTSEL_REG { Uint16 all; struct ADCEVTSEL_BITS bit; }; struct ADCEVTINTSEL_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTINTSEL_REG { Uint16 all; struct ADCEVTINTSEL_BITS bit; }; struct ADCCOUNTER_BITS { // bits description Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value Uint16 rsvd1:4; // 15:12 Reserved }; union ADCCOUNTER_REG { Uint16 all; struct ADCCOUNTER_BITS bit; }; struct ADCREV_BITS { // bits description Uint16 TYPE:8; // 7:0 ADC Type Uint16 REV:8; // 15:8 ADC Revision }; union ADCREV_REG { Uint16 all; struct ADCREV_BITS bit; }; struct ADCOFFTRIM_BITS { // bits description Uint16 OFFTRIM:12; // 11:0 ADC Offset Trim Uint16 rsvd1:4; // 15:12 Reserved }; union ADCOFFTRIM_REG { Uint16 all; struct ADCOFFTRIM_BITS bit; }; struct ADCPPB1CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB1CONFIG_REG { Uint16 all; struct ADCPPB1CONFIG_BITS bit; }; struct ADCPPB1STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB1STAMP_REG { Uint16 all; struct ADCPPB1STAMP_BITS bit; }; struct ADCPPB1OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB1OFFCAL_REG { Uint16 all; struct ADCPPB1OFFCAL_BITS bit; }; struct ADCPPB1TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB1TRIPHI_REG { Uint32 all; struct ADCPPB1TRIPHI_BITS bit; }; struct ADCPPB1TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB1TRIPLO_REG { Uint32 all; struct ADCPPB1TRIPLO_BITS bit; }; struct ADCPPB2CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB2CONFIG_REG { Uint16 all; struct ADCPPB2CONFIG_BITS bit; }; struct ADCPPB2STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB2STAMP_REG { Uint16 all; struct ADCPPB2STAMP_BITS bit; }; struct ADCPPB2OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB2OFFCAL_REG { Uint16 all; struct ADCPPB2OFFCAL_BITS bit; }; struct ADCPPB2TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB2TRIPHI_REG { Uint32 all; struct ADCPPB2TRIPHI_BITS bit; }; struct ADCPPB2TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB2TRIPLO_REG { Uint32 all; struct ADCPPB2TRIPLO_BITS bit; }; struct ADCPPB3CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB3CONFIG_REG { Uint16 all; struct ADCPPB3CONFIG_BITS bit; }; struct ADCPPB3STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB3STAMP_REG { Uint16 all; struct ADCPPB3STAMP_BITS bit; }; struct ADCPPB3OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB3OFFCAL_REG { Uint16 all; struct ADCPPB3OFFCAL_BITS bit; }; struct ADCPPB3TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB3TRIPHI_REG { Uint32 all; struct ADCPPB3TRIPHI_BITS bit; }; struct ADCPPB3TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB3TRIPLO_REG { Uint32 all; struct ADCPPB3TRIPLO_BITS bit; }; struct ADCPPB4CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB4CONFIG_REG { Uint16 all; struct ADCPPB4CONFIG_BITS bit; }; struct ADCPPB4STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB4STAMP_REG { Uint16 all; struct ADCPPB4STAMP_BITS bit; }; struct ADCPPB4OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB4OFFCAL_REG { Uint16 all; struct ADCPPB4OFFCAL_BITS bit; }; struct ADCPPB4TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB4TRIPHI_REG { Uint32 all; struct ADCPPB4TRIPHI_BITS bit; }; struct ADCPPB4TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block Request Time Stamp }; union ADCPPB4TRIPLO_REG { Uint32 all; struct ADCPPB4TRIPLO_BITS bit; }; struct ADC_REGS { union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register Uint16 rsvd1; // Reserved union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register Uint16 rsvd2; // Reserved union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register Uint16 rsvd3; // Reserved union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register Uint16 rsvd4[2]; // Reserved union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register union ADCREV_REG ADCREV; // ADC Revision Register union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register Uint16 rsvd5[4]; // Reserved union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register Uint16 rsvd6[15]; // Reserved Uint16 ADCINTCYCLE; // ADC Early Interrupt generation cycle Uint16 rsvd7[16]; // Reserved }; struct ADCPPB1RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB1RESULT_REG { Uint32 all; struct ADCPPB1RESULT_BITS bit; }; struct ADCPPB2RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB2RESULT_REG { Uint32 all; struct ADCPPB2RESULT_BITS bit; }; struct ADCPPB3RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB3RESULT_REG { Uint32 all; struct ADCPPB3RESULT_BITS bit; }; struct ADCPPB4RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB4RESULT_REG { Uint32 all; struct ADCPPB4RESULT_BITS bit; }; struct ADC_RESULT_REGS { Uint16 ADCRESULT0; // ADC Result 0 Register Uint16 ADCRESULT1; // ADC Result 1 Register Uint16 ADCRESULT2; // ADC Result 2 Register Uint16 ADCRESULT3; // ADC Result 3 Register Uint16 ADCRESULT4; // ADC Result 4 Register Uint16 ADCRESULT5; // ADC Result 5 Register Uint16 ADCRESULT6; // ADC Result 6 Register Uint16 ADCRESULT7; // ADC Result 7 Register Uint16 ADCRESULT8; // ADC Result 8 Register Uint16 ADCRESULT9; // ADC Result 9 Register Uint16 ADCRESULT10; // ADC Result 10 Register Uint16 ADCRESULT11; // ADC Result 11 Register Uint16 ADCRESULT12; // ADC Result 12 Register Uint16 ADCRESULT13; // ADC Result 13 Register Uint16 ADCRESULT14; // ADC Result 14 Register Uint16 ADCRESULT15; // ADC Result 15 Register union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register }; //--------------------------------------------------------------------------- // ADC External References & Function Declarations: // extern volatile struct ADC_RESULT_REGS AdcaResultRegs; extern volatile struct ADC_RESULT_REGS AdcbResultRegs; extern volatile struct ADC_RESULT_REGS AdccResultRegs; extern volatile struct ADC_REGS AdcaRegs; extern volatile struct ADC_REGS AdcbRegs; extern volatile struct ADC_REGS AdccRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_analogsubsys.h // // TITLE: ANALOGSUBSYS Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ANALOGSUBSYS Individual Register Bit Definitions: struct ANAREFPP_BITS { // bits description Uint16 ANAREFBDIS:1; // 0 Disable ANAREFB Uint16 ANAREFCDIS:1; // 1 Disable ANAREFC Uint16 rsvd1:14; // 15:2 Reserved }; union ANAREFPP_REG { Uint16 all; struct ANAREFPP_BITS bit; }; struct TSNSCTL_BITS { // bits description Uint16 ENABLE:1; // 0 Temperature Sensor Enable Uint16 rsvd1:15; // 15:1 Reserved }; union TSNSCTL_REG { Uint16 all; struct TSNSCTL_BITS bit; }; struct ANAREFCTL_BITS { // bits description Uint16 ANAREFASEL:1; // 0 Analog Reference A Select Uint16 ANAREFBSEL:1; // 1 Analog Reference B Select Uint16 ANAREFCSEL:1; // 2 Analog Reference C Select Uint16 rsvd1:5; // 7:3 Reserved Uint16 ANAREFA2P5SEL:1; // 8 Analog Reference A Select Uint16 ANAREFB2P5SEL:1; // 9 Analog Reference B Select Uint16 ANAREFC2P5SEL:1; // 10 Analog Reference B Select Uint16 rsvd2:5; // 15:11 Reserved }; union ANAREFCTL_REG { Uint16 all; struct ANAREFCTL_BITS bit; }; struct DCDCCTL_BITS { // bits description Uint16 DCDCEN:1; // 0 DCDC Enable Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:15; // 30:16 Reserved Uint16 rsvd3:1; // 31 Reserved }; union DCDCCTL_REG { Uint32 all; struct DCDCCTL_BITS bit; }; struct DCDCSTS_BITS { // bits description Uint16 INDDETECT:1; // 0 Inductor Detected Uint16 SWSEQDONE:1; // 1 Switch sequence to DC-DC done. Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:13; // 15:3 Reserved }; union DCDCSTS_REG { Uint16 all; struct DCDCSTS_BITS bit; }; struct CMPHPMXSEL_BITS { // bits description Uint16 CMP1HPMXSEL:3; // 2:0 CMP1HPMXSEL bits Uint16 CMP2HPMXSEL:3; // 5:3 CMP2HPMXSEL bits Uint16 CMP3HPMXSEL:3; // 8:6 CMP3HPMXSEL bits Uint16 CMP4HPMXSEL:3; // 11:9 CMP4HPMXSEL bits Uint16 CMP5HPMXSEL:3; // 14:12 CMP5HPMXSEL bits Uint16 rsvd1:1; // 15 Reserved Uint16 CMP6HPMXSEL:3; // 18:16 CMP6HPMXSEL bits Uint16 CMP7HPMXSEL:3; // 21:19 CMP7HPMXSEL bits Uint16 rsvd2:10; // 31:22 Reserved }; union CMPHPMXSEL_REG { Uint32 all; struct CMPHPMXSEL_BITS bit; }; struct CMPLPMXSEL_BITS { // bits description Uint16 CMP1LPMXSEL:3; // 2:0 CMP1LPMXSEL bits Uint16 CMP2LPMXSEL:3; // 5:3 CMP2LPMXSEL bits Uint16 CMP3LPMXSEL:3; // 8:6 CMP3LPMXSEL bits Uint16 CMP4LPMXSEL:3; // 11:9 CMP4LPMXSEL bits Uint16 CMP5LPMXSEL:3; // 14:12 CMP5LPMXSEL bits Uint16 rsvd1:1; // 15 Reserved Uint16 CMP6LPMXSEL:3; // 18:16 CMP6LPMXSEL bits Uint16 CMP7LPMXSEL:3; // 21:19 CMP7LPMXSEL bits Uint16 rsvd2:10; // 31:22 Reserved }; union CMPLPMXSEL_REG { Uint32 all; struct CMPLPMXSEL_BITS bit; }; struct CMPHNMXSEL_BITS { // bits description Uint16 CMP1HNMXSEL:1; // 0 CMP1HNMXSEL bits Uint16 CMP2HNMXSEL:1; // 1 CMP2HNMXSEL bits Uint16 CMP3HNMXSEL:1; // 2 CMP3HNMXSEL bits Uint16 CMP4HNMXSEL:1; // 3 CMP4HNMXSEL bits Uint16 CMP5HNMXSEL:1; // 4 CMP5HNMXSEL bits Uint16 CMP6HNMXSEL:1; // 5 CMP6HNMXSEL bits Uint16 CMP7HNMXSEL:1; // 6 CMP7HNMXSEL bits Uint16 rsvd1:9; // 15:7 Reserved }; union CMPHNMXSEL_REG { Uint16 all; struct CMPHNMXSEL_BITS bit; }; struct CMPLNMXSEL_BITS { // bits description Uint16 CMP1LNMXSEL:1; // 0 CMP1LNMXSEL bits Uint16 CMP2LNMXSEL:1; // 1 CMP2LNMXSEL bits Uint16 CMP3LNMXSEL:1; // 2 CMP3LNMXSEL bits Uint16 CMP4LNMXSEL:1; // 3 CMP4LNMXSEL bits Uint16 CMP5LNMXSEL:1; // 4 CMP5LNMXSEL bits Uint16 CMP6LNMXSEL:1; // 5 CMP6LNMXSEL bits Uint16 CMP7LNMXSEL:1; // 6 CMP7LNMXSEL bits Uint16 rsvd1:9; // 15:7 Reserved }; union CMPLNMXSEL_REG { Uint16 all; struct CMPLNMXSEL_BITS bit; }; struct LOCK_BITS { // bits description Uint16 TSNSCTL:1; // 0 TSNSCTL Register lock bit Uint16 ANAREFCTL:1; // 1 ANAREFCTL Register lock bit Uint16 VMONCTL:1; // 2 VMONCTL Register lock bit Uint16 DCDCCTL:1; // 3 DCDCCTL Register lock bit Uint16 ADCINMXSEL:1; // 4 ADCINMXSEL Register lock bit Uint16 CMPHPMXSEL:1; // 5 CMPHPMXSEL Register lock bit Uint16 CMPLPMXSEL:1; // 6 CMPLPMXSEL Register lock bit Uint16 CMPHNMXSEL:1; // 7 CMPHNMXSEL Register lock bit Uint16 CMPLNMXSEL:1; // 8 CMPLNMXSEL Register lock bit Uint16 VREGCTL:1; // 9 VREGCTL Register lock bit Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LOCK_REG { Uint32 all; struct LOCK_BITS bit; }; struct ANALOG_SUBSYS_REGS { Uint16 rsvd1[30]; // Reserved union ANAREFPP_REG ANAREFPP; // ADC Analog Reference Peripheral Properties register Uint16 rsvd2[65]; // Reserved union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register Uint16 rsvd3[7]; // Reserved union ANAREFCTL_REG ANAREFCTL; // Analog Reference Control Register Uint16 rsvd4[15]; // Reserved union DCDCCTL_REG DCDCCTL; // DC-DC control register. union DCDCSTS_REG DCDCSTS; // DC-DC status register. Uint16 rsvd5[7]; // Reserved union CMPHPMXSEL_REG CMPHPMXSEL; // Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details. union CMPLPMXSEL_REG CMPLPMXSEL; // Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details. union CMPHNMXSEL_REG CMPHNMXSEL; // Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details. union CMPLNMXSEL_REG CMPLNMXSEL; // Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details. Uint16 rsvd6[6]; // Reserved union LOCK_REG LOCK; // Lock Register }; //--------------------------------------------------------------------------- // ANALOGSUBSYS External References & Function Declarations: // extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_cla.h // // TITLE: CLA Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CLA Individual Register Bit Definitions: struct MCTL_BITS { // bits description Uint16 HARDRESET:1; // 0 Hard Reset Uint16 SOFTRESET:1; // 1 Soft Reset Uint16 IACKE:1; // 2 IACK enable Uint16 rsvd1:13; // 15:3 Reserved }; union MCTL_REG { Uint16 all; struct MCTL_BITS bit; }; struct SOFTINTEN_BITS { // bits description Uint16 TASK1:1; // 0 Configure Software Interrupt or End of Task interrupt. Uint16 TASK2:1; // 1 Configure Software Interrupt or End of Task interrupt. Uint16 TASK3:1; // 2 Configure Software Interrupt or End of Task interrupt. Uint16 TASK4:1; // 3 Configure Software Interrupt or End of Task interrupt. Uint16 TASK5:1; // 4 Configure Software Interrupt or End of Task interrupt. Uint16 TASK6:1; // 5 Configure Software Interrupt or End of Task interrupt. Uint16 TASK7:1; // 6 Configure Software Interrupt or End of Task interrupt. Uint16 TASK8:1; // 7 Configure Software Interrupt or End of Task interrupt. Uint16 rsvd1:8; // 15:8 Reserved }; union SOFTINTEN_REG { Uint16 all; struct SOFTINTEN_BITS bit; }; struct _MSTSBGRND_BITS { // bits description Uint16 RUN:1; // 0 Background task run status bit. Uint16 BGINTM:1; // 1 Indicates whether background task can be interrupted. Uint16 BGOVF:1; // 2 background task harware trigger overflow. Uint16 rsvd1:13; // 15:3 Reserved }; union _MSTSBGRND_REG { Uint16 all; struct _MSTSBGRND_BITS bit; }; struct _MCTLBGRND_BITS { // bits description Uint16 BGSTART:1; // 0 Background task start bit Uint16 TRIGEN:1; // 1 Background task hardware trigger enable Uint16 rsvd1:13; // 14:2 Reserved Uint16 BGEN:1; // 15 Enable background task }; union _MCTLBGRND_REG { Uint16 all; struct _MCTLBGRND_BITS bit; }; struct MIFR_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Flag Uint16 INT2:1; // 1 Task 2 Interrupt Flag Uint16 INT3:1; // 2 Task 3 Interrupt Flag Uint16 INT4:1; // 3 Task 4 Interrupt Flag Uint16 INT5:1; // 4 Task 5 Interrupt Flag Uint16 INT6:1; // 5 Task 6 Interrupt Flag Uint16 INT7:1; // 6 Task 7 Interrupt Flag Uint16 INT8:1; // 7 Task 8 Interrupt Flag Uint16 rsvd1:8; // 15:8 Reserved }; union MIFR_REG { Uint16 all; struct MIFR_BITS bit; }; struct MIOVF_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Uint16 rsvd1:8; // 15:8 Reserved }; union MIOVF_REG { Uint16 all; struct MIOVF_BITS bit; }; struct MIFRC_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Force Uint16 INT2:1; // 1 Task 2 Interrupt Force Uint16 INT3:1; // 2 Task 3 Interrupt Force Uint16 INT4:1; // 3 Task 4 Interrupt Force Uint16 INT5:1; // 4 Task 5 Interrupt Force Uint16 INT6:1; // 5 Task 6 Interrupt Force Uint16 INT7:1; // 6 Task 7 Interrupt Force Uint16 INT8:1; // 7 Task 8 Interrupt Force Uint16 rsvd1:8; // 15:8 Reserved }; union MIFRC_REG { Uint16 all; struct MIFRC_BITS bit; }; struct MICLR_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear Uint16 rsvd1:8; // 15:8 Reserved }; union MICLR_REG { Uint16 all; struct MICLR_BITS bit; }; struct MICLROVF_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear Uint16 rsvd1:8; // 15:8 Reserved }; union MICLROVF_REG { Uint16 all; struct MICLROVF_BITS bit; }; struct MIER_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Enable Uint16 INT2:1; // 1 Task 2 Interrupt Enable Uint16 INT3:1; // 2 Task 3 Interrupt Enable Uint16 INT4:1; // 3 Task 4 Interrupt Enable Uint16 INT5:1; // 4 Task 5 Interrupt Enable Uint16 INT6:1; // 5 Task 6 Interrupt Enable Uint16 INT7:1; // 6 Task 7 Interrupt Enable Uint16 INT8:1; // 7 Task 8 Interrupt Enable Uint16 rsvd1:8; // 15:8 Reserved }; union MIER_REG { Uint16 all; struct MIER_BITS bit; }; struct MIRUN_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Run Status Uint16 INT2:1; // 1 Task 2 Run Status Uint16 INT3:1; // 2 Task 3 Run Status Uint16 INT4:1; // 3 Task 4 Run Status Uint16 INT5:1; // 4 Task 5 Run Status Uint16 INT6:1; // 5 Task 6 Run Status Uint16 INT7:1; // 6 Task 7 Run Status Uint16 INT8:1; // 7 Task 8 Run Status Uint16 rsvd1:8; // 15:8 Reserved }; union MIRUN_REG { Uint16 all; struct MIRUN_BITS bit; }; struct _MSTF_BITS { // bits description Uint16 LVF:1; // 0 Latched Overflow Flag Uint16 LUF:1; // 1 Latched Underflow Flag Uint16 NF:1; // 2 Negative Float Flag Uint16 ZF:1; // 3 Zero Float Flag Uint16 rsvd1:2; // 5:4 Reserved Uint16 TF:1; // 6 Test Flag Uint16 rsvd2:2; // 8:7 Reserved Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode Uint16 rsvd3:1; // 10 Reserved Uint16 MEALLOW:1; // 11 MEALLOW Status Uint32 RPC:16; // 27:12 Return PC Uint16 rsvd4:4; // 31:28 Reserved }; union _MSTF_REG { Uint32 all; struct _MSTF_BITS bit; }; struct _MPSACTL_BITS { // bits description Uint16 MPABSTART:1; // 0 Start logging PAB onto PSA1 Uint16 MPABCYC:1; // 1 PAB logging into PSA1 is on every cycle or when PAB changes. Uint16 MDWDBSTART:1; // 2 Start logging DWDB onto PSA2 Uint16 MDWDBCYC:1; // 3 DWDB logging into PSA2 is on every cycle. Uint16 MPSA1CLEAR:1; // 4 PSA1 clear Uint16 MPSA2CLEAR:1; // 5 PSA2 Clear Uint16 MPSA2CFG:2; // 7:6 PSA2 Polynomial Configuration Uint16 rsvd1:8; // 15:8 Reserved }; union _MPSACTL_REG { Uint16 all; struct _MPSACTL_BITS bit; }; union MR_REG { Uint32 i32; float f32; }; struct CLA_REGS { Uint16 MVECT1; // Task Interrupt Vector Uint16 MVECT2; // Task Interrupt Vector Uint16 MVECT3; // Task Interrupt Vector Uint16 MVECT4; // Task Interrupt Vector Uint16 MVECT5; // Task Interrupt Vector Uint16 MVECT6; // Task Interrupt Vector Uint16 MVECT7; // Task Interrupt Vector Uint16 MVECT8; // Task Interrupt Vector Uint16 rsvd1[8]; // Reserved union MCTL_REG MCTL; // Control Register Uint16 rsvd2[10]; // Reserved Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register union _MSTSBGRND_REG _MSTSBGRND; // Status register for the back ground task. union _MCTLBGRND_REG _MCTLBGRND; // Control register for the back ground task. Uint16 _MVECTBGRND; // Vector for the back ground task. union MIFR_REG MIFR; // Interrupt Flag Register union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register union MIFRC_REG MIFRC; // Interrupt Force Register union MICLR_REG MICLR; // Interrupt Flag Clear Register union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register union MIER_REG MIER; // Interrupt Enable Register union MIRUN_REG MIRUN; // Interrupt Run Status Register Uint16 rsvd3; // Reserved Uint16 _MPC; // CLA Program Counter Uint16 rsvd4; // Reserved Uint16 _MAR0; // CLA Auxiliary Register 0 Uint16 _MAR1; // CLA Auxiliary Register 1 Uint16 rsvd5[2]; // Reserved union _MSTF_REG _MSTF; // CLA Floating-Point Status Register union MR_REG _MR0; // CLA Floating-Point Result Register 0 Uint16 rsvd6[2]; // Reserved union MR_REG _MR1; // CLA Floating-Point Result Register 1 Uint16 rsvd7[2]; // Reserved union MR_REG _MR2; // CLA Floating-Point Result Register 2 Uint16 rsvd8[2]; // Reserved union MR_REG _MR3; // CLA Floating-Point Result Register 3 Uint16 rsvd9[4]; // Reserved union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register Uint16 rsvd10; // Reserved Uint32 _MPSA1; // CLA PSA1 Register Uint32 _MPSA2; // CLA PSA2 Register Uint16 rsvd11[56]; // Reserved }; struct SOFTINTFRC_BITS { // bits description Uint16 TASK1:1; // 0 Force CLA software interrupt for the corresponding task. Uint16 TASK2:1; // 1 Force CLA software interrupt for the corresponding task. Uint16 TASK3:1; // 2 Force CLA software interrupt for the corresponding task. Uint16 TASK4:1; // 3 Force CLA software interrupt for the corresponding task. Uint16 TASK5:1; // 4 Force CLA software interrupt for the corresponding task. Uint16 TASK6:1; // 5 Force CLA software interrupt for the corresponding task. Uint16 TASK7:1; // 6 Force CLA software interrupt for the corresponding task. Uint16 TASK8:1; // 7 Force CLA software interrupt for the corresponding task. Uint16 rsvd1:8; // 15:8 Reserved }; union SOFTINTFRC_REG { Uint16 all; struct SOFTINTFRC_BITS bit; }; struct CLA_ONLY_REGS { Uint16 rsvd1[128]; // Reserved Uint16 _MVECTBGRNDACTIVE; // Active register for MVECTBGRND. Uint16 rsvd2[63]; // Reserved union _MPSACTL_REG _MPSACTL; // CLA PSA Control Register Uint16 rsvd3; // Reserved Uint32 _MPSA1; // CLA PSA1 Register Uint32 _MPSA2; // CLA PSA2 Register Uint16 rsvd4[26]; // Reserved union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register Uint16 rsvd5; // Reserved union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register Uint16 rsvd6[12]; // Reserved }; struct CLA_SOFTINT_REGS { union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register Uint16 rsvd1; // Reserved union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register Uint16 rsvd2[12]; // Reserved }; //--------------------------------------------------------------------------- // CLA External References & Function Declarations: // extern volatile struct CLA_ONLY_REGS Cla1OnlyRegs; extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; extern volatile struct CLA_REGS Cla1Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_cla_prom_crc32.h // // TITLE: CLA_PROM_CRC32 Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CLA_PROM_CRC32 Individual Register Bit Definitions: struct CRC32_CONTROLREG_BITS { // bits description Uint16 START:1; // 0 Start Bit Uint16 rsvd1:3; // 3:1 Reserved Uint16 FREE_SOFT:1; // 4 emulation control bit Uint16 rsvd2:3; // 7:5 Reserved Uint16 HALT:1; // 8 Halt Bit Uint16 rsvd3:7; // 15:9 Reserved Uint16 BLOCKSIZE:7; // 22:16 Block size of ROM for which CRC is to be calculated Uint16 rsvd4:9; // 31:23 Reserved }; union CRC32_CONTROLREG_REG { Uint32 all; struct CRC32_CONTROLREG_BITS bit; }; struct CRC32_STATUSREG_BITS { // bits description Uint16 CURRENTADDR:16; // 15:0 Point to the data fetch unit current address Uint16 rsvd1:7; // 22:16 Reserved Uint16 CRCCHECKSTATUS:1; // 23 CRC active status Uint16 rsvd2:7; // 30:24 Reserved Uint16 RUNSTATUS:1; // 31 CRC active status }; union CRC32_STATUSREG_REG { Uint32 all; struct CRC32_STATUSREG_BITS bit; }; struct CRC32_INTEN_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CRCDONE:1; // 1 CRCDONE interrupt enable register Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CRC32_INTEN_REG { Uint32 all; struct CRC32_INTEN_BITS bit; }; struct CRC32_FLG_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt status flag Uint16 CRCDONE:1; // 1 CRCDONE Interrupt status flag Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CRC32_FLG_REG { Uint32 all; struct CRC32_FLG_BITS bit; }; struct CRC32_CLR_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt clear Uint16 CRCDONE:1; // 1 CRCDONE Interrupt clear Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CRC32_CLR_REG { Uint32 all; struct CRC32_CLR_BITS bit; }; struct CRC32_FRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CRCDONE:1; // 1 CRCDONE Interrupt force Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CRC32_FRC_REG { Uint32 all; struct CRC32_FRC_BITS bit; }; struct CLA_PROM_CRC32_REGS { union CRC32_CONTROLREG_REG CRC32_CONTROLREG; // CRC32-Control Register Uint32 CRC32_STARTADDRESS; // CRC32-Start address register Uint32 CRC32_SEED; // CRC32-Seed Register union CRC32_STATUSREG_REG CRC32_STATUSREG; // CRC32-Status Register Uint32 CRC32_CRCRESULT; // CRC32-CRC result Register Uint32 CRC32_GOLDENCRC; // CRC32-Golden CRC register Uint16 rsvd1[12]; // Reserved union CRC32_INTEN_REG CRC32_INTEN; // CRC32-Interrupt enable register union CRC32_FLG_REG CRC32_FLG; // CRC32-Interrupt Flag Register union CRC32_CLR_REG CRC32_CLR; // CRC32-Interrupt Clear Register union CRC32_FRC_REG CRC32_FRC; // CRC32-Interrupt Force Register }; //--------------------------------------------------------------------------- // CLA_PROM_CRC32 External References & Function Declarations: // extern volatile struct CLA_PROM_CRC32_REGS ClaPromCrc0Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_cmpss.h // // TITLE: CMPSS Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CMPSS Individual Register Bit Definitions: struct COMPCTL_BITS { // bits description Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select Uint16 COMPHINV:1; // 1 High Comparator Invert Select Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable Uint16 rsvd1:1; // 7 Reserved Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select Uint16 COMPLINV:1; // 9 Low Comparator Invert Select Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable Uint16 COMPDACE:1; // 15 Comparator/DAC Enable }; union COMPCTL_REG { Uint16 all; struct COMPCTL_BITS bit; }; struct COMPHYSCTL_BITS { // bits description Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim Uint16 rsvd1:13; // 15:3 Reserved }; union COMPHYSCTL_REG { Uint16 all; struct COMPHYSCTL_BITS bit; }; struct COMPSTS_BITS { // bits description Uint16 COMPHSTS:1; // 0 High Comparator Status Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status Uint16 rsvd1:6; // 7:2 Reserved Uint16 COMPLSTS:1; // 8 Low Comparator Status Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status Uint16 rsvd2:6; // 15:10 Reserved }; union COMPSTS_REG { Uint16 all; struct COMPSTS_BITS bit; }; struct COMPSTSCLR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear Uint16 HSYNCCLREN:1; // 2 High Comparator PWMSYNC Clear Enable Uint16 rsvd2:6; // 8:3 Reserved Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear Uint16 LSYNCCLREN:1; // 10 Low Comparator PWMSYNC Clear Enable Uint16 rsvd3:5; // 15:11 Reserved }; union COMPSTSCLR_REG { Uint16 all; struct COMPSTSCLR_BITS bit; }; struct COMPDACCTL_BITS { // bits description Uint16 DACSOURCE:1; // 0 DAC Source Control Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control Uint16 SELREF:1; // 5 DAC Reference Select Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select Uint16 SWLOADSEL:1; // 7 Software Load Select Uint16 BLANKSOURCE:4; // 11:8 PWMBLANK Source Select Uint16 BLANKEN:1; // 12 PWMBLANK Enable Uint16 rsvd1:1; // 13 Reserved Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits }; union COMPDACCTL_REG { Uint16 all; struct COMPDACCTL_BITS bit; }; struct DACHVALS_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACHVALS_REG { Uint16 all; struct DACHVALS_BITS bit; }; struct DACHVALA_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACHVALA_REG { Uint16 all; struct DACHVALA_BITS bit; }; struct DACLVALS_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACLVALS_REG { Uint16 all; struct DACLVALS_BITS bit; }; struct DACLVALA_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACLVALA_REG { Uint16 all; struct DACLVALA_BITS bit; }; struct RAMPDLYA_BITS { // bits description Uint16 DELAY:13; // 12:0 Ramp Delay Value Uint16 rsvd1:3; // 15:13 Reserved }; union RAMPDLYA_REG { Uint16 all; struct RAMPDLYA_BITS bit; }; struct RAMPDLYS_BITS { // bits description Uint16 DELAY:13; // 12:0 Ramp Delay Value Uint16 rsvd1:3; // 15:13 Reserved }; union RAMPDLYS_REG { Uint16 all; struct RAMPDLYS_BITS bit; }; struct CTRIPLFILCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union CTRIPLFILCTL_REG { Uint16 all; struct CTRIPLFILCTL_BITS bit; }; struct CTRIPLFILCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union CTRIPLFILCLKCTL_REG { Uint16 all; struct CTRIPLFILCLKCTL_BITS bit; }; struct CTRIPHFILCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union CTRIPHFILCTL_REG { Uint16 all; struct CTRIPHFILCTL_BITS bit; }; struct CTRIPHFILCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union CTRIPHFILCLKCTL_REG { Uint16 all; struct CTRIPHFILCLKCTL_BITS bit; }; struct COMPLOCK_BITS { // bits description Uint16 COMPCTL:1; // 0 COMPCTL Lock Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock Uint16 DACCTL:1; // 2 DACCTL Lock Uint16 CTRIP:1; // 3 CTRIP Lock Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:11; // 15:5 Reserved }; union COMPLOCK_REG { Uint16 all; struct COMPLOCK_BITS bit; }; struct CMPSS_REGS { union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register Uint16 rsvd1; // Reserved union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register Uint16 rsvd2; // Reserved Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register Uint16 rsvd3; // Reserved Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register Uint16 rsvd4; // Reserved Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register Uint16 rsvd5; // Reserved Uint16 RAMPSTS; // CMPSS Ramp Status Register Uint16 rsvd6; // Reserved union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register Uint16 rsvd7[5]; // Reserved }; //--------------------------------------------------------------------------- // CMPSS External References & Function Declarations: // extern volatile struct CMPSS_REGS Cmpss1Regs; extern volatile struct CMPSS_REGS Cmpss2Regs; extern volatile struct CMPSS_REGS Cmpss3Regs; extern volatile struct CMPSS_REGS Cmpss4Regs; extern volatile struct CMPSS_REGS Cmpss5Regs; extern volatile struct CMPSS_REGS Cmpss6Regs; extern volatile struct CMPSS_REGS Cmpss7Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_cputimer.h // // TITLE: CPUTIMER Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CPUTIMER Individual Register Bit Definitions: struct TIM_BITS { // bits description Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High }; union TIM_REG { Uint32 all; struct TIM_BITS bit; }; struct PRD_BITS { // bits description Uint16 LSW:16; // 15:0 CPU-Timer Period Registers Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High }; union PRD_REG { Uint32 all; struct PRD_BITS bit; }; struct TCR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 TSS:1; // 4 CPU-Timer stop status bit. Uint16 TRB:1; // 5 Timer reload Uint16 rsvd2:4; // 9:6 Reserved Uint16 SOFT:1; // 10 Emulation modes Uint16 FREE:1; // 11 Emulation modes Uint16 rsvd3:2; // 13:12 Reserved Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. }; union TCR_REG { Uint16 all; struct TCR_BITS bit; }; struct TPR_BITS { // bits description Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. }; union TPR_REG { Uint16 all; struct TPR_BITS bit; }; struct TPRH_BITS { // bits description Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. }; union TPRH_REG { Uint16 all; struct TPRH_BITS bit; }; struct CPUTIMER_REGS { union TIM_REG TIM; // CPU-Timer, Counter Register union PRD_REG PRD; // CPU-Timer, Period Register union TCR_REG TCR; // CPU-Timer, Control Register Uint16 rsvd1; // Reserved union TPR_REG TPR; // CPU-Timer, Prescale Register union TPRH_REG TPRH; // CPU-Timer, Prescale Register High }; //--------------------------------------------------------------------------- // CPUTIMER External References & Function Declarations: // extern volatile struct CPUTIMER_REGS CpuTimer0Regs; extern volatile struct CPUTIMER_REGS CpuTimer1Regs; extern volatile struct CPUTIMER_REGS CpuTimer2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_dac.h // // TITLE: DAC Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // DAC Individual Register Bit Definitions: struct DACREV_BITS { // bits description Uint16 REV:8; // 7:0 DAC Revision Register Uint16 rsvd1:8; // 15:8 Reserved }; union DACREV_REG { Uint16 all; struct DACREV_BITS bit; }; struct DACCTL_BITS { // bits description Uint16 DACREFSEL:1; // 0 DAC Reference Select Uint16 MODE:1; // 1 DAC Mode Select Uint16 LOADMODE:1; // 2 DACVALA Load Mode Uint16 rsvd1:1; // 3 Reserved Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select Uint16 rsvd2:8; // 15:8 Reserved }; union DACCTL_REG { Uint16 all; struct DACCTL_BITS bit; }; struct DACVALA_BITS { // bits description Uint16 DACVALA:12; // 11:0 DAC Active Output Code Uint16 rsvd1:4; // 15:12 Reserved }; union DACVALA_REG { Uint16 all; struct DACVALA_BITS bit; }; struct DACVALS_BITS { // bits description Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code Uint16 rsvd1:4; // 15:12 Reserved }; union DACVALS_REG { Uint16 all; struct DACVALS_BITS bit; }; struct DACOUTEN_BITS { // bits description Uint16 DACOUTEN:1; // 0 DAC Output Code Uint16 rsvd1:15; // 15:1 Reserved }; union DACOUTEN_REG { Uint16 all; struct DACOUTEN_BITS bit; }; struct DACLOCK_BITS { // bits description Uint16 DACCTL:1; // 0 DAC Control Register Lock Uint16 DACVAL:1; // 1 DAC Value Register Lock Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock Uint16 rsvd1:9; // 11:3 Reserved Uint16 KEY:4; // 15:12 DAC Register Lock Key }; union DACLOCK_REG { Uint16 all; struct DACLOCK_BITS bit; }; struct DACTRIM_BITS { // bits description Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim Uint16 rsvd1:4; // 11:8 Reserved Uint16 rsvd2:4; // 15:12 Reserved }; union DACTRIM_REG { Uint16 all; struct DACTRIM_BITS bit; }; struct DAC_REGS { union DACREV_REG DACREV; // DAC Revision Register union DACCTL_REG DACCTL; // DAC Control Register union DACVALA_REG DACVALA; // DAC Value Register - Active union DACVALS_REG DACVALS; // DAC Value Register - Shadow union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register union DACLOCK_REG DACLOCK; // DAC Lock Register union DACTRIM_REG DACTRIM; // DAC Trim Register Uint16 rsvd1; // Reserved }; //--------------------------------------------------------------------------- // DAC External References & Function Declarations: // extern volatile struct DAC_REGS DacaRegs; extern volatile struct DAC_REGS DacbRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_dcsm.h // // TITLE: DCSM Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // DCSM Individual Register Bit Definitions: struct B0_Z1_LINKPOINTER_BITS { // bits description Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer for zone Flash BANK0 Uint16 rsvd1:3; // 31:29 Reserved }; union B0_Z1_LINKPOINTER_REG { Uint32 all; struct B0_Z1_LINKPOINTER_BITS bit; }; struct Z1_OTPSECLOCK_BITS { // bits description Uint16 JTAGLOCK:4; // 3:0 Zone1 JTAG Lock. Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_OTPSECLOCK_REG { Uint32 all; struct Z1_OTPSECLOCK_BITS bit; }; struct B0_Z1_LINKPOINTERERR_BITS { // bits description Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values Uint16 rsvd1:3; // 31:29 Reserved }; union B0_Z1_LINKPOINTERERR_REG { Uint32 all; struct B0_Z1_LINKPOINTERERR_BITS bit; }; struct Z1_CR_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros Uint16 ALLONE:1; // 4 CSMPSWD All Ones Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY Uint16 ARMED:1; // 6 CSM Passwords Read Status Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:7; // 14:8 Reserved Uint16 FORCESEC:1; // 15 Force Secure }; union Z1_CR_REG { Uint16 all; struct Z1_CR_BITS bit; }; struct B0_Z1_GRABSECTR_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK0 Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK0 Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK0 Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK0 Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK0 Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK0 Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK0 Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK0 Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK0 Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK0 Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK0 Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK0 Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK0 Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK0 Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK0 Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK0 }; union B0_Z1_GRABSECTR_REG { Uint32 all; struct B0_Z1_GRABSECTR_BITS bit; }; struct Z1_GRABRAMR_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 Uint16 rsvd1:16; // 31:16 Reserved }; union Z1_GRABRAMR_REG { Uint32 all; struct Z1_GRABRAMR_BITS bit; }; struct B0_Z1_EXEONLYSECTR_BITS { // bits description Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 Uint16 rsvd1:16; // 31:16 Reserved }; union B0_Z1_EXEONLYSECTR_REG { Uint32 all; struct B0_Z1_EXEONLYSECTR_BITS bit; }; struct Z1_EXEONLYRAMR_BITS { // bits description Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_EXEONLYRAMR_REG { Uint32 all; struct Z1_EXEONLYRAMR_BITS bit; }; struct DCSM_BANK0_Z1_REGS { union B0_Z1_LINKPOINTER_REG B0_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK0 union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock Uint32 Z1_BOOTDEF_HIGH; // Boot definition (high 32bit) union B0_Z1_LINKPOINTERERR_REG B0_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK0 Uint32 Z1_BOOTPIN_CONFIG; // Boot Pin Configuration Uint32 Z1_GPREG2; // Zone1 General Purpose Register-2 Uint32 Z1_BOOTDEF_LOW; // Boot definition (low 32bit) Uint16 rsvd1[2]; // Reserved Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 Uint16 rsvd2; // Reserved union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register union B0_Z1_GRABSECTR_REG B0_Z1_GRABSECTR; // Zone 1 Grab Flash BANK0 Sectors Register union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register union B0_Z1_EXEONLYSECTR_REG B0_Z1_EXEONLYSECTR; // Zone 1 Flash BANK0 Execute_Only Sector Register union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register Uint16 rsvd3; // Reserved }; struct B0_Z2_LINKPOINTER_BITS { // bits description Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK0 Uint16 rsvd1:3; // 31:29 Reserved }; union B0_Z2_LINKPOINTER_REG { Uint32 all; struct B0_Z2_LINKPOINTER_BITS bit; }; struct Z2_OTPSECLOCK_BITS { // bits description Uint16 JTAGLOCK:4; // 3:0 Zone2 JTAG Lock. Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z2_OTPSECLOCK_REG { Uint32 all; struct Z2_OTPSECLOCK_BITS bit; }; struct B0_Z2_LINKPOINTERERR_BITS { // bits description Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values Uint16 rsvd1:3; // 31:29 Reserved }; union B0_Z2_LINKPOINTERERR_REG { Uint32 all; struct B0_Z2_LINKPOINTERERR_BITS bit; }; struct Z2_CR_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros Uint16 ALLONE:1; // 4 CSMPSWD All Ones Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY Uint16 ARMED:1; // 6 CSM Passwords Read Status Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:7; // 14:8 Reserved Uint16 FORCESEC:1; // 15 Force Secure }; union Z2_CR_REG { Uint16 all; struct Z2_CR_BITS bit; }; struct B0_Z2_GRABSECTR_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK0 Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK0 Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK0 Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK0 Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK0 Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK0 Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK0 Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK0 Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK0 Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK0 Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK0 Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK0 Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK0 Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK0 Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK0 Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK0 }; union B0_Z2_GRABSECTR_REG { Uint32 all; struct B0_Z2_GRABSECTR_BITS bit; }; struct Z2_GRABRAMR_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM LS6 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM LS7 Uint16 rsvd1:16; // 31:16 Reserved }; union Z2_GRABRAMR_REG { Uint32 all; struct Z2_GRABRAMR_BITS bit; }; struct B0_Z2_EXEONLYSECTR_BITS { // bits description Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK0 Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK0 Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK0 Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK0 Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK0 Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK0 Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK0 Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK0 Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK0 Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK0 Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK0 Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK0 Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK0 Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK0 Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK0 Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK0 Uint16 rsvd1:16; // 31:16 Reserved }; union B0_Z2_EXEONLYSECTR_REG { Uint32 all; struct B0_Z2_EXEONLYSECTR_BITS bit; }; struct Z2_EXEONLYRAMR_BITS { // bits description Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM LS6 Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM LS7 Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z2_EXEONLYRAMR_REG { Uint32 all; struct Z2_EXEONLYRAMR_BITS bit; }; struct DCSM_BANK0_Z2_REGS { union B0_Z2_LINKPOINTER_REG B0_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK0 union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock Uint16 rsvd1[2]; // Reserved union B0_Z2_LINKPOINTERERR_REG B0_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK0 Uint16 rsvd2[8]; // Reserved Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 Uint16 rsvd3; // Reserved union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register union B0_Z2_GRABSECTR_REG B0_Z2_GRABSECTR; // Zone 2 Grab Flash BANK0 Sectors Register union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register union B0_Z2_EXEONLYSECTR_REG B0_Z2_EXEONLYSECTR; // Zone 2 Flash BANK0 Execute_Only Sector Register union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register Uint16 rsvd4; // Reserved }; struct FLSEM_BITS { // bits description Uint16 SEM:2; // 1:0 Flash Semaphore Bit Uint16 rsvd1:6; // 7:2 Reserved Uint16 KEY:8; // 15:8 Semaphore Key Uint16 rsvd2:16; // 31:16 Reserved }; union FLSEM_REG { Uint32 all; struct FLSEM_BITS bit; }; struct B0_SECTSTAT_BITS { // bits description Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK0 Sector 0 Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK0 sector 1 Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK0 Sector 2 Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK0 Sector 3 Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK0 Sector 4 Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK0 Sector 5 Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK0 Sector 6 Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK0 Sector 7 Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK0 sector 8 Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK0 Sector 9 Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK0 Sector 10 Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK0 Sector 11 Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK0 Sector 12 Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK0 Sector 13 Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK0 Sector 14 Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK0 Sector 15 }; union B0_SECTSTAT_REG { Uint32 all; struct B0_SECTSTAT_BITS bit; }; struct RAMSTAT_BITS { // bits description Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM LS6 Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM LS7 Uint16 rsvd1:16; // 31:16 Reserved }; union RAMSTAT_REG { Uint32 all; struct RAMSTAT_BITS bit; }; struct B1_SECTSTAT_BITS { // bits description Uint16 STATUS_SECT0:2; // 1:0 Zone Status Flash BANK1 Sector 0 Uint16 STATUS_SECT1:2; // 3:2 Zone Status Flash BANK1 sector 1 Uint16 STATUS_SECT2:2; // 5:4 Zone Status Flash BANK1 Sector 2 Uint16 STATUS_SECT3:2; // 7:6 Zone Status Flash BANK1 Sector 3 Uint16 STATUS_SECT4:2; // 9:8 Zone Status Flash BANK1 Sector 4 Uint16 STATUS_SECT5:2; // 11:10 Zone Status Flash BANK1 Sector 5 Uint16 STATUS_SECT6:2; // 13:12 Zone Status Flash BANK1 Sector 6 Uint16 STATUS_SECT7:2; // 15:14 Zone Status Flash BANK1 Sector 7 Uint16 STATUS_SECT8:2; // 17:16 Zone Status Flash BANK1 sector 8 Uint16 STATUS_SECT9:2; // 19:18 Zone Status Flash BANK1 Sector 9 Uint16 STATUS_SECT10:2; // 21:20 Zone Status Flash BANK1 Sector 10 Uint16 STATUS_SECT11:2; // 23:22 Zone Status Flash BANK1 Sector 11 Uint16 STATUS_SECT12:2; // 25:24 Zone Status Flash BANK1 Sector 12 Uint16 STATUS_SECT13:2; // 27:26 Zone Status Flash BANK1 Sector 13 Uint16 STATUS_SECT14:2; // 29:28 Zone Status Flash BANK1 Sector 14 Uint16 STATUS_SECT15:2; // 31:30 Zone Status Flash BANK1 Sector 15 }; union B1_SECTSTAT_REG { Uint32 all; struct B1_SECTSTAT_BITS bit; }; struct SECERRSTAT_BITS { // bits description Uint16 ERR:1; // 0 Security Configuration load Error Status Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SECERRSTAT_REG { Uint32 all; struct SECERRSTAT_BITS bit; }; struct SECERRCLR_BITS { // bits description Uint16 ERR:1; // 0 Clear Security Configuration Load Error Status Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SECERRCLR_REG { Uint32 all; struct SECERRCLR_BITS bit; }; struct SECERRFRC_BITS { // bits description Uint16 ERR:1; // 0 Set Security Configuration Load Error Status Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SECERRFRC_REG { Uint32 all; struct SECERRFRC_BITS bit; }; struct DCSM_COMMON_REGS { union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register union B0_SECTSTAT_REG B0_SECTSTAT; // Flash BANK0 Sectors Status Register union RAMSTAT_REG RAMSTAT; // RAM Status Register Uint16 rsvd1[2]; // Reserved union B1_SECTSTAT_REG B1_SECTSTAT; // Flash BANK1 Sectors Status Register union SECERRSTAT_REG SECERRSTAT; // Security Error Status Register union SECERRCLR_REG SECERRCLR; // Security Error Clear Register union SECERRFRC_REG SECERRFRC; // Security Error Force Register }; struct B1_Z1_LINKPOINTER_BITS { // bits description Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer in Flash BANK1 Uint16 rsvd1:3; // 31:29 Reserved }; union B1_Z1_LINKPOINTER_REG { Uint32 all; struct B1_Z1_LINKPOINTER_BITS bit; }; struct B1_Z1_LINKPOINTERERR_BITS { // bits description Uint32 Z1_LINKPOINTERERR:29; // 28:0 Error to Resolve Z1 Link pointer from OTP loaded values Uint16 rsvd1:3; // 31:29 Reserved }; union B1_Z1_LINKPOINTERERR_REG { Uint32 all; struct B1_Z1_LINKPOINTERERR_BITS bit; }; struct B1_Z1_GRABSECTR_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in BANK1 Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in BANK1 Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in BANK1 Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in BANK1 Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in BANK1 Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in BANK1 Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in BANK1 Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in BANK1 Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in BANK1 Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in BANK1 Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in BANK1 Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in BANK1 Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in BANK1 Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in BANK1 Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in BANK1 Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in BANK1 }; union B1_Z1_GRABSECTR_REG { Uint32 all; struct B1_Z1_GRABSECTR_BITS bit; }; struct B1_Z1_EXEONLYSECTR_BITS { // bits description Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 Uint16 rsvd1:16; // 31:16 Reserved }; union B1_Z1_EXEONLYSECTR_REG { Uint32 all; struct B1_Z1_EXEONLYSECTR_BITS bit; }; struct DCSM_BANK1_Z1_REGS { union B1_Z1_LINKPOINTER_REG B1_Z1_LINKPOINTER; // Zone 1 Link Pointer for flash BANK1 Uint16 rsvd1[4]; // Reserved union B1_Z1_LINKPOINTERERR_REG B1_Z1_LINKPOINTERERR; // Link Pointer Error for flash BANK1 Uint16 rsvd2[18]; // Reserved union B1_Z1_GRABSECTR_REG B1_Z1_GRABSECTR; // Zone 1 Grab Flash BANK1 Sectors Register Uint16 rsvd3[2]; // Reserved union B1_Z1_EXEONLYSECTR_REG B1_Z1_EXEONLYSECTR; // Zone 1 Flash BANK1 Execute_Only Sector Register Uint16 rsvd4[3]; // Reserved }; struct B1_Z2_LINKPOINTER_BITS { // bits description Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer in Flash BANK1 Uint16 rsvd1:3; // 31:29 Reserved }; union B1_Z2_LINKPOINTER_REG { Uint32 all; struct B1_Z2_LINKPOINTER_BITS bit; }; struct B1_Z2_LINKPOINTERERR_BITS { // bits description Uint32 Z2_LINKPOINTERERR:29; // 28:0 Error to Resolve Z2 Link pointer from OTP loaded values Uint16 rsvd1:3; // 31:29 Reserved }; union B1_Z2_LINKPOINTERERR_REG { Uint32 all; struct B1_Z2_LINKPOINTERERR_BITS bit; }; struct B1_Z2_GRABSECTR_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in Flash BANK1 Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in Flash BANK1 Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in Flash BANK1 Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in Flash BANK1 Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in Flash BANK1 Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in Flash BANK1 Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in Flash BANK1 Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in Flash BANK1 Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in Flash BANK1 Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in Flash BANK1 Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in Flash BANK1 Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in Flash BANK1 Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in Flash BANK1 Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in Flash BANK1 Uint16 GRAB_SECT14:2; // 29:28 Grab Flash Sector 14 in Flash BANK1 Uint16 GRAB_SECT15:2; // 31:30 Grab Flash Sector 15 in Flash BANK1 }; union B1_Z2_GRABSECTR_REG { Uint32 all; struct B1_Z2_GRABSECTR_BITS bit; }; struct B1_Z2_EXEONLYSECTR_BITS { // bits description Uint16 EXEONLY_SECT0:1; // 0 Execute-Only Flash Sector 0 in Flash BANK1 Uint16 EXEONLY_SECT1:1; // 1 Execute-Only Flash Sector 1 in Flash BANK1 Uint16 EXEONLY_SECT2:1; // 2 Execute-Only Flash Sector 2 in Flash BANK1 Uint16 EXEONLY_SECT3:1; // 3 Execute-Only Flash Sector 3 in Flash BANK1 Uint16 EXEONLY_SECT4:1; // 4 Execute-Only Flash Sector 4 in Flash BANK1 Uint16 EXEONLY_SECT5:1; // 5 Execute-Only Flash Sector 5 in Flash BANK1 Uint16 EXEONLY_SECT6:1; // 6 Execute-Only Flash Sector 6 in Flash BANK1 Uint16 EXEONLY_SECT7:1; // 7 Execute-Only Flash Sector 7 in Flash BANK1 Uint16 EXEONLY_SECT8:1; // 8 Execute-Only Flash Sector 8 in Flash BANK1 Uint16 EXEONLY_SECT9:1; // 9 Execute-Only Flash Sector 9 in Flash BANK1 Uint16 EXEONLY_SECT10:1; // 10 Execute-Only Flash Sector 10 in Flash BANK1 Uint16 EXEONLY_SECT11:1; // 11 Execute-Only Flash Sector 11 in Flash BANK1 Uint16 EXEONLY_SECT12:1; // 12 Execute-Only Flash Sector 12 in Flash BANK1 Uint16 EXEONLY_SECT13:1; // 13 Execute-Only Flash Sector 13 in Flash BANK1 Uint16 EXEONLY_SECT14:1; // 14 Execute-Only Flash Sector 14 in Flash BANK1 Uint16 EXEONLY_SECT15:1; // 15 Execute-Only Flash Sector 15 in Flash BANK1 Uint16 rsvd1:16; // 31:16 Reserved }; union B1_Z2_EXEONLYSECTR_REG { Uint32 all; struct B1_Z2_EXEONLYSECTR_BITS bit; }; struct DCSM_BANK1_Z2_REGS { union B1_Z2_LINKPOINTER_REG B1_Z2_LINKPOINTER; // Zone 2 Link Pointer for flash BANK1 Uint16 rsvd1[4]; // Reserved union B1_Z2_LINKPOINTERERR_REG B1_Z2_LINKPOINTERERR; // Link Pointer Error for flash BANK1 Uint16 rsvd2[18]; // Reserved union B1_Z2_GRABSECTR_REG B1_Z2_GRABSECTR; // Zone 2 Grab Flash BANK1 Sectors Register Uint16 rsvd3[2]; // Reserved union B1_Z2_EXEONLYSECTR_REG B1_Z2_EXEONLYSECTR; // Zone 2 Flash BANK1 Execute_Only Sector Register Uint16 rsvd4[3]; // Reserved }; //--------------------------------------------------------------------------- // DCSM External References & Function Declarations: // extern volatile struct DCSM_BANK0_Z1_REGS DcsmBank0Z1Regs; extern volatile struct DCSM_BANK0_Z2_REGS DcsmBank0Z2Regs; extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; extern volatile struct DCSM_BANK1_Z1_REGS DcsmBank1Z1Regs; extern volatile struct DCSM_BANK1_Z2_REGS DcsmBank1Z2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_dma.h // // TITLE: F28004x Device DMA Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // DMA Individual Register Bit Definitions: struct MODE_BITS { // bits description Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Uint16 rsvd1:2; // 6:5 Reserved Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Uint16 ONESHOT:1; // 10 One Shot Mode Bit Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit Uint16 rsvd2:2; // 13:12 Reserved Uint16 DATASIZE:1; // 14 Data Size Mode Bit Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit }; union MODE_REG { Uint16 all; struct MODE_BITS bit; }; struct CONTROL_BITS { // bits description Uint16 RUN:1; // 0 Run Bit Uint16 HALT:1; // 1 Halt Bit Uint16 SOFTRESET:1; // 2 Soft Reset Bit Uint16 PERINTFRC:1; // 3 Interrupt Force Bit Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit Uint16 rsvd2:2; // 6:5 Reserved Uint16 ERRCLR:1; // 7 Error Clear Bit Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit Uint16 SYNCFLG:1; // 9 Sync Flag Bit Uint16 SYNCERR:1; // 10 Sync Error Flag Bit Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit Uint16 BURSTSTS:1; // 12 Burst Status Bit Uint16 RUNSTS:1; // 13 Run Status Bit Uint16 OVRFLG:1; // 14 Overflow Flag Bit Uint16 rsvd1:1; // 15 Reserved }; union CONTROL_REG { Uint16 all; struct CONTROL_BITS bit; }; struct DMACTRL_BITS { // bits description Uint16 HARDRESET:1; // 0 Hard Reset Bit Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit Uint16 rsvd1:14; // 15:2 Reserved }; union DMACTRL_REG { Uint16 all; struct DMACTRL_BITS bit; }; struct DEBUGCTRL_BITS { // bits description Uint16 rsvd1:15; // 14:0 Reserved Uint16 FREE:1; // 15 Debug Mode Bit }; union DEBUGCTRL_REG { Uint16 all; struct DEBUGCTRL_BITS bit; }; struct PRIORITYCTRL1_BITS { // bits description Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit Uint16 rsvd1:15; // 15:1 Reserved }; union PRIORITYCTRL1_REG { Uint16 all; struct PRIORITYCTRL1_BITS bit; }; struct PRIORITYSTAT_BITS { // bits description Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits Uint16 rsvd1:1; // 3 Reserved Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits Uint16 rsvd2:9; // 15:7 Reserved }; union PRIORITYSTAT_REG { Uint16 all; struct PRIORITYSTAT_BITS bit; }; struct BURST_SIZE_BITS { // bits description Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size Uint16 rsvd1:11; // 15:5 Reserved }; union BURST_SIZE_REG { Uint16 all; struct BURST_SIZE_BITS bit; }; struct BURST_COUNT_BITS { // bits description Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count Uint16 rsvd1:11; // 15:5 Reserved }; union BURST_COUNT_REG { Uint16 all; struct BURST_COUNT_BITS bit; }; struct CH_REGS { union MODE_REG MODE; // Mode Register union CONTROL_REG CONTROL; // Control Register union BURST_SIZE_REG BURST_SIZE; // Burst Size Register union BURST_COUNT_REG BURST_COUNT; // Burst Count Register int16 SRC_BURST_STEP; // Source Burst Step Register int16 DST_BURST_STEP; // Destination Burst Step Register Uint16 TRANSFER_SIZE; // Transfer Size Register Uint16 TRANSFER_COUNT; // Transfer Count Register int16 SRC_TRANSFER_STEP; // Source Transfer Step Register int16 DST_TRANSFER_STEP; // Destination Transfer Step Register Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register int16 SRC_WRAP_STEP; // Source Wrap Step Register Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register int16 DST_WRAP_STEP; // Destination Wrap Step Register Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register }; struct DMA_REGS { union DMACTRL_REG DMACTRL; // DMA Control Register union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register Uint16 rsvd0; // Reserved Uint16 rsvd1; // Reserved union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register Uint16 rsvd2; // Reserved union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register Uint16 rsvd3[25]; // Reserved struct CH_REGS CH1; // DMA Channel 1 Registers struct CH_REGS CH2; // DMA Channel 2 Registers struct CH_REGS CH3; // DMA Channel 3 Registers struct CH_REGS CH4; // DMA Channel 4 Registers struct CH_REGS CH5; // DMA Channel 5 Registers struct CH_REGS CH6; // DMA Channel 6 Registers }; //--------------------------------------------------------------------------- // DMA External References & Function Declarations: // extern volatile struct DMA_REGS DmaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_ecap.h // // TITLE: ECAP Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ECAP Individual Register Bit Definitions: struct ECCTL0_BITS { // bits description Uint16 INPUTSEL:7; // 6:0 INPUT source select Uint16 rsvd1:9; // 15:7 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECCTL0_REG { Uint32 all; struct ECCTL0_BITS bit; }; struct ECCTL1_BITS { // bits description Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event Uint16 PRESCALE:5; // 13:9 Event Filter prescale select Uint16 FREE_SOFT:2; // 15:14 Emulation mode }; union ECCTL1_REG { Uint16 all; struct ECCTL1_BITS bit; }; struct ECCTL2_BITS { // bits description Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous Uint16 REARM:1; // 3 One-shot re-arm Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop Uint16 SYNCI_EN:1; // 5 Counter sync-in select Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode Uint16 SWSYNC:1; // 8 SW forced counter sync Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select Uint16 APWMPOL:1; // 10 APWM output polarity select Uint16 CTRFILTRESET:1; // 11 Reset event filter, modulus counter, and interrupt flags. Uint16 DMAEVTSEL:2; // 13:12 DMA event select Uint16 MODCNTRSTS:2; // 15:14 modulo counter status }; union ECCTL2_REG { Uint16 all; struct ECCTL2_BITS bit; }; struct ECEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:7; // 15:9 Reserved }; union ECEINT_REG { Uint16 all; struct ECEINT_BITS bit; }; struct ECFLG_BITS { // bits description Uint16 INT:1; // 0 Global Flag Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:7; // 15:9 Reserved }; union ECFLG_REG { Uint16 all; struct ECFLG_BITS bit; }; struct ECCLR_BITS { // bits description Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear Uint16 CTROVF:1; // 5 Counter Overflow Status Clear Uint16 CTR_PRD:1; // 6 Period Equal Status Clear Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:7; // 15:9 Reserved }; union ECCLR_REG { Uint16 all; struct ECCLR_BITS bit; }; struct ECFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:7; // 15:9 Reserved }; union ECFRC_REG { Uint16 all; struct ECFRC_BITS bit; }; struct ECAPSYNCINSEL_BITS { // bits description Uint16 SEL:5; // 4:0 SYNCIN source select Uint16 rsvd1:11; // 15:5 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAPSYNCINSEL_REG { Uint32 all; struct ECAPSYNCINSEL_BITS bit; }; struct ECAP_REGS { Uint32 TSCTR; // Time-Stamp Counter Uint32 CTRPHS; // Counter Phase Offset Value Register Uint32 CAP1; // Capture 1 Register Uint32 CAP2; // Capture 2 Register Uint32 CAP3; // Capture 3 Register Uint32 CAP4; // Capture 4 Register Uint16 rsvd1[6]; // Reserved union ECCTL0_REG ECCTL0; // Capture Control Register 0 union ECCTL1_REG ECCTL1; // Capture Control Register 1 union ECCTL2_REG ECCTL2; // Capture Control Register 2 union ECEINT_REG ECEINT; // Capture Interrupt Enable Register union ECFLG_REG ECFLG; // Capture Interrupt Flag Register union ECCLR_REG ECCLR; // Capture Interrupt Clear Register union ECFRC_REG ECFRC; // Capture Interrupt Force Register Uint16 rsvd2[4]; // Reserved union ECAPSYNCINSEL_REG ECAPSYNCINSEL; // SYNC source select register }; struct HRCTL_BITS { // bits description Uint16 HRE:1; // 0 High Resolution Enable Uint16 HRCLKE:1; // 1 High Resolution Clock Enable Uint16 PRDSEL:1; // 2 Calibration Period Match Uint16 CALIBSTART:1; // 3 Calibration start Uint16 CALIBSTS:1; // 4 Calibration status Uint16 CALIBCONT:1; // 5 Continuous mode Calibration Select Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRCTL_REG { Uint32 all; struct HRCTL_BITS bit; }; struct HRINTEN_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CALIBDONE:1; // 1 Calibration doe interrupt enable Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status enable Uint16 rsvd2:13; // 15:3 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union HRINTEN_REG { Uint32 all; struct HRINTEN_BITS bit; }; struct HRFLG_BITS { // bits description Uint16 CALIBINT:1; // 0 Global calibration Interrupt Status Flag Uint16 CALIBDONE:1; // 1 Calibration Done Interrupt Flag Bit Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status Flag Bi Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRFLG_REG { Uint32 all; struct HRFLG_BITS bit; }; struct HRCLR_BITS { // bits description Uint16 CALIBINT:1; // 0 Clear Global calibration Interrupt Flag Uint16 CALIBDONE:1; // 1 Clear Calibration Done Interrupt Flag Bit Uint16 CALPRDCHKSTS:1; // 2 Clear Calibration period check status Flag Bit: Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRCLR_REG { Uint32 all; struct HRCLR_BITS bit; }; struct HRFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CALIBDONE:1; // 1 Force Calibration Done Interrupt Flag Bit Uint16 CALPRDCHKSTS:1; // 2 Force Calibration period check status Flag Bit: Uint16 rsvd2:13; // 15:3 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union HRFRC_REG { Uint32 all; struct HRFRC_BITS bit; }; struct HRCAP_REGS { union HRCTL_REG HRCTL; // High-Res Control Register Uint16 rsvd1[2]; // Reserved union HRINTEN_REG HRINTEN; // High-Res Calibration Interrupt Enable Register union HRFLG_REG HRFLG; // High-Res Calibration Interrupt Flag Register union HRCLR_REG HRCLR; // High-Res Calibration Interrupt Clear Register union HRFRC_REG HRFRC; // High-Res Calibration Interrupt Force Register Uint32 HRCALPRD; // High-Res Calibration Period Register Uint32 HRSYSCLKCTR; // High-Res Calibration SYSCLK Counter Register Uint32 HRSYSCLKCAP; // High-Res Calibration SYSCLK Capture Register Uint32 HRCLKCTR; // High-Res Calibration HRCLK Counter Register Uint32 HRCLKCAP; // High-Res Calibration HRCLK Capture Register Uint16 rsvd2[10]; // Reserved }; //--------------------------------------------------------------------------- // ECAP External References & Function Declarations: // extern volatile struct ECAP_REGS ECap1Regs; extern volatile struct ECAP_REGS ECap2Regs; extern volatile struct ECAP_REGS ECap3Regs; extern volatile struct ECAP_REGS ECap4Regs; extern volatile struct ECAP_REGS ECap5Regs; extern volatile struct ECAP_REGS ECap6Regs; extern volatile struct ECAP_REGS ECap7Regs; extern volatile struct HRCAP_REGS HRCap6Regs; extern volatile struct HRCAP_REGS HRCap7Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_epwm.h // // TITLE: EPWM Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // EPWM Individual Register Bit Definitions: struct TBCTL_BITS { // bits description Uint16 CTRMODE:2; // 1:0 Counter Mode Uint16 PHSEN:1; // 2 Phase Load Enable Uint16 PRDLD:1; // 3 Active Period Load Uint16 SYNCOSEL:2; // 5:4 Sync Output Select Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler Uint16 PHSDIR:1; // 13 Phase Direction Bit Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits }; union TBCTL_REG { Uint16 all; struct TBCTL_BITS bit; }; struct TBCTL2_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 SELFCLRTRREM:1; // 5 Self clear Translator reminder Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode Uint16 OSHTSYNC:1; // 7 One shot sync Uint16 rsvd2:4; // 11:8 Reserved Uint16 SYNCOSELX:2; // 13:12 Syncout selection Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event }; union TBCTL2_REG { Uint16 all; struct TBCTL2_BITS bit; }; struct TBSTS_BITS { // bits description Uint16 CTRDIR:1; // 0 Counter Direction Status Uint16 SYNCI:1; // 1 External Input Sync Status Uint16 CTRMAX:1; // 2 Counter Max Latched Status Uint16 rsvd1:13; // 15:3 Reserved }; union TBSTS_REG { Uint16 all; struct TBSTS_BITS bit; }; struct CMPCTL_BITS { // bits description Uint16 LOADAMODE:2; // 1:0 Active Compare A Load Uint16 LOADBMODE:2; // 3:2 Active Compare B Load Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode Uint16 rsvd2:1; // 7 Reserved Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC Uint16 rsvd3:2; // 15:14 Reserved }; union CMPCTL_REG { Uint16 all; struct CMPCTL_BITS bit; }; struct CMPCTL2_BITS { // bits description Uint16 LOADCMODE:2; // 1:0 Active Compare C Load Uint16 LOADDMODE:2; // 3:2 Active Compare D load Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode Uint16 rsvd2:3; // 9:7 Reserved Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC Uint16 rsvd3:2; // 15:14 Reserved }; union CMPCTL2_REG { Uint16 all; struct CMPCTL2_BITS bit; }; struct DBCTL_BITS { // bits description Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control Uint16 POLSEL:2; // 3:2 Polarity Select Control Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable }; union DBCTL_REG { Uint16 all; struct DBCTL_BITS bit; }; struct DBCTL2_BITS { // bits description Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select Uint16 rsvd1:13; // 15:3 Reserved }; union DBCTL2_REG { Uint16 all; struct DBCTL2_BITS bit; }; struct AQCTL_BITS { // bits description Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode Uint16 rsvd2:1; // 7 Reserved Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC Uint16 rsvd3:4; // 15:12 Reserved }; union AQCTL_REG { Uint16 all; struct AQCTL_BITS bit; }; struct AQTSRCSEL_BITS { // bits description Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits Uint16 rsvd1:8; // 15:8 Reserved }; union AQTSRCSEL_REG { Uint16 all; struct AQTSRCSEL_BITS bit; }; struct PCCTL_BITS { // bits description Uint16 CHPEN:1; // 0 PWM chopping enable Uint16 OSHTWTH:4; // 4:1 One-shot pulse width Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle Uint16 rsvd1:5; // 15:11 Reserved }; union PCCTL_REG { Uint16 all; struct PCCTL_BITS bit; }; struct HRCNFG_BITS { // bits description Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit Uint16 AUTOCONV:1; // 6 Autoconversion Bit Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits Uint16 rsvd1:1; // 13 Reserved Uint16 rsvd2:2; // 15:14 Reserved }; union HRCNFG_REG { Uint16 all; struct HRCNFG_BITS bit; }; struct HRPWR_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:4; // 9:6 Reserved Uint16 rsvd7:5; // 14:10 Reserved Uint16 CALPWRON:1; // 15 Calibration Power On }; union HRPWR_REG { Uint16 all; struct HRPWR_BITS bit; }; struct HRMSTEP_BITS { // bits description Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value Uint16 rsvd1:8; // 15:8 Reserved }; union HRMSTEP_REG { Uint16 all; struct HRMSTEP_BITS bit; }; struct HRCNFG2_BITS { // bits description Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits Uint16 rsvd1:8; // 13:6 Reserved Uint16 rsvd2:1; // 14 Reserved Uint16 rsvd3:1; // 15 Reserved }; union HRCNFG2_REG { Uint16 all; struct HRCNFG2_BITS bit; }; struct HRPCTL_BITS { // bits description Uint16 HRPE:1; // 0 High Resolution Period Enable Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: Uint16 rsvd2:9; // 15:7 Reserved }; union HRPCTL_REG { Uint16 all; struct HRPCTL_BITS bit; }; struct TRREM_BITS { // bits description Uint16 TRREM:11; // 10:0 Translator Remainder Bits Uint16 rsvd1:5; // 15:11 Reserved }; union TRREM_REG { Uint16 all; struct TRREM_BITS bit; }; struct GLDCTL_BITS { // bits description Uint16 GLD:1; // 0 Global Shadow to Active load event control Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit Uint16 rsvd1:1; // 6 Reserved Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register Uint16 rsvd2:3; // 15:13 Reserved }; union GLDCTL_REG { Uint16 all; struct GLDCTL_BITS bit; }; struct GLDCFG_BITS { // bits description Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR Uint16 CMPC:1; // 3 Global load event configuration for CMPC Uint16 CMPD:1; // 4 Global load event configuration for CMPD Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC Uint16 rsvd1:5; // 15:11 Reserved }; union GLDCFG_REG { Uint16 all; struct GLDCFG_BITS bit; }; struct EPWMXLINK_BITS { // bits description Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link Uint16 CMPCLINK:4; // 15:12 CMPC Link Uint16 CMPDLINK:4; // 19:16 CMPD Link Uint16 rsvd1:8; // 27:20 Reserved Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link }; union EPWMXLINK_REG { Uint32 all; struct EPWMXLINK_BITS bit; }; struct AQCTLA_BITS { // bits description Uint16 ZRO:2; // 1:0 Action Counter = Zero Uint16 PRD:2; // 3:2 Action Counter = Period Uint16 CAU:2; // 5:4 Action Counter = Compare A Up Uint16 CAD:2; // 7:6 Action Counter = Compare A Down Uint16 CBU:2; // 9:8 Action Counter = Compare B Up Uint16 CBD:2; // 11:10 Action Counter = Compare B Down Uint16 rsvd1:4; // 15:12 Reserved }; union AQCTLA_REG { Uint16 all; struct AQCTLA_BITS bit; }; struct AQCTLA2_BITS { // bits description Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count Uint16 rsvd1:8; // 15:8 Reserved }; union AQCTLA2_REG { Uint16 all; struct AQCTLA2_BITS bit; }; struct AQCTLB_BITS { // bits description Uint16 ZRO:2; // 1:0 Action Counter = Zero Uint16 PRD:2; // 3:2 Action Counter = Period Uint16 CAU:2; // 5:4 Action Counter = Compare A Up Uint16 CAD:2; // 7:6 Action Counter = Compare A Down Uint16 CBU:2; // 9:8 Action Counter = Compare B Up Uint16 CBD:2; // 11:10 Action Counter = Compare B Down Uint16 rsvd1:4; // 15:12 Reserved }; union AQCTLB_REG { Uint16 all; struct AQCTLB_BITS bit; }; struct AQCTLB2_BITS { // bits description Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count Uint16 rsvd1:8; // 15:8 Reserved }; union AQCTLB2_REG { Uint16 all; struct AQCTLB2_BITS bit; }; struct AQSFRC_BITS { // bits description Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked Uint16 OTSFA:1; // 2 One-time SW Force A Output Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked Uint16 OTSFB:1; // 5 One-time SW Force A Output Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options Uint16 rsvd1:8; // 15:8 Reserved }; union AQSFRC_REG { Uint16 all; struct AQSFRC_BITS bit; }; struct AQCSFRC_BITS { // bits description Uint16 CSFA:2; // 1:0 Continuous Software Force on output A Uint16 CSFB:2; // 3:2 Continuous Software Force on output B Uint16 rsvd1:12; // 15:4 Reserved }; union AQCSFRC_REG { Uint16 all; struct AQCSFRC_BITS bit; }; struct DBREDHR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:7; // 7:1 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits }; union DBREDHR_REG { Uint16 all; struct DBREDHR_BITS bit; }; struct DBRED_BITS { // bits description Uint16 DBRED:14; // 13:0 Rising edge delay value Uint16 rsvd1:2; // 15:14 Reserved }; union DBRED_REG { Uint16 all; struct DBRED_BITS bit; }; struct DBFEDHR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:7; // 7:1 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits }; union DBFEDHR_REG { Uint16 all; struct DBFEDHR_BITS bit; }; struct DBFED_BITS { // bits description Uint16 DBFED:14; // 13:0 Falling edge delay value Uint16 rsvd1:2; // 15:14 Reserved }; union DBFED_REG { Uint16 all; struct DBFED_BITS bit; }; struct TBPHS_BITS { // bits description Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) Uint16 TBPHS:16; // 31:16 Phase Offset Register }; union TBPHS_REG { Uint32 all; struct TBPHS_BITS bit; }; struct CMPA_BITS { // bits description Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register Uint16 CMPA:16; // 31:16 Compare A Register }; union CMPA_REG { Uint32 all; struct CMPA_BITS bit; }; struct CMPB_BITS { // bits description Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits Uint16 CMPB:16; // 31:16 Compare B Register }; union CMPB_REG { Uint32 all; struct CMPB_BITS bit; }; struct GLDCTL2_BITS { // bits description Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode Uint16 GFRCLD:1; // 1 Force reload event in one shot mode Uint16 rsvd1:14; // 15:2 Reserved }; union GLDCTL2_REG { Uint16 all; struct GLDCTL2_BITS bit; }; struct TZSEL_BITS { // bits description Uint16 CBC1:1; // 0 TZ1 CBC select Uint16 CBC2:1; // 1 TZ2 CBC select Uint16 CBC3:1; // 2 TZ3 CBC select Uint16 CBC4:1; // 3 TZ4 CBC select Uint16 CBC5:1; // 4 TZ5 CBC select Uint16 CBC6:1; // 5 TZ6 CBC select Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select Uint16 OSHT1:1; // 8 One-shot TZ1 select Uint16 OSHT2:1; // 9 One-shot TZ2 select Uint16 OSHT3:1; // 10 One-shot TZ3 select Uint16 OSHT4:1; // 11 One-shot TZ4 select Uint16 OSHT5:1; // 12 One-shot TZ5 select Uint16 OSHT6:1; // 13 One-shot TZ6 select Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select }; union TZSEL_REG { Uint16 all; struct TZSEL_BITS bit; }; struct TZDCSEL_BITS { // bits description Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 Uint16 rsvd1:4; // 15:12 Reserved }; union TZDCSEL_REG { Uint16 all; struct TZDCSEL_BITS bit; }; struct TZCTL_BITS { // bits description Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTL_REG { Uint16 all; struct TZCTL_BITS bit; }; struct TZCTL2_BITS { // bits description Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN Uint16 rsvd1:3; // 14:12 Reserved Uint16 ETZE:1; // 15 TZCTL2 Enable }; union TZCTL2_REG { Uint16 all; struct TZCTL2_BITS bit; }; struct TZCTLDCA_BITS { // bits description Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTLDCA_REG { Uint16 all; struct TZCTLDCA_BITS bit; }; struct TZCTLDCB_BITS { // bits description Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTLDCB_REG { Uint16 all; struct TZCTLDCB_BITS bit; }; struct TZEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable Uint16 OST:1; // 2 Trip Zones One Shot Int Enable Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable Uint16 rsvd2:9; // 15:7 Reserved }; union TZEINT_REG { Uint16 all; struct TZEINT_BITS bit; }; struct TZFLG_BITS { // bits description Uint16 INT:1; // 0 Global Int Status Flag Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag Uint16 OST:1; // 2 Trip Zones One Shot Flag Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag Uint16 rsvd1:9; // 15:7 Reserved }; union TZFLG_REG { Uint16 all; struct TZFLG_BITS bit; }; struct TZCBCFLG_BITS { // bits description Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 Uint16 rsvd1:8; // 15:8 Reserved }; union TZCBCFLG_REG { Uint16 all; struct TZCBCFLG_BITS bit; }; struct TZOSTFLG_BITS { // bits description Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 Uint16 rsvd1:8; // 15:8 Reserved }; union TZOSTFLG_REG { Uint16 all; struct TZOSTFLG_BITS bit; }; struct TZCLR_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt Clear Flag Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear Uint16 OST:1; // 2 One-Shot Flag Clear Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear Uint16 rsvd1:7; // 13:7 Reserved Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch }; union TZCLR_REG { Uint16 all; struct TZCLR_BITS bit; }; struct TZCBCCLR_BITS { // bits description Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC Uint16 rsvd1:8; // 15:8 Reserved }; union TZCBCCLR_REG { Uint16 all; struct TZCBCCLR_BITS bit; }; struct TZOSTCLR_BITS { // bits description Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST Uint16 rsvd1:8; // 15:8 Reserved }; union TZOSTCLR_REG { Uint16 all; struct TZOSTCLR_BITS bit; }; struct TZFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event Uint16 OST:1; // 2 Force Trip Zones One Shot Event Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 Uint16 rsvd2:9; // 15:7 Reserved }; union TZFRC_REG { Uint16 all; struct TZFRC_BITS bit; }; struct ETSEL_BITS { // bits description Uint16 INTSEL:3; // 2:0 EPWMxINTn Select Uint16 INTEN:1; // 3 EPWMxINTn Enable Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select Uint16 rsvd1:1; // 7 Reserved Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select Uint16 SOCAEN:1; // 11 Start of Conversion A Enable Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select Uint16 SOCBEN:1; // 15 Start of Conversion B Enable }; union ETSEL_REG { Uint16 all; struct ETSEL_BITS bit; }; struct ETPS_BITS { // bits description Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits Uint16 rsvd1:2; // 7:6 Reserved Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter }; union ETPS_REG { Uint16 all; struct ETPS_BITS bit; }; struct ETFLG_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Flag Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Flag Uint16 SOCB:1; // 3 EPWMxSOCB Flag Uint16 rsvd2:12; // 15:4 Reserved }; union ETFLG_REG { Uint16 all; struct ETFLG_BITS bit; }; struct ETCLR_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Clear Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Clear Uint16 SOCB:1; // 3 EPWMxSOCB Clear Uint16 rsvd2:12; // 15:4 Reserved }; union ETCLR_REG { Uint16 all; struct ETCLR_BITS bit; }; struct ETFRC_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Force Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Force Uint16 SOCB:1; // 3 EPWMxSOCB Force Uint16 rsvd2:12; // 15:4 Reserved }; union ETFRC_REG { Uint16 all; struct ETFRC_BITS bit; }; struct ETINTPS_BITS { // bits description Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register Uint16 rsvd1:8; // 15:8 Reserved }; union ETINTPS_REG { Uint16 all; struct ETINTPS_BITS bit; }; struct ETSOCPS_BITS { // bits description Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register }; union ETSOCPS_REG { Uint16 all; struct ETSOCPS_BITS bit; }; struct ETCNTINITCTL_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable }; union ETCNTINITCTL_REG { Uint16 all; struct ETCNTINITCTL_BITS bit; }; struct ETCNTINIT_BITS { // bits description Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits Uint16 rsvd1:4; // 15:12 Reserved }; union ETCNTINIT_REG { Uint16 all; struct ETCNTINIT_BITS bit; }; struct DCTRIPSEL_BITS { // bits description Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select }; union DCTRIPSEL_REG { Uint16 all; struct DCTRIPSEL_BITS bit; }; struct DCACTL_BITS { // bits description Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:2; // 6:5 Reserved Uint16 rsvd3:1; // 7 Reserved Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal Uint16 rsvd4:2; // 11:10 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 rsvd6:2; // 14:13 Reserved Uint16 rsvd7:1; // 15 Reserved }; union DCACTL_REG { Uint16 all; struct DCACTL_BITS bit; }; struct DCBCTL_BITS { // bits description Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:2; // 6:5 Reserved Uint16 rsvd3:1; // 7 Reserved Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal Uint16 rsvd4:2; // 11:10 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 rsvd6:2; // 14:13 Reserved Uint16 rsvd7:1; // 15 Reserved }; union DCBCTL_REG { Uint16 all; struct DCBCTL_BITS bit; }; struct DCFCTL_BITS { // bits description Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select Uint16 BLANKE:1; // 2 Blanking Enable/Disable Uint16 BLANKINV:1; // 3 Blanking Window Inversion Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment Uint16 rsvd1:1; // 6 Reserved Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:2; // 9:8 Reserved Uint16 rsvd4:3; // 12:10 Reserved Uint16 rsvd5:3; // 15:13 Reserved }; union DCFCTL_REG { Uint16 all; struct DCFCTL_BITS bit; }; struct DCCAPCTL_BITS { // bits description Uint16 CAPE:1; // 0 Counter Capture Enable Uint16 SHDWMODE:1; // 1 Counter Capture Mode Uint16 rsvd1:11; // 12:2 Reserved Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag Uint16 CAPMODE:1; // 15 Counter Capture Mode }; union DCCAPCTL_REG { Uint16 all; struct DCCAPCTL_BITS bit; }; struct DCAHTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux Uint16 rsvd2:1; // 15 Reserved }; union DCAHTRIPSEL_REG { Uint16 all; struct DCAHTRIPSEL_BITS bit; }; struct DCALTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux Uint16 rsvd2:1; // 15 Reserved }; union DCALTRIPSEL_REG { Uint16 all; struct DCALTRIPSEL_BITS bit; }; struct DCBHTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux Uint16 rsvd2:1; // 15 Reserved }; union DCBHTRIPSEL_REG { Uint16 all; struct DCBHTRIPSEL_BITS bit; }; struct DCBLTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux Uint16 rsvd2:1; // 15 Reserved }; union DCBLTRIPSEL_REG { Uint16 all; struct DCBLTRIPSEL_BITS bit; }; struct EPWMLOCK_BITS { // bits description Uint16 HRLOCK:1; // 0 HRPWM Register Set Lock Uint16 GLLOCK:1; // 1 Global Load Register Set Lock Uint16 TZCFGLOCK:1; // 2 TripZone Register Set Lock Uint16 TZCLRLOCK:1; // 3 TripZone Clear Register Set Lock Uint16 DCLOCK:1; // 4 Digital Compare Register Set Lock Uint16 rsvd1:11; // 15:5 Reserved Uint16 KEY:16; // 31:16 Key to write to this register }; union EPWMLOCK_REG { Uint32 all; struct EPWMLOCK_BITS bit; }; struct EPWM_REGS { union TBCTL_REG TBCTL; // Time Base Control Register union TBCTL2_REG TBCTL2; // Time Base Control Register 2 Uint16 rsvd1[2]; // Reserved Uint16 TBCTR; // Time Base Counter Register union TBSTS_REG TBSTS; // Time Base Status Register Uint16 rsvd2[2]; // Reserved union CMPCTL_REG CMPCTL; // Counter Compare Control Register union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 Uint16 rsvd3[2]; // Reserved union DBCTL_REG DBCTL; // Dead-Band Generator Control Register union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 Uint16 rsvd4[2]; // Reserved union AQCTL_REG AQCTL; // Action Qualifier Control Register union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register Uint16 rsvd5[2]; // Reserved union PCCTL_REG PCCTL; // PWM Chopper Control Register Uint16 rsvd6[11]; // Reserved union HRCNFG_REG HRCNFG; // HRPWM Configuration Register union HRPWR_REG HRPWR; // HRPWM Power Register Uint16 rsvd7[4]; // Reserved union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register Uint16 rsvd8[5]; // Reserved union HRPCTL_REG HRPCTL; // High Resolution Period Control Register union TRREM_REG TRREM; // Translator High Resolution Remainder Register Uint16 rsvd9[5]; // Reserved union GLDCTL_REG GLDCTL; // Global PWM Load Control Register union GLDCFG_REG GLDCFG; // Global PWM Load Config Register Uint16 rsvd10[2]; // Reserved union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register Uint16 rsvd11[6]; // Reserved union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B Uint16 rsvd12[3]; // Reserved union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register Uint16 rsvd13; // Reserved union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register Uint16 rsvd14[6]; // Reserved union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register Uint16 rsvd15[12]; // Reserved union TBPHS_REG TBPHS; // Time Base Phase High Uint16 TBPRDHR; // Time Base Period High Resolution Register Uint16 TBPRD; // Time Base Period Register Uint16 rsvd16[6]; // Reserved union CMPA_REG CMPA; // Counter Compare A Register union CMPB_REG CMPB; // Compare B Register Uint16 rsvd17; // Reserved Uint16 CMPC; // Counter Compare C Register Uint16 rsvd18; // Reserved Uint16 CMPD; // Counter Compare D Register Uint16 rsvd19[2]; // Reserved union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 Uint16 rsvd20[11]; // Reserved union TZSEL_REG TZSEL; // Trip Zone Select Register Uint16 rsvd21; // Reserved union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register Uint16 rsvd22; // Reserved union TZCTL_REG TZCTL; // Trip Zone Control Register union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B Uint16 rsvd23[5]; // Reserved union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register Uint16 rsvd24[5]; // Reserved union TZFLG_REG TZFLG; // Trip Zone Flag Register union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register Uint16 rsvd25; // Reserved union TZCLR_REG TZCLR; // Trip Zone Clear Register union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register Uint16 rsvd26; // Reserved union TZFRC_REG TZFRC; // Trip Zone Force Register Uint16 rsvd27[8]; // Reserved union ETSEL_REG ETSEL; // Event Trigger Selection Register Uint16 rsvd28; // Reserved union ETPS_REG ETPS; // Event Trigger Pre-Scale Register Uint16 rsvd29; // Reserved union ETFLG_REG ETFLG; // Event Trigger Flag Register Uint16 rsvd30; // Reserved union ETCLR_REG ETCLR; // Event Trigger Clear Register Uint16 rsvd31; // Reserved union ETFRC_REG ETFRC; // Event Trigger Force Register Uint16 rsvd32; // Reserved union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register Uint16 rsvd33; // Reserved union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register Uint16 rsvd34; // Reserved union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register Uint16 rsvd35; // Reserved union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register Uint16 rsvd36[11]; // Reserved union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register Uint16 rsvd37[2]; // Reserved union DCACTL_REG DCACTL; // Digital Compare A Control Register union DCBCTL_REG DCBCTL; // Digital Compare B Control Register Uint16 rsvd38[2]; // Reserved union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register Uint16 DCFOFFSET; // Digital Compare Filter Offset Register Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register Uint16 DCFWINDOW; // Digital Compare Filter Window Register Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register Uint16 rsvd39[2]; // Reserved Uint16 DCCAP; // Digital Compare Counter Capture Register Uint16 rsvd40[2]; // Reserved union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select Uint16 rsvd41[36]; // Reserved union EPWMLOCK_REG EPWMLOCK; // EPWM Lock Register Uint16 rsvd42[4]; // Reserved }; //--------------------------------------------------------------------------- // EPWM External References & Function Declarations: // extern volatile struct EPWM_REGS EPwm1Regs; extern volatile struct EPWM_REGS EPwm2Regs; extern volatile struct EPWM_REGS EPwm3Regs; extern volatile struct EPWM_REGS EPwm4Regs; extern volatile struct EPWM_REGS EPwm5Regs; extern volatile struct EPWM_REGS EPwm6Regs; extern volatile struct EPWM_REGS EPwm7Regs; extern volatile struct EPWM_REGS EPwm8Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_epwm_xbar.h // // TITLE: EPWM_XBAR Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // EPWM_XBAR Individual Register Bit Definitions: struct TRIP4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR }; union TRIP4MUX0TO15CFG_REG { Uint32 all; struct TRIP4MUX0TO15CFG_BITS bit; }; struct TRIP4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR }; union TRIP4MUX16TO31CFG_REG { Uint32 all; struct TRIP4MUX16TO31CFG_BITS bit; }; struct TRIP5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR }; union TRIP5MUX0TO15CFG_REG { Uint32 all; struct TRIP5MUX0TO15CFG_BITS bit; }; struct TRIP5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR }; union TRIP5MUX16TO31CFG_REG { Uint32 all; struct TRIP5MUX16TO31CFG_BITS bit; }; struct TRIP7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR }; union TRIP7MUX0TO15CFG_REG { Uint32 all; struct TRIP7MUX0TO15CFG_BITS bit; }; struct TRIP7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR }; union TRIP7MUX16TO31CFG_REG { Uint32 all; struct TRIP7MUX16TO31CFG_BITS bit; }; struct TRIP8MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR }; union TRIP8MUX0TO15CFG_REG { Uint32 all; struct TRIP8MUX0TO15CFG_BITS bit; }; struct TRIP8MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR }; union TRIP8MUX16TO31CFG_REG { Uint32 all; struct TRIP8MUX16TO31CFG_BITS bit; }; struct TRIP9MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR }; union TRIP9MUX0TO15CFG_REG { Uint32 all; struct TRIP9MUX0TO15CFG_BITS bit; }; struct TRIP9MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR }; union TRIP9MUX16TO31CFG_REG { Uint32 all; struct TRIP9MUX16TO31CFG_BITS bit; }; struct TRIP10MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR }; union TRIP10MUX0TO15CFG_REG { Uint32 all; struct TRIP10MUX0TO15CFG_BITS bit; }; struct TRIP10MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR }; union TRIP10MUX16TO31CFG_REG { Uint32 all; struct TRIP10MUX16TO31CFG_BITS bit; }; struct TRIP11MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR }; union TRIP11MUX0TO15CFG_REG { Uint32 all; struct TRIP11MUX0TO15CFG_BITS bit; }; struct TRIP11MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR }; union TRIP11MUX16TO31CFG_REG { Uint32 all; struct TRIP11MUX16TO31CFG_BITS bit; }; struct TRIP12MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR }; union TRIP12MUX0TO15CFG_REG { Uint32 all; struct TRIP12MUX0TO15CFG_BITS bit; }; struct TRIP12MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR }; union TRIP12MUX16TO31CFG_REG { Uint32 all; struct TRIP12MUX16TO31CFG_BITS bit; }; struct TRIP4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR }; union TRIP4MUXENABLE_REG { Uint32 all; struct TRIP4MUXENABLE_BITS bit; }; struct TRIP5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR }; union TRIP5MUXENABLE_REG { Uint32 all; struct TRIP5MUXENABLE_BITS bit; }; struct TRIP7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR }; union TRIP7MUXENABLE_REG { Uint32 all; struct TRIP7MUXENABLE_BITS bit; }; struct TRIP8MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR }; union TRIP8MUXENABLE_REG { Uint32 all; struct TRIP8MUXENABLE_BITS bit; }; struct TRIP9MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR }; union TRIP9MUXENABLE_REG { Uint32 all; struct TRIP9MUXENABLE_BITS bit; }; struct TRIP10MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR }; union TRIP10MUXENABLE_REG { Uint32 all; struct TRIP10MUXENABLE_BITS bit; }; struct TRIP11MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR }; union TRIP11MUXENABLE_REG { Uint32 all; struct TRIP11MUXENABLE_BITS bit; }; struct TRIP12MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR }; union TRIP12MUXENABLE_REG { Uint32 all; struct TRIP12MUXENABLE_BITS bit; }; struct TRIPOUTINV_BITS { // bits description Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union TRIPOUTINV_REG { Uint32 all; struct TRIPOUTINV_BITS bit; }; struct TRIPLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write protection KEY }; union TRIPLOCK_REG { Uint32 all; struct TRIPLOCK_BITS bit; }; struct EPWM_XBAR_REGS { union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 Uint16 rsvd1[8]; // Reserved union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register Uint16 rsvd2[4]; // Reserved union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register }; //--------------------------------------------------------------------------- // EPWM_XBAR External References & Function Declarations: // extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_eqep.h // // TITLE: EQEP Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // EQEP Individual Register Bit Definitions: struct QDECCTL_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 QSP:1; // 5 QEPS input polarity Uint16 QIP:1; // 6 QEPI input polarity Uint16 QBP:1; // 7 QEPB input polarity Uint16 QAP:1; // 8 QEPA input polarity Uint16 IGATE:1; // 9 Index pulse gating option Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter Uint16 XCR:1; // 11 External Clock Rate Uint16 SPSEL:1; // 12 Sync output pin selection Uint16 SOEN:1; // 13 Sync output-enable Uint16 QSRC:2; // 15:14 Position-counter source selection }; union QDECCTL_REG { Uint16 all; struct QDECCTL_BITS bit; }; struct QEPCTL_BITS { // bits description Uint16 WDE:1; // 0 QEP watchdog enable Uint16 UTE:1; // 1 QEP unit timer enable Uint16 QCLM:1; // 2 QEP capture latch mode Uint16 QPEN:1; // 3 Quadrature postotion counter enable Uint16 IEL:2; // 5:4 Index event latch Uint16 SEL:1; // 6 Strobe event latch Uint16 SWI:1; // 7 Software init position counter Uint16 IEI:2; // 9:8 Index event init of position count Uint16 SEI:2; // 11:10 Strobe event init Uint16 PCRM:2; // 13:12 Postion counter reset Uint16 FREE_SOFT:2; // 15:14 Emulation mode }; union QEPCTL_REG { Uint16 all; struct QEPCTL_BITS bit; }; struct QCAPCTL_BITS { // bits description Uint16 UPPS:4; // 3:0 Unit position event prescaler Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler Uint16 rsvd1:8; // 14:7 Reserved Uint16 CEN:1; // 15 Enable eQEP capture }; union QCAPCTL_REG { Uint16 all; struct QCAPCTL_BITS bit; }; struct QPOSCTL_BITS { // bits description Uint16 PCSPW:12; // 11:0 Position compare sync pulse width Uint16 PCE:1; // 12 Position compare enable/disable Uint16 PCPOL:1; // 13 Polarity of sync output Uint16 PCLOAD:1; // 14 Position compare of shadow load Uint16 PCSHDW:1; // 15 Position compare of shadow enable }; union QPOSCTL_REG { Uint16 all; struct QPOSCTL_BITS bit; }; struct QEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PCE:1; // 1 Position counter error interrupt enable Uint16 QPE:1; // 2 Quadrature phase error interrupt enable Uint16 QDC:1; // 3 Quadrature direction change interrupt enable Uint16 WTO:1; // 4 Watchdog time out interrupt enable Uint16 PCU:1; // 5 Position counter underflow interrupt enable Uint16 PCO:1; // 6 Position counter overflow interrupt enable Uint16 PCR:1; // 7 Position-compare ready interrupt enable Uint16 PCM:1; // 8 Position-compare match interrupt enable Uint16 SEL:1; // 9 Strobe event latch interrupt enable Uint16 IEL:1; // 10 Index event latch interrupt enable Uint16 UTO:1; // 11 Unit time out interrupt enable Uint16 QMAE:1; // 12 QMA error interrupt enable Uint16 rsvd2:3; // 15:13 Reserved }; union QEINT_REG { Uint16 all; struct QEINT_BITS bit; }; struct QFLG_BITS { // bits description Uint16 INT:1; // 0 Global interrupt status flag Uint16 PCE:1; // 1 Position counter error interrupt flag Uint16 PHE:1; // 2 Quadrature phase error interrupt flag Uint16 QDC:1; // 3 Quadrature direction change interrupt flag Uint16 WTO:1; // 4 Watchdog timeout interrupt flag Uint16 PCU:1; // 5 Position counter underflow interrupt flag Uint16 PCO:1; // 6 Position counter overflow interrupt flag Uint16 PCR:1; // 7 Position-compare ready interrupt flag Uint16 PCM:1; // 8 eQEP compare match event interrupt flag Uint16 SEL:1; // 9 Strobe event latch interrupt flag Uint16 IEL:1; // 10 Index event latch interrupt flag Uint16 UTO:1; // 11 Unit time out interrupt flag Uint16 QMAE:1; // 12 QMA error interrupt flag Uint16 rsvd1:3; // 15:13 Reserved }; union QFLG_REG { Uint16 all; struct QFLG_BITS bit; }; struct QCLR_BITS { // bits description Uint16 INT:1; // 0 Global interrupt clear flag Uint16 PCE:1; // 1 Clear position counter error interrupt flag Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag Uint16 IEL:1; // 10 Clear index event latch interrupt flag Uint16 UTO:1; // 11 Clear unit time out interrupt flag Uint16 QMAE:1; // 12 Clear QMA error interrupt flag Uint16 rsvd1:3; // 15:13 Reserved }; union QCLR_REG { Uint16 all; struct QCLR_BITS bit; }; struct QFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PCE:1; // 1 Force position counter error interrupt Uint16 PHE:1; // 2 Force quadrature phase error interrupt Uint16 QDC:1; // 3 Force quadrature direction change interrupt Uint16 WTO:1; // 4 Force watchdog time out interrupt Uint16 PCU:1; // 5 Force position counter underflow interrupt Uint16 PCO:1; // 6 Force position counter overflow interrupt Uint16 PCR:1; // 7 Force position-compare ready interrupt Uint16 PCM:1; // 8 Force position-compare match interrupt Uint16 SEL:1; // 9 Force strobe event latch interrupt Uint16 IEL:1; // 10 Force index event latch interrupt Uint16 UTO:1; // 11 Force unit time out interrupt Uint16 QMAE:1; // 12 Force QMA error interrupt Uint16 rsvd2:3; // 15:13 Reserved }; union QFRC_REG { Uint16 all; struct QFRC_BITS bit; }; struct QEPSTS_BITS { // bits description Uint16 PCEF:1; // 0 Position counter error flag. Uint16 FIMF:1; // 1 First index marker flag Uint16 CDEF:1; // 2 Capture direction error flag Uint16 COEF:1; // 3 Capture overflow error flag Uint16 QDLF:1; // 4 eQEP direction latch flag Uint16 QDF:1; // 5 Quadrature direction flag Uint16 FIDF:1; // 6 The first index marker Uint16 UPEVNT:1; // 7 Unit position event flag Uint16 rsvd1:8; // 15:8 Reserved }; union QEPSTS_REG { Uint16 all; struct QEPSTS_BITS bit; }; struct REV_BITS { // bits description Uint16 MAJOR:3; // 2:0 Major Revision Number Uint16 MINOR:3; // 5:3 Minor Revision Number Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union REV_REG { Uint32 all; struct REV_BITS bit; }; struct QEPSTROBESEL_BITS { // bits description Uint16 STROBESEL:2; // 1:0 QMA Mode Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union QEPSTROBESEL_REG { Uint32 all; struct QEPSTROBESEL_BITS bit; }; struct QMACTRL_BITS { // bits description Uint16 MODE:3; // 2:0 QMA Mode Select Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union QMACTRL_REG { Uint32 all; struct QMACTRL_BITS bit; }; struct EQEP_REGS { Uint32 QPOSCNT; // Position Counter Uint32 QPOSINIT; // Position Counter Init Uint32 QPOSMAX; // Maximum Position Count Uint32 QPOSCMP; // Position Compare Uint32 QPOSILAT; // Index Position Latch Uint32 QPOSSLAT; // Strobe Position Latch Uint32 QPOSLAT; // Position Latch Uint32 QUTMR; // QEP Unit Timer Uint32 QUPRD; // QEP Unit Period Uint16 QWDTMR; // QEP Watchdog Timer Uint16 QWDPRD; // QEP Watchdog Period union QDECCTL_REG QDECCTL; // Quadrature Decoder Control union QEPCTL_REG QEPCTL; // QEP Control union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control union QPOSCTL_REG QPOSCTL; // Position Compare Control union QEINT_REG QEINT; // QEP Interrupt Control union QFLG_REG QFLG; // QEP Interrupt Flag union QCLR_REG QCLR; // QEP Interrupt Clear union QFRC_REG QFRC; // QEP Interrupt Force union QEPSTS_REG QEPSTS; // QEP Status Uint16 QCTMR; // QEP Capture Timer Uint16 QCPRD; // QEP Capture Period Uint16 QCTMRLAT; // QEP Capture Latch Uint16 QCPRDLAT; // QEP Capture Period Latch Uint16 rsvd1[15]; // Reserved union REV_REG REV; // QEP Revision Number union QEPSTROBESEL_REG QEPSTROBESEL; // QEP Strobe select register union QMACTRL_REG QMACTRL; // QMA Control register Uint16 rsvd2[10]; // Reserved }; //--------------------------------------------------------------------------- // EQEP External References & Function Declarations: // extern volatile struct EQEP_REGS EQep1Regs; extern volatile struct EQEP_REGS EQep2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_flash.h // // TITLE: FLASH Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // FLASH Individual Register Bit Definitions: struct FRDCNTL_BITS { // bits description Uint16 rsvd1:8; // 7:0 Reserved Uint16 RWAIT:4; // 11:8 Random Read Waitstate Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union FRDCNTL_REG { Uint32 all; struct FRDCNTL_BITS bit; }; struct FBAC_BITS { // bits description Uint16 rsvd1:8; // 7:0 Reserved Uint16 BAGP:8; // 15:8 Bank Active Grace Period Uint16 rsvd2:16; // 31:16 Reserved }; union FBAC_REG { Uint32 all; struct FBAC_BITS bit; }; struct FBFALLBACK_BITS { // bits description Uint16 BNKPWR0:2; // 1:0 Bank Power Mode of BANK0 Uint16 BNKPWR1:2; // 3:2 Bank Power Mode of BANK1 Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FBFALLBACK_REG { Uint32 all; struct FBFALLBACK_BITS bit; }; struct FBPRDY_BITS { // bits description Uint16 BANK0RDY:1; // 0 Flash Bank Active Power State Uint16 BANK1RDY:1; // 1 Flash Bank Active Power State Uint16 rsvd1:13; // 14:2 Reserved Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode Uint16 rsvd2:16; // 31:16 Reserved }; union FBPRDY_REG { Uint32 all; struct FBPRDY_BITS bit; }; struct FPAC1_BITS { // bits description Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode Uint16 rsvd1:15; // 15:1 Reserved Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count Uint16 rsvd2:4; // 31:28 Reserved }; union FPAC1_REG { Uint32 all; struct FPAC1_BITS bit; }; struct FPAC2_BITS { // bits description Uint16 PAGP:16; // 15:0 Pump Active Grace Period Uint16 rsvd1:16; // 31:16 Reserved }; union FPAC2_REG { Uint32 all; struct FPAC2_BITS bit; }; struct FMSTAT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status Uint16 CSTAT:1; // 4 Command Fail Status Uint16 INVDAT:1; // 5 Invalid Data Uint16 PGM:1; // 6 Program Operation Status Uint16 ERS:1; // 7 Erase Operation Status Uint16 BUSY:1; // 8 Busy Bit Uint16 rsvd4:1; // 9 Reserved Uint16 EV:1; // 10 Erase Verify Status Uint16 rsvd5:1; // 11 Reserved Uint16 PGV:1; // 12 Programming Verify Status Uint16 rsvd6:1; // 13 Reserved Uint16 ILA:1; // 14 Illegal Address Detected Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:14; // 31:18 Reserved }; union FMSTAT_REG { Uint32 all; struct FMSTAT_BITS bit; }; struct FRD_INTF_CTRL_BITS { // bits description Uint16 PREFETCH_EN:1; // 0 Prefetch Enable Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FRD_INTF_CTRL_REG { Uint32 all; struct FRD_INTF_CTRL_BITS bit; }; struct FLASH_CTRL_REGS { union FRDCNTL_REG FRDCNTL; // Flash Read Control Register Uint16 rsvd1[28]; // Reserved union FBAC_REG FBAC; // Flash Bank Access Control Register union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 union FPAC2_REG FPAC2; // Flash Pump Access Control Register 2 Uint16 rsvd2[2]; // Reserved union FMSTAT_REG FMSTAT; // Flash Module Status Register Uint16 rsvd3[340]; // Reserved union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register }; struct ECC_ENABLE_BITS { // bits description Uint16 ENABLE:4; // 3:0 Enable ECC Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECC_ENABLE_REG { Uint32 all; struct ECC_ENABLE_BITS bit; }; struct ERR_STATUS_BITS { // bits description Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred Uint16 rsvd1:13; // 15:3 Reserved Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred Uint16 rsvd2:13; // 31:19 Reserved }; union ERR_STATUS_REG { Uint32 all; struct ERR_STATUS_BITS bit; }; struct ERR_POS_BITS { // bits description Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits Uint16 rsvd1:2; // 7:6 Reserved Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits Uint16 rsvd2:7; // 15:9 Reserved Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits Uint16 rsvd3:2; // 23:22 Reserved Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits Uint16 rsvd4:7; // 31:25 Reserved }; union ERR_POS_REG { Uint32 all; struct ERR_POS_BITS bit; }; struct ERR_STATUS_CLR_BITS { // bits description Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear Uint16 rsvd1:13; // 15:3 Reserved Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear Uint16 rsvd2:13; // 31:19 Reserved }; union ERR_STATUS_CLR_REG { Uint32 all; struct ERR_STATUS_CLR_BITS bit; }; struct ERR_CNT_BITS { // bits description Uint16 ERR_CNT:16; // 15:0 Error counter Uint16 rsvd1:16; // 31:16 Reserved }; union ERR_CNT_REG { Uint32 all; struct ERR_CNT_BITS bit; }; struct ERR_THRESHOLD_BITS { // bits description Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold Uint16 rsvd1:16; // 31:16 Reserved }; union ERR_THRESHOLD_REG { Uint32 all; struct ERR_THRESHOLD_BITS bit; }; struct ERR_INTFLG_BITS { // bits description Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ERR_INTFLG_REG { Uint32 all; struct ERR_INTFLG_BITS bit; }; struct ERR_INTCLR_BITS { // bits description Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ERR_INTCLR_REG { Uint32 all; struct ERR_INTCLR_BITS bit; }; struct FADDR_TEST_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ADDRL:13; // 15:3 ECC Address Low Uint16 ADDRH:6; // 21:16 ECC Address High Uint16 rsvd2:10; // 31:22 Reserved }; union FADDR_TEST_REG { Uint32 all; struct FADDR_TEST_BITS bit; }; struct FECC_TEST_BITS { // bits description Uint16 ECC:8; // 7:0 ECC Control Bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_TEST_REG { Uint32 all; struct FECC_TEST_BITS bit; }; struct FECC_CTRL_BITS { // bits description Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic Uint16 ECC_SELECT:1; // 1 ECC Bit Select Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_CTRL_REG { Uint32 all; struct FECC_CTRL_BITS bit; }; struct FECC_STATUS_BITS { // bits description Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error Uint16 rsvd1:7; // 15:9 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_STATUS_REG { Uint32 all; struct FECC_STATUS_BITS bit; }; struct FLASH_ECC_REGS { union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High union ERR_STATUS_REG ERR_STATUS; // Error Status union ERR_POS_REG ERR_POS; // Error Position union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear union ERR_CNT_REG ERR_CNT; // Error Control union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear Uint32 FDATAH_TEST; // Data High Test Uint32 FDATAL_TEST; // Data Low Test union FADDR_TEST_REG FADDR_TEST; // ECC Test Address union FECC_TEST_REG FECC_TEST; // ECC Test Address union FECC_CTRL_REG FECC_CTRL; // ECC Control Uint32 FOUTH_TEST; // Test Data Out High Uint32 FOUTL_TEST; // Test Data Out Low union FECC_STATUS_REG FECC_STATUS; // ECC Status }; //--------------------------------------------------------------------------- // FLASH External References & Function Declarations: // extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; extern volatile struct FLASH_ECC_REGS Flash0EccRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_fsi.h // // TITLE: FSI Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // FSI Individual Register Bit Definitions: struct TX_MASTER_CTRL_BITS { // bits description Uint16 CORE_RST:1; // 0 Transmitter Master Core Reset Uint16 FLUSH:1; // 1 Flush Operation Start Uint16 rsvd1:6; // 7:2 Reserved Uint16 KEY:8; // 15:8 Write Key }; union TX_MASTER_CTRL_REG { Uint16 all; struct TX_MASTER_CTRL_BITS bit; }; struct TX_CLK_CTRL_BITS { // bits description Uint16 CLK_RST:1; // 0 Soft Reset for the Clock Divider Uint16 CLK_EN:1; // 1 Clock Divider Enable Uint16 PRESCALE_VAL:8; // 9:2 Prescale value Uint16 rsvd1:6; // 15:10 Reserved }; union TX_CLK_CTRL_REG { Uint16 all; struct TX_CLK_CTRL_BITS bit; }; struct TX_OPER_CTRL_LO_BITS { // bits description Uint16 DATA_WIDTH:2; // 1:0 Transmit Data width Uint16 rsvd1:1; // 2 Reserved Uint16 START_MODE:3; // 5:3 Transmission Start Mode Select Uint16 SW_CRC:1; // 6 CRC Source Select Uint16 PING_TO_MODE:1; // 7 Ping Counter Reset Mode Select Uint16 SEL_PLLCLK:1; // 8 Input Clock Select Uint16 rsvd2:7; // 15:9 Reserved }; union TX_OPER_CTRL_LO_REG { Uint16 all; struct TX_OPER_CTRL_LO_BITS bit; }; struct TX_OPER_CTRL_HI_BITS { // bits description Uint16 EXT_TRIG_SEL:5; // 4:0 External Trigger Select Uint16 FORCE_ERR:1; // 5 Error Frame Force Uint16 ECC_SEL:1; // 6 ECC Data Width Select Uint16 rsvd1:9; // 15:7 Reserved }; union TX_OPER_CTRL_HI_REG { Uint16 all; struct TX_OPER_CTRL_HI_BITS bit; }; struct TX_FRAME_CTRL_BITS { // bits description Uint16 FRAME_TYPE:4; // 3:0 Transmit Frame Type Uint16 N_WORDS:4; // 7:4 Number of Words to be Transmitted Uint16 rsvd1:7; // 14:8 Reserved Uint16 START:1; // 15 Start Transmission }; union TX_FRAME_CTRL_REG { Uint16 all; struct TX_FRAME_CTRL_BITS bit; }; struct TX_FRAME_TAG_UDATA_BITS { // bits description Uint16 FRAME_TAG:4; // 3:0 Frame Tag Uint16 rsvd1:4; // 7:4 Reserved Uint16 USER_DATA:8; // 15:8 User Data }; union TX_FRAME_TAG_UDATA_REG { Uint16 all; struct TX_FRAME_TAG_UDATA_BITS bit; }; struct TX_BUF_PTR_LOAD_BITS { // bits description Uint16 BUF_PTR_LOAD:4; // 3:0 Buffer Pointer Force Load Uint16 rsvd1:12; // 15:4 Reserved }; union TX_BUF_PTR_LOAD_REG { Uint16 all; struct TX_BUF_PTR_LOAD_BITS bit; }; struct TX_BUF_PTR_STS_BITS { // bits description Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index Uint16 rsvd1:4; // 7:4 Reserved Uint16 CURR_WORD_CNT:5; // 12:8 Remaining Words in Buffer Uint16 rsvd2:3; // 15:13 Reserved }; union TX_BUF_PTR_STS_REG { Uint16 all; struct TX_BUF_PTR_STS_BITS bit; }; struct TX_PING_CTRL_BITS { // bits description Uint16 CNT_RST:1; // 0 Ping Counter Reset Uint16 TIMER_EN:1; // 1 Ping Counter Enable Uint16 EXT_TRIG_EN:1; // 2 External Trigger Enable Uint16 EXT_TRIG_SEL:5; // 7:3 External Trigger Select Uint16 rsvd1:8; // 15:8 Reserved }; union TX_PING_CTRL_REG { Uint16 all; struct TX_PING_CTRL_BITS bit; }; struct TX_PING_TAG_BITS { // bits description Uint16 TAG:4; // 3:0 Ping Frame Tag Uint16 rsvd1:12; // 15:4 Reserved }; union TX_PING_TAG_REG { Uint16 all; struct TX_PING_TAG_BITS bit; }; struct TX_INT_CTRL_BITS { // bits description Uint16 INT1_EN_FRAME_DONE:1; // 0 Enable Frame Done Interrupt to INT1 Uint16 INT1_EN_BUF_UNDERRUN:1; // 1 Enable Buffer Underrun Interrupt to INT1 Uint16 INT1_EN_BUF_OVERRUN:1; // 2 Enable Buffer Overrun Interrupt to INT1 Uint16 INT1_EN_PING_TO:1; // 3 Enable Ping Timer Interrupt to INT1 Uint16 rsvd1:4; // 7:4 Reserved Uint16 INT2_EN_FRAME_DONE:1; // 8 Enable Frame Done Interrupt to INT2 Uint16 INT2_EN_BUF_UNDERRUN:1; // 9 Enable Buffer Underrun Interrupt to INT2 Uint16 INT2_EN_BUF_OVERRUN:1; // 10 Enable Buffer Overrun Interrupt to INT2 Uint16 INT2_EN_PING_TO:1; // 11 Enable Ping Timer Interrupt to INT2 Uint16 rsvd2:4; // 15:12 Reserved }; union TX_INT_CTRL_REG { Uint16 all; struct TX_INT_CTRL_BITS bit; }; struct TX_DMA_CTRL_BITS { // bits description Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable Uint16 rsvd1:15; // 15:1 Reserved }; union TX_DMA_CTRL_REG { Uint16 all; struct TX_DMA_CTRL_BITS bit; }; struct TX_LOCK_CTRL_BITS { // bits description Uint16 LOCK:1; // 0 Control Register Lock Enable Uint16 rsvd1:7; // 7:1 Reserved Uint16 KEY:8; // 15:8 Write Key }; union TX_LOCK_CTRL_REG { Uint16 all; struct TX_LOCK_CTRL_BITS bit; }; struct TX_EVT_STS_BITS { // bits description Uint16 FRAME_DONE:1; // 0 Frame Done Flag Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Uint16 rsvd1:12; // 15:4 Reserved }; union TX_EVT_STS_REG { Uint16 all; struct TX_EVT_STS_BITS bit; }; struct TX_EVT_CLR_BITS { // bits description Uint16 FRAME_DONE:1; // 0 Frame Done Flag Clear Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Clear Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Clear Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Clear Uint16 rsvd1:12; // 15:4 Reserved }; union TX_EVT_CLR_REG { Uint16 all; struct TX_EVT_CLR_BITS bit; }; struct TX_EVT_FRC_BITS { // bits description Uint16 FRAME_DONE:1; // 0 Frame Done Flag Force Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Force Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Force Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Force Uint16 rsvd1:12; // 15:4 Reserved }; union TX_EVT_FRC_REG { Uint16 all; struct TX_EVT_FRC_BITS bit; }; struct TX_USER_CRC_BITS { // bits description Uint16 USER_CRC:8; // 7:0 User-defined CRC Uint16 rsvd1:8; // 15:8 Reserved }; union TX_USER_CRC_REG { Uint16 all; struct TX_USER_CRC_BITS bit; }; struct TX_ECC_DATA_BITS { // bits description Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits }; union TX_ECC_DATA_REG { Uint32 all; struct TX_ECC_DATA_BITS bit; }; struct TX_ECC_VAL_BITS { // bits description Uint16 ECC_VAL:8; // 7:0 Computed ECC Value Uint16 rsvd1:8; // 15:8 Reserved }; union TX_ECC_VAL_REG { Uint16 all; struct TX_ECC_VAL_BITS bit; }; struct FSI_TX_REGS { union TX_MASTER_CTRL_REG TX_MASTER_CTRL; // Transmit master control register Uint16 rsvd1; // Reserved union TX_CLK_CTRL_REG TX_CLK_CTRL; // Transmit clock control register Uint16 rsvd2; // Reserved union TX_OPER_CTRL_LO_REG TX_OPER_CTRL_LO; // Transmit operation control register low union TX_OPER_CTRL_HI_REG TX_OPER_CTRL_HI; // Transmit operation control register high union TX_FRAME_CTRL_REG TX_FRAME_CTRL; // Transmit frame control register union TX_FRAME_TAG_UDATA_REG TX_FRAME_TAG_UDATA; // Transmit frame tag and user data register union TX_BUF_PTR_LOAD_REG TX_BUF_PTR_LOAD; // Transmit buffer pointer control load register union TX_BUF_PTR_STS_REG TX_BUF_PTR_STS; // Transmit buffer pointer control status register union TX_PING_CTRL_REG TX_PING_CTRL; // Transmit ping control register union TX_PING_TAG_REG TX_PING_TAG; // Transmit ping tag register Uint32 TX_PING_TO_REF; // Transmit ping timeout counter reference Uint32 TX_PING_TO_CNT; // Transmit ping timeout current count union TX_INT_CTRL_REG TX_INT_CTRL; // Transmit interrupt event control register union TX_DMA_CTRL_REG TX_DMA_CTRL; // Transmit DMA event control register union TX_LOCK_CTRL_REG TX_LOCK_CTRL; // Transmit lock control register Uint16 rsvd3; // Reserved union TX_EVT_STS_REG TX_EVT_STS; // Transmit event and error status flag register Uint16 rsvd4; // Reserved union TX_EVT_CLR_REG TX_EVT_CLR; // Transmit event and error clear register union TX_EVT_FRC_REG TX_EVT_FRC; // Transmit event and error flag force register union TX_USER_CRC_REG TX_USER_CRC; // Transmit user-defined CRC register Uint16 rsvd5[7]; // Reserved union TX_ECC_DATA_REG TX_ECC_DATA; // Transmit ECC data register union TX_ECC_VAL_REG TX_ECC_VAL; // Transmit ECC value register Uint16 rsvd6[29]; // Reserved Uint16 TX_BUF_BASE; // Base address for transmit buffer }; struct RX_MASTER_CTRL_BITS { // bits description Uint16 CORE_RST:1; // 0 Receiver Master Core Reset Uint16 INT_LOOPBACK:1; // 1 Internal Loopback Enable Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:5; // 7:3 Reserved Uint16 KEY:8; // 15:8 Write Key }; union RX_MASTER_CTRL_REG { Uint16 all; struct RX_MASTER_CTRL_BITS bit; }; struct RX_OPER_CTRL_BITS { // bits description Uint16 DATA_WIDTH:2; // 1:0 Receive Data Width Select Uint16 rsvd1:1; // 2 Reserved Uint16 N_WORDS:4; // 6:3 Number of Words to be Received Uint16 ECC_SEL:1; // 7 ECC Data Width Select Uint16 PING_WD_RST_MODE:1; // 8 Ping Watchdog Timeout Mode Select Uint16 rsvd2:7; // 15:9 Reserved }; union RX_OPER_CTRL_REG { Uint16 all; struct RX_OPER_CTRL_BITS bit; }; struct RX_FRAME_INFO_BITS { // bits description Uint16 FRAME_TYPE:4; // 3:0 Received Frame Type Uint16 rsvd1:12; // 15:4 Reserved }; union RX_FRAME_INFO_REG { Uint16 all; struct RX_FRAME_INFO_BITS bit; }; struct RX_FRAME_TAG_UDATA_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 FRAME_TAG:4; // 4:1 Received Frame Tag Uint16 rsvd2:3; // 7:5 Reserved Uint16 USER_DATA:8; // 15:8 Received User Data }; union RX_FRAME_TAG_UDATA_REG { Uint16 all; struct RX_FRAME_TAG_UDATA_BITS bit; }; struct RX_DMA_CTRL_BITS { // bits description Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable Uint16 rsvd1:15; // 15:1 Reserved }; union RX_DMA_CTRL_REG { Uint16 all; struct RX_DMA_CTRL_BITS bit; }; struct RX_EVT_STS_BITS { // bits description Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag. Uint16 CRC_ERR:1; // 2 CRC Error Flag Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Uint16 FRAME_DONE:1; // 6 Frame Done Flag Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Uint16 rsvd1:4; // 15:12 Reserved }; union RX_EVT_STS_REG { Uint16 all; struct RX_EVT_STS_BITS bit; }; struct RX_CRC_INFO_BITS { // bits description Uint16 RX_CRC:8; // 7:0 Received CRC Value Uint16 CALC_CRC:8; // 15:8 Hardware Calculated CRC }; union RX_CRC_INFO_REG { Uint16 all; struct RX_CRC_INFO_BITS bit; }; struct RX_EVT_CLR_BITS { // bits description Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Clear Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Clear Uint16 CRC_ERR:1; // 2 CRC Error Flag Clear Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Clear Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Clear Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Clear Uint16 FRAME_DONE:1; // 6 Frame Done Flag Clear Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Clear Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Clear Uint16 PING_FRAME:1; // 9 PING Frame Received Flag Clear Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Clear Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Clear Uint16 rsvd1:4; // 15:12 Reserved }; union RX_EVT_CLR_REG { Uint16 all; struct RX_EVT_CLR_BITS bit; }; struct RX_EVT_FRC_BITS { // bits description Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Force Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Force Uint16 CRC_ERR:1; // 2 CRC Error Flag Force Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Force Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Force Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Force Uint16 FRAME_DONE:1; // 6 Frame Done Flag Force Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Force Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Force Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Force Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Force Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Force Uint16 rsvd1:4; // 15:12 Reserved }; union RX_EVT_FRC_REG { Uint16 all; struct RX_EVT_FRC_BITS bit; }; struct RX_BUF_PTR_LOAD_BITS { // bits description Uint16 BUF_PTR_LOAD:4; // 3:0 Load value for receive buffer pointer Uint16 rsvd1:12; // 15:4 Reserved }; union RX_BUF_PTR_LOAD_REG { Uint16 all; struct RX_BUF_PTR_LOAD_BITS bit; }; struct RX_BUF_PTR_STS_BITS { // bits description Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index Uint16 rsvd1:4; // 7:4 Reserved Uint16 CURR_WORD_CNT:5; // 12:8 Available Words in Buffer Uint16 rsvd2:3; // 15:13 Reserved }; union RX_BUF_PTR_STS_REG { Uint16 all; struct RX_BUF_PTR_STS_BITS bit; }; struct RX_FRAME_WD_CTRL_BITS { // bits description Uint16 FRAME_WD_CNT_RST:1; // 0 Frame Watchdog Counter Reset Uint16 FRAME_WD_EN:1; // 1 Frame Watchdog Counter Enable Uint16 rsvd1:14; // 15:2 Reserved }; union RX_FRAME_WD_CTRL_REG { Uint16 all; struct RX_FRAME_WD_CTRL_BITS bit; }; struct RX_PING_WD_CTRL_BITS { // bits description Uint16 PING_WD_RST:1; // 0 Ping Watchdog Counter Reset Uint16 PING_WD_EN:1; // 1 Ping Watchdog Counter Enable Uint16 rsvd1:14; // 15:2 Reserved }; union RX_PING_WD_CTRL_REG { Uint16 all; struct RX_PING_WD_CTRL_BITS bit; }; struct RX_PING_TAG_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PING_TAG:4; // 4:1 Ping Frame Tag Uint16 rsvd2:11; // 15:5 Reserved }; union RX_PING_TAG_REG { Uint16 all; struct RX_PING_TAG_BITS bit; }; struct RX_INT1_CTRL_BITS { // bits description Uint16 INT1_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT1 Uint16 INT1_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT1 Uint16 INT1_EN_CRC_ERR:1; // 2 Enable CRC Error Interrupt to INT1 Uint16 INT1_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT1 Uint16 INT1_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT1 Uint16 INT1_EN_OVERRUN:1; // 5 Enable Receive Buffer Overrun Interrupt to INT1 Uint16 INT1_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT1 Uint16 INT1_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT1 Uint16 INT1_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT1 Uint16 INT1_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT1 Uint16 INT1_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT1 Uint16 INT1_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT1 Uint16 rsvd1:4; // 15:12 Reserved }; union RX_INT1_CTRL_REG { Uint16 all; struct RX_INT1_CTRL_BITS bit; }; struct RX_INT2_CTRL_BITS { // bits description Uint16 INT2_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT2 Uint16 INT2_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT2 Uint16 INT2_EN_CRC_ERR:1; // 2 Enable CRC Errror Interrupt to INT2 Uint16 INT2_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT2 Uint16 INT2_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT2 Uint16 INT2_EN_OVERRUN:1; // 5 Enable Buffer Overrun Interrupt to INT2 Uint16 INT2_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT2 Uint16 INT2_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT2 Uint16 INT2_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT2 Uint16 INT2_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT2 Uint16 INT2_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT2 Uint16 INT2_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT2 Uint16 rsvd1:4; // 15:12 Reserved }; union RX_INT2_CTRL_REG { Uint16 all; struct RX_INT2_CTRL_BITS bit; }; struct RX_LOCK_CTRL_BITS { // bits description Uint16 LOCK:1; // 0 Control Register Lock Enable Uint16 rsvd1:7; // 7:1 Reserved Uint16 KEY:8; // 15:8 Write Key }; union RX_LOCK_CTRL_REG { Uint16 all; struct RX_LOCK_CTRL_BITS bit; }; struct RX_ECC_DATA_BITS { // bits description Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits }; union RX_ECC_DATA_REG { Uint32 all; struct RX_ECC_DATA_BITS bit; }; struct RX_ECC_VAL_BITS { // bits description Uint16 ECC_VAL:8; // 7:0 Computed ECC Value Uint16 rsvd1:8; // 15:8 Reserved }; union RX_ECC_VAL_REG { Uint16 all; struct RX_ECC_VAL_BITS bit; }; struct RX_ECC_LOG_BITS { // bits description Uint16 SBE:1; // 0 Single Bit Error Detected Uint16 MBE:1; // 1 Multiple Bit Errors Detected Uint16 rsvd1:14; // 15:2 Reserved }; union RX_ECC_LOG_REG { Uint16 all; struct RX_ECC_LOG_BITS bit; }; struct RX_DLYLINE_CTRL_BITS { // bits description Uint16 RXCLK_DLY:5; // 4:0 Delay Line Tap Select for RXCLK Uint16 RXD0_DLY:5; // 9:5 Delay Line Tap Select for RXD0 Uint16 RXD1_DLY:5; // 14:10 Delay Line Tap Select for RXD1 Uint16 rsvd1:1; // 15 Reserved }; union RX_DLYLINE_CTRL_REG { Uint16 all; struct RX_DLYLINE_CTRL_BITS bit; }; struct RX_VIS_1_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 RX_CORE_STS:1; // 3 Receiver Core Status Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union RX_VIS_1_REG { Uint32 all; struct RX_VIS_1_BITS bit; }; struct FSI_RX_REGS { union RX_MASTER_CTRL_REG RX_MASTER_CTRL; // Receive master control register Uint16 rsvd1[3]; // Reserved union RX_OPER_CTRL_REG RX_OPER_CTRL; // Receive operation control register Uint16 rsvd2; // Reserved union RX_FRAME_INFO_REG RX_FRAME_INFO; // Receive frame control register union RX_FRAME_TAG_UDATA_REG RX_FRAME_TAG_UDATA; // Receive frame tag and user data register union RX_DMA_CTRL_REG RX_DMA_CTRL; // Receive DMA event control register Uint16 rsvd3; // Reserved union RX_EVT_STS_REG RX_EVT_STS; // Receive event and error status flag register union RX_CRC_INFO_REG RX_CRC_INFO; // Receive CRC info of received and computed CRC union RX_EVT_CLR_REG RX_EVT_CLR; // Receive event and error clear register union RX_EVT_FRC_REG RX_EVT_FRC; // Receive event and error flag force register union RX_BUF_PTR_LOAD_REG RX_BUF_PTR_LOAD; // Receive buffer pointer load register union RX_BUF_PTR_STS_REG RX_BUF_PTR_STS; // Receive buffer pointer status register union RX_FRAME_WD_CTRL_REG RX_FRAME_WD_CTRL; // Receive frame watchdog control register Uint16 rsvd4; // Reserved Uint32 RX_FRAME_WD_REF; // Receive frame watchdog counter reference Uint32 RX_FRAME_WD_CNT; // Receive frame watchdog current count union RX_PING_WD_CTRL_REG RX_PING_WD_CTRL; // Receive ping watchdog control register union RX_PING_TAG_REG RX_PING_TAG; // Receive ping tag register Uint32 RX_PING_WD_REF; // Receive ping watchdog counter reference Uint32 RX_PING_WD_CNT; // Receive pingwatchdog current count union RX_INT1_CTRL_REG RX_INT1_CTRL; // Receive interrupt control register for RX_INT1 union RX_INT2_CTRL_REG RX_INT2_CTRL; // Receive interrupt control register for RX_INT2 union RX_LOCK_CTRL_REG RX_LOCK_CTRL; // Receive lock control register Uint16 rsvd5; // Reserved union RX_ECC_DATA_REG RX_ECC_DATA; // Receive ECC data register union RX_ECC_VAL_REG RX_ECC_VAL; // Receive ECC value register Uint16 rsvd6; // Reserved Uint32 RX_ECC_SEC_DATA; // Receive ECC corrected data register union RX_ECC_LOG_REG RX_ECC_LOG; // Receive ECC log and status register Uint16 rsvd7[9]; // Reserved union RX_DLYLINE_CTRL_REG RX_DLYLINE_CTRL; // Receive delay line control register Uint16 rsvd8[7]; // Reserved union RX_VIS_1_REG RX_VIS_1; // Receive debug visibility register 1 Uint16 rsvd9[6]; // Reserved Uint16 RX_BUF_BASE; // Base address for receive data buffer }; //--------------------------------------------------------------------------- // FSI External References & Function Declarations: // extern volatile struct FSI_TX_REGS FsiTxaRegs; extern volatile struct FSI_RX_REGS FsiRxaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_gpio.h // // TITLE: GPIO Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // GPIO Individual Register Bit Definitions: struct GPACTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 }; union GPACTRL_REG { Uint32 all; struct GPACTRL_BITS bit; }; struct GPAQSEL1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 }; union GPAQSEL1_REG { Uint32 all; struct GPAQSEL1_BITS bit; }; struct GPAQSEL2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 }; union GPAQSEL2_REG { Uint32 all; struct GPAQSEL2_BITS bit; }; struct GPAMUX1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 }; union GPAMUX1_REG { Uint32 all; struct GPAMUX1_BITS bit; }; struct GPAMUX2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 }; union GPAMUX2_REG { Uint32 all; struct GPAMUX2_BITS bit; }; struct GPADIR_BITS { // bits description Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode }; union GPADIR_REG { Uint32 all; struct GPADIR_BITS bit; }; struct GPAPUD_BITS { // bits description Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin }; union GPAPUD_REG { Uint32 all; struct GPAPUD_BITS bit; }; struct GPAINV_BITS { // bits description Uint16 GPIO0:1; // 0 Input inversion control for this pin Uint16 GPIO1:1; // 1 Input inversion control for this pin Uint16 GPIO2:1; // 2 Input inversion control for this pin Uint16 GPIO3:1; // 3 Input inversion control for this pin Uint16 GPIO4:1; // 4 Input inversion control for this pin Uint16 GPIO5:1; // 5 Input inversion control for this pin Uint16 GPIO6:1; // 6 Input inversion control for this pin Uint16 GPIO7:1; // 7 Input inversion control for this pin Uint16 GPIO8:1; // 8 Input inversion control for this pin Uint16 GPIO9:1; // 9 Input inversion control for this pin Uint16 GPIO10:1; // 10 Input inversion control for this pin Uint16 GPIO11:1; // 11 Input inversion control for this pin Uint16 GPIO12:1; // 12 Input inversion control for this pin Uint16 GPIO13:1; // 13 Input inversion control for this pin Uint16 GPIO14:1; // 14 Input inversion control for this pin Uint16 GPIO15:1; // 15 Input inversion control for this pin Uint16 GPIO16:1; // 16 Input inversion control for this pin Uint16 GPIO17:1; // 17 Input inversion control for this pin Uint16 GPIO18:1; // 18 Input inversion control for this pin Uint16 GPIO19:1; // 19 Input inversion control for this pin Uint16 GPIO20:1; // 20 Input inversion control for this pin Uint16 GPIO21:1; // 21 Input inversion control for this pin Uint16 GPIO22:1; // 22 Input inversion control for this pin Uint16 GPIO23:1; // 23 Input inversion control for this pin Uint16 GPIO24:1; // 24 Input inversion control for this pin Uint16 GPIO25:1; // 25 Input inversion control for this pin Uint16 GPIO26:1; // 26 Input inversion control for this pin Uint16 GPIO27:1; // 27 Input inversion control for this pin Uint16 GPIO28:1; // 28 Input inversion control for this pin Uint16 GPIO29:1; // 29 Input inversion control for this pin Uint16 GPIO30:1; // 30 Input inversion control for this pin Uint16 GPIO31:1; // 31 Input inversion control for this pin }; union GPAINV_REG { Uint32 all; struct GPAINV_BITS bit; }; struct GPAODR_BITS { // bits description Uint16 GPIO0:1; // 0 Output Open-Drain control for this pin Uint16 GPIO1:1; // 1 Output Open-Drain control for this pin Uint16 GPIO2:1; // 2 Output Open-Drain control for this pin Uint16 GPIO3:1; // 3 Output Open-Drain control for this pin Uint16 GPIO4:1; // 4 Output Open-Drain control for this pin Uint16 GPIO5:1; // 5 Output Open-Drain control for this pin Uint16 GPIO6:1; // 6 Output Open-Drain control for this pin Uint16 GPIO7:1; // 7 Output Open-Drain control for this pin Uint16 GPIO8:1; // 8 Output Open-Drain control for this pin Uint16 GPIO9:1; // 9 Output Open-Drain control for this pin Uint16 GPIO10:1; // 10 Output Open-Drain control for this pin Uint16 GPIO11:1; // 11 Output Open-Drain control for this pin Uint16 GPIO12:1; // 12 Output Open-Drain control for this pin Uint16 GPIO13:1; // 13 Output Open-Drain control for this pin Uint16 GPIO14:1; // 14 Output Open-Drain control for this pin Uint16 GPIO15:1; // 15 Output Open-Drain control for this pin Uint16 GPIO16:1; // 16 Output Open-Drain control for this pin Uint16 GPIO17:1; // 17 Output Open-Drain control for this pin Uint16 GPIO18:1; // 18 Output Open-Drain control for this pin Uint16 GPIO19:1; // 19 Output Open-Drain control for this pin Uint16 GPIO20:1; // 20 Output Open-Drain control for this pin Uint16 GPIO21:1; // 21 Output Open-Drain control for this pin Uint16 GPIO22:1; // 22 Output Open-Drain control for this pin Uint16 GPIO23:1; // 23 Output Open-Drain control for this pin Uint16 GPIO24:1; // 24 Output Open-Drain control for this pin Uint16 GPIO25:1; // 25 Output Open-Drain control for this pin Uint16 GPIO26:1; // 26 Output Open-Drain control for this pin Uint16 GPIO27:1; // 27 Output Open-Drain control for this pin Uint16 GPIO28:1; // 28 Output Open-Drain control for this pin Uint16 GPIO29:1; // 29 Output Open-Drain control for this pin Uint16 GPIO30:1; // 30 Output Open-Drain control for this pin Uint16 GPIO31:1; // 31 Output Open-Drain control for this pin }; union GPAODR_REG { Uint32 all; struct GPAODR_BITS bit; }; struct GPAAMSEL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:1; // 4 Reserved Uint16 rsvd6:1; // 5 Reserved Uint16 rsvd7:1; // 6 Reserved Uint16 rsvd8:1; // 7 Reserved Uint16 rsvd9:1; // 8 Reserved Uint16 rsvd10:1; // 9 Reserved Uint16 rsvd11:1; // 10 Reserved Uint16 rsvd12:1; // 11 Reserved Uint16 rsvd13:1; // 12 Reserved Uint16 rsvd14:1; // 13 Reserved Uint16 rsvd15:1; // 14 Reserved Uint16 rsvd16:1; // 15 Reserved Uint16 rsvd17:1; // 16 Reserved Uint16 rsvd18:1; // 17 Reserved Uint16 rsvd19:1; // 18 Reserved Uint16 rsvd20:1; // 19 Reserved Uint16 rsvd21:1; // 20 Reserved Uint16 rsvd22:1; // 21 Reserved Uint16 GPIO22:1; // 22 Analog Mode select for this pin Uint16 GPIO23:1; // 23 Analog Mode select for this pin Uint16 rsvd23:1; // 24 Reserved Uint16 rsvd24:1; // 25 Reserved Uint16 rsvd25:1; // 26 Reserved Uint16 rsvd26:1; // 27 Reserved Uint16 rsvd27:1; // 28 Reserved Uint16 rsvd28:1; // 29 Reserved Uint16 rsvd29:1; // 30 Reserved Uint16 rsvd30:1; // 31 Reserved }; union GPAAMSEL_REG { Uint32 all; struct GPAAMSEL_BITS bit; }; struct GPAGMUX1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 }; union GPAGMUX1_REG { Uint32 all; struct GPAGMUX1_BITS bit; }; struct GPAGMUX2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 }; union GPAGMUX2_REG { Uint32 all; struct GPAGMUX2_BITS bit; }; struct GPACSEL1_BITS { // bits description Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select }; union GPACSEL1_REG { Uint32 all; struct GPACSEL1_BITS bit; }; struct GPACSEL2_BITS { // bits description Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select }; union GPACSEL2_REG { Uint32 all; struct GPACSEL2_BITS bit; }; struct GPACSEL3_BITS { // bits description Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select }; union GPACSEL3_REG { Uint32 all; struct GPACSEL3_BITS bit; }; struct GPACSEL4_BITS { // bits description Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select }; union GPACSEL4_REG { Uint32 all; struct GPACSEL4_BITS bit; }; struct GPALOCK_BITS { // bits description Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin }; union GPALOCK_REG { Uint32 all; struct GPALOCK_BITS bit; }; struct GPACR_BITS { // bits description Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin }; union GPACR_REG { Uint32 all; struct GPACR_BITS bit; }; struct GPBCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 }; union GPBCTRL_REG { Uint32 all; struct GPBCTRL_BITS bit; }; struct GPBQSEL1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 Uint16 rsvd1:2; // 9:8 Reserved Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 Uint16 rsvd2:2; // 13:12 Reserved Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 }; union GPBQSEL1_REG { Uint32 all; struct GPBQSEL1_BITS bit; }; struct GPBQSEL2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 Uint16 rsvd1:2; // 25:24 Reserved Uint16 rsvd2:2; // 27:26 Reserved Uint16 rsvd3:2; // 29:28 Reserved Uint16 rsvd4:2; // 31:30 Reserved }; union GPBQSEL2_REG { Uint32 all; struct GPBQSEL2_BITS bit; }; struct GPBMUX1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 Uint16 rsvd1:2; // 9:8 Reserved Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 Uint16 rsvd2:2; // 13:12 Reserved Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 }; union GPBMUX1_REG { Uint32 all; struct GPBMUX1_BITS bit; }; struct GPBMUX2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 Uint16 rsvd1:2; // 25:24 Reserved Uint16 rsvd2:2; // 27:26 Reserved Uint16 rsvd3:2; // 29:28 Reserved Uint16 rsvd4:2; // 31:30 Reserved }; union GPBMUX2_REG { Uint32 all; struct GPBMUX2_BITS bit; }; struct GPBDIR_BITS { // bits description Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBDIR_REG { Uint32 all; struct GPBDIR_BITS bit; }; struct GPBPUD_BITS { // bits description Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBPUD_REG { Uint32 all; struct GPBPUD_BITS bit; }; struct GPBINV_BITS { // bits description Uint16 GPIO32:1; // 0 Input inversion control for this pin Uint16 GPIO33:1; // 1 Input inversion control for this pin Uint16 GPIO34:1; // 2 Input inversion control for this pin Uint16 GPIO35:1; // 3 Input inversion control for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Input inversion control for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Input inversion control for this pin Uint16 GPIO40:1; // 8 Input inversion control for this pin Uint16 GPIO41:1; // 9 Input inversion control for this pin Uint16 GPIO42:1; // 10 Input inversion control for this pin Uint16 GPIO43:1; // 11 Input inversion control for this pin Uint16 GPIO44:1; // 12 Input inversion control for this pin Uint16 GPIO45:1; // 13 Input inversion control for this pin Uint16 GPIO46:1; // 14 Input inversion control for this pin Uint16 GPIO47:1; // 15 Input inversion control for this pin Uint16 GPIO48:1; // 16 Input inversion control for this pin Uint16 GPIO49:1; // 17 Input inversion control for this pin Uint16 GPIO50:1; // 18 Input inversion control for this pin Uint16 GPIO51:1; // 19 Input inversion control for this pin Uint16 GPIO52:1; // 20 Input inversion control for this pin Uint16 GPIO53:1; // 21 Input inversion control for this pin Uint16 GPIO54:1; // 22 Input inversion control for this pin Uint16 GPIO55:1; // 23 Input inversion control for this pin Uint16 GPIO56:1; // 24 Input inversion control for this pin Uint16 GPIO57:1; // 25 Input inversion control for this pin Uint16 GPIO58:1; // 26 Input inversion control for this pin Uint16 GPIO59:1; // 27 Input inversion control for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBINV_REG { Uint32 all; struct GPBINV_BITS bit; }; struct GPBODR_BITS { // bits description Uint16 GPIO32:1; // 0 Output Open-Drain control for this pin Uint16 GPIO33:1; // 1 Output Open-Drain control for this pin Uint16 GPIO34:1; // 2 Output Open-Drain control for this pin Uint16 GPIO35:1; // 3 Output Open-Drain control for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Output Open-Drain control for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Output Open-Drain control for this pin Uint16 GPIO40:1; // 8 Output Open-Drain control for this pin Uint16 GPIO41:1; // 9 Output Open-Drain control for this pin Uint16 GPIO42:1; // 10 Output Open-Drain control for this pin Uint16 GPIO43:1; // 11 Output Open-Drain control for this pin Uint16 GPIO44:1; // 12 Output Open-Drain control for this pin Uint16 GPIO45:1; // 13 Output Open-Drain control for this pin Uint16 GPIO46:1; // 14 Output Open-Drain control for this pin Uint16 GPIO47:1; // 15 Output Open-Drain control for this pin Uint16 GPIO48:1; // 16 Output Open-Drain control for this pin Uint16 GPIO49:1; // 17 Output Open-Drain control for this pin Uint16 GPIO50:1; // 18 Output Open-Drain control for this pin Uint16 GPIO51:1; // 19 Output Open-Drain control for this pin Uint16 GPIO52:1; // 20 Output Open-Drain control for this pin Uint16 GPIO53:1; // 21 Output Open-Drain control for this pin Uint16 GPIO54:1; // 22 Output Open-Drain control for this pin Uint16 GPIO55:1; // 23 Output Open-Drain control for this pin Uint16 GPIO56:1; // 24 Output Open-Drain control for this pin Uint16 GPIO57:1; // 25 Output Open-Drain control for this pin Uint16 GPIO58:1; // 26 Output Open-Drain control for this pin Uint16 GPIO59:1; // 27 Output Open-Drain control for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBODR_REG { Uint32 all; struct GPBODR_BITS bit; }; struct GPBGMUX1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 Uint16 rsvd1:2; // 9:8 Reserved Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 Uint16 rsvd2:2; // 13:12 Reserved Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 }; union GPBGMUX1_REG { Uint32 all; struct GPBGMUX1_BITS bit; }; struct GPBGMUX2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 Uint16 rsvd1:2; // 25:24 Reserved Uint16 rsvd2:2; // 27:26 Reserved Uint16 rsvd3:2; // 29:28 Reserved Uint16 rsvd4:2; // 31:30 Reserved }; union GPBGMUX2_REG { Uint32 all; struct GPBGMUX2_BITS bit; }; struct GPBCSEL1_BITS { // bits description Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select Uint16 rsvd1:4; // 19:16 Reserved Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select Uint16 rsvd2:4; // 27:24 Reserved Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select }; union GPBCSEL1_REG { Uint32 all; struct GPBCSEL1_BITS bit; }; struct GPBCSEL2_BITS { // bits description Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select }; union GPBCSEL2_REG { Uint32 all; struct GPBCSEL2_BITS bit; }; struct GPBCSEL3_BITS { // bits description Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select }; union GPBCSEL3_REG { Uint32 all; struct GPBCSEL3_BITS bit; }; struct GPBCSEL4_BITS { // bits description Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select Uint16 rsvd1:4; // 19:16 Reserved Uint16 rsvd2:4; // 23:20 Reserved Uint16 rsvd3:4; // 27:24 Reserved Uint16 rsvd4:4; // 31:28 Reserved }; union GPBCSEL4_REG { Uint32 all; struct GPBCSEL4_BITS bit; }; struct GPBLOCK_BITS { // bits description Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBLOCK_REG { Uint32 all; struct GPBLOCK_BITS bit; }; struct GPBCR_BITS { // bits description Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBCR_REG { Uint32 all; struct GPBCR_BITS bit; }; struct GPHCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO224 to GPIO231 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO232 to GPIO239 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO240 to GPIO247 Uint16 rsvd1:8; // 31:24 Reserved }; union GPHCTRL_REG { Uint32 all; struct GPHCTRL_BITS bit; }; struct GPHQSEL1_BITS { // bits description Uint16 GPIO224:2; // 1:0 Select input qualification type for this GPIO Pin Uint16 GPIO225:2; // 3:2 Select input qualification type for this GPIO Pin Uint16 GPIO226:2; // 5:4 Select input qualification type for this GPIO Pin Uint16 GPIO227:2; // 7:6 Select input qualification type for this GPIO Pin Uint16 GPIO228:2; // 9:8 Select input qualification type for this GPIO Pin Uint16 GPIO229:2; // 11:10 Select input qualification type for this GPIO Pin Uint16 GPIO230:2; // 13:12 Select input qualification type for this GPIO Pin Uint16 GPIO231:2; // 15:14 Select input qualification type for this GPIO Pin Uint16 GPIO232:2; // 17:16 Select input qualification type for this GPIO Pin Uint16 GPIO233:2; // 19:18 Select input qualification type for this GPIO Pin Uint16 GPIO234:2; // 21:20 Select input qualification type for this GPIO Pin Uint16 GPIO235:2; // 23:22 Select input qualification type for this GPIO Pin Uint16 GPIO236:2; // 25:24 Select input qualification type for this GPIO Pin Uint16 GPIO237:2; // 27:26 Select input qualification type for this GPIO Pin Uint16 GPIO238:2; // 29:28 Select input qualification type for this GPIO Pin Uint16 GPIO239:2; // 31:30 Select input qualification type for this GPIO Pin }; union GPHQSEL1_REG { Uint32 all; struct GPHQSEL1_BITS bit; }; struct GPHQSEL2_BITS { // bits description Uint16 GPIO240:2; // 1:0 Select input qualification type for this GPIO Pin Uint16 GPIO241:2; // 3:2 Select input qualification type for this GPIO Pin Uint16 GPIO242:2; // 5:4 Select input qualification type for this GPIO Pin Uint16 GPIO243:2; // 7:6 Select input qualification type for this GPIO Pin Uint16 GPIO244:2; // 9:8 Select input qualification type for this GPIO Pin Uint16 GPIO245:2; // 11:10 Select input qualification type for this GPIO Pin Uint16 GPIO246:2; // 13:12 Select input qualification type for this GPIO Pin Uint16 GPIO247:2; // 15:14 Select input qualification type for this GPIO Pin Uint16 rsvd1:2; // 17:16 Reserved Uint16 rsvd2:2; // 19:18 Reserved Uint16 rsvd3:2; // 21:20 Reserved Uint16 rsvd4:2; // 23:22 Reserved Uint16 rsvd5:2; // 25:24 Reserved Uint16 rsvd6:2; // 27:26 Reserved Uint16 rsvd7:2; // 29:28 Reserved Uint16 rsvd8:2; // 31:30 Reserved }; union GPHQSEL2_REG { Uint32 all; struct GPHQSEL2_BITS bit; }; struct GPHINV_BITS { // bits description Uint16 GPIO224:1; // 0 Input inversion control for this pin Uint16 GPIO225:1; // 1 Input inversion control for this pin Uint16 GPIO226:1; // 2 Input inversion control for this pin Uint16 GPIO227:1; // 3 Input inversion control for this pin Uint16 GPIO228:1; // 4 Input inversion control for this pin Uint16 GPIO229:1; // 5 Input inversion control for this pin Uint16 GPIO230:1; // 6 Input inversion control for this pin Uint16 GPIO231:1; // 7 Input inversion control for this pin Uint16 GPIO232:1; // 8 Input inversion control for this pin Uint16 GPIO233:1; // 9 Input inversion control for this pin Uint16 GPIO234:1; // 10 Input inversion control for this pin Uint16 GPIO235:1; // 11 Input inversion control for this pin Uint16 GPIO236:1; // 12 Input inversion control for this pin Uint16 GPIO237:1; // 13 Input inversion control for this pin Uint16 GPIO238:1; // 14 Input inversion control for this pin Uint16 GPIO239:1; // 15 Input inversion control for this pin Uint16 GPIO240:1; // 16 Input inversion control for this pin Uint16 GPIO241:1; // 17 Input inversion control for this pin Uint16 GPIO242:1; // 18 Input inversion control for this pin Uint16 GPIO243:1; // 19 Input inversion control for this pin Uint16 GPIO244:1; // 20 Input inversion control for this pin Uint16 GPIO245:1; // 21 Input inversion control for this pin Uint16 GPIO246:1; // 22 Input inversion control for this pin Uint16 GPIO247:1; // 23 Input inversion control for this pin Uint16 rsvd1:1; // 24 Reserved Uint16 rsvd2:1; // 25 Reserved Uint16 rsvd3:1; // 26 Reserved Uint16 rsvd4:1; // 27 Reserved Uint16 rsvd5:1; // 28 Reserved Uint16 rsvd6:1; // 29 Reserved Uint16 rsvd7:1; // 30 Reserved Uint16 rsvd8:1; // 31 Reserved }; union GPHINV_REG { Uint32 all; struct GPHINV_BITS bit; }; struct GPHAMSEL_BITS { // bits description Uint16 GPIO224:1; // 0 Analog Mode select for this pin Uint16 GPIO225:1; // 1 Analog Mode select for this pin Uint16 GPIO226:1; // 2 Analog Mode select for this pin Uint16 GPIO227:1; // 3 Analog Mode select for this pin Uint16 GPIO228:1; // 4 Analog Mode select for this pin Uint16 GPIO229:1; // 5 Analog Mode select for this pin Uint16 GPIO230:1; // 6 Analog Mode select for this pin Uint16 GPIO231:1; // 7 Analog Mode select for this pin Uint16 GPIO232:1; // 8 Analog Mode select for this pin Uint16 GPIO233:1; // 9 Analog Mode select for this pin Uint16 GPIO234:1; // 10 Analog Mode select for this pin Uint16 GPIO235:1; // 11 Analog Mode select for this pin Uint16 GPIO236:1; // 12 Analog Mode select for this pin Uint16 GPIO237:1; // 13 Analog Mode select for this pin Uint16 GPIO238:1; // 14 Analog Mode select for this pin Uint16 GPIO239:1; // 15 Analog Mode select for this pin Uint16 GPIO240:1; // 16 Analog Mode select for this pin Uint16 GPIO241:1; // 17 Analog Mode select for this pin Uint16 GPIO242:1; // 18 Analog Mode select for this pin Uint16 GPIO243:1; // 19 Analog Mode select for this pin Uint16 GPIO244:1; // 20 Analog Mode select for this pin Uint16 GPIO245:1; // 21 Analog Mode select for this pin Uint16 GPIO246:1; // 22 Analog Mode select for this pin Uint16 GPIO247:1; // 23 Analog Mode select for this pin Uint16 rsvd1:1; // 24 Reserved Uint16 rsvd2:1; // 25 Reserved Uint16 rsvd3:1; // 26 Reserved Uint16 rsvd4:1; // 27 Reserved Uint16 rsvd5:1; // 28 Reserved Uint16 rsvd6:1; // 29 Reserved Uint16 rsvd7:1; // 30 Reserved Uint16 rsvd8:1; // 31 Reserved }; union GPHAMSEL_REG { Uint32 all; struct GPHAMSEL_BITS bit; }; struct GPHLOCK_BITS { // bits description Uint16 GPIO224:1; // 0 Configuration Lock bit for this pin Uint16 GPIO225:1; // 1 Configuration Lock bit for this pin Uint16 GPIO226:1; // 2 Configuration Lock bit for this pin Uint16 GPIO227:1; // 3 Configuration Lock bit for this pin Uint16 GPIO228:1; // 4 Configuration Lock bit for this pin Uint16 GPIO229:1; // 5 Configuration Lock bit for this pin Uint16 GPIO230:1; // 6 Configuration Lock bit for this pin Uint16 GPIO231:1; // 7 Configuration Lock bit for this pin Uint16 GPIO232:1; // 8 Configuration Lock bit for this pin Uint16 GPIO233:1; // 9 Configuration Lock bit for this pin Uint16 GPIO234:1; // 10 Configuration Lock bit for this pin Uint16 GPIO235:1; // 11 Configuration Lock bit for this pin Uint16 GPIO236:1; // 12 Configuration Lock bit for this pin Uint16 GPIO237:1; // 13 Configuration Lock bit for this pin Uint16 GPIO238:1; // 14 Configuration Lock bit for this pin Uint16 GPIO239:1; // 15 Configuration Lock bit for this pin Uint16 GPIO240:1; // 16 Configuration Lock bit for this pin Uint16 GPIO241:1; // 17 Configuration Lock bit for this pin Uint16 GPIO242:1; // 18 Configuration Lock bit for this pin Uint16 GPIO243:1; // 19 Configuration Lock bit for this pin Uint16 GPIO244:1; // 20 Configuration Lock bit for this pin Uint16 GPIO245:1; // 21 Configuration Lock bit for this pin Uint16 GPIO246:1; // 22 Configuration Lock bit for this pin Uint16 GPIO247:1; // 23 Configuration Lock bit for this pin Uint16 rsvd1:1; // 24 Reserved Uint16 rsvd2:1; // 25 Reserved Uint16 rsvd3:1; // 26 Reserved Uint16 rsvd4:1; // 27 Reserved Uint16 rsvd5:1; // 28 Reserved Uint16 rsvd6:1; // 29 Reserved Uint16 rsvd7:1; // 30 Reserved Uint16 rsvd8:1; // 31 Reserved }; union GPHLOCK_REG { Uint32 all; struct GPHLOCK_BITS bit; }; struct GPHCR_BITS { // bits description Uint16 GPIO224:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO225:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO226:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO227:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO228:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO229:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO230:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO231:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO232:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO233:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO234:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO235:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO236:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO237:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO238:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO239:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO240:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO241:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO242:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO243:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO244:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO245:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO246:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO247:1; // 23 Configuration lock commit bit for this pin Uint16 rsvd1:1; // 24 Reserved Uint16 rsvd2:1; // 25 Reserved Uint16 rsvd3:1; // 26 Reserved Uint16 rsvd4:1; // 27 Reserved Uint16 rsvd5:1; // 28 Reserved Uint16 rsvd6:1; // 29 Reserved Uint16 rsvd7:1; // 30 Reserved Uint16 rsvd8:1; // 31 Reserved }; union GPHCR_REG { Uint32 all; struct GPHCR_BITS bit; }; struct GPIO_CTRL_REGS { union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period (GPIO0 to GPIO31) union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualification Type (GPIO0 to GPIO15) union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualification Type (GPIO16 to GPIO31) union GPAMUX1_REG GPAMUX1; // GPIO A Peripheral Mux (GPIO0 to GPIO15) union GPAMUX2_REG GPAMUX2; // GPIO A Peripheral Mux (GPIO16 to GPIO31) union GPADIR_REG GPADIR; // GPIO A Direction (GPIO0 to GPIO31) union GPAPUD_REG GPAPUD; // GPIO A Pull-Up Disable (GPIO0 to GPIO31) Uint16 rsvd1[2]; // Reserved union GPAINV_REG GPAINV; // GPIO A Input Inversion (GPIO0 to GPIO31) union GPAODR_REG GPAODR; // GPIO A Open Drain Output Mode (GPIO0 to GPIO31) union GPAAMSEL_REG GPAAMSEL; // GPIO A Analog Mode Select (GPIO0 to GPIO31) Uint16 rsvd2[10]; // Reserved union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to GPIO15) union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to GPIO31) Uint16 rsvd3[4]; // Reserved union GPACSEL1_REG GPACSEL1; // GPIO A Master Core Select (GPIO0 to GPIO7) union GPACSEL2_REG GPACSEL2; // GPIO A Master Core Select (GPIO8 to GPIO15) union GPACSEL3_REG GPACSEL3; // GPIO A Master Core Select (GPIO16 to GPIO23) union GPACSEL4_REG GPACSEL4; // GPIO A Master Core Select (GPIO24 to GPIO31) Uint16 rsvd4[12]; // Reserved union GPALOCK_REG GPALOCK; // GPIO A Lock Register (GPIO0 to GPIO31) union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to GPIO31) union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period (GPIO32 to GPIO63) union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualification Type (GPIO32 to GPIO47) union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualification Type (GPIO48 to GPIO63) union GPBMUX1_REG GPBMUX1; // GPIO B Peripheral Mux (GPIO32 to GPIO47) union GPBMUX2_REG GPBMUX2; // GPIO B Peripheral Mux (GPIO48 to GPIO63) union GPBDIR_REG GPBDIR; // GPIO B Direction (GPIO32 to GPIO63) union GPBPUD_REG GPBPUD; // GPIO B Pull-Up Disable (GPIO32 to GPIO63) Uint16 rsvd5[2]; // Reserved union GPBINV_REG GPBINV; // GPIO B Input Inversion (GPIO32 to GPIO63) union GPBODR_REG GPBODR; // GPIO B Open Drain Output Mode (GPIO32 to GPIO63) Uint16 rsvd6[12]; // Reserved union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to GPIO47) union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to GPIO63) Uint16 rsvd7[4]; // Reserved union GPBCSEL1_REG GPBCSEL1; // GPIO B Master Core Select (GPIO32 to GPIO39) union GPBCSEL2_REG GPBCSEL2; // GPIO B Master Core Select (GPIO40 to GPIO47) union GPBCSEL3_REG GPBCSEL3; // GPIO B Master Core Select (GPIO48 to GPIO55) union GPBCSEL4_REG GPBCSEL4; // GPIO B Master Core Select (GPIO56 to GPIO63) Uint16 rsvd8[12]; // Reserved union GPBLOCK_REG GPBLOCK; // GPIO B Lock Register (GPIO32 to GPIO63) union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to GPIO63) Uint16 rsvd9[320]; // Reserved union GPHCTRL_REG GPHCTRL; // GPIO H Qualification Sampling Period (GPIO224 to GPIO255) union GPHQSEL1_REG GPHQSEL1; // GPIO H Qualification Type (GPIO224 to GPIO239) union GPHQSEL2_REG GPHQSEL2; // GPIO H Qualification Type (GPIO240 to GPIO255) Uint16 rsvd10[10]; // Reserved union GPHINV_REG GPHINV; // GPIO H Input Inversion (GPIO224 to GPIO255) Uint16 rsvd11[2]; // Reserved union GPHAMSEL_REG GPHAMSEL; // GPIO H Analog Mode Select (GPIO224 to GPIO255) Uint16 rsvd12[38]; // Reserved union GPHLOCK_REG GPHLOCK; // GPIO H Lock Register (GPIO224 to GPIO255) union GPHCR_REG GPHCR; // GPIO H Lock Commit Register (GPIO224 to GPIO255) }; struct GPADAT_BITS { // bits description Uint16 GPIO0:1; // 0 Data Register for this pin Uint16 GPIO1:1; // 1 Data Register for this pin Uint16 GPIO2:1; // 2 Data Register for this pin Uint16 GPIO3:1; // 3 Data Register for this pin Uint16 GPIO4:1; // 4 Data Register for this pin Uint16 GPIO5:1; // 5 Data Register for this pin Uint16 GPIO6:1; // 6 Data Register for this pin Uint16 GPIO7:1; // 7 Data Register for this pin Uint16 GPIO8:1; // 8 Data Register for this pin Uint16 GPIO9:1; // 9 Data Register for this pin Uint16 GPIO10:1; // 10 Data Register for this pin Uint16 GPIO11:1; // 11 Data Register for this pin Uint16 GPIO12:1; // 12 Data Register for this pin Uint16 GPIO13:1; // 13 Data Register for this pin Uint16 GPIO14:1; // 14 Data Register for this pin Uint16 GPIO15:1; // 15 Data Register for this pin Uint16 GPIO16:1; // 16 Data Register for this pin Uint16 GPIO17:1; // 17 Data Register for this pin Uint16 GPIO18:1; // 18 Data Register for this pin Uint16 GPIO19:1; // 19 Data Register for this pin Uint16 GPIO20:1; // 20 Data Register for this pin Uint16 GPIO21:1; // 21 Data Register for this pin Uint16 GPIO22:1; // 22 Data Register for this pin Uint16 GPIO23:1; // 23 Data Register for this pin Uint16 GPIO24:1; // 24 Data Register for this pin Uint16 GPIO25:1; // 25 Data Register for this pin Uint16 GPIO26:1; // 26 Data Register for this pin Uint16 GPIO27:1; // 27 Data Register for this pin Uint16 GPIO28:1; // 28 Data Register for this pin Uint16 GPIO29:1; // 29 Data Register for this pin Uint16 GPIO30:1; // 30 Data Register for this pin Uint16 GPIO31:1; // 31 Data Register for this pin }; union GPADAT_REG { Uint32 all; struct GPADAT_BITS bit; }; struct GPASET_BITS { // bits description Uint16 GPIO0:1; // 0 Output Set bit for this pin Uint16 GPIO1:1; // 1 Output Set bit for this pin Uint16 GPIO2:1; // 2 Output Set bit for this pin Uint16 GPIO3:1; // 3 Output Set bit for this pin Uint16 GPIO4:1; // 4 Output Set bit for this pin Uint16 GPIO5:1; // 5 Output Set bit for this pin Uint16 GPIO6:1; // 6 Output Set bit for this pin Uint16 GPIO7:1; // 7 Output Set bit for this pin Uint16 GPIO8:1; // 8 Output Set bit for this pin Uint16 GPIO9:1; // 9 Output Set bit for this pin Uint16 GPIO10:1; // 10 Output Set bit for this pin Uint16 GPIO11:1; // 11 Output Set bit for this pin Uint16 GPIO12:1; // 12 Output Set bit for this pin Uint16 GPIO13:1; // 13 Output Set bit for this pin Uint16 GPIO14:1; // 14 Output Set bit for this pin Uint16 GPIO15:1; // 15 Output Set bit for this pin Uint16 GPIO16:1; // 16 Output Set bit for this pin Uint16 GPIO17:1; // 17 Output Set bit for this pin Uint16 GPIO18:1; // 18 Output Set bit for this pin Uint16 GPIO19:1; // 19 Output Set bit for this pin Uint16 GPIO20:1; // 20 Output Set bit for this pin Uint16 GPIO21:1; // 21 Output Set bit for this pin Uint16 GPIO22:1; // 22 Output Set bit for this pin Uint16 GPIO23:1; // 23 Output Set bit for this pin Uint16 GPIO24:1; // 24 Output Set bit for this pin Uint16 GPIO25:1; // 25 Output Set bit for this pin Uint16 GPIO26:1; // 26 Output Set bit for this pin Uint16 GPIO27:1; // 27 Output Set bit for this pin Uint16 GPIO28:1; // 28 Output Set bit for this pin Uint16 GPIO29:1; // 29 Output Set bit for this pin Uint16 GPIO30:1; // 30 Output Set bit for this pin Uint16 GPIO31:1; // 31 Output Set bit for this pin }; union GPASET_REG { Uint32 all; struct GPASET_BITS bit; }; struct GPACLEAR_BITS { // bits description Uint16 GPIO0:1; // 0 Output Clear bit for this pin Uint16 GPIO1:1; // 1 Output Clear bit for this pin Uint16 GPIO2:1; // 2 Output Clear bit for this pin Uint16 GPIO3:1; // 3 Output Clear bit for this pin Uint16 GPIO4:1; // 4 Output Clear bit for this pin Uint16 GPIO5:1; // 5 Output Clear bit for this pin Uint16 GPIO6:1; // 6 Output Clear bit for this pin Uint16 GPIO7:1; // 7 Output Clear bit for this pin Uint16 GPIO8:1; // 8 Output Clear bit for this pin Uint16 GPIO9:1; // 9 Output Clear bit for this pin Uint16 GPIO10:1; // 10 Output Clear bit for this pin Uint16 GPIO11:1; // 11 Output Clear bit for this pin Uint16 GPIO12:1; // 12 Output Clear bit for this pin Uint16 GPIO13:1; // 13 Output Clear bit for this pin Uint16 GPIO14:1; // 14 Output Clear bit for this pin Uint16 GPIO15:1; // 15 Output Clear bit for this pin Uint16 GPIO16:1; // 16 Output Clear bit for this pin Uint16 GPIO17:1; // 17 Output Clear bit for this pin Uint16 GPIO18:1; // 18 Output Clear bit for this pin Uint16 GPIO19:1; // 19 Output Clear bit for this pin Uint16 GPIO20:1; // 20 Output Clear bit for this pin Uint16 GPIO21:1; // 21 Output Clear bit for this pin Uint16 GPIO22:1; // 22 Output Clear bit for this pin Uint16 GPIO23:1; // 23 Output Clear bit for this pin Uint16 GPIO24:1; // 24 Output Clear bit for this pin Uint16 GPIO25:1; // 25 Output Clear bit for this pin Uint16 GPIO26:1; // 26 Output Clear bit for this pin Uint16 GPIO27:1; // 27 Output Clear bit for this pin Uint16 GPIO28:1; // 28 Output Clear bit for this pin Uint16 GPIO29:1; // 29 Output Clear bit for this pin Uint16 GPIO30:1; // 30 Output Clear bit for this pin Uint16 GPIO31:1; // 31 Output Clear bit for this pin }; union GPACLEAR_REG { Uint32 all; struct GPACLEAR_BITS bit; }; struct GPATOGGLE_BITS { // bits description Uint16 GPIO0:1; // 0 Output Toggle bit for this pin Uint16 GPIO1:1; // 1 Output Toggle bit for this pin Uint16 GPIO2:1; // 2 Output Toggle bit for this pin Uint16 GPIO3:1; // 3 Output Toggle bit for this pin Uint16 GPIO4:1; // 4 Output Toggle bit for this pin Uint16 GPIO5:1; // 5 Output Toggle bit for this pin Uint16 GPIO6:1; // 6 Output Toggle bit for this pin Uint16 GPIO7:1; // 7 Output Toggle bit for this pin Uint16 GPIO8:1; // 8 Output Toggle bit for this pin Uint16 GPIO9:1; // 9 Output Toggle bit for this pin Uint16 GPIO10:1; // 10 Output Toggle bit for this pin Uint16 GPIO11:1; // 11 Output Toggle bit for this pin Uint16 GPIO12:1; // 12 Output Toggle bit for this pin Uint16 GPIO13:1; // 13 Output Toggle bit for this pin Uint16 GPIO14:1; // 14 Output Toggle bit for this pin Uint16 GPIO15:1; // 15 Output Toggle bit for this pin Uint16 GPIO16:1; // 16 Output Toggle bit for this pin Uint16 GPIO17:1; // 17 Output Toggle bit for this pin Uint16 GPIO18:1; // 18 Output Toggle bit for this pin Uint16 GPIO19:1; // 19 Output Toggle bit for this pin Uint16 GPIO20:1; // 20 Output Toggle bit for this pin Uint16 GPIO21:1; // 21 Output Toggle bit for this pin Uint16 GPIO22:1; // 22 Output Toggle bit for this pin Uint16 GPIO23:1; // 23 Output Toggle bit for this pin Uint16 GPIO24:1; // 24 Output Toggle bit for this pin Uint16 GPIO25:1; // 25 Output Toggle bit for this pin Uint16 GPIO26:1; // 26 Output Toggle bit for this pin Uint16 GPIO27:1; // 27 Output Toggle bit for this pin Uint16 GPIO28:1; // 28 Output Toggle bit for this pin Uint16 GPIO29:1; // 29 Output Toggle bit for this pin Uint16 GPIO30:1; // 30 Output Toggle bit for this pin Uint16 GPIO31:1; // 31 Output Toggle bit for this pin }; union GPATOGGLE_REG { Uint32 all; struct GPATOGGLE_BITS bit; }; struct GPBDAT_BITS { // bits description Uint16 GPIO32:1; // 0 Data Register for this pin Uint16 GPIO33:1; // 1 Data Register for this pin Uint16 GPIO34:1; // 2 Data Register for this pin Uint16 GPIO35:1; // 3 Data Register for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Data Register for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Data Register for this pin Uint16 GPIO40:1; // 8 Data Register for this pin Uint16 GPIO41:1; // 9 Data Register for this pin Uint16 GPIO42:1; // 10 Data Register for this pin Uint16 GPIO43:1; // 11 Data Register for this pin Uint16 GPIO44:1; // 12 Data Register for this pin Uint16 GPIO45:1; // 13 Data Register for this pin Uint16 GPIO46:1; // 14 Data Register for this pin Uint16 GPIO47:1; // 15 Data Register for this pin Uint16 GPIO48:1; // 16 Data Register for this pin Uint16 GPIO49:1; // 17 Data Register for this pin Uint16 GPIO50:1; // 18 Data Register for this pin Uint16 GPIO51:1; // 19 Data Register for this pin Uint16 GPIO52:1; // 20 Data Register for this pin Uint16 GPIO53:1; // 21 Data Register for this pin Uint16 GPIO54:1; // 22 Data Register for this pin Uint16 GPIO55:1; // 23 Data Register for this pin Uint16 GPIO56:1; // 24 Data Register for this pin Uint16 GPIO57:1; // 25 Data Register for this pin Uint16 GPIO58:1; // 26 Data Register for this pin Uint16 GPIO59:1; // 27 Data Register for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBDAT_REG { Uint32 all; struct GPBDAT_BITS bit; }; struct GPBSET_BITS { // bits description Uint16 GPIO32:1; // 0 Output Set bit for this pin Uint16 GPIO33:1; // 1 Output Set bit for this pin Uint16 GPIO34:1; // 2 Output Set bit for this pin Uint16 GPIO35:1; // 3 Output Set bit for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Output Set bit for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Output Set bit for this pin Uint16 GPIO40:1; // 8 Output Set bit for this pin Uint16 GPIO41:1; // 9 Output Set bit for this pin Uint16 GPIO42:1; // 10 Output Set bit for this pin Uint16 GPIO43:1; // 11 Output Set bit for this pin Uint16 GPIO44:1; // 12 Output Set bit for this pin Uint16 GPIO45:1; // 13 Output Set bit for this pin Uint16 GPIO46:1; // 14 Output Set bit for this pin Uint16 GPIO47:1; // 15 Output Set bit for this pin Uint16 GPIO48:1; // 16 Output Set bit for this pin Uint16 GPIO49:1; // 17 Output Set bit for this pin Uint16 GPIO50:1; // 18 Output Set bit for this pin Uint16 GPIO51:1; // 19 Output Set bit for this pin Uint16 GPIO52:1; // 20 Output Set bit for this pin Uint16 GPIO53:1; // 21 Output Set bit for this pin Uint16 GPIO54:1; // 22 Output Set bit for this pin Uint16 GPIO55:1; // 23 Output Set bit for this pin Uint16 GPIO56:1; // 24 Output Set bit for this pin Uint16 GPIO57:1; // 25 Output Set bit for this pin Uint16 GPIO58:1; // 26 Output Set bit for this pin Uint16 GPIO59:1; // 27 Output Set bit for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBSET_REG { Uint32 all; struct GPBSET_BITS bit; }; struct GPBCLEAR_BITS { // bits description Uint16 GPIO32:1; // 0 Output Clear bit for this pin Uint16 GPIO33:1; // 1 Output Clear bit for this pin Uint16 GPIO34:1; // 2 Output Clear bit for this pin Uint16 GPIO35:1; // 3 Output Clear bit for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Output Clear bit for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Output Clear bit for this pin Uint16 GPIO40:1; // 8 Output Clear bit for this pin Uint16 GPIO41:1; // 9 Output Clear bit for this pin Uint16 GPIO42:1; // 10 Output Clear bit for this pin Uint16 GPIO43:1; // 11 Output Clear bit for this pin Uint16 GPIO44:1; // 12 Output Clear bit for this pin Uint16 GPIO45:1; // 13 Output Clear bit for this pin Uint16 GPIO46:1; // 14 Output Clear bit for this pin Uint16 GPIO47:1; // 15 Output Clear bit for this pin Uint16 GPIO48:1; // 16 Output Clear bit for this pin Uint16 GPIO49:1; // 17 Output Clear bit for this pin Uint16 GPIO50:1; // 18 Output Clear bit for this pin Uint16 GPIO51:1; // 19 Output Clear bit for this pin Uint16 GPIO52:1; // 20 Output Clear bit for this pin Uint16 GPIO53:1; // 21 Output Clear bit for this pin Uint16 GPIO54:1; // 22 Output Clear bit for this pin Uint16 GPIO55:1; // 23 Output Clear bit for this pin Uint16 GPIO56:1; // 24 Output Clear bit for this pin Uint16 GPIO57:1; // 25 Output Clear bit for this pin Uint16 GPIO58:1; // 26 Output Clear bit for this pin Uint16 GPIO59:1; // 27 Output Clear bit for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBCLEAR_REG { Uint32 all; struct GPBCLEAR_BITS bit; }; struct GPBTOGGLE_BITS { // bits description Uint16 GPIO32:1; // 0 Output Toggle bit for this pin Uint16 GPIO33:1; // 1 Output Toggle bit for this pin Uint16 GPIO34:1; // 2 Output Toggle bit for this pin Uint16 GPIO35:1; // 3 Output Toggle bit for this pin Uint16 rsvd1:1; // 4 Reserved Uint16 GPIO37:1; // 5 Output Toggle bit for this pin Uint16 rsvd2:1; // 6 Reserved Uint16 GPIO39:1; // 7 Output Toggle bit for this pin Uint16 GPIO40:1; // 8 Output Toggle bit for this pin Uint16 GPIO41:1; // 9 Output Toggle bit for this pin Uint16 GPIO42:1; // 10 Output Toggle bit for this pin Uint16 GPIO43:1; // 11 Output Toggle bit for this pin Uint16 GPIO44:1; // 12 Output Toggle bit for this pin Uint16 GPIO45:1; // 13 Output Toggle bit for this pin Uint16 GPIO46:1; // 14 Output Toggle bit for this pin Uint16 GPIO47:1; // 15 Output Toggle bit for this pin Uint16 GPIO48:1; // 16 Output Toggle bit for this pin Uint16 GPIO49:1; // 17 Output Toggle bit for this pin Uint16 GPIO50:1; // 18 Output Toggle bit for this pin Uint16 GPIO51:1; // 19 Output Toggle bit for this pin Uint16 GPIO52:1; // 20 Output Toggle bit for this pin Uint16 GPIO53:1; // 21 Output Toggle bit for this pin Uint16 GPIO54:1; // 22 Output Toggle bit for this pin Uint16 GPIO55:1; // 23 Output Toggle bit for this pin Uint16 GPIO56:1; // 24 Output Toggle bit for this pin Uint16 GPIO57:1; // 25 Output Toggle bit for this pin Uint16 GPIO58:1; // 26 Output Toggle bit for this pin Uint16 GPIO59:1; // 27 Output Toggle bit for this pin Uint16 rsvd3:1; // 28 Reserved Uint16 rsvd4:1; // 29 Reserved Uint16 rsvd5:1; // 30 Reserved Uint16 rsvd6:1; // 31 Reserved }; union GPBTOGGLE_REG { Uint32 all; struct GPBTOGGLE_BITS bit; }; struct GPHDAT_BITS { // bits description Uint16 GPIO224:1; // 0 Data Register for this pin Uint16 GPIO225:1; // 1 Data Register for this pin Uint16 GPIO226:1; // 2 Data Register for this pin Uint16 GPIO227:1; // 3 Data Register for this pin Uint16 GPIO228:1; // 4 Data Register for this pin Uint16 GPIO229:1; // 5 Data Register for this pin Uint16 GPIO230:1; // 6 Data Register for this pin Uint16 GPIO231:1; // 7 Data Register for this pin Uint16 GPIO232:1; // 8 Data Register for this pin Uint16 GPIO233:1; // 9 Data Register for this pin Uint16 GPIO234:1; // 10 Data Register for this pin Uint16 GPIO235:1; // 11 Data Register for this pin Uint16 GPIO236:1; // 12 Data Register for this pin Uint16 GPIO237:1; // 13 Data Register for this pin Uint16 GPIO238:1; // 14 Data Register for this pin Uint16 GPIO239:1; // 15 Data Register for this pin Uint16 GPIO240:1; // 16 Data Register for this pin Uint16 GPIO241:1; // 17 Data Register for this pin Uint16 GPIO242:1; // 18 Data Register for this pin Uint16 GPIO243:1; // 19 Data Register for this pin Uint16 GPIO244:1; // 20 Data Register for this pin Uint16 GPIO245:1; // 21 Data Register for this pin Uint16 GPIO246:1; // 22 Data Register for this pin Uint16 GPIO247:1; // 23 Data Register for this pin Uint16 rsvd1:1; // 24 Reserved Uint16 rsvd2:1; // 25 Reserved Uint16 rsvd3:1; // 26 Reserved Uint16 rsvd4:1; // 27 Reserved Uint16 rsvd5:1; // 28 Reserved Uint16 rsvd6:1; // 29 Reserved Uint16 rsvd7:1; // 30 Reserved Uint16 rsvd8:1; // 31 Reserved }; union GPHDAT_REG { Uint32 all; struct GPHDAT_BITS bit; }; struct GPIO_DATA_REGS { union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to GPIO31) union GPASET_REG GPASET; // GPIO A Output Set (GPIO0 to GPIO31) union GPACLEAR_REG GPACLEAR; // GPIO A Output Clear (GPIO0 to GPIO31) union GPATOGGLE_REG GPATOGGLE; // GPIO A Output Toggle (GPIO0 to GPIO31) union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to GPIO64) union GPBSET_REG GPBSET; // GPIO B Output Set (GPIO32 to GPIO64) union GPBCLEAR_REG GPBCLEAR; // GPIO B Output Clear (GPIO32 to GPIO64) union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Output Toggle (GPIO32 to GPIO64) Uint16 rsvd1[40]; // Reserved union GPHDAT_REG GPHDAT; // GPIO H Data Register (GPIO0 to GPIO255) Uint16 rsvd2[6]; // Reserved }; //--------------------------------------------------------------------------- // GPIO External References & Function Declarations: // extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; extern volatile struct GPIO_DATA_REGS GpioDataRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_i2c.h // // TITLE: I2C Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // I2C Individual Register Bit Definitions: struct I2COAR_BITS { // bits description Uint16 OAR:10; // 9:0 I2C Own address Uint16 rsvd1:6; // 15:10 Reserved }; union I2COAR_REG { Uint16 all; struct I2COAR_BITS bit; }; struct I2CIER_BITS { // bits description Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable Uint16 NACK:1; // 1 No-acknowledgment interrupt enable Uint16 ARDY:1; // 2 Register-access-ready interrupt enable Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable Uint16 SCD:1; // 5 Stop condition detected interrupt enable Uint16 AAS:1; // 6 Addressed as slave interrupt enable Uint16 rsvd1:9; // 15:7 Reserved }; union I2CIER_REG { Uint16 all; struct I2CIER_BITS bit; }; struct I2CSTR_BITS { // bits description Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. Uint16 SCD:1; // 5 Stop condition detected bit. Uint16 BYTESENT:1; // 6 Byte transmit over indication Uint16 rsvd1:1; // 7 Reserved Uint16 AD0:1; // 8 Address 0 bits Uint16 AAS:1; // 9 Addressed-as-slave bit Uint16 XSMT:1; // 10 Transmit shift register empty bit. Uint16 RSFULL:1; // 11 Receive shift register full bit. Uint16 BB:1; // 12 Bus busy bit. Uint16 NACKSNT:1; // 13 NACK sent bit. Uint16 SDIR:1; // 14 Slave direction bit Uint16 rsvd2:1; // 15 Reserved }; union I2CSTR_REG { Uint16 all; struct I2CSTR_BITS bit; }; struct I2CDRR_BITS { // bits description Uint16 DATA:8; // 7:0 Receive data Uint16 rsvd1:8; // 15:8 Reserved }; union I2CDRR_REG { Uint16 all; struct I2CDRR_BITS bit; }; struct I2CSAR_BITS { // bits description Uint16 SAR:10; // 9:0 Slave Address Uint16 rsvd1:6; // 15:10 Reserved }; union I2CSAR_REG { Uint16 all; struct I2CSAR_BITS bit; }; struct I2CDXR_BITS { // bits description Uint16 DATA:8; // 7:0 Transmit data Uint16 rsvd1:8; // 15:8 Reserved }; union I2CDXR_REG { Uint16 all; struct I2CDXR_BITS bit; }; struct I2CMDR_BITS { // bits description Uint16 BC:3; // 2:0 Bit count bits. Uint16 FDF:1; // 3 Free Data Format Uint16 STB:1; // 4 START Byte Mode Uint16 IRS:1; // 5 I2C Module Reset Uint16 DLB:1; // 6 Digital Loopback Mode Uint16 RM:1; // 7 Repeat Mode Uint16 XA:1; // 8 Expanded Address Mode Uint16 TRX:1; // 9 Transmitter Mode Uint16 MST:1; // 10 Master Mode Uint16 STP:1; // 11 STOP Condition Uint16 rsvd1:1; // 12 Reserved Uint16 STT:1; // 13 START condition bit Uint16 FREE:1; // 14 Debug Action Uint16 NACKMOD:1; // 15 NACK mode bit }; union I2CMDR_REG { Uint16 all; struct I2CMDR_BITS bit; }; struct I2CISRC_BITS { // bits description Uint16 INTCODE:3; // 2:0 Interrupt code bits. Uint16 rsvd1:5; // 7:3 Reserved Uint16 WRITE_ZEROS:4; // 11:8 Always write all 0s to this field Uint16 rsvd2:4; // 15:12 Reserved }; union I2CISRC_REG { Uint16 all; struct I2CISRC_BITS bit; }; struct I2CEMDR_BITS { // bits description Uint16 BC:1; // 0 Backwards compatibility mode Uint16 FCM:1; // 1 Forward Compatibility for Tx behav in Type1 Uint16 rsvd1:14; // 15:2 Reserved }; union I2CEMDR_REG { Uint16 all; struct I2CEMDR_BITS bit; }; struct I2CPSC_BITS { // bits description Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down Uint16 rsvd1:8; // 15:8 Reserved }; union I2CPSC_REG { Uint16 all; struct I2CPSC_BITS bit; }; struct I2CFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag Uint16 TXFFST:5; // 12:8 Transmit FIFO Status Uint16 TXFFRST:1; // 13 Transmit FIFO Reset Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable Uint16 rsvd1:1; // 15 Reserved }; union I2CFFTX_REG { Uint16 all; struct I2CFFTX_BITS bit; }; struct I2CFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag Uint16 RXFFST:5; // 12:8 Receive FIFO Status Uint16 RXFFRST:1; // 13 Receive FIFO Reset Uint16 rsvd1:2; // 15:14 Reserved }; union I2CFFRX_REG { Uint16 all; struct I2CFFRX_BITS bit; }; struct I2C_REGS { union I2COAR_REG I2COAR; // I2C Own address union I2CIER_REG I2CIER; // I2C Interrupt Enable union I2CSTR_REG I2CSTR; // I2C Status Uint16 I2CCLKL; // I2C Clock low-time divider Uint16 I2CCLKH; // I2C Clock high-time divider Uint16 I2CCNT; // I2C Data count union I2CDRR_REG I2CDRR; // I2C Data receive union I2CSAR_REG I2CSAR; // I2C Slave address union I2CDXR_REG I2CDXR; // I2C Data Transmit union I2CMDR_REG I2CMDR; // I2C Mode union I2CISRC_REG I2CISRC; // I2C Interrupt Source union I2CEMDR_REG I2CEMDR; // I2C Extended Mode union I2CPSC_REG I2CPSC; // I2C Prescaler Uint16 rsvd1[19]; // Reserved union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive }; //--------------------------------------------------------------------------- // I2C External References & Function Declarations: // extern volatile struct I2C_REGS I2caRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_input_xbar.h // // TITLE: INPUT_XBAR Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // INPUT_XBAR Individual Register Bit Definitions: struct INPUTSELECTLOCK_BITS { // bits description Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register Uint16 rsvd1:16; // 31:16 Reserved }; union INPUTSELECTLOCK_REG { Uint32 all; struct INPUTSELECTLOCK_BITS bit; }; struct INPUT_XBAR_REGS { Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) Uint16 INPUT15SELECT; // INPUT15 Input Select Register (GPIO0 to x) Uint16 INPUT16SELECT; // INPUT16 Input Select Register (GPIO0 to x) Uint16 rsvd1[14]; // Reserved union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register }; //--------------------------------------------------------------------------- // INPUT_XBAR External References & Function Declarations: // extern volatile struct INPUT_XBAR_REGS InputXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_memconfig.h // // TITLE: MEMCONFIG Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // MEMCONFIG Individual Register Bit Definitions: struct DxLOCK_BITS { // bits description Uint16 LOCK_M0:1; // 0 M0 RAM Lock bits Uint16 LOCK_M1:1; // 1 M1 RAM Lock bits Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DxLOCK_REG { Uint32 all; struct DxLOCK_BITS bit; }; struct DxCOMMIT_BITS { // bits description Uint16 COMMIT_M0:1; // 0 M0 RAM Permanent Lock bits Uint16 COMMIT_M1:1; // 1 M1 RAM Permanent Lock bits Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DxCOMMIT_REG { Uint32 all; struct DxCOMMIT_BITS bit; }; struct DxTEST_BITS { // bits description Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:2; // 7:6 Reserved Uint16 rsvd3:8; // 15:8 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DxTEST_REG { Uint32 all; struct DxTEST_BITS bit; }; struct DxINIT_BITS { // bits description Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DxINIT_REG { Uint32 all; struct DxINIT_BITS bit; }; struct DxINITDONE_BITS { // bits description Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union DxINITDONE_REG { Uint32 all; struct DxINITDONE_BITS bit; }; struct LSxLOCK_BITS { // bits description Uint16 LOCK_LS0:1; // 0 LS0 RAM Lock bits Uint16 LOCK_LS1:1; // 1 LS1 RAM Lock bits Uint16 LOCK_LS2:1; // 2 LS2 RAM Lock bits Uint16 LOCK_LS3:1; // 3 LS3 RAM Lock bits Uint16 LOCK_LS4:1; // 4 LS4 RAM Lock bits Uint16 LOCK_LS5:1; // 5 LS5 RAM Lock bits Uint16 LOCK_LS6:1; // 6 LS6 RAM Lock bits Uint16 LOCK_LS7:1; // 7 LS7 RAM Lock bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxLOCK_REG { Uint32 all; struct LSxLOCK_BITS bit; }; struct LSxCOMMIT_BITS { // bits description Uint16 COMMIT_LS0:1; // 0 LS0 RAM Permanent Lock bits Uint16 COMMIT_LS1:1; // 1 LS1 RAM Permanent Lock bits Uint16 COMMIT_LS2:1; // 2 LS2 RAM Permanent Lock bits Uint16 COMMIT_LS3:1; // 3 LS3 RAM Permanent Lock bits Uint16 COMMIT_LS4:1; // 4 LS4 RAM Permanent Lock bits Uint16 COMMIT_LS5:1; // 5 LS5 RAM Permanent Lock bits Uint16 COMMIT_LS6:1; // 6 LS6 RAM Permanent Lock bits Uint16 COMMIT_LS7:1; // 7 LS7 RAM Permanent Lock bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxCOMMIT_REG { Uint32 all; struct LSxCOMMIT_BITS bit; }; struct LSxMSEL_BITS { // bits description Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM Uint16 MSEL_LS6:2; // 13:12 Master Select for LS6 RAM Uint16 MSEL_LS7:2; // 15:14 Master Select for LS7 RAM Uint16 rsvd1:16; // 31:16 Reserved }; union LSxMSEL_REG { Uint32 all; struct LSxMSEL_BITS bit; }; struct LSxCLAPGM_BITS { // bits description Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA Uint16 CLAPGM_LS6:1; // 6 Selects LS6 RAM as program vs data memory for CLA Uint16 CLAPGM_LS7:1; // 7 Selects LS7 RAM as program vs data memory for CLA Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxCLAPGM_REG { Uint32 all; struct LSxCLAPGM_BITS bit; }; struct LSxACCPROT0_BITS { // bits description Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM Uint16 rsvd3:6; // 23:18 Reserved Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM Uint16 rsvd4:6; // 31:26 Reserved }; union LSxACCPROT0_REG { Uint32 all; struct LSxACCPROT0_BITS bit; }; struct LSxACCPROT1_BITS { // bits description Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 FETCHPROT_LS6:1; // 16 Fetch Protection For LS6 RAM Uint16 CPUWRPROT_LS6:1; // 17 CPU WR Protection For LS6 RAM Uint16 rsvd3:6; // 23:18 Reserved Uint16 FETCHPROT_LS7:1; // 24 Fetch Protection For LS7 RAM Uint16 CPUWRPROT_LS7:1; // 25 CPU WR Protection For LS7 RAM Uint16 rsvd4:6; // 31:26 Reserved }; union LSxACCPROT1_REG { Uint32 all; struct LSxACCPROT1_BITS bit; }; struct LSxTEST_BITS { // bits description Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM Uint16 TEST_LS6:2; // 13:12 Selects the different modes for LS6 RAM Uint16 TEST_LS7:2; // 15:14 Selects the different modes for LS7 RAM Uint16 rsvd1:16; // 31:16 Reserved }; union LSxTEST_REG { Uint32 all; struct LSxTEST_BITS bit; }; struct LSxINIT_BITS { // bits description Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. Uint16 INIT_LS6:1; // 6 RAM Initialization control for LS6 RAM. Uint16 INIT_LS7:1; // 7 RAM Initialization control for LS7 RAM. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxINIT_REG { Uint32 all; struct LSxINIT_BITS bit; }; struct LSxINITDONE_BITS { // bits description Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. Uint16 INITDONE_LS6:1; // 6 RAM Initialization status for LS6 RAM. Uint16 INITDONE_LS7:1; // 7 RAM Initialization status for LS7 RAM. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxINITDONE_REG { Uint32 all; struct LSxINITDONE_BITS bit; }; struct GSxLOCK_BITS { // bits description Uint16 LOCK_GS0:1; // 0 GS0 RAM Lock bits Uint16 LOCK_GS1:1; // 1 GS1 RAM Lock bits Uint16 LOCK_GS2:1; // 2 GS2 RAM Lock bits Uint16 LOCK_GS3:1; // 3 GS3 RAM Lock bits Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:1; // 11 Reserved Uint16 rsvd9:1; // 12 Reserved Uint16 rsvd10:1; // 13 Reserved Uint16 rsvd11:1; // 14 Reserved Uint16 rsvd12:1; // 15 Reserved Uint16 rsvd13:16; // 31:16 Reserved }; union GSxLOCK_REG { Uint32 all; struct GSxLOCK_BITS bit; }; struct GSxCOMMIT_BITS { // bits description Uint16 COMMIT_GS0:1; // 0 GS0 RAM Permanent Lock bits Uint16 COMMIT_GS1:1; // 1 GS1 RAM Permanent Lock bits Uint16 COMMIT_GS2:1; // 2 GS2 RAM Permanent Lock bits Uint16 COMMIT_GS3:1; // 3 GS3 RAM Permanent Lock bits Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:1; // 11 Reserved Uint16 rsvd9:1; // 12 Reserved Uint16 rsvd10:1; // 13 Reserved Uint16 rsvd11:1; // 14 Reserved Uint16 rsvd12:1; // 15 Reserved Uint16 rsvd13:16; // 31:16 Reserved }; union GSxCOMMIT_REG { Uint32 all; struct GSxCOMMIT_BITS bit; }; struct GSxACCPROT0_BITS { // bits description Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT0_REG { Uint32 all; struct GSxACCPROT0_BITS bit; }; struct GSxTEST_BITS { // bits description Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM Uint16 rsvd1:2; // 9:8 Reserved Uint16 rsvd2:2; // 11:10 Reserved Uint16 rsvd3:2; // 13:12 Reserved Uint16 rsvd4:2; // 15:14 Reserved Uint16 rsvd5:2; // 17:16 Reserved Uint16 rsvd6:2; // 19:18 Reserved Uint16 rsvd7:2; // 21:20 Reserved Uint16 rsvd8:2; // 23:22 Reserved Uint16 rsvd9:2; // 25:24 Reserved Uint16 rsvd10:2; // 27:26 Reserved Uint16 rsvd11:2; // 29:28 Reserved Uint16 rsvd12:2; // 31:30 Reserved }; union GSxTEST_REG { Uint32 all; struct GSxTEST_BITS bit; }; struct GSxINIT_BITS { // bits description Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:1; // 11 Reserved Uint16 rsvd9:1; // 12 Reserved Uint16 rsvd10:1; // 13 Reserved Uint16 rsvd11:1; // 14 Reserved Uint16 rsvd12:1; // 15 Reserved Uint16 rsvd13:16; // 31:16 Reserved }; union GSxINIT_REG { Uint32 all; struct GSxINIT_BITS bit; }; struct GSxINITDONE_BITS { // bits description Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:1; // 11 Reserved Uint16 rsvd9:1; // 12 Reserved Uint16 rsvd10:1; // 13 Reserved Uint16 rsvd11:1; // 14 Reserved Uint16 rsvd12:1; // 15 Reserved Uint16 rsvd13:16; // 31:16 Reserved }; union GSxINITDONE_REG { Uint32 all; struct GSxINITDONE_BITS bit; }; struct MSGxLOCK_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 LOCK_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM Lock bits Uint16 LOCK_CLA1TOCPU:1; // 2 CLA1TOCPU RAM Lock bits Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union MSGxLOCK_REG { Uint32 all; struct MSGxLOCK_BITS bit; }; struct MSGxCOMMIT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 COMMIT_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM control fields COMMIT bit Uint16 COMMIT_CLA1TOCPU:1; // 2 CLA1TOCPU RAM control fields COMMIT bit Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union MSGxCOMMIT_REG { Uint32 all; struct MSGxCOMMIT_BITS bit; }; struct MSGxTEST_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select Uint16 rsvd2:2; // 7:6 Reserved Uint16 rsvd3:2; // 9:8 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union MSGxTEST_REG { Uint32 all; struct MSGxTEST_BITS bit; }; struct MSGxINIT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union MSGxINIT_REG { Uint32 all; struct MSGxINIT_BITS bit; }; struct MSGxINITDONE_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union MSGxINITDONE_REG { Uint32 all; struct MSGxINITDONE_BITS bit; }; struct MEM_CFG_REGS { union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register Uint16 rsvd1[12]; // Reserved union DxTEST_REG DxTEST; // Dedicated RAM TEST Register union DxINIT_REG DxINIT; // Dedicated RAM Init Register union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register Uint16 rsvd2[10]; // Reserved union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 Uint16 rsvd3[4]; // Reserved union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register Uint16 rsvd4[10]; // Reserved union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register Uint16 rsvd5[4]; // Reserved union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 Uint16 rsvd6[6]; // Reserved union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register Uint16 rsvd7[10]; // Reserved union MSGxLOCK_REG MSGxLOCK; // Message RAM Config Lock Register union MSGxCOMMIT_REG MSGxCOMMIT; // Message RAM Config Lock Commit Register Uint16 rsvd8[12]; // Reserved union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register union MSGxINIT_REG MSGxINIT; // Message RAM Init Register union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register Uint16 rsvd9[10]; // Reserved }; struct NMAVFLG_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVFLG_REG { Uint32 all; struct NMAVFLG_BITS bit; }; struct NMAVSET_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVSET_REG { Uint32 all; struct NMAVSET_BITS bit; }; struct NMAVCLR_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVCLR_REG { Uint32 all; struct NMAVCLR_BITS bit; }; struct NMAVINTEN_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable Uint16 rsvd1:1; // 3 Reserved Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable Uint16 rsvd2:1; // 7 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:6; // 15:10 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union NMAVINTEN_REG { Uint32 all; struct NMAVINTEN_BITS bit; }; struct MAVFLG_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVFLG_REG { Uint32 all; struct MAVFLG_BITS bit; }; struct MAVSET_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVSET_REG { Uint32 all; struct MAVSET_BITS bit; }; struct MAVCLR_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVCLR_REG { Uint32 all; struct MAVCLR_BITS bit; }; struct MAVINTEN_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVINTEN_REG { Uint32 all; struct MAVINTEN_BITS bit; }; struct ACCESS_PROTECTION_REGS { union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address Uint16 rsvd1[2]; // Reserved Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address Uint16 rsvd2[10]; // Reserved union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address Uint16 rsvd3[18]; // Reserved }; struct UCERRFLG_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRFLG_REG { Uint32 all; struct UCERRFLG_BITS bit; }; struct UCERRSET_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRSET_REG { Uint32 all; struct UCERRSET_BITS bit; }; struct UCERRCLR_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRCLR_REG { Uint32 all; struct UCERRCLR_BITS bit; }; struct CERRFLG_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRFLG_REG { Uint32 all; struct CERRFLG_BITS bit; }; struct CERRSET_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRSET_REG { Uint32 all; struct CERRSET_BITS bit; }; struct CERRCLR_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRCLR_REG { Uint32 all; struct CERRCLR_BITS bit; }; struct CEINTFLG_BITS { // bits description Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTFLG_REG { Uint32 all; struct CEINTFLG_BITS bit; }; struct CEINTCLR_BITS { // bits description Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTCLR_REG { Uint32 all; struct CEINTCLR_BITS bit; }; struct CEINTSET_BITS { // bits description Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTSET_REG { Uint32 all; struct CEINTSET_BITS bit; }; struct CEINTEN_BITS { // bits description Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTEN_REG { Uint32 all; struct CEINTEN_BITS bit; }; struct MEMORY_ERROR_REGS { union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address Uint16 rsvd1[20]; // Reserved union CERRFLG_REG CERRFLG; // Correctable Error Flag Register union CERRSET_REG CERRSET; // Correctable Error Flag Set Register union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register Uint32 CCPUREADDR; // Correctable CPU Read Error Address Uint16 rsvd2[6]; // Reserved Uint32 CERRCNT; // Correctable Error Count Register Uint32 CERRTHRES; // Correctable Error Threshold Value Register union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register Uint16 rsvd3[6]; // Reserved }; //--------------------------------------------------------------------------- // MEMCONFIG External References & Function Declarations: // extern volatile struct MEM_CFG_REGS MemCfgRegs; extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_nmiintrupt.h // // TITLE: NMIINTRUPT Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // NMIINTRUPT Individual Register Bit Definitions: struct NMICFG_BITS { // bits description Uint16 NMIE:1; // 0 Global NMI Enable Uint16 rsvd1:15; // 15:1 Reserved }; union NMICFG_REG { Uint16 all; struct NMICFG_BITS bit; }; struct NMIFLG_BITS { // bits description Uint16 NMIINT:1; // 0 NMI Interrupt Flag Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:1; // 8 Reserved Uint16 rsvd5:1; // 9 Reserved Uint16 rsvd6:1; // 10 Reserved Uint16 rsvd7:1; // 11 Reserved Uint16 rsvd8:1; // 12 Reserved Uint16 SWERR:1; // 13 SW Error Force NMI Flag Uint16 rsvd9:2; // 15:14 Reserved }; union NMIFLG_REG { Uint16 all; struct NMIFLG_BITS bit; }; struct NMIFLGCLR_BITS { // bits description Uint16 NMIINT:1; // 0 NMIINT Flag Clear Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:1; // 8 Reserved Uint16 rsvd5:1; // 9 Reserved Uint16 rsvd6:1; // 10 Reserved Uint16 rsvd7:1; // 11 Reserved Uint16 rsvd8:1; // 12 Reserved Uint16 SWERR:1; // 13 SWERR Flag Clear Uint16 rsvd9:2; // 15:14 Reserved }; union NMIFLGCLR_REG { Uint16 all; struct NMIFLGCLR_BITS bit; }; struct NMIFLGFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force Uint16 rsvd2:1; // 4 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:1; // 11 Reserved Uint16 rsvd9:1; // 12 Reserved Uint16 SWERR:1; // 13 SWERR Flag Force Uint16 rsvd10:2; // 15:14 Reserved }; union NMIFLGFRC_REG { Uint16 all; struct NMIFLGFRC_BITS bit; }; struct NMISHDFLG_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag Uint16 rsvd2:1; // 4 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:1; // 11 Reserved Uint16 rsvd9:1; // 12 Reserved Uint16 SWERR:1; // 13 SW Error Force NMI Flag Uint16 rsvd10:2; // 15:14 Reserved }; union NMISHDFLG_REG { Uint16 all; struct NMISHDFLG_BITS bit; }; struct NMI_INTRUPT_REGS { union NMICFG_REG NMICFG; // NMI Configuration Register union NMIFLG_REG NMIFLG; // NMI Flag Register (SYSRsn Clear) union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register Uint16 NMIWDCNT; // NMI Watchdog Counter Register Uint16 NMIWDPRD; // NMI Watchdog Period Register union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register }; //--------------------------------------------------------------------------- // NMIINTRUPT External References & Function Declarations: // extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_output_xbar.h // // TITLE: OUTPUT_XBAR Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // OUTPUT_XBAR Individual Register Bit Definitions: struct OUTPUT1MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUX0TO15CFG_REG { Uint32 all; struct OUTPUT1MUX0TO15CFG_BITS bit; }; struct OUTPUT1MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUX16TO31CFG_REG { Uint32 all; struct OUTPUT1MUX16TO31CFG_BITS bit; }; struct OUTPUT2MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUX0TO15CFG_REG { Uint32 all; struct OUTPUT2MUX0TO15CFG_BITS bit; }; struct OUTPUT2MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUX16TO31CFG_REG { Uint32 all; struct OUTPUT2MUX16TO31CFG_BITS bit; }; struct OUTPUT3MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUX0TO15CFG_REG { Uint32 all; struct OUTPUT3MUX0TO15CFG_BITS bit; }; struct OUTPUT3MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUX16TO31CFG_REG { Uint32 all; struct OUTPUT3MUX16TO31CFG_BITS bit; }; struct OUTPUT4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUX0TO15CFG_REG { Uint32 all; struct OUTPUT4MUX0TO15CFG_BITS bit; }; struct OUTPUT4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUX16TO31CFG_REG { Uint32 all; struct OUTPUT4MUX16TO31CFG_BITS bit; }; struct OUTPUT5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUX0TO15CFG_REG { Uint32 all; struct OUTPUT5MUX0TO15CFG_BITS bit; }; struct OUTPUT5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUX16TO31CFG_REG { Uint32 all; struct OUTPUT5MUX16TO31CFG_BITS bit; }; struct OUTPUT6MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUX0TO15CFG_REG { Uint32 all; struct OUTPUT6MUX0TO15CFG_BITS bit; }; struct OUTPUT6MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUX16TO31CFG_REG { Uint32 all; struct OUTPUT6MUX16TO31CFG_BITS bit; }; struct OUTPUT7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUX0TO15CFG_REG { Uint32 all; struct OUTPUT7MUX0TO15CFG_BITS bit; }; struct OUTPUT7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUX16TO31CFG_REG { Uint32 all; struct OUTPUT7MUX16TO31CFG_BITS bit; }; struct OUTPUT8MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUX0TO15CFG_REG { Uint32 all; struct OUTPUT8MUX0TO15CFG_BITS bit; }; struct OUTPUT8MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUX16TO31CFG_REG { Uint32 all; struct OUTPUT8MUX16TO31CFG_BITS bit; }; struct OUTPUT1MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUXENABLE_REG { Uint32 all; struct OUTPUT1MUXENABLE_BITS bit; }; struct OUTPUT2MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUXENABLE_REG { Uint32 all; struct OUTPUT2MUXENABLE_BITS bit; }; struct OUTPUT3MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUXENABLE_REG { Uint32 all; struct OUTPUT3MUXENABLE_BITS bit; }; struct OUTPUT4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUXENABLE_REG { Uint32 all; struct OUTPUT4MUXENABLE_BITS bit; }; struct OUTPUT5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUXENABLE_REG { Uint32 all; struct OUTPUT5MUXENABLE_BITS bit; }; struct OUTPUT6MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUXENABLE_REG { Uint32 all; struct OUTPUT6MUXENABLE_BITS bit; }; struct OUTPUT7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUXENABLE_REG { Uint32 all; struct OUTPUT7MUXENABLE_BITS bit; }; struct OUTPUT8MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUXENABLE_REG { Uint32 all; struct OUTPUT8MUXENABLE_BITS bit; }; struct OUTPUTLATCH_BITS { // bits description Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCH_REG { Uint32 all; struct OUTPUTLATCH_BITS bit; }; struct OUTPUTLATCHCLR_BITS { // bits description Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHCLR_REG { Uint32 all; struct OUTPUTLATCHCLR_BITS bit; }; struct OUTPUTLATCHFRC_BITS { // bits description Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHFRC_REG { Uint32 all; struct OUTPUTLATCHFRC_BITS bit; }; struct OUTPUTLATCHENABLE_BITS { // bits description Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Selects the output latch to drive output1 for OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Selects the output latch to drive output2 for OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Selects the output latch to drive output3 for OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Selects the output latch to drive output4 for OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Selects the output latch to drive output5 for OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Selects the output latch to drive output6 for OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Selects the output latch to drive output7 for OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHENABLE_REG { Uint32 all; struct OUTPUTLATCHENABLE_BITS bit; }; struct OUTPUTINV_BITS { // bits description Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTINV_REG { Uint32 all; struct OUTPUTINV_BITS bit; }; struct OUTPUTLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write Protection KEY }; union OUTPUTLOCK_REG { Uint32 all; struct OUTPUTLOCK_BITS bit; }; struct OUTPUT_XBAR_REGS { union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion Uint16 rsvd1[4]; // Reserved union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register }; //--------------------------------------------------------------------------- // OUTPUT_XBAR External References & Function Declarations: // extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_pga.h // // TITLE: PGA Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PGA Individual Register Bit Definitions: struct PGACTL_BITS { // bits description Uint16 PGAEN:1; // 0 PGA Enable Uint16 FILTRESSEL:4; // 4:1 Filter Resistor Select Uint16 GAIN:3; // 7:5 PGA gain setting Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGACTL_REG { Uint32 all; struct PGACTL_BITS bit; }; struct PGALOCK_BITS { // bits description Uint16 PGACTL:1; // 0 Lock bit for PGACTL. Uint16 rsvd1:1; // 1 Reserved Uint16 PGAGAIN3TRIM:1; // 2 Lock bit for PGAGAIN3TRIM. Uint16 PGAGAIN6TRIM:1; // 3 Lock bit for PGAGAIN6TRIM. Uint16 PGAGAIN12TRIM:1; // 4 Lock bit for PGAGAIN12TRIM. Uint16 PGAGAIN24TRIM:1; // 5 Lock bit for PGAGAIN24TRIM. Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:8; // 15:8 Reserved }; union PGALOCK_REG { Uint16 all; struct PGALOCK_BITS bit; }; struct PGAGAIN3TRIM_BITS { // bits description Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 3 Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 3 }; union PGAGAIN3TRIM_REG { Uint16 all; struct PGAGAIN3TRIM_BITS bit; }; struct PGAGAIN6TRIM_BITS { // bits description Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 6 Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 6 }; union PGAGAIN6TRIM_REG { Uint16 all; struct PGAGAIN6TRIM_BITS bit; }; struct PGAGAIN12TRIM_BITS { // bits description Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 12 Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 12 }; union PGAGAIN12TRIM_REG { Uint16 all; struct PGAGAIN12TRIM_BITS bit; }; struct PGAGAIN24TRIM_BITS { // bits description Uint16 GAINTRIM:8; // 7:0 Gain TRIM value, when gain setting is 24 Uint16 OFFSETTRIM:8; // 15:8 OFFSET TRIM value, when Gain setting is 24 }; union PGAGAIN24TRIM_REG { Uint16 all; struct PGAGAIN24TRIM_BITS bit; }; struct PGATYPE_BITS { // bits description Uint16 REV:8; // 7:0 PGA Revision Field Uint16 TYPE:8; // 15:8 PGA Type Field }; union PGATYPE_REG { Uint16 all; struct PGATYPE_BITS bit; }; struct PGA_REGS { union PGACTL_REG PGACTL; // PGA Control Register union PGALOCK_REG PGALOCK; // PGA Lock Register Uint16 rsvd1; // Reserved union PGAGAIN3TRIM_REG PGAGAIN3TRIM; // PGA Gain Trim Register for a gain setting of 3 union PGAGAIN6TRIM_REG PGAGAIN6TRIM; // PGA Gain Trim Register for a gain setting of 6 union PGAGAIN12TRIM_REG PGAGAIN12TRIM; // PGA Gain Trim Register for a gain setting of 12 union PGAGAIN24TRIM_REG PGAGAIN24TRIM; // PGA Gain Trim Register for a gain setting of 24 union PGATYPE_REG PGATYPE; // PGA Type Register Uint16 rsvd2[7]; // Reserved }; //--------------------------------------------------------------------------- // PGA External References & Function Declarations: // extern volatile struct PGA_REGS Pga1Regs; extern volatile struct PGA_REGS Pga2Regs; extern volatile struct PGA_REGS Pga3Regs; extern volatile struct PGA_REGS Pga4Regs; extern volatile struct PGA_REGS Pga5Regs; extern volatile struct PGA_REGS Pga6Regs; extern volatile struct PGA_REGS Pga7Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_piectrl.h // // TITLE: PIECTRL Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PIECTRL Individual Register Bit Definitions: struct PIECTRL_BITS { // bits description Uint16 ENPIE:1; // 0 PIE Enable Uint16 PIEVECT:15; // 15:1 PIE Vector Address }; union PIECTRL_REG { Uint16 all; struct PIECTRL_BITS bit; }; struct PIEACK_BITS { // bits description Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 Uint16 rsvd1:4; // 15:12 Reserved }; union PIEACK_REG { Uint16 all; struct PIEACK_BITS bit; }; struct PIEIER1_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 }; union PIEIER1_REG { Uint16 all; struct PIEIER1_BITS bit; }; struct PIEIFR1_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 }; union PIEIFR1_REG { Uint16 all; struct PIEIFR1_BITS bit; }; struct PIEIER2_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 }; union PIEIER2_REG { Uint16 all; struct PIEIER2_BITS bit; }; struct PIEIFR2_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 }; union PIEIFR2_REG { Uint16 all; struct PIEIFR2_BITS bit; }; struct PIEIER3_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 }; union PIEIER3_REG { Uint16 all; struct PIEIER3_BITS bit; }; struct PIEIFR3_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 }; union PIEIFR3_REG { Uint16 all; struct PIEIFR3_BITS bit; }; struct PIEIER4_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 }; union PIEIER4_REG { Uint16 all; struct PIEIER4_BITS bit; }; struct PIEIFR4_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 }; union PIEIFR4_REG { Uint16 all; struct PIEIFR4_BITS bit; }; struct PIEIER5_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 }; union PIEIER5_REG { Uint16 all; struct PIEIER5_BITS bit; }; struct PIEIFR5_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 }; union PIEIFR5_REG { Uint16 all; struct PIEIFR5_BITS bit; }; struct PIEIER6_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 }; union PIEIER6_REG { Uint16 all; struct PIEIER6_BITS bit; }; struct PIEIFR6_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 }; union PIEIFR6_REG { Uint16 all; struct PIEIFR6_BITS bit; }; struct PIEIER7_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 }; union PIEIER7_REG { Uint16 all; struct PIEIER7_BITS bit; }; struct PIEIFR7_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 }; union PIEIFR7_REG { Uint16 all; struct PIEIFR7_BITS bit; }; struct PIEIER8_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 }; union PIEIER8_REG { Uint16 all; struct PIEIER8_BITS bit; }; struct PIEIFR8_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 }; union PIEIFR8_REG { Uint16 all; struct PIEIFR8_BITS bit; }; struct PIEIER9_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 }; union PIEIER9_REG { Uint16 all; struct PIEIER9_BITS bit; }; struct PIEIFR9_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 }; union PIEIFR9_REG { Uint16 all; struct PIEIFR9_BITS bit; }; struct PIEIER10_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 }; union PIEIER10_REG { Uint16 all; struct PIEIER10_BITS bit; }; struct PIEIFR10_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 }; union PIEIFR10_REG { Uint16 all; struct PIEIFR10_BITS bit; }; struct PIEIER11_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 }; union PIEIER11_REG { Uint16 all; struct PIEIER11_BITS bit; }; struct PIEIFR11_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 }; union PIEIFR11_REG { Uint16 all; struct PIEIFR11_BITS bit; }; struct PIEIER12_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 }; union PIEIER12_REG { Uint16 all; struct PIEIER12_BITS bit; }; struct PIEIFR12_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 }; union PIEIFR12_REG { Uint16 all; struct PIEIFR12_BITS bit; }; struct PIE_CTRL_REGS { union PIECTRL_REG PIECTRL; // ePIE Control Register union PIEACK_REG PIEACK; // Interrupt Acknowledge Register union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register }; //--------------------------------------------------------------------------- // PIECTRL External References & Function Declarations: // extern volatile struct PIE_CTRL_REGS PieCtrlRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_pievect.h // // TITLE: F28004x Device PIE Vector Table Definitions // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PIE Interrupt Vector Table Definition: // Create a user type called PINT (pointer to interrupt): typedef __interrupt void (*PINT)(void); // Define Vector Table: struct PIE_VECT_TABLE { PINT PIE1_RESERVED_INT; // Reserved PINT PIE2_RESERVED_INT; // Reserved PINT PIE3_RESERVED_INT; // Reserved PINT PIE4_RESERVED_INT; // Reserved PINT PIE5_RESERVED_INT; // Reserved PINT PIE6_RESERVED_INT; // Reserved PINT PIE7_RESERVED_INT; // Reserved PINT PIE8_RESERVED_INT; // Reserved PINT PIE9_RESERVED_INT; // Reserved PINT PIE10_RESERVED_INT; // Reserved PINT PIE11_RESERVED_INT; // Reserved PINT PIE12_RESERVED_INT; // Reserved PINT PIE13_RESERVED_INT; // Reserved PINT TIMER1_INT; // CPU Timer 1 Interrupt PINT TIMER2_INT; // CPU Timer 2 Interrupt PINT DATALOG_INT; // Datalogging Interrupt PINT RTOS_INT; // RTOS Interrupt PINT EMU_INT; // Emulation Interrupt PINT NMI_INT; // Non-Maskable Interrupt PINT ILLEGAL_INT; // Illegal Operation Trap PINT USER1_INT; // User Defined Trap 1 PINT USER2_INT; // User Defined Trap 2 PINT USER3_INT; // User Defined Trap 3 PINT USER4_INT; // User Defined Trap 4 PINT USER5_INT; // User Defined Trap 5 PINT USER6_INT; // User Defined Trap 6 PINT USER7_INT; // User Defined Trap 7 PINT USER8_INT; // User Defined Trap 8 PINT USER9_INT; // User Defined Trap 9 PINT USER10_INT; // User Defined Trap 10 PINT USER11_INT; // User Defined Trap 11 PINT USER12_INT; // User Defined Trap 12 PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 PINT XINT1_INT; // 1.4 - XINT1 Interrupt PINT XINT2_INT; // 1.5 - XINT2 Interrupt PINT PIE14_RESERVED_INT; // 1.6 - Reserved PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt PINT ECAP7_INT; // 4.7 - eCAP7 Interrupt PINT PIE15_RESERVED_INT; // 4.8 - Reserved PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt PINT PIE16_RESERVED_INT; // 5.3 - Reserved PINT PIE17_RESERVED_INT; // 5.4 - Reserved PINT PIE18_RESERVED_INT; // 5.5 - Reserved PINT PIE19_RESERVED_INT; // 5.6 - Reserved PINT PIE20_RESERVED_INT; // 5.7 - Reserved PINT PIE21_RESERVED_INT; // 5.8 - Reserved PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt PINT PIE22_RESERVED_INT; // 6.5 - Reserved PINT PIE23_RESERVED_INT; // 6.6 - Reserved PINT PIE24_RESERVED_INT; // 6.7 - Reserved PINT PIE25_RESERVED_INT; // 6.8 - Reserved PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt PINT PIE26_RESERVED_INT; // 7.7 - Reserved PINT PIE27_RESERVED_INT; // 7.8 - Reserved PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 PINT PIE28_RESERVED_INT; // 8.3 - Reserved PINT PIE29_RESERVED_INT; // 8.4 - Reserved PINT PIE30_RESERVED_INT; // 8.5 - Reserved PINT PIE31_RESERVED_INT; // 8.6 - Reserved PINT PIE32_RESERVED_INT; // 8.7 - Reserved PINT PIE33_RESERVED_INT; // 8.8 - Reserved PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt PINT CANA0_INT; // 9.5 - CANA Interrupt 0 PINT CANA1_INT; // 9.6 - CANA Interrupt 1 PINT CANB0_INT; // 9.7 - CANB Interrupt 0 PINT CANB1_INT; // 9.8 - CANB Interrupt 1 PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 PINT XINT3_INT; // 12.1 - XINT3 Interrupt PINT XINT4_INT; // 12.2 - XINT4 Interrupt PINT XINT5_INT; // 12.3 - XINT5 Interrupt PINT PIE34_RESERVED_INT; // 12.4 - Reserved PINT PIE35_RESERVED_INT; // 12.5 - Reserved PINT PIE36_RESERVED_INT; // 12.6 - Reserved PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt PINT PIE37_RESERVED_INT; // 1.9 - Reserved PINT PIE38_RESERVED_INT; // 1.10 - Reserved PINT PIE39_RESERVED_INT; // 1.11 - Reserved PINT PIE40_RESERVED_INT; // 1.12 - Reserved PINT PIE41_RESERVED_INT; // 1.13 - Reserved PINT PIE42_RESERVED_INT; // 1.14 - Reserved PINT PIE43_RESERVED_INT; // 1.15 - Reserved PINT PIE44_RESERVED_INT; // 1.16 - Reserved PINT PIE45_RESERVED_INT; // 2.9 - Reserved PINT PIE46_RESERVED_INT; // 2.10 - Reserved PINT PIE47_RESERVED_INT; // 2.11 - Reserved PINT PIE48_RESERVED_INT; // 2.12 - Reserved PINT PIE49_RESERVED_INT; // 2.13 - Reserved PINT PIE50_RESERVED_INT; // 2.14 - Reserved PINT PIE51_RESERVED_INT; // 2.15 - Reserved PINT PIE52_RESERVED_INT; // 2.16 - Reserved PINT PIE53_RESERVED_INT; // 3.9 - Reserved PINT PIE54_RESERVED_INT; // 3.10 - Reserved PINT PIE55_RESERVED_INT; // 3.11 - Reserved PINT PIE56_RESERVED_INT; // 3.12 - Reserved PINT PIE57_RESERVED_INT; // 3.13 - Reserved PINT PIE58_RESERVED_INT; // 3.14 - Reserved PINT PIE59_RESERVED_INT; // 3.15 - Reserved PINT PIE60_RESERVED_INT; // 3.16 - Reserved PINT PIE61_RESERVED_INT; // 4.9 - Reserved PINT PIE62_RESERVED_INT; // 4.10 - Reserved PINT PIE63_RESERVED_INT; // 4.11 - Reserved PINT PIE64_RESERVED_INT; // 4.12 - Reserved PINT PIE65_RESERVED_INT; // 4.13 - Reserved PINT ECAP6_2_INT; // 4.14 - eCAP6_2 Interrupt PINT ECAP7_2_INT; // 4.15 - eCAP7_2 Interrupt PINT PIE66_RESERVED_INT; // 4.16 - Reserved PINT SD1_INT; // 5.9 - SD1 Interrupt PINT PIE67_RESERVED_INT; // 5.10 - Reserved PINT PIE68_RESERVED_INT; // 5.11 - Reserved PINT PIE69_RESERVED_INT; // 5.12 - Reserved PINT SD1DR1_INT; // 5.13 - SD1DR1 Interrupt PINT SD1DR2_INT; // 5.14 - SD1DR2 Interrupt PINT SD1DR3_INT; // 5.15 - SD1DR3 Interrupt PINT SD1DR4_INT; // 5.16 - SD1DR4 Interrupt PINT PIE70_RESERVED_INT; // 6.9 - Reserved PINT PIE71_RESERVED_INT; // 6.10 - Reserved PINT PIE72_RESERVED_INT; // 6.11 - Reserved PINT PIE73_RESERVED_INT; // 6.12 - Reserved PINT PIE74_RESERVED_INT; // 6.13 - Reserved PINT PIE75_RESERVED_INT; // 6.14 - Reserved PINT PIE76_RESERVED_INT; // 6.15 - Reserved PINT PIE77_RESERVED_INT; // 6.16 - Reserved PINT PIE78_RESERVED_INT; // 7.9 - Reserved PINT PIE79_RESERVED_INT; // 7.10 - Reserved PINT PIE80_RESERVED_INT; // 7.11 - Reserved PINT PIE81_RESERVED_INT; // 7.12 - Reserved PINT PIE82_RESERVED_INT; // 7.13 - Reserved PINT PIE83_RESERVED_INT; // 7.14 - Reserved PINT CLA1PROMCRC_INT; // 7.15 - CLA1PROMCRC Interrupt PINT PIE84_RESERVED_INT; // 7.16 - Reserved PINT LINA_0_INT; // 8.9 - LINA Interrupt0 PINT LINA_1_INT; // 8.10 - LINA Interrupt1 PINT PIE85_RESERVED_INT; // 8.11 - Reserved PINT PIE86_RESERVED_INT; // 8.12 - Reserved PINT PMBUSA_INT; // 8.13 - PMBUSA Interrupt PINT PIE87_RESERVED_INT; // 8.14 - Reserved PINT PIE88_RESERVED_INT; // 8.15 - Reserved PINT PIE89_RESERVED_INT; // 8.16 - Reserved PINT PIE90_RESERVED_INT; // 9.9 - Reserved PINT PIE91_RESERVED_INT; // 9.10 - Reserved PINT PIE92_RESERVED_INT; // 9.11 - Reserved PINT PIE93_RESERVED_INT; // 9.12 - Reserved PINT PIE94_RESERVED_INT; // 9.13 - Reserved PINT PIE95_RESERVED_INT; // 9.14 - Reserved PINT PIE96_RESERVED_INT; // 9.15 - Reserved PINT PIE97_RESERVED_INT; // 9.16 - Reserved PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 PINT PIE98_RESERVED_INT; // 10.13 - Reserved PINT PIE99_RESERVED_INT; // 10.14 - Reserved PINT PIE100_RESERVED_INT; // 10.15 - Reserved PINT PIE101_RESERVED_INT; // 10.16 - Reserved PINT PIE102_RESERVED_INT; // 11.9 - Reserved PINT PIE103_RESERVED_INT; // 11.10 - Reserved PINT PIE104_RESERVED_INT; // 11.11 - Reserved PINT PIE105_RESERVED_INT; // 11.12 - Reserved PINT PIE106_RESERVED_INT; // 11.13 - Reserved PINT PIE107_RESERVED_INT; // 11.14 - Reserved PINT PIE108_RESERVED_INT; // 11.15 - Reserved PINT PIE109_RESERVED_INT; // 11.16 - Reserved PINT PIE110_RESERVED_INT; // 12.9 - Reserved PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt PINT PIE111_RESERVED_INT; // 12.14 - Reserved PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt }; //--------------------------------------------------------------------------- // PieVect External References & Function Declarations: // extern volatile struct PIE_VECT_TABLE PieVectTable; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_pmbus.h // // TITLE: PMBUS Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PMBUS Individual Register Bit Definitions: struct PMBMC_BITS { // bits description Uint16 RW:1; // 0 RnW bit of the Message Uint16 SLAVE_ADDR:7; // 7:1 Slave Address Uint16 BYTE_COUNT:8; // 15:8 Number of Bytes Transmitted Uint16 CMD_ENA:1; // 16 Master Command Code Enable Uint16 EXT_CMD:1; // 17 Master Extended Command Code Enable Uint16 PEC_ENA:1; // 18 Master PEC Processing Enable Uint16 GRP_CMD:1; // 19 Master Group Command Message Enable Uint16 PRC_CALL:1; // 20 Master Process Call Message Enable Uint16 rsvd1:11; // 31:21 Reserved }; union PMBMC_REG { Uint32 all; struct PMBMC_BITS bit; }; struct PMBACK_BITS { // bits description Uint16 ACK:1; // 0 Allows firmware to ack/nack received data Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBACK_REG { Uint32 all; struct PMBACK_BITS bit; }; struct PMBSTS_BITS { // bits description Uint16 RD_BYTE_COUNT:3; // 2:0 Number of Data Bytes available in Receive Data Register Uint16 DATA_READY:1; // 3 Data Ready Flag Uint16 DATA_REQUEST:1; // 4 Data Request Flag Uint16 EOM:1; // 5 End of Message Indicator Uint16 NACK:1; // 6 Not Acknowledge Flag Status Uint16 PEC_VALID:1; // 7 PEC Valid Indicator Uint16 CLK_LOW_TIMEOUT:1; // 8 Clock Low Timeout Status Uint16 CLK_HIGH_DETECTED:1; // 9 Clock High Detection Status Uint16 SLAVE_ADDR_READY:1; // 10 Slave Address Ready Uint16 RPT_START:1; // 11 Repeated Start Flag Uint16 UNIT_BUSY:1; // 12 PMBus Busy Indicator Uint16 BUS_FREE:1; // 13 PMBus Free Indicator Uint16 LOST_ARB:1; // 14 Lost Arbitration Flag Uint16 MASTER:1; // 15 Master Indicator Uint16 ALERT_EDGE:1; // 16 Alert Edge Detection Status Uint16 CONTROL_EDGE:1; // 17 Control Edge Detection Status Uint16 ALERT_RAW:1; // 18 Alert Pin Real Time Status Uint16 CONTROL_RAW:1; // 19 Control Pin Real Time Status Uint16 SDA_RAW:1; // 20 PMBus Data Pin Real Time Status Uint16 SCL_RAW:1; // 21 PMBus Clock Pin Real Time Status Uint16 rsvd1:10; // 31:22 Reserved }; union PMBSTS_REG { Uint32 all; struct PMBSTS_BITS bit; }; struct PMBINTM_BITS { // bits description Uint16 BUS_FREE:1; // 0 Bus Free Interrupt Mask Uint16 BUS_LOW_TIMEOUT:1; // 1 Clock Low Timeout Interrupt Mask Uint16 DATA_READY:1; // 2 Data Ready Interrupt Mask Uint16 DATA_REQUEST:1; // 3 Data Request Interrupt Mask Uint16 SLAVE_ADDR_READY:1; // 4 Slave Address Ready Interrupt Mask Uint16 EOM:1; // 5 End of Message Interrupt Mask Uint16 ALERT:1; // 6 Alert Detection Interrupt Mask Uint16 CONTROL:1; // 7 Control Detection Interrupt Mask Uint16 LOST_ARB:1; // 8 Lost Arbitration Interrupt Mask Uint16 CLK_HIGH_DETECT:1; // 9 Clock High Detection Interrupt Mask Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBINTM_REG { Uint32 all; struct PMBINTM_BITS bit; }; struct PMBSC_BITS { // bits description Uint16 SLAVE_ADDR:7; // 6:0 Configures the current device address of the slave. Uint16 MAN_SLAVE_ACK:1; // 7 Manual Slave Address Acknowledgement Mode Uint16 SLAVE_MASK:7; // 14:8 Slave address mask Uint16 PEC_ENA:1; // 15 PEC Processing Enable Uint16 TX_COUNT:3; // 18:16 Number of valid bytes in Transmit Data Register Uint16 TX_PEC:1; // 19 send a PEC byte at end of message Uint16 MAN_CMD:1; // 20 Manual Command Acknowledgement Mode Uint16 RX_BYTE_ACK_CNT:2; // 22:21 Number of data bytes to automatically acknowledge Uint16 rsvd1:9; // 31:23 Reserved }; union PMBSC_REG { Uint32 all; struct PMBSC_BITS bit; }; struct PMBHSA_BITS { // bits description Uint16 SLAVE_RW:1; // 0 Stored R/W bit Uint16 SLAVE_ADDR:7; // 7:1 Stored device address Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBHSA_REG { Uint32 all; struct PMBHSA_BITS bit; }; struct PMBCTRL_BITS { // bits description Uint16 RESET:1; // 0 PMBus Interface Synchronous Reset Uint16 ALERT_EN:1; // 1 Slave Alert Enable Uint16 BUS_LO_INT_EDGE:1; // 2 Clock Low Timeout Interrupt Edge Select Uint16 FAST_MODE:1; // 3 Fast Mode Enable Uint16 FAST_MODE_PLUS:1; // 4 Fast Mode Plus Enable Uint16 CNTL_INT_EDGE:1; // 5 Control Interrupt Edge Select Uint16 ALERT_MODE:1; // 6 Configures mode of Alert pin Uint16 ALERT_VALUE:1; // 7 Configures output value of Alert pin in GPIO Mode Uint16 ALERT_DIR:1; // 8 Configures direction of Alert pin in GPIO mode Uint16 CNTL_MODE:1; // 9 Configures mode of Control pin Uint16 CNTL_VALUE:1; // 10 Configures output value of Control pin in GPIO Mode Uint16 CNTL_DIR:1; // 11 Configures direction of Control pin in GPIO mode Uint16 SDA_MODE:1; // 12 Configures mode of PMBus Data pin Uint16 SDA_VALUE:1; // 13 Configures output value of PMBus data pin in GPIO Mode Uint16 SDA_DIR:1; // 14 Configures direction of PMBus data pin in GPIO mode Uint16 SCL_MODE:1; // 15 Configures mode of PMBus Clock pin Uint16 SCL_VALUE:1; // 16 Configures output value of PMBus clock pin in GPIO Mode Uint16 SCL_DIR:1; // 17 Configures direction of PMBus clock pin in GPIO mode Uint16 IBIAS_A_EN:1; // 18 PMBus Current Source A Control Uint16 IBIAS_B_EN:1; // 19 PMBus Current Source B Control Uint16 CLK_LO_DIS:1; // 20 Clock Low Timeout Disable Uint16 SLAVE_EN:1; // 21 PMBus Slave Enable Uint16 MASTER_EN:1; // 22 PMBus Master Enable Uint16 CLKDIV:5; // 27:23 PMBUS IP Clock Divide Value Uint16 rsvd1:3; // 30:28 Reserved Uint16 I2CMODE:1; // 31 Bit to enable I2C mode }; union PMBCTRL_REG { Uint32 all; struct PMBCTRL_BITS bit; }; struct PMBTIMCTL_BITS { // bits description Uint16 TIM_OVERRIDE:1; // 0 Overide the default settings of the timing parameters. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMCTL_REG { Uint32 all; struct PMBTIMCTL_BITS bit; }; struct PMBTIMCLK_BITS { // bits description Uint16 CLK_HIGH_LIMIT:8; // 7:0 Determines the PMBUS master clock high pulse width. Uint16 rsvd1:8; // 15:8 Reserved Uint16 CLK_FREQ:8; // 23:16 Determines the PMBUS master clock frequency. Uint16 rsvd2:8; // 31:24 Reserved }; union PMBTIMCLK_REG { Uint32 all; struct PMBTIMCLK_BITS bit; }; struct PMBTIMSTSETUP_BITS { // bits description Uint16 TSU_STA:8; // 7:0 Setup time, rise edge of PMBUS master clock to start edge. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMSTSETUP_REG { Uint32 all; struct PMBTIMSTSETUP_BITS bit; }; struct PMBTIMBIDLE_BITS { // bits description Uint16 BUSIDLE:10; // 9:0 Determines the Bus Idle Limit Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMBIDLE_REG { Uint32 all; struct PMBTIMBIDLE_BITS bit; }; struct PMBTIMLOWTIMOUT_BITS { // bits description Uint32 CLKLOWTIMOUT:20; // 19:0 Determines the clock low timeout value Uint16 rsvd1:12; // 31:20 Reserved }; union PMBTIMLOWTIMOUT_REG { Uint32 all; struct PMBTIMLOWTIMOUT_BITS bit; }; struct PMBTIMHIGHTIMOUT_BITS { // bits description Uint16 CLKHIGHTIMOUT:10; // 9:0 Determines the clock high timeout value Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMHIGHTIMOUT_REG { Uint32 all; struct PMBTIMHIGHTIMOUT_BITS bit; }; struct PMBUS_REGS { union PMBMC_REG PMBMC; // PMBUS Master Mode Control Register Uint32 PMBTXBUF; // PMBUS Transmit Buffer Uint32 PMBRXBUF; // PMBUS Receive buffer union PMBACK_REG PMBACK; // PMBUS Acknowledge Register union PMBSTS_REG PMBSTS; // PMBUS Status Register union PMBINTM_REG PMBINTM; // PMBUS Interrupt Mask Register union PMBSC_REG PMBSC; // PMBUS Slave Mode Configuration Register union PMBHSA_REG PMBHSA; // PMBUS Hold Slave Address Register union PMBCTRL_REG PMBCTRL; // PMBUS Control Register union PMBTIMCTL_REG PMBTIMCTL; // PMBUS Timing Control Register union PMBTIMCLK_REG PMBTIMCLK; // PMBUS Clock Timing Register union PMBTIMSTSETUP_REG PMBTIMSTSETUP; // PMBUS Start Setup Time Register union PMBTIMBIDLE_REG PMBTIMBIDLE; // PMBUS Bus Idle Time Register union PMBTIMLOWTIMOUT_REG PMBTIMLOWTIMOUT; // PMBUS Clock Low Timeout Value Register union PMBTIMHIGHTIMOUT_REG PMBTIMHIGHTIMOUT; // PMBUS Clock High Timeout Value Register Uint16 rsvd1[2]; // Reserved }; //--------------------------------------------------------------------------- // PMBUS External References & Function Declarations: // extern volatile struct PMBUS_REGS PmbusaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_sci.h // // TITLE: SCI Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SCI Individual Register Bit Definitions: struct SCICCR_BITS { // bits description Uint16 SCICHAR:3; // 2:0 Character length control Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control Uint16 LOOPBKENA:1; // 4 Loop Back enable Uint16 PARITYENA:1; // 5 Parity enable Uint16 PARITY:1; // 6 Even or Odd Parity Uint16 STOPBITS:1; // 7 Number of Stop Bits Uint16 rsvd1:8; // 15:8 Reserved }; union SCICCR_REG { Uint16 all; struct SCICCR_BITS bit; }; struct SCICTL1_BITS { // bits description Uint16 RXENA:1; // 0 SCI receiver enable Uint16 TXENA:1; // 1 SCI transmitter enable Uint16 SLEEP:1; // 2 SCI sleep Uint16 TXWAKE:1; // 3 Transmitter wakeup method Uint16 rsvd1:1; // 4 Reserved Uint16 SWRESET:1; // 5 Software reset Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable Uint16 rsvd2:9; // 15:7 Reserved }; union SCICTL1_REG { Uint16 all; struct SCICTL1_BITS bit; }; struct SCIHBAUD_BITS { // bits description Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD Uint16 rsvd1:8; // 15:8 Reserved }; union SCIHBAUD_REG { Uint16 all; struct SCIHBAUD_BITS bit; }; struct SCILBAUD_BITS { // bits description Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD Uint16 rsvd1:8; // 15:8 Reserved }; union SCILBAUD_REG { Uint16 all; struct SCILBAUD_BITS bit; }; struct SCICTL2_BITS { // bits description Uint16 TXINTENA:1; // 0 Transmit __interrupt enable Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable Uint16 rsvd1:4; // 5:2 Reserved Uint16 TXEMPTY:1; // 6 Transmitter empty flag Uint16 TXRDY:1; // 7 Transmitter ready flag Uint16 rsvd2:8; // 15:8 Reserved }; union SCICTL2_REG { Uint16 all; struct SCICTL2_BITS bit; }; struct SCIRXST_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag Uint16 PE:1; // 2 Parity error flag Uint16 OE:1; // 3 Overrun error flag Uint16 FE:1; // 4 Framing error flag Uint16 BRKDT:1; // 5 Break-detect flag Uint16 RXRDY:1; // 6 Receiver ready flag Uint16 RXERROR:1; // 7 Receiver error flag Uint16 rsvd2:8; // 15:8 Reserved }; union SCIRXST_REG { Uint16 all; struct SCIRXST_BITS bit; }; struct SCIRXEMU_BITS { // bits description Uint16 ERXDT:8; // 7:0 Receive emulation buffer data Uint16 rsvd1:8; // 15:8 Reserved }; union SCIRXEMU_REG { Uint16 all; struct SCIRXEMU_BITS bit; }; struct SCIRXBUF_BITS { // bits description Uint16 SAR:8; // 7:0 Receive Character bits Uint16 rsvd1:6; // 13:8 Reserved Uint16 SCIFFPE:1; // 14 Receiver error flag Uint16 SCIFFFE:1; // 15 Receiver error flag }; union SCIRXBUF_REG { Uint16 all; struct SCIRXBUF_BITS bit; }; struct SCITXBUF_BITS { // bits description Uint16 TXDT:8; // 7:0 Transmit data buffer Uint16 rsvd1:8; // 15:8 Reserved }; union SCITXBUF_REG { Uint16 all; struct SCITXBUF_BITS bit; }; struct SCIFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 Interrupt level Uint16 TXFFIENA:1; // 5 Interrupt enable Uint16 TXFFINTCLR:1; // 6 Clear INT flag Uint16 TXFFINT:1; // 7 INT flag Uint16 TXFFST:5; // 12:8 FIFO status Uint16 TXFIFORESET:1; // 13 FIFO reset Uint16 SCIFFENA:1; // 14 Enhancement enable Uint16 SCIRST:1; // 15 SCI reset rx/tx channels }; union SCIFFTX_REG { Uint16 all; struct SCIFFTX_BITS bit; }; struct SCIFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 Interrupt level Uint16 RXFFIENA:1; // 5 Interrupt enable Uint16 RXFFINTCLR:1; // 6 Clear INT flag Uint16 RXFFINT:1; // 7 INT flag Uint16 RXFFST:5; // 12:8 FIFO status Uint16 RXFIFORESET:1; // 13 FIFO reset Uint16 RXFFOVRCLR:1; // 14 Clear overflow Uint16 RXFFOVF:1; // 15 FIFO overflow }; union SCIFFRX_REG { Uint16 all; struct SCIFFRX_BITS bit; }; struct SCIFFCT_BITS { // bits description Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay Uint16 rsvd1:5; // 12:8 Reserved Uint16 CDC:1; // 13 Auto baud mode enable Uint16 ABDCLR:1; // 14 Auto baud clear Uint16 ABD:1; // 15 Auto baud detect }; union SCIFFCT_REG { Uint16 all; struct SCIFFCT_BITS bit; }; struct SCIPRI_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 FREESOFT:2; // 4:3 Emulation modes Uint16 rsvd2:3; // 7:5 Reserved Uint16 rsvd3:8; // 15:8 Reserved }; union SCIPRI_REG { Uint16 all; struct SCIPRI_BITS bit; }; struct SCI_REGS { union SCICCR_REG SCICCR; // Communications control register union SCICTL1_REG SCICTL1; // Control register 1 union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register union SCILBAUD_REG SCILBAUD; // Baud rate (low) register union SCICTL2_REG SCICTL2; // Control register 2 union SCIRXST_REG SCIRXST; // Recieve status register union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer Uint16 rsvd1; // Reserved union SCITXBUF_REG SCITXBUF; // Transmit data buffer union SCIFFTX_REG SCIFFTX; // FIFO transmit register union SCIFFRX_REG SCIFFRX; // FIFO recieve register union SCIFFCT_REG SCIFFCT; // FIFO control register Uint16 rsvd2[2]; // Reserved union SCIPRI_REG SCIPRI; // SCI Priority control }; //--------------------------------------------------------------------------- // SCI External References & Function Declarations: // extern volatile struct SCI_REGS SciaRegs; extern volatile struct SCI_REGS ScibRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_sdfm.h // // TITLE: SDFM Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SDFM Individual Register Bit Definitions: struct SDIFLG_BITS { // bits description Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 Uint16 SDFFOVF1:1; // 16 FIFO Overflow Flag for Ch1. Uint16 SDFFOVF2:1; // 17 FIFO Overflow Flag for Ch2 Uint16 SDFFOVF3:1; // 18 FIFO Overflow Flag for Ch3 Uint16 SDFFOVF4:1; // 19 FIFO Overflow Flag for Ch4 Uint16 SDFFINT1:1; // 20 SDFIFO interrupt for Ch1 Uint16 SDFFINT2:1; // 21 SDFIFO interrupt for Ch2 Uint16 SDFFINT3:1; // 22 SDFIFO interrupt for Ch3 Uint16 SDFFINT4:1; // 23 SDFIFO interrupt for Ch4 Uint16 rsvd1:7; // 30:24 Reserved Uint16 MIF:1; // 31 Master Interrupt Flag }; union SDIFLG_REG { Uint32 all; struct SDIFLG_BITS bit; }; struct SDIFLGCLR_BITS { // bits description Uint16 IFH1:1; // 0 High-level Interrupt flag for Ch1 Uint16 IFL1:1; // 1 Low-level Interrupt flag for Ch1 Uint16 IFH2:1; // 2 High-level Interrupt flag for Ch2 Uint16 IFL2:1; // 3 Low-level Interrupt flag for Ch2 Uint16 IFH3:1; // 4 High-level Interrupt flag for Ch3 Uint16 IFL3:1; // 5 Low-level Interrupt flag for Ch3 Uint16 IFH4:1; // 6 High-level Interrupt flag for Ch4 Uint16 IFL4:1; // 7 Low-level Interrupt flag for Ch4 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 Uint16 SDFFOVF1:1; // 16 SDFIFO overflow clear Ch1 Uint16 SDFFOVF2:1; // 17 SDFIFO overflow clear Ch2 Uint16 SDFFOVF3:1; // 18 SDFIFO overflow clear Ch3 Uint16 SDFFOVF4:1; // 19 SDFIFO overflow clear Ch4 Uint16 SDFFINT1:1; // 20 SDFIFO Interrupt flag-clear bit for Ch1 Uint16 SDFFINT2:1; // 21 SDFIFO Interrupt flag-clear bit for Ch2 Uint16 SDFFINT3:1; // 22 SDFIFO Interrupt flag-clear bit for Ch3 Uint16 SDFFINT4:1; // 23 SDFIFO Interrupt flag-clear bit for Ch4 Uint16 rsvd1:7; // 30:24 Reserved Uint16 MIF:1; // 31 Master Interrupt Flag }; union SDIFLGCLR_REG { Uint32 all; struct SDIFLGCLR_BITS bit; }; struct SDCTL_BITS { // bits description Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 Uint16 rsvd1:9; // 12:4 Reserved Uint16 MIE:1; // 13 Master SDy_ERR Interrupt enable Uint16 rsvd2:1; // 14 Reserved Uint16 rsvd3:1; // 15 Reserved }; union SDCTL_REG { Uint16 all; struct SDCTL_BITS bit; }; struct SDMFILEN_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 rsvd2:3; // 6:4 Reserved Uint16 rsvd3:2; // 8:7 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:1; // 10 Reserved Uint16 MFE:1; // 11 Master Filter Enable. Uint16 rsvd6:1; // 12 Reserved Uint16 rsvd7:3; // 15:13 Reserved }; union SDMFILEN_REG { Uint16 all; struct SDMFILEN_BITS bit; }; struct SDSTATUS_BITS { // bits description Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 Uint16 rsvd1:4; // 7:4 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:1; // 10 Reserved Uint16 rsvd5:1; // 11 Reserved Uint16 rsvd6:1; // 12 Reserved Uint16 rsvd7:1; // 13 Reserved Uint16 rsvd8:1; // 14 Reserved Uint16 rsvd9:1; // 15 Reserved }; union SDSTATUS_REG { Uint16 all; struct SDSTATUS_BITS bit; }; struct SDCTLPARM1_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM1_REG { Uint16 all; struct SDCTLPARM1_BITS bit; }; struct SDDFPARM1_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM1_REG { Uint16 all; struct SDDFPARM1_BITS bit; }; struct SDDPARM1_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM1_REG { Uint16 all; struct SDDPARM1_BITS bit; }; struct SDCMPH1_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH1_REG { Uint16 all; struct SDCMPH1_BITS bit; }; struct SDCMPL1_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL1_REG { Uint16 all; struct SDCMPL1_BITS bit; }; struct SDCPARM1_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 IEH:1; // 5 High-level Interrupt enable. Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 rsvd1:2; // 12:11 Reserved Uint16 CEN:1; // 13 Comparator Enable Uint16 rsvd2:2; // 15:14 Reserved }; union SDCPARM1_REG { Uint16 all; struct SDCPARM1_BITS bit; }; struct SDDATA1_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA1_REG { Uint32 all; struct SDDATA1_BITS bit; }; struct SDDATFIFO1_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO1_REG { Uint32 all; struct SDDATFIFO1_BITS bit; }; struct SDCMPHZ1_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPHZ1_REG { Uint16 all; struct SDCMPHZ1_BITS bit; }; struct SDFIFOCTL1_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL1_REG { Uint16 all; struct SDFIFOCTL1_BITS bit; }; struct SDSYNC1_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC1_REG { Uint16 all; struct SDSYNC1_BITS bit; }; struct SDCTLPARM2_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM2_REG { Uint16 all; struct SDCTLPARM2_BITS bit; }; struct SDDFPARM2_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM2_REG { Uint16 all; struct SDDFPARM2_BITS bit; }; struct SDDPARM2_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM2_REG { Uint16 all; struct SDDPARM2_BITS bit; }; struct SDCMPH2_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH2_REG { Uint16 all; struct SDCMPH2_BITS bit; }; struct SDCMPL2_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL2_REG { Uint16 all; struct SDCMPL2_BITS bit; }; struct SDCPARM2_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 IEH:1; // 5 High-level Interrupt enable. Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 rsvd1:2; // 12:11 Reserved Uint16 CEN:1; // 13 Comparator Enable Uint16 rsvd2:2; // 15:14 Reserved }; union SDCPARM2_REG { Uint16 all; struct SDCPARM2_BITS bit; }; struct SDDATA2_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA2_REG { Uint32 all; struct SDDATA2_BITS bit; }; struct SDDATFIFO2_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO2_REG { Uint32 all; struct SDDATFIFO2_BITS bit; }; struct SDCMPHZ2_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPHZ2_REG { Uint16 all; struct SDCMPHZ2_BITS bit; }; struct SDFIFOCTL2_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL2_REG { Uint16 all; struct SDFIFOCTL2_BITS bit; }; struct SDSYNC2_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC2_REG { Uint16 all; struct SDSYNC2_BITS bit; }; struct SDCTLPARM3_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM3_REG { Uint16 all; struct SDCTLPARM3_BITS bit; }; struct SDDFPARM3_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM3_REG { Uint16 all; struct SDDFPARM3_BITS bit; }; struct SDDPARM3_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM3_REG { Uint16 all; struct SDDPARM3_BITS bit; }; struct SDCMPH3_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH3_REG { Uint16 all; struct SDCMPH3_BITS bit; }; struct SDCMPL3_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL3_REG { Uint16 all; struct SDCMPL3_BITS bit; }; struct SDCPARM3_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 IEH:1; // 5 High-level Interrupt enable. Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 rsvd1:2; // 12:11 Reserved Uint16 CEN:1; // 13 Comparator Enable Uint16 rsvd2:2; // 15:14 Reserved }; union SDCPARM3_REG { Uint16 all; struct SDCPARM3_BITS bit; }; struct SDDATA3_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA3_REG { Uint32 all; struct SDDATA3_BITS bit; }; struct SDDATFIFO3_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO3_REG { Uint32 all; struct SDDATFIFO3_BITS bit; }; struct SDCMPHZ3_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPHZ3_REG { Uint16 all; struct SDCMPHZ3_BITS bit; }; struct SDFIFOCTL3_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL3_REG { Uint16 all; struct SDFIFOCTL3_BITS bit; }; struct SDSYNC3_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC3_REG { Uint16 all; struct SDSYNC3_BITS bit; }; struct SDCTLPARM4_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCTLPARM4_REG { Uint16 all; struct SDCTLPARM4_BITS bit; }; struct SDDFPARM4_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM4_REG { Uint16 all; struct SDDFPARM4_BITS bit; }; struct SDDPARM4_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM4_REG { Uint16 all; struct SDDPARM4_BITS bit; }; struct SDCMPH4_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPH4_REG { Uint16 all; struct SDCMPH4_BITS bit; }; struct SDCMPL4_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPL4_REG { Uint16 all; struct SDCMPL4_BITS bit; }; struct SDCPARM4_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 IEH:1; // 5 High-level Interrupt enable. Uint16 IEL:1; // 6 Low-level interrupt enable Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 rsvd1:2; // 12:11 Reserved Uint16 CEN:1; // 13 Comparator Enable Uint16 rsvd2:2; // 15:14 Reserved }; union SDCPARM4_REG { Uint16 all; struct SDCPARM4_BITS bit; }; struct SDDATA4_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA4_REG { Uint32 all; struct SDDATA4_BITS bit; }; struct SDDATFIFO4_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO4_REG { Uint32 all; struct SDDATFIFO4_BITS bit; }; struct SDCMPHZ4_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDCMPHZ4_REG { Uint16 all; struct SDCMPHZ4_BITS bit; }; struct SDFIFOCTL4_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL4_REG { Uint16 all; struct SDFIFOCTL4_BITS bit; }; struct SDSYNC4_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC4_REG { Uint16 all; struct SDSYNC4_BITS bit; }; struct SDFM_REGS { union SDIFLG_REG SDIFLG; // SD Interrupt Flag Register union SDIFLGCLR_REG SDIFLGCLR; // SD Interrupt Flag Clear Register union SDCTL_REG SDCTL; // SD Control Register Uint16 rsvd1; // Reserved union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable union SDSTATUS_REG SDSTATUS; // SD Status Register Uint16 rsvd2[8]; // Reserved union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 union SDDPARM1_REG SDDPARM1; // Data Parameter Register for Ch1 union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 union SDCPARM1_REG SDCPARM1; // Comparator Filter Parameter Register for Ch1 union SDDATA1_REG SDDATA1; // Data Filter Data Register (16 or 32bit) for Ch1 union SDDATFIFO1_REG SDDATFIFO1; // Filter Data FIFO Output(32b) for Ch1 Uint16 SDCDATA1; // Comparator Filter Data Register (16b) for Ch1 Uint16 rsvd3; // Reserved union SDCMPHZ1_REG SDCMPHZ1; // High-level (Z) Threshold Register for Ch1 union SDFIFOCTL1_REG SDFIFOCTL1; // FIFO Control Register for Ch1 union SDSYNC1_REG SDSYNC1; // SD Filter Sync control for Ch1 Uint16 rsvd4; // Reserved union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 union SDDPARM2_REG SDDPARM2; // Data Parameter Register for Ch2 union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 union SDCPARM2_REG SDCPARM2; // Comparator Filter Parameter Register for Ch2 union SDDATA2_REG SDDATA2; // Data Filter Data Register (16 or 32bit) for Ch2 union SDDATFIFO2_REG SDDATFIFO2; // Filter Data FIFO Output(32b) for Ch2 Uint16 SDCDATA2; // Comparator Filter Data Register (16b) for Ch2 Uint16 rsvd5; // Reserved union SDCMPHZ2_REG SDCMPHZ2; // High-level (Z) Threshold Register for Ch2 union SDFIFOCTL2_REG SDFIFOCTL2; // FIFO Control Register for Ch2 union SDSYNC2_REG SDSYNC2; // SD Filter Sync control for Ch2 Uint16 rsvd6; // Reserved union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 union SDDPARM3_REG SDDPARM3; // Data Parameter Register for Ch3 union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 union SDCPARM3_REG SDCPARM3; // Comparator Filter Parameter Register for Ch3 union SDDATA3_REG SDDATA3; // Data Filter Data Register (16 or 32bit) for Ch3 union SDDATFIFO3_REG SDDATFIFO3; // Filter Data FIFO Output(32b) for Ch3 Uint16 SDCDATA3; // Comparator Filter Data Register (16b) for Ch3 Uint16 rsvd7; // Reserved union SDCMPHZ3_REG SDCMPHZ3; // High-level (Z) Threshold Register for Ch3 union SDFIFOCTL3_REG SDFIFOCTL3; // FIFO Control Register for Ch3 union SDSYNC3_REG SDSYNC3; // SD Filter Sync control for Ch3 Uint16 rsvd8; // Reserved union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 union SDDPARM4_REG SDDPARM4; // Data Parameter Register for Ch4 union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 union SDCPARM4_REG SDCPARM4; // Comparator Filter Parameter Register for Ch4 union SDDATA4_REG SDDATA4; // Data Filter Data Register (16 or 32bit) for Ch4 union SDDATFIFO4_REG SDDATFIFO4; // Filter Data FIFO Output(32b) for Ch4 Uint16 SDCDATA4; // Comparator Filter Data Register (16b) for Ch4 Uint16 rsvd9; // Reserved union SDCMPHZ4_REG SDCMPHZ4; // High-level (Z) Threshold Register for Ch4 union SDFIFOCTL4_REG SDFIFOCTL4; // FIFO Control Register for Ch4 union SDSYNC4_REG SDSYNC4; // SD Filter Sync control for Ch4 Uint16 rsvd10[33]; // Reserved }; //--------------------------------------------------------------------------- // SDFM External References & Function Declarations: // extern volatile struct SDFM_REGS Sdfm1Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_spi.h // // TITLE: SPI Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SPI Individual Register Bit Definitions: struct SPICCR_BITS { // bits description Uint16 SPICHAR:4; // 3:0 Character Length Control Uint16 SPILBK:1; // 4 SPI Loopback Uint16 HS_MODE:1; // 5 High Speed mode control Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity Uint16 SPISWRESET:1; // 7 SPI Software Reset Uint16 rsvd1:8; // 15:8 Reserved }; union SPICCR_REG { Uint16 all; struct SPICCR_BITS bit; }; struct SPICTL_BITS { // bits description Uint16 SPIINTENA:1; // 0 SPI Interupt Enable Uint16 TALK:1; // 1 Master/Slave Transmit Enable Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control Uint16 CLK_PHASE:1; // 3 SPI Clock Phase Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable Uint16 rsvd1:11; // 15:5 Reserved }; union SPICTL_REG { Uint16 all; struct SPICTL_BITS bit; }; struct SPISTS_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag Uint16 rsvd2:8; // 15:8 Reserved }; union SPISTS_REG { Uint16 all; struct SPISTS_BITS bit; }; struct SPIBRR_BITS { // bits description Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control Uint16 rsvd1:9; // 15:7 Reserved }; union SPIBRR_REG { Uint16 all; struct SPIBRR_BITS bit; }; struct SPIFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag Uint16 TXFFST:5; // 12:8 Transmit FIFO Status Uint16 TXFIFO:1; // 13 TXFIFO Reset Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable Uint16 SPIRST:1; // 15 SPI Reset }; union SPIFFTX_REG { Uint16 all; struct SPIFFTX_BITS bit; }; struct SPIFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag Uint16 RXFFST:5; // 12:8 Receive FIFO Status Uint16 RXFIFORESET:1; // 13 RXFIFO Reset Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag }; union SPIFFRX_REG { Uint16 all; struct SPIFFRX_BITS bit; }; struct SPIFFCT_BITS { // bits description Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits Uint16 rsvd1:8; // 15:8 Reserved }; union SPIFFCT_REG { Uint16 all; struct SPIFFCT_BITS bit; }; struct SPIPRI_BITS { // bits description Uint16 TRIWIRE:1; // 0 3-wire mode select bit Uint16 STEINV:1; // 1 SPISTE inversion bit Uint16 rsvd1:2; // 3:2 Reserved Uint16 FREE:1; // 4 Free emulation mode Uint16 SOFT:1; // 5 Soft emulation mode Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:9; // 15:7 Reserved }; union SPIPRI_REG { Uint16 all; struct SPIPRI_BITS bit; }; struct SPI_REGS { union SPICCR_REG SPICCR; // SPI Configuration Control Register union SPICTL_REG SPICTL; // SPI Operation Control Register union SPISTS_REG SPISTS; // SPI Status Register Uint16 rsvd1; // Reserved union SPIBRR_REG SPIBRR; // SPI Baud Rate Register Uint16 rsvd2; // Reserved Uint16 SPIRXEMU; // SPI Emulation Buffer Register Uint16 SPIRXBUF; // SPI Serial Input Buffer Register Uint16 SPITXBUF; // SPI Serial Output Buffer Register Uint16 SPIDAT; // SPI Serial Data Register union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register Uint16 rsvd3[2]; // Reserved union SPIPRI_REG SPIPRI; // SPI Priority Control Register }; //--------------------------------------------------------------------------- // SPI External References & Function Declarations: // extern volatile struct SPI_REGS SpiaRegs; extern volatile struct SPI_REGS SpibRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_sysctrl.h // // TITLE: SYSCTRL Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SYSCTRL Individual Register Bit Definitions: struct PARTIDL_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 rsvd2:2; // 4:3 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 QUAL:2; // 7:6 Qualification Status Uint16 PIN_COUNT:3; // 10:8 Device Pin Count Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 INSTASPIN:2; // 14:13 Instaspin feature set Uint16 rsvd6:1; // 15 Reserved Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB Uint16 rsvd7:4; // 27:24 Reserved Uint16 rsvd8:4; // 31:28 Reserved }; union PARTIDL_REG { Uint32 all; struct PARTIDL_BITS bit; }; struct PARTIDH_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 rsvd2:4; // 7:4 Reserved Uint16 FAMILY:8; // 15:8 Device family Uint16 PARTNO:8; // 23:16 Device part number Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID }; union PARTIDH_REG { Uint32 all; struct PARTIDH_BITS bit; }; struct REVID_BITS { // bits description Uint16 REVID:16; // 15:0 Device Revision ID. This is specific to the Device Uint16 rsvd1:16; // 31:16 Reserved }; union REVID_REG { Uint32 all; struct REVID_BITS bit; }; struct FUSEERR_BITS { // bits description Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status Uint16 ERR:1; // 5 Efuse Self Test Error Status Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FUSEERR_REG { Uint32 all; struct FUSEERR_BITS bit; }; struct SOFTPRES0_BITS { // bits description Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:12; // 15:4 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union SOFTPRES0_REG { Uint32 all; struct SOFTPRES0_BITS bit; }; struct SOFTPRES2_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 software reset bit Uint16 EPWM2:1; // 1 EPWM2 software reset bit Uint16 EPWM3:1; // 2 EPWM3 software reset bit Uint16 EPWM4:1; // 3 EPWM4 software reset bit Uint16 EPWM5:1; // 4 EPWM5 software reset bit Uint16 EPWM6:1; // 5 EPWM6 software reset bit Uint16 EPWM7:1; // 6 EPWM7 software reset bit Uint16 EPWM8:1; // 7 EPWM8 software reset bit Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 rsvd6:1; // 13 Reserved Uint16 rsvd7:1; // 14 Reserved Uint16 rsvd8:1; // 15 Reserved Uint16 rsvd9:16; // 31:16 Reserved }; union SOFTPRES2_REG { Uint32 all; struct SOFTPRES2_BITS bit; }; struct SOFTPRES3_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 software reset bit Uint16 ECAP2:1; // 1 ECAP2 software reset bit Uint16 ECAP3:1; // 2 ECAP3 software reset bit Uint16 ECAP4:1; // 3 ECAP4 software reset bit Uint16 ECAP5:1; // 4 ECAP5 software reset bit Uint16 ECAP6:1; // 5 ECAP6 software reset bit Uint16 ECAP7:1; // 6 ECAP7 software reset bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES3_REG { Uint32 all; struct SOFTPRES3_BITS bit; }; struct SOFTPRES4_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 software reset bit Uint16 EQEP2:1; // 1 EQEP2 software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union SOFTPRES4_REG { Uint32 all; struct SOFTPRES4_BITS bit; }; struct SOFTPRES6_BITS { // bits description Uint16 SD1:1; // 0 SD1 software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:1; // 6 Reserved Uint16 rsvd7:1; // 7 Reserved Uint16 rsvd8:8; // 15:8 Reserved Uint16 rsvd9:16; // 31:16 Reserved }; union SOFTPRES6_REG { Uint32 all; struct SOFTPRES6_BITS bit; }; struct SOFTPRES7_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A software reset bit Uint16 SCI_B:1; // 1 SCI_B software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union SOFTPRES7_REG { Uint32 all; struct SOFTPRES7_BITS bit; }; struct SOFTPRES8_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A software reset bit Uint16 SPI_B:1; // 1 SPI_B software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:1; // 16 Reserved Uint16 rsvd5:1; // 17 Reserved Uint16 rsvd6:14; // 31:18 Reserved }; union SOFTPRES8_REG { Uint32 all; struct SOFTPRES8_BITS bit; }; struct SOFTPRES9_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES9_REG { Uint32 all; struct SOFTPRES9_BITS bit; }; struct SOFTPRES10_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A software reset bit Uint16 CAN_B:1; // 1 CAN_B software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union SOFTPRES10_REG { Uint32 all; struct SOFTPRES10_BITS bit; }; struct SOFTPRES13_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A software reset bit Uint16 ADC_B:1; // 1 ADC_B software reset bit Uint16 ADC_C:1; // 2 ADC_C software reset bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES13_REG { Uint32 all; struct SOFTPRES13_BITS bit; }; struct SOFTPRES14_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES14_REG { Uint32 all; struct SOFTPRES14_BITS bit; }; struct SOFTPRES15_BITS { // bits description Uint16 PGA1:1; // 0 PGA1 software reset bit Uint16 PGA2:1; // 1 PGA2 software reset bit Uint16 PGA3:1; // 2 PGA3 software reset bit Uint16 PGA4:1; // 3 PGA4 software reset bit Uint16 PGA5:1; // 4 PGA5 software reset bit Uint16 PGA6:1; // 5 PGA6 software reset bit Uint16 PGA7:1; // 6 PGA7 software reset bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES15_REG { Uint32 all; struct SOFTPRES15_BITS bit; }; struct SOFTPRES16_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit Uint16 rsvd6:1; // 18 Reserved Uint16 rsvd7:1; // 19 Reserved Uint16 rsvd8:12; // 31:20 Reserved }; union SOFTPRES16_REG { Uint32 all; struct SOFTPRES16_BITS bit; }; struct SOFTPRES19_BITS { // bits description Uint16 LIN_A:1; // 0 LIN_A software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:12; // 15:4 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union SOFTPRES19_REG { Uint32 all; struct SOFTPRES19_BITS bit; }; struct SOFTPRES20_BITS { // bits description Uint16 PMBUS_A:1; // 0 PMBUS_A software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES20_REG { Uint32 all; struct SOFTPRES20_BITS bit; }; struct TAP_STATUS_BITS { // bits description Uint16 TAP_STATE:16; // 15:0 Present TAP State Uint16 rsvd1:15; // 30:16 Reserved Uint16 DCON:1; // 31 Debugger Connect Indication }; union TAP_STATUS_REG { Uint32 all; struct TAP_STATUS_BITS bit; }; struct DEV_CFG_REGS { Uint16 rsvd1[8]; // Reserved union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number union REVID_REG REVID; // Device Revision Number Uint16 rsvd2[102]; // Reserved union FUSEERR_REG FUSEERR; // e-Fuse error Status register Uint16 rsvd3[12]; // Reserved union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register Uint16 rsvd4[2]; // Reserved union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register Uint16 rsvd5[2]; // Reserved union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register union SOFTPRES10_REG SOFTPRES10; // Peripheral Software Reset register Uint16 rsvd6[4]; // Reserved union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register union SOFTPRES15_REG SOFTPRES15; // Peripheral Software Reset register union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register Uint16 rsvd7[4]; // Reserved union SOFTPRES19_REG SOFTPRES19; // Peripheral Software Reset register union SOFTPRES20_REG SOFTPRES20; // Peripheral Software Reset register Uint16 rsvd8[132]; // Reserved union TAP_STATUS_REG TAP_STATUS; // Status of JTAG State machine & Debugger Connect Uint16 rsvd9[78]; // Reserved }; struct CLKCFGLOCK1_BITS { // bits description Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:1; // 8 Reserved Uint16 rsvd5:1; // 9 Reserved Uint16 rsvd6:1; // 10 Reserved Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register Uint16 rsvd7:1; // 12 Reserved Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register Uint16 rsvd8:1; // 14 Reserved Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register Uint16 XTALCR:1; // 16 Lock bit for XTALCR register Uint16 rsvd9:15; // 31:17 Reserved }; union CLKCFGLOCK1_REG { Uint32 all; struct CLKCFGLOCK1_BITS bit; }; struct CLKSRCCTL1_BITS { // bits description Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit Uint16 rsvd1:1; // 2 Reserved Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit Uint16 rsvd2:1; // 4 Reserved Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit Uint16 rsvd3:10; // 15:6 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CLKSRCCTL1_REG { Uint32 all; struct CLKSRCCTL1_BITS bit; }; struct CLKSRCCTL2_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit Uint16 rsvd2:2; // 7:6 Reserved Uint16 rsvd3:2; // 9:8 Reserved Uint16 rsvd4:6; // 15:10 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union CLKSRCCTL2_REG { Uint32 all; struct CLKSRCCTL2_BITS bit; }; struct CLKSRCCTL3_BITS { // bits description Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLKSRCCTL3_REG { Uint32 all; struct CLKSRCCTL3_BITS bit; }; struct SYSPLLCTL1_BITS { // bits description Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSPLLCTL1_REG { Uint32 all; struct SYSPLLCTL1_BITS bit; }; struct SYSPLLMULT_BITS { // bits description Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier Uint16 rsvd1:1; // 7 Reserved Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier Uint16 rsvd2:6; // 15:10 Reserved Uint16 ODIV:3; // 18:16 Output Clock Divider Uint16 rsvd3:5; // 23:19 Reserved Uint16 rsvd4:6; // 29:24 Reserved Uint16 rsvd5:2; // 31:30 Reserved }; union SYSPLLMULT_REG { Uint32 all; struct SYSPLLMULT_BITS bit; }; struct SYSPLLSTS_BITS { // bits description Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSPLLSTS_REG { Uint32 all; struct SYSPLLSTS_BITS bit; }; struct SYSCLKDIVSEL_BITS { // bits description Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSCLKDIVSEL_REG { Uint32 all; struct SYSCLKDIVSEL_BITS bit; }; struct XCLKOUTDIVSEL_BITS { // bits description Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union XCLKOUTDIVSEL_REG { Uint32 all; struct XCLKOUTDIVSEL_BITS bit; }; struct LOSPCP_BITS { // bits description Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LOSPCP_REG { Uint32 all; struct LOSPCP_BITS bit; }; struct MCDCR_BITS { // bits description Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCDCR_REG { Uint32 all; struct MCDCR_BITS bit; }; struct X1CNT_BITS { // bits description Uint16 X1CNT:10; // 9:0 X1 Counter Uint16 rsvd1:6; // 15:10 Reserved Uint16 CLR:1; // 16 X1 Counter Clear Uint16 rsvd2:15; // 31:17 Reserved }; union X1CNT_REG { Uint32 all; struct X1CNT_BITS bit; }; struct XTALCR_BITS { // bits description Uint16 OSCOFF:1; // 0 XTAL Oscillator powered-down Uint16 SE:1; // 1 XTAL Oscilator in Single-Ended mode Uint16 SWH:1; // 2 XTAL Oscilator Operation range Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union XTALCR_REG { Uint32 all; struct XTALCR_BITS bit; }; struct CLK_CFG_REGS { Uint16 rsvd1[2]; // Reserved union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers Uint16 rsvd2[4]; // Reserved union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 Uint16 rsvd3[4]; // Reserved union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register Uint16 rsvd4[10]; // Reserved union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register Uint16 rsvd5[4]; // Reserved union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register Uint16 rsvd6[2]; // Reserved union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar union MCDCR_REG MCDCR; // Missing Clock Detect Control Register union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock union XTALCR_REG XTALCR; // XTAL Control Register Uint16 rsvd7[2]; // Reserved }; struct CPUSYSLOCK1_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register Uint16 rsvd3:1; // 4 Reserved Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register Uint16 rsvd4:1; // 8 Reserved Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register Uint16 rsvd5:1; // 14 Reserved Uint16 rsvd6:1; // 15 Reserved Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register Uint16 rsvd7:1; // 20 Reserved Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register Uint16 PCLKCR17:1; // 24 Lock bit for PCLKCR17 Register Uint16 PCLKCR18:1; // 25 Lock bit for PCLKCR18 Register Uint16 PCLKCR19:1; // 26 Lock bit for PCLKCR19 Register Uint16 PCLKCR20:1; // 27 Lock bit for PCLKCR20 Register Uint16 PCLKCR21:1; // 28 Lock bit for PCLKCR21 Register Uint16 rsvd8:1; // 29 Reserved Uint16 rsvd9:1; // 30 Reserved Uint16 rsvd10:1; // 31 Reserved }; union CPUSYSLOCK1_REG { Uint32 all; struct CPUSYSLOCK1_BITS bit; }; struct PIEVERRADDR_BITS { // bits description Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address Uint16 rsvd1:10; // 31:22 Reserved }; union PIEVERRADDR_REG { Uint32 all; struct PIEVERRADDR_BITS bit; }; struct PCLKCR0_BITS { // bits description Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit Uint16 rsvd1:1; // 1 Reserved Uint16 DMA:1; // 2 DMA Clock Enable bit Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit Uint16 rsvd2:10; // 15:6 Reserved Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit Uint16 rsvd3:1; // 17 Reserved Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync Uint16 rsvd4:1; // 19 Reserved Uint16 rsvd5:12; // 31:20 Reserved }; union PCLKCR0_REG { Uint32 all; struct PCLKCR0_BITS bit; }; struct PCLKCR2_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 rsvd6:1; // 13 Reserved Uint16 rsvd7:1; // 14 Reserved Uint16 rsvd8:1; // 15 Reserved Uint16 rsvd9:16; // 31:16 Reserved }; union PCLKCR2_REG { Uint32 all; struct PCLKCR2_BITS bit; }; struct PCLKCR3_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit Uint16 ECAP7:1; // 6 ECAP7 Clock Enable bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR3_REG { Uint32 all; struct PCLKCR3_BITS bit; }; struct PCLKCR4_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PCLKCR4_REG { Uint32 all; struct PCLKCR4_BITS bit; }; struct PCLKCR6_BITS { // bits description Uint16 SD1:1; // 0 SD1 Clock Enable bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:1; // 6 Reserved Uint16 rsvd7:1; // 7 Reserved Uint16 rsvd8:8; // 15:8 Reserved Uint16 rsvd9:16; // 31:16 Reserved }; union PCLKCR6_REG { Uint32 all; struct PCLKCR6_BITS bit; }; struct PCLKCR7_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PCLKCR7_REG { Uint32 all; struct PCLKCR7_BITS bit; }; struct PCLKCR8_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:1; // 16 Reserved Uint16 rsvd5:1; // 17 Reserved Uint16 rsvd6:14; // 31:18 Reserved }; union PCLKCR8_REG { Uint32 all; struct PCLKCR8_BITS bit; }; struct PCLKCR9_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR9_REG { Uint32 all; struct PCLKCR9_BITS bit; }; struct PCLKCR10_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PCLKCR10_REG { Uint32 all; struct PCLKCR10_BITS bit; }; struct PCLKCR13_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR13_REG { Uint32 all; struct PCLKCR13_BITS bit; }; struct PCLKCR14_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR14_REG { Uint32 all; struct PCLKCR14_BITS bit; }; struct PCLKCR15_BITS { // bits description Uint16 PGA1:1; // 0 PGA1 Clock Enable bit Uint16 PGA2:1; // 1 PGA2 Clock Enable bit Uint16 PGA3:1; // 2 PGA3 Clock Enable bit Uint16 PGA4:1; // 3 PGA4 Clock Enable bit Uint16 PGA5:1; // 4 PGA5 Clock Enable bit Uint16 PGA6:1; // 5 PGA6 Clock Enable bit Uint16 PGA7:1; // 6 PGA7 Clock Enable bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR15_REG { Uint32 all; struct PCLKCR15_BITS bit; }; struct PCLKCR16_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit Uint16 rsvd6:1; // 18 Reserved Uint16 rsvd7:1; // 19 Reserved Uint16 rsvd8:12; // 31:20 Reserved }; union PCLKCR16_REG { Uint32 all; struct PCLKCR16_BITS bit; }; struct PCLKCR19_BITS { // bits description Uint16 LIN_A:1; // 0 LIN_A Clock Enable bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:12; // 15:4 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union PCLKCR19_REG { Uint32 all; struct PCLKCR19_BITS bit; }; struct PCLKCR20_BITS { // bits description Uint16 PMBUS_A:1; // 0 PMBUS_A Clock Enable bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR20_REG { Uint32 all; struct PCLKCR20_BITS bit; }; struct PCLKCR21_BITS { // bits description Uint16 DCC_0:1; // 0 DCC_0 Clock Enable Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR21_REG { Uint32 all; struct PCLKCR21_BITS bit; }; struct LPMCR_BITS { // bits description Uint16 LPM:2; // 1:0 Low Power Mode setting Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting Uint16 rsvd1:7; // 14:8 Reserved Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY Uint16 rsvd2:2; // 17:16 Reserved Uint16 rsvd3:13; // 30:18 Reserved Uint16 rsvd4:1; // 31 Reserved }; union LPMCR_REG { Uint32 all; struct LPMCR_BITS bit; }; struct GPIOLPMSEL0_BITS { // bits description Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup }; union GPIOLPMSEL0_REG { Uint32 all; struct GPIOLPMSEL0_BITS bit; }; struct GPIOLPMSEL1_BITS { // bits description Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup }; union GPIOLPMSEL1_REG { Uint32 all; struct GPIOLPMSEL1_BITS bit; }; struct TMR2CLKCTL_BITS { // bits description Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union TMR2CLKCTL_REG { Uint32 all; struct TMR2CLKCTL_BITS bit; }; struct RESCCLR_BITS { // bits description Uint16 POR:1; // 0 POR Reset Cause Indication Bit Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit Uint16 rsvd5:7; // 15:9 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union RESCCLR_REG { Uint32 all; struct RESCCLR_BITS bit; }; struct RESC_BITS { // bits description Uint16 POR:1; // 0 POR Reset Cause Indication Bit Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit Uint16 rsvd5:7; // 15:9 Reserved Uint16 rsvd6:14; // 29:16 Reserved Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status Uint16 DCON:1; // 31 Debugger conntion status to C28x }; union RESC_REG { Uint32 all; struct RESC_BITS bit; }; struct CPU_SYS_REGS { union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers Uint16 rsvd1[8]; // Reserved union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register Uint16 rsvd2[22]; // Reserved union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers Uint16 rsvd3[2]; // Reserved union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers Uint16 rsvd4[2]; // Reserved union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers Uint16 rsvd5[4]; // Reserved union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers union PCLKCR15_REG PCLKCR15; // Peripheral Clock Gating Registers union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers Uint16 rsvd6[4]; // Reserved union PCLKCR19_REG PCLKCR19; // Peripheral Clock Gating Registers union PCLKCR20_REG PCLKCR20; // Peripheral Clock Gating Registers union PCLKCR21_REG PCLKCR21; // Peripheral Clock Gating Registers Uint16 rsvd7[40]; // Reserved union LPMCR_REG LPMCR; // LPM Control Register union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register union RESCCLR_REG RESCCLR; // Reset Cause Clear Register union RESC_REG RESC; // Reset Cause register }; struct SCSR_BITS { // bits description Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit Uint16 WDENINT:1; // 1 WD Interrupt Enable Uint16 WDINTS:1; // 2 WD Interrupt Status Uint16 rsvd1:13; // 15:3 Reserved }; union SCSR_REG { Uint16 all; struct SCSR_BITS bit; }; struct WDCNTR_BITS { // bits description Uint16 WDCNTR:8; // 7:0 WD Counter Uint16 rsvd1:8; // 15:8 Reserved }; union WDCNTR_REG { Uint16 all; struct WDCNTR_BITS bit; }; struct WDKEY_BITS { // bits description Uint16 WDKEY:8; // 7:0 Key to pet the watchdog timer. Uint16 rsvd1:8; // 15:8 Reserved }; union WDKEY_REG { Uint16 all; struct WDKEY_BITS bit; }; struct WDCR_BITS { // bits description Uint16 WDPS:3; // 2:0 WD Clock Prescalar Uint16 WDCHK:3; // 5:3 WD Check Bits Uint16 WDDIS:1; // 6 WD Disable Uint16 rsvd1:1; // 7 Reserved Uint16 WDPRECLKDIV:4; // 11:8 WD Pre Clock Divider Uint16 rsvd2:4; // 15:12 Reserved }; union WDCR_REG { Uint16 all; struct WDCR_BITS bit; }; struct WDWCR_BITS { // bits description Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:7; // 15:9 Reserved }; union WDWCR_REG { Uint16 all; struct WDWCR_BITS bit; }; struct WD_REGS { Uint16 rsvd1[34]; // Reserved union SCSR_REG SCSR; // System Control & Status Register union WDCNTR_REG WDCNTR; // Watchdog Counter Register Uint16 rsvd2; // Reserved union WDKEY_REG WDKEY; // Watchdog Reset Key Register Uint16 rsvd3[3]; // Reserved union WDCR_REG WDCR; // Watchdog Control Register union WDWCR_REG WDWCR; // Watchdog Windowed Control Register }; struct CLA1TASKSRCSELLOCK_BITS { // bits description Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLA1TASKSRCSELLOCK_REG { Uint32 all; struct CLA1TASKSRCSELLOCK_BITS bit; }; struct DMACHSRCSELLOCK_BITS { // bits description Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DMACHSRCSELLOCK_REG { Uint32 all; struct DMACHSRCSELLOCK_BITS bit; }; struct CLA1TASKSRCSEL1_BITS { // bits description Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 }; union CLA1TASKSRCSEL1_REG { Uint32 all; struct CLA1TASKSRCSEL1_BITS bit; }; struct CLA1TASKSRCSEL2_BITS { // bits description Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 }; union CLA1TASKSRCSEL2_REG { Uint32 all; struct CLA1TASKSRCSEL2_BITS bit; }; struct DMACHSRCSEL1_BITS { // bits description Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA }; union DMACHSRCSEL1_REG { Uint32 all; struct DMACHSRCSEL1_BITS bit; }; struct DMACHSRCSEL2_BITS { // bits description Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA Uint16 rsvd1:16; // 31:16 Reserved }; union DMACHSRCSEL2_REG { Uint32 all; struct DMACHSRCSEL2_BITS bit; }; struct DMA_CLA_SRC_SEL_REGS { union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register Uint16 rsvd1[2]; // Reserved union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 Uint16 rsvd2[12]; // Reserved union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 }; struct ADCA_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCA_AC_REG { Uint32 all; struct ADCA_AC_BITS bit; }; struct ADCB_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCB_AC_REG { Uint32 all; struct ADCB_AC_BITS bit; }; struct ADCC_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCC_AC_REG { Uint32 all; struct ADCC_AC_BITS bit; }; struct CMPSS1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS1_AC_REG { Uint32 all; struct CMPSS1_AC_BITS bit; }; struct CMPSS2_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS2_AC_REG { Uint32 all; struct CMPSS2_AC_BITS bit; }; struct CMPSS3_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS3_AC_REG { Uint32 all; struct CMPSS3_AC_BITS bit; }; struct CMPSS4_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS4_AC_REG { Uint32 all; struct CMPSS4_AC_BITS bit; }; struct CMPSS5_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS5_AC_REG { Uint32 all; struct CMPSS5_AC_BITS bit; }; struct CMPSS6_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS6_AC_REG { Uint32 all; struct CMPSS6_AC_BITS bit; }; struct CMPSS7_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS7_AC_REG { Uint32 all; struct CMPSS7_AC_BITS bit; }; struct DACA_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DACA_AC_REG { Uint32 all; struct DACA_AC_BITS bit; }; struct DACB_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DACB_AC_REG { Uint32 all; struct DACB_AC_BITS bit; }; struct PGA1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA1_AC_REG { Uint32 all; struct PGA1_AC_BITS bit; }; struct PGA2_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA2_AC_REG { Uint32 all; struct PGA2_AC_BITS bit; }; struct PGA3_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA3_AC_REG { Uint32 all; struct PGA3_AC_BITS bit; }; struct PGA4_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA4_AC_REG { Uint32 all; struct PGA4_AC_BITS bit; }; struct PGA5_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA5_AC_REG { Uint32 all; struct PGA5_AC_BITS bit; }; struct PGA6_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA6_AC_REG { Uint32 all; struct PGA6_AC_BITS bit; }; struct PGA7_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PGA7_AC_REG { Uint32 all; struct PGA7_AC_BITS bit; }; struct EPWM1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM1_AC_REG { Uint32 all; struct EPWM1_AC_BITS bit; }; struct EPWM2_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM2_AC_REG { Uint32 all; struct EPWM2_AC_BITS bit; }; struct EPWM3_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM3_AC_REG { Uint32 all; struct EPWM3_AC_BITS bit; }; struct EPWM4_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM4_AC_REG { Uint32 all; struct EPWM4_AC_BITS bit; }; struct EPWM5_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM5_AC_REG { Uint32 all; struct EPWM5_AC_BITS bit; }; struct EPWM6_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM6_AC_REG { Uint32 all; struct EPWM6_AC_BITS bit; }; struct EPWM7_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM7_AC_REG { Uint32 all; struct EPWM7_AC_BITS bit; }; struct EPWM8_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM8_AC_REG { Uint32 all; struct EPWM8_AC_BITS bit; }; struct EQEP1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EQEP1_AC_REG { Uint32 all; struct EQEP1_AC_BITS bit; }; struct EQEP2_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EQEP2_AC_REG { Uint32 all; struct EQEP2_AC_BITS bit; }; struct ECAP1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP1_AC_REG { Uint32 all; struct ECAP1_AC_BITS bit; }; struct ECAP2_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP2_AC_REG { Uint32 all; struct ECAP2_AC_BITS bit; }; struct ECAP3_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP3_AC_REG { Uint32 all; struct ECAP3_AC_BITS bit; }; struct ECAP4_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP4_AC_REG { Uint32 all; struct ECAP4_AC_BITS bit; }; struct ECAP5_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP5_AC_REG { Uint32 all; struct ECAP5_AC_BITS bit; }; struct ECAP6_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP6_AC_REG { Uint32 all; struct ECAP6_AC_BITS bit; }; struct ECAP7_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP7_AC_REG { Uint32 all; struct ECAP7_AC_BITS bit; }; struct SDFM1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SDFM1_AC_REG { Uint32 all; struct SDFM1_AC_BITS bit; }; struct CLB1_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB1_AC_REG { Uint32 all; struct CLB1_AC_BITS bit; }; struct CLB2_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB2_AC_REG { Uint32 all; struct CLB2_AC_BITS bit; }; struct CLB3_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB3_AC_REG { Uint32 all; struct CLB3_AC_BITS bit; }; struct CLB4_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB4_AC_REG { Uint32 all; struct CLB4_AC_BITS bit; }; struct CLA1PROMCRC_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLA1PROMCRC_AC_REG { Uint32 all; struct CLA1PROMCRC_AC_BITS bit; }; struct SPIA_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SPIA_AC_REG { Uint32 all; struct SPIA_AC_BITS bit; }; struct SPIB_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SPIB_AC_REG { Uint32 all; struct SPIB_AC_BITS bit; }; struct PMBUS_A_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBUS_A_AC_REG { Uint32 all; struct PMBUS_A_AC_BITS bit; }; struct LIN_A_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LIN_A_AC_REG { Uint32 all; struct LIN_A_AC_BITS bit; }; struct DCANA_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 rsvd1:2; // 3:2 Reserved Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union DCANA_AC_REG { Uint32 all; struct DCANA_AC_BITS bit; }; struct DCANB_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 rsvd1:2; // 3:2 Reserved Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union DCANB_AC_REG { Uint32 all; struct DCANB_AC_BITS bit; }; struct FSIATX_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIATX_AC_REG { Uint32 all; struct FSIATX_AC_BITS bit; }; struct FSIARX_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIARX_AC_REG { Uint32 all; struct FSIARX_AC_BITS bit; }; struct HRPWM_A_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRPWM_A_AC_REG { Uint32 all; struct HRPWM_A_AC_BITS bit; }; struct PERIPH_AC_LOCK_BITS { // bits description Uint16 LOCK_AC_WR:1; // 0 Lock control for Access control registers write. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PERIPH_AC_LOCK_REG { Uint32 all; struct PERIPH_AC_LOCK_BITS bit; }; struct PERIPH_AC_REGS { union ADCA_AC_REG ADCA_AC; // ADCA Master Access Control Register union ADCB_AC_REG ADCB_AC; // ADCB Master Access Control Register union ADCC_AC_REG ADCC_AC; // ADCC Master Access Control Register Uint16 rsvd1[10]; // Reserved union CMPSS1_AC_REG CMPSS1_AC; // CMPSS1 Master Access Control Register union CMPSS2_AC_REG CMPSS2_AC; // CMPSS2 Master Access Control Register union CMPSS3_AC_REG CMPSS3_AC; // CMPSS3 Master Access Control Register union CMPSS4_AC_REG CMPSS4_AC; // CMPSS4 Master Access Control Register union CMPSS5_AC_REG CMPSS5_AC; // CMPSS5 Master Access Control Register union CMPSS6_AC_REG CMPSS6_AC; // CMPSS6 Master Access Control Register union CMPSS7_AC_REG CMPSS7_AC; // CMPSS7 Master Access Control Register Uint16 rsvd2[10]; // Reserved union DACA_AC_REG DACA_AC; // DACA Master Access Control Register union DACB_AC_REG DACB_AC; // DACB Master Access Control Register Uint16 rsvd3[12]; // Reserved union PGA1_AC_REG PGA1_AC; // PGAA Master Access Control Register union PGA2_AC_REG PGA2_AC; // PGAB Master Access Control Register union PGA3_AC_REG PGA3_AC; // PGAC Master Access Control Register union PGA4_AC_REG PGA4_AC; // PGAD Master Access Control Register union PGA5_AC_REG PGA5_AC; // PGAE Master Access Control Register union PGA6_AC_REG PGA6_AC; // PGAF Master Access Control Register union PGA7_AC_REG PGA7_AC; // PGAG Master Access Control Register Uint16 rsvd4[2]; // Reserved union EPWM1_AC_REG EPWM1_AC; // EPWM1 Master Access Control Register union EPWM2_AC_REG EPWM2_AC; // EPWM2 Master Access Control Register union EPWM3_AC_REG EPWM3_AC; // EPWM3 Master Access Control Register union EPWM4_AC_REG EPWM4_AC; // EPWM4 Master Access Control Register union EPWM5_AC_REG EPWM5_AC; // EPWM5 Master Access Control Register union EPWM6_AC_REG EPWM6_AC; // EPWM6 Master Access Control Register union EPWM7_AC_REG EPWM7_AC; // EPWM7 Master Access Control Register union EPWM8_AC_REG EPWM8_AC; // EPWM8 Master Access Control Register Uint16 rsvd5[24]; // Reserved union EQEP1_AC_REG EQEP1_AC; // EQEP1 Master Access Control Register union EQEP2_AC_REG EQEP2_AC; // EQEP2 Master Access Control Register Uint16 rsvd6[12]; // Reserved union ECAP1_AC_REG ECAP1_AC; // ECAP1 Master Access Control Register union ECAP2_AC_REG ECAP2_AC; // ECAP2 Master Access Control Register union ECAP3_AC_REG ECAP3_AC; // ECAP3 Master Access Control Register union ECAP4_AC_REG ECAP4_AC; // ECAP4 Master Access Control Register union ECAP5_AC_REG ECAP5_AC; // ECAP5 Master Access Control Register union ECAP6_AC_REG ECAP6_AC; // ECAP6 Master Access Control Register union ECAP7_AC_REG ECAP7_AC; // ECAP7 Master Access Control Register Uint16 rsvd7[26]; // Reserved union SDFM1_AC_REG SDFM1_AC; // SDFM1 Master Access Control Register Uint16 rsvd8[6]; // Reserved union CLB1_AC_REG CLB1_AC; // CLB1 Master Access Control Register union CLB2_AC_REG CLB2_AC; // CLB2 Master Access Control Register union CLB3_AC_REG CLB3_AC; // CLB3 Master Access Control Register union CLB4_AC_REG CLB4_AC; // CLB4 Master Access Control Register Uint16 rsvd9[8]; // Reserved union CLA1PROMCRC_AC_REG CLA1PROMCRC_AC; // CLA1PROMCRC Master Access Control Register Uint16 rsvd10[78]; // Reserved union SPIA_AC_REG SPIA_AC; // SPIA Master Access Control Register union SPIB_AC_REG SPIB_AC; // SPIB Master Access Control Register Uint16 rsvd11[28]; // Reserved union PMBUS_A_AC_REG PMBUS_A_AC; // PMBUSA Master Access Control Register Uint16 rsvd12[6]; // Reserved union LIN_A_AC_REG LIN_A_AC; // LINA Master Access Control Register Uint16 rsvd13[6]; // Reserved union DCANA_AC_REG DCANA_AC; // DCANA Master Access Control Register union DCANB_AC_REG DCANB_AC; // DCANB Master Access Control Register Uint16 rsvd14[20]; // Reserved union FSIATX_AC_REG FSIATX_AC; // FSIA Master Access Control Register union FSIARX_AC_REG FSIARX_AC; // FSIB Master Access Control Register Uint16 rsvd15[78]; // Reserved union HRPWM_A_AC_REG HRPWM_A_AC; // HRPWM Master Access Control Register Uint16 rsvd16[82]; // Reserved union PERIPH_AC_LOCK_REG PERIPH_AC_LOCK; // Lock Register to stop Write access to peripheral Access register. }; struct SYNCSELECT_BITS { // bits description Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 Uint16 rsvd1:3; // 8:6 Reserved Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 Uint32 ECAP6SYNCIN:3; // 17:15 Selects Sync Input Source for ECAP6 Uint16 rsvd2:9; // 26:18 Reserved Uint16 SYNCOUT:2; // 28:27 Select Syncout Source Uint16 EPWM1SYNCIN:3; // 31:29 Selects Sync Input Source for EPWM1 }; union SYNCSELECT_REG { Uint32 all; struct SYNCSELECT_BITS bit; }; struct ADCSOCOUTSELECT_BITS { // bits description Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAOn Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAOn Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAOn Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAOn Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAOn Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAOn Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAOn Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAOn Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:4; // 15:12 Reserved Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBOn Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBOn Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBOn Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBOn Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBOn Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBOn Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBOn Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBOn Uint16 rsvd6:1; // 24 Reserved Uint16 rsvd7:1; // 25 Reserved Uint16 rsvd8:1; // 26 Reserved Uint16 rsvd9:1; // 27 Reserved Uint16 rsvd10:4; // 31:28 Reserved }; union ADCSOCOUTSELECT_REG { Uint32 all; struct ADCSOCOUTSELECT_BITS bit; }; struct SYNCSOCLOCK_BITS { // bits description Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYNCSOCLOCK_REG { Uint32 all; struct SYNCSOCLOCK_BITS bit; }; struct SYNC_SOC_REGS { union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADCSOC Select Register union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register }; //--------------------------------------------------------------------------- // SYSCTRL External References & Function Declarations: // extern volatile struct WD_REGS WdRegs; extern volatile struct SYNC_SOC_REGS SyncSocRegs; extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; extern volatile struct DEV_CFG_REGS DevCfgRegs; extern volatile struct CLK_CFG_REGS ClkCfgRegs; extern volatile struct CPU_SYS_REGS CpuSysRegs; extern volatile struct PERIPH_AC_REGS SysPeriphAcRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_xbar.h // // TITLE: XBAR Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct XBARFLG1_BITS { // bits description Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal }; union XBARFLG1_REG { Uint32 all; struct XBARFLG1_BITS bit; }; struct XBARFLG2_BITS { // bits description Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal Uint16 ADCSOCA:1; // 6 Input Flag for ADCSOCA Signal Uint16 ADCSOCB:1; // 7 Input Flag for ADCSOCB Signal Uint16 INPUT7:1; // 8 Input Flag for INPUT7 Signal Uint16 INPUT8:1; // 9 Input Flag for INPUT8 Signal Uint16 INPUT9:1; // 10 Input Flag for INPUT9 Signal Uint16 INPUT10:1; // 11 Input Flag for INPUT10\ Signal Uint16 INPUT11:1; // 12 Input Flag for INPUT11 Signal Uint16 INPUT12:1; // 13 Input Flag for INPUT12 Signal Uint16 INPUT13:1; // 14 Input Flag for INPUT13 Signal Uint16 INPUT14:1; // 15 Input Flag for INPUT14 Signal Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal }; union XBARFLG2_REG { Uint32 all; struct XBARFLG2_BITS bit; }; struct XBARFLG3_BITS { // bits description Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal Uint16 rsvd5:1; // 15 Reserved Uint16 rsvd6:1; // 16 Reserved Uint16 rsvd7:1; // 17 Reserved Uint16 rsvd8:1; // 18 Reserved Uint16 rsvd9:1; // 19 Reserved Uint16 rsvd10:1; // 20 Reserved Uint16 rsvd11:1; // 21 Reserved Uint16 rsvd12:1; // 22 Reserved Uint16 ECAP7_OUT:1; // 23 Input Flag for ECAP7.OUT Signal Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag for SD1FLT1.COMPZ Signal Uint16 SD1FLT1_DRINT:1; // 25 Input Flag for SD1FLT1.DRINT Signal Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag for SD1FLT2.COMPZ Signal Uint16 SD1FLT2_DRINT:1; // 27 Input Flag for SD1FLT2.DRINT Signal Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag for SD1FLT3.COMPZ Signal Uint16 SD1FLT3_DRINT:1; // 29 Input Flag for SD1FLT3.DRINT Signal Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag for SD1FLT4.COMPZ Signal Uint16 SD1FLT4_DRINT:1; // 31 Input Flag for SD1FLT4.DRINT Signal }; union XBARFLG3_REG { Uint32 all; struct XBARFLG3_BITS bit; }; struct XBARFLG4_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:1; // 4 Reserved Uint16 rsvd6:1; // 5 Reserved Uint16 rsvd7:1; // 6 Reserved Uint16 rsvd8:1; // 7 Reserved Uint16 rsvd9:8; // 15:8 Reserved Uint16 rsvd10:1; // 16 Reserved Uint16 rsvd11:1; // 17 Reserved Uint16 rsvd12:1; // 18 Reserved Uint16 rsvd13:1; // 19 Reserved Uint16 rsvd14:1; // 20 Reserved Uint16 rsvd15:1; // 21 Reserved Uint16 rsvd16:1; // 22 Reserved Uint16 rsvd17:1; // 23 Reserved Uint16 rsvd18:7; // 30:24 Reserved Uint16 CLAHALT:1; // 31 Input Flag for CLAHALT Signal }; union XBARFLG4_REG { Uint32 all; struct XBARFLG4_BITS bit; }; struct XBARCLR1_BITS { // bits description Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal }; union XBARCLR1_REG { Uint32 all; struct XBARCLR1_BITS bit; }; struct XBARCLR2_BITS { // bits description Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal Uint16 INPUT6:1; // 5 Input Flag Clear for INPUT6 Signal Uint16 ADCSOCA:1; // 6 Input Flag Clear for ADCSOCA Signal Uint16 ADCSOCB:1; // 7 Input Flag Clear for ADCSOCB Signal Uint16 INPUT7:1; // 8 Input Flag Clear for INPUT7 Signal Uint16 INPUT8:1; // 9 Input Flag Clear for INPUT8 Signal Uint16 INPUT9:1; // 10 Input Flag Clear for INPUT9 Signal Uint16 INPUT10:1; // 11 Input Flag Clear for INPUT10 Signal Uint16 INPUT11:1; // 12 Input Flag Clear for INPUT11 Signal Uint16 INPUT12:1; // 13 Input Flag Clear for INPUT12 Signal Uint16 INPUT13:1; // 14 Input Flag Clear for INPUT13 Signal Uint16 INPUT14:1; // 15 Input Flag Clear for INPUT14 Signal Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal }; union XBARCLR2_REG { Uint32 all; struct XBARCLR2_BITS bit; }; struct XBARCLR3_BITS { // bits description Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal Uint16 rsvd5:1; // 15 Reserved Uint16 rsvd6:1; // 16 Reserved Uint16 rsvd7:1; // 17 Reserved Uint16 rsvd8:1; // 18 Reserved Uint16 rsvd9:1; // 19 Reserved Uint16 rsvd10:1; // 20 Reserved Uint16 rsvd11:1; // 21 Reserved Uint16 rsvd12:1; // 22 Reserved Uint16 ECAP7_OUT:1; // 23 Input Flag clear for ECAP7.OUT Signal Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag clear for SD1FLT1.COMPZ Signal Uint16 SD1FLT1_DRINT:1; // 25 Input Flag clear for SD1FLT1.DRINT Signal Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag clear for SD1FLT2.COMPZ Signal Uint16 SD1FLT2_DRINT:1; // 27 Input Flag clear for SD1FLT2.DRINT Signal Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag clear for SD1FLT3.COMPZ Signal Uint16 SD1FLT3_DRINT:1; // 29 Input Flag clear for SD1FLT3.DRINT Signal Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag clear for SD1FLT4.COMPZ Signal Uint16 SD1FLT4_DRINT:1; // 31 Input Flag clear for SD1FLT4.DRINT Signal }; union XBARCLR3_REG { Uint32 all; struct XBARCLR3_BITS bit; }; struct XBARCLR4_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:1; // 4 Reserved Uint16 rsvd6:1; // 5 Reserved Uint16 rsvd7:1; // 6 Reserved Uint16 rsvd8:1; // 7 Reserved Uint16 rsvd9:8; // 15:8 Reserved Uint16 rsvd10:1; // 16 Reserved Uint16 rsvd11:1; // 17 Reserved Uint16 rsvd12:1; // 18 Reserved Uint16 rsvd13:1; // 19 Reserved Uint16 rsvd14:1; // 20 Reserved Uint16 rsvd15:1; // 21 Reserved Uint16 rsvd16:1; // 22 Reserved Uint16 rsvd17:1; // 23 Reserved Uint16 rsvd18:7; // 30:24 Reserved Uint16 CLAHALT:1; // 31 Input Flag clear for CLAHALT Signal }; union XBARCLR4_REG { Uint32 all; struct XBARCLR4_BITS bit; }; struct XBAR_REGS { union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 union XBARFLG4_REG XBARFLG4; // X-Bar Input Flag Register 4 union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 union XBARCLR4_REG XBARCLR4; // X-Bar Input Flag Clear Register 4 Uint16 rsvd1[16]; // Reserved }; //--------------------------------------------------------------------------- // XBAR External References & Function Declarations: // extern volatile struct XBAR_REGS XbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f28004x_xint.h // // TITLE: XINT Register Definitions. // //########################################################################### // $TI Release: F28004x Support Library v1.01.00.00 $ // $Release Date: Mon May 22 15:39:38 CDT 2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XINT Individual Register Bit Definitions: struct XINT1CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT1 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT1 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT1CR_REG { Uint16 all; struct XINT1CR_BITS bit; }; struct XINT2CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT2 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT2 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT2CR_REG { Uint16 all; struct XINT2CR_BITS bit; }; struct XINT3CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT3 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT3 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT3CR_REG { Uint16 all; struct XINT3CR_BITS bit; }; struct XINT4CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT4 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT4 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT4CR_REG { Uint16 all; struct XINT4CR_BITS bit; }; struct XINT5CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT5 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT5 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT5CR_REG { Uint16 all; struct XINT5CR_BITS bit; }; struct XINT_REGS { union XINT1CR_REG XINT1CR; // XINT1 configuration register union XINT2CR_REG XINT2CR; // XINT2 configuration register union XINT3CR_REG XINT3CR; // XINT3 configuration register union XINT4CR_REG XINT4CR; // XINT4 configuration register union XINT5CR_REG XINT5CR; // XINT5 configuration register Uint16 rsvd1[3]; // Reserved Uint16 XINT1CTR; // XINT1 counter register Uint16 XINT2CTR; // XINT2 counter register Uint16 XINT3CTR; // XINT3 counter register }; //--------------------------------------------------------------------------- // XINT External References & Function Declarations: // extern volatile struct XINT_REGS XintRegs; //=========================================================================== // End of file. //=========================================================================== // // byte_peripheral attribute is only supported on the C28 // //=========================================================================== // End of file. //=========================================================================== /******************************************************************************* * File: diag_test_pin_control.h * * History: 2017-Aug-03 PF Initial creation of this file. * 2017-Aug-15 PF Changed this to be general purpose test pin control. *******************************************************************************/ /*************** * Prototypes. **************/ extern void diag_test_pin_ctrl_init(void); /************ * Defines. ***********/ /******************************************************************************* * File: diag_test_pin_hardware.h * * History: 2017-Aug-30 PF Initial creation of this file. *******************************************************************************/ /*************** * Prototypes. **************/ /* None. */ /************ * Defines. ***********/ /* LED2 uses GPIO34, LED Off requires output at a logic 1. */ /* Test pin 1 uses GPIO56. */ /* Test pin 2 uses GPIO57. */ /* Test pin 3 uses GPIO58. */ /*********************************** * For ISR enabling and disabling. **********************************/ /*********************** * For event captures. **********************/ /* PFC ADC has 4 conversions (ignoring temperature) at 320nS apiece, as measured by the capture timer. */ /* HV ADC has 5 conversions at 320nS apiece, as measured by the capture timer. */ /* ADCs must complete within one-half of a PWM cycle, as measured by the capture timer. */ /************************************ * For PFC related hardware access. ***********************************/ /*********************************** * For HV related hardware access. **********************************/ /************************************ * For SCR related hardware access. ***********************************/ /******************************************************************************* * File: cla_global.h * * History: 2017-Aug-28 PF Initial creation of this file. *******************************************************************************/ /************ * Defines. ***********/ /* The CLA is very sensitive to word alignment. The filler bytes below * are used to create a structure size optimized for CLA data access. * * The CLA is very sensitive to aligning long words (32 bit values) on * long word starting addresses. Therefore to optimize storage the largest * values need to be listed first otherwise the compiler stuffs extra * space in. * * The CLA is optimized for moving 32 bit values around. The structures * below allow all data to be moved using 32 bit values rather than the * actual 16 bit values. */ /* Storage for PFC ADC results. Broken into two separate buffers for better memory usage. */ typedef struct { union { struct { Uint32 Timestamp; Uint16 TimestampCheck; Uint16 StartOfCycle; int16 Shunt_Current; int16 Line_1_Voltage; int16 Line_X_Voltage; int16 CPU_Temperature; }; struct { Uint32 QuickMove0; Uint32 QuickMove1; Uint32 QuickMove2; Uint32 QuickMove3; }; }; } PFC_ADC_Results_STRUCT1; typedef struct { union { struct { int16 HV_Pos_Voltage; int16 HV_Mid_Voltage; }; struct { Uint32 QuickMove0; }; }; } PFC_ADC_Results_STRUCT2; /* Storage for HV ADC results. */ typedef struct { union { struct { Uint32 Timestamp; Uint16 TimestampCheck; Uint16 StartOfCycle; int16 Input_Shunt_Current; int16 Output_Voltage; int16 Output_Current; }; struct { Uint32 QuickMove0; Uint32 QuickMove1; Uint32 QuickMove2; Uint32 QuickMove3; }; }; } HV_ADC_Results_STRUCT; /* ADC buffer size. Must be power of 2. */ /* Duty cycle control - used for background task to tell ADC measurements * tasks how to set FETs. Must be a power of 2. */ /* Storage for PFC duty cycle control */ typedef struct { Uint16 MOS1_Buffer0[32]; /* Stores duty cycles that the PFC ISR task will use for continuously updating the MOS1 FET PWM. */ Uint16 MOS1_Buffer1[32]; /* Stores duty cycles that the PFC ISR task will use for continuously updating the MOS1 FET PWM. */ Uint16 MOS2_Buffer0[32]; /* Stores duty cycles that the PFC ISR task will use for continuously updating the MOS1 FET PWM. */ Uint16 MOS2_Buffer1[32]; /* Stores duty cycles that the PFC ISR task will use for continuously updating the MOS1 FET PWM. */ Uint16 BufferSelect; /* Selects use of Buffer0 or Buffer1. */ Uint16 BufferIndex_Get; /* Running index (non-wrap-around) for getting values from the duty cycle buffer. */ } PFC_DutyCycle_Control_STRUCT; /*************** * Prototypes. **************/ /* ADC result storage. */ extern volatile PFC_ADC_Results_STRUCT1 PFC_ADC_Results1[]; /* Global storage buffer for ADC values read during PFC ISR task. */ extern volatile PFC_ADC_Results_STRUCT2 PFC_ADC_Results2[]; /* Global storage buffer for ADC values read during PFC ISR task. */ extern volatile HV_ADC_Results_STRUCT HV_ADC_Results[]; /* Global storage buffer for ADC values read during HV ISR task. */ extern volatile Uint16 PFC_ADC_BufferIndex_Put; /* Running index (wrap-around) for putting values into the PFC ADC buffer. */ extern volatile Uint16 HV_ADC_BufferIndex_Put; /* Running index (wrap-around) for putting values into the HV ADC buffer. */ /* Duty cycle control (used for background task to tell ADC measurements tasks how to set FETs. */ extern volatile PFC_DutyCycle_Control_STRUCT PFC_DutyCycle_Control; /******************************************************************************* * File: cla_hv_task.h * * History: 2017-Aug-23 PF Initial creation of this file. *******************************************************************************/ /*************** * Prototypes. **************/ extern __attribute__((interrupt)) void cla_hv_task(void); /************ * Defines. ***********/ /* None. */ /******************** * Local variables. *******************/ /* None. */ /********************* * Local prototypes. ********************/ /* None. */ /******************************************************************************* * Function: cla_hv_task *******************************************************************************/ __attribute__((interrupt)) void cla_hv_task(void) { volatile uint16_t Test0; uint32_t Test1; uint32_t Test2; __mdebugstop(); Test0 = 0; //Test1 = 3, Test2 = 2147483652; Yes (test fails, improper unsigned 32 bit comparison) //Test1 = 3, Test2 = 2147483651; Yes //Test1 = 3, Test2 = 2147483650; No (test passed, correct unsigned 32 bit comparison) //Test1 = 3, Test2 = 2147483649; No //Test1 = 2, Test2 = 2147483651; Yes //Test1 = 2, Test2 = 2147483650; Yes //Test1 = 2, Test2 = 2147483649; No //Test1 = 2, Test2 = 2147483648; No //Test1 = 1, Test2 = 4294967295; Yes //Test1 = 1, Test2 = 4294967294; Yes //Test1 = 1, Test2 = 2147483651; Yes //Test1 = 1, Test2 = 2147483650; Yes //Test1 = 1, Test2 = 2147483649; Yes //Test1 = 1, Test2 = 2147483648; No //Test1 = 1, Test2 = 2147483647; No Test1 = 1; Test2 = 2147483649; if ( Test1 > Test2 ) { Test0 = 1; // This is just a failure indicator; it does not influence the problem. } __mdebugstop(); /* Acknowledge the interrupt and clear the event capture. */ AdccRegs . ADCINTFLGCLR . bit . ADCINT1 = 1; ECap2Regs . ECCLR . bit . CEVT1 = 1; }