/************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* STDINT.H */ /* */ /* Copyright (c) 2002 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* _ti_config.h */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*Unsupported pragmas are omitted */ # pragma diag_push # pragma CHECK_MISRA("-19.7") # pragma CHECK_MISRA("-19.4") # pragma CHECK_MISRA("-19.1") # pragma CHECK_MISRA("-19.15") # pragma diag_pop _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") _Pragma("CHECK_MISRA(\"-19.1\")") _Pragma("CHECK_MISRA(\"-19.6\")") /* Hide uses of the TI proprietary macros behind other macros. Implementations that don't implement these features should leave these macros undefined. */ /* Common definitions */ /* C */ /* C89/C99 */ /* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It is intended to be used for functions like abort and atexit that are supposed to be declared noexcept only in C++14 mode. */ /* Target-specific definitions */ /*****************************************************************************/ /* linkage.h */ /* */ /* Copyright (c) 1998 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ /* No modifiers are needed to access code or data */ /*--------------------------------------------------------------------------*/ /* Define _IDECL ==> how inline functions are declared */ /*--------------------------------------------------------------------------*/ #pragma diag_pop _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.1\")") /* no code before #include */ _Pragma("CHECK_MISRA(\"-19.7\")") /* prefer functions to macros */ /*****************************************************************************/ /* _STDINT40.H */ /* */ /* Copyright (c) 2018 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.7\")") /* prefer functions to macros */ /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ _Pragma("diag_pop") /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1991, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Berkeley Software Design, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 * $FreeBSD$ */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"none\")") /* * Testing against Clang-specific extensions. */ /* * This code has been put in place to help reduce the addition of * compiler specific defines in FreeBSD code. It helps to aid in * having a compiler-agnostic source tree. */ /* * Macro to test if we're using a specific version of gcc or later. */ /* * The __CONCAT macro is used to concatenate parts of symbol names, e.g. * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI * mode -- there must be no spaces between its arguments, and for nested * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also * concatenate double-quoted strings produced by the __STRING macro, but * this only works with ANSI C. * * __XSTRING is like __STRING, but it expands any macros in its argument * first. It is only available with ANSI C. */ /* * Compiler-dependent macros to help declare dead (non-returning) and * pure (no side effects) functions, and unused variables. They are * null except for versions of gcc that are known to support the features * properly (old versions of gcc-2 supported the dead and pure features * in a different (wrong) way). If we do not provide an implementation * for a given compiler, let the compile fail if it is told to use * a feature that we cannot live without. */ /* * TI ADD - check that __GNUC__ is defined before referencing it to avoid * generating an error when __GNUC__ treated as zero warning is * promoted to an error via -pdse195 option. */ /* * Keywords added in C11. */ /* * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode * without actually supporting the thread_local keyword. Don't check for * the presence of C++11 when defining _Thread_local. */ /* * Emulation of C11 _Generic(). Unlike the previously defined C11 * keywords, it is not possible to implement this using exactly the same * syntax. Therefore implement something similar under the name * __generic(). Unlike _Generic(), this macro can only distinguish * between a single type, so it requires nested invocations to * distinguish multiple cases. */ /* * C99 Static array indices in function parameter declarations. Syntax such as: * void bar(int myArray[static 10]); * is allowed in C99 but not in C++. Define __min_size appropriately so * headers using it can be compiled in either language. Use like this: * void bar(int myArray[__min_size(10)]); */ /* XXX: should use `#if __STDC_VERSION__ < 199901'. */ /* C++11 exposes a load of C99 stuff */ /* * GCC 2.95 provides `__restrict' as an extension to C90 to support the * C99-specific `restrict' type qualifier. We happen to use `__restrict' as * a way to define the `restrict' type qualifier without disturbing older * software that is unaware of C99 keywords. * The TI compiler supports __restrict in all compilation modes. */ /* * GNU C version 2.96 adds explicit branch prediction so that * the CPU back-end can hint the processor and also so that * code blocks can be reordered such that the predicted path * sees a more linear flow, thus improving cache behavior, etc. * * The following two macros provide us with a way to utilize this * compiler feature. Use __predict_true() if you expect the expression * to evaluate to true, and __predict_false() if you expect the * expression to evaluate to false. * * A few notes about usage: * * * Generally, __predict_false() error condition checks (unless * you have some _strong_ reason to do otherwise, in which case * document it), and/or __predict_true() `no-error' condition * checks, assuming you want to optimize for the no-error case. * * * Other than that, if you don't know the likelihood of a test * succeeding from empirical or other `hard' evidence, don't * make predictions. * * * These are meant to be used in places that are run `a lot'. * It is wasteful to make predictions in code that is run * seldomly (e.g. at subsystem initialization time) as the * basic block reordering that this affects can often generate * larger code. */ /* * We define this here since , , and * require it. */ /* * Given the pointer x to the member m of the struct s, return * a pointer to the containing structure. When using GCC, we first * assign pointer x to a local variable, to check that its type is * compatible with member m. */ /* * Compiler-dependent macros to declare that functions take printf-like * or scanf-like arguments. They are null except for versions of gcc * that are known to support the features properly (old versions of gcc-2 * didn't permit keeping the keywords out of the application namespace). */ /* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ /* * The following definition might not work well if used in header files, * but it should be better than nothing. If you want a "do nothing" * version, then it should generate some harmless declaration, such as: * #define __IDSTRING(name,string) struct __hack */ /* * Embed the rcs id of a source file in the resulting library. Note that in * more recent ELF binutils, we use .ident allowing the ID to be stripped. * Usage: * __FBSDID("$FreeBSD$"); */ /*- * The following definitions are an extension of the behavior originally * implemented in , but with a different level of granularity. * POSIX.1 requires that the macros we test be defined before any standard * header file is included. * * Here's a quick run-down of the versions: * defined(_POSIX_SOURCE) 1003.1-1988 * _POSIX_C_SOURCE == 1 1003.1-1990 * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option * _POSIX_C_SOURCE == 199309 1003.1b-1993 * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, * and the omnibus ISO/IEC 9945-1: 1996 * _POSIX_C_SOURCE == 200112 1003.1-2001 * _POSIX_C_SOURCE == 200809 1003.1-2008 * * In addition, the X/Open Portability Guide, which is now the Single UNIX * Specification, defines a feature-test macro which indicates the version of * that specification, and which subsumes _POSIX_C_SOURCE. * * Our macros begin with two underscores to avoid namespace screwage. */ /* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ /* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ /* Deal with various X/Open Portability Guides and Single UNIX Spec. */ /* * Deal with all versions of POSIX. The ordering relative to the tests above is * important. */ /*- * Deal with _ANSI_SOURCE: * If it is defined, and no other compilation environment is explicitly * requested, then define our internal feature-test macros to zero. This * makes no difference to the preprocessor (undefined symbols in preprocessing * expressions are defined to have value zero), but makes it more convenient for * a test program to print out the values. * * If a program mistakenly defines _ANSI_SOURCE and some other macro such as * _POSIX_C_SOURCE, we will assume that it wants the broader compilation * environment (and in fact we will never get here). */ /* User override __EXT1_VISIBLE */ /* * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h * translates them to __ARM_ARCH and the modern feature symbols defined by ARM. */ /* * Nullability qualifiers: currently only supported by Clang. */ /* * Type Safety Checking * * Clang provides additional attributes to enable checking type safety * properties that cannot be enforced by the C type system. */ /* * Lock annotations. * * Clang provides support for doing basic thread-safety tests at * compile-time, by marking which locks will/should be held when * entering/leaving a functions. * * Furthermore, it is also possible to annotate variables and structure * members to enforce that they are only accessed when certain locks are * held. */ /* Structure implements a lock. */ /* Function acquires an exclusive or shared lock. */ /* Function attempts to acquire an exclusive or shared lock. */ /* Function releases a lock. */ /* Function asserts that an exclusive or shared lock is held. */ /* Function requires that an exclusive or shared lock is or is not held. */ /* Function should not be analyzed. */ /* Guard variables and structure members by lock. */ _Pragma("diag_pop") /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2002 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 2002 Mike Barcroft * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 * From: @(#)types.h 8.3 (Berkeley) 1/5/94 * $FreeBSD$ */ _Pragma("diag_push") /* This file is required to use base types */ _Pragma("CHECK_MISRA(\"-6.3\")") /* * Basic types upon which most other types are built. */ typedef signed char __int8_t; typedef unsigned char __uint8_t; typedef short __int16_t; typedef unsigned short __uint16_t; typedef int __int32_t; typedef unsigned int __uint32_t; /* LONGLONG */ typedef long long __int64_t; /* LONGLONG */ typedef unsigned long long __uint64_t; /* * Standard type definitions. */ typedef __uint32_t __clock_t; /* clock()... */ typedef __int32_t __critical_t; typedef double __double_t; typedef float __float_t; typedef __int32_t __intfptr_t; typedef __int64_t __intmax_t; typedef __int32_t __intptr_t; typedef __int32_t __int_fast8_t; typedef __int32_t __int_fast16_t; typedef __int32_t __int_fast32_t; typedef __int64_t __int_fast64_t; typedef __int8_t __int_least8_t; typedef __int16_t __int_least16_t; typedef __int32_t __int_least32_t; typedef __int64_t __int_least64_t; typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ typedef __int32_t __register_t; typedef __int32_t __segsz_t; /* segment size (in pages) */ typedef __uint32_t __size_t; /* sizeof() */ typedef __int32_t __ssize_t; /* byte count or error */ typedef __uint32_t __time_t; typedef __uint32_t __uintfptr_t; typedef __uint64_t __uintmax_t; typedef __uint32_t __uintptr_t; typedef __uint32_t __uint_fast8_t; typedef __uint32_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; typedef __uint64_t __uint_fast64_t; typedef __uint8_t __uint_least8_t; typedef __uint16_t __uint_least16_t; typedef __uint32_t __uint_least32_t; typedef __uint64_t __uint_least64_t; typedef __uint32_t __u_register_t; typedef __uint32_t __vm_offset_t; typedef __uint32_t __vm_paddr_t; typedef __uint32_t __vm_size_t; typedef unsigned short ___wchar_t; /* * POSIX target specific _off_t type definition */ typedef long _off_t; /* * Unusual type definitions. */ typedef struct __va_list_t { void * __ap; } __va_list; _Pragma("diag_pop") _Pragma("diag_push") /* This file is required to use types without size and signedness */ _Pragma("CHECK_MISRA(\"-6.3\")") /* * Standard type definitions. */ typedef __int32_t __blksize_t; /* file block size */ typedef __int64_t __blkcnt_t; /* file block count */ typedef __int32_t __clockid_t; /* clock_gettime()... */ typedef __uint32_t __fflags_t; /* file flags */ typedef __uint64_t __fsblkcnt_t; typedef __uint64_t __fsfilcnt_t; typedef __uint32_t __gid_t; typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ typedef __uint64_t __ino_t; /* inode number */ typedef long __key_t; /* IPC key (for Sys V IPC) */ typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ typedef __uint16_t __mode_t; /* permissions */ typedef int __accmode_t; /* access permissions */ typedef int __nl_item; typedef __uint64_t __nlink_t; /* link count */ typedef _off_t __off_t; /* file offset (target-specific) */ typedef __int64_t __off64_t; /* file offset (always 64-bit) */ typedef __int32_t __pid_t; /* process [group] */ typedef __int64_t __rlim_t; /* resource limit - intentionally */ /* signed, because of legacy code */ /* that uses -1 for RLIM_INFINITY */ typedef __uint8_t __sa_family_t; typedef __uint32_t __socklen_t; typedef long __suseconds_t; /* microseconds (signed) */ typedef struct __timer *__timer_t; /* timer_gettime()... */ typedef struct __mq *__mqd_t; /* mq_open()... */ typedef __uint32_t __uid_t; typedef unsigned int __useconds_t; /* microseconds (unsigned) */ typedef int __cpuwhich_t; /* which parameter for cpuset. */ typedef int __cpulevel_t; /* level parameter for cpuset. */ typedef int __cpusetid_t; /* cpuset identifier. */ /* * Unusual type definitions. */ /* * rune_t is declared to be an ``int'' instead of the more natural * ``unsigned long'' or ``long''. Two things are happening here. It is not * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, * it looks like 10646 will be a 31 bit standard. This means that if your * ints cannot hold 32 bits, you will be in trouble. The reason an int was * chosen over a long is that the is*() and to*() routines take ints (says * ANSI C), but they use __ct_rune_t instead of int. * * NOTE: rune_t is not covered by ANSI nor other standards, and should not * be instantiated outside of lib/libc/locale. Use wchar_t. wint_t and * rune_t must be the same type. Also, wint_t should be able to hold all * members of the largest character set plus one extra value (WEOF), and * must be at least 16 bits. */ typedef int __ct_rune_t; /* arg type for ctype funcs */ typedef __ct_rune_t __rune_t; /* rune_t (see above) */ typedef __ct_rune_t __wint_t; /* wint_t (see above) */ /* Clang already provides these types as built-ins, but only in C++ mode. */ typedef __uint_least16_t __char16_t; typedef __uint_least32_t __char32_t; /* In C++11, char16_t and char32_t are built-in types. */ typedef struct { long long __max_align1 __attribute__((aligned(__alignof__(long long)))); long double __max_align2 __attribute__((aligned(__alignof__(long double)))); } __max_align_t; typedef __uint64_t __dev_t; /* device number */ typedef __uint32_t __fixpt_t; /* fixed point number */ /* * mbstate_t is an opaque object to keep conversion state during multibyte * stream conversions. */ typedef int _Mbstatet; typedef _Mbstatet __mbstate_t; typedef __uintmax_t __rman_res_t; /* * When the following macro is defined, the system uses 64-bit inode numbers. * Programs can use this to avoid including , with its associated * namespace pollution. */ _Pragma("diag_pop") /*- * SPDX-License-Identifier: BSD-2-Clause-NetBSD * * Copyright (c) 2001, 2002 Mike Barcroft * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ _Pragma("diag_push") /* 19.4 is issued for macros that are defined in terms of other macros. */ _Pragma("CHECK_MISRA(\"-19.4\")") _Pragma("CHECK_MISRA(\"-19.7\")") _Pragma("CHECK_MISRA(\"-19.13\")") /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types */ /* Minimum values of exact-width signed integer types. */ /* Maximum values of exact-width signed integer types. */ /* Maximum values of exact-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.2 Limits of minimum-width integer types */ /* Minimum values of minimum-width signed integer types. */ /* Maximum values of minimum-width signed integer types. */ /* Maximum values of minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.3 Limits of fastest minimum-width integer types */ /* Minimum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.4 Limits of integer types capable of holding object pointers */ /* * ISO/IEC 9899:1999 * 7.18.2.5 Limits of greatest-width integer types */ /* * ISO/IEC 9899:1999 * 7.18.3 Limits of other integer types */ /* Limits of ptrdiff_t. */ /* Limits of sig_atomic_t. */ /* Limit of size_t. */ /* Limits of wint_t. */ _Pragma("diag_pop") /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 David E. O'Brien * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ typedef __int8_t int8_t; typedef __int16_t int16_t; typedef __int32_t int32_t; typedef __int64_t int64_t; typedef __uint8_t uint8_t; typedef __uint16_t uint16_t; typedef __uint32_t uint32_t; typedef __uint64_t uint64_t; typedef __intptr_t intptr_t; typedef __uintptr_t uintptr_t; typedef __intmax_t intmax_t; typedef __uintmax_t uintmax_t; typedef __int_least8_t int_least8_t; typedef __int_least16_t int_least16_t; typedef __int_least32_t int_least32_t; typedef __int_least64_t int_least64_t; typedef __uint_least8_t uint_least8_t; typedef __uint_least16_t uint_least16_t; typedef __uint_least32_t uint_least32_t; typedef __uint_least64_t uint_least64_t; typedef __int_fast8_t int_fast8_t; typedef __int_fast16_t int_fast16_t; typedef __int_fast32_t int_fast32_t; typedef __int_fast64_t int_fast64_t; typedef __uint_fast8_t uint_fast8_t; typedef __uint_fast16_t uint_fast16_t; typedef __uint_fast32_t uint_fast32_t; typedef __uint_fast64_t uint_fast64_t; _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-10.1\")") /* GNU and Darwin define this and people seem to think it's portable */ _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") /* Limits of wchar_t. */ _Pragma("diag_pop") /* ISO/IEC 9899:2011 K.3.4.4 */ _Pragma("diag_pop") /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ _Pragma("CHECK_MISRA(\"-8.5\")") /* need to define inline function */ _Pragma("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ _Pragma("CHECK_MISRA(\"-19.7\")") /* need function-like macros */ _Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ _Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ /*---------------------------------------------------------------------------*/ /* Attributes are only available in relaxed ANSI mode. */ /*---------------------------------------------------------------------------*/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-5.7\")") /* keep names intact */ typedef struct { int quot, rem; } div_t; typedef struct { int quot, rem; } ldiv_t; typedef struct { long long quot, rem; } lldiv_t; _Pragma("diag_pop") typedef unsigned size_t; typedef unsigned short wchar_t; /*---------------------------------------------------------------*/ /* NOTE - Normally, abs, labs, and fabs are expanded inline, so */ /* no formal definition is really required. However, ANSI */ /* requires that they exist as separate functions, so */ /* they are supplied in the library. The prototype is */ /* here mainly for documentation. */ /*---------------------------------------------------------------*/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ int abs(int _val); long labs(long _val); long long llabs(long long _val); _Pragma("diag_pop") int atoi(const char *_st); long atol(const char *_st); long long atoll(const char *_st); char *ltoa(long val, char * buffer, int radix); static __inline double atof(const char *_st); long strtol(const char * __restrict _st, char ** __restrict _endptr, int _base); unsigned long strtoul(const char * __restrict _st, char ** __restrict _endptr, int _base); long long strtoll(const char * __restrict _st, char ** __restrict _endptr, int _base); unsigned long long strtoull(const char * __restrict _st, char ** __restrict _endptr, int _base); float strtof(const char * __restrict _st, char ** __restrict _endptr); double strtod(const char * __restrict _st, char ** __restrict _endptr); long double strtold(const char * __restrict _st, char ** __restrict _endptr); int rand(void); void srand(unsigned _seed); void *calloc(size_t _num, size_t _size) ; void *malloc(size_t _size) ; void *realloc(void *_ptr, size_t _size); void free(void *_ptr); void *memalign(size_t _aln, size_t _size) ; void *aligned_alloc(size_t _aln, size_t _size) ; void __TI_heap_stats(void); void *__TI_heap_check(void); size_t __TI_heap_total_available(void); size_t __TI_heap_largest_available(void); __attribute__((noreturn)) void abort(void) ; typedef void (*__TI_atexit_fn)(void); int atexit(__TI_atexit_fn _func) ; typedef int (*__TI_compar_fn)(const void *_a,const void *_b); void *bsearch(const void *_key, const void *_base, size_t _nmemb, size_t _size, __TI_compar_fn compar); void qsort(void *_base, size_t _nmemb, size_t _size, __TI_compar_fn compar); __attribute__((noreturn)) void exit(int _status); __attribute__((noreturn)) void _Exit(int _status); __attribute__((noreturn)) void quick_exit(int _status); int at_quick_exit(__TI_atexit_fn _func) ; div_t div(int _numer, int _denom); ldiv_t ldiv(long _numer, long _denom); lldiv_t lldiv(long long _numer, long long _denom); char *getenv(const char *_string); int system(const char *_name); int mblen(const char *_s, size_t _n); size_t mbstowcs(wchar_t * __restrict _dest, const char * __restrict _src, size_t _n); int mbtowc(wchar_t * __restrict _dest, const char * __restrict _src, size_t _n); size_t wcstombs(char * __restrict _dest, const wchar_t * __restrict _src, size_t _n); int wctomb(char *_s, wchar_t _wc); static __inline double atof(const char *_st) { return strtod(_st, (char **)0); } /* C2000-specific additions to header implemented with #include */ _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /*****************************************************************************/ /* stddef.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ _Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ typedef int ptrdiff_t; /*----------------------------------------------------------------------------*/ /* C++11 and C11 required max_align_t to be defined. The libc++ cstddef */ /* header expects the macro __DEFINED_max_align_t to be defined if it is to */ /* use the definintion of max_align_t from stddef.h. Only define it if */ /* compiling for C11 or we're in non strict ansi mode. */ /*----------------------------------------------------------------------------*/ typedef long double max_align_t; _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.10\")") /* need types as macro arguments */ _Pragma("diag_pop") _Pragma("diag_pop") /*****************************************************************************/ /* string.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ _Pragma("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ _Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ _Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ _Pragma("diag_pop") size_t strlen(const char *string); char *strcpy(char * __restrict dest, const char * __restrict src); char *strncpy(char * __restrict dest, const char * __restrict src, size_t n); char *strcat(char * __restrict string1, const char * __restrict string2); char *strncat(char * __restrict dest, const char * __restrict src, size_t n); char *strchr(const char *string, int c); char *strrchr(const char *string, int c); int strcmp(const char *string1, const char *string2); int strncmp(const char *string1, const char *string2, size_t n); int strcoll(const char *string1, const char *_string2); size_t strxfrm(char * __restrict to, const char * __restrict from, size_t n); char *strpbrk(const char *string, const char *chs); size_t strspn(const char *string, const char *chs); size_t strcspn(const char *string, const char *chs); char *strstr(const char *string1, const char *string2); char *strtok(char * __restrict str1, const char * __restrict str2); char *strerror(int _errno); char *strdup(const char *string); void *memmove(void *s1, const void *s2, size_t n); void *memccpy(void *dest, const void *src, int ch, size_t count); _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ void *memcpy(void * __restrict s1, const void * __restrict s2, size_t n); _Pragma("diag_pop") int memcmp(const void *cs, const void *ct, size_t n); void *memchr(const void *cs, int c, size_t n); void *memset(void *mem, int ch, size_t length); /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_string.h if POSIX is enabled. This will expose the */ /* xlocale string interface. */ /*----------------------------------------------------------------------------*/ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011, 2012 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ typedef struct _xlocale *locale_t; /* * This file is included from both string.h and xlocale.h. We need to expose * the declarations unconditionally if we are included from xlocale.h, but only * if we are in POSIX2008 mode if included from string.h. */ /* * POSIX2008 functions */ int strcoll_l(const char *s1, const char *s2, locale_t l); size_t strxfrm_l(char *s1, const char *s2, size_t sz, locale_t l); /* * xlocale extensions */ _Pragma("diag_pop") /*****************************************************************************/ /* STDIO.H */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* stdarg.h */ /* */ /* Copyright (c) 1996 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.7") /* need function-like macros */ #pragma CHECK_MISRA("-19.10") /* need types as macro arguments */ #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ typedef __va_list va_list; #pragma diag_pop _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-20.2\")") /* reuse of standard macros/objects/funcs */ _Pragma("CHECK_MISRA(\"-20.1\")") /* redefining reserved identifiers */ _Pragma("CHECK_MISRA(\"-19.7\")") /* use function instead of function-like macro */ _Pragma("CHECK_MISRA(\"-19.4\")") /* macros should have only simple expansions */ _Pragma("CHECK_MISRA(\"-19.1\")") /* include should follow directive or comment */ _Pragma("CHECK_MISRA(\"-16.3\")") /* parameters without names */ _Pragma("CHECK_MISRA(\"-6.3\")") /* use size/sign-specific typedefs */ /*---------------------------------------------------------------------------*/ /* Attributes are only available in relaxed ANSI mode. */ /*---------------------------------------------------------------------------*/ /****************************************************************************/ /* TYPES THAT ANSI REQUIRES TO BE DEFINED */ /****************************************************************************/ struct __sFILE { int fd; /* File descriptor */ unsigned char* buf; /* Pointer to start of buffer */ unsigned char* pos; /* Position in buffer */ unsigned char* bufend; /* Pointer to end of buffer */ unsigned char* buff_stop; /* Pointer to last read char in buffer */ unsigned int flags; /* File status flags (see below) */ }; typedef struct __sFILE FILE; typedef long fpos_t; /****************************************************************************/ /* DEVICE AND STREAM RELATED MACROS */ /****************************************************************************/ /****************************************************************************/ /* MACROS THAT DEFINE AND USE FILE STATUS FLAGS */ /****************************************************************************/ /****************************************************************************/ /* MACROS THAT ANSI REQUIRES TO BE DEFINED */ /****************************************************************************/ /******** END OF ANSI MACROS ************************************************/ /****************************************************************************/ /* DEVICE AND STREAM RELATED DATA STRUCTURES AND MACROS */ /****************************************************************************/ extern FILE _ftable[10]; extern char __TI_tmpnams[10][16]; /****************************************************************************/ /* FUNCTION DEFINITIONS - ANSI */ /****************************************************************************/ /****************************************************************************/ /* OPERATIONS ON FILES */ /****************************************************************************/ extern int remove(const char *_file); extern int rename(const char *_old, const char *_new); extern FILE *tmpfile(void); extern char *tmpnam(char *_s); /****************************************************************************/ /* FILE ACCESS FUNCTIONS */ /****************************************************************************/ extern int fclose(FILE * __restrict _fp); extern FILE *fopen(const char * __restrict _fname, const char * __restrict _mode); extern FILE *freopen(const char * __restrict _fname, const char * __restrict _mode, FILE * __restrict _fp); extern void setbuf(FILE * __restrict _fp, char * __restrict _buf); extern int setvbuf(FILE * __restrict _fp, char * __restrict _buf, int _type, size_t _size); extern int fflush(FILE *_fp); /****************************************************************************/ /* FORMATTED INPUT/OUTPUT FUNCTIONS */ /****************************************************************************/ extern int fprintf(FILE * __restrict _fp, const char * __restrict _format, ...) ; extern int fscanf(FILE * __restrict _fp, const char * __restrict _fmt, ...) ; extern int printf(const char * __restrict _format, ...) ; extern int scanf(const char * __restrict _fmt, ...) ; extern int sprintf(char * __restrict _string, const char * __restrict _format, ...) ; extern int snprintf(char * __restrict _string, size_t _n, const char * __restrict _format, ...) ; extern int sscanf(const char * __restrict _str, const char * __restrict _fmt, ...) ; extern int vfprintf(FILE * __restrict _fp, const char * __restrict _format, va_list _ap) ; extern int vfscanf(FILE * __restrict _fp, const char * __restrict _fmt, va_list _ap) ; extern int vprintf(const char * __restrict _format, va_list _ap) ; extern int vscanf(const char * __restrict _format, va_list _ap) ; extern int vsprintf(char * __restrict _string, const char * __restrict _format, va_list _ap) ; extern int vsnprintf(char * __restrict _string, size_t _n, const char * __restrict _format, va_list _ap) ; extern int vsscanf(const char * __restrict _str, const char * __restrict _fmt, va_list _ap) ; extern int asprintf(char **, const char *, ...) ; extern int vasprintf(char **, const char *, va_list) ; /****************************************************************************/ /* CHARACTER INPUT/OUTPUT FUNCTIONS */ /****************************************************************************/ extern int fgetc(FILE *_fp); extern char *fgets(char * __restrict _ptr, int _size, FILE * __restrict _fp); extern int fputc(int _c, FILE *_fp); extern int fputs(const char * __restrict _ptr, FILE * __restrict _fp); extern int getc(FILE *_p); extern int getchar(void); extern char *gets(char *_ptr); extern int putc(int _x, FILE *_fp); extern int putchar(int _x); extern int puts(const char *_ptr); extern int ungetc(int _c, FILE *_fp); /****************************************************************************/ /* DIRECT INPUT/OUTPUT FUNCTIONS */ /****************************************************************************/ extern size_t fread(void * __restrict _ptr, size_t _size, size_t _count, FILE * __restrict _fp); extern size_t fwrite(const void * __restrict _ptr, size_t _size, size_t _count, FILE * __restrict _fp); /****************************************************************************/ /* FILE POSITIONING FUNCTIONS */ /****************************************************************************/ extern int fgetpos(FILE * __restrict _fp, fpos_t * __restrict _pos); extern int fseek(FILE *_fp, long _offset, int _ptrname); extern int fsetpos(FILE * __restrict _fp, const fpos_t * __restrict _pos); extern long ftell(FILE *_fp); extern void rewind(FILE *_fp); /****************************************************************************/ /* ERROR-HANDLING FUNCTIONS */ /****************************************************************************/ extern void clearerr(FILE *_fp); extern int feof(FILE *_fp); extern int ferror(FILE *_fp); extern void perror(const char *_s); /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* If sys/_types.h is available, include it. xlocale.h assumes this file will */ /* have already provided a definition of __va_list. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdio.h if xlocale.h has already been included. This is */ /* to conform with FreeBSD's xlocale implementation. */ /*----------------------------------------------------------------------------*/ _Pragma("diag_pop") /* * Copyright (c) 2015-2015 Texas Instruments Incorporated * * ==================================================== * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this * software is freely granted, provided that this notice * is preserved. * ==================================================== */ /* * from: @(#)fdlibm.h 5.1 93/09/24 * $FreeBSD$ */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ _Pragma("CHECK_MISRA(\"-12.7\")") /* bitwise operators not allowed on signed ints */ _Pragma("CHECK_MISRA(\"-16.4\")") /* identifiers in fn defn/decl identical??? fabs/fabsf */ _Pragma("CHECK_MISRA(\"-19.1\")") /* only comments and preproc before #include */ _Pragma("CHECK_MISRA(\"-19.4\")") /* macros expand to simple things */ _Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-19.10\")") /* macro params enclosed in parens */ _Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ _Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ /*****************************************************************************/ /* _defs.h */ /* */ /* Copyright (c) 2015 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-6.3\")") /* numerical typedefs */ _Pragma("CHECK_MISRA(\"-8.1\")") /* visible prototypes */ _Pragma("CHECK_MISRA(\"-8.5\")") /* functions in header files */ _Pragma("CHECK_MISRA(\"-8.11\")") /* use static on fns with internal linkage */ _Pragma("CHECK_MISRA(\"-10.1\")") /* implicit conversion ... bool to int??? */ _Pragma("CHECK_MISRA(\"-10.3\")") /* cast integers but don't widen */ _Pragma("CHECK_MISRA(\"-12.1\")") /* operator precedence */ _Pragma("CHECK_MISRA(\"-12.2\")") /* different order of operations??? */ _Pragma("CHECK_MISRA(\"-12.4\")") /* RHS of &&/|| has side effects??? */ _Pragma("CHECK_MISRA(\"-12.7\")") /* Bitwise operators on signed types */ _Pragma("CHECK_MISRA(\"-14.7\")") /* single point of return */ _Pragma("CHECK_MISRA(\"-14.9\")") /* only compound statement after if/else */ _Pragma("CHECK_MISRA(\"-19.1\")") /* only comments and preproc before #include??? */ _Pragma("CHECK_MISRA(\"-19.4\")") /* macro expands to unparenthesized */ _Pragma("CHECK_MISRA(\"-19.6\")") /* #undef */ _Pragma("CHECK_MISRA(\"-19.7\")") /* function-like macro */ _Pragma("diag_suppress 1558") /* --float_operations_allowed checks */ _Pragma("diag_suppress 3195") /* --advice:performance EABI float_operations_allowed checks */ /*---------------------------------------------------------------------------*/ /* _INLINE_DEFINITION */ /* */ /* The regular (non-llvm-based) TI tools assume C++ inline semantics by */ /* default, so if a function ends up not being inlined, then its definition */ /* is kept in the compilation unit (but via COMDAT, we'll only keep one */ /* definition of the function for the whole application). */ /* */ /* However, llvm-based TI tools (like arm-llvm) use clang, and clang does */ /* not assume C++ inline semantics by default. With the below definition of */ /* _INLINE_DEFINITION for clang, we are going to force functions that are */ /* declared with __inline to be *always* inlined (even when optimization or */ /* inlining is somehow disabled). */ /*---------------------------------------------------------------------------*/ /* This file is included in other user header files; take care not to pollute the namespace */ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1988, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)limits.h 8.3 (Berkeley) 1/4/94 * $FreeBSD$ */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") /* * According to ANSI (section 2.2.4.2), the values below must be usable by * #if preprocessing directives. Additionally, the expression must have the * same type as would an expression that is an object of the corresponding * type converted according to the integral promotions. The subtraction for * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). */ /* max value for an unsigned long long */ /* Quads and long longs are the same size. Ensure they stay in sync. */ /* Minimum signal stack size. */ _Pragma("diag_pop") /* normalize target-specific intrinsics */ /* always inline these functions so that calls to them don't appear in an object file and become part of the ABI. */ __inline int __isfinite(double d) { return (((((unsigned int)(((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) == 0; } __inline int __isfinitef(float f) { return (((((unsigned int)((_ftoi(f)) >> 16)) & 0x7f80u) == 0x7f80u)) == 0; } __inline int __isfinitel(long double e) { return (((((unsigned int)(((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) == 0; } __inline int __isnan(double d) { return (((((unsigned int)(((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) && ((((((((__uint64_t)_hi(d) << 32 | _lo(d)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0)) == 0); } __inline int __isnanf(float f) { return (((((unsigned int)((_ftoi(f)) >> 16)) & 0x7f80u) == 0x7f80u)) && (((((_ftoi(f)) & (((__uint32_t)(1) << (24-1)) - 1)) == 0)) == 0); } __inline int __isnanl(long double e) { return (((((unsigned int)(((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) && ((((((((__uint64_t)_hi(e) << 32 | _lo(e)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0)) == 0); } __inline int __isnormal(double d) { return (((((((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> (53-1)) & ((1024u * 2) - 1)) == 0)) == 0) && ((((((unsigned int)(((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) == 0); } __inline int __isnormalf(float f) { return ((((((unsigned int)((_ftoi(f)) >> (24-1))) & ((128u * 2) - 1)) == 0)) == 0) && ((((((unsigned int)((_ftoi(f)) >> 16)) & 0x7f80u) == 0x7f80u)) == 0); } __inline int __isnormall(long double e) { return (((((((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> (53-1)) & ((1024u * 2) - 1)) == 0)) == 0) && ((((((unsigned int)(((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) == 0); } __inline int __signbit(double d) { return (((((((__uint64_t)_hi(d) << 32 | _lo(d)))) & ((__uint64_t)(1) << (64-1))) == 0)) == 0; } __inline int __signbitf(float f) { return ((((_ftoi(f)) & ((__uint32_t)(1) << (32-1))) == 0)) == 0; } __inline int __signbitl(long double e) { return (((((((__uint64_t)_hi(e) << 32 | _lo(e)))) & ((__uint64_t)(1) << (64-1))) == 0)) == 0; } /* FreeBSD lib/libc/gen/isinf.c says "These routines belong in libm, but they must remain in libc for binary compat until we can bump libm's major version number" */ __inline int __isinff(float f) { return (((((unsigned int)((_ftoi(f)) >> 16)) & 0x7f80u) == 0x7f80u)) && ((((_ftoi(f)) & (((__uint32_t)(1) << (24-1)) - 1)) == 0)); } __inline int __isinf (double d) { return (((((unsigned int)(((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) && (((((((__uint64_t)_hi(d) << 32 | _lo(d)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0)); } __inline int __isinfl(long double e) { return (((((unsigned int)(((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> 48)) & 0x7ff0u) == 0x7ff0u)) && (((((((__uint64_t)_hi(e) << 32 | _lo(e)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0)); } /* Symbolic constants to classify floating point numbers. */ __inline int __fpclassifyf(float f) { if ((((((unsigned int)((_ftoi(f)) >> 16)) & 0x7f80u) == 0x7f80u))) { if (((((_ftoi(f)) & (((__uint32_t)(1) << (24-1)) - 1)) == 0))) return 1; else return 2; } if ((((((unsigned int)((_ftoi(f)) >> (24-1))) & ((128u * 2) - 1)) == 0))) { if (((((_ftoi(f)) & (((__uint32_t)(1) << (24-1)) - 1)) == 0))) return 0; else return (-2); } return (-1); } __inline int __fpclassify (double d) { if ((((((unsigned int)(((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> 48)) & 0x7ff0u) == 0x7ff0u))) { if ((((((((__uint64_t)_hi(d) << 32 | _lo(d)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0))) return 1; else return 2; } if (((((((((__uint64_t)_hi(d) << 32 | _lo(d)))) >> (53-1)) & ((1024u * 2) - 1)) == 0))) { if ((((((((__uint64_t)_hi(d) << 32 | _lo(d)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0))) return 0; else return (-2); } return (-1); } __inline int __fpclassifyl(long double e) { if ((((((unsigned int)(((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> 48)) & 0x7ff0u) == 0x7ff0u))) { if ((((((((__uint64_t)_hi(e) << 32 | _lo(e)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0))) return 1; else return 2; } if (((((((((__uint64_t)_hi(e) << 32 | _lo(e)))) >> (53-1)) & ((1024u * 2) - 1)) == 0))) { if ((((((((__uint64_t)_hi(e) << 32 | _lo(e)))) & (((__uint64_t)(1) << (53-1)) - 1)) == 0))) return 0; else return (-2); } return (-1); } /* * Relevant target macros indicating hardware float support * * all * __TI_PROPRIETARY_STRICT_FP_MACRO * ARM * __ARM_FP * C2000 * __TMS320C28XX_FPU32__ * __TMS320C28XX_FPU64__ * __TMS320C28XX_TMU__ adds div, sqrt, sin, cos, atan, atan2 * C6000 * _TMS320C6700 indicates C67x or later */ _Pragma("diag_pop") /* * ANSI/POSIX */ /* Symbolic constants to classify floating point numbers. */ /* * XOPEN/SVID */ /*---------------------------------------------------------------------------*/ /* If --fp_mode=relaxed is used and VFP is enabled, use the hardware square */ /* root directly instead of calling the sqrtx routine. This will not set */ /* errno if the argument is negative. */ /* */ /* This is done by defining sqrt to _relaxed_sqrt to allow other translation */ /* units to use the normal sqrt routine under strict mode. */ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /* TMU SUPPORT AND RELAXED MODE: USE INSTRINSICS. */ /*---------------------------------------------------------------------------*/ /* Disable double_t and float_t for C28x because of Motorware (AY 2015) */ /* These typedefs depend on the value of FLT_EVAL_METHOD */ typedef double double_t; typedef float float_t; double acos(double x); float acosf(float x); long double acosl(long double x); double asin(double x); float asinf(float x); long double asinl(long double x); double atan(double x); float atanf(float x); long double atanl(long double x); double atan2(double y, double x); float atan2f(float y, float x); long double atan2l(long double y, long double x); double cos(double x); float cosf(float x); long double cosl(long double x); double sin(double x); float sinf(float x); long double sinl(long double x); double tan(double x); float tanf(float x); long double tanl(long double x); double acosh(double x); float acoshf(float x); long double acoshl(long double x); double asinh(double x); float asinhf(float x); long double asinhl(long double x); double atanh(double x); float atanhf(float x); long double atanhl(long double x); double cosh(double x); float coshf(float x); long double coshl(long double x); double sinh(double x); float sinhf(float x); long double sinhl(long double x); double tanh(double x); float tanhf(float x); long double tanhl(long double x); double exp(double x); float expf(float x); long double expl(long double x); double exp2(double x); float exp2f(float x); long double exp2l(long double x); double expm1(double x); float expm1f(float x); long double expm1l(long double x); double frexp(double val, int *e); float frexpf(float val, int *e); long double frexpl(long double val, int *e); int ilogb(double x); int ilogbf(float x); int ilogbl(long double x); double ldexp(double x, int e); float ldexpf(float x, int e); long double ldexpl(long double x, int e); double log(double x); float logf(float x); long double logl(long double x); double log10(double x); float log10f(float x); long double log10l(long double x); double log1p(double x); float log1pf(float x); long double log1pl(long double x); double log2(double x); float log2f(float x); long double log2l(long double x); double logb(double x); float logbf(float x); long double logbl(long double x); double modf(double val, double *iptr); float modff(float val, float *iptr); long double modfl(long double val, long double *iptr); double scalbn(double x, int n); float scalbnf(float x, int n); long double scalbnl(long double x, int n); double scalbln(double x, long n); float scalblnf(float x, long n); long double scalblnl(long double x, long n); double cbrt(double x); float cbrtf(float x); long double cbrtl(long double x); double fabs(double x); float fabsf(float x); long double fabsl(long double x); double hypot(double x, double y); float hypotf(float x, float y); long double hypotl(long double x, long double y); double pow(double x, double y); float powf(float x, float y); long double powl(long double x, long double y); double sqrt(double x); float sqrtf(float x); long double sqrtl(long double x); double erf(double x); float erff(float x); long double erfl(long double x); double erfc(double x); float erfcf(float x); long double erfcl(long double x); double lgamma(double x); float lgammaf(float x); long double lgammal(long double x); double tgamma(double x); float tgammaf(float x); long double tgammal(long double x); double ceil(double x); float ceilf(float x); long double ceill(long double x); double floor(double x); float floorf(float x); long double floorl(long double x); double nearbyint(double x); float nearbyintf(float x); long double nearbyintl(long double x); double rint(double x); float rintf(float x); long double rintl(long double x); long lrint(double x); long lrintf(float x); long lrintl(long double x); long long llrint(double x); long long llrintf(float x); long long llrintl(long double x); double round(double x); float roundf(float x); long double roundl(long double x); long lround(double x); long lroundf(float x); long lroundl(long double x); long long llround(double x); long long llroundf(float x); long long llroundl(long double x); double trunc(double x); float truncf(float x); long double truncl(long double x); double fmod(double x, double y); float fmodf(float x, float y); long double fmodl(long double x, long double y); double remainder(double x, double y); float remainderf(float x, float y); long double remainderl(long double x, long double y); double remquo(double x, double y, int *quo); float remquof(float x, float y, int *quo); long double remquol(long double x, long double y, int *quo); double copysign(double x, double y); float copysignf(float x, float y); long double copysignl(long double x, long double y); double nan(const char *tagp); float nanf(const char *tagp); long double nanl(const char *tagp); double nextafter(double x, double y); float nextafterf(float x, float y); long double nextafterl(long double x, long double y); double nexttoward(double x, long double y); float nexttowardf(float x, long double y); long double nexttowardl(long double x, long double y); double fdim(double x, double y); float fdimf(float x, float y); long double fdiml(long double x, long double y); double fmax(double x, double y); float fmaxf(float x, float y); long double fmaxl(long double x, long double y); double fmin(double x, double y); float fminf(float x, float y); long double fminl(long double x, long double y); double fma(double x, double y, double z); float fmaf(float x, float y, float z); long double fmal(long double x, long double y, long double z); _Pragma("diag_pop") /* BIOS/XDC Include Files. */ /* * Copyright (c) 2008-2016 Texas Instruments. All rights reserved. * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* macros to simplify "stringification" and computed includes */ /* TitleCase standard types */ typedef char xdc_Char; typedef unsigned char xdc_UChar; typedef short xdc_Short; typedef unsigned short xdc_UShort; typedef int xdc_Int; typedef unsigned int xdc_UInt; typedef long xdc_Long; typedef unsigned long xdc_ULong; typedef float xdc_Float; typedef double xdc_Double; typedef long double xdc_LDouble; typedef size_t xdc_SizeT; typedef va_list xdc_VaList; /* Generic Extended Types */ typedef unsigned short xdc_Bool; /* boolean flag */ typedef void *xdc_Ptr; /* data pointer */ typedef const void *xdc_CPtr; /* data pointer */ typedef char *xdc_String; /* null terminated string */ typedef const char *xdc_CString; /* null terminated immutable string */ /* we intentionally omit arguments from Fxn to indicate that it can have * any (or none). Unfortunately this causes gcc to emit warnings when * -Wstrict-prototypes is used. Newer gcc's (4.6 or later) support a pragma * that works around this: * * #pragma GCC diagnostic ignored "-Wstrict-prototypes" */ typedef int (*xdc_Fxn)(); /* function pointer */ /* * Import the target-specific std.h */ /* * Copyright (c) 2008 Texas Instruments and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * which accompanies this distribution, and is available at * http://www.eclipse.org/legal/epl-v10.html * * Contributors: * Texas Instruments - initial implementation * * */ /* * ======== ti/targets/arm/elf/std.h ======== * Standard types for supported TI Arm compilers for ELF */ /* Define target-specific "portable" macros * * The build command-line define xdc_target_name__ to be the value * of the target's name config parameter. We use this to include the * target-specific definitions for the required target-independent * xdc_target* macros. */ /* * Copyright 2018 by Texas Instruments Incorporated. * */ /* * ======== R4F.h ======== * DO NOT MODIFY: This header is generated from stddef.xdt * * This header contains target-specific definitions of target-independent * macros required by the ITarget interface. These definitions allow C/C++ * sources to portably compile for multiple targets (using #ifdef ...). */ /* * ======== ti_targets_arm_elf_R4F ======== * This macro identifies the specific target being used. This macro should * probably be avoided in portable sources. */ /* * ======== xdc_target__arraytype_VaList ======== * The following macro specifies whether or not a VaList is an * array type; e.g., struct __va_list_tag (*)[1] verses a simple char *. * This affects how va_list variables are passed to functions (by value * or by address). */ /* * ======== xdc_target__isaCompatible_* macros ======== * The following definitions enable clients to conditionally compile for any * compatible subset of the actual target ISA. */ /* * ======== xdc_target__isa_v7R ======== * This macro identifies the specific target ISA for which we are being * compiled. */ /* * ======== xdc_target__{big|little}Endian ======== * The following macro enables clients to portably compile for big or little * endian targets. */ /* * ======== xdc_target__os_undefined ======== * The following macro enables clients to portably compile for target specific * OS; e.g., Linux, Solaris, Windows, undefined. */ /* * ======== xdc_target__sizeof_ ======== * The following macros enable clients to portably determine type sizes * within #ifdef blocks; sizeof() can't be used and the definitions in * stdint.h are not available to C++ clients (unless the special macro * __STDC_LIMIT_MACROS is defined). */ /* * ======== xdc_target__alignof_ ======== * The following macros enable clients to portably determine type alignment * within #ifdef blocks; even if provided by the compiler, alignof() can't * be used in pre-processor statements. */ /* * ======== xdc_target__bitsPerChar ======== * The number of bits in a char. This macro allow one to determine the * precise number of bits in any of the standard types (whose sizes are * expressed as a number of chars). */ /* * @(#) ti.targets.arm.elf; 1, 0, 0,0; 7-20-2018 13:59:04; /db/ztree/library/trees/xdctargets/xdctargets-r09/src/ xlibrary */ /* "inherit" (i.e., include) all ti.targets standard types */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * which accompanies this distribution, and is available at * http://www.eclipse.org/legal/epl-v10.html * * Contributors: * Texas Instruments - initial implementation * * */ /* * ======== ti/targets/std.h ======== * Standard types for supported TI compilers * */ /* allow _TI_STD_TYPES like 'Uns' and 'Uint8' */ /* include target-specific "portable" macros */ /* * xdc__LONGLONG__ indicates if compiler supports 'long long' type * xdc__BITS __ indicates if compiler supports 'uint_t' type */ /* * ======== [U]Int ======== */ typedef int_least8_t xdc_Int8; typedef uint_least8_t xdc_UInt8; typedef int_least16_t xdc_Int16; typedef uint_least16_t xdc_UInt16; typedef int_least32_t xdc_Int32; typedef uint_least32_t xdc_UInt32; typedef int_least64_t xdc_Int64; typedef uint_least64_t xdc_UInt64; /* * ======== Bits ======== */ typedef uint8_t xdc_Bits8; typedef uint16_t xdc_Bits16; typedef uint32_t xdc_Bits32; typedef uint64_t xdc_Bits64; /* * ======== [UI]Arg ======== */ typedef intptr_t xdc_IArg; typedef uintptr_t xdc_UArg; /* * ======== restrict ======== */ /* * ======== ti_targets_mkPragma ======== */ /* * ======== xdc__META ======== */ /* * ======== __ti__ ======== * These symbols are used by RTSC tools to indicate presence/absence of * assorted #pragma options in TI compiler. */ /* * @(#) ti.targets; 1, 0, 3,0; 7-20-2018 13:58:59; /db/ztree/library/trees/xdctargets/xdctargets-r09/src/ xlibrary */ /* * @(#) ti.targets.arm.elf; 1, 0, 0,0; 7-20-2018 13:59:04; /db/ztree/library/trees/xdctargets/xdctargets-r09/src/ xlibrary */ /* Each modules' internal header file defines 'module' as * xdc__MODOBJADDR__(Module__state__V), where Module__state__V is the actual * object where the module state is kept. For most targets, the default macro * given here results in the construct '(&Module__state__V)->field', when the * expression 'module->field' is used. Compilers then generate the code that * doesn't dereference a pointer, but puts the address of the field in the * code. * The targets that need to do something different can define * xdc__MODOBJADDR__ in std.h for their target package. */ /* Long Long Types */ typedef long long xdc_LLong; typedef unsigned long long xdc_ULLong; /* Arg to Ptr and Fxn conversion operators * * Individual targets may override these definitions in the event * that compilers issue warnings about shortening of an Arg to a pointer, * for example. */ static xdc_Ptr xdc_iargToPtr(xdc_IArg a); static xdc_Ptr xdc_uargToPtr(xdc_UArg a); static inline xdc_Ptr xdc_iargToPtr(xdc_IArg a) { return ((xdc_Ptr)a); } static inline xdc_Ptr xdc_uargToPtr(xdc_UArg a) { return ((xdc_Ptr)a); } static xdc_Fxn xdc_iargToFxn(xdc_IArg a); static xdc_Fxn xdc_uargToFxn(xdc_UArg a); static inline xdc_Fxn xdc_iargToFxn(xdc_IArg a) { return ((xdc_Fxn)a); } static inline xdc_Fxn xdc_uargToFxn(xdc_UArg a) { return ((xdc_Fxn)a); } /* * functions to efficiently convert a single precision float to an IArg * and vice-versa while maintaining client type safety * * Here the assumption is that sizeof(Float) <= sizeof(IArg); */ typedef union { xdc_Float f; xdc_IArg a; } xdc_FloatData; static xdc_IArg xdc_floatToArg(xdc_Float f); static inline xdc_IArg xdc_floatToArg(xdc_Float f) { xdc_FloatData u; u.f = f; return (u.a); } static xdc_Float xdc_argToFloat(xdc_IArg a); static inline xdc_Float xdc_argToFloat(xdc_IArg a) { xdc_FloatData u; u.a = a; return (u.f); } /* restrict keyword */ /* Unprefixed Aliases */ typedef xdc_Char Char; typedef xdc_UChar UChar; typedef xdc_Short Short; typedef xdc_UShort UShort; typedef xdc_Int Int; typedef xdc_UInt UInt; typedef xdc_Long Long; typedef xdc_ULong ULong; typedef xdc_LLong LLong; typedef xdc_ULLong ULLong; typedef xdc_Float Float; typedef xdc_Double Double; typedef xdc_LDouble LDouble; typedef xdc_SizeT SizeT; typedef xdc_VaList VaList; typedef xdc_IArg IArg; typedef xdc_UArg UArg; typedef xdc_Bool Bool; typedef xdc_Int8 Int8; typedef xdc_Int16 Int16; typedef xdc_Int32 Int32; typedef xdc_Fxn Fxn; typedef xdc_Ptr Ptr; typedef xdc_CPtr CPtr; typedef xdc_String String; typedef xdc_CString CString; typedef xdc_UInt8 UInt8; typedef xdc_UInt16 UInt16; typedef xdc_UInt32 UInt32; /* DEPRECATED Aliases */ /* xdc_Arg is defined only in ti/targets/std.h; use IArg and UArg instead */ typedef xdc_UInt8 Uint8; typedef xdc_UInt16 Uint16; typedef xdc_UInt32 Uint32; typedef xdc_UInt Uns; /* * ======== optional types ======== * The following types are not always defined for all targets */ typedef xdc_Int64 Int64; typedef xdc_UInt64 UInt64; /* The following exact size types are not required by C99 and may not be * supported by some compiler/processor environments. For greater * portability, use the IntN or UIntN types above. */ typedef xdc_Bits8 Bits8; typedef xdc_Bits16 Bits16; typedef xdc_Bits32 Bits32; typedef xdc_Bits64 Bits64; /* Standard Constants */ /* NULL must be 0 for C++ and is set to 0 in C to allow legacy code to * compile without warnings. * * If xdc__strict is defined, NULL is defined to be a pointer to allow * maximal type checking in "modern" C sources */ /* Declaration Qualifiers */ /* * ======== xdc__CODESECT ======== * Code-Section Directive * * Targets can optionally #define xdc__CODESECT in their specific * std.h files. This directive is placed in front of all * "extern" function declarations, and specifies a section-name in * which to place this function. This approach * provides more control on combining/organizing groups of * related functions into a single named sub-section (e.g., * "init-code") If this macro is not defined by the target, an * empty definition is used instead. */ /* * ======== xdc__META ======== * Embed unreferenced string in the current file * * Strings emebdded via xdc__META can be placed in a section that is * _not_ loaded on the target but are, nevertheless, part of the * executable and available to loaders. * * Different targets may define this macro in a way that places these * strings in an output section that is not loaded (and therefore does * not takeup space on the target). Unless the target provides a * definition of xdc__META, the definition below simply defines * as string constant in the current file. */ /* * @(#) xdc; 1, 1, 1,0; 7-31-2018 11:48:19; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2008 Texas Instruments and others. * All rights reserved. This program and the accompanying materials * are made available under the terms of the Eclipse Public License v1.0 * which accompanies this distribution, and is available at * http://www.eclipse.org/legal/epl-v10.html * * Contributors: * Texas Instruments - initial implementation * * */ /* * ======== global.h ======== * This header is used by C/C++ sources that want to "portably" include a * configuration-specific generated header (which contains extern * declarations of configuration specified global variables). * * To use this header you must define the symbol xdc_cfg__header__ to be * the package-qualified name of the configuration header. * * For example, to compile sources that reference config values * for a TI C6x target with a generated * configuration header named "package/cfg/mycfg_p62.h" in a package * named "local.examples" the following command line is sufficient: * * cl6x -Dxdc_cfg__header__=local/examples/package/cfg/mycfg_p62.h ... */ /* support old compiler option for naming config include file */ /* if specified, include configuration generated header */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Copyright (c) 2008-2018 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== xdc.h ======== * All generated public module headers include this file */ /* * ======== __CONC__ ======== * Concatenate the specified tokens to create a new single token */ /* * ======== __STR__ ======== * Stringify the specified arguement */ /* * ======== xdc_FILE__ ======== * Alternative to __FILE__ which defaults to NULL * * We define our own symbol in lieu of the standard __FILE__ * so we can avoid embedding lots of static strings in applications * that use Error and Assert. * * Both Error and Assert use xdc_FILE__ and ALL module internal headers * redefine xdc_FILE__ to be NULL, unless xdc_FILE is defined. If xdc_FILE * is defined, xdc-FILE__ has the same value assigned to xdc_FILE. So, by * default, Error and Asserts in modules do *not* provide a file name. * * Since this header is included in all module public headers, "non-module" * clients of Error and Assert *will*, by default, provide a file name * string. To eliminate these embedded strings, add the following line * before all module headers: * #define xdc_FILE NULL * * Module creators may opt to define xdc_FILE as the string to use in * Error and Assert messages. For example, adding the following line * to a module's implementation (before the inclusion of the module's * internal header) will cause the standard __FILE__ to be * used in lieu of NULL in Error and Assert calls: * #define xdc_FILE __FILE__ * */ /* * ======== xdc_LINE ======== * Standard file-line-number string for identifying a call site */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== Types__prologue.h ======== * Hand crafted definitions for Types.xdc */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== interface xdc.runtime.IModule ======== */ typedef struct xdc_runtime_IModule_Fxns__ xdc_runtime_IModule_Fxns__; typedef const struct xdc_runtime_IModule_Fxns__* xdc_runtime_IModule_Module; /* * ======== module xdc.runtime.Assert ======== */ /* * ======== module xdc.runtime.Core ======== */ typedef struct xdc_runtime_Core_ObjDesc xdc_runtime_Core_ObjDesc; /* * ======== module xdc.runtime.Defaults ======== */ /* * ======== module xdc.runtime.Diags ======== */ typedef struct xdc_runtime_Diags_DictElem xdc_runtime_Diags_DictElem; /* * ======== module xdc.runtime.Error ======== */ typedef struct xdc_runtime_Error_Data xdc_runtime_Error_Data; typedef struct xdc_runtime_Error_Block xdc_runtime_Error_Block; typedef struct xdc_runtime_Error_Module_State xdc_runtime_Error_Module_State; /* * ======== module xdc.runtime.Gate ======== */ /* * ======== interface xdc.runtime.IGateProvider ======== */ typedef struct xdc_runtime_IGateProvider_Fxns__ xdc_runtime_IGateProvider_Fxns__; typedef const struct xdc_runtime_IGateProvider_Fxns__* xdc_runtime_IGateProvider_Module; typedef struct xdc_runtime_IGateProvider_Params xdc_runtime_IGateProvider_Params; typedef struct xdc_runtime_IGateProvider___Object { xdc_runtime_IGateProvider_Fxns__* __fxns; xdc_Bits32 __label; } *xdc_runtime_IGateProvider_Handle; /* * ======== module xdc.runtime.GateNull ======== */ typedef struct xdc_runtime_GateNull_Fxns__ xdc_runtime_GateNull_Fxns__; typedef const struct xdc_runtime_GateNull_Fxns__* xdc_runtime_GateNull_Module; typedef struct xdc_runtime_GateNull_Params xdc_runtime_GateNull_Params; typedef struct xdc_runtime_GateNull_Object xdc_runtime_GateNull_Object; typedef struct xdc_runtime_GateNull_Struct xdc_runtime_GateNull_Struct; typedef xdc_runtime_GateNull_Object* xdc_runtime_GateNull_Handle; typedef struct xdc_runtime_GateNull_Object__ xdc_runtime_GateNull_Instance_State; typedef xdc_runtime_GateNull_Object* xdc_runtime_GateNull_Instance; /* * ======== module xdc.runtime.Log ======== */ typedef struct xdc_runtime_Log_EventRec xdc_runtime_Log_EventRec; /* * ======== interface xdc.runtime.ILogger ======== */ typedef struct xdc_runtime_ILogger_Fxns__ xdc_runtime_ILogger_Fxns__; typedef const struct xdc_runtime_ILogger_Fxns__* xdc_runtime_ILogger_Module; typedef struct xdc_runtime_ILogger_Params xdc_runtime_ILogger_Params; typedef struct xdc_runtime_ILogger___Object { xdc_runtime_ILogger_Fxns__* __fxns; xdc_Bits32 __label; } *xdc_runtime_ILogger_Handle; /* * ======== interface xdc.runtime.IFilterLogger ======== */ typedef struct xdc_runtime_IFilterLogger_Fxns__ xdc_runtime_IFilterLogger_Fxns__; typedef const struct xdc_runtime_IFilterLogger_Fxns__* xdc_runtime_IFilterLogger_Module; typedef struct xdc_runtime_IFilterLogger_Params xdc_runtime_IFilterLogger_Params; typedef struct xdc_runtime_IFilterLogger___Object { xdc_runtime_IFilterLogger_Fxns__* __fxns; xdc_Bits32 __label; } *xdc_runtime_IFilterLogger_Handle; /* * ======== module xdc.runtime.LoggerBuf ======== */ typedef struct xdc_runtime_LoggerBuf_Entry xdc_runtime_LoggerBuf_Entry; typedef struct xdc_runtime_LoggerBuf_Module_State xdc_runtime_LoggerBuf_Module_State; typedef struct xdc_runtime_LoggerBuf_Fxns__ xdc_runtime_LoggerBuf_Fxns__; typedef const struct xdc_runtime_LoggerBuf_Fxns__* xdc_runtime_LoggerBuf_Module; typedef struct xdc_runtime_LoggerBuf_Params xdc_runtime_LoggerBuf_Params; typedef struct xdc_runtime_LoggerBuf_Object xdc_runtime_LoggerBuf_Object; typedef struct xdc_runtime_LoggerBuf_Struct xdc_runtime_LoggerBuf_Struct; typedef xdc_runtime_LoggerBuf_Object* xdc_runtime_LoggerBuf_Handle; typedef struct xdc_runtime_LoggerBuf_Object__ xdc_runtime_LoggerBuf_Instance_State; typedef xdc_runtime_LoggerBuf_Object* xdc_runtime_LoggerBuf_Instance; /* * ======== module xdc.runtime.LoggerCallback ======== */ typedef struct xdc_runtime_LoggerCallback_Fxns__ xdc_runtime_LoggerCallback_Fxns__; typedef const struct xdc_runtime_LoggerCallback_Fxns__* xdc_runtime_LoggerCallback_Module; typedef struct xdc_runtime_LoggerCallback_Params xdc_runtime_LoggerCallback_Params; typedef struct xdc_runtime_LoggerCallback_Object xdc_runtime_LoggerCallback_Object; typedef struct xdc_runtime_LoggerCallback_Struct xdc_runtime_LoggerCallback_Struct; typedef xdc_runtime_LoggerCallback_Object* xdc_runtime_LoggerCallback_Handle; typedef struct xdc_runtime_LoggerCallback_Object__ xdc_runtime_LoggerCallback_Instance_State; typedef xdc_runtime_LoggerCallback_Object* xdc_runtime_LoggerCallback_Instance; /* * ======== module xdc.runtime.LoggerSys ======== */ typedef struct xdc_runtime_LoggerSys_Fxns__ xdc_runtime_LoggerSys_Fxns__; typedef const struct xdc_runtime_LoggerSys_Fxns__* xdc_runtime_LoggerSys_Module; typedef struct xdc_runtime_LoggerSys_Params xdc_runtime_LoggerSys_Params; typedef struct xdc_runtime_LoggerSys_Object xdc_runtime_LoggerSys_Object; typedef struct xdc_runtime_LoggerSys_Struct xdc_runtime_LoggerSys_Struct; typedef xdc_runtime_LoggerSys_Object* xdc_runtime_LoggerSys_Handle; typedef struct xdc_runtime_LoggerSys_Object__ xdc_runtime_LoggerSys_Instance_State; typedef xdc_runtime_LoggerSys_Object* xdc_runtime_LoggerSys_Instance; /* * ======== module xdc.runtime.Main ======== */ /* * ======== module xdc.runtime.Memory ======== */ typedef struct xdc_runtime_Memory_Stats xdc_runtime_Memory_Stats; typedef struct xdc_runtime_Memory_Module_State xdc_runtime_Memory_Module_State; /* * ======== interface xdc.runtime.IHeap ======== */ typedef struct xdc_runtime_IHeap_Fxns__ xdc_runtime_IHeap_Fxns__; typedef const struct xdc_runtime_IHeap_Fxns__* xdc_runtime_IHeap_Module; typedef struct xdc_runtime_IHeap_Params xdc_runtime_IHeap_Params; typedef struct xdc_runtime_IHeap___Object { xdc_runtime_IHeap_Fxns__* __fxns; xdc_Bits32 __label; } *xdc_runtime_IHeap_Handle; /* * ======== module xdc.runtime.HeapMin ======== */ typedef struct xdc_runtime_HeapMin_Fxns__ xdc_runtime_HeapMin_Fxns__; typedef const struct xdc_runtime_HeapMin_Fxns__* xdc_runtime_HeapMin_Module; typedef struct xdc_runtime_HeapMin_Params xdc_runtime_HeapMin_Params; typedef struct xdc_runtime_HeapMin_Object xdc_runtime_HeapMin_Object; typedef struct xdc_runtime_HeapMin_Struct xdc_runtime_HeapMin_Struct; typedef xdc_runtime_HeapMin_Object* xdc_runtime_HeapMin_Handle; typedef struct xdc_runtime_HeapMin_Object__ xdc_runtime_HeapMin_Instance_State; typedef xdc_runtime_HeapMin_Object* xdc_runtime_HeapMin_Instance; /* * ======== module xdc.runtime.HeapStd ======== */ typedef struct xdc_runtime_HeapStd_Module_State xdc_runtime_HeapStd_Module_State; typedef struct xdc_runtime_HeapStd_Fxns__ xdc_runtime_HeapStd_Fxns__; typedef const struct xdc_runtime_HeapStd_Fxns__* xdc_runtime_HeapStd_Module; typedef struct xdc_runtime_HeapStd_Params xdc_runtime_HeapStd_Params; typedef struct xdc_runtime_HeapStd_Object xdc_runtime_HeapStd_Object; typedef struct xdc_runtime_HeapStd_Struct xdc_runtime_HeapStd_Struct; typedef xdc_runtime_HeapStd_Object* xdc_runtime_HeapStd_Handle; typedef struct xdc_runtime_HeapStd_Object__ xdc_runtime_HeapStd_Instance_State; typedef xdc_runtime_HeapStd_Object* xdc_runtime_HeapStd_Instance; /* * ======== module xdc.runtime.Registry ======== */ typedef struct xdc_runtime_Registry_Module_State xdc_runtime_Registry_Module_State; /* * ======== module xdc.runtime.Rta ======== */ typedef struct xdc_runtime_Rta_CommandPacket xdc_runtime_Rta_CommandPacket; typedef struct xdc_runtime_Rta_ResponsePacket xdc_runtime_Rta_ResponsePacket; /* * ======== module xdc.runtime.Startup ======== */ typedef struct xdc_runtime_Startup_IdMap xdc_runtime_Startup_IdMap; typedef struct xdc_runtime_Startup_Module_State xdc_runtime_Startup_Module_State; /* * ======== module xdc.runtime.System ======== */ typedef struct xdc_runtime_System_ParseData xdc_runtime_System_ParseData; typedef struct xdc_runtime_System_Module_State xdc_runtime_System_Module_State; /* * ======== interface xdc.runtime.ISystemSupport ======== */ typedef struct xdc_runtime_ISystemSupport_Fxns__ xdc_runtime_ISystemSupport_Fxns__; typedef const struct xdc_runtime_ISystemSupport_Fxns__* xdc_runtime_ISystemSupport_Module; /* * ======== module xdc.runtime.SysCallback ======== */ typedef struct xdc_runtime_SysCallback_Fxns__ xdc_runtime_SysCallback_Fxns__; typedef const struct xdc_runtime_SysCallback_Fxns__* xdc_runtime_SysCallback_Module; /* * ======== module xdc.runtime.SysMin ======== */ typedef struct xdc_runtime_SysMin_Module_State xdc_runtime_SysMin_Module_State; typedef struct xdc_runtime_SysMin_Fxns__ xdc_runtime_SysMin_Fxns__; typedef const struct xdc_runtime_SysMin_Fxns__* xdc_runtime_SysMin_Module; /* * ======== module xdc.runtime.SysStd ======== */ typedef struct xdc_runtime_SysStd_Fxns__ xdc_runtime_SysStd_Fxns__; typedef const struct xdc_runtime_SysStd_Fxns__* xdc_runtime_SysStd_Module; /* * ======== module xdc.runtime.Text ======== */ typedef struct xdc_runtime_Text_Node xdc_runtime_Text_Node; typedef struct xdc_runtime_Text_MatchVisState xdc_runtime_Text_MatchVisState; typedef struct xdc_runtime_Text_PrintVisState xdc_runtime_Text_PrintVisState; typedef struct xdc_runtime_Text_Module_State xdc_runtime_Text_Module_State; /* * ======== interface xdc.runtime.ITimestampClient ======== */ typedef struct xdc_runtime_ITimestampClient_Fxns__ xdc_runtime_ITimestampClient_Fxns__; typedef const struct xdc_runtime_ITimestampClient_Fxns__* xdc_runtime_ITimestampClient_Module; /* * ======== module xdc.runtime.Timestamp ======== */ typedef struct xdc_runtime_Timestamp_Fxns__ xdc_runtime_Timestamp_Fxns__; typedef const struct xdc_runtime_Timestamp_Fxns__* xdc_runtime_Timestamp_Module; /* * ======== interface xdc.runtime.ITimestampProvider ======== */ typedef struct xdc_runtime_ITimestampProvider_Fxns__ xdc_runtime_ITimestampProvider_Fxns__; typedef const struct xdc_runtime_ITimestampProvider_Fxns__* xdc_runtime_ITimestampProvider_Module; /* * ======== module xdc.runtime.TimestampNull ======== */ typedef struct xdc_runtime_TimestampNull_Fxns__ xdc_runtime_TimestampNull_Fxns__; typedef const struct xdc_runtime_TimestampNull_Fxns__* xdc_runtime_TimestampNull_Module; /* * ======== module xdc.runtime.TimestampStd ======== */ typedef struct xdc_runtime_TimestampStd_Fxns__ xdc_runtime_TimestampStd_Fxns__; typedef const struct xdc_runtime_TimestampStd_Fxns__* xdc_runtime_TimestampStd_Module; /* * ======== module xdc.runtime.Types ======== */ typedef struct xdc_runtime_Types_CordAddr__ xdc_runtime_Types_CordAddr__; typedef struct xdc_runtime_Types_GateRef__ xdc_runtime_Types_GateRef__; typedef struct xdc_runtime_Types_Label xdc_runtime_Types_Label; typedef struct xdc_runtime_Types_Site xdc_runtime_Types_Site; typedef struct xdc_runtime_Types_Timestamp64 xdc_runtime_Types_Timestamp64; typedef struct xdc_runtime_Types_FreqHz xdc_runtime_Types_FreqHz; typedef struct xdc_runtime_Types_RegDesc xdc_runtime_Types_RegDesc; typedef struct xdc_runtime_Types_Vec xdc_runtime_Types_Vec; typedef struct xdc_runtime_Types_Link xdc_runtime_Types_Link; typedef struct xdc_runtime_Types_InstHdr xdc_runtime_Types_InstHdr; typedef struct xdc_runtime_Types_PrmsHdr xdc_runtime_Types_PrmsHdr; typedef struct xdc_runtime_Types_Base xdc_runtime_Types_Base; typedef struct xdc_runtime_Types_SysFxns2 xdc_runtime_Types_SysFxns2; /* * ======== interface xdc.runtime.IInstance ======== */ typedef struct xdc_runtime_IInstance_Fxns__ xdc_runtime_IInstance_Fxns__; typedef const struct xdc_runtime_IInstance_Fxns__* xdc_runtime_IInstance_Module; typedef struct xdc_runtime_IInstance_Params xdc_runtime_IInstance_Params; typedef struct xdc_runtime_IInstance___Object { xdc_runtime_IInstance_Fxns__* __fxns; xdc_Bits32 __label; } *xdc_runtime_IInstance_Handle; /* * ======== module xdc.runtime.LoggerBuf_TimestampProxy ======== */ typedef struct xdc_runtime_LoggerBuf_TimestampProxy_Fxns__ xdc_runtime_LoggerBuf_TimestampProxy_Fxns__; typedef const struct xdc_runtime_LoggerBuf_TimestampProxy_Fxns__* xdc_runtime_LoggerBuf_TimestampProxy_Module; /* * ======== module xdc.runtime.LoggerBuf_Module_GateProxy ======== */ typedef struct xdc_runtime_LoggerBuf_Module_GateProxy_Fxns__ xdc_runtime_LoggerBuf_Module_GateProxy_Fxns__; typedef const struct xdc_runtime_LoggerBuf_Module_GateProxy_Fxns__* xdc_runtime_LoggerBuf_Module_GateProxy_Module; typedef struct xdc_runtime_LoggerBuf_Module_GateProxy_Params xdc_runtime_LoggerBuf_Module_GateProxy_Params; typedef struct xdc_runtime_IGateProvider___Object *xdc_runtime_LoggerBuf_Module_GateProxy_Handle; /* * ======== module xdc.runtime.LoggerSys_TimestampProxy ======== */ typedef struct xdc_runtime_LoggerSys_TimestampProxy_Fxns__ xdc_runtime_LoggerSys_TimestampProxy_Fxns__; typedef const struct xdc_runtime_LoggerSys_TimestampProxy_Fxns__* xdc_runtime_LoggerSys_TimestampProxy_Module; /* * ======== module xdc.runtime.Main_Module_GateProxy ======== */ typedef struct xdc_runtime_Main_Module_GateProxy_Fxns__ xdc_runtime_Main_Module_GateProxy_Fxns__; typedef const struct xdc_runtime_Main_Module_GateProxy_Fxns__* xdc_runtime_Main_Module_GateProxy_Module; typedef struct xdc_runtime_Main_Module_GateProxy_Params xdc_runtime_Main_Module_GateProxy_Params; typedef struct xdc_runtime_IGateProvider___Object *xdc_runtime_Main_Module_GateProxy_Handle; /* * ======== module xdc.runtime.Memory_HeapProxy ======== */ typedef struct xdc_runtime_Memory_HeapProxy_Fxns__ xdc_runtime_Memory_HeapProxy_Fxns__; typedef const struct xdc_runtime_Memory_HeapProxy_Fxns__* xdc_runtime_Memory_HeapProxy_Module; typedef struct xdc_runtime_Memory_HeapProxy_Params xdc_runtime_Memory_HeapProxy_Params; typedef struct xdc_runtime_IHeap___Object *xdc_runtime_Memory_HeapProxy_Handle; /* * ======== module xdc.runtime.System_SupportProxy ======== */ typedef struct xdc_runtime_System_SupportProxy_Fxns__ xdc_runtime_System_SupportProxy_Fxns__; typedef const struct xdc_runtime_System_SupportProxy_Fxns__* xdc_runtime_System_SupportProxy_Module; /* * ======== module xdc.runtime.System_Module_GateProxy ======== */ typedef struct xdc_runtime_System_Module_GateProxy_Fxns__ xdc_runtime_System_Module_GateProxy_Fxns__; typedef const struct xdc_runtime_System_Module_GateProxy_Fxns__* xdc_runtime_System_Module_GateProxy_Module; typedef struct xdc_runtime_System_Module_GateProxy_Params xdc_runtime_System_Module_GateProxy_Params; typedef struct xdc_runtime_IGateProvider___Object *xdc_runtime_System_Module_GateProxy_Handle; /* * ======== module xdc.runtime.Timestamp_SupportProxy ======== */ typedef struct xdc_runtime_Timestamp_SupportProxy_Fxns__ xdc_runtime_Timestamp_SupportProxy_Fxns__; typedef const struct xdc_runtime_Timestamp_SupportProxy_Fxns__* xdc_runtime_Timestamp_SupportProxy_Module; /* * ======== AUXILIARY DEFINITIONS ======== */ /* ModuleId */ typedef xdc_Bits16 xdc_runtime_Types_ModuleId; /* DiagsMask */ typedef xdc_Bits16 xdc_runtime_Types_DiagsMask; /* Event */ typedef xdc_Bits32 xdc_runtime_Types_Event; /* EventId */ typedef xdc_runtime_Types_Event xdc_runtime_Types_EventId; /* CordAddr__ */ struct xdc_runtime_Types_CordAddr__; /* CordAddr */ typedef xdc_runtime_Types_CordAddr__ *xdc_runtime_Types_CordAddr; /* GateRef__ */ struct xdc_runtime_Types_GateRef__; /* GateRef */ typedef xdc_runtime_Types_GateRef__ *xdc_runtime_Types_GateRef; /* RopeId */ typedef xdc_Bits16 xdc_runtime_Types_RopeId; /* CreatePolicy */ enum xdc_runtime_Types_CreatePolicy { xdc_runtime_Types_STATIC_POLICY, xdc_runtime_Types_CREATE_POLICY, xdc_runtime_Types_DELETE_POLICY }; typedef enum xdc_runtime_Types_CreatePolicy xdc_runtime_Types_CreatePolicy; /* OutputPolicy */ enum xdc_runtime_Types_OutputPolicy { xdc_runtime_Types_COMMON_FILE, xdc_runtime_Types_SEPARATE_FILE, xdc_runtime_Types_NO_FILE }; typedef enum xdc_runtime_Types_OutputPolicy xdc_runtime_Types_OutputPolicy; /* Label */ struct xdc_runtime_Types_Label { xdc_Ptr handle; xdc_runtime_Types_ModuleId modId; xdc_String iname; xdc_Bool named; }; /* Site */ struct xdc_runtime_Types_Site { xdc_runtime_Types_ModuleId mod; xdc_CString file; xdc_Int line; }; /* Timestamp64 */ struct xdc_runtime_Types_Timestamp64 { xdc_Bits32 hi; xdc_Bits32 lo; }; /* FreqHz */ struct xdc_runtime_Types_FreqHz { xdc_Bits32 hi; xdc_Bits32 lo; }; /* RegDesc */ struct xdc_runtime_Types_RegDesc { xdc_runtime_Types_RegDesc *next; xdc_CString modName; xdc_runtime_Types_ModuleId id; xdc_runtime_Types_DiagsMask mask; }; /* * ======== INTERNAL DEFINITIONS ======== */ /* LogEvent */ typedef xdc_Bits32 xdc_runtime_Types_LogEvent; /* LoggerFxn0 */ typedef void (*xdc_runtime_Types_LoggerFxn0)(xdc_Ptr arg1, xdc_runtime_Types_LogEvent arg2, xdc_runtime_Types_ModuleId arg3); /* LoggerFxn1 */ typedef void (*xdc_runtime_Types_LoggerFxn1)(xdc_Ptr arg1, xdc_runtime_Types_LogEvent arg2, xdc_runtime_Types_ModuleId arg3, xdc_IArg arg4); /* LoggerFxn2 */ typedef void (*xdc_runtime_Types_LoggerFxn2)(xdc_Ptr arg1, xdc_runtime_Types_LogEvent arg2, xdc_runtime_Types_ModuleId arg3, xdc_IArg arg4, xdc_IArg arg5); /* LoggerFxn4 */ typedef void (*xdc_runtime_Types_LoggerFxn4)(xdc_Ptr arg1, xdc_runtime_Types_LogEvent arg2, xdc_runtime_Types_ModuleId arg3, xdc_IArg arg4, xdc_IArg arg5, xdc_IArg arg6, xdc_IArg arg7); /* LoggerFxn8 */ typedef void (*xdc_runtime_Types_LoggerFxn8)(xdc_Ptr arg1, xdc_runtime_Types_LogEvent arg2, xdc_runtime_Types_ModuleId arg3, xdc_IArg arg4, xdc_IArg arg5, xdc_IArg arg6, xdc_IArg arg7, xdc_IArg arg8, xdc_IArg arg9, xdc_IArg arg10, xdc_IArg arg11); /* Vec */ struct xdc_runtime_Types_Vec { xdc_Int len; xdc_Ptr arr; }; /* Link */ struct xdc_runtime_Types_Link { xdc_runtime_Types_Link *next; xdc_runtime_Types_Link *prev; }; /* InstHdr */ struct xdc_runtime_Types_InstHdr { xdc_runtime_Types_Link link; }; /* PrmsHdr */ struct xdc_runtime_Types_PrmsHdr { xdc_SizeT size; xdc_Ptr self; xdc_Ptr modFxns; xdc_Ptr instPrms; }; /* Base */ struct xdc_runtime_Types_Base { const xdc_runtime_Types_Base *base; }; /* SysFxns2 */ struct xdc_runtime_Types_SysFxns2 { xdc_Ptr (*__create)(xdc_CPtr arg1, const xdc_UChar* arg2, xdc_SizeT arg3, xdc_runtime_Error_Block* arg4); void (*__delete)(xdc_Ptr arg1); xdc_runtime_Types_Label *(*__label)(xdc_Ptr arg1, xdc_runtime_Types_Label* arg2); xdc_runtime_Types_ModuleId __mid; }; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Types_Module__diagsEnabled; extern const CT__xdc_runtime_Types_Module__diagsEnabled xdc_runtime_Types_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Types_Module__diagsIncluded; extern const CT__xdc_runtime_Types_Module__diagsIncluded xdc_runtime_Types_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Types_Module__diagsMask; extern const CT__xdc_runtime_Types_Module__diagsMask xdc_runtime_Types_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Types_Module__gateObj; extern const CT__xdc_runtime_Types_Module__gateObj xdc_runtime_Types_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Types_Module__gatePrms; extern const CT__xdc_runtime_Types_Module__gatePrms xdc_runtime_Types_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Types_Module__id; extern const CT__xdc_runtime_Types_Module__id xdc_runtime_Types_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Types_Module__loggerDefined; extern const CT__xdc_runtime_Types_Module__loggerDefined xdc_runtime_Types_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Types_Module__loggerObj; extern const CT__xdc_runtime_Types_Module__loggerObj xdc_runtime_Types_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Types_Module__loggerFxn0; extern const CT__xdc_runtime_Types_Module__loggerFxn0 xdc_runtime_Types_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Types_Module__loggerFxn1; extern const CT__xdc_runtime_Types_Module__loggerFxn1 xdc_runtime_Types_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Types_Module__loggerFxn2; extern const CT__xdc_runtime_Types_Module__loggerFxn2 xdc_runtime_Types_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Types_Module__loggerFxn4; extern const CT__xdc_runtime_Types_Module__loggerFxn4 xdc_runtime_Types_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Types_Module__loggerFxn8; extern const CT__xdc_runtime_Types_Module__loggerFxn8 xdc_runtime_Types_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Types_Object__count; extern const CT__xdc_runtime_Types_Object__count xdc_runtime_Types_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Types_Object__heap; extern const CT__xdc_runtime_Types_Object__heap xdc_runtime_Types_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Types_Object__sizeof; extern const CT__xdc_runtime_Types_Object__sizeof xdc_runtime_Types_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Types_Object__table; extern const CT__xdc_runtime_Types_Object__table xdc_runtime_Types_Object__table__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Types_Module__startupDone__S( void ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Types_Module__id xdc_runtime_Types_Module_id(void); static inline CT__xdc_runtime_Types_Module__id xdc_runtime_Types_Module_id( void ) { return xdc_runtime_Types_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Types_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Types_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Types_Module__diagsMask__C != (CT__xdc_runtime_Types_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Types_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Types_Module_getMask(void) { return (xdc_runtime_Types_Module__diagsMask__C != (CT__xdc_runtime_Types_Module__diagsMask)0) ? *xdc_runtime_Types_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Types_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Types_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Types_Module__diagsMask__C != (CT__xdc_runtime_Types_Module__diagsMask)0) { *xdc_runtime_Types_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== Types__epilogue.h ======== * Hand crafted macros for Types.xdc */ /* * ======== xdc_runtime_Types_getEventId ======== */ /* * ======== xdc_runtime_Types_makeEvent ======== */ /* * ======== xdc_runtime_Types_getModuleId ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct xdc_runtime_IInstance_Params { size_t __size; xdc_CString name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_IInstance_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base xdc_runtime_IInstance_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* create */ extern xdc_runtime_IInstance_Handle xdc_runtime_IInstance_create(xdc_runtime_IInstance_Module mod, const xdc_runtime_IInstance_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void xdc_runtime_IInstance_delete(xdc_runtime_IInstance_Handle *inst); /* Handle_to_Module */ static inline xdc_runtime_IInstance_Module xdc_runtime_IInstance_Handle_to_Module(xdc_runtime_IInstance_Handle inst); static inline xdc_runtime_IInstance_Module xdc_runtime_IInstance_Handle_to_Module(xdc_runtime_IInstance_Handle inst) { return inst->__fxns; } /* Handle_label */ static inline xdc_runtime_Types_Label *xdc_runtime_IInstance_Handle_label(xdc_runtime_IInstance_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *xdc_runtime_IInstance_Handle_label(xdc_runtime_IInstance_Handle inst, xdc_runtime_Types_Label *lab) { return inst->__fxns->__sysp->__label(inst, lab); } /* Module_id */ static inline xdc_runtime_Types_ModuleId xdc_runtime_IInstance_Module_id(xdc_runtime_IInstance_Module mod); static inline xdc_runtime_Types_ModuleId xdc_runtime_IInstance_Module_id(xdc_runtime_IInstance_Module mod) { return mod->__sysp->__mid; } /* * ======== FUNCTION SELECTORS ======== */ /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.heaps.HeapBuf ======== */ typedef struct ti_sysbios_heaps_HeapBuf_ExtendedStats ti_sysbios_heaps_HeapBuf_ExtendedStats; typedef struct ti_sysbios_heaps_HeapBuf_Module_State ti_sysbios_heaps_HeapBuf_Module_State; typedef struct ti_sysbios_heaps_HeapBuf_Fxns__ ti_sysbios_heaps_HeapBuf_Fxns__; typedef const struct ti_sysbios_heaps_HeapBuf_Fxns__* ti_sysbios_heaps_HeapBuf_Module; typedef struct ti_sysbios_heaps_HeapBuf_Params ti_sysbios_heaps_HeapBuf_Params; typedef struct ti_sysbios_heaps_HeapBuf_Object ti_sysbios_heaps_HeapBuf_Object; typedef struct ti_sysbios_heaps_HeapBuf_Struct ti_sysbios_heaps_HeapBuf_Struct; typedef ti_sysbios_heaps_HeapBuf_Object* ti_sysbios_heaps_HeapBuf_Handle; typedef struct ti_sysbios_heaps_HeapBuf_Object__ ti_sysbios_heaps_HeapBuf_Instance_State; typedef ti_sysbios_heaps_HeapBuf_Object* ti_sysbios_heaps_HeapBuf_Instance; /* * ======== module ti.sysbios.heaps.HeapMem ======== */ typedef struct ti_sysbios_heaps_HeapMem_ExtendedStats ti_sysbios_heaps_HeapMem_ExtendedStats; typedef struct ti_sysbios_heaps_HeapMem_Header ti_sysbios_heaps_HeapMem_Header; typedef struct ti_sysbios_heaps_HeapMem_Fxns__ ti_sysbios_heaps_HeapMem_Fxns__; typedef const struct ti_sysbios_heaps_HeapMem_Fxns__* ti_sysbios_heaps_HeapMem_Module; typedef struct ti_sysbios_heaps_HeapMem_Params ti_sysbios_heaps_HeapMem_Params; typedef struct ti_sysbios_heaps_HeapMem_Object ti_sysbios_heaps_HeapMem_Object; typedef struct ti_sysbios_heaps_HeapMem_Struct ti_sysbios_heaps_HeapMem_Struct; typedef ti_sysbios_heaps_HeapMem_Object* ti_sysbios_heaps_HeapMem_Handle; typedef struct ti_sysbios_heaps_HeapMem_Object__ ti_sysbios_heaps_HeapMem_Instance_State; typedef ti_sysbios_heaps_HeapMem_Object* ti_sysbios_heaps_HeapMem_Instance; /* * ======== module ti.sysbios.heaps.HeapMultiBuf ======== */ typedef struct ti_sysbios_heaps_HeapMultiBuf_AddrPair ti_sysbios_heaps_HeapMultiBuf_AddrPair; typedef struct ti_sysbios_heaps_HeapMultiBuf_Fxns__ ti_sysbios_heaps_HeapMultiBuf_Fxns__; typedef const struct ti_sysbios_heaps_HeapMultiBuf_Fxns__* ti_sysbios_heaps_HeapMultiBuf_Module; typedef struct ti_sysbios_heaps_HeapMultiBuf_Params ti_sysbios_heaps_HeapMultiBuf_Params; typedef struct ti_sysbios_heaps_HeapMultiBuf_Object ti_sysbios_heaps_HeapMultiBuf_Object; typedef struct ti_sysbios_heaps_HeapMultiBuf_Struct ti_sysbios_heaps_HeapMultiBuf_Struct; typedef ti_sysbios_heaps_HeapMultiBuf_Object* ti_sysbios_heaps_HeapMultiBuf_Handle; typedef struct ti_sysbios_heaps_HeapMultiBuf_Object__ ti_sysbios_heaps_HeapMultiBuf_Instance_State; typedef ti_sysbios_heaps_HeapMultiBuf_Object* ti_sysbios_heaps_HeapMultiBuf_Instance; /* * ======== module ti.sysbios.heaps.HeapNull ======== */ typedef struct ti_sysbios_heaps_HeapNull_Fxns__ ti_sysbios_heaps_HeapNull_Fxns__; typedef const struct ti_sysbios_heaps_HeapNull_Fxns__* ti_sysbios_heaps_HeapNull_Module; typedef struct ti_sysbios_heaps_HeapNull_Params ti_sysbios_heaps_HeapNull_Params; typedef struct ti_sysbios_heaps_HeapNull_Object ti_sysbios_heaps_HeapNull_Object; typedef struct ti_sysbios_heaps_HeapNull_Struct ti_sysbios_heaps_HeapNull_Struct; typedef ti_sysbios_heaps_HeapNull_Object* ti_sysbios_heaps_HeapNull_Handle; typedef struct ti_sysbios_heaps_HeapNull_Object__ ti_sysbios_heaps_HeapNull_Instance_State; typedef ti_sysbios_heaps_HeapNull_Object* ti_sysbios_heaps_HeapNull_Instance; /* * ======== module ti.sysbios.heaps.HeapTrack ======== */ typedef struct ti_sysbios_heaps_HeapTrack_Tracker ti_sysbios_heaps_HeapTrack_Tracker; typedef struct ti_sysbios_heaps_HeapTrack_Fxns__ ti_sysbios_heaps_HeapTrack_Fxns__; typedef const struct ti_sysbios_heaps_HeapTrack_Fxns__* ti_sysbios_heaps_HeapTrack_Module; typedef struct ti_sysbios_heaps_HeapTrack_Params ti_sysbios_heaps_HeapTrack_Params; typedef struct ti_sysbios_heaps_HeapTrack_Object ti_sysbios_heaps_HeapTrack_Object; typedef struct ti_sysbios_heaps_HeapTrack_Struct ti_sysbios_heaps_HeapTrack_Struct; typedef ti_sysbios_heaps_HeapTrack_Object* ti_sysbios_heaps_HeapTrack_Handle; typedef struct ti_sysbios_heaps_HeapTrack_Object__ ti_sysbios_heaps_HeapTrack_Instance_State; typedef ti_sysbios_heaps_HeapTrack_Object* ti_sysbios_heaps_HeapTrack_Instance; /* * ======== module ti.sysbios.heaps.HeapCallback ======== */ typedef struct ti_sysbios_heaps_HeapCallback_Fxns__ ti_sysbios_heaps_HeapCallback_Fxns__; typedef const struct ti_sysbios_heaps_HeapCallback_Fxns__* ti_sysbios_heaps_HeapCallback_Module; typedef struct ti_sysbios_heaps_HeapCallback_Params ti_sysbios_heaps_HeapCallback_Params; typedef struct ti_sysbios_heaps_HeapCallback_Object ti_sysbios_heaps_HeapCallback_Object; typedef struct ti_sysbios_heaps_HeapCallback_Struct ti_sysbios_heaps_HeapCallback_Struct; typedef ti_sysbios_heaps_HeapCallback_Object* ti_sysbios_heaps_HeapCallback_Handle; typedef struct ti_sysbios_heaps_HeapCallback_Object__ ti_sysbios_heaps_HeapCallback_Instance_State; typedef ti_sysbios_heaps_HeapCallback_Object* ti_sysbios_heaps_HeapCallback_Instance; /* * ======== module ti.sysbios.heaps.HeapMem_Module_GateProxy ======== */ typedef struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Fxns__ ti_sysbios_heaps_HeapMem_Module_GateProxy_Fxns__; typedef const struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Fxns__* ti_sysbios_heaps_HeapMem_Module_GateProxy_Module; typedef struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Params ti_sysbios_heaps_HeapMem_Module_GateProxy_Params; typedef struct xdc_runtime_IGateProvider___Object *ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Q_BLOCKING */ /* Q_PREEMPTING */ /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct xdc_runtime_IGateProvider_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_IGateProvider_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*query)(xdc_Int qual); xdc_IArg (*enter)(void* inst); void (*leave)(void* inst, xdc_IArg key); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base xdc_runtime_IGateProvider_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* create */ extern xdc_runtime_IGateProvider_Handle xdc_runtime_IGateProvider_create(xdc_runtime_IGateProvider_Module mod, const xdc_runtime_IGateProvider_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void xdc_runtime_IGateProvider_delete(xdc_runtime_IGateProvider_Handle *inst); /* Handle_to_Module */ static inline xdc_runtime_IGateProvider_Module xdc_runtime_IGateProvider_Handle_to_Module(xdc_runtime_IGateProvider_Handle inst); static inline xdc_runtime_IGateProvider_Module xdc_runtime_IGateProvider_Handle_to_Module(xdc_runtime_IGateProvider_Handle inst) { return inst->__fxns; } /* Handle_label */ static inline xdc_runtime_Types_Label *xdc_runtime_IGateProvider_Handle_label(xdc_runtime_IGateProvider_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *xdc_runtime_IGateProvider_Handle_label(xdc_runtime_IGateProvider_Handle inst, xdc_runtime_Types_Label *lab) { return inst->__fxns->__sysp->__label(inst, lab); } /* Module_id */ static inline xdc_runtime_Types_ModuleId xdc_runtime_IGateProvider_Module_id(xdc_runtime_IGateProvider_Module mod); static inline xdc_runtime_Types_ModuleId xdc_runtime_IGateProvider_Module_id(xdc_runtime_IGateProvider_Module mod) { return mod->__sysp->__mid; } /* query */ static inline xdc_Bool xdc_runtime_IGateProvider_query(xdc_runtime_IGateProvider_Module mod, xdc_Int qual); static inline xdc_Bool xdc_runtime_IGateProvider_query( xdc_runtime_IGateProvider_Module mod, xdc_Int qual ) { return mod->query(qual); } /* enter */ static inline xdc_IArg xdc_runtime_IGateProvider_enter(xdc_runtime_IGateProvider_Handle inst); static inline xdc_IArg xdc_runtime_IGateProvider_enter( xdc_runtime_IGateProvider_Handle inst ) { return inst->__fxns->enter((void*)inst); } /* leave */ static inline void xdc_runtime_IGateProvider_leave(xdc_runtime_IGateProvider_Handle inst, xdc_IArg key); static inline void xdc_runtime_IGateProvider_leave( xdc_runtime_IGateProvider_Handle inst, xdc_IArg key ) { inst->__fxns->leave((void*)inst, key); } /* * ======== FUNCTION SELECTORS ======== */ /* These functions return function pointers for module and instance functions. * The functions accept modules and instances declared as types defined in this * interface, but they return functions defined for the actual objects passed * as parameters. These functions are not invoked by any generated code or * XDCtools internal code. */ /* query_{FxnT,fxnP} */ typedef xdc_Bool (*xdc_runtime_IGateProvider_query_FxnT)(xdc_Int qual); static inline xdc_runtime_IGateProvider_query_FxnT xdc_runtime_IGateProvider_query_fxnP(xdc_runtime_IGateProvider_Module mod); static inline xdc_runtime_IGateProvider_query_FxnT xdc_runtime_IGateProvider_query_fxnP(xdc_runtime_IGateProvider_Module mod) { return (xdc_runtime_IGateProvider_query_FxnT)mod->query; } /* enter_{FxnT,fxnP} */ typedef xdc_IArg (*xdc_runtime_IGateProvider_enter_FxnT)(void *inst); static inline xdc_runtime_IGateProvider_enter_FxnT xdc_runtime_IGateProvider_enter_fxnP(xdc_runtime_IGateProvider_Handle inst); static inline xdc_runtime_IGateProvider_enter_FxnT xdc_runtime_IGateProvider_enter_fxnP(xdc_runtime_IGateProvider_Handle inst) { return (xdc_runtime_IGateProvider_enter_FxnT)inst->__fxns->enter; } /* leave_{FxnT,fxnP} */ typedef void (*xdc_runtime_IGateProvider_leave_FxnT)(void *inst, xdc_IArg key); static inline xdc_runtime_IGateProvider_leave_FxnT xdc_runtime_IGateProvider_leave_fxnP(xdc_runtime_IGateProvider_Handle inst); static inline xdc_runtime_IGateProvider_leave_FxnT xdc_runtime_IGateProvider_leave_fxnP(xdc_runtime_IGateProvider_Handle inst) { return (xdc_runtime_IGateProvider_leave_FxnT)inst->__fxns->leave; } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Q_BLOCKING */ /* Q_PREEMPTING */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Main_Module_GateProxy_Module__diagsEnabled; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__diagsEnabled xdc_runtime_Main_Module_GateProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Main_Module_GateProxy_Module__diagsIncluded; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__diagsIncluded xdc_runtime_Main_Module_GateProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Main_Module_GateProxy_Module__diagsMask; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__diagsMask xdc_runtime_Main_Module_GateProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Main_Module_GateProxy_Module__gateObj; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__gateObj xdc_runtime_Main_Module_GateProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Main_Module_GateProxy_Module__gatePrms; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__gatePrms xdc_runtime_Main_Module_GateProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Main_Module_GateProxy_Module__id; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__id xdc_runtime_Main_Module_GateProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Main_Module_GateProxy_Module__loggerDefined; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerDefined xdc_runtime_Main_Module_GateProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Main_Module_GateProxy_Module__loggerObj; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerObj xdc_runtime_Main_Module_GateProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn0; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn0 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn1; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn1 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn2; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn2 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn4; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn4 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn8; extern const CT__xdc_runtime_Main_Module_GateProxy_Module__loggerFxn8 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Main_Module_GateProxy_Object__count; extern const CT__xdc_runtime_Main_Module_GateProxy_Object__count xdc_runtime_Main_Module_GateProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Main_Module_GateProxy_Object__heap; extern const CT__xdc_runtime_Main_Module_GateProxy_Object__heap xdc_runtime_Main_Module_GateProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Main_Module_GateProxy_Object__sizeof; extern const CT__xdc_runtime_Main_Module_GateProxy_Object__sizeof xdc_runtime_Main_Module_GateProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Main_Module_GateProxy_Object__table; extern const CT__xdc_runtime_Main_Module_GateProxy_Object__table xdc_runtime_Main_Module_GateProxy_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct xdc_runtime_Main_Module_GateProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct xdc_runtime_Main_Module_GateProxy_Struct { const xdc_runtime_Main_Module_GateProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_Main_Module_GateProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*query)(xdc_Int qual); xdc_IArg (*enter)(xdc_runtime_Main_Module_GateProxy_Handle inst); void (*leave)(xdc_runtime_Main_Module_GateProxy_Handle inst, xdc_IArg key); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const xdc_runtime_Main_Module_GateProxy_Fxns__ xdc_runtime_Main_Module_GateProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern xdc_runtime_Main_Module_GateProxy_Handle xdc_runtime_Main_Module_GateProxy_create( const xdc_runtime_Main_Module_GateProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void xdc_runtime_Main_Module_GateProxy_delete(xdc_runtime_Main_Module_GateProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *xdc_runtime_Main_Module_GateProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Main_Module_GateProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr xdc_runtime_Main_Module_GateProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr xdc_runtime_Main_Module_GateProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr xdc_runtime_Main_Module_GateProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void xdc_runtime_Main_Module_GateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool xdc_runtime_Main_Module_GateProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr xdc_runtime_Main_Module_GateProxy_Proxy__delegate__S( void ); /* query__E */ extern xdc_Bool xdc_runtime_Main_Module_GateProxy_query__E( xdc_Int qual ); /* enter__E */ extern xdc_IArg xdc_runtime_Main_Module_GateProxy_enter__E( xdc_runtime_Main_Module_GateProxy_Handle __inst ); /* leave__E */ extern void xdc_runtime_Main_Module_GateProxy_leave__E( xdc_runtime_Main_Module_GateProxy_Handle __inst, xdc_IArg key ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IGateProvider_Module xdc_runtime_Main_Module_GateProxy_Module_upCast(void); static inline xdc_runtime_IGateProvider_Module xdc_runtime_Main_Module_GateProxy_Module_upCast(void) { return (xdc_runtime_IGateProvider_Module)xdc_runtime_Main_Module_GateProxy_Proxy__delegate__S(); } /* Module_to_xdc_runtime_IGateProvider */ /* Handle_upCast */ static inline xdc_runtime_IGateProvider_Handle xdc_runtime_Main_Module_GateProxy_Handle_upCast(xdc_runtime_Main_Module_GateProxy_Handle i); static inline xdc_runtime_IGateProvider_Handle xdc_runtime_Main_Module_GateProxy_Handle_upCast(xdc_runtime_Main_Module_GateProxy_Handle i) { return (xdc_runtime_IGateProvider_Handle)i; } /* Handle_to_xdc_runtime_IGateProvider */ /* Handle_downCast */ static inline xdc_runtime_Main_Module_GateProxy_Handle xdc_runtime_Main_Module_GateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i); static inline xdc_runtime_Main_Module_GateProxy_Handle xdc_runtime_Main_Module_GateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i) { xdc_runtime_IGateProvider_Handle i2 = (xdc_runtime_IGateProvider_Handle)i; if (xdc_runtime_Main_Module_GateProxy_Proxy__abstract__S()) { return (xdc_runtime_Main_Module_GateProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)xdc_runtime_Main_Module_GateProxy_Proxy__delegate__S()) ? (xdc_runtime_Main_Module_GateProxy_Handle)i : (xdc_runtime_Main_Module_GateProxy_Handle)0; } /* Handle_from_xdc_runtime_IGateProvider */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Main_Module_GateProxy_Module__id xdc_runtime_Main_Module_GateProxy_Module_id(void); static inline CT__xdc_runtime_Main_Module_GateProxy_Module__id xdc_runtime_Main_Module_GateProxy_Module_id( void ) { return xdc_runtime_Main_Module_GateProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void xdc_runtime_Main_Module_GateProxy_Params_init(xdc_runtime_Main_Module_GateProxy_Params *prms); static inline void xdc_runtime_Main_Module_GateProxy_Params_init( xdc_runtime_Main_Module_GateProxy_Params *prms ) { if (prms != 0) { xdc_runtime_Main_Module_GateProxy_Params__init__S(prms, 0, sizeof(xdc_runtime_Main_Module_GateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void xdc_runtime_Main_Module_GateProxy_Params_copy(xdc_runtime_Main_Module_GateProxy_Params *dst, const xdc_runtime_Main_Module_GateProxy_Params *src); static inline void xdc_runtime_Main_Module_GateProxy_Params_copy(xdc_runtime_Main_Module_GateProxy_Params *dst, const xdc_runtime_Main_Module_GateProxy_Params *src) { if (dst != 0) { xdc_runtime_Main_Module_GateProxy_Params__init__S(dst, (const void *)src, sizeof(xdc_runtime_Main_Module_GateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Main_Module__diagsEnabled; extern const CT__xdc_runtime_Main_Module__diagsEnabled xdc_runtime_Main_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Main_Module__diagsIncluded; extern const CT__xdc_runtime_Main_Module__diagsIncluded xdc_runtime_Main_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Main_Module__diagsMask; extern const CT__xdc_runtime_Main_Module__diagsMask xdc_runtime_Main_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Main_Module__gateObj; extern const CT__xdc_runtime_Main_Module__gateObj xdc_runtime_Main_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Main_Module__gatePrms; extern const CT__xdc_runtime_Main_Module__gatePrms xdc_runtime_Main_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Main_Module__id; extern const CT__xdc_runtime_Main_Module__id xdc_runtime_Main_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Main_Module__loggerDefined; extern const CT__xdc_runtime_Main_Module__loggerDefined xdc_runtime_Main_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Main_Module__loggerObj; extern const CT__xdc_runtime_Main_Module__loggerObj xdc_runtime_Main_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Main_Module__loggerFxn0; extern const CT__xdc_runtime_Main_Module__loggerFxn0 xdc_runtime_Main_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Main_Module__loggerFxn1; extern const CT__xdc_runtime_Main_Module__loggerFxn1 xdc_runtime_Main_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Main_Module__loggerFxn2; extern const CT__xdc_runtime_Main_Module__loggerFxn2 xdc_runtime_Main_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Main_Module__loggerFxn4; extern const CT__xdc_runtime_Main_Module__loggerFxn4 xdc_runtime_Main_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Main_Module__loggerFxn8; extern const CT__xdc_runtime_Main_Module__loggerFxn8 xdc_runtime_Main_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Main_Object__count; extern const CT__xdc_runtime_Main_Object__count xdc_runtime_Main_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Main_Object__heap; extern const CT__xdc_runtime_Main_Object__heap xdc_runtime_Main_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Main_Object__sizeof; extern const CT__xdc_runtime_Main_Object__sizeof xdc_runtime_Main_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Main_Object__table; extern const CT__xdc_runtime_Main_Object__table xdc_runtime_Main_Object__table__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Main_Module__startupDone__S( void ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Main_Module__id xdc_runtime_Main_Module_id(void); static inline CT__xdc_runtime_Main_Module__id xdc_runtime_Main_Module_id( void ) { return xdc_runtime_Main_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Main_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Main_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Main_Module__diagsMask__C != (CT__xdc_runtime_Main_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Main_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Main_Module_getMask(void) { return (xdc_runtime_Main_Module__diagsMask__C != (CT__xdc_runtime_Main_Module__diagsMask)0) ? *xdc_runtime_Main_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Main_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Main_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Main_Module__diagsMask__C != (CT__xdc_runtime_Main_Module__diagsMask)0) { *xdc_runtime_Main_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== xdc_runtime_Error_Id ======== */ typedef xdc_Bits32 xdc_runtime_Error_Id; /* * ======== Module__MID ======== * This definition allows non-module code to * use the Error module. This symbol is normally defined in each * module internal header (i.e., package/internal/.xdc.h). * * Only do this if this file is not one that will be included in the Registry. * This check ensures that Registry.h (which similarly defines these Module__* * symbols) can be included in any order relative to other xdc.runtime * headers. */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Policy */ enum xdc_runtime_Error_Policy { xdc_runtime_Error_TERMINATE, xdc_runtime_Error_UNWIND }; typedef enum xdc_runtime_Error_Policy xdc_runtime_Error_Policy; /* HookFxn */ typedef void (*xdc_runtime_Error_HookFxn)(xdc_runtime_Error_Block* arg1); /* NUMARGS */ /* Data */ typedef xdc_IArg __T1_xdc_runtime_Error_Data__arg; typedef xdc_IArg ARRAY1_xdc_runtime_Error_Data__arg[2]; typedef xdc_IArg CARRAY1_xdc_runtime_Error_Data__arg[2]; typedef CARRAY1_xdc_runtime_Error_Data__arg __TA_xdc_runtime_Error_Data__arg; struct xdc_runtime_Error_Data { __TA_xdc_runtime_Error_Data__arg arg; }; /* Block */ struct xdc_runtime_Error_Block { xdc_UInt16 unused; xdc_runtime_Error_Data data; xdc_runtime_Error_Id id; xdc_CString msg; xdc_runtime_Types_Site site; }; /* IGNORE */ /* ABORT */ /* PolicyFxn */ typedef void (*xdc_runtime_Error_PolicyFxn)(xdc_runtime_Error_Block* arg1, xdc_runtime_Types_ModuleId arg2, xdc_CString arg3, xdc_Int arg4, xdc_runtime_Error_Id arg5, xdc_IArg arg6, xdc_IArg arg7); /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Error_Module__diagsEnabled; extern const CT__xdc_runtime_Error_Module__diagsEnabled xdc_runtime_Error_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Error_Module__diagsIncluded; extern const CT__xdc_runtime_Error_Module__diagsIncluded xdc_runtime_Error_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Error_Module__diagsMask; extern const CT__xdc_runtime_Error_Module__diagsMask xdc_runtime_Error_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Error_Module__gateObj; extern const CT__xdc_runtime_Error_Module__gateObj xdc_runtime_Error_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Error_Module__gatePrms; extern const CT__xdc_runtime_Error_Module__gatePrms xdc_runtime_Error_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Error_Module__id; extern const CT__xdc_runtime_Error_Module__id xdc_runtime_Error_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Error_Module__loggerDefined; extern const CT__xdc_runtime_Error_Module__loggerDefined xdc_runtime_Error_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Error_Module__loggerObj; extern const CT__xdc_runtime_Error_Module__loggerObj xdc_runtime_Error_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Error_Module__loggerFxn0; extern const CT__xdc_runtime_Error_Module__loggerFxn0 xdc_runtime_Error_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Error_Module__loggerFxn1; extern const CT__xdc_runtime_Error_Module__loggerFxn1 xdc_runtime_Error_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Error_Module__loggerFxn2; extern const CT__xdc_runtime_Error_Module__loggerFxn2 xdc_runtime_Error_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Error_Module__loggerFxn4; extern const CT__xdc_runtime_Error_Module__loggerFxn4 xdc_runtime_Error_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Error_Module__loggerFxn8; extern const CT__xdc_runtime_Error_Module__loggerFxn8 xdc_runtime_Error_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Error_Object__count; extern const CT__xdc_runtime_Error_Object__count xdc_runtime_Error_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Error_Object__heap; extern const CT__xdc_runtime_Error_Object__heap xdc_runtime_Error_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Error_Object__sizeof; extern const CT__xdc_runtime_Error_Object__sizeof xdc_runtime_Error_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Error_Object__table; extern const CT__xdc_runtime_Error_Object__table xdc_runtime_Error_Object__table__C; /* policyFxn */ typedef xdc_runtime_Error_PolicyFxn CT__xdc_runtime_Error_policyFxn; extern const CT__xdc_runtime_Error_policyFxn xdc_runtime_Error_policyFxn__C; /* E_generic */ typedef xdc_runtime_Error_Id CT__xdc_runtime_Error_E_generic; extern const CT__xdc_runtime_Error_E_generic xdc_runtime_Error_E_generic__C; /* E_memory */ typedef xdc_runtime_Error_Id CT__xdc_runtime_Error_E_memory; extern const CT__xdc_runtime_Error_E_memory xdc_runtime_Error_E_memory__C; /* E_msgCode */ typedef xdc_runtime_Error_Id CT__xdc_runtime_Error_E_msgCode; extern const CT__xdc_runtime_Error_E_msgCode xdc_runtime_Error_E_msgCode__C; /* policy */ typedef xdc_runtime_Error_Policy CT__xdc_runtime_Error_policy; extern const CT__xdc_runtime_Error_policy xdc_runtime_Error_policy__C; /* raiseHook */ typedef xdc_runtime_Error_HookFxn CT__xdc_runtime_Error_raiseHook; extern const CT__xdc_runtime_Error_raiseHook xdc_runtime_Error_raiseHook__C; /* maxDepth */ typedef xdc_UInt16 CT__xdc_runtime_Error_maxDepth; extern const CT__xdc_runtime_Error_maxDepth xdc_runtime_Error_maxDepth__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Error_Module__startupDone__S( void ); /* check__E */ extern xdc_Bool xdc_runtime_Error_check__E( xdc_runtime_Error_Block *eb ); /* getData__E */ extern xdc_runtime_Error_Data *xdc_runtime_Error_getData__E( xdc_runtime_Error_Block *eb ); /* getCode__E */ extern xdc_UInt16 xdc_runtime_Error_getCode__E( xdc_runtime_Error_Block *eb ); /* getId__E */ extern xdc_runtime_Error_Id xdc_runtime_Error_getId__E( xdc_runtime_Error_Block *eb ); /* getMsg__E */ extern xdc_CString xdc_runtime_Error_getMsg__E( xdc_runtime_Error_Block *eb ); /* getSite__E */ extern xdc_runtime_Types_Site *xdc_runtime_Error_getSite__E( xdc_runtime_Error_Block *eb ); /* init__E */ extern void xdc_runtime_Error_init__E( xdc_runtime_Error_Block *eb ); /* print__E */ extern void xdc_runtime_Error_print__E( xdc_runtime_Error_Block *eb ); /* policyDefault__E */ extern void xdc_runtime_Error_policyDefault__E( xdc_runtime_Error_Block *eb, xdc_runtime_Types_ModuleId mod, xdc_CString file, xdc_Int line, xdc_runtime_Error_Id id, xdc_IArg arg1, xdc_IArg arg2 ); /* policyMin__E */ extern void xdc_runtime_Error_policyMin__E( xdc_runtime_Error_Block *eb, xdc_runtime_Types_ModuleId mod, xdc_CString file, xdc_Int line, xdc_runtime_Error_Id id, xdc_IArg arg1, xdc_IArg arg2 ); /* policySpin__E */ extern void xdc_runtime_Error_policySpin__E( xdc_runtime_Error_Block *eb, xdc_runtime_Types_ModuleId mod, xdc_CString file, xdc_Int line, xdc_runtime_Error_Id id, xdc_IArg arg1, xdc_IArg arg2 ); /* raiseX__E */ extern void xdc_runtime_Error_raiseX__E( xdc_runtime_Error_Block *eb, xdc_runtime_Types_ModuleId mod, xdc_CString file, xdc_Int line, xdc_runtime_Error_Id id, xdc_IArg arg1, xdc_IArg arg2 ); /* setX__E */ extern void xdc_runtime_Error_setX__E( xdc_runtime_Error_Block *eb, xdc_runtime_Types_ModuleId mod, xdc_CString file, xdc_Int line, xdc_runtime_Error_Id id, xdc_IArg arg1, xdc_IArg arg2 ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Error_Module__id xdc_runtime_Error_Module_id(void); static inline CT__xdc_runtime_Error_Module__id xdc_runtime_Error_Module_id( void ) { return xdc_runtime_Error_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Error_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Error_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Error_Module__diagsMask__C != (CT__xdc_runtime_Error_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Error_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Error_Module_getMask(void) { return (xdc_runtime_Error_Module__diagsMask__C != (CT__xdc_runtime_Error_Module__diagsMask)0) ? *xdc_runtime_Error_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Error_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Error_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Error_Module__diagsMask__C != (CT__xdc_runtime_Error_Module__diagsMask)0) { *xdc_runtime_Error_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== xdc_runtime_Error_raise ======== * Call underlying error handler with current module ID, file name, and * line number. * * Note use of xdc_FILE__ in lieu of __FILE__; this is done * to prevent accumulation of file name strings in the application. See * xdc.h for details. */ /* * ======== xdc_runtime_Error_idToCode ======== */ /* * ======== xdc_runtime_Error_idToUid ======== */ extern xdc_runtime_Error_Block xdc_runtime_Error_IgnoreBlock; /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct xdc_runtime_IHeap_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_IHeap_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Ptr (*alloc)(void* inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block* eb); void (*free)(void* inst, xdc_Ptr block, xdc_SizeT size); xdc_Bool (*isBlocking)(void* inst); void (*getStats)(void* inst, xdc_runtime_Memory_Stats* stats); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base xdc_runtime_IHeap_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* create */ extern xdc_runtime_IHeap_Handle xdc_runtime_IHeap_create(xdc_runtime_IHeap_Module mod, const xdc_runtime_IHeap_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void xdc_runtime_IHeap_delete(xdc_runtime_IHeap_Handle *inst); /* Handle_to_Module */ static inline xdc_runtime_IHeap_Module xdc_runtime_IHeap_Handle_to_Module(xdc_runtime_IHeap_Handle inst); static inline xdc_runtime_IHeap_Module xdc_runtime_IHeap_Handle_to_Module(xdc_runtime_IHeap_Handle inst) { return inst->__fxns; } /* Handle_label */ static inline xdc_runtime_Types_Label *xdc_runtime_IHeap_Handle_label(xdc_runtime_IHeap_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *xdc_runtime_IHeap_Handle_label(xdc_runtime_IHeap_Handle inst, xdc_runtime_Types_Label *lab) { return inst->__fxns->__sysp->__label(inst, lab); } /* Module_id */ static inline xdc_runtime_Types_ModuleId xdc_runtime_IHeap_Module_id(xdc_runtime_IHeap_Module mod); static inline xdc_runtime_Types_ModuleId xdc_runtime_IHeap_Module_id(xdc_runtime_IHeap_Module mod) { return mod->__sysp->__mid; } /* alloc */ static inline xdc_Ptr xdc_runtime_IHeap_alloc(xdc_runtime_IHeap_Handle inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb); static inline xdc_Ptr xdc_runtime_IHeap_alloc( xdc_runtime_IHeap_Handle inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ) { return inst->__fxns->alloc((void*)inst, size, align, eb); } /* free */ static inline void xdc_runtime_IHeap_free(xdc_runtime_IHeap_Handle inst, xdc_Ptr block, xdc_SizeT size); static inline void xdc_runtime_IHeap_free( xdc_runtime_IHeap_Handle inst, xdc_Ptr block, xdc_SizeT size ) { inst->__fxns->free((void*)inst, block, size); } /* isBlocking */ static inline xdc_Bool xdc_runtime_IHeap_isBlocking(xdc_runtime_IHeap_Handle inst); static inline xdc_Bool xdc_runtime_IHeap_isBlocking( xdc_runtime_IHeap_Handle inst ) { return inst->__fxns->isBlocking((void*)inst); } /* getStats */ static inline void xdc_runtime_IHeap_getStats(xdc_runtime_IHeap_Handle inst, xdc_runtime_Memory_Stats *stats); static inline void xdc_runtime_IHeap_getStats( xdc_runtime_IHeap_Handle inst, xdc_runtime_Memory_Stats *stats ) { inst->__fxns->getStats((void*)inst, stats); } /* * ======== FUNCTION SELECTORS ======== */ /* These functions return function pointers for module and instance functions. * The functions accept modules and instances declared as types defined in this * interface, but they return functions defined for the actual objects passed * as parameters. These functions are not invoked by any generated code or * XDCtools internal code. */ /* alloc_{FxnT,fxnP} */ typedef xdc_Ptr (*xdc_runtime_IHeap_alloc_FxnT)(void *inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block* eb); static inline xdc_runtime_IHeap_alloc_FxnT xdc_runtime_IHeap_alloc_fxnP(xdc_runtime_IHeap_Handle inst); static inline xdc_runtime_IHeap_alloc_FxnT xdc_runtime_IHeap_alloc_fxnP(xdc_runtime_IHeap_Handle inst) { return (xdc_runtime_IHeap_alloc_FxnT)inst->__fxns->alloc; } /* free_{FxnT,fxnP} */ typedef void (*xdc_runtime_IHeap_free_FxnT)(void *inst, xdc_Ptr block, xdc_SizeT size); static inline xdc_runtime_IHeap_free_FxnT xdc_runtime_IHeap_free_fxnP(xdc_runtime_IHeap_Handle inst); static inline xdc_runtime_IHeap_free_FxnT xdc_runtime_IHeap_free_fxnP(xdc_runtime_IHeap_Handle inst) { return (xdc_runtime_IHeap_free_FxnT)inst->__fxns->free; } /* isBlocking_{FxnT,fxnP} */ typedef xdc_Bool (*xdc_runtime_IHeap_isBlocking_FxnT)(void *inst); static inline xdc_runtime_IHeap_isBlocking_FxnT xdc_runtime_IHeap_isBlocking_fxnP(xdc_runtime_IHeap_Handle inst); static inline xdc_runtime_IHeap_isBlocking_FxnT xdc_runtime_IHeap_isBlocking_fxnP(xdc_runtime_IHeap_Handle inst) { return (xdc_runtime_IHeap_isBlocking_FxnT)inst->__fxns->isBlocking; } /* getStats_{FxnT,fxnP} */ typedef void (*xdc_runtime_IHeap_getStats_FxnT)(void *inst, xdc_runtime_Memory_Stats* stats); static inline xdc_runtime_IHeap_getStats_FxnT xdc_runtime_IHeap_getStats_fxnP(xdc_runtime_IHeap_Handle inst); static inline xdc_runtime_IHeap_getStats_FxnT xdc_runtime_IHeap_getStats_fxnP(xdc_runtime_IHeap_Handle inst) { return (xdc_runtime_IHeap_getStats_FxnT)inst->__fxns->getStats; } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_IModule_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base xdc_runtime_IModule_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* Module_id */ static inline xdc_runtime_Types_ModuleId xdc_runtime_IModule_Module_id(xdc_runtime_IModule_Module mod); static inline xdc_runtime_Types_ModuleId xdc_runtime_IModule_Module_id(xdc_runtime_IModule_Module mod) { return mod->__sysp->__mid; } /* * ======== FUNCTION SELECTORS ======== */ /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Memory_HeapProxy_Module__diagsEnabled; extern const CT__xdc_runtime_Memory_HeapProxy_Module__diagsEnabled xdc_runtime_Memory_HeapProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Memory_HeapProxy_Module__diagsIncluded; extern const CT__xdc_runtime_Memory_HeapProxy_Module__diagsIncluded xdc_runtime_Memory_HeapProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Memory_HeapProxy_Module__diagsMask; extern const CT__xdc_runtime_Memory_HeapProxy_Module__diagsMask xdc_runtime_Memory_HeapProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Memory_HeapProxy_Module__gateObj; extern const CT__xdc_runtime_Memory_HeapProxy_Module__gateObj xdc_runtime_Memory_HeapProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Memory_HeapProxy_Module__gatePrms; extern const CT__xdc_runtime_Memory_HeapProxy_Module__gatePrms xdc_runtime_Memory_HeapProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Memory_HeapProxy_Module__id; extern const CT__xdc_runtime_Memory_HeapProxy_Module__id xdc_runtime_Memory_HeapProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Memory_HeapProxy_Module__loggerDefined; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerDefined xdc_runtime_Memory_HeapProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Memory_HeapProxy_Module__loggerObj; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerObj xdc_runtime_Memory_HeapProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn0; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn0 xdc_runtime_Memory_HeapProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn1; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn1 xdc_runtime_Memory_HeapProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn2; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn2 xdc_runtime_Memory_HeapProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn4; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn4 xdc_runtime_Memory_HeapProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn8; extern const CT__xdc_runtime_Memory_HeapProxy_Module__loggerFxn8 xdc_runtime_Memory_HeapProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Memory_HeapProxy_Object__count; extern const CT__xdc_runtime_Memory_HeapProxy_Object__count xdc_runtime_Memory_HeapProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Memory_HeapProxy_Object__heap; extern const CT__xdc_runtime_Memory_HeapProxy_Object__heap xdc_runtime_Memory_HeapProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Memory_HeapProxy_Object__sizeof; extern const CT__xdc_runtime_Memory_HeapProxy_Object__sizeof xdc_runtime_Memory_HeapProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Memory_HeapProxy_Object__table; extern const CT__xdc_runtime_Memory_HeapProxy_Object__table xdc_runtime_Memory_HeapProxy_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct xdc_runtime_Memory_HeapProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct xdc_runtime_Memory_HeapProxy_Struct { const xdc_runtime_Memory_HeapProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_Memory_HeapProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Ptr (*alloc)(xdc_runtime_Memory_HeapProxy_Handle inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block* eb); void (*free)(xdc_runtime_Memory_HeapProxy_Handle inst, xdc_Ptr block, xdc_SizeT size); xdc_Bool (*isBlocking)(xdc_runtime_Memory_HeapProxy_Handle inst); void (*getStats)(xdc_runtime_Memory_HeapProxy_Handle inst, xdc_runtime_Memory_Stats* stats); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const xdc_runtime_Memory_HeapProxy_Fxns__ xdc_runtime_Memory_HeapProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern xdc_runtime_Memory_HeapProxy_Handle xdc_runtime_Memory_HeapProxy_create( const xdc_runtime_Memory_HeapProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void xdc_runtime_Memory_HeapProxy_delete(xdc_runtime_Memory_HeapProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *xdc_runtime_Memory_HeapProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Memory_HeapProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr xdc_runtime_Memory_HeapProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr xdc_runtime_Memory_HeapProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr xdc_runtime_Memory_HeapProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void xdc_runtime_Memory_HeapProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool xdc_runtime_Memory_HeapProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr xdc_runtime_Memory_HeapProxy_Proxy__delegate__S( void ); /* alloc__E */ extern xdc_Ptr xdc_runtime_Memory_HeapProxy_alloc__E( xdc_runtime_Memory_HeapProxy_Handle __inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ); /* free__E */ extern void xdc_runtime_Memory_HeapProxy_free__E( xdc_runtime_Memory_HeapProxy_Handle __inst, xdc_Ptr block, xdc_SizeT size ); /* isBlocking__E */ extern xdc_Bool xdc_runtime_Memory_HeapProxy_isBlocking__E( xdc_runtime_Memory_HeapProxy_Handle __inst ); /* getStats__E */ extern void xdc_runtime_Memory_HeapProxy_getStats__E( xdc_runtime_Memory_HeapProxy_Handle __inst, xdc_runtime_Memory_Stats *stats ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IHeap_Module xdc_runtime_Memory_HeapProxy_Module_upCast(void); static inline xdc_runtime_IHeap_Module xdc_runtime_Memory_HeapProxy_Module_upCast(void) { return (xdc_runtime_IHeap_Module)xdc_runtime_Memory_HeapProxy_Proxy__delegate__S(); } /* Module_to_xdc_runtime_IHeap */ /* Handle_upCast */ static inline xdc_runtime_IHeap_Handle xdc_runtime_Memory_HeapProxy_Handle_upCast(xdc_runtime_Memory_HeapProxy_Handle i); static inline xdc_runtime_IHeap_Handle xdc_runtime_Memory_HeapProxy_Handle_upCast(xdc_runtime_Memory_HeapProxy_Handle i) { return (xdc_runtime_IHeap_Handle)i; } /* Handle_to_xdc_runtime_IHeap */ /* Handle_downCast */ static inline xdc_runtime_Memory_HeapProxy_Handle xdc_runtime_Memory_HeapProxy_Handle_downCast(xdc_runtime_IHeap_Handle i); static inline xdc_runtime_Memory_HeapProxy_Handle xdc_runtime_Memory_HeapProxy_Handle_downCast(xdc_runtime_IHeap_Handle i) { xdc_runtime_IHeap_Handle i2 = (xdc_runtime_IHeap_Handle)i; if (xdc_runtime_Memory_HeapProxy_Proxy__abstract__S()) { return (xdc_runtime_Memory_HeapProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)xdc_runtime_Memory_HeapProxy_Proxy__delegate__S()) ? (xdc_runtime_Memory_HeapProxy_Handle)i : (xdc_runtime_Memory_HeapProxy_Handle)0; } /* Handle_from_xdc_runtime_IHeap */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Memory_HeapProxy_Module__id xdc_runtime_Memory_HeapProxy_Module_id(void); static inline CT__xdc_runtime_Memory_HeapProxy_Module__id xdc_runtime_Memory_HeapProxy_Module_id( void ) { return xdc_runtime_Memory_HeapProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void xdc_runtime_Memory_HeapProxy_Params_init(xdc_runtime_Memory_HeapProxy_Params *prms); static inline void xdc_runtime_Memory_HeapProxy_Params_init( xdc_runtime_Memory_HeapProxy_Params *prms ) { if (prms != 0) { xdc_runtime_Memory_HeapProxy_Params__init__S(prms, 0, sizeof(xdc_runtime_Memory_HeapProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void xdc_runtime_Memory_HeapProxy_Params_copy(xdc_runtime_Memory_HeapProxy_Params *dst, const xdc_runtime_Memory_HeapProxy_Params *src); static inline void xdc_runtime_Memory_HeapProxy_Params_copy(xdc_runtime_Memory_HeapProxy_Params *dst, const xdc_runtime_Memory_HeapProxy_Params *src) { if (dst != 0) { xdc_runtime_Memory_HeapProxy_Params__init__S(dst, (const void *)src, sizeof(xdc_runtime_Memory_HeapProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Q_BLOCKING */ /* Size */ typedef xdc_UArg xdc_runtime_Memory_Size; /* Stats */ struct xdc_runtime_Memory_Stats { xdc_runtime_Memory_Size totalSize; xdc_runtime_Memory_Size totalFreeSize; xdc_runtime_Memory_Size largestFreeSize; }; /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Memory_Module__diagsEnabled; extern const CT__xdc_runtime_Memory_Module__diagsEnabled xdc_runtime_Memory_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Memory_Module__diagsIncluded; extern const CT__xdc_runtime_Memory_Module__diagsIncluded xdc_runtime_Memory_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Memory_Module__diagsMask; extern const CT__xdc_runtime_Memory_Module__diagsMask xdc_runtime_Memory_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Memory_Module__gateObj; extern const CT__xdc_runtime_Memory_Module__gateObj xdc_runtime_Memory_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Memory_Module__gatePrms; extern const CT__xdc_runtime_Memory_Module__gatePrms xdc_runtime_Memory_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Memory_Module__id; extern const CT__xdc_runtime_Memory_Module__id xdc_runtime_Memory_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Memory_Module__loggerDefined; extern const CT__xdc_runtime_Memory_Module__loggerDefined xdc_runtime_Memory_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Memory_Module__loggerObj; extern const CT__xdc_runtime_Memory_Module__loggerObj xdc_runtime_Memory_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Memory_Module__loggerFxn0; extern const CT__xdc_runtime_Memory_Module__loggerFxn0 xdc_runtime_Memory_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Memory_Module__loggerFxn1; extern const CT__xdc_runtime_Memory_Module__loggerFxn1 xdc_runtime_Memory_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Memory_Module__loggerFxn2; extern const CT__xdc_runtime_Memory_Module__loggerFxn2 xdc_runtime_Memory_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Memory_Module__loggerFxn4; extern const CT__xdc_runtime_Memory_Module__loggerFxn4 xdc_runtime_Memory_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Memory_Module__loggerFxn8; extern const CT__xdc_runtime_Memory_Module__loggerFxn8 xdc_runtime_Memory_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Memory_Object__count; extern const CT__xdc_runtime_Memory_Object__count xdc_runtime_Memory_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Memory_Object__heap; extern const CT__xdc_runtime_Memory_Object__heap xdc_runtime_Memory_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Memory_Object__sizeof; extern const CT__xdc_runtime_Memory_Object__sizeof xdc_runtime_Memory_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Memory_Object__table; extern const CT__xdc_runtime_Memory_Object__table xdc_runtime_Memory_Object__table__C; /* defaultHeapInstance */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Memory_defaultHeapInstance; extern const CT__xdc_runtime_Memory_defaultHeapInstance xdc_runtime_Memory_defaultHeapInstance__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Memory_Module__startupDone__S( void ); /* alloc__E */ extern xdc_Ptr xdc_runtime_Memory_alloc__E( xdc_runtime_IHeap_Handle heap, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ); /* calloc__E */ extern xdc_Ptr xdc_runtime_Memory_calloc__E( xdc_runtime_IHeap_Handle heap, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ); /* free__E */ extern void xdc_runtime_Memory_free__E( xdc_runtime_IHeap_Handle heap, xdc_Ptr block, xdc_SizeT size ); /* getStats__E */ extern void xdc_runtime_Memory_getStats__E( xdc_runtime_IHeap_Handle heap, xdc_runtime_Memory_Stats *stats ); /* query__E */ extern xdc_Bool xdc_runtime_Memory_query__E( xdc_runtime_IHeap_Handle heap, xdc_Int qual ); /* getMaxDefaultTypeAlign__E */ extern xdc_SizeT xdc_runtime_Memory_getMaxDefaultTypeAlign__E( void ); /* valloc__E */ extern xdc_Ptr xdc_runtime_Memory_valloc__E( xdc_runtime_IHeap_Handle heap, xdc_SizeT size, xdc_SizeT align, xdc_Char value, xdc_runtime_Error_Block *eb ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Memory_Module__id xdc_runtime_Memory_Module_id(void); static inline CT__xdc_runtime_Memory_Module__id xdc_runtime_Memory_Module_id( void ) { return xdc_runtime_Memory_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Memory_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Memory_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Memory_Module__diagsMask__C != (CT__xdc_runtime_Memory_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Memory_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Memory_Module_getMask(void) { return (xdc_runtime_Memory_Module__diagsMask__C != (CT__xdc_runtime_Memory_Module__diagsMask)0) ? *xdc_runtime_Memory_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Memory_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Memory_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Memory_Module__diagsMask__C != (CT__xdc_runtime_Memory_Module__diagsMask)0) { *xdc_runtime_Memory_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== Assert__prologue.h ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== Diags__prologue.h ======== * * This header defines Module__* symbols for every Module__* value used * by the Diags module's headers. This allows non-module code to * use the Diags module. These symbols are normally defined in * module internal headers (i.e., package/internal/.xdc.h) and they * define a "current module context". */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Only define these symbols for xdc.runtime.Main if this file is not one that * will be included in the Registry. This check ensures that Registry.h (which * similarly defines these Module__* symbols) can be included in any order * relative to other xdc.runtime headers. */ /* * ======== Module__DGSINCL ======== * The set of diags categories that are runtime controllable _or_ always on * * This costant is computed at config time and enables us to eliminate * expensive runtime time checks and unnecessary data (the module's diags * mask) when whole program optimization is used. */ /* * ======== Module__DGSENAB ======== * The set of diags categories that are _always_ enabled * * This costant is computed at config time and enables us to eliminate * expensive runtime time checks and unnecessary data (the module's diags * mask) when whole program optimization is used. */ /* * ======== Module__DGSMASK ======== * Pointer to the set of diags categories that are runtime controllable */ /* * ======== Module__MID ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Mask */ typedef xdc_runtime_Types_DiagsMask xdc_runtime_Diags_Mask; /* ENTRY */ /* EXIT */ /* LIFECYCLE */ /* INTERNAL */ /* ASSERT */ /* STATUS */ /* LEVEL */ /* USER1 */ /* USER2 */ /* USER3 */ /* USER4 */ /* USER5 */ /* USER6 */ /* USER7 */ /* INFO */ /* USER8 */ /* ANALYSIS */ /* ALL */ /* ALL_LOGGING */ /* EventLevel */ enum xdc_runtime_Diags_EventLevel { xdc_runtime_Diags_LEVEL1 = 0x0, xdc_runtime_Diags_LEVEL2 = 0x20, xdc_runtime_Diags_LEVEL3 = 0x40, xdc_runtime_Diags_LEVEL4 = 0x60 }; typedef enum xdc_runtime_Diags_EventLevel xdc_runtime_Diags_EventLevel; /* EMERGENCY */ /* CRITICAL */ /* ERROR */ /* WARNING */ /* * ======== INTERNAL DEFINITIONS ======== */ /* DictElem */ struct xdc_runtime_Diags_DictElem { xdc_runtime_Types_ModuleId modId; xdc_runtime_Diags_Mask *maskAddr; }; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Diags_Module__diagsEnabled; extern const CT__xdc_runtime_Diags_Module__diagsEnabled xdc_runtime_Diags_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Diags_Module__diagsIncluded; extern const CT__xdc_runtime_Diags_Module__diagsIncluded xdc_runtime_Diags_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Diags_Module__diagsMask; extern const CT__xdc_runtime_Diags_Module__diagsMask xdc_runtime_Diags_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Diags_Module__gateObj; extern const CT__xdc_runtime_Diags_Module__gateObj xdc_runtime_Diags_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Diags_Module__gatePrms; extern const CT__xdc_runtime_Diags_Module__gatePrms xdc_runtime_Diags_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Diags_Module__id; extern const CT__xdc_runtime_Diags_Module__id xdc_runtime_Diags_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Diags_Module__loggerDefined; extern const CT__xdc_runtime_Diags_Module__loggerDefined xdc_runtime_Diags_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Diags_Module__loggerObj; extern const CT__xdc_runtime_Diags_Module__loggerObj xdc_runtime_Diags_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Diags_Module__loggerFxn0; extern const CT__xdc_runtime_Diags_Module__loggerFxn0 xdc_runtime_Diags_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Diags_Module__loggerFxn1; extern const CT__xdc_runtime_Diags_Module__loggerFxn1 xdc_runtime_Diags_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Diags_Module__loggerFxn2; extern const CT__xdc_runtime_Diags_Module__loggerFxn2 xdc_runtime_Diags_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Diags_Module__loggerFxn4; extern const CT__xdc_runtime_Diags_Module__loggerFxn4 xdc_runtime_Diags_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Diags_Module__loggerFxn8; extern const CT__xdc_runtime_Diags_Module__loggerFxn8 xdc_runtime_Diags_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Diags_Object__count; extern const CT__xdc_runtime_Diags_Object__count xdc_runtime_Diags_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Diags_Object__heap; extern const CT__xdc_runtime_Diags_Object__heap xdc_runtime_Diags_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Diags_Object__sizeof; extern const CT__xdc_runtime_Diags_Object__sizeof xdc_runtime_Diags_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Diags_Object__table; extern const CT__xdc_runtime_Diags_Object__table xdc_runtime_Diags_Object__table__C; /* setMaskEnabled */ typedef xdc_Bool CT__xdc_runtime_Diags_setMaskEnabled; extern const CT__xdc_runtime_Diags_setMaskEnabled xdc_runtime_Diags_setMaskEnabled__C; /* dictBase */ typedef xdc_runtime_Diags_DictElem *CT__xdc_runtime_Diags_dictBase; extern const CT__xdc_runtime_Diags_dictBase xdc_runtime_Diags_dictBase__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Diags_Module__startupDone__S( void ); /* setMask__E */ extern void xdc_runtime_Diags_setMask__E( xdc_CString control ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Diags_Module__id xdc_runtime_Diags_Module_id(void); static inline CT__xdc_runtime_Diags_Module__id xdc_runtime_Diags_Module_id( void ) { return xdc_runtime_Diags_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Diags_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Diags_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Diags_Module__diagsMask__C != (CT__xdc_runtime_Diags_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Diags_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Diags_Module_getMask(void) { return (xdc_runtime_Diags_Module__diagsMask__C != (CT__xdc_runtime_Diags_Module__diagsMask)0) ? *xdc_runtime_Diags_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Diags_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Diags_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Diags_Module__diagsMask__C != (CT__xdc_runtime_Diags_Module__diagsMask)0) { *xdc_runtime_Diags_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== xdc_runtime_Diags_query ======== * Returns true iff: * 1. the current module's included diags intersect evt's mask, and * 2. either the permanently enabled diags intersect evt's mask or * the runtime controllable diags intersect evt's mask. * * This macro relies on three "internal" macros which are defined in each * module's internal header (e.g., package/internal/System.xdc.h): * Module__DGSINCL - a const bit mask of bits that are _not_ ALWAYS_OFF * Module__DGSENAB - a const bit mask of bits that are ALWAYS_ON * Module__DGSMASK - a const pointer to a bit mask of currently enabled * diagnostics * These macros reference module-specific variables generated at config * time, when we know the value of these constants. * */ /* * ======== xdc_runtime_Diags_getLevel ======== * Returns the event level set in the given diags mask. The level is a value * stored using two bits of the diags mask. */ /* * ======== xdc_runtime_Diags_compareLevels ======== * The definition of the diags levels assigns the value '0' to the highest * priority events and '3' to the lowest, so the comparison is done backwards. * For example, for (LEVEL4 (0), LEVEL1 (3)) this must return false. */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== xdc_runtime_Assert_Id ======== */ typedef xdc_Bits32 xdc_runtime_Assert_Id; /* * ======== Module__MID ======== * This definition allows non-module code to * use the Assert module. This symbol is normally defined in each * module internal header (i.e., package/internal/.xdc.h). * * Only do this if this file is not one that will be included in the Registry. * This check ensures that Registry.h (which similarly defines these Module__* * symbols) can be included in any order relative to other xdc.runtime * headers. */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Assert_Module__diagsEnabled; extern const CT__xdc_runtime_Assert_Module__diagsEnabled xdc_runtime_Assert_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Assert_Module__diagsIncluded; extern const CT__xdc_runtime_Assert_Module__diagsIncluded xdc_runtime_Assert_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Assert_Module__diagsMask; extern const CT__xdc_runtime_Assert_Module__diagsMask xdc_runtime_Assert_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Assert_Module__gateObj; extern const CT__xdc_runtime_Assert_Module__gateObj xdc_runtime_Assert_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Assert_Module__gatePrms; extern const CT__xdc_runtime_Assert_Module__gatePrms xdc_runtime_Assert_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Assert_Module__id; extern const CT__xdc_runtime_Assert_Module__id xdc_runtime_Assert_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Assert_Module__loggerDefined; extern const CT__xdc_runtime_Assert_Module__loggerDefined xdc_runtime_Assert_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Assert_Module__loggerObj; extern const CT__xdc_runtime_Assert_Module__loggerObj xdc_runtime_Assert_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Assert_Module__loggerFxn0; extern const CT__xdc_runtime_Assert_Module__loggerFxn0 xdc_runtime_Assert_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Assert_Module__loggerFxn1; extern const CT__xdc_runtime_Assert_Module__loggerFxn1 xdc_runtime_Assert_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Assert_Module__loggerFxn2; extern const CT__xdc_runtime_Assert_Module__loggerFxn2 xdc_runtime_Assert_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Assert_Module__loggerFxn4; extern const CT__xdc_runtime_Assert_Module__loggerFxn4 xdc_runtime_Assert_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Assert_Module__loggerFxn8; extern const CT__xdc_runtime_Assert_Module__loggerFxn8 xdc_runtime_Assert_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Assert_Object__count; extern const CT__xdc_runtime_Assert_Object__count xdc_runtime_Assert_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Assert_Object__heap; extern const CT__xdc_runtime_Assert_Object__heap xdc_runtime_Assert_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Assert_Object__sizeof; extern const CT__xdc_runtime_Assert_Object__sizeof xdc_runtime_Assert_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Assert_Object__table; extern const CT__xdc_runtime_Assert_Object__table xdc_runtime_Assert_Object__table__C; /* E_assertFailed */ typedef xdc_runtime_Error_Id CT__xdc_runtime_Assert_E_assertFailed; extern const CT__xdc_runtime_Assert_E_assertFailed xdc_runtime_Assert_E_assertFailed__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Assert_Module__startupDone__S( void ); /* raise__I */ extern void xdc_runtime_Assert_raise__I( xdc_runtime_Types_ModuleId mod, xdc_CString file, xdc_Int line, xdc_runtime_Assert_Id id ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Assert_Module__id xdc_runtime_Assert_Module_id(void); static inline CT__xdc_runtime_Assert_Module__id xdc_runtime_Assert_Module_id( void ) { return xdc_runtime_Assert_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Assert_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Assert_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Assert_Module__diagsMask__C != (CT__xdc_runtime_Assert_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Assert_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Assert_Module_getMask(void) { return (xdc_runtime_Assert_Module__diagsMask__C != (CT__xdc_runtime_Assert_Module__diagsMask)0) ? *xdc_runtime_Assert_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Assert_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Assert_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Assert_Module__diagsMask__C != (CT__xdc_runtime_Assert_Module__diagsMask)0) { *xdc_runtime_Assert_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== xdc_runtime_Assert_getMask ======== * Convert an id into a mask */ /* * ======== xdc_runtime_Assert_isTrue ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Q_BLOCKING */ /* Q_PREEMPTING */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsEnabled; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsEnabled ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsIncluded; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsIncluded ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsMask; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsMask ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gateObj; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gateObj ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gatePrms; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gatePrms ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerDefined; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerDefined ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerObj; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerObj ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn0; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn0 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn1; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn1 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn2; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn2 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn4; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn4 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn8; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn8 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__count; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__count ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__heap; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__heap ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__sizeof; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__sizeof ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__table; extern const CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__table ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Struct { const ti_sysbios_heaps_HeapMem_Module_GateProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*query)(xdc_Int qual); xdc_IArg (*enter)(ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle inst); void (*leave)(ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle inst, xdc_IArg key); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_heaps_HeapMem_Module_GateProxy_Fxns__ ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle ti_sysbios_heaps_HeapMem_Module_GateProxy_create( const ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_heaps_HeapMem_Module_GateProxy_delete(ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_heaps_HeapMem_Module_GateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__delegate__S( void ); /* query__E */ extern xdc_Bool ti_sysbios_heaps_HeapMem_Module_GateProxy_query__E( xdc_Int qual ); /* enter__E */ extern xdc_IArg ti_sysbios_heaps_HeapMem_Module_GateProxy_enter__E( ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle __inst ); /* leave__E */ extern void ti_sysbios_heaps_HeapMem_Module_GateProxy_leave__E( ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle __inst, xdc_IArg key ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IGateProvider_Module ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_upCast(void); static inline xdc_runtime_IGateProvider_Module ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_upCast(void) { return (xdc_runtime_IGateProvider_Module)ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__delegate__S(); } /* Module_to_xdc_runtime_IGateProvider */ /* Handle_upCast */ static inline xdc_runtime_IGateProvider_Handle ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle_upCast(ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle i); static inline xdc_runtime_IGateProvider_Handle ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle_upCast(ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle i) { return (xdc_runtime_IGateProvider_Handle)i; } /* Handle_to_xdc_runtime_IGateProvider */ /* Handle_downCast */ static inline ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i); static inline ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i) { xdc_runtime_IGateProvider_Handle i2 = (xdc_runtime_IGateProvider_Handle)i; if (ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__abstract__S()) { return (ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__delegate__S()) ? (ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle)i : (ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle)0; } /* Handle_from_xdc_runtime_IGateProvider */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_id(void); static inline CT__ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_id( void ) { return ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void ti_sysbios_heaps_HeapMem_Module_GateProxy_Params_init(ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *prms); static inline void ti_sysbios_heaps_HeapMem_Module_GateProxy_Params_init( ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *prms ) { if (prms != 0) { ti_sysbios_heaps_HeapMem_Module_GateProxy_Params__init__S(prms, 0, sizeof(ti_sysbios_heaps_HeapMem_Module_GateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_heaps_HeapMem_Module_GateProxy_Params_copy(ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *dst, const ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *src); static inline void ti_sysbios_heaps_HeapMem_Module_GateProxy_Params_copy(ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *dst, const ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *src) { if (dst != 0) { ti_sysbios_heaps_HeapMem_Module_GateProxy_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_heaps_HeapMem_Module_GateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* ExtendedStats */ struct ti_sysbios_heaps_HeapMem_ExtendedStats { xdc_Ptr buf; xdc_SizeT size; }; /* * ======== INTERNAL DEFINITIONS ======== */ /* Header */ struct ti_sysbios_heaps_HeapMem_Header { ti_sysbios_heaps_HeapMem_Header *next; xdc_runtime_Memory_Size size; }; /* Instance_State */ typedef xdc_Char __T1_ti_sysbios_heaps_HeapMem_Instance_State__buf; typedef xdc_Char *ARRAY1_ti_sysbios_heaps_HeapMem_Instance_State__buf; typedef const xdc_Char *CARRAY1_ti_sysbios_heaps_HeapMem_Instance_State__buf; typedef ARRAY1_ti_sysbios_heaps_HeapMem_Instance_State__buf __TA_ti_sysbios_heaps_HeapMem_Instance_State__buf; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_heaps_HeapMem_Module__diagsEnabled; extern const CT__ti_sysbios_heaps_HeapMem_Module__diagsEnabled ti_sysbios_heaps_HeapMem_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_heaps_HeapMem_Module__diagsIncluded; extern const CT__ti_sysbios_heaps_HeapMem_Module__diagsIncluded ti_sysbios_heaps_HeapMem_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_heaps_HeapMem_Module__diagsMask; extern const CT__ti_sysbios_heaps_HeapMem_Module__diagsMask ti_sysbios_heaps_HeapMem_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module__gateObj; extern const CT__ti_sysbios_heaps_HeapMem_Module__gateObj ti_sysbios_heaps_HeapMem_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module__gatePrms; extern const CT__ti_sysbios_heaps_HeapMem_Module__gatePrms ti_sysbios_heaps_HeapMem_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_heaps_HeapMem_Module__id; extern const CT__ti_sysbios_heaps_HeapMem_Module__id ti_sysbios_heaps_HeapMem_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_heaps_HeapMem_Module__loggerDefined; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerDefined ti_sysbios_heaps_HeapMem_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Module__loggerObj; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerObj ti_sysbios_heaps_HeapMem_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn0; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn0 ti_sysbios_heaps_HeapMem_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn1; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn1 ti_sysbios_heaps_HeapMem_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn2; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn2 ti_sysbios_heaps_HeapMem_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn4; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn4 ti_sysbios_heaps_HeapMem_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn8; extern const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn8 ti_sysbios_heaps_HeapMem_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_heaps_HeapMem_Object__count; extern const CT__ti_sysbios_heaps_HeapMem_Object__count ti_sysbios_heaps_HeapMem_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_heaps_HeapMem_Object__heap; extern const CT__ti_sysbios_heaps_HeapMem_Object__heap ti_sysbios_heaps_HeapMem_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_heaps_HeapMem_Object__sizeof; extern const CT__ti_sysbios_heaps_HeapMem_Object__sizeof ti_sysbios_heaps_HeapMem_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapMem_Object__table; extern const CT__ti_sysbios_heaps_HeapMem_Object__table ti_sysbios_heaps_HeapMem_Object__table__C; /* A_zeroBlock */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapMem_A_zeroBlock; extern const CT__ti_sysbios_heaps_HeapMem_A_zeroBlock ti_sysbios_heaps_HeapMem_A_zeroBlock__C; /* A_heapSize */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapMem_A_heapSize; extern const CT__ti_sysbios_heaps_HeapMem_A_heapSize ti_sysbios_heaps_HeapMem_A_heapSize__C; /* A_align */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapMem_A_align; extern const CT__ti_sysbios_heaps_HeapMem_A_align ti_sysbios_heaps_HeapMem_A_align__C; /* E_memory */ typedef xdc_runtime_Error_Id CT__ti_sysbios_heaps_HeapMem_E_memory; extern const CT__ti_sysbios_heaps_HeapMem_E_memory ti_sysbios_heaps_HeapMem_E_memory__C; /* A_invalidFree */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapMem_A_invalidFree; extern const CT__ti_sysbios_heaps_HeapMem_A_invalidFree ti_sysbios_heaps_HeapMem_A_invalidFree__C; /* primaryHeapBaseAddr */ typedef xdc_Char *CT__ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr; extern const CT__ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr__C; /* primaryHeapEndAddr */ typedef xdc_Char *CT__ti_sysbios_heaps_HeapMem_primaryHeapEndAddr; extern const CT__ti_sysbios_heaps_HeapMem_primaryHeapEndAddr ti_sysbios_heaps_HeapMem_primaryHeapEndAddr__C; /* reqAlign */ typedef xdc_SizeT CT__ti_sysbios_heaps_HeapMem_reqAlign; extern const CT__ti_sysbios_heaps_HeapMem_reqAlign ti_sysbios_heaps_HeapMem_reqAlign__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_heaps_HeapMem_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_SizeT minBlockAlign; xdc_Ptr buf; xdc_runtime_Memory_Size size; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_heaps_HeapMem_Struct { const ti_sysbios_heaps_HeapMem_Fxns__ *__fxns; xdc_runtime_Memory_Size f0; __TA_ti_sysbios_heaps_HeapMem_Instance_State__buf f1; ti_sysbios_heaps_HeapMem_Header f2; xdc_SizeT f3; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_heaps_HeapMem_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Ptr (*alloc)(ti_sysbios_heaps_HeapMem_Handle inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block* eb); void (*free)(ti_sysbios_heaps_HeapMem_Handle inst, xdc_Ptr block, xdc_SizeT size); xdc_Bool (*isBlocking)(ti_sysbios_heaps_HeapMem_Handle inst); void (*getStats)(ti_sysbios_heaps_HeapMem_Handle inst, xdc_runtime_Memory_Stats* stats); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_heaps_HeapMem_Fxns__ ti_sysbios_heaps_HeapMem_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Instance_init__E */ extern void ti_sysbios_heaps_HeapMem_Instance_init__E(ti_sysbios_heaps_HeapMem_Object *obj, const ti_sysbios_heaps_HeapMem_Params *prms); /* create */ extern ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_create( const ti_sysbios_heaps_HeapMem_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_heaps_HeapMem_construct(ti_sysbios_heaps_HeapMem_Struct *obj, const ti_sysbios_heaps_HeapMem_Params *prms); /* delete */ extern void ti_sysbios_heaps_HeapMem_delete(ti_sysbios_heaps_HeapMem_Handle *instp); /* destruct */ extern void ti_sysbios_heaps_HeapMem_destruct(ti_sysbios_heaps_HeapMem_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_heaps_HeapMem_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_heaps_HeapMem_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_heaps_HeapMem_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_heaps_HeapMem_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* enter__E */ extern xdc_IArg ti_sysbios_heaps_HeapMem_enter__E( void ); /* leave__E */ extern void ti_sysbios_heaps_HeapMem_leave__E( xdc_IArg key ); /* alloc__E */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_alloc__E( ti_sysbios_heaps_HeapMem_Handle __inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ); /* allocUnprotected__E */ extern xdc_Ptr ti_sysbios_heaps_HeapMem_allocUnprotected__E( ti_sysbios_heaps_HeapMem_Handle __inst, xdc_SizeT size, xdc_SizeT align ); /* free__E */ extern void ti_sysbios_heaps_HeapMem_free__E( ti_sysbios_heaps_HeapMem_Handle __inst, xdc_Ptr block, xdc_SizeT size ); /* freeUnprotected__E */ extern void ti_sysbios_heaps_HeapMem_freeUnprotected__E( ti_sysbios_heaps_HeapMem_Handle __inst, xdc_Ptr block, xdc_SizeT size ); /* isBlocking__E */ extern xdc_Bool ti_sysbios_heaps_HeapMem_isBlocking__E( ti_sysbios_heaps_HeapMem_Handle __inst ); /* getStats__E */ extern void ti_sysbios_heaps_HeapMem_getStats__E( ti_sysbios_heaps_HeapMem_Handle __inst, xdc_runtime_Memory_Stats *stats ); /* restore__E */ extern void ti_sysbios_heaps_HeapMem_restore__E( ti_sysbios_heaps_HeapMem_Handle __inst ); /* getExtendedStats__E */ extern void ti_sysbios_heaps_HeapMem_getExtendedStats__E( ti_sysbios_heaps_HeapMem_Handle __inst, ti_sysbios_heaps_HeapMem_ExtendedStats *stats ); /* init__I */ extern void ti_sysbios_heaps_HeapMem_init__I( void ); /* initPrimary__I */ extern void ti_sysbios_heaps_HeapMem_initPrimary__I( void ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IHeap_Module ti_sysbios_heaps_HeapMem_Module_upCast(void); static inline xdc_runtime_IHeap_Module ti_sysbios_heaps_HeapMem_Module_upCast(void) { return (xdc_runtime_IHeap_Module)&ti_sysbios_heaps_HeapMem_Module__FXNS__C; } /* Module_to_xdc_runtime_IHeap */ /* Handle_upCast */ static inline xdc_runtime_IHeap_Handle ti_sysbios_heaps_HeapMem_Handle_upCast(ti_sysbios_heaps_HeapMem_Handle i); static inline xdc_runtime_IHeap_Handle ti_sysbios_heaps_HeapMem_Handle_upCast(ti_sysbios_heaps_HeapMem_Handle i) { return (xdc_runtime_IHeap_Handle)i; } /* Handle_to_xdc_runtime_IHeap */ /* Handle_downCast */ static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Handle_downCast(xdc_runtime_IHeap_Handle i); static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Handle_downCast(xdc_runtime_IHeap_Handle i) { xdc_runtime_IHeap_Handle i2 = (xdc_runtime_IHeap_Handle)i; return ((const void*)i2->__fxns == (const void*)&ti_sysbios_heaps_HeapMem_Module__FXNS__C) ? (ti_sysbios_heaps_HeapMem_Handle)i : (ti_sysbios_heaps_HeapMem_Handle)0; } /* Handle_from_xdc_runtime_IHeap */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_heaps_HeapMem_Module__id ti_sysbios_heaps_HeapMem_Module_id(void); static inline CT__ti_sysbios_heaps_HeapMem_Module__id ti_sysbios_heaps_HeapMem_Module_id( void ) { return ti_sysbios_heaps_HeapMem_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_heaps_HeapMem_Module_hasMask(void); static inline xdc_Bool ti_sysbios_heaps_HeapMem_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_heaps_HeapMem_Module__diagsMask__C != (CT__ti_sysbios_heaps_HeapMem_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_heaps_HeapMem_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_heaps_HeapMem_Module_getMask(void) { return (ti_sysbios_heaps_HeapMem_Module__diagsMask__C != (CT__ti_sysbios_heaps_HeapMem_Module__diagsMask)0) ? *ti_sysbios_heaps_HeapMem_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_heaps_HeapMem_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_heaps_HeapMem_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_heaps_HeapMem_Module__diagsMask__C != (CT__ti_sysbios_heaps_HeapMem_Module__diagsMask)0) { *ti_sysbios_heaps_HeapMem_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_heaps_HeapMem_Params_init(ti_sysbios_heaps_HeapMem_Params *prms); static inline void ti_sysbios_heaps_HeapMem_Params_init( ti_sysbios_heaps_HeapMem_Params *prms ) { if (prms != 0) { ti_sysbios_heaps_HeapMem_Params__init__S(prms, 0, sizeof(ti_sysbios_heaps_HeapMem_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_heaps_HeapMem_Params_copy(ti_sysbios_heaps_HeapMem_Params *dst, const ti_sysbios_heaps_HeapMem_Params *src); static inline void ti_sysbios_heaps_HeapMem_Params_copy(ti_sysbios_heaps_HeapMem_Params *dst, const ti_sysbios_heaps_HeapMem_Params *src) { if (dst != 0) { ti_sysbios_heaps_HeapMem_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_heaps_HeapMem_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Object_get(ti_sysbios_heaps_HeapMem_Instance_State *oarr, int i); static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Object_get(ti_sysbios_heaps_HeapMem_Instance_State *oarr, int i) { return (ti_sysbios_heaps_HeapMem_Handle)ti_sysbios_heaps_HeapMem_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Object_first(void); static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Object_first(void) { return (ti_sysbios_heaps_HeapMem_Handle)ti_sysbios_heaps_HeapMem_Object__first__S(); } /* Object_next */ static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Object_next(ti_sysbios_heaps_HeapMem_Object *obj); static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_Object_next(ti_sysbios_heaps_HeapMem_Object *obj) { return (ti_sysbios_heaps_HeapMem_Handle)ti_sysbios_heaps_HeapMem_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_heaps_HeapMem_Handle_label(ti_sysbios_heaps_HeapMem_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_heaps_HeapMem_Handle_label(ti_sysbios_heaps_HeapMem_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_heaps_HeapMem_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_heaps_HeapMem_Handle_name(ti_sysbios_heaps_HeapMem_Handle inst); static inline xdc_String ti_sysbios_heaps_HeapMem_Handle_name(ti_sysbios_heaps_HeapMem_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_heaps_HeapMem_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_handle(ti_sysbios_heaps_HeapMem_Struct *str); static inline ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_handle(ti_sysbios_heaps_HeapMem_Struct *str) { return (ti_sysbios_heaps_HeapMem_Handle)str; } /* struct */ static inline ti_sysbios_heaps_HeapMem_Struct *ti_sysbios_heaps_HeapMem_struct(ti_sysbios_heaps_HeapMem_Handle inst); static inline ti_sysbios_heaps_HeapMem_Struct *ti_sysbios_heaps_HeapMem_struct(ti_sysbios_heaps_HeapMem_Handle inst) { return (ti_sysbios_heaps_HeapMem_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ extern const ti_sysbios_heaps_HeapMem_Handle heap0; extern int xdc_runtime_Startup__EXECFXN__C; extern int xdc_runtime_Startup__RESETFXN__C; /* * @(#) xdc.cfg; 1, 0, 2,0; 7-31-2018 11:48:43; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_ISystemSupport_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; void (*abort)(xdc_CString str); void (*exit)(xdc_Int stat); void (*flush)(void); void (*putch)(xdc_Char ch); xdc_Bool (*ready)(void); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base xdc_runtime_ISystemSupport_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* Module_id */ static inline xdc_runtime_Types_ModuleId xdc_runtime_ISystemSupport_Module_id(xdc_runtime_ISystemSupport_Module mod); static inline xdc_runtime_Types_ModuleId xdc_runtime_ISystemSupport_Module_id(xdc_runtime_ISystemSupport_Module mod) { return mod->__sysp->__mid; } /* abort */ static inline void xdc_runtime_ISystemSupport_abort(xdc_runtime_ISystemSupport_Module mod, xdc_CString str); static inline void xdc_runtime_ISystemSupport_abort( xdc_runtime_ISystemSupport_Module mod, xdc_CString str ) { mod->abort(str); } /* exit */ static inline void xdc_runtime_ISystemSupport_exit(xdc_runtime_ISystemSupport_Module mod, xdc_Int stat); static inline void xdc_runtime_ISystemSupport_exit( xdc_runtime_ISystemSupport_Module mod, xdc_Int stat ) { mod->exit(stat); } /* flush */ static inline void xdc_runtime_ISystemSupport_flush(xdc_runtime_ISystemSupport_Module mod); static inline void xdc_runtime_ISystemSupport_flush( xdc_runtime_ISystemSupport_Module mod ) { mod->flush(); } /* putch */ static inline void xdc_runtime_ISystemSupport_putch(xdc_runtime_ISystemSupport_Module mod, xdc_Char ch); static inline void xdc_runtime_ISystemSupport_putch( xdc_runtime_ISystemSupport_Module mod, xdc_Char ch ) { mod->putch(ch); } /* ready */ static inline xdc_Bool xdc_runtime_ISystemSupport_ready(xdc_runtime_ISystemSupport_Module mod); static inline xdc_Bool xdc_runtime_ISystemSupport_ready( xdc_runtime_ISystemSupport_Module mod ) { return mod->ready(); } /* * ======== FUNCTION SELECTORS ======== */ /* These functions return function pointers for module and instance functions. * The functions accept modules and instances declared as types defined in this * interface, but they return functions defined for the actual objects passed * as parameters. These functions are not invoked by any generated code or * XDCtools internal code. */ /* abort_{FxnT,fxnP} */ typedef void (*xdc_runtime_ISystemSupport_abort_FxnT)(xdc_CString str); static inline xdc_runtime_ISystemSupport_abort_FxnT xdc_runtime_ISystemSupport_abort_fxnP(xdc_runtime_ISystemSupport_Module mod); static inline xdc_runtime_ISystemSupport_abort_FxnT xdc_runtime_ISystemSupport_abort_fxnP(xdc_runtime_ISystemSupport_Module mod) { return (xdc_runtime_ISystemSupport_abort_FxnT)mod->abort; } /* exit_{FxnT,fxnP} */ typedef void (*xdc_runtime_ISystemSupport_exit_FxnT)(xdc_Int stat); static inline xdc_runtime_ISystemSupport_exit_FxnT xdc_runtime_ISystemSupport_exit_fxnP(xdc_runtime_ISystemSupport_Module mod); static inline xdc_runtime_ISystemSupport_exit_FxnT xdc_runtime_ISystemSupport_exit_fxnP(xdc_runtime_ISystemSupport_Module mod) { return (xdc_runtime_ISystemSupport_exit_FxnT)mod->exit; } /* flush_{FxnT,fxnP} */ typedef void (*xdc_runtime_ISystemSupport_flush_FxnT)(void); static inline xdc_runtime_ISystemSupport_flush_FxnT xdc_runtime_ISystemSupport_flush_fxnP(xdc_runtime_ISystemSupport_Module mod); static inline xdc_runtime_ISystemSupport_flush_FxnT xdc_runtime_ISystemSupport_flush_fxnP(xdc_runtime_ISystemSupport_Module mod) { return (xdc_runtime_ISystemSupport_flush_FxnT)mod->flush; } /* putch_{FxnT,fxnP} */ typedef void (*xdc_runtime_ISystemSupport_putch_FxnT)(xdc_Char ch); static inline xdc_runtime_ISystemSupport_putch_FxnT xdc_runtime_ISystemSupport_putch_fxnP(xdc_runtime_ISystemSupport_Module mod); static inline xdc_runtime_ISystemSupport_putch_FxnT xdc_runtime_ISystemSupport_putch_fxnP(xdc_runtime_ISystemSupport_Module mod) { return (xdc_runtime_ISystemSupport_putch_FxnT)mod->putch; } /* ready_{FxnT,fxnP} */ typedef xdc_Bool (*xdc_runtime_ISystemSupport_ready_FxnT)(void); static inline xdc_runtime_ISystemSupport_ready_FxnT xdc_runtime_ISystemSupport_ready_fxnP(xdc_runtime_ISystemSupport_Module mod); static inline xdc_runtime_ISystemSupport_ready_FxnT xdc_runtime_ISystemSupport_ready_fxnP(xdc_runtime_ISystemSupport_Module mod) { return (xdc_runtime_ISystemSupport_ready_FxnT)mod->ready; } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_System_SupportProxy_Module__diagsEnabled; extern const CT__xdc_runtime_System_SupportProxy_Module__diagsEnabled xdc_runtime_System_SupportProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_System_SupportProxy_Module__diagsIncluded; extern const CT__xdc_runtime_System_SupportProxy_Module__diagsIncluded xdc_runtime_System_SupportProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_System_SupportProxy_Module__diagsMask; extern const CT__xdc_runtime_System_SupportProxy_Module__diagsMask xdc_runtime_System_SupportProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_System_SupportProxy_Module__gateObj; extern const CT__xdc_runtime_System_SupportProxy_Module__gateObj xdc_runtime_System_SupportProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_System_SupportProxy_Module__gatePrms; extern const CT__xdc_runtime_System_SupportProxy_Module__gatePrms xdc_runtime_System_SupportProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_System_SupportProxy_Module__id; extern const CT__xdc_runtime_System_SupportProxy_Module__id xdc_runtime_System_SupportProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_System_SupportProxy_Module__loggerDefined; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerDefined xdc_runtime_System_SupportProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_System_SupportProxy_Module__loggerObj; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerObj xdc_runtime_System_SupportProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_System_SupportProxy_Module__loggerFxn0; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerFxn0 xdc_runtime_System_SupportProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_System_SupportProxy_Module__loggerFxn1; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerFxn1 xdc_runtime_System_SupportProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_System_SupportProxy_Module__loggerFxn2; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerFxn2 xdc_runtime_System_SupportProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_System_SupportProxy_Module__loggerFxn4; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerFxn4 xdc_runtime_System_SupportProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_System_SupportProxy_Module__loggerFxn8; extern const CT__xdc_runtime_System_SupportProxy_Module__loggerFxn8 xdc_runtime_System_SupportProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_System_SupportProxy_Object__count; extern const CT__xdc_runtime_System_SupportProxy_Object__count xdc_runtime_System_SupportProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_System_SupportProxy_Object__heap; extern const CT__xdc_runtime_System_SupportProxy_Object__heap xdc_runtime_System_SupportProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_System_SupportProxy_Object__sizeof; extern const CT__xdc_runtime_System_SupportProxy_Object__sizeof xdc_runtime_System_SupportProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_System_SupportProxy_Object__table; extern const CT__xdc_runtime_System_SupportProxy_Object__table xdc_runtime_System_SupportProxy_Object__table__C; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_System_SupportProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; void (*abort)(xdc_CString str); void (*exit)(xdc_Int stat); void (*flush)(void); void (*putch)(xdc_Char ch); xdc_Bool (*ready)(void); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const xdc_runtime_System_SupportProxy_Fxns__ xdc_runtime_System_SupportProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Handle__label__S */ extern xdc_runtime_Types_Label *xdc_runtime_System_SupportProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_System_SupportProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr xdc_runtime_System_SupportProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr xdc_runtime_System_SupportProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr xdc_runtime_System_SupportProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void xdc_runtime_System_SupportProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool xdc_runtime_System_SupportProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr xdc_runtime_System_SupportProxy_Proxy__delegate__S( void ); /* abort__E */ extern void xdc_runtime_System_SupportProxy_abort__E( xdc_CString str ); /* exit__E */ extern void xdc_runtime_System_SupportProxy_exit__E( xdc_Int stat ); /* flush__E */ extern void xdc_runtime_System_SupportProxy_flush__E( void ); /* putch__E */ extern void xdc_runtime_System_SupportProxy_putch__E( xdc_Char ch ); /* ready__E */ extern xdc_Bool xdc_runtime_System_SupportProxy_ready__E( void ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_ISystemSupport_Module xdc_runtime_System_SupportProxy_Module_upCast(void); static inline xdc_runtime_ISystemSupport_Module xdc_runtime_System_SupportProxy_Module_upCast(void) { return (xdc_runtime_ISystemSupport_Module)xdc_runtime_System_SupportProxy_Proxy__delegate__S(); } /* Module_to_xdc_runtime_ISystemSupport */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_System_SupportProxy_Module__id xdc_runtime_System_SupportProxy_Module_id(void); static inline CT__xdc_runtime_System_SupportProxy_Module__id xdc_runtime_System_SupportProxy_Module_id( void ) { return xdc_runtime_System_SupportProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Q_BLOCKING */ /* Q_PREEMPTING */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_System_Module_GateProxy_Module__diagsEnabled; extern const CT__xdc_runtime_System_Module_GateProxy_Module__diagsEnabled xdc_runtime_System_Module_GateProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_System_Module_GateProxy_Module__diagsIncluded; extern const CT__xdc_runtime_System_Module_GateProxy_Module__diagsIncluded xdc_runtime_System_Module_GateProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_System_Module_GateProxy_Module__diagsMask; extern const CT__xdc_runtime_System_Module_GateProxy_Module__diagsMask xdc_runtime_System_Module_GateProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_System_Module_GateProxy_Module__gateObj; extern const CT__xdc_runtime_System_Module_GateProxy_Module__gateObj xdc_runtime_System_Module_GateProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_System_Module_GateProxy_Module__gatePrms; extern const CT__xdc_runtime_System_Module_GateProxy_Module__gatePrms xdc_runtime_System_Module_GateProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_System_Module_GateProxy_Module__id; extern const CT__xdc_runtime_System_Module_GateProxy_Module__id xdc_runtime_System_Module_GateProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_System_Module_GateProxy_Module__loggerDefined; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerDefined xdc_runtime_System_Module_GateProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_System_Module_GateProxy_Module__loggerObj; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerObj xdc_runtime_System_Module_GateProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn0; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn0 xdc_runtime_System_Module_GateProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn1; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn1 xdc_runtime_System_Module_GateProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn2; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn2 xdc_runtime_System_Module_GateProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn4; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn4 xdc_runtime_System_Module_GateProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn8; extern const CT__xdc_runtime_System_Module_GateProxy_Module__loggerFxn8 xdc_runtime_System_Module_GateProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_System_Module_GateProxy_Object__count; extern const CT__xdc_runtime_System_Module_GateProxy_Object__count xdc_runtime_System_Module_GateProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_System_Module_GateProxy_Object__heap; extern const CT__xdc_runtime_System_Module_GateProxy_Object__heap xdc_runtime_System_Module_GateProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_System_Module_GateProxy_Object__sizeof; extern const CT__xdc_runtime_System_Module_GateProxy_Object__sizeof xdc_runtime_System_Module_GateProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_System_Module_GateProxy_Object__table; extern const CT__xdc_runtime_System_Module_GateProxy_Object__table xdc_runtime_System_Module_GateProxy_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct xdc_runtime_System_Module_GateProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct xdc_runtime_System_Module_GateProxy_Struct { const xdc_runtime_System_Module_GateProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct xdc_runtime_System_Module_GateProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*query)(xdc_Int qual); xdc_IArg (*enter)(xdc_runtime_System_Module_GateProxy_Handle inst); void (*leave)(xdc_runtime_System_Module_GateProxy_Handle inst, xdc_IArg key); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const xdc_runtime_System_Module_GateProxy_Fxns__ xdc_runtime_System_Module_GateProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern xdc_runtime_System_Module_GateProxy_Handle xdc_runtime_System_Module_GateProxy_create( const xdc_runtime_System_Module_GateProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void xdc_runtime_System_Module_GateProxy_delete(xdc_runtime_System_Module_GateProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *xdc_runtime_System_Module_GateProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_System_Module_GateProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr xdc_runtime_System_Module_GateProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr xdc_runtime_System_Module_GateProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr xdc_runtime_System_Module_GateProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void xdc_runtime_System_Module_GateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool xdc_runtime_System_Module_GateProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr xdc_runtime_System_Module_GateProxy_Proxy__delegate__S( void ); /* query__E */ extern xdc_Bool xdc_runtime_System_Module_GateProxy_query__E( xdc_Int qual ); /* enter__E */ extern xdc_IArg xdc_runtime_System_Module_GateProxy_enter__E( xdc_runtime_System_Module_GateProxy_Handle __inst ); /* leave__E */ extern void xdc_runtime_System_Module_GateProxy_leave__E( xdc_runtime_System_Module_GateProxy_Handle __inst, xdc_IArg key ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IGateProvider_Module xdc_runtime_System_Module_GateProxy_Module_upCast(void); static inline xdc_runtime_IGateProvider_Module xdc_runtime_System_Module_GateProxy_Module_upCast(void) { return (xdc_runtime_IGateProvider_Module)xdc_runtime_System_Module_GateProxy_Proxy__delegate__S(); } /* Module_to_xdc_runtime_IGateProvider */ /* Handle_upCast */ static inline xdc_runtime_IGateProvider_Handle xdc_runtime_System_Module_GateProxy_Handle_upCast(xdc_runtime_System_Module_GateProxy_Handle i); static inline xdc_runtime_IGateProvider_Handle xdc_runtime_System_Module_GateProxy_Handle_upCast(xdc_runtime_System_Module_GateProxy_Handle i) { return (xdc_runtime_IGateProvider_Handle)i; } /* Handle_to_xdc_runtime_IGateProvider */ /* Handle_downCast */ static inline xdc_runtime_System_Module_GateProxy_Handle xdc_runtime_System_Module_GateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i); static inline xdc_runtime_System_Module_GateProxy_Handle xdc_runtime_System_Module_GateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i) { xdc_runtime_IGateProvider_Handle i2 = (xdc_runtime_IGateProvider_Handle)i; if (xdc_runtime_System_Module_GateProxy_Proxy__abstract__S()) { return (xdc_runtime_System_Module_GateProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)xdc_runtime_System_Module_GateProxy_Proxy__delegate__S()) ? (xdc_runtime_System_Module_GateProxy_Handle)i : (xdc_runtime_System_Module_GateProxy_Handle)0; } /* Handle_from_xdc_runtime_IGateProvider */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_System_Module_GateProxy_Module__id xdc_runtime_System_Module_GateProxy_Module_id(void); static inline CT__xdc_runtime_System_Module_GateProxy_Module__id xdc_runtime_System_Module_GateProxy_Module_id( void ) { return xdc_runtime_System_Module_GateProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void xdc_runtime_System_Module_GateProxy_Params_init(xdc_runtime_System_Module_GateProxy_Params *prms); static inline void xdc_runtime_System_Module_GateProxy_Params_init( xdc_runtime_System_Module_GateProxy_Params *prms ) { if (prms != 0) { xdc_runtime_System_Module_GateProxy_Params__init__S(prms, 0, sizeof(xdc_runtime_System_Module_GateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void xdc_runtime_System_Module_GateProxy_Params_copy(xdc_runtime_System_Module_GateProxy_Params *dst, const xdc_runtime_System_Module_GateProxy_Params *src); static inline void xdc_runtime_System_Module_GateProxy_Params_copy(xdc_runtime_System_Module_GateProxy_Params *dst, const xdc_runtime_System_Module_GateProxy_Params *src) { if (dst != 0) { xdc_runtime_System_Module_GateProxy_Params__init__S(dst, (const void *)src, sizeof(xdc_runtime_System_Module_GateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* AtexitHandler */ typedef void (*xdc_runtime_System_AtexitHandler)(xdc_Int arg1); /* STATUS_UNKNOWN */ /* AbortFxn */ typedef void (*xdc_runtime_System_AbortFxn)(void); /* ExitFxn */ typedef void (*xdc_runtime_System_ExitFxn)(xdc_Int arg1); /* * ======== INTERNAL DEFINITIONS ======== */ /* ParseData */ struct xdc_runtime_System_ParseData { xdc_Int width; xdc_Bool lFlag; xdc_Bool lJust; xdc_Int precis; xdc_UInt len; xdc_Int zpad; xdc_Char *end; xdc_Bool aFlag; xdc_Char *ptr; }; /* ExtendFxn */ typedef xdc_Int (*xdc_runtime_System_ExtendFxn)(xdc_Char** arg1, xdc_CString* arg2, xdc_VaList* arg3, xdc_runtime_System_ParseData* arg4); /* Module_State */ typedef xdc_runtime_System_AtexitHandler __T1_xdc_runtime_System_Module_State__atexitHandlers; typedef xdc_runtime_System_AtexitHandler *ARRAY1_xdc_runtime_System_Module_State__atexitHandlers; typedef const xdc_runtime_System_AtexitHandler *CARRAY1_xdc_runtime_System_Module_State__atexitHandlers; typedef ARRAY1_xdc_runtime_System_Module_State__atexitHandlers __TA_xdc_runtime_System_Module_State__atexitHandlers; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_System_Module__diagsEnabled; extern const CT__xdc_runtime_System_Module__diagsEnabled xdc_runtime_System_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_System_Module__diagsIncluded; extern const CT__xdc_runtime_System_Module__diagsIncluded xdc_runtime_System_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_System_Module__diagsMask; extern const CT__xdc_runtime_System_Module__diagsMask xdc_runtime_System_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_System_Module__gateObj; extern const CT__xdc_runtime_System_Module__gateObj xdc_runtime_System_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_System_Module__gatePrms; extern const CT__xdc_runtime_System_Module__gatePrms xdc_runtime_System_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_System_Module__id; extern const CT__xdc_runtime_System_Module__id xdc_runtime_System_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_System_Module__loggerDefined; extern const CT__xdc_runtime_System_Module__loggerDefined xdc_runtime_System_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_System_Module__loggerObj; extern const CT__xdc_runtime_System_Module__loggerObj xdc_runtime_System_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_System_Module__loggerFxn0; extern const CT__xdc_runtime_System_Module__loggerFxn0 xdc_runtime_System_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_System_Module__loggerFxn1; extern const CT__xdc_runtime_System_Module__loggerFxn1 xdc_runtime_System_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_System_Module__loggerFxn2; extern const CT__xdc_runtime_System_Module__loggerFxn2 xdc_runtime_System_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_System_Module__loggerFxn4; extern const CT__xdc_runtime_System_Module__loggerFxn4 xdc_runtime_System_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_System_Module__loggerFxn8; extern const CT__xdc_runtime_System_Module__loggerFxn8 xdc_runtime_System_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_System_Object__count; extern const CT__xdc_runtime_System_Object__count xdc_runtime_System_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_System_Object__heap; extern const CT__xdc_runtime_System_Object__heap xdc_runtime_System_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_System_Object__sizeof; extern const CT__xdc_runtime_System_Object__sizeof xdc_runtime_System_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_System_Object__table; extern const CT__xdc_runtime_System_Object__table xdc_runtime_System_Object__table__C; /* A_cannotFitIntoArg */ typedef xdc_runtime_Assert_Id CT__xdc_runtime_System_A_cannotFitIntoArg; extern const CT__xdc_runtime_System_A_cannotFitIntoArg xdc_runtime_System_A_cannotFitIntoArg__C; /* maxAtexitHandlers */ typedef xdc_Int CT__xdc_runtime_System_maxAtexitHandlers; extern const CT__xdc_runtime_System_maxAtexitHandlers xdc_runtime_System_maxAtexitHandlers__C; /* abortFxn */ typedef xdc_runtime_System_AbortFxn CT__xdc_runtime_System_abortFxn; extern const CT__xdc_runtime_System_abortFxn xdc_runtime_System_abortFxn__C; /* exitFxn */ typedef xdc_runtime_System_ExitFxn CT__xdc_runtime_System_exitFxn; extern const CT__xdc_runtime_System_exitFxn xdc_runtime_System_exitFxn__C; /* extendFxn */ typedef xdc_runtime_System_ExtendFxn CT__xdc_runtime_System_extendFxn; extern const CT__xdc_runtime_System_extendFxn xdc_runtime_System_extendFxn__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int xdc_runtime_System_Module_startup__E( xdc_Int state ); extern xdc_Int xdc_runtime_System_Module_startup__F( xdc_Int state ); /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_System_Module__startupDone__S( void ); /* abort__E */ extern void xdc_runtime_System_abort__E( xdc_CString str ); /* abortStd__E */ extern void xdc_runtime_System_abortStd__E( void ); /* abortSpin__E */ extern void xdc_runtime_System_abortSpin__E( void ); /* atexit__E */ extern xdc_Bool xdc_runtime_System_atexit__E( xdc_runtime_System_AtexitHandler handler ); /* exit__E */ extern void xdc_runtime_System_exit__E( xdc_Int stat ); /* exitStd__E */ extern void xdc_runtime_System_exitStd__E( xdc_Int stat ); /* exitSpin__E */ extern void xdc_runtime_System_exitSpin__E( xdc_Int stat ); /* processAtExit__E */ extern void xdc_runtime_System_processAtExit__E( xdc_Int stat ); /* putch__E */ extern void xdc_runtime_System_putch__E( xdc_Char ch ); /* flush__E */ extern void xdc_runtime_System_flush__E( void ); /* printf__E */ extern xdc_Int xdc_runtime_System_printf__E( xdc_CString fmt, ... ); extern xdc_Int xdc_runtime_System_printf_va__E( xdc_CString fmt, va_list _va ); extern xdc_Int xdc_runtime_System_printf_va__F( xdc_CString fmt, va_list _va ); /* aprintf__E */ extern xdc_Int xdc_runtime_System_aprintf__E( xdc_CString fmt, ... ); extern xdc_Int xdc_runtime_System_aprintf_va__E( xdc_CString fmt, va_list _va ); extern xdc_Int xdc_runtime_System_aprintf_va__F( xdc_CString fmt, va_list _va ); /* sprintf__E */ extern xdc_Int xdc_runtime_System_sprintf__E( xdc_Char buf[], xdc_CString fmt, ... ); extern xdc_Int xdc_runtime_System_sprintf_va__E( xdc_Char buf[], xdc_CString fmt, va_list _va ); extern xdc_Int xdc_runtime_System_sprintf_va__F( xdc_Char buf[], xdc_CString fmt, va_list _va ); /* asprintf__E */ extern xdc_Int xdc_runtime_System_asprintf__E( xdc_Char buf[], xdc_CString fmt, ... ); extern xdc_Int xdc_runtime_System_asprintf_va__E( xdc_Char buf[], xdc_CString fmt, va_list _va ); extern xdc_Int xdc_runtime_System_asprintf_va__F( xdc_Char buf[], xdc_CString fmt, va_list _va ); /* vprintf__E */ extern xdc_Int xdc_runtime_System_vprintf__E( xdc_CString fmt, xdc_VaList va ); /* avprintf__E */ extern xdc_Int xdc_runtime_System_avprintf__E( xdc_CString fmt, xdc_VaList va ); /* vsprintf__E */ extern xdc_Int xdc_runtime_System_vsprintf__E( xdc_Char buf[], xdc_CString fmt, xdc_VaList va ); /* avsprintf__E */ extern xdc_Int xdc_runtime_System_avsprintf__E( xdc_Char buf[], xdc_CString fmt, xdc_VaList va ); /* snprintf__E */ extern xdc_Int xdc_runtime_System_snprintf__E( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, ... ); extern xdc_Int xdc_runtime_System_snprintf_va__E( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, va_list _va ); extern xdc_Int xdc_runtime_System_snprintf_va__F( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, va_list _va ); /* vsnprintf__E */ extern xdc_Int xdc_runtime_System_vsnprintf__E( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, xdc_VaList va ); /* printfExtend__I */ extern xdc_Int xdc_runtime_System_printfExtend__I( xdc_Char **bufp, xdc_CString *fmt, xdc_VaList *va, xdc_runtime_System_ParseData *parse ); /* doPrint__I */ extern xdc_Int xdc_runtime_System_doPrint__I( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, xdc_VaList *pva, xdc_Bool aFlag ); /* lastFxn__I */ extern void xdc_runtime_System_lastFxn__I( void ); /* putchar__I */ extern void xdc_runtime_System_putchar__I( xdc_Char **bufp, xdc_Char ch, xdc_SizeT *n ); /* rtsExit__I */ extern void xdc_runtime_System_rtsExit__I( void ); /* atexitDone__I */ extern xdc_Bool xdc_runtime_System_atexitDone__I( void ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_System_Module__id xdc_runtime_System_Module_id(void); static inline CT__xdc_runtime_System_Module__id xdc_runtime_System_Module_id( void ) { return xdc_runtime_System_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_System_Module_hasMask(void); static inline xdc_Bool xdc_runtime_System_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_System_Module__diagsMask__C != (CT__xdc_runtime_System_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_System_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_System_Module_getMask(void) { return (xdc_runtime_System_Module__diagsMask__C != (CT__xdc_runtime_System_Module__diagsMask)0) ? *xdc_runtime_System_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_System_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_System_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_System_Module__diagsMask__C != (CT__xdc_runtime_System_Module__diagsMask)0) { *xdc_runtime_System_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2012-2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.BIOS ======== */ typedef struct ti_sysbios_BIOS_intSize ti_sysbios_BIOS_intSize; typedef struct ti_sysbios_BIOS_Module_State ti_sysbios_BIOS_Module_State; /* * ======== module ti.sysbios.BIOS_RtsGateProxy ======== */ typedef struct ti_sysbios_BIOS_RtsGateProxy_Fxns__ ti_sysbios_BIOS_RtsGateProxy_Fxns__; typedef const struct ti_sysbios_BIOS_RtsGateProxy_Fxns__* ti_sysbios_BIOS_RtsGateProxy_Module; typedef struct ti_sysbios_BIOS_RtsGateProxy_Params ti_sysbios_BIOS_RtsGateProxy_Params; typedef struct xdc_runtime_IGateProvider___Object *ti_sysbios_BIOS_RtsGateProxy_Handle; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Q_BLOCKING */ /* Q_PREEMPTING */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_BIOS_RtsGateProxy_Module__diagsEnabled; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__diagsEnabled ti_sysbios_BIOS_RtsGateProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_BIOS_RtsGateProxy_Module__diagsIncluded; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__diagsIncluded ti_sysbios_BIOS_RtsGateProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_BIOS_RtsGateProxy_Module__diagsMask; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__diagsMask ti_sysbios_BIOS_RtsGateProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_BIOS_RtsGateProxy_Module__gateObj; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__gateObj ti_sysbios_BIOS_RtsGateProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_BIOS_RtsGateProxy_Module__gatePrms; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__gatePrms ti_sysbios_BIOS_RtsGateProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_BIOS_RtsGateProxy_Module__id; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__id ti_sysbios_BIOS_RtsGateProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerDefined; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerDefined ti_sysbios_BIOS_RtsGateProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerObj; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerObj ti_sysbios_BIOS_RtsGateProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn0; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn0 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn1; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn1 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn2; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn2 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn4; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn4 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn8; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn8 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_BIOS_RtsGateProxy_Object__count; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Object__count ti_sysbios_BIOS_RtsGateProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_BIOS_RtsGateProxy_Object__heap; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Object__heap ti_sysbios_BIOS_RtsGateProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_BIOS_RtsGateProxy_Object__sizeof; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Object__sizeof ti_sysbios_BIOS_RtsGateProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_BIOS_RtsGateProxy_Object__table; extern const CT__ti_sysbios_BIOS_RtsGateProxy_Object__table ti_sysbios_BIOS_RtsGateProxy_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_BIOS_RtsGateProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_BIOS_RtsGateProxy_Struct { const ti_sysbios_BIOS_RtsGateProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_BIOS_RtsGateProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*query)(xdc_Int qual); xdc_IArg (*enter)(ti_sysbios_BIOS_RtsGateProxy_Handle inst); void (*leave)(ti_sysbios_BIOS_RtsGateProxy_Handle inst, xdc_IArg key); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_BIOS_RtsGateProxy_Fxns__ ti_sysbios_BIOS_RtsGateProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern ti_sysbios_BIOS_RtsGateProxy_Handle ti_sysbios_BIOS_RtsGateProxy_create( const ti_sysbios_BIOS_RtsGateProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_BIOS_RtsGateProxy_delete(ti_sysbios_BIOS_RtsGateProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_BIOS_RtsGateProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_BIOS_RtsGateProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_BIOS_RtsGateProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_BIOS_RtsGateProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_BIOS_RtsGateProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_BIOS_RtsGateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool ti_sysbios_BIOS_RtsGateProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr ti_sysbios_BIOS_RtsGateProxy_Proxy__delegate__S( void ); /* query__E */ extern xdc_Bool ti_sysbios_BIOS_RtsGateProxy_query__E( xdc_Int qual ); /* enter__E */ extern xdc_IArg ti_sysbios_BIOS_RtsGateProxy_enter__E( ti_sysbios_BIOS_RtsGateProxy_Handle __inst ); /* leave__E */ extern void ti_sysbios_BIOS_RtsGateProxy_leave__E( ti_sysbios_BIOS_RtsGateProxy_Handle __inst, xdc_IArg key ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IGateProvider_Module ti_sysbios_BIOS_RtsGateProxy_Module_upCast(void); static inline xdc_runtime_IGateProvider_Module ti_sysbios_BIOS_RtsGateProxy_Module_upCast(void) { return (xdc_runtime_IGateProvider_Module)ti_sysbios_BIOS_RtsGateProxy_Proxy__delegate__S(); } /* Module_to_xdc_runtime_IGateProvider */ /* Handle_upCast */ static inline xdc_runtime_IGateProvider_Handle ti_sysbios_BIOS_RtsGateProxy_Handle_upCast(ti_sysbios_BIOS_RtsGateProxy_Handle i); static inline xdc_runtime_IGateProvider_Handle ti_sysbios_BIOS_RtsGateProxy_Handle_upCast(ti_sysbios_BIOS_RtsGateProxy_Handle i) { return (xdc_runtime_IGateProvider_Handle)i; } /* Handle_to_xdc_runtime_IGateProvider */ /* Handle_downCast */ static inline ti_sysbios_BIOS_RtsGateProxy_Handle ti_sysbios_BIOS_RtsGateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i); static inline ti_sysbios_BIOS_RtsGateProxy_Handle ti_sysbios_BIOS_RtsGateProxy_Handle_downCast(xdc_runtime_IGateProvider_Handle i) { xdc_runtime_IGateProvider_Handle i2 = (xdc_runtime_IGateProvider_Handle)i; if (ti_sysbios_BIOS_RtsGateProxy_Proxy__abstract__S()) { return (ti_sysbios_BIOS_RtsGateProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)ti_sysbios_BIOS_RtsGateProxy_Proxy__delegate__S()) ? (ti_sysbios_BIOS_RtsGateProxy_Handle)i : (ti_sysbios_BIOS_RtsGateProxy_Handle)0; } /* Handle_from_xdc_runtime_IGateProvider */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_BIOS_RtsGateProxy_Module__id ti_sysbios_BIOS_RtsGateProxy_Module_id(void); static inline CT__ti_sysbios_BIOS_RtsGateProxy_Module__id ti_sysbios_BIOS_RtsGateProxy_Module_id( void ) { return ti_sysbios_BIOS_RtsGateProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void ti_sysbios_BIOS_RtsGateProxy_Params_init(ti_sysbios_BIOS_RtsGateProxy_Params *prms); static inline void ti_sysbios_BIOS_RtsGateProxy_Params_init( ti_sysbios_BIOS_RtsGateProxy_Params *prms ) { if (prms != 0) { ti_sysbios_BIOS_RtsGateProxy_Params__init__S(prms, 0, sizeof(ti_sysbios_BIOS_RtsGateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_BIOS_RtsGateProxy_Params_copy(ti_sysbios_BIOS_RtsGateProxy_Params *dst, const ti_sysbios_BIOS_RtsGateProxy_Params *src); static inline void ti_sysbios_BIOS_RtsGateProxy_Params_copy(ti_sysbios_BIOS_RtsGateProxy_Params *dst, const ti_sysbios_BIOS_RtsGateProxy_Params *src) { if (dst != 0) { ti_sysbios_BIOS_RtsGateProxy_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_BIOS_RtsGateProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* ThreadType */ enum ti_sysbios_BIOS_ThreadType { ti_sysbios_BIOS_ThreadType_Hwi, ti_sysbios_BIOS_ThreadType_Swi, ti_sysbios_BIOS_ThreadType_Task, ti_sysbios_BIOS_ThreadType_Main }; typedef enum ti_sysbios_BIOS_ThreadType ti_sysbios_BIOS_ThreadType; /* RtsLockType */ enum ti_sysbios_BIOS_RtsLockType { ti_sysbios_BIOS_NoLocking, ti_sysbios_BIOS_GateHwi, ti_sysbios_BIOS_GateSwi, ti_sysbios_BIOS_GateMutex, ti_sysbios_BIOS_GateMutexPri }; typedef enum ti_sysbios_BIOS_RtsLockType ti_sysbios_BIOS_RtsLockType; /* LibType */ enum ti_sysbios_BIOS_LibType { ti_sysbios_BIOS_LibType_Instrumented, ti_sysbios_BIOS_LibType_NonInstrumented, ti_sysbios_BIOS_LibType_Custom, ti_sysbios_BIOS_LibType_Debug }; typedef enum ti_sysbios_BIOS_LibType ti_sysbios_BIOS_LibType; /* WAIT_FOREVER */ /* NO_WAIT */ /* StartupFuncPtr */ typedef void (*ti_sysbios_BIOS_StartupFuncPtr)(void ); /* version */ /* * ======== INTERNAL DEFINITIONS ======== */ /* intSize */ struct ti_sysbios_BIOS_intSize { xdc_Int intSize; }; /* StartFuncPtr */ typedef void (*ti_sysbios_BIOS_StartFuncPtr)(void ); /* ExitFuncPtr */ typedef void (*ti_sysbios_BIOS_ExitFuncPtr)(xdc_Int arg1); /* Module_State */ typedef ti_sysbios_BIOS_ThreadType __T1_ti_sysbios_BIOS_Module_State__smpThreadType; typedef ti_sysbios_BIOS_ThreadType *ARRAY1_ti_sysbios_BIOS_Module_State__smpThreadType; typedef const ti_sysbios_BIOS_ThreadType *CARRAY1_ti_sysbios_BIOS_Module_State__smpThreadType; typedef ARRAY1_ti_sysbios_BIOS_Module_State__smpThreadType __TA_ti_sysbios_BIOS_Module_State__smpThreadType; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_BIOS_Module__diagsEnabled; extern const CT__ti_sysbios_BIOS_Module__diagsEnabled ti_sysbios_BIOS_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_BIOS_Module__diagsIncluded; extern const CT__ti_sysbios_BIOS_Module__diagsIncluded ti_sysbios_BIOS_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_BIOS_Module__diagsMask; extern const CT__ti_sysbios_BIOS_Module__diagsMask ti_sysbios_BIOS_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_BIOS_Module__gateObj; extern const CT__ti_sysbios_BIOS_Module__gateObj ti_sysbios_BIOS_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_BIOS_Module__gatePrms; extern const CT__ti_sysbios_BIOS_Module__gatePrms ti_sysbios_BIOS_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_BIOS_Module__id; extern const CT__ti_sysbios_BIOS_Module__id ti_sysbios_BIOS_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_BIOS_Module__loggerDefined; extern const CT__ti_sysbios_BIOS_Module__loggerDefined ti_sysbios_BIOS_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_BIOS_Module__loggerObj; extern const CT__ti_sysbios_BIOS_Module__loggerObj ti_sysbios_BIOS_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_BIOS_Module__loggerFxn0; extern const CT__ti_sysbios_BIOS_Module__loggerFxn0 ti_sysbios_BIOS_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_BIOS_Module__loggerFxn1; extern const CT__ti_sysbios_BIOS_Module__loggerFxn1 ti_sysbios_BIOS_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_BIOS_Module__loggerFxn2; extern const CT__ti_sysbios_BIOS_Module__loggerFxn2 ti_sysbios_BIOS_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_BIOS_Module__loggerFxn4; extern const CT__ti_sysbios_BIOS_Module__loggerFxn4 ti_sysbios_BIOS_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_BIOS_Module__loggerFxn8; extern const CT__ti_sysbios_BIOS_Module__loggerFxn8 ti_sysbios_BIOS_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_BIOS_Object__count; extern const CT__ti_sysbios_BIOS_Object__count ti_sysbios_BIOS_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_BIOS_Object__heap; extern const CT__ti_sysbios_BIOS_Object__heap ti_sysbios_BIOS_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_BIOS_Object__sizeof; extern const CT__ti_sysbios_BIOS_Object__sizeof ti_sysbios_BIOS_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_BIOS_Object__table; extern const CT__ti_sysbios_BIOS_Object__table ti_sysbios_BIOS_Object__table__C; /* smpEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_smpEnabled; extern const CT__ti_sysbios_BIOS_smpEnabled ti_sysbios_BIOS_smpEnabled__C; /* mpeEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_mpeEnabled; extern const CT__ti_sysbios_BIOS_mpeEnabled ti_sysbios_BIOS_mpeEnabled__C; /* cpuFreq */ typedef xdc_runtime_Types_FreqHz CT__ti_sysbios_BIOS_cpuFreq; extern const CT__ti_sysbios_BIOS_cpuFreq ti_sysbios_BIOS_cpuFreq__C; /* runtimeCreatesEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_runtimeCreatesEnabled; extern const CT__ti_sysbios_BIOS_runtimeCreatesEnabled ti_sysbios_BIOS_runtimeCreatesEnabled__C; /* taskEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_taskEnabled; extern const CT__ti_sysbios_BIOS_taskEnabled ti_sysbios_BIOS_taskEnabled__C; /* swiEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_swiEnabled; extern const CT__ti_sysbios_BIOS_swiEnabled ti_sysbios_BIOS_swiEnabled__C; /* clockEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_clockEnabled; extern const CT__ti_sysbios_BIOS_clockEnabled ti_sysbios_BIOS_clockEnabled__C; /* defaultKernelHeapInstance */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_BIOS_defaultKernelHeapInstance; extern const CT__ti_sysbios_BIOS_defaultKernelHeapInstance ti_sysbios_BIOS_defaultKernelHeapInstance__C; /* kernelHeapSize */ typedef xdc_SizeT CT__ti_sysbios_BIOS_kernelHeapSize; extern const CT__ti_sysbios_BIOS_kernelHeapSize ti_sysbios_BIOS_kernelHeapSize__C; /* kernelHeapSection */ typedef xdc_String CT__ti_sysbios_BIOS_kernelHeapSection; extern const CT__ti_sysbios_BIOS_kernelHeapSection ti_sysbios_BIOS_kernelHeapSection__C; /* heapSize */ typedef xdc_SizeT CT__ti_sysbios_BIOS_heapSize; extern const CT__ti_sysbios_BIOS_heapSize ti_sysbios_BIOS_heapSize__C; /* heapSection */ typedef xdc_String CT__ti_sysbios_BIOS_heapSection; extern const CT__ti_sysbios_BIOS_heapSection ti_sysbios_BIOS_heapSection__C; /* heapTrackEnabled */ typedef xdc_Bool CT__ti_sysbios_BIOS_heapTrackEnabled; extern const CT__ti_sysbios_BIOS_heapTrackEnabled ti_sysbios_BIOS_heapTrackEnabled__C; /* setupSecureContext */ typedef xdc_Bool CT__ti_sysbios_BIOS_setupSecureContext; extern const CT__ti_sysbios_BIOS_setupSecureContext ti_sysbios_BIOS_setupSecureContext__C; /* useSK */ typedef xdc_Bool CT__ti_sysbios_BIOS_useSK; extern const CT__ti_sysbios_BIOS_useSK ti_sysbios_BIOS_useSK__C; /* installedErrorHook */ typedef void (*CT__ti_sysbios_BIOS_installedErrorHook)(xdc_runtime_Error_Block* arg1); extern const CT__ti_sysbios_BIOS_installedErrorHook ti_sysbios_BIOS_installedErrorHook__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_BIOS_Module__startupDone__S( void ); /* linkedWithIncorrectBootLibrary__E */ extern void ti_sysbios_BIOS_linkedWithIncorrectBootLibrary__E( void ); /* start__E */ extern void ti_sysbios_BIOS_start__E( void ); /* exit__E */ extern void ti_sysbios_BIOS_exit__E( xdc_Int stat ); /* getThreadType__E */ extern ti_sysbios_BIOS_ThreadType ti_sysbios_BIOS_getThreadType__E( void ); /* setThreadType__E */ extern ti_sysbios_BIOS_ThreadType ti_sysbios_BIOS_setThreadType__E( ti_sysbios_BIOS_ThreadType ttype ); /* setCpuFreq__E */ extern void ti_sysbios_BIOS_setCpuFreq__E( xdc_runtime_Types_FreqHz *freq ); /* getCpuFreq__E */ extern void ti_sysbios_BIOS_getCpuFreq__E( xdc_runtime_Types_FreqHz *freq ); /* errorRaiseHook__I */ extern void ti_sysbios_BIOS_errorRaiseHook__I( xdc_runtime_Error_Block *eb ); /* startFunc__I */ extern void ti_sysbios_BIOS_startFunc__I( void ); /* atExitFunc__I */ extern void ti_sysbios_BIOS_atExitFunc__I( xdc_Int stat ); /* exitFunc__I */ extern void ti_sysbios_BIOS_exitFunc__I( xdc_Int stat ); /* registerRTSLock__I */ extern void ti_sysbios_BIOS_registerRTSLock__I( void ); /* removeRTSLock__I */ extern void ti_sysbios_BIOS_removeRTSLock__I( void ); /* rtsLock__I */ extern void ti_sysbios_BIOS_rtsLock__I( void ); /* rtsUnlock__I */ extern void ti_sysbios_BIOS_rtsUnlock__I( void ); /* nullFunc__I */ extern void ti_sysbios_BIOS_nullFunc__I( void ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_BIOS_Module__id ti_sysbios_BIOS_Module_id(void); static inline CT__ti_sysbios_BIOS_Module__id ti_sysbios_BIOS_Module_id( void ) { return ti_sysbios_BIOS_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_BIOS_Module_hasMask(void); static inline xdc_Bool ti_sysbios_BIOS_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_BIOS_Module__diagsMask__C != (CT__ti_sysbios_BIOS_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_BIOS_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_BIOS_Module_getMask(void) { return (ti_sysbios_BIOS_Module__diagsMask__C != (CT__ti_sysbios_BIOS_Module__diagsMask)0) ? *ti_sysbios_BIOS_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_BIOS_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_BIOS_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_BIOS_Module__diagsMask__C != (CT__ti_sysbios_BIOS_Module__diagsMask)0) { *ti_sysbios_BIOS_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2012-2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2012-2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.knl.Clock ======== */ typedef struct ti_sysbios_knl_Clock_Module_State ti_sysbios_knl_Clock_Module_State; typedef struct ti_sysbios_knl_Clock_Params ti_sysbios_knl_Clock_Params; typedef struct ti_sysbios_knl_Clock_Object ti_sysbios_knl_Clock_Object; typedef struct ti_sysbios_knl_Clock_Struct ti_sysbios_knl_Clock_Struct; typedef ti_sysbios_knl_Clock_Object* ti_sysbios_knl_Clock_Handle; typedef struct ti_sysbios_knl_Clock_Object__ ti_sysbios_knl_Clock_Instance_State; typedef ti_sysbios_knl_Clock_Object* ti_sysbios_knl_Clock_Instance; /* * ======== module ti.sysbios.knl.Idle ======== */ /* * ======== module ti.sysbios.knl.Intrinsics ======== */ typedef struct ti_sysbios_knl_Intrinsics_Fxns__ ti_sysbios_knl_Intrinsics_Fxns__; typedef const struct ti_sysbios_knl_Intrinsics_Fxns__* ti_sysbios_knl_Intrinsics_Module; /* * ======== module ti.sysbios.knl.Event ======== */ typedef struct ti_sysbios_knl_Event_PendElem ti_sysbios_knl_Event_PendElem; typedef struct ti_sysbios_knl_Event_Params ti_sysbios_knl_Event_Params; typedef struct ti_sysbios_knl_Event_Object ti_sysbios_knl_Event_Object; typedef struct ti_sysbios_knl_Event_Struct ti_sysbios_knl_Event_Struct; typedef ti_sysbios_knl_Event_Object* ti_sysbios_knl_Event_Handle; typedef struct ti_sysbios_knl_Event_Object__ ti_sysbios_knl_Event_Instance_State; typedef ti_sysbios_knl_Event_Object* ti_sysbios_knl_Event_Instance; /* * ======== module ti.sysbios.knl.Mailbox ======== */ typedef struct ti_sysbios_knl_Mailbox_MbxElem ti_sysbios_knl_Mailbox_MbxElem; typedef struct ti_sysbios_knl_Mailbox_Params ti_sysbios_knl_Mailbox_Params; typedef struct ti_sysbios_knl_Mailbox_Object ti_sysbios_knl_Mailbox_Object; typedef struct ti_sysbios_knl_Mailbox_Struct ti_sysbios_knl_Mailbox_Struct; typedef ti_sysbios_knl_Mailbox_Object* ti_sysbios_knl_Mailbox_Handle; typedef struct ti_sysbios_knl_Mailbox_Object__ ti_sysbios_knl_Mailbox_Instance_State; typedef ti_sysbios_knl_Mailbox_Object* ti_sysbios_knl_Mailbox_Instance; /* * ======== module ti.sysbios.knl.Queue ======== */ typedef struct ti_sysbios_knl_Queue_Elem ti_sysbios_knl_Queue_Elem; typedef struct ti_sysbios_knl_Queue_Params ti_sysbios_knl_Queue_Params; typedef struct ti_sysbios_knl_Queue_Object ti_sysbios_knl_Queue_Object; typedef struct ti_sysbios_knl_Queue_Struct ti_sysbios_knl_Queue_Struct; typedef ti_sysbios_knl_Queue_Object* ti_sysbios_knl_Queue_Handle; typedef struct ti_sysbios_knl_Queue_Object__ ti_sysbios_knl_Queue_Instance_State; typedef ti_sysbios_knl_Queue_Object* ti_sysbios_knl_Queue_Instance; /* * ======== module ti.sysbios.knl.Semaphore ======== */ typedef struct ti_sysbios_knl_Semaphore_PendElem ti_sysbios_knl_Semaphore_PendElem; typedef struct ti_sysbios_knl_Semaphore_Params ti_sysbios_knl_Semaphore_Params; typedef struct ti_sysbios_knl_Semaphore_Object ti_sysbios_knl_Semaphore_Object; typedef struct ti_sysbios_knl_Semaphore_Struct ti_sysbios_knl_Semaphore_Struct; typedef ti_sysbios_knl_Semaphore_Object* ti_sysbios_knl_Semaphore_Handle; typedef struct ti_sysbios_knl_Semaphore_Object__ ti_sysbios_knl_Semaphore_Instance_State; typedef ti_sysbios_knl_Semaphore_Object* ti_sysbios_knl_Semaphore_Instance; /* * ======== module ti.sysbios.knl.Swi ======== */ typedef struct ti_sysbios_knl_Swi_HookSet ti_sysbios_knl_Swi_HookSet; typedef struct ti_sysbios_knl_Swi_Struct2__ ti_sysbios_knl_Swi_Struct2__; typedef struct ti_sysbios_knl_Swi_Module_State ti_sysbios_knl_Swi_Module_State; typedef struct ti_sysbios_knl_Swi_Params ti_sysbios_knl_Swi_Params; typedef struct ti_sysbios_knl_Swi_Object ti_sysbios_knl_Swi_Object; typedef struct ti_sysbios_knl_Swi_Struct ti_sysbios_knl_Swi_Struct; typedef ti_sysbios_knl_Swi_Object* ti_sysbios_knl_Swi_Handle; typedef struct ti_sysbios_knl_Swi_Object__ ti_sysbios_knl_Swi_Instance_State; typedef ti_sysbios_knl_Swi_Object* ti_sysbios_knl_Swi_Instance; /* * ======== module ti.sysbios.knl.Task ======== */ typedef struct ti_sysbios_knl_Task_Stat ti_sysbios_knl_Task_Stat; typedef struct ti_sysbios_knl_Task_HookSet ti_sysbios_knl_Task_HookSet; typedef struct ti_sysbios_knl_Task_PendElem ti_sysbios_knl_Task_PendElem; typedef struct ti_sysbios_knl_Task_Module_State ti_sysbios_knl_Task_Module_State; typedef struct ti_sysbios_knl_Task_RunQEntry ti_sysbios_knl_Task_RunQEntry; typedef struct ti_sysbios_knl_Task_Module_StateSmp ti_sysbios_knl_Task_Module_StateSmp; typedef struct ti_sysbios_knl_Task_Params ti_sysbios_knl_Task_Params; typedef struct ti_sysbios_knl_Task_Object ti_sysbios_knl_Task_Object; typedef struct ti_sysbios_knl_Task_Struct ti_sysbios_knl_Task_Struct; typedef ti_sysbios_knl_Task_Object* ti_sysbios_knl_Task_Handle; typedef struct ti_sysbios_knl_Task_Object__ ti_sysbios_knl_Task_Instance_State; typedef ti_sysbios_knl_Task_Object* ti_sysbios_knl_Task_Instance; /* * ======== module ti.sysbios.knl.Clock_TimerProxy ======== */ typedef struct ti_sysbios_knl_Clock_TimerProxy_Fxns__ ti_sysbios_knl_Clock_TimerProxy_Fxns__; typedef const struct ti_sysbios_knl_Clock_TimerProxy_Fxns__* ti_sysbios_knl_Clock_TimerProxy_Module; typedef struct ti_sysbios_knl_Clock_TimerProxy_Params ti_sysbios_knl_Clock_TimerProxy_Params; typedef struct ti_sysbios_interfaces_ITimer___Object *ti_sysbios_knl_Clock_TimerProxy_Handle; /* * ======== module ti.sysbios.knl.Intrinsics_SupportProxy ======== */ typedef struct ti_sysbios_knl_Intrinsics_SupportProxy_Fxns__ ti_sysbios_knl_Intrinsics_SupportProxy_Fxns__; typedef const struct ti_sysbios_knl_Intrinsics_SupportProxy_Fxns__* ti_sysbios_knl_Intrinsics_SupportProxy_Module; /* * ======== module ti.sysbios.knl.Task_SupportProxy ======== */ typedef struct ti_sysbios_knl_Task_SupportProxy_Fxns__ ti_sysbios_knl_Task_SupportProxy_Fxns__; typedef const struct ti_sysbios_knl_Task_SupportProxy_Fxns__* ti_sysbios_knl_Task_SupportProxy_Module; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== xdc_runtime_Log_Event ======== * Log_Event is an encoded type. Log Events are encoded on the target as * a 32-bit value: * * | format rope | module ID or mask | * | 31 ----- 16 | 15 ------------ 0 | * * The lower 16-bits contain either a mask or a module ID; when the event * is statically declared this field has a mask, when the event is passed * to an ILogger this field is the module ID of the module that generated * the event. * * The upper 16-bits are an ID (rope) that that identifies the format * string to use to render the event (and its arguments). */ typedef xdc_Bits32 xdc_runtime_Log_Event; /* * The following macros establish xdc.runtime.Main as the "default" * module for all sources files not part of a module. * * Module__MID - the module's ID (see Text.xs) * Module__LOGOBJ - the module's logger object * Module__LOGFXN0 - the module's logger's write0 function * Module__LOGFXN1 - the module's logger's write1 function * Module__LOGFXN2 - the module's logger's write2 function * Module__LOGFXN4 - the module's logger's write4 function * Module__LOGFXN8 - the module's logger's write8 function * Module__LOGDEF - 0 if the module has a logger, non-zero otherwise * * Only define these symbols for xdc.runtime.Main if this file is not one that * will be included in the Registry. This check ensures that Registry.h (which * similarly defines these Module__* symbols) can be included in any order * relative to other xdc.runtime headers. */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* CordAddr */ typedef xdc_runtime_Types_CordAddr xdc_runtime_Text_CordAddr; /* Label */ typedef xdc_runtime_Types_Label xdc_runtime_Text_Label; /* RopeId */ typedef xdc_runtime_Types_RopeId xdc_runtime_Text_RopeId; /* * ======== INTERNAL DEFINITIONS ======== */ /* Node */ struct xdc_runtime_Text_Node { xdc_runtime_Types_RopeId left; xdc_runtime_Types_RopeId right; }; /* RopeVisitor */ typedef xdc_Bool (*xdc_runtime_Text_RopeVisitor)(xdc_Ptr arg1, xdc_CString arg2); /* MatchVisState */ struct xdc_runtime_Text_MatchVisState { xdc_CString pat; xdc_UShort *lenp; xdc_Int res; }; /* PrintVisState */ struct xdc_runtime_Text_PrintVisState { xdc_Char **bufp; xdc_UShort len; xdc_Int res; }; /* VisitRopeFxn */ typedef void (*xdc_runtime_Text_VisitRopeFxn)(xdc_runtime_Text_RopeId arg1, xdc_Fxn arg2, xdc_Ptr arg3); /* VisitRopeFxn2 */ typedef void (*xdc_runtime_Text_VisitRopeFxn2)(xdc_runtime_Text_RopeId arg1, xdc_Fxn arg2, xdc_Ptr arg3, xdc_CString arg4[]); /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Text_Module__diagsEnabled; extern const CT__xdc_runtime_Text_Module__diagsEnabled xdc_runtime_Text_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Text_Module__diagsIncluded; extern const CT__xdc_runtime_Text_Module__diagsIncluded xdc_runtime_Text_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Text_Module__diagsMask; extern const CT__xdc_runtime_Text_Module__diagsMask xdc_runtime_Text_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Text_Module__gateObj; extern const CT__xdc_runtime_Text_Module__gateObj xdc_runtime_Text_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Text_Module__gatePrms; extern const CT__xdc_runtime_Text_Module__gatePrms xdc_runtime_Text_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Text_Module__id; extern const CT__xdc_runtime_Text_Module__id xdc_runtime_Text_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Text_Module__loggerDefined; extern const CT__xdc_runtime_Text_Module__loggerDefined xdc_runtime_Text_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Text_Module__loggerObj; extern const CT__xdc_runtime_Text_Module__loggerObj xdc_runtime_Text_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Text_Module__loggerFxn0; extern const CT__xdc_runtime_Text_Module__loggerFxn0 xdc_runtime_Text_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Text_Module__loggerFxn1; extern const CT__xdc_runtime_Text_Module__loggerFxn1 xdc_runtime_Text_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Text_Module__loggerFxn2; extern const CT__xdc_runtime_Text_Module__loggerFxn2 xdc_runtime_Text_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Text_Module__loggerFxn4; extern const CT__xdc_runtime_Text_Module__loggerFxn4 xdc_runtime_Text_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Text_Module__loggerFxn8; extern const CT__xdc_runtime_Text_Module__loggerFxn8 xdc_runtime_Text_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Text_Object__count; extern const CT__xdc_runtime_Text_Object__count xdc_runtime_Text_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Text_Object__heap; extern const CT__xdc_runtime_Text_Object__heap xdc_runtime_Text_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Text_Object__sizeof; extern const CT__xdc_runtime_Text_Object__sizeof xdc_runtime_Text_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Text_Object__table; extern const CT__xdc_runtime_Text_Object__table xdc_runtime_Text_Object__table__C; /* nameUnknown */ typedef xdc_String CT__xdc_runtime_Text_nameUnknown; extern const CT__xdc_runtime_Text_nameUnknown xdc_runtime_Text_nameUnknown__C; /* nameEmpty */ typedef xdc_String CT__xdc_runtime_Text_nameEmpty; extern const CT__xdc_runtime_Text_nameEmpty xdc_runtime_Text_nameEmpty__C; /* nameStatic */ typedef xdc_String CT__xdc_runtime_Text_nameStatic; extern const CT__xdc_runtime_Text_nameStatic xdc_runtime_Text_nameStatic__C; /* isLoaded */ typedef xdc_Bool CT__xdc_runtime_Text_isLoaded; extern const CT__xdc_runtime_Text_isLoaded xdc_runtime_Text_isLoaded__C; /* charTab */ typedef xdc_Char __T1_xdc_runtime_Text_charTab; typedef xdc_Char *ARRAY1_xdc_runtime_Text_charTab; typedef const xdc_Char *CARRAY1_xdc_runtime_Text_charTab; typedef CARRAY1_xdc_runtime_Text_charTab __TA_xdc_runtime_Text_charTab; typedef CARRAY1_xdc_runtime_Text_charTab CT__xdc_runtime_Text_charTab; extern const CT__xdc_runtime_Text_charTab xdc_runtime_Text_charTab__C; /* nodeTab */ typedef xdc_runtime_Text_Node __T1_xdc_runtime_Text_nodeTab; typedef xdc_runtime_Text_Node *ARRAY1_xdc_runtime_Text_nodeTab; typedef const xdc_runtime_Text_Node *CARRAY1_xdc_runtime_Text_nodeTab; typedef CARRAY1_xdc_runtime_Text_nodeTab __TA_xdc_runtime_Text_nodeTab; typedef CARRAY1_xdc_runtime_Text_nodeTab CT__xdc_runtime_Text_nodeTab; extern const CT__xdc_runtime_Text_nodeTab xdc_runtime_Text_nodeTab__C; /* charCnt */ typedef xdc_Int16 CT__xdc_runtime_Text_charCnt; extern const CT__xdc_runtime_Text_charCnt xdc_runtime_Text_charCnt__C; /* nodeCnt */ typedef xdc_Int16 CT__xdc_runtime_Text_nodeCnt; extern const CT__xdc_runtime_Text_nodeCnt xdc_runtime_Text_nodeCnt__C; /* unnamedModsLastId */ typedef xdc_UInt16 CT__xdc_runtime_Text_unnamedModsLastId; extern const CT__xdc_runtime_Text_unnamedModsLastId xdc_runtime_Text_unnamedModsLastId__C; /* registryModsLastId */ typedef xdc_UInt16 CT__xdc_runtime_Text_registryModsLastId; extern const CT__xdc_runtime_Text_registryModsLastId xdc_runtime_Text_registryModsLastId__C; /* visitRopeFxn */ typedef xdc_runtime_Text_VisitRopeFxn CT__xdc_runtime_Text_visitRopeFxn; extern const CT__xdc_runtime_Text_visitRopeFxn xdc_runtime_Text_visitRopeFxn__C; /* visitRopeFxn2 */ typedef xdc_runtime_Text_VisitRopeFxn2 CT__xdc_runtime_Text_visitRopeFxn2; extern const CT__xdc_runtime_Text_visitRopeFxn2 xdc_runtime_Text_visitRopeFxn2__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Text_Module__startupDone__S( void ); /* cordText__E */ extern xdc_String xdc_runtime_Text_cordText__E( xdc_runtime_Text_CordAddr cord ); /* ropeText__E */ extern xdc_CString xdc_runtime_Text_ropeText__E( xdc_runtime_Text_RopeId rope ); /* matchRope__E */ extern xdc_Int xdc_runtime_Text_matchRope__E( xdc_runtime_Text_RopeId rope, xdc_CString pat, xdc_UShort *lenp ); /* putLab__E */ extern xdc_Int xdc_runtime_Text_putLab__E( xdc_runtime_Types_Label *lab, xdc_Char **bufp, xdc_Int len ); /* putMod__E */ extern xdc_Int xdc_runtime_Text_putMod__E( xdc_runtime_Types_ModuleId mid, xdc_Char **bufp, xdc_Int len ); /* putSite__E */ extern xdc_Int xdc_runtime_Text_putSite__E( xdc_runtime_Types_Site *site, xdc_Char **bufp, xdc_Int len ); /* matchVisFxn__I */ extern xdc_Bool xdc_runtime_Text_matchVisFxn__I( xdc_Ptr p, xdc_CString s ); /* printVisFxn__I */ extern xdc_Bool xdc_runtime_Text_printVisFxn__I( xdc_Ptr p, xdc_CString s ); /* visitRope__I */ extern void xdc_runtime_Text_visitRope__I( xdc_runtime_Text_RopeId rope, xdc_Fxn visFxn, xdc_Ptr visState ); /* visitRope2__I */ extern void xdc_runtime_Text_visitRope2__I( xdc_runtime_Text_RopeId rope, xdc_Fxn visFxn, xdc_Ptr visState, xdc_CString stack[] ); /* xprintf__I */ extern xdc_Int xdc_runtime_Text_xprintf__I( xdc_Char **bufp, xdc_SizeT len, xdc_CString fmt, ... ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Text_Module__id xdc_runtime_Text_Module_id(void); static inline CT__xdc_runtime_Text_Module__id xdc_runtime_Text_Module_id( void ) { return xdc_runtime_Text_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Text_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Text_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Text_Module__diagsMask__C != (CT__xdc_runtime_Text_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Text_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Text_Module_getMask(void) { return (xdc_runtime_Text_Module__diagsMask__C != (CT__xdc_runtime_Text_Module__diagsMask)0) ? *xdc_runtime_Text_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Text_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Text_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Text_Module__diagsMask__C != (CT__xdc_runtime_Text_Module__diagsMask)0) { *xdc_runtime_Text_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* NUMARGS */ /* PRINTFID */ /* EventRec */ typedef xdc_IArg __T1_xdc_runtime_Log_EventRec__arg; typedef xdc_IArg ARRAY1_xdc_runtime_Log_EventRec__arg[8]; typedef xdc_IArg CARRAY1_xdc_runtime_Log_EventRec__arg[8]; typedef CARRAY1_xdc_runtime_Log_EventRec__arg __TA_xdc_runtime_Log_EventRec__arg; struct xdc_runtime_Log_EventRec { xdc_runtime_Types_Timestamp64 tstamp; xdc_Bits32 serial; xdc_runtime_Types_Event evt; __TA_xdc_runtime_Log_EventRec__arg arg; }; /* EventId */ typedef xdc_runtime_Types_RopeId xdc_runtime_Log_EventId; /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__xdc_runtime_Log_Module__diagsEnabled; extern const CT__xdc_runtime_Log_Module__diagsEnabled xdc_runtime_Log_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__xdc_runtime_Log_Module__diagsIncluded; extern const CT__xdc_runtime_Log_Module__diagsIncluded xdc_runtime_Log_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__xdc_runtime_Log_Module__diagsMask; extern const CT__xdc_runtime_Log_Module__diagsMask xdc_runtime_Log_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__xdc_runtime_Log_Module__gateObj; extern const CT__xdc_runtime_Log_Module__gateObj xdc_runtime_Log_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__xdc_runtime_Log_Module__gatePrms; extern const CT__xdc_runtime_Log_Module__gatePrms xdc_runtime_Log_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__xdc_runtime_Log_Module__id; extern const CT__xdc_runtime_Log_Module__id xdc_runtime_Log_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__xdc_runtime_Log_Module__loggerDefined; extern const CT__xdc_runtime_Log_Module__loggerDefined xdc_runtime_Log_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__xdc_runtime_Log_Module__loggerObj; extern const CT__xdc_runtime_Log_Module__loggerObj xdc_runtime_Log_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__xdc_runtime_Log_Module__loggerFxn0; extern const CT__xdc_runtime_Log_Module__loggerFxn0 xdc_runtime_Log_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__xdc_runtime_Log_Module__loggerFxn1; extern const CT__xdc_runtime_Log_Module__loggerFxn1 xdc_runtime_Log_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__xdc_runtime_Log_Module__loggerFxn2; extern const CT__xdc_runtime_Log_Module__loggerFxn2 xdc_runtime_Log_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__xdc_runtime_Log_Module__loggerFxn4; extern const CT__xdc_runtime_Log_Module__loggerFxn4 xdc_runtime_Log_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__xdc_runtime_Log_Module__loggerFxn8; extern const CT__xdc_runtime_Log_Module__loggerFxn8 xdc_runtime_Log_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__xdc_runtime_Log_Object__count; extern const CT__xdc_runtime_Log_Object__count xdc_runtime_Log_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__xdc_runtime_Log_Object__heap; extern const CT__xdc_runtime_Log_Object__heap xdc_runtime_Log_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__xdc_runtime_Log_Object__sizeof; extern const CT__xdc_runtime_Log_Object__sizeof xdc_runtime_Log_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__xdc_runtime_Log_Object__table; extern const CT__xdc_runtime_Log_Object__table xdc_runtime_Log_Object__table__C; /* L_construct */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_construct; extern const CT__xdc_runtime_Log_L_construct xdc_runtime_Log_L_construct__C; /* L_create */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_create; extern const CT__xdc_runtime_Log_L_create xdc_runtime_Log_L_create__C; /* L_destruct */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_destruct; extern const CT__xdc_runtime_Log_L_destruct xdc_runtime_Log_L_destruct__C; /* L_delete */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_delete; extern const CT__xdc_runtime_Log_L_delete xdc_runtime_Log_L_delete__C; /* L_error */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_error; extern const CT__xdc_runtime_Log_L_error xdc_runtime_Log_L_error__C; /* L_warning */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_warning; extern const CT__xdc_runtime_Log_L_warning xdc_runtime_Log_L_warning__C; /* L_info */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_info; extern const CT__xdc_runtime_Log_L_info xdc_runtime_Log_L_info__C; /* L_start */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_start; extern const CT__xdc_runtime_Log_L_start xdc_runtime_Log_L_start__C; /* L_stop */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_stop; extern const CT__xdc_runtime_Log_L_stop xdc_runtime_Log_L_stop__C; /* L_startInstance */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_startInstance; extern const CT__xdc_runtime_Log_L_startInstance xdc_runtime_Log_L_startInstance__C; /* L_stopInstance */ typedef xdc_runtime_Log_Event CT__xdc_runtime_Log_L_stopInstance; extern const CT__xdc_runtime_Log_L_stopInstance xdc_runtime_Log_L_stopInstance__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool xdc_runtime_Log_Module__startupDone__S( void ); /* doPrint__E */ extern void xdc_runtime_Log_doPrint__E( xdc_runtime_Log_EventRec *evRec ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__xdc_runtime_Log_Module__id xdc_runtime_Log_Module_id(void); static inline CT__xdc_runtime_Log_Module__id xdc_runtime_Log_Module_id( void ) { return xdc_runtime_Log_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool xdc_runtime_Log_Module_hasMask(void); static inline xdc_Bool xdc_runtime_Log_Module_hasMask(void) { return (xdc_Bool)(xdc_runtime_Log_Module__diagsMask__C != (CT__xdc_runtime_Log_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 xdc_runtime_Log_Module_getMask(void); static inline xdc_Bits16 xdc_runtime_Log_Module_getMask(void) { return (xdc_runtime_Log_Module__diagsMask__C != (CT__xdc_runtime_Log_Module__diagsMask)0) ? *xdc_runtime_Log_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void xdc_runtime_Log_Module_setMask(xdc_Bits16 mask); static inline void xdc_runtime_Log_Module_setMask(xdc_Bits16 mask) { if (xdc_runtime_Log_Module__diagsMask__C != (CT__xdc_runtime_Log_Module__diagsMask)0) { *xdc_runtime_Log_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2008-2017 Texas Instruments Incorporated * This program and the accompanying materials are made available under the * terms of the Eclipse Public License v1.0 and Eclipse Distribution License * v. 1.0 which accompanies this distribution. The Eclipse Public License is * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse * Distribution License is available at * http://www.eclipse.org/org/documents/edl-v10.php. * * Contributors: * Texas Instruments - initial implementation * */ /* * ======== Log__epilogue.h ======== * Implementation of the Log_* macros * * The implementation below relies on eight symbols defined by every module * header. Each of these symbols is a reference to a constant defined in a * separate compilation unit. The values of these constants are as follows: * * Module__MID - the module's ID (see Text.xs) * Module__LOGOBJ - the module's logger instance object * Module__LOGFXN0 - the module's logger's write0 function * Module__LOGFXN1 - the module's logger's write1 function * Module__LOGFXN2 - the module's logger's write2 function * Module__LOGFXN4 - the module's logger's write4 function * Module__LOGFXN8 - the module's logger's write8 function * Module__LOGDEF - 0 if the module has a logger, non-zero otherwise */ /* * Define flags for compiling out all Log calls * * The intent of these flags is to allow users to completely optimize logging * out of their code even when not using whole program optimization. This is * implemented by controlling the definitions of the Log macros. This will * only affect code compiled with the flag(s) set, so it will not disable * logging in any precompiled libraries. * * The DISABLE_ALL flag will have the effect of disabling all Log put, write, * print, error, warning, and info log calls. The flag just has to be defined, * we give it a value of zero or one to use in the macros. * * There are additional flags which can be used to disable all log calls * "except for". We use the presence of the DISABLE_ALL flag and the presence * of any ENABLE_ERROR, ENABLE_INFO, or ENABLE_WARNING flags to compute the * value of ENABLE_ERROR, etc., as zero or one. * * We ensure that all of the flags are ultimately defined and given a zero or * one value. Then the macro definitions are conditional on the value of the * appropriate flag. */ /* * If DISABLE_ALL is defined, give it the value 1, and assign values to all * of the ENABLE flags based on whether they've been defined or not. */ /* * ======== xdc_runtime_Log_getMask ======== */ /* * ======== xdc_runtime_Log_getRope ======== */ /* * ======== xdc_runtime_Log_getEventId ======== */ /* * ======== xdc_runtime_Log_doPut* ======== * The 'doPut' macros are the real implementation of the Log_put* APIs. * The Log_put* macros are just stubs which point to these definitions. We do * this so that we can disable the Log_put* APIs but still leave their * functionality available for any other Log macros which use them. * * For example, if the flags DISABLE_ALL and ENABLE_ERROR are set, we want * to disable the Log_put* macros, but not the Log_error* macros which are * also built on top of these 'doPut' macros. */ /* * ======== xdc_runtime_Log_put* ======== * See Log_doPut* */ /* * ======== xdc_runtime_Log_doWrite* ======== * The real implementations of the Log_write* APIs. See Log_doPut* for an * explanation of why we stub-out the Log_put* and Log_write* APIs. */ /* * ======== xdc_runtime_Log_write* ======== * See Log_doWrite* */ /* * ======== xdc_runtime_Log_print* ======== * Since "print" events do not have a rope, we use 0 (an invalid rope value) * as the event Id and construct a Log_Event to pass to Log_put. This has the * benefit that the Log_Event is equal to just the mask: (0 | mask). For this * reason, we simply pass the 'mask' as the first argument to 'put'. * * Each print function is mapped to a call to appropriate 'put' function. * print0 -> put1 * print1 -> put2 * print2 -> print3 -> put4 * print3 -> put4 * print4 -> print6 -> put8 * print5 -> print6 -> put8 * print6 -> put8 */ /* * ======== xdc_runtime_Log_error* ======== * Log an error event */ /* * ======== xdc_runtime_Log_warning* ======== * Log a warning event */ /* * ======== xdc_runtime_Log_info* ======== * Log an informational event */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Elem */ struct ti_sysbios_knl_Queue_Elem { ti_sysbios_knl_Queue_Elem *volatile next; ti_sysbios_knl_Queue_Elem *volatile prev; }; /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Queue_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Queue_Module__diagsEnabled ti_sysbios_knl_Queue_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Queue_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Queue_Module__diagsIncluded ti_sysbios_knl_Queue_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Queue_Module__diagsMask; extern const CT__ti_sysbios_knl_Queue_Module__diagsMask ti_sysbios_knl_Queue_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Queue_Module__gateObj; extern const CT__ti_sysbios_knl_Queue_Module__gateObj ti_sysbios_knl_Queue_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Queue_Module__gatePrms; extern const CT__ti_sysbios_knl_Queue_Module__gatePrms ti_sysbios_knl_Queue_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Queue_Module__id; extern const CT__ti_sysbios_knl_Queue_Module__id ti_sysbios_knl_Queue_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Queue_Module__loggerDefined; extern const CT__ti_sysbios_knl_Queue_Module__loggerDefined ti_sysbios_knl_Queue_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Queue_Module__loggerObj; extern const CT__ti_sysbios_knl_Queue_Module__loggerObj ti_sysbios_knl_Queue_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Queue_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Queue_Module__loggerFxn0 ti_sysbios_knl_Queue_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Queue_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Queue_Module__loggerFxn1 ti_sysbios_knl_Queue_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Queue_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Queue_Module__loggerFxn2 ti_sysbios_knl_Queue_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Queue_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Queue_Module__loggerFxn4 ti_sysbios_knl_Queue_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Queue_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Queue_Module__loggerFxn8 ti_sysbios_knl_Queue_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Queue_Object__count; extern const CT__ti_sysbios_knl_Queue_Object__count ti_sysbios_knl_Queue_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Queue_Object__heap; extern const CT__ti_sysbios_knl_Queue_Object__heap ti_sysbios_knl_Queue_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Queue_Object__sizeof; extern const CT__ti_sysbios_knl_Queue_Object__sizeof ti_sysbios_knl_Queue_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Queue_Object__table; extern const CT__ti_sysbios_knl_Queue_Object__table ti_sysbios_knl_Queue_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Queue_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Queue_Struct { ti_sysbios_knl_Queue_Elem f0; xdc_runtime_Types_CordAddr __name; }; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Instance_init__E */ extern void ti_sysbios_knl_Queue_Instance_init__E(ti_sysbios_knl_Queue_Object *obj, const ti_sysbios_knl_Queue_Params *prms); /* create */ extern ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_create( const ti_sysbios_knl_Queue_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_knl_Queue_construct(ti_sysbios_knl_Queue_Struct *obj, const ti_sysbios_knl_Queue_Params *prms); /* delete */ extern void ti_sysbios_knl_Queue_delete(ti_sysbios_knl_Queue_Handle *instp); /* destruct */ extern void ti_sysbios_knl_Queue_destruct(ti_sysbios_knl_Queue_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Queue_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Queue_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_knl_Queue_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_knl_Queue_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Queue_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Queue_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Queue_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Queue_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* elemClear__E */ extern void ti_sysbios_knl_Queue_elemClear__E( ti_sysbios_knl_Queue_Elem *qelem ); /* insert__E */ extern void ti_sysbios_knl_Queue_insert__E( ti_sysbios_knl_Queue_Elem *qelem, ti_sysbios_knl_Queue_Elem *elem ); /* next__E */ extern xdc_Ptr ti_sysbios_knl_Queue_next__E( ti_sysbios_knl_Queue_Elem *qelem ); /* prev__E */ extern xdc_Ptr ti_sysbios_knl_Queue_prev__E( ti_sysbios_knl_Queue_Elem *qelem ); /* remove__E */ extern void ti_sysbios_knl_Queue_remove__E( ti_sysbios_knl_Queue_Elem *qelem ); /* isQueued__E */ extern xdc_Bool ti_sysbios_knl_Queue_isQueued__E( ti_sysbios_knl_Queue_Elem *qelem ); /* dequeue__E */ extern xdc_Ptr ti_sysbios_knl_Queue_dequeue__E( ti_sysbios_knl_Queue_Handle __inst ); /* empty__E */ extern xdc_Bool ti_sysbios_knl_Queue_empty__E( ti_sysbios_knl_Queue_Handle __inst ); /* enqueue__E */ extern void ti_sysbios_knl_Queue_enqueue__E( ti_sysbios_knl_Queue_Handle __inst, ti_sysbios_knl_Queue_Elem *elem ); /* get__E */ extern xdc_Ptr ti_sysbios_knl_Queue_get__E( ti_sysbios_knl_Queue_Handle __inst ); /* getTail__E */ extern xdc_Ptr ti_sysbios_knl_Queue_getTail__E( ti_sysbios_knl_Queue_Handle __inst ); /* head__E */ extern xdc_Ptr ti_sysbios_knl_Queue_head__E( ti_sysbios_knl_Queue_Handle __inst ); /* put__E */ extern void ti_sysbios_knl_Queue_put__E( ti_sysbios_knl_Queue_Handle __inst, ti_sysbios_knl_Queue_Elem *elem ); /* putHead__E */ extern void ti_sysbios_knl_Queue_putHead__E( ti_sysbios_knl_Queue_Handle __inst, ti_sysbios_knl_Queue_Elem *elem ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Queue_Module__id ti_sysbios_knl_Queue_Module_id(void); static inline CT__ti_sysbios_knl_Queue_Module__id ti_sysbios_knl_Queue_Module_id( void ) { return ti_sysbios_knl_Queue_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_knl_Queue_Module_hasMask(void); static inline xdc_Bool ti_sysbios_knl_Queue_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_knl_Queue_Module__diagsMask__C != (CT__ti_sysbios_knl_Queue_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_knl_Queue_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_knl_Queue_Module_getMask(void) { return (ti_sysbios_knl_Queue_Module__diagsMask__C != (CT__ti_sysbios_knl_Queue_Module__diagsMask)0) ? *ti_sysbios_knl_Queue_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_knl_Queue_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_knl_Queue_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_knl_Queue_Module__diagsMask__C != (CT__ti_sysbios_knl_Queue_Module__diagsMask)0) { *ti_sysbios_knl_Queue_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_knl_Queue_Params_init(ti_sysbios_knl_Queue_Params *prms); static inline void ti_sysbios_knl_Queue_Params_init( ti_sysbios_knl_Queue_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Queue_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Queue_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Queue_Params_copy(ti_sysbios_knl_Queue_Params *dst, const ti_sysbios_knl_Queue_Params *src); static inline void ti_sysbios_knl_Queue_Params_copy(ti_sysbios_knl_Queue_Params *dst, const ti_sysbios_knl_Queue_Params *src) { if (dst != 0) { ti_sysbios_knl_Queue_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Queue_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_Object_get(ti_sysbios_knl_Queue_Instance_State *oarr, int i); static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_Object_get(ti_sysbios_knl_Queue_Instance_State *oarr, int i) { return (ti_sysbios_knl_Queue_Handle)ti_sysbios_knl_Queue_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_Object_first(void); static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_Object_first(void) { return (ti_sysbios_knl_Queue_Handle)ti_sysbios_knl_Queue_Object__first__S(); } /* Object_next */ static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_Object_next(ti_sysbios_knl_Queue_Object *obj); static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_Object_next(ti_sysbios_knl_Queue_Object *obj) { return (ti_sysbios_knl_Queue_Handle)ti_sysbios_knl_Queue_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_knl_Queue_Handle_label(ti_sysbios_knl_Queue_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_knl_Queue_Handle_label(ti_sysbios_knl_Queue_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_knl_Queue_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_knl_Queue_Handle_name(ti_sysbios_knl_Queue_Handle inst); static inline xdc_String ti_sysbios_knl_Queue_Handle_name(ti_sysbios_knl_Queue_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_knl_Queue_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_handle(ti_sysbios_knl_Queue_Struct *str); static inline ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_handle(ti_sysbios_knl_Queue_Struct *str) { return (ti_sysbios_knl_Queue_Handle)str; } /* struct */ static inline ti_sysbios_knl_Queue_Struct *ti_sysbios_knl_Queue_struct(ti_sysbios_knl_Queue_Handle inst); static inline ti_sysbios_knl_Queue_Struct *ti_sysbios_knl_Queue_struct(ti_sysbios_knl_Queue_Handle inst) { return (ti_sysbios_knl_Queue_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== interface ti.sysbios.interfaces.ICore ======== */ typedef struct ti_sysbios_interfaces_ICore_Fxns__ ti_sysbios_interfaces_ICore_Fxns__; typedef const struct ti_sysbios_interfaces_ICore_Fxns__* ti_sysbios_interfaces_ICore_Module; /* * ======== interface ti.sysbios.interfaces.IHwi ======== */ typedef struct ti_sysbios_interfaces_IHwi_HookSet ti_sysbios_interfaces_IHwi_HookSet; typedef struct ti_sysbios_interfaces_IHwi_StackInfo ti_sysbios_interfaces_IHwi_StackInfo; typedef struct ti_sysbios_interfaces_IHwi_Fxns__ ti_sysbios_interfaces_IHwi_Fxns__; typedef const struct ti_sysbios_interfaces_IHwi_Fxns__* ti_sysbios_interfaces_IHwi_Module; typedef struct ti_sysbios_interfaces_IHwi_Params ti_sysbios_interfaces_IHwi_Params; typedef struct ti_sysbios_interfaces_IHwi___Object { ti_sysbios_interfaces_IHwi_Fxns__* __fxns; xdc_Bits32 __label; } *ti_sysbios_interfaces_IHwi_Handle; /* * ======== interface ti.sysbios.interfaces.ITaskSupport ======== */ typedef struct ti_sysbios_interfaces_ITaskSupport_Fxns__ ti_sysbios_interfaces_ITaskSupport_Fxns__; typedef const struct ti_sysbios_interfaces_ITaskSupport_Fxns__* ti_sysbios_interfaces_ITaskSupport_Module; /* * ======== interface ti.sysbios.interfaces.ITimer ======== */ typedef struct ti_sysbios_interfaces_ITimer_Fxns__ ti_sysbios_interfaces_ITimer_Fxns__; typedef const struct ti_sysbios_interfaces_ITimer_Fxns__* ti_sysbios_interfaces_ITimer_Module; typedef struct ti_sysbios_interfaces_ITimer_Params ti_sysbios_interfaces_ITimer_Params; typedef struct ti_sysbios_interfaces_ITimer___Object { ti_sysbios_interfaces_ITimer_Fxns__* __fxns; xdc_Bits32 __label; } *ti_sysbios_interfaces_ITimer_Handle; /* * ======== interface ti.sysbios.interfaces.ITimerSupport ======== */ typedef struct ti_sysbios_interfaces_ITimerSupport_Fxns__ ti_sysbios_interfaces_ITimerSupport_Fxns__; typedef const struct ti_sysbios_interfaces_ITimerSupport_Fxns__* ti_sysbios_interfaces_ITimerSupport_Module; /* * ======== interface ti.sysbios.interfaces.ITimestamp ======== */ typedef struct ti_sysbios_interfaces_ITimestamp_Fxns__ ti_sysbios_interfaces_ITimestamp_Fxns__; typedef const struct ti_sysbios_interfaces_ITimestamp_Fxns__* ti_sysbios_interfaces_ITimestamp_Module; /* * ======== interface ti.sysbios.interfaces.IIntrinsicsSupport ======== */ typedef struct ti_sysbios_interfaces_IIntrinsicsSupport_Fxns__ ti_sysbios_interfaces_IIntrinsicsSupport_Fxns__; typedef const struct ti_sysbios_interfaces_IIntrinsicsSupport_Fxns__* ti_sysbios_interfaces_IIntrinsicsSupport_Module; /* * ======== interface ti.sysbios.interfaces.ICache ======== */ typedef struct ti_sysbios_interfaces_ICache_Fxns__ ti_sysbios_interfaces_ICache_Fxns__; typedef const struct ti_sysbios_interfaces_ICache_Fxns__* ti_sysbios_interfaces_ICache_Module; /* * ======== interface ti.sysbios.interfaces.IPower ======== */ typedef struct ti_sysbios_interfaces_IPower_Fxns__ ti_sysbios_interfaces_IPower_Fxns__; typedef const struct ti_sysbios_interfaces_IPower_Fxns__* ti_sysbios_interfaces_IPower_Module; /* * ======== interface ti.sysbios.interfaces.IRomDevice ======== */ typedef struct ti_sysbios_interfaces_IRomDevice_Fxns__ ti_sysbios_interfaces_IRomDevice_Fxns__; typedef const struct ti_sysbios_interfaces_IRomDevice_Fxns__* ti_sysbios_interfaces_IRomDevice_Module; /* * ======== interface ti.sysbios.interfaces.ISeconds ======== */ typedef struct ti_sysbios_interfaces_ISeconds_Time ti_sysbios_interfaces_ISeconds_Time; typedef struct ti_sysbios_interfaces_ISeconds_Fxns__ ti_sysbios_interfaces_ISeconds_Fxns__; typedef const struct ti_sysbios_interfaces_ISeconds_Fxns__* ti_sysbios_interfaces_ISeconds_Module; /* * ======== interface ti.sysbios.interfaces.ISysCall ======== */ typedef struct ti_sysbios_interfaces_ISysCall_Fxns__ ti_sysbios_interfaces_ISysCall_Fxns__; typedef const struct ti_sysbios_interfaces_ISysCall_Fxns__* ti_sysbios_interfaces_ISysCall_Module; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef void (*ti_sysbios_interfaces_ITaskSupport_FuncPtr)(void); /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_interfaces_ITaskSupport_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Ptr (*start)(xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enterFxn, ti_sysbios_interfaces_ITaskSupport_FuncPtr exitFxn, xdc_runtime_Error_Block* eb); void (*swap)(xdc_Ptr* oldtskContext, xdc_Ptr* newtskContext); xdc_Bool (*checkStack)(xdc_Char* stack, xdc_SizeT size); xdc_SizeT (*stackUsed)(xdc_Char* stack, xdc_SizeT size); xdc_UInt (*getStackAlignment)(void); xdc_SizeT (*getDefaultStackSize)(void); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base ti_sysbios_interfaces_ITaskSupport_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* Module_id */ static inline xdc_runtime_Types_ModuleId ti_sysbios_interfaces_ITaskSupport_Module_id(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline xdc_runtime_Types_ModuleId ti_sysbios_interfaces_ITaskSupport_Module_id(ti_sysbios_interfaces_ITaskSupport_Module mod) { return mod->__sysp->__mid; } /* start */ static inline xdc_Ptr ti_sysbios_interfaces_ITaskSupport_start(ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enterFxn, ti_sysbios_interfaces_ITaskSupport_FuncPtr exitFxn, xdc_runtime_Error_Block *eb); static inline xdc_Ptr ti_sysbios_interfaces_ITaskSupport_start( ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enterFxn, ti_sysbios_interfaces_ITaskSupport_FuncPtr exitFxn, xdc_runtime_Error_Block *eb ) { return mod->start(curTask, enterFxn, exitFxn, eb); } /* swap */ static inline void ti_sysbios_interfaces_ITaskSupport_swap(ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Ptr *oldtskContext, xdc_Ptr *newtskContext); static inline void ti_sysbios_interfaces_ITaskSupport_swap( ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Ptr *oldtskContext, xdc_Ptr *newtskContext ) { mod->swap(oldtskContext, newtskContext); } /* checkStack */ static inline xdc_Bool ti_sysbios_interfaces_ITaskSupport_checkStack(ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Char *stack, xdc_SizeT size); static inline xdc_Bool ti_sysbios_interfaces_ITaskSupport_checkStack( ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Char *stack, xdc_SizeT size ) { return mod->checkStack(stack, size); } /* stackUsed */ static inline xdc_SizeT ti_sysbios_interfaces_ITaskSupport_stackUsed(ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Char *stack, xdc_SizeT size); static inline xdc_SizeT ti_sysbios_interfaces_ITaskSupport_stackUsed( ti_sysbios_interfaces_ITaskSupport_Module mod, xdc_Char *stack, xdc_SizeT size ) { return mod->stackUsed(stack, size); } /* getStackAlignment */ static inline xdc_UInt ti_sysbios_interfaces_ITaskSupport_getStackAlignment(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline xdc_UInt ti_sysbios_interfaces_ITaskSupport_getStackAlignment( ti_sysbios_interfaces_ITaskSupport_Module mod ) { return mod->getStackAlignment(); } /* getDefaultStackSize */ static inline xdc_SizeT ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline xdc_SizeT ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize( ti_sysbios_interfaces_ITaskSupport_Module mod ) { return mod->getDefaultStackSize(); } /* * ======== FUNCTION SELECTORS ======== */ /* These functions return function pointers for module and instance functions. * The functions accept modules and instances declared as types defined in this * interface, but they return functions defined for the actual objects passed * as parameters. These functions are not invoked by any generated code or * XDCtools internal code. */ /* start_{FxnT,fxnP} */ typedef xdc_Ptr (*ti_sysbios_interfaces_ITaskSupport_start_FxnT)(xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enterFxn, ti_sysbios_interfaces_ITaskSupport_FuncPtr exitFxn, xdc_runtime_Error_Block* eb); static inline ti_sysbios_interfaces_ITaskSupport_start_FxnT ti_sysbios_interfaces_ITaskSupport_start_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline ti_sysbios_interfaces_ITaskSupport_start_FxnT ti_sysbios_interfaces_ITaskSupport_start_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod) { return (ti_sysbios_interfaces_ITaskSupport_start_FxnT)mod->start; } /* swap_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITaskSupport_swap_FxnT)(xdc_Ptr* oldtskContext, xdc_Ptr* newtskContext); static inline ti_sysbios_interfaces_ITaskSupport_swap_FxnT ti_sysbios_interfaces_ITaskSupport_swap_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline ti_sysbios_interfaces_ITaskSupport_swap_FxnT ti_sysbios_interfaces_ITaskSupport_swap_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod) { return (ti_sysbios_interfaces_ITaskSupport_swap_FxnT)mod->swap; } /* checkStack_{FxnT,fxnP} */ typedef xdc_Bool (*ti_sysbios_interfaces_ITaskSupport_checkStack_FxnT)(xdc_Char* stack, xdc_SizeT size); static inline ti_sysbios_interfaces_ITaskSupport_checkStack_FxnT ti_sysbios_interfaces_ITaskSupport_checkStack_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline ti_sysbios_interfaces_ITaskSupport_checkStack_FxnT ti_sysbios_interfaces_ITaskSupport_checkStack_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod) { return (ti_sysbios_interfaces_ITaskSupport_checkStack_FxnT)mod->checkStack; } /* stackUsed_{FxnT,fxnP} */ typedef xdc_SizeT (*ti_sysbios_interfaces_ITaskSupport_stackUsed_FxnT)(xdc_Char* stack, xdc_SizeT size); static inline ti_sysbios_interfaces_ITaskSupport_stackUsed_FxnT ti_sysbios_interfaces_ITaskSupport_stackUsed_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline ti_sysbios_interfaces_ITaskSupport_stackUsed_FxnT ti_sysbios_interfaces_ITaskSupport_stackUsed_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod) { return (ti_sysbios_interfaces_ITaskSupport_stackUsed_FxnT)mod->stackUsed; } /* getStackAlignment_{FxnT,fxnP} */ typedef xdc_UInt (*ti_sysbios_interfaces_ITaskSupport_getStackAlignment_FxnT)(void); static inline ti_sysbios_interfaces_ITaskSupport_getStackAlignment_FxnT ti_sysbios_interfaces_ITaskSupport_getStackAlignment_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline ti_sysbios_interfaces_ITaskSupport_getStackAlignment_FxnT ti_sysbios_interfaces_ITaskSupport_getStackAlignment_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod) { return (ti_sysbios_interfaces_ITaskSupport_getStackAlignment_FxnT)mod->getStackAlignment; } /* getDefaultStackSize_{FxnT,fxnP} */ typedef xdc_SizeT (*ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize_FxnT)(void); static inline ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize_FxnT ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod); static inline ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize_FxnT ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize_fxnP(ti_sysbios_interfaces_ITaskSupport_Module mod) { return (ti_sysbios_interfaces_ITaskSupport_getDefaultStackSize_FxnT)mod->getDefaultStackSize; } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef void (*ti_sysbios_interfaces_ITimer_FuncPtr)(xdc_UArg arg1); /* ANY */ /* StartMode */ enum ti_sysbios_interfaces_ITimer_StartMode { ti_sysbios_interfaces_ITimer_StartMode_AUTO, ti_sysbios_interfaces_ITimer_StartMode_USER }; typedef enum ti_sysbios_interfaces_ITimer_StartMode ti_sysbios_interfaces_ITimer_StartMode; /* RunMode */ enum ti_sysbios_interfaces_ITimer_RunMode { ti_sysbios_interfaces_ITimer_RunMode_CONTINUOUS, ti_sysbios_interfaces_ITimer_RunMode_ONESHOT, ti_sysbios_interfaces_ITimer_RunMode_DYNAMIC }; typedef enum ti_sysbios_interfaces_ITimer_RunMode ti_sysbios_interfaces_ITimer_RunMode; /* Status */ enum ti_sysbios_interfaces_ITimer_Status { ti_sysbios_interfaces_ITimer_Status_INUSE, ti_sysbios_interfaces_ITimer_Status_FREE }; typedef enum ti_sysbios_interfaces_ITimer_Status ti_sysbios_interfaces_ITimer_Status; /* PeriodType */ enum ti_sysbios_interfaces_ITimer_PeriodType { ti_sysbios_interfaces_ITimer_PeriodType_MICROSECS, ti_sysbios_interfaces_ITimer_PeriodType_COUNTS }; typedef enum ti_sysbios_interfaces_ITimer_PeriodType ti_sysbios_interfaces_ITimer_PeriodType; /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_interfaces_ITimer_Args__create { xdc_Int id; ti_sysbios_interfaces_ITimer_FuncPtr tickFxn; } ti_sysbios_interfaces_ITimer_Args__create; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_interfaces_ITimer_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_interfaces_ITimer_RunMode runMode; ti_sysbios_interfaces_ITimer_StartMode startMode; xdc_UArg arg; xdc_UInt32 period; ti_sysbios_interfaces_ITimer_PeriodType periodType; xdc_runtime_Types_FreqHz extFreq; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_interfaces_ITimer_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_UInt (*getNumTimers)(void); ti_sysbios_interfaces_ITimer_Status (*getStatus)(xdc_UInt id); void (*startup)(void); xdc_UInt32 (*getMaxTicks)(void* inst); void (*setNextTick)(void* inst, xdc_UInt32 ticks); void (*start)(void* inst); void (*stop)(void* inst); void (*setPeriod)(void* inst, xdc_UInt32 period); xdc_Bool (*setPeriodMicroSecs)(void* inst, xdc_UInt32 microsecs); xdc_UInt32 (*getPeriod)(void* inst); xdc_UInt32 (*getCount)(void* inst); void (*getFreq)(void* inst, xdc_runtime_Types_FreqHz* freq); ti_sysbios_interfaces_ITimer_FuncPtr (*getFunc)(void* inst, xdc_UArg* arg); void (*setFunc)(void* inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg); void (*trigger)(void* inst, xdc_UInt32 cycles); xdc_UInt32 (*getExpiredCounts)(void* inst); xdc_UInt32 (*getExpiredTicks)(void* inst, xdc_UInt32 tickPeriod); xdc_UInt32 (*getCurrentTick)(void* inst, xdc_Bool save); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base ti_sysbios_interfaces_ITimer_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* create */ extern ti_sysbios_interfaces_ITimer_Handle ti_sysbios_interfaces_ITimer_create(ti_sysbios_interfaces_ITimer_Module mod, xdc_Int id, ti_sysbios_interfaces_ITimer_FuncPtr tickFxn, const ti_sysbios_interfaces_ITimer_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_interfaces_ITimer_delete(ti_sysbios_interfaces_ITimer_Handle *inst); /* Handle_to_Module */ static inline ti_sysbios_interfaces_ITimer_Module ti_sysbios_interfaces_ITimer_Handle_to_Module(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_Module ti_sysbios_interfaces_ITimer_Handle_to_Module(ti_sysbios_interfaces_ITimer_Handle inst) { return inst->__fxns; } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_interfaces_ITimer_Handle_label(ti_sysbios_interfaces_ITimer_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_interfaces_ITimer_Handle_label(ti_sysbios_interfaces_ITimer_Handle inst, xdc_runtime_Types_Label *lab) { return inst->__fxns->__sysp->__label(inst, lab); } /* Module_id */ static inline xdc_runtime_Types_ModuleId ti_sysbios_interfaces_ITimer_Module_id(ti_sysbios_interfaces_ITimer_Module mod); static inline xdc_runtime_Types_ModuleId ti_sysbios_interfaces_ITimer_Module_id(ti_sysbios_interfaces_ITimer_Module mod) { return mod->__sysp->__mid; } /* getNumTimers */ static inline xdc_UInt ti_sysbios_interfaces_ITimer_getNumTimers(ti_sysbios_interfaces_ITimer_Module mod); static inline xdc_UInt ti_sysbios_interfaces_ITimer_getNumTimers( ti_sysbios_interfaces_ITimer_Module mod ) { return mod->getNumTimers(); } /* getStatus */ static inline ti_sysbios_interfaces_ITimer_Status ti_sysbios_interfaces_ITimer_getStatus(ti_sysbios_interfaces_ITimer_Module mod, xdc_UInt id); static inline ti_sysbios_interfaces_ITimer_Status ti_sysbios_interfaces_ITimer_getStatus( ti_sysbios_interfaces_ITimer_Module mod, xdc_UInt id ) { return mod->getStatus(id); } /* startup */ static inline void ti_sysbios_interfaces_ITimer_startup(ti_sysbios_interfaces_ITimer_Module mod); static inline void ti_sysbios_interfaces_ITimer_startup( ti_sysbios_interfaces_ITimer_Module mod ) { mod->startup(); } /* getMaxTicks */ static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getMaxTicks(ti_sysbios_interfaces_ITimer_Handle inst); static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getMaxTicks( ti_sysbios_interfaces_ITimer_Handle inst ) { return inst->__fxns->getMaxTicks((void*)inst); } /* setNextTick */ static inline void ti_sysbios_interfaces_ITimer_setNextTick(ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 ticks); static inline void ti_sysbios_interfaces_ITimer_setNextTick( ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 ticks ) { inst->__fxns->setNextTick((void*)inst, ticks); } /* start */ static inline void ti_sysbios_interfaces_ITimer_start(ti_sysbios_interfaces_ITimer_Handle inst); static inline void ti_sysbios_interfaces_ITimer_start( ti_sysbios_interfaces_ITimer_Handle inst ) { inst->__fxns->start((void*)inst); } /* stop */ static inline void ti_sysbios_interfaces_ITimer_stop(ti_sysbios_interfaces_ITimer_Handle inst); static inline void ti_sysbios_interfaces_ITimer_stop( ti_sysbios_interfaces_ITimer_Handle inst ) { inst->__fxns->stop((void*)inst); } /* setPeriod */ static inline void ti_sysbios_interfaces_ITimer_setPeriod(ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 period); static inline void ti_sysbios_interfaces_ITimer_setPeriod( ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 period ) { inst->__fxns->setPeriod((void*)inst, period); } /* setPeriodMicroSecs */ static inline xdc_Bool ti_sysbios_interfaces_ITimer_setPeriodMicroSecs(ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 microsecs); static inline xdc_Bool ti_sysbios_interfaces_ITimer_setPeriodMicroSecs( ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 microsecs ) { return inst->__fxns->setPeriodMicroSecs((void*)inst, microsecs); } /* getPeriod */ static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getPeriod(ti_sysbios_interfaces_ITimer_Handle inst); static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getPeriod( ti_sysbios_interfaces_ITimer_Handle inst ) { return inst->__fxns->getPeriod((void*)inst); } /* getCount */ static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getCount(ti_sysbios_interfaces_ITimer_Handle inst); static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getCount( ti_sysbios_interfaces_ITimer_Handle inst ) { return inst->__fxns->getCount((void*)inst); } /* getFreq */ static inline void ti_sysbios_interfaces_ITimer_getFreq(ti_sysbios_interfaces_ITimer_Handle inst, xdc_runtime_Types_FreqHz *freq); static inline void ti_sysbios_interfaces_ITimer_getFreq( ti_sysbios_interfaces_ITimer_Handle inst, xdc_runtime_Types_FreqHz *freq ) { inst->__fxns->getFreq((void*)inst, freq); } /* getFunc */ static inline ti_sysbios_interfaces_ITimer_FuncPtr ti_sysbios_interfaces_ITimer_getFunc(ti_sysbios_interfaces_ITimer_Handle inst, xdc_UArg *arg); static inline ti_sysbios_interfaces_ITimer_FuncPtr ti_sysbios_interfaces_ITimer_getFunc( ti_sysbios_interfaces_ITimer_Handle inst, xdc_UArg *arg ) { return inst->__fxns->getFunc((void*)inst, arg); } /* setFunc */ static inline void ti_sysbios_interfaces_ITimer_setFunc(ti_sysbios_interfaces_ITimer_Handle inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg); static inline void ti_sysbios_interfaces_ITimer_setFunc( ti_sysbios_interfaces_ITimer_Handle inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg ) { inst->__fxns->setFunc((void*)inst, fxn, arg); } /* trigger */ static inline void ti_sysbios_interfaces_ITimer_trigger(ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 cycles); static inline void ti_sysbios_interfaces_ITimer_trigger( ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 cycles ) { inst->__fxns->trigger((void*)inst, cycles); } /* getExpiredCounts */ static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getExpiredCounts(ti_sysbios_interfaces_ITimer_Handle inst); static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getExpiredCounts( ti_sysbios_interfaces_ITimer_Handle inst ) { return inst->__fxns->getExpiredCounts((void*)inst); } /* getExpiredTicks */ static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getExpiredTicks(ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 tickPeriod); static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getExpiredTicks( ti_sysbios_interfaces_ITimer_Handle inst, xdc_UInt32 tickPeriod ) { return inst->__fxns->getExpiredTicks((void*)inst, tickPeriod); } /* getCurrentTick */ static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getCurrentTick(ti_sysbios_interfaces_ITimer_Handle inst, xdc_Bool save); static inline xdc_UInt32 ti_sysbios_interfaces_ITimer_getCurrentTick( ti_sysbios_interfaces_ITimer_Handle inst, xdc_Bool save ) { return inst->__fxns->getCurrentTick((void*)inst, save); } /* * ======== FUNCTION SELECTORS ======== */ /* These functions return function pointers for module and instance functions. * The functions accept modules and instances declared as types defined in this * interface, but they return functions defined for the actual objects passed * as parameters. These functions are not invoked by any generated code or * XDCtools internal code. */ /* getNumTimers_{FxnT,fxnP} */ typedef xdc_UInt (*ti_sysbios_interfaces_ITimer_getNumTimers_FxnT)(void); static inline ti_sysbios_interfaces_ITimer_getNumTimers_FxnT ti_sysbios_interfaces_ITimer_getNumTimers_fxnP(ti_sysbios_interfaces_ITimer_Module mod); static inline ti_sysbios_interfaces_ITimer_getNumTimers_FxnT ti_sysbios_interfaces_ITimer_getNumTimers_fxnP(ti_sysbios_interfaces_ITimer_Module mod) { return (ti_sysbios_interfaces_ITimer_getNumTimers_FxnT)mod->getNumTimers; } /* getStatus_{FxnT,fxnP} */ typedef ti_sysbios_interfaces_ITimer_Status (*ti_sysbios_interfaces_ITimer_getStatus_FxnT)(xdc_UInt id); static inline ti_sysbios_interfaces_ITimer_getStatus_FxnT ti_sysbios_interfaces_ITimer_getStatus_fxnP(ti_sysbios_interfaces_ITimer_Module mod); static inline ti_sysbios_interfaces_ITimer_getStatus_FxnT ti_sysbios_interfaces_ITimer_getStatus_fxnP(ti_sysbios_interfaces_ITimer_Module mod) { return (ti_sysbios_interfaces_ITimer_getStatus_FxnT)mod->getStatus; } /* startup_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_startup_FxnT)(void); static inline ti_sysbios_interfaces_ITimer_startup_FxnT ti_sysbios_interfaces_ITimer_startup_fxnP(ti_sysbios_interfaces_ITimer_Module mod); static inline ti_sysbios_interfaces_ITimer_startup_FxnT ti_sysbios_interfaces_ITimer_startup_fxnP(ti_sysbios_interfaces_ITimer_Module mod) { return (ti_sysbios_interfaces_ITimer_startup_FxnT)mod->startup; } /* getMaxTicks_{FxnT,fxnP} */ typedef xdc_UInt32 (*ti_sysbios_interfaces_ITimer_getMaxTicks_FxnT)(void *inst); static inline ti_sysbios_interfaces_ITimer_getMaxTicks_FxnT ti_sysbios_interfaces_ITimer_getMaxTicks_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getMaxTicks_FxnT ti_sysbios_interfaces_ITimer_getMaxTicks_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getMaxTicks_FxnT)inst->__fxns->getMaxTicks; } /* setNextTick_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_setNextTick_FxnT)(void *inst, xdc_UInt32 ticks); static inline ti_sysbios_interfaces_ITimer_setNextTick_FxnT ti_sysbios_interfaces_ITimer_setNextTick_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_setNextTick_FxnT ti_sysbios_interfaces_ITimer_setNextTick_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_setNextTick_FxnT)inst->__fxns->setNextTick; } /* start_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_start_FxnT)(void *inst); static inline ti_sysbios_interfaces_ITimer_start_FxnT ti_sysbios_interfaces_ITimer_start_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_start_FxnT ti_sysbios_interfaces_ITimer_start_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_start_FxnT)inst->__fxns->start; } /* stop_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_stop_FxnT)(void *inst); static inline ti_sysbios_interfaces_ITimer_stop_FxnT ti_sysbios_interfaces_ITimer_stop_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_stop_FxnT ti_sysbios_interfaces_ITimer_stop_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_stop_FxnT)inst->__fxns->stop; } /* setPeriod_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_setPeriod_FxnT)(void *inst, xdc_UInt32 period); static inline ti_sysbios_interfaces_ITimer_setPeriod_FxnT ti_sysbios_interfaces_ITimer_setPeriod_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_setPeriod_FxnT ti_sysbios_interfaces_ITimer_setPeriod_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_setPeriod_FxnT)inst->__fxns->setPeriod; } /* setPeriodMicroSecs_{FxnT,fxnP} */ typedef xdc_Bool (*ti_sysbios_interfaces_ITimer_setPeriodMicroSecs_FxnT)(void *inst, xdc_UInt32 microsecs); static inline ti_sysbios_interfaces_ITimer_setPeriodMicroSecs_FxnT ti_sysbios_interfaces_ITimer_setPeriodMicroSecs_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_setPeriodMicroSecs_FxnT ti_sysbios_interfaces_ITimer_setPeriodMicroSecs_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_setPeriodMicroSecs_FxnT)inst->__fxns->setPeriodMicroSecs; } /* getPeriod_{FxnT,fxnP} */ typedef xdc_UInt32 (*ti_sysbios_interfaces_ITimer_getPeriod_FxnT)(void *inst); static inline ti_sysbios_interfaces_ITimer_getPeriod_FxnT ti_sysbios_interfaces_ITimer_getPeriod_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getPeriod_FxnT ti_sysbios_interfaces_ITimer_getPeriod_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getPeriod_FxnT)inst->__fxns->getPeriod; } /* getCount_{FxnT,fxnP} */ typedef xdc_UInt32 (*ti_sysbios_interfaces_ITimer_getCount_FxnT)(void *inst); static inline ti_sysbios_interfaces_ITimer_getCount_FxnT ti_sysbios_interfaces_ITimer_getCount_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getCount_FxnT ti_sysbios_interfaces_ITimer_getCount_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getCount_FxnT)inst->__fxns->getCount; } /* getFreq_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_getFreq_FxnT)(void *inst, xdc_runtime_Types_FreqHz* freq); static inline ti_sysbios_interfaces_ITimer_getFreq_FxnT ti_sysbios_interfaces_ITimer_getFreq_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getFreq_FxnT ti_sysbios_interfaces_ITimer_getFreq_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getFreq_FxnT)inst->__fxns->getFreq; } /* getFunc_{FxnT,fxnP} */ typedef ti_sysbios_interfaces_ITimer_FuncPtr (*ti_sysbios_interfaces_ITimer_getFunc_FxnT)(void *inst, xdc_UArg* arg); static inline ti_sysbios_interfaces_ITimer_getFunc_FxnT ti_sysbios_interfaces_ITimer_getFunc_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getFunc_FxnT ti_sysbios_interfaces_ITimer_getFunc_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getFunc_FxnT)inst->__fxns->getFunc; } /* setFunc_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_setFunc_FxnT)(void *inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg); static inline ti_sysbios_interfaces_ITimer_setFunc_FxnT ti_sysbios_interfaces_ITimer_setFunc_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_setFunc_FxnT ti_sysbios_interfaces_ITimer_setFunc_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_setFunc_FxnT)inst->__fxns->setFunc; } /* trigger_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_ITimer_trigger_FxnT)(void *inst, xdc_UInt32 cycles); static inline ti_sysbios_interfaces_ITimer_trigger_FxnT ti_sysbios_interfaces_ITimer_trigger_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_trigger_FxnT ti_sysbios_interfaces_ITimer_trigger_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_trigger_FxnT)inst->__fxns->trigger; } /* getExpiredCounts_{FxnT,fxnP} */ typedef xdc_UInt32 (*ti_sysbios_interfaces_ITimer_getExpiredCounts_FxnT)(void *inst); static inline ti_sysbios_interfaces_ITimer_getExpiredCounts_FxnT ti_sysbios_interfaces_ITimer_getExpiredCounts_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getExpiredCounts_FxnT ti_sysbios_interfaces_ITimer_getExpiredCounts_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getExpiredCounts_FxnT)inst->__fxns->getExpiredCounts; } /* getExpiredTicks_{FxnT,fxnP} */ typedef xdc_UInt32 (*ti_sysbios_interfaces_ITimer_getExpiredTicks_FxnT)(void *inst, xdc_UInt32 tickPeriod); static inline ti_sysbios_interfaces_ITimer_getExpiredTicks_FxnT ti_sysbios_interfaces_ITimer_getExpiredTicks_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getExpiredTicks_FxnT ti_sysbios_interfaces_ITimer_getExpiredTicks_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getExpiredTicks_FxnT)inst->__fxns->getExpiredTicks; } /* getCurrentTick_{FxnT,fxnP} */ typedef xdc_UInt32 (*ti_sysbios_interfaces_ITimer_getCurrentTick_FxnT)(void *inst, xdc_Bool save); static inline ti_sysbios_interfaces_ITimer_getCurrentTick_FxnT ti_sysbios_interfaces_ITimer_getCurrentTick_fxnP(ti_sysbios_interfaces_ITimer_Handle inst); static inline ti_sysbios_interfaces_ITimer_getCurrentTick_FxnT ti_sysbios_interfaces_ITimer_getCurrentTick_fxnP(ti_sysbios_interfaces_ITimer_Handle inst) { return (ti_sysbios_interfaces_ITimer_getCurrentTick_FxnT)inst->__fxns->getCurrentTick; } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef void (*ti_sysbios_knl_Swi_FuncPtr)(xdc_UArg arg1, xdc_UArg arg2); /* HookSet */ struct ti_sysbios_knl_Swi_HookSet { void (*registerFxn)(xdc_Int arg1); void (*createFxn)(ti_sysbios_knl_Swi_Handle arg1, xdc_runtime_Error_Block* arg2); void (*readyFxn)(ti_sysbios_knl_Swi_Handle arg1); void (*beginFxn)(ti_sysbios_knl_Swi_Handle arg1); void (*endFxn)(ti_sysbios_knl_Swi_Handle arg1); void (*deleteFxn)(ti_sysbios_knl_Swi_Handle arg1); }; /* Struct2__ */ typedef xdc_Ptr __T1_ti_sysbios_knl_Swi_Struct2____hookEnv; typedef xdc_Ptr *ARRAY1_ti_sysbios_knl_Swi_Struct2____hookEnv; typedef const xdc_Ptr *CARRAY1_ti_sysbios_knl_Swi_Struct2____hookEnv; typedef CARRAY1_ti_sysbios_knl_Swi_Struct2____hookEnv __TA_ti_sysbios_knl_Swi_Struct2____hookEnv; struct ti_sysbios_knl_Swi_Struct2__ { ti_sysbios_knl_Queue_Elem qElem; ti_sysbios_knl_Swi_FuncPtr fxn; xdc_UArg arg0; xdc_UArg arg1; xdc_UInt priority; xdc_UInt mask; xdc_Bool posted; xdc_UInt initTrigger; xdc_UInt trigger; ti_sysbios_knl_Queue_Handle readyQ; __TA_ti_sysbios_knl_Swi_Struct2____hookEnv hookEnv; xdc_runtime_Types_CordAddr name; }; /* Struct2 */ typedef ti_sysbios_knl_Swi_Struct2__ ti_sysbios_knl_Swi_Struct2; /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_knl_Swi_Args__create { ti_sysbios_knl_Swi_FuncPtr swiFxn; } ti_sysbios_knl_Swi_Args__create; /* * ======== INTERNAL DEFINITIONS ======== */ /* Instance_State */ typedef xdc_Ptr __T1_ti_sysbios_knl_Swi_Instance_State__hookEnv; typedef xdc_Ptr *ARRAY1_ti_sysbios_knl_Swi_Instance_State__hookEnv; typedef const xdc_Ptr *CARRAY1_ti_sysbios_knl_Swi_Instance_State__hookEnv; typedef ARRAY1_ti_sysbios_knl_Swi_Instance_State__hookEnv __TA_ti_sysbios_knl_Swi_Instance_State__hookEnv; /* Module_State */ typedef ti_sysbios_knl_Queue_Instance_State __T1_ti_sysbios_knl_Swi_Module_State__readyQ; typedef ti_sysbios_knl_Queue_Instance_State *ARRAY1_ti_sysbios_knl_Swi_Module_State__readyQ; typedef const ti_sysbios_knl_Queue_Instance_State *CARRAY1_ti_sysbios_knl_Swi_Module_State__readyQ; typedef ARRAY1_ti_sysbios_knl_Swi_Module_State__readyQ __TA_ti_sysbios_knl_Swi_Module_State__readyQ; typedef ti_sysbios_knl_Swi_Handle __T1_ti_sysbios_knl_Swi_Module_State__constructedSwis; typedef ti_sysbios_knl_Swi_Handle *ARRAY1_ti_sysbios_knl_Swi_Module_State__constructedSwis; typedef const ti_sysbios_knl_Swi_Handle *CARRAY1_ti_sysbios_knl_Swi_Module_State__constructedSwis; typedef ARRAY1_ti_sysbios_knl_Swi_Module_State__constructedSwis __TA_ti_sysbios_knl_Swi_Module_State__constructedSwis; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Swi_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Swi_Module__diagsEnabled ti_sysbios_knl_Swi_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Swi_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Swi_Module__diagsIncluded ti_sysbios_knl_Swi_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Swi_Module__diagsMask; extern const CT__ti_sysbios_knl_Swi_Module__diagsMask ti_sysbios_knl_Swi_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Swi_Module__gateObj; extern const CT__ti_sysbios_knl_Swi_Module__gateObj ti_sysbios_knl_Swi_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Swi_Module__gatePrms; extern const CT__ti_sysbios_knl_Swi_Module__gatePrms ti_sysbios_knl_Swi_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Swi_Module__id; extern const CT__ti_sysbios_knl_Swi_Module__id ti_sysbios_knl_Swi_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Swi_Module__loggerDefined; extern const CT__ti_sysbios_knl_Swi_Module__loggerDefined ti_sysbios_knl_Swi_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Swi_Module__loggerObj; extern const CT__ti_sysbios_knl_Swi_Module__loggerObj ti_sysbios_knl_Swi_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Swi_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Swi_Module__loggerFxn0 ti_sysbios_knl_Swi_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Swi_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Swi_Module__loggerFxn1 ti_sysbios_knl_Swi_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Swi_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Swi_Module__loggerFxn2 ti_sysbios_knl_Swi_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Swi_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Swi_Module__loggerFxn4 ti_sysbios_knl_Swi_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Swi_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Swi_Module__loggerFxn8 ti_sysbios_knl_Swi_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Swi_Object__count; extern const CT__ti_sysbios_knl_Swi_Object__count ti_sysbios_knl_Swi_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Swi_Object__heap; extern const CT__ti_sysbios_knl_Swi_Object__heap ti_sysbios_knl_Swi_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Swi_Object__sizeof; extern const CT__ti_sysbios_knl_Swi_Object__sizeof ti_sysbios_knl_Swi_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Swi_Object__table; extern const CT__ti_sysbios_knl_Swi_Object__table ti_sysbios_knl_Swi_Object__table__C; /* LM_begin */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Swi_LM_begin; extern const CT__ti_sysbios_knl_Swi_LM_begin ti_sysbios_knl_Swi_LM_begin__C; /* LD_end */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Swi_LD_end; extern const CT__ti_sysbios_knl_Swi_LD_end ti_sysbios_knl_Swi_LD_end__C; /* LM_post */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Swi_LM_post; extern const CT__ti_sysbios_knl_Swi_LM_post ti_sysbios_knl_Swi_LM_post__C; /* A_swiDisabled */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Swi_A_swiDisabled; extern const CT__ti_sysbios_knl_Swi_A_swiDisabled ti_sysbios_knl_Swi_A_swiDisabled__C; /* A_badPriority */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Swi_A_badPriority; extern const CT__ti_sysbios_knl_Swi_A_badPriority ti_sysbios_knl_Swi_A_badPriority__C; /* numPriorities */ typedef xdc_UInt CT__ti_sysbios_knl_Swi_numPriorities; extern const CT__ti_sysbios_knl_Swi_numPriorities ti_sysbios_knl_Swi_numPriorities__C; /* hooks */ typedef ti_sysbios_knl_Swi_HookSet __T1_ti_sysbios_knl_Swi_hooks; typedef struct { int length; ti_sysbios_knl_Swi_HookSet *elem; } ARRAY1_ti_sysbios_knl_Swi_hooks; typedef struct { int length; ti_sysbios_knl_Swi_HookSet const *elem; } CARRAY1_ti_sysbios_knl_Swi_hooks; typedef CARRAY1_ti_sysbios_knl_Swi_hooks __TA_ti_sysbios_knl_Swi_hooks; typedef CARRAY1_ti_sysbios_knl_Swi_hooks CT__ti_sysbios_knl_Swi_hooks; extern const CT__ti_sysbios_knl_Swi_hooks ti_sysbios_knl_Swi_hooks__C; /* taskDisable */ typedef xdc_UInt (*CT__ti_sysbios_knl_Swi_taskDisable)(void); extern const CT__ti_sysbios_knl_Swi_taskDisable ti_sysbios_knl_Swi_taskDisable__C; /* taskRestore */ typedef void (*CT__ti_sysbios_knl_Swi_taskRestore)(xdc_UInt arg1); extern const CT__ti_sysbios_knl_Swi_taskRestore ti_sysbios_knl_Swi_taskRestore__C; /* numConstructedSwis */ typedef xdc_UInt CT__ti_sysbios_knl_Swi_numConstructedSwis; extern const CT__ti_sysbios_knl_Swi_numConstructedSwis ti_sysbios_knl_Swi_numConstructedSwis__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Swi_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_UArg arg0; xdc_UArg arg1; xdc_UInt priority; xdc_UInt trigger; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Swi_Struct { ti_sysbios_knl_Queue_Elem f0; ti_sysbios_knl_Swi_FuncPtr f1; xdc_UArg f2; xdc_UArg f3; xdc_UInt f4; xdc_UInt f5; xdc_Bool f6; xdc_UInt f7; xdc_UInt f8; ti_sysbios_knl_Queue_Handle f9; __TA_ti_sysbios_knl_Swi_Instance_State__hookEnv f10; xdc_runtime_Types_CordAddr __name; }; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_knl_Swi_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_knl_Swi_Module_startup__F( xdc_Int state ); /* Instance_init__E */ extern xdc_Int ti_sysbios_knl_Swi_Instance_init__E(ti_sysbios_knl_Swi_Object *obj, ti_sysbios_knl_Swi_FuncPtr swiFxn, const ti_sysbios_knl_Swi_Params *prms, xdc_runtime_Error_Block *eb); /* Instance_finalize__E */ extern void ti_sysbios_knl_Swi_Instance_finalize__E(ti_sysbios_knl_Swi_Object *obj, int ec); /* create */ extern ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_create( ti_sysbios_knl_Swi_FuncPtr swiFxn, const ti_sysbios_knl_Swi_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_knl_Swi_construct(ti_sysbios_knl_Swi_Struct *obj, ti_sysbios_knl_Swi_FuncPtr swiFxn, const ti_sysbios_knl_Swi_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_knl_Swi_delete(ti_sysbios_knl_Swi_Handle *instp); /* destruct */ extern void ti_sysbios_knl_Swi_destruct(ti_sysbios_knl_Swi_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Swi_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Swi_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_knl_Swi_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_knl_Swi_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Swi_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Swi_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Swi_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Swi_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* construct2__E */ extern ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_construct2__E( ti_sysbios_knl_Swi_Struct2 *swi, ti_sysbios_knl_Swi_FuncPtr swiFxn, const ti_sysbios_knl_Swi_Params *prms ); /* startup__E */ extern void ti_sysbios_knl_Swi_startup__E( void ); /* enabled__E */ extern xdc_Bool ti_sysbios_knl_Swi_enabled__E( void ); /* unlockSched__E */ extern void ti_sysbios_knl_Swi_unlockSched__E( void ); /* disable__E */ extern xdc_UInt ti_sysbios_knl_Swi_disable__E( void ); /* enable__E */ extern void ti_sysbios_knl_Swi_enable__E( void ); /* restore__E */ extern void ti_sysbios_knl_Swi_restore__E( xdc_UInt key ); /* restoreHwi__E */ extern void ti_sysbios_knl_Swi_restoreHwi__E( xdc_UInt key ); /* self__E */ extern ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_self__E( void ); /* getTrigger__E */ extern xdc_UInt ti_sysbios_knl_Swi_getTrigger__E( void ); /* raisePri__E */ extern xdc_UInt ti_sysbios_knl_Swi_raisePri__E( xdc_UInt priority ); /* restorePri__E */ extern void ti_sysbios_knl_Swi_restorePri__E( xdc_UInt key ); /* andn__E */ extern void ti_sysbios_knl_Swi_andn__E( ti_sysbios_knl_Swi_Handle __inst, xdc_UInt mask ); /* dec__E */ extern void ti_sysbios_knl_Swi_dec__E( ti_sysbios_knl_Swi_Handle __inst ); /* getHookContext__E */ extern xdc_Ptr ti_sysbios_knl_Swi_getHookContext__E( ti_sysbios_knl_Swi_Handle __inst, xdc_Int id ); /* setHookContext__E */ extern void ti_sysbios_knl_Swi_setHookContext__E( ti_sysbios_knl_Swi_Handle __inst, xdc_Int id, xdc_Ptr hookContext ); /* getPri__E */ extern xdc_UInt ti_sysbios_knl_Swi_getPri__E( ti_sysbios_knl_Swi_Handle __inst ); /* getFunc__E */ extern ti_sysbios_knl_Swi_FuncPtr ti_sysbios_knl_Swi_getFunc__E( ti_sysbios_knl_Swi_Handle __inst, xdc_UArg *arg0, xdc_UArg *arg1 ); /* getAttrs__E */ extern void ti_sysbios_knl_Swi_getAttrs__E( ti_sysbios_knl_Swi_Handle __inst, ti_sysbios_knl_Swi_FuncPtr *swiFxn, ti_sysbios_knl_Swi_Params *params ); /* setAttrs__E */ extern void ti_sysbios_knl_Swi_setAttrs__E( ti_sysbios_knl_Swi_Handle __inst, ti_sysbios_knl_Swi_FuncPtr swiFxn, ti_sysbios_knl_Swi_Params *params ); /* setPri__E */ extern void ti_sysbios_knl_Swi_setPri__E( ti_sysbios_knl_Swi_Handle __inst, xdc_UInt priority ); /* inc__E */ extern void ti_sysbios_knl_Swi_inc__E( ti_sysbios_knl_Swi_Handle __inst ); /* or__E */ extern void ti_sysbios_knl_Swi_or__E( ti_sysbios_knl_Swi_Handle __inst, xdc_UInt mask ); /* post__E */ extern void ti_sysbios_knl_Swi_post__E( ti_sysbios_knl_Swi_Handle __inst ); /* schedule__I */ extern void ti_sysbios_knl_Swi_schedule__I( void ); /* runLoop__I */ extern void ti_sysbios_knl_Swi_runLoop__I( void ); /* run__I */ extern void ti_sysbios_knl_Swi_run__I( ti_sysbios_knl_Swi_Object *swi ); /* postInit__I */ extern xdc_Int ti_sysbios_knl_Swi_postInit__I( ti_sysbios_knl_Swi_Object *swi, xdc_runtime_Error_Block *eb ); /* restoreSMP__I */ extern void ti_sysbios_knl_Swi_restoreSMP__I( void ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Swi_Module__id ti_sysbios_knl_Swi_Module_id(void); static inline CT__ti_sysbios_knl_Swi_Module__id ti_sysbios_knl_Swi_Module_id( void ) { return ti_sysbios_knl_Swi_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_knl_Swi_Module_hasMask(void); static inline xdc_Bool ti_sysbios_knl_Swi_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_knl_Swi_Module__diagsMask__C != (CT__ti_sysbios_knl_Swi_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_knl_Swi_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_knl_Swi_Module_getMask(void) { return (ti_sysbios_knl_Swi_Module__diagsMask__C != (CT__ti_sysbios_knl_Swi_Module__diagsMask)0) ? *ti_sysbios_knl_Swi_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_knl_Swi_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_knl_Swi_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_knl_Swi_Module__diagsMask__C != (CT__ti_sysbios_knl_Swi_Module__diagsMask)0) { *ti_sysbios_knl_Swi_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_knl_Swi_Params_init(ti_sysbios_knl_Swi_Params *prms); static inline void ti_sysbios_knl_Swi_Params_init( ti_sysbios_knl_Swi_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Swi_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Swi_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Swi_Params_copy(ti_sysbios_knl_Swi_Params *dst, const ti_sysbios_knl_Swi_Params *src); static inline void ti_sysbios_knl_Swi_Params_copy(ti_sysbios_knl_Swi_Params *dst, const ti_sysbios_knl_Swi_Params *src) { if (dst != 0) { ti_sysbios_knl_Swi_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Swi_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_Object_get(ti_sysbios_knl_Swi_Instance_State *oarr, int i); static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_Object_get(ti_sysbios_knl_Swi_Instance_State *oarr, int i) { return (ti_sysbios_knl_Swi_Handle)ti_sysbios_knl_Swi_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_Object_first(void); static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_Object_first(void) { return (ti_sysbios_knl_Swi_Handle)ti_sysbios_knl_Swi_Object__first__S(); } /* Object_next */ static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_Object_next(ti_sysbios_knl_Swi_Object *obj); static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_Object_next(ti_sysbios_knl_Swi_Object *obj) { return (ti_sysbios_knl_Swi_Handle)ti_sysbios_knl_Swi_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_knl_Swi_Handle_label(ti_sysbios_knl_Swi_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_knl_Swi_Handle_label(ti_sysbios_knl_Swi_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_knl_Swi_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_knl_Swi_Handle_name(ti_sysbios_knl_Swi_Handle inst); static inline xdc_String ti_sysbios_knl_Swi_Handle_name(ti_sysbios_knl_Swi_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_knl_Swi_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_handle(ti_sysbios_knl_Swi_Struct *str); static inline ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_handle(ti_sysbios_knl_Swi_Struct *str) { return (ti_sysbios_knl_Swi_Handle)str; } /* struct */ static inline ti_sysbios_knl_Swi_Struct *ti_sysbios_knl_Swi_struct(ti_sysbios_knl_Swi_Handle inst); static inline ti_sysbios_knl_Swi_Struct *ti_sysbios_knl_Swi_struct(ti_sysbios_knl_Swi_Handle inst) { return (ti_sysbios_knl_Swi_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef ti_sysbios_interfaces_ITimer_FuncPtr ti_sysbios_knl_Clock_TimerProxy_FuncPtr; /* ANY */ /* StartMode */ typedef ti_sysbios_interfaces_ITimer_StartMode ti_sysbios_knl_Clock_TimerProxy_StartMode; /* RunMode */ typedef ti_sysbios_interfaces_ITimer_RunMode ti_sysbios_knl_Clock_TimerProxy_RunMode; /* Status */ typedef ti_sysbios_interfaces_ITimer_Status ti_sysbios_knl_Clock_TimerProxy_Status; /* PeriodType */ typedef ti_sysbios_interfaces_ITimer_PeriodType ti_sysbios_knl_Clock_TimerProxy_PeriodType; /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_knl_Clock_TimerProxy_Args__create { xdc_Int id; ti_sysbios_interfaces_ITimer_FuncPtr tickFxn; } ti_sysbios_knl_Clock_TimerProxy_Args__create; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Clock_TimerProxy_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__diagsEnabled ti_sysbios_knl_Clock_TimerProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Clock_TimerProxy_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__diagsIncluded ti_sysbios_knl_Clock_TimerProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Clock_TimerProxy_Module__diagsMask; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__diagsMask ti_sysbios_knl_Clock_TimerProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_TimerProxy_Module__gateObj; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__gateObj ti_sysbios_knl_Clock_TimerProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_TimerProxy_Module__gatePrms; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__gatePrms ti_sysbios_knl_Clock_TimerProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Clock_TimerProxy_Module__id; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__id ti_sysbios_knl_Clock_TimerProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerDefined; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerDefined ti_sysbios_knl_Clock_TimerProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerObj; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerObj ti_sysbios_knl_Clock_TimerProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn0 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn1 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn2 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn4 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn8 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Clock_TimerProxy_Object__count; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Object__count ti_sysbios_knl_Clock_TimerProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Clock_TimerProxy_Object__heap; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Object__heap ti_sysbios_knl_Clock_TimerProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Clock_TimerProxy_Object__sizeof; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Object__sizeof ti_sysbios_knl_Clock_TimerProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_TimerProxy_Object__table; extern const CT__ti_sysbios_knl_Clock_TimerProxy_Object__table ti_sysbios_knl_Clock_TimerProxy_Object__table__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Clock_TimerProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_interfaces_ITimer_RunMode runMode; ti_sysbios_interfaces_ITimer_StartMode startMode; xdc_UArg arg; xdc_UInt32 period; ti_sysbios_interfaces_ITimer_PeriodType periodType; xdc_runtime_Types_FreqHz extFreq; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Clock_TimerProxy_Struct { const ti_sysbios_knl_Clock_TimerProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_knl_Clock_TimerProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_UInt (*getNumTimers)(void); ti_sysbios_interfaces_ITimer_Status (*getStatus)(xdc_UInt id); void (*startup)(void); xdc_UInt32 (*getMaxTicks)(ti_sysbios_knl_Clock_TimerProxy_Handle inst); void (*setNextTick)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_UInt32 ticks); void (*start)(ti_sysbios_knl_Clock_TimerProxy_Handle inst); void (*stop)(ti_sysbios_knl_Clock_TimerProxy_Handle inst); void (*setPeriod)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_UInt32 period); xdc_Bool (*setPeriodMicroSecs)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_UInt32 microsecs); xdc_UInt32 (*getPeriod)(ti_sysbios_knl_Clock_TimerProxy_Handle inst); xdc_UInt32 (*getCount)(ti_sysbios_knl_Clock_TimerProxy_Handle inst); void (*getFreq)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_runtime_Types_FreqHz* freq); ti_sysbios_interfaces_ITimer_FuncPtr (*getFunc)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_UArg* arg); void (*setFunc)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg); void (*trigger)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_UInt32 cycles); xdc_UInt32 (*getExpiredCounts)(ti_sysbios_knl_Clock_TimerProxy_Handle inst); xdc_UInt32 (*getExpiredTicks)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_UInt32 tickPeriod); xdc_UInt32 (*getCurrentTick)(ti_sysbios_knl_Clock_TimerProxy_Handle inst, xdc_Bool save); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_knl_Clock_TimerProxy_Fxns__ ti_sysbios_knl_Clock_TimerProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern ti_sysbios_knl_Clock_TimerProxy_Handle ti_sysbios_knl_Clock_TimerProxy_create( xdc_Int id, ti_sysbios_interfaces_ITimer_FuncPtr tickFxn, const ti_sysbios_knl_Clock_TimerProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_knl_Clock_TimerProxy_delete(ti_sysbios_knl_Clock_TimerProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Clock_TimerProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Clock_TimerProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Clock_TimerProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Clock_TimerProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Clock_TimerProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Clock_TimerProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool ti_sysbios_knl_Clock_TimerProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr ti_sysbios_knl_Clock_TimerProxy_Proxy__delegate__S( void ); /* getNumTimers__E */ extern xdc_UInt ti_sysbios_knl_Clock_TimerProxy_getNumTimers__E( void ); /* getStatus__E */ extern ti_sysbios_interfaces_ITimer_Status ti_sysbios_knl_Clock_TimerProxy_getStatus__E( xdc_UInt id ); /* startup__E */ extern void ti_sysbios_knl_Clock_TimerProxy_startup__E( void ); /* getMaxTicks__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getMaxTicks__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ); /* setNextTick__E */ extern void ti_sysbios_knl_Clock_TimerProxy_setNextTick__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 ticks ); /* start__E */ extern void ti_sysbios_knl_Clock_TimerProxy_start__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ); /* stop__E */ extern void ti_sysbios_knl_Clock_TimerProxy_stop__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ); /* setPeriod__E */ extern void ti_sysbios_knl_Clock_TimerProxy_setPeriod__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 period ); /* setPeriodMicroSecs__E */ extern xdc_Bool ti_sysbios_knl_Clock_TimerProxy_setPeriodMicroSecs__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 microsecs ); /* getPeriod__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getPeriod__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ); /* getCount__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getCount__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ); /* getFreq__E */ extern void ti_sysbios_knl_Clock_TimerProxy_getFreq__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_runtime_Types_FreqHz *freq ); /* getFunc__E */ extern ti_sysbios_interfaces_ITimer_FuncPtr ti_sysbios_knl_Clock_TimerProxy_getFunc__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UArg *arg ); /* setFunc__E */ extern void ti_sysbios_knl_Clock_TimerProxy_setFunc__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg ); /* trigger__E */ extern void ti_sysbios_knl_Clock_TimerProxy_trigger__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 cycles ); /* getExpiredCounts__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getExpiredCounts__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ); /* getExpiredTicks__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getExpiredTicks__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 tickPeriod ); /* getCurrentTick__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getCurrentTick__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_Bool save ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline ti_sysbios_interfaces_ITimer_Module ti_sysbios_knl_Clock_TimerProxy_Module_upCast(void); static inline ti_sysbios_interfaces_ITimer_Module ti_sysbios_knl_Clock_TimerProxy_Module_upCast(void) { return (ti_sysbios_interfaces_ITimer_Module)ti_sysbios_knl_Clock_TimerProxy_Proxy__delegate__S(); } /* Module_to_ti_sysbios_interfaces_ITimer */ /* Handle_upCast */ static inline ti_sysbios_interfaces_ITimer_Handle ti_sysbios_knl_Clock_TimerProxy_Handle_upCast(ti_sysbios_knl_Clock_TimerProxy_Handle i); static inline ti_sysbios_interfaces_ITimer_Handle ti_sysbios_knl_Clock_TimerProxy_Handle_upCast(ti_sysbios_knl_Clock_TimerProxy_Handle i) { return (ti_sysbios_interfaces_ITimer_Handle)i; } /* Handle_to_ti_sysbios_interfaces_ITimer */ /* Handle_downCast */ static inline ti_sysbios_knl_Clock_TimerProxy_Handle ti_sysbios_knl_Clock_TimerProxy_Handle_downCast(ti_sysbios_interfaces_ITimer_Handle i); static inline ti_sysbios_knl_Clock_TimerProxy_Handle ti_sysbios_knl_Clock_TimerProxy_Handle_downCast(ti_sysbios_interfaces_ITimer_Handle i) { ti_sysbios_interfaces_ITimer_Handle i2 = (ti_sysbios_interfaces_ITimer_Handle)i; if (ti_sysbios_knl_Clock_TimerProxy_Proxy__abstract__S()) { return (ti_sysbios_knl_Clock_TimerProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)ti_sysbios_knl_Clock_TimerProxy_Proxy__delegate__S()) ? (ti_sysbios_knl_Clock_TimerProxy_Handle)i : (ti_sysbios_knl_Clock_TimerProxy_Handle)0; } /* Handle_from_ti_sysbios_interfaces_ITimer */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Clock_TimerProxy_Module__id ti_sysbios_knl_Clock_TimerProxy_Module_id(void); static inline CT__ti_sysbios_knl_Clock_TimerProxy_Module__id ti_sysbios_knl_Clock_TimerProxy_Module_id( void ) { return ti_sysbios_knl_Clock_TimerProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void ti_sysbios_knl_Clock_TimerProxy_Params_init(ti_sysbios_knl_Clock_TimerProxy_Params *prms); static inline void ti_sysbios_knl_Clock_TimerProxy_Params_init( ti_sysbios_knl_Clock_TimerProxy_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Clock_TimerProxy_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Clock_TimerProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Clock_TimerProxy_Params_copy(ti_sysbios_knl_Clock_TimerProxy_Params *dst, const ti_sysbios_knl_Clock_TimerProxy_Params *src); static inline void ti_sysbios_knl_Clock_TimerProxy_Params_copy(ti_sysbios_knl_Clock_TimerProxy_Params *dst, const ti_sysbios_knl_Clock_TimerProxy_Params *src) { if (dst != 0) { ti_sysbios_knl_Clock_TimerProxy_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Clock_TimerProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* TickSource */ enum ti_sysbios_knl_Clock_TickSource { ti_sysbios_knl_Clock_TickSource_TIMER, ti_sysbios_knl_Clock_TickSource_USER, ti_sysbios_knl_Clock_TickSource_NULL }; typedef enum ti_sysbios_knl_Clock_TickSource ti_sysbios_knl_Clock_TickSource; /* TickMode */ enum ti_sysbios_knl_Clock_TickMode { ti_sysbios_knl_Clock_TickMode_PERIODIC, ti_sysbios_knl_Clock_TickMode_DYNAMIC }; typedef enum ti_sysbios_knl_Clock_TickMode ti_sysbios_knl_Clock_TickMode; /* FuncPtr */ typedef void (*ti_sysbios_knl_Clock_FuncPtr)(xdc_UArg arg1); /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_knl_Clock_Args__create { ti_sysbios_knl_Clock_FuncPtr clockFxn; xdc_UInt timeout; } ti_sysbios_knl_Clock_Args__create; /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Clock_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Clock_Module__diagsEnabled ti_sysbios_knl_Clock_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Clock_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Clock_Module__diagsIncluded ti_sysbios_knl_Clock_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Clock_Module__diagsMask; extern const CT__ti_sysbios_knl_Clock_Module__diagsMask ti_sysbios_knl_Clock_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_Module__gateObj; extern const CT__ti_sysbios_knl_Clock_Module__gateObj ti_sysbios_knl_Clock_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_Module__gatePrms; extern const CT__ti_sysbios_knl_Clock_Module__gatePrms ti_sysbios_knl_Clock_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Clock_Module__id; extern const CT__ti_sysbios_knl_Clock_Module__id ti_sysbios_knl_Clock_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Clock_Module__loggerDefined; extern const CT__ti_sysbios_knl_Clock_Module__loggerDefined ti_sysbios_knl_Clock_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_Module__loggerObj; extern const CT__ti_sysbios_knl_Clock_Module__loggerObj ti_sysbios_knl_Clock_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Clock_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Clock_Module__loggerFxn0 ti_sysbios_knl_Clock_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Clock_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Clock_Module__loggerFxn1 ti_sysbios_knl_Clock_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Clock_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Clock_Module__loggerFxn2 ti_sysbios_knl_Clock_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Clock_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Clock_Module__loggerFxn4 ti_sysbios_knl_Clock_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Clock_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Clock_Module__loggerFxn8 ti_sysbios_knl_Clock_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Clock_Object__count; extern const CT__ti_sysbios_knl_Clock_Object__count ti_sysbios_knl_Clock_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Clock_Object__heap; extern const CT__ti_sysbios_knl_Clock_Object__heap ti_sysbios_knl_Clock_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Clock_Object__sizeof; extern const CT__ti_sysbios_knl_Clock_Object__sizeof ti_sysbios_knl_Clock_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Clock_Object__table; extern const CT__ti_sysbios_knl_Clock_Object__table ti_sysbios_knl_Clock_Object__table__C; /* LW_delayed */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Clock_LW_delayed; extern const CT__ti_sysbios_knl_Clock_LW_delayed ti_sysbios_knl_Clock_LW_delayed__C; /* LM_tick */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Clock_LM_tick; extern const CT__ti_sysbios_knl_Clock_LM_tick ti_sysbios_knl_Clock_LM_tick__C; /* LM_begin */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Clock_LM_begin; extern const CT__ti_sysbios_knl_Clock_LM_begin ti_sysbios_knl_Clock_LM_begin__C; /* A_clockDisabled */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Clock_A_clockDisabled; extern const CT__ti_sysbios_knl_Clock_A_clockDisabled ti_sysbios_knl_Clock_A_clockDisabled__C; /* A_badThreadType */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Clock_A_badThreadType; extern const CT__ti_sysbios_knl_Clock_A_badThreadType ti_sysbios_knl_Clock_A_badThreadType__C; /* serviceMargin */ typedef xdc_UInt32 CT__ti_sysbios_knl_Clock_serviceMargin; extern const CT__ti_sysbios_knl_Clock_serviceMargin ti_sysbios_knl_Clock_serviceMargin__C; /* tickSource */ typedef ti_sysbios_knl_Clock_TickSource CT__ti_sysbios_knl_Clock_tickSource; extern const CT__ti_sysbios_knl_Clock_tickSource ti_sysbios_knl_Clock_tickSource__C; /* tickMode */ typedef ti_sysbios_knl_Clock_TickMode CT__ti_sysbios_knl_Clock_tickMode; extern const CT__ti_sysbios_knl_Clock_tickMode ti_sysbios_knl_Clock_tickMode__C; /* timerId */ typedef xdc_UInt CT__ti_sysbios_knl_Clock_timerId; extern const CT__ti_sysbios_knl_Clock_timerId ti_sysbios_knl_Clock_timerId__C; /* tickPeriod */ typedef xdc_UInt32 CT__ti_sysbios_knl_Clock_tickPeriod; extern const CT__ti_sysbios_knl_Clock_tickPeriod ti_sysbios_knl_Clock_tickPeriod__C; /* doTickFunc */ typedef void (*CT__ti_sysbios_knl_Clock_doTickFunc)(xdc_UArg arg1); extern const CT__ti_sysbios_knl_Clock_doTickFunc ti_sysbios_knl_Clock_doTickFunc__C; /* triggerClock */ typedef ti_sysbios_knl_Clock_Handle CT__ti_sysbios_knl_Clock_triggerClock; extern const CT__ti_sysbios_knl_Clock_triggerClock ti_sysbios_knl_Clock_triggerClock__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Clock_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_Bool startFlag; xdc_UInt32 period; xdc_UArg arg; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Clock_Struct { ti_sysbios_knl_Queue_Elem f0; xdc_UInt32 f1; xdc_UInt32 f2; xdc_UInt32 f3; volatile xdc_Bool f4; ti_sysbios_knl_Clock_FuncPtr f5; xdc_UArg f6; xdc_runtime_Types_CordAddr __name; }; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_knl_Clock_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_knl_Clock_Module_startup__F( xdc_Int state ); /* Instance_init__E */ extern void ti_sysbios_knl_Clock_Instance_init__E(ti_sysbios_knl_Clock_Object *obj, ti_sysbios_knl_Clock_FuncPtr clockFxn, xdc_UInt timeout, const ti_sysbios_knl_Clock_Params *prms); /* Instance_finalize__E */ extern void ti_sysbios_knl_Clock_Instance_finalize__E(ti_sysbios_knl_Clock_Object *obj); /* create */ extern ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_create( ti_sysbios_knl_Clock_FuncPtr clockFxn, xdc_UInt timeout, const ti_sysbios_knl_Clock_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_knl_Clock_construct(ti_sysbios_knl_Clock_Struct *obj, ti_sysbios_knl_Clock_FuncPtr clockFxn, xdc_UInt timeout, const ti_sysbios_knl_Clock_Params *prms); /* delete */ extern void ti_sysbios_knl_Clock_delete(ti_sysbios_knl_Clock_Handle *instp); /* destruct */ extern void ti_sysbios_knl_Clock_destruct(ti_sysbios_knl_Clock_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Clock_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Clock_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_knl_Clock_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_knl_Clock_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Clock_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Clock_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Clock_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Clock_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* getTicks__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getTicks__E( void ); /* getTimerHandle__E */ extern ti_sysbios_knl_Clock_TimerProxy_Handle ti_sysbios_knl_Clock_getTimerHandle__E( void ); /* setTicks__E */ extern void ti_sysbios_knl_Clock_setTicks__E( xdc_UInt32 ticks ); /* tickStop__E */ extern void ti_sysbios_knl_Clock_tickStop__E( void ); /* tickReconfig__E */ extern xdc_Bool ti_sysbios_knl_Clock_tickReconfig__E( void ); /* tickStart__E */ extern void ti_sysbios_knl_Clock_tickStart__E( void ); /* tick__E */ extern void ti_sysbios_knl_Clock_tick__E( void ); /* workFunc__E */ extern void ti_sysbios_knl_Clock_workFunc__E( xdc_UArg arg0, xdc_UArg arg1 ); /* workFuncDynamic__E */ extern void ti_sysbios_knl_Clock_workFuncDynamic__E( xdc_UArg arg0, xdc_UArg arg1 ); /* logTick__E */ extern void ti_sysbios_knl_Clock_logTick__E( void ); /* getCompletedTicks__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getCompletedTicks__E( void ); /* getTickPeriod__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getTickPeriod__E( void ); /* getTicksUntilInterrupt__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getTicksUntilInterrupt__E( void ); /* getTicksUntilTimeout__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getTicksUntilTimeout__E( void ); /* walkQueueDynamic__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_walkQueueDynamic__E( xdc_Bool service, xdc_UInt32 tick ); /* walkQueuePeriodic__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_walkQueuePeriodic__E( void ); /* scheduleNextTick__E */ extern void ti_sysbios_knl_Clock_scheduleNextTick__E( xdc_UInt32 deltaTicks, xdc_UInt32 absTick ); /* addI__E */ extern void ti_sysbios_knl_Clock_addI__E( ti_sysbios_knl_Clock_Handle __inst, ti_sysbios_knl_Clock_FuncPtr clockFxn, xdc_UInt32 timeout, xdc_UArg arg ); /* removeI__E */ extern void ti_sysbios_knl_Clock_removeI__E( ti_sysbios_knl_Clock_Handle __inst ); /* start__E */ extern void ti_sysbios_knl_Clock_start__E( ti_sysbios_knl_Clock_Handle __inst ); /* startI__E */ extern void ti_sysbios_knl_Clock_startI__E( ti_sysbios_knl_Clock_Handle __inst ); /* stop__E */ extern void ti_sysbios_knl_Clock_stop__E( ti_sysbios_knl_Clock_Handle __inst ); /* setPeriod__E */ extern void ti_sysbios_knl_Clock_setPeriod__E( ti_sysbios_knl_Clock_Handle __inst, xdc_UInt32 period ); /* setTimeout__E */ extern void ti_sysbios_knl_Clock_setTimeout__E( ti_sysbios_knl_Clock_Handle __inst, xdc_UInt32 timeout ); /* setFunc__E */ extern void ti_sysbios_knl_Clock_setFunc__E( ti_sysbios_knl_Clock_Handle __inst, ti_sysbios_knl_Clock_FuncPtr fxn, xdc_UArg arg ); /* getPeriod__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getPeriod__E( ti_sysbios_knl_Clock_Handle __inst ); /* getTimeout__E */ extern xdc_UInt32 ti_sysbios_knl_Clock_getTimeout__E( ti_sysbios_knl_Clock_Handle __inst ); /* isActive__E */ extern xdc_Bool ti_sysbios_knl_Clock_isActive__E( ti_sysbios_knl_Clock_Handle __inst ); /* doTick__I */ extern void ti_sysbios_knl_Clock_doTick__I( xdc_UArg arg ); /* triggerFunc__I */ extern void ti_sysbios_knl_Clock_triggerFunc__I( xdc_UArg arg ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Clock_Module__id ti_sysbios_knl_Clock_Module_id(void); static inline CT__ti_sysbios_knl_Clock_Module__id ti_sysbios_knl_Clock_Module_id( void ) { return ti_sysbios_knl_Clock_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_knl_Clock_Module_hasMask(void); static inline xdc_Bool ti_sysbios_knl_Clock_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_knl_Clock_Module__diagsMask__C != (CT__ti_sysbios_knl_Clock_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_knl_Clock_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_knl_Clock_Module_getMask(void) { return (ti_sysbios_knl_Clock_Module__diagsMask__C != (CT__ti_sysbios_knl_Clock_Module__diagsMask)0) ? *ti_sysbios_knl_Clock_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_knl_Clock_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_knl_Clock_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_knl_Clock_Module__diagsMask__C != (CT__ti_sysbios_knl_Clock_Module__diagsMask)0) { *ti_sysbios_knl_Clock_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_knl_Clock_Params_init(ti_sysbios_knl_Clock_Params *prms); static inline void ti_sysbios_knl_Clock_Params_init( ti_sysbios_knl_Clock_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Clock_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Clock_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Clock_Params_copy(ti_sysbios_knl_Clock_Params *dst, const ti_sysbios_knl_Clock_Params *src); static inline void ti_sysbios_knl_Clock_Params_copy(ti_sysbios_knl_Clock_Params *dst, const ti_sysbios_knl_Clock_Params *src) { if (dst != 0) { ti_sysbios_knl_Clock_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Clock_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_Object_get(ti_sysbios_knl_Clock_Instance_State *oarr, int i); static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_Object_get(ti_sysbios_knl_Clock_Instance_State *oarr, int i) { return (ti_sysbios_knl_Clock_Handle)ti_sysbios_knl_Clock_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_Object_first(void); static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_Object_first(void) { return (ti_sysbios_knl_Clock_Handle)ti_sysbios_knl_Clock_Object__first__S(); } /* Object_next */ static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_Object_next(ti_sysbios_knl_Clock_Object *obj); static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_Object_next(ti_sysbios_knl_Clock_Object *obj) { return (ti_sysbios_knl_Clock_Handle)ti_sysbios_knl_Clock_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_knl_Clock_Handle_label(ti_sysbios_knl_Clock_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_knl_Clock_Handle_label(ti_sysbios_knl_Clock_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_knl_Clock_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_knl_Clock_Handle_name(ti_sysbios_knl_Clock_Handle inst); static inline xdc_String ti_sysbios_knl_Clock_Handle_name(ti_sysbios_knl_Clock_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_knl_Clock_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_handle(ti_sysbios_knl_Clock_Struct *str); static inline ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_handle(ti_sysbios_knl_Clock_Struct *str) { return (ti_sysbios_knl_Clock_Handle)str; } /* struct */ static inline ti_sysbios_knl_Clock_Struct *ti_sysbios_knl_Clock_struct(ti_sysbios_knl_Clock_Handle inst); static inline ti_sysbios_knl_Clock_Struct *ti_sysbios_knl_Clock_struct(ti_sysbios_knl_Clock_Handle inst) { return (ti_sysbios_knl_Clock_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef ti_sysbios_interfaces_ITaskSupport_FuncPtr ti_sysbios_knl_Task_SupportProxy_FuncPtr; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Task_SupportProxy_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__diagsEnabled ti_sysbios_knl_Task_SupportProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Task_SupportProxy_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__diagsIncluded ti_sysbios_knl_Task_SupportProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Task_SupportProxy_Module__diagsMask; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__diagsMask ti_sysbios_knl_Task_SupportProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_SupportProxy_Module__gateObj; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__gateObj ti_sysbios_knl_Task_SupportProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_SupportProxy_Module__gatePrms; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__gatePrms ti_sysbios_knl_Task_SupportProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Task_SupportProxy_Module__id; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__id ti_sysbios_knl_Task_SupportProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerDefined; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerDefined ti_sysbios_knl_Task_SupportProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerObj; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerObj ti_sysbios_knl_Task_SupportProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn0 ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn1 ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn2 ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn4 ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn8 ti_sysbios_knl_Task_SupportProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Task_SupportProxy_Object__count; extern const CT__ti_sysbios_knl_Task_SupportProxy_Object__count ti_sysbios_knl_Task_SupportProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Task_SupportProxy_Object__heap; extern const CT__ti_sysbios_knl_Task_SupportProxy_Object__heap ti_sysbios_knl_Task_SupportProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Task_SupportProxy_Object__sizeof; extern const CT__ti_sysbios_knl_Task_SupportProxy_Object__sizeof ti_sysbios_knl_Task_SupportProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_SupportProxy_Object__table; extern const CT__ti_sysbios_knl_Task_SupportProxy_Object__table ti_sysbios_knl_Task_SupportProxy_Object__table__C; /* defaultStackSize */ typedef xdc_SizeT CT__ti_sysbios_knl_Task_SupportProxy_defaultStackSize; extern const CT__ti_sysbios_knl_Task_SupportProxy_defaultStackSize ti_sysbios_knl_Task_SupportProxy_defaultStackSize__C; /* stackAlignment */ typedef xdc_UInt CT__ti_sysbios_knl_Task_SupportProxy_stackAlignment; extern const CT__ti_sysbios_knl_Task_SupportProxy_stackAlignment ti_sysbios_knl_Task_SupportProxy_stackAlignment__C; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_knl_Task_SupportProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Ptr (*start)(xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enterFxn, ti_sysbios_interfaces_ITaskSupport_FuncPtr exitFxn, xdc_runtime_Error_Block* eb); void (*swap)(xdc_Ptr* oldtskContext, xdc_Ptr* newtskContext); xdc_Bool (*checkStack)(xdc_Char* stack, xdc_SizeT size); xdc_SizeT (*stackUsed)(xdc_Char* stack, xdc_SizeT size); xdc_UInt (*getStackAlignment)(void); xdc_SizeT (*getDefaultStackSize)(void); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_knl_Task_SupportProxy_Fxns__ ti_sysbios_knl_Task_SupportProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Task_SupportProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Task_SupportProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Task_SupportProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Task_SupportProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Task_SupportProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Task_SupportProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool ti_sysbios_knl_Task_SupportProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr ti_sysbios_knl_Task_SupportProxy_Proxy__delegate__S( void ); /* start__E */ extern xdc_Ptr ti_sysbios_knl_Task_SupportProxy_start__E( xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enterFxn, ti_sysbios_interfaces_ITaskSupport_FuncPtr exitFxn, xdc_runtime_Error_Block *eb ); /* swap__E */ extern void ti_sysbios_knl_Task_SupportProxy_swap__E( xdc_Ptr *oldtskContext, xdc_Ptr *newtskContext ); /* checkStack__E */ extern xdc_Bool ti_sysbios_knl_Task_SupportProxy_checkStack__E( xdc_Char *stack, xdc_SizeT size ); /* stackUsed__E */ extern xdc_SizeT ti_sysbios_knl_Task_SupportProxy_stackUsed__E( xdc_Char *stack, xdc_SizeT size ); /* getStackAlignment__E */ extern xdc_UInt ti_sysbios_knl_Task_SupportProxy_getStackAlignment__E( void ); /* getDefaultStackSize__E */ extern xdc_SizeT ti_sysbios_knl_Task_SupportProxy_getDefaultStackSize__E( void ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline ti_sysbios_interfaces_ITaskSupport_Module ti_sysbios_knl_Task_SupportProxy_Module_upCast(void); static inline ti_sysbios_interfaces_ITaskSupport_Module ti_sysbios_knl_Task_SupportProxy_Module_upCast(void) { return (ti_sysbios_interfaces_ITaskSupport_Module)ti_sysbios_knl_Task_SupportProxy_Proxy__delegate__S(); } /* Module_to_ti_sysbios_interfaces_ITaskSupport */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Task_SupportProxy_Module__id ti_sysbios_knl_Task_SupportProxy_Module_id(void); static inline CT__ti_sysbios_knl_Task_SupportProxy_Module__id ti_sysbios_knl_Task_SupportProxy_Module_id( void ) { return ti_sysbios_knl_Task_SupportProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef void (*ti_sysbios_knl_Task_FuncPtr)(xdc_UArg arg1, xdc_UArg arg2); /* AllBlockedFuncPtr */ typedef void (*ti_sysbios_knl_Task_AllBlockedFuncPtr)(void ); /* ModStateCheckValueFuncPtr */ typedef xdc_UInt32 (*ti_sysbios_knl_Task_ModStateCheckValueFuncPtr)(ti_sysbios_knl_Task_Module_State* arg1); /* ModStateCheckFuncPtr */ typedef xdc_Int (*ti_sysbios_knl_Task_ModStateCheckFuncPtr)(ti_sysbios_knl_Task_Module_State* arg1, xdc_UInt32 arg2); /* ObjectCheckValueFuncPtr */ typedef xdc_UInt32 (*ti_sysbios_knl_Task_ObjectCheckValueFuncPtr)(ti_sysbios_knl_Task_Handle arg1); /* ObjectCheckFuncPtr */ typedef xdc_Int (*ti_sysbios_knl_Task_ObjectCheckFuncPtr)(ti_sysbios_knl_Task_Handle arg1, xdc_UInt32 arg2); /* Mode */ enum ti_sysbios_knl_Task_Mode { ti_sysbios_knl_Task_Mode_RUNNING, ti_sysbios_knl_Task_Mode_READY, ti_sysbios_knl_Task_Mode_BLOCKED, ti_sysbios_knl_Task_Mode_TERMINATED, ti_sysbios_knl_Task_Mode_INACTIVE }; typedef enum ti_sysbios_knl_Task_Mode ti_sysbios_knl_Task_Mode; /* Stat */ struct ti_sysbios_knl_Task_Stat { xdc_Int priority; xdc_Ptr stack; xdc_SizeT stackSize; xdc_runtime_IHeap_Handle stackHeap; xdc_Ptr env; ti_sysbios_knl_Task_Mode mode; xdc_Ptr sp; xdc_SizeT used; }; /* HookSet */ struct ti_sysbios_knl_Task_HookSet { void (*registerFxn)(xdc_Int arg1); void (*createFxn)(ti_sysbios_knl_Task_Handle arg1, xdc_runtime_Error_Block* arg2); void (*readyFxn)(ti_sysbios_knl_Task_Handle arg1); void (*switchFxn)(ti_sysbios_knl_Task_Handle arg1, ti_sysbios_knl_Task_Handle arg2); void (*exitFxn)(ti_sysbios_knl_Task_Handle arg1); void (*deleteFxn)(ti_sysbios_knl_Task_Handle arg1); }; /* AFFINITY_NONE */ /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_knl_Task_Args__create { ti_sysbios_knl_Task_FuncPtr fxn; } ti_sysbios_knl_Task_Args__create; /* * ======== INTERNAL DEFINITIONS ======== */ /* PendElem */ struct ti_sysbios_knl_Task_PendElem { ti_sysbios_knl_Queue_Elem qElem; ti_sysbios_knl_Task_Handle taskHandle; ti_sysbios_knl_Clock_Handle clockHandle; }; /* Instance_State */ typedef xdc_Char __T1_ti_sysbios_knl_Task_Instance_State__stack; typedef xdc_Char *ARRAY1_ti_sysbios_knl_Task_Instance_State__stack; typedef const xdc_Char *CARRAY1_ti_sysbios_knl_Task_Instance_State__stack; typedef ARRAY1_ti_sysbios_knl_Task_Instance_State__stack __TA_ti_sysbios_knl_Task_Instance_State__stack; typedef xdc_Ptr __T1_ti_sysbios_knl_Task_Instance_State__hookEnv; typedef xdc_Ptr *ARRAY1_ti_sysbios_knl_Task_Instance_State__hookEnv; typedef const xdc_Ptr *CARRAY1_ti_sysbios_knl_Task_Instance_State__hookEnv; typedef ARRAY1_ti_sysbios_knl_Task_Instance_State__hookEnv __TA_ti_sysbios_knl_Task_Instance_State__hookEnv; /* Module_State */ typedef ti_sysbios_knl_Queue_Instance_State __T1_ti_sysbios_knl_Task_Module_State__readyQ; typedef ti_sysbios_knl_Queue_Instance_State *ARRAY1_ti_sysbios_knl_Task_Module_State__readyQ; typedef const ti_sysbios_knl_Queue_Instance_State *CARRAY1_ti_sysbios_knl_Task_Module_State__readyQ; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__readyQ __TA_ti_sysbios_knl_Task_Module_State__readyQ; typedef volatile xdc_UInt __T1_ti_sysbios_knl_Task_Module_State__smpCurSet; typedef volatile xdc_UInt *ARRAY1_ti_sysbios_knl_Task_Module_State__smpCurSet; typedef const volatile xdc_UInt *CARRAY1_ti_sysbios_knl_Task_Module_State__smpCurSet; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__smpCurSet __TA_ti_sysbios_knl_Task_Module_State__smpCurSet; typedef volatile xdc_UInt __T1_ti_sysbios_knl_Task_Module_State__smpCurMask; typedef volatile xdc_UInt *ARRAY1_ti_sysbios_knl_Task_Module_State__smpCurMask; typedef const volatile xdc_UInt *CARRAY1_ti_sysbios_knl_Task_Module_State__smpCurMask; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__smpCurMask __TA_ti_sysbios_knl_Task_Module_State__smpCurMask; typedef ti_sysbios_knl_Task_Handle __T1_ti_sysbios_knl_Task_Module_State__smpCurTask; typedef ti_sysbios_knl_Task_Handle *ARRAY1_ti_sysbios_knl_Task_Module_State__smpCurTask; typedef const ti_sysbios_knl_Task_Handle *CARRAY1_ti_sysbios_knl_Task_Module_State__smpCurTask; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__smpCurTask __TA_ti_sysbios_knl_Task_Module_State__smpCurTask; typedef ti_sysbios_knl_Queue_Handle __T1_ti_sysbios_knl_Task_Module_State__smpReadyQ; typedef ti_sysbios_knl_Queue_Handle *ARRAY1_ti_sysbios_knl_Task_Module_State__smpReadyQ; typedef const ti_sysbios_knl_Queue_Handle *CARRAY1_ti_sysbios_knl_Task_Module_State__smpReadyQ; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__smpReadyQ __TA_ti_sysbios_knl_Task_Module_State__smpReadyQ; typedef ti_sysbios_knl_Task_Handle __T1_ti_sysbios_knl_Task_Module_State__idleTask; typedef ti_sysbios_knl_Task_Handle *ARRAY1_ti_sysbios_knl_Task_Module_State__idleTask; typedef const ti_sysbios_knl_Task_Handle *CARRAY1_ti_sysbios_knl_Task_Module_State__idleTask; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__idleTask __TA_ti_sysbios_knl_Task_Module_State__idleTask; typedef ti_sysbios_knl_Task_Handle __T1_ti_sysbios_knl_Task_Module_State__constructedTasks; typedef ti_sysbios_knl_Task_Handle *ARRAY1_ti_sysbios_knl_Task_Module_State__constructedTasks; typedef const ti_sysbios_knl_Task_Handle *CARRAY1_ti_sysbios_knl_Task_Module_State__constructedTasks; typedef ARRAY1_ti_sysbios_knl_Task_Module_State__constructedTasks __TA_ti_sysbios_knl_Task_Module_State__constructedTasks; /* RunQEntry */ struct ti_sysbios_knl_Task_RunQEntry { ti_sysbios_knl_Queue_Elem elem; xdc_UInt coreId; xdc_Int priority; }; /* Module_StateSmp */ typedef volatile ti_sysbios_knl_Task_RunQEntry __T1_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ; typedef volatile ti_sysbios_knl_Task_RunQEntry *ARRAY1_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ; typedef const volatile ti_sysbios_knl_Task_RunQEntry *CARRAY1_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ; typedef ARRAY1_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ __TA_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ; struct ti_sysbios_knl_Task_Module_StateSmp { ti_sysbios_knl_Queue_Object *sortedRunQ; __TA_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ smpRunQ; }; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Task_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Task_Module__diagsEnabled ti_sysbios_knl_Task_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Task_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Task_Module__diagsIncluded ti_sysbios_knl_Task_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Task_Module__diagsMask; extern const CT__ti_sysbios_knl_Task_Module__diagsMask ti_sysbios_knl_Task_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_Module__gateObj; extern const CT__ti_sysbios_knl_Task_Module__gateObj ti_sysbios_knl_Task_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_Module__gatePrms; extern const CT__ti_sysbios_knl_Task_Module__gatePrms ti_sysbios_knl_Task_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Task_Module__id; extern const CT__ti_sysbios_knl_Task_Module__id ti_sysbios_knl_Task_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Task_Module__loggerDefined; extern const CT__ti_sysbios_knl_Task_Module__loggerDefined ti_sysbios_knl_Task_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_Module__loggerObj; extern const CT__ti_sysbios_knl_Task_Module__loggerObj ti_sysbios_knl_Task_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Task_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Task_Module__loggerFxn0 ti_sysbios_knl_Task_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Task_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Task_Module__loggerFxn1 ti_sysbios_knl_Task_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Task_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Task_Module__loggerFxn2 ti_sysbios_knl_Task_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Task_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Task_Module__loggerFxn4 ti_sysbios_knl_Task_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Task_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Task_Module__loggerFxn8 ti_sysbios_knl_Task_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Task_Object__count; extern const CT__ti_sysbios_knl_Task_Object__count ti_sysbios_knl_Task_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Task_Object__heap; extern const CT__ti_sysbios_knl_Task_Object__heap ti_sysbios_knl_Task_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Task_Object__sizeof; extern const CT__ti_sysbios_knl_Task_Object__sizeof ti_sysbios_knl_Task_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Task_Object__table; extern const CT__ti_sysbios_knl_Task_Object__table ti_sysbios_knl_Task_Object__table__C; /* LM_switch */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_switch; extern const CT__ti_sysbios_knl_Task_LM_switch ti_sysbios_knl_Task_LM_switch__C; /* LM_sleep */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_sleep; extern const CT__ti_sysbios_knl_Task_LM_sleep ti_sysbios_knl_Task_LM_sleep__C; /* LD_ready */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LD_ready; extern const CT__ti_sysbios_knl_Task_LD_ready ti_sysbios_knl_Task_LD_ready__C; /* LD_block */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LD_block; extern const CT__ti_sysbios_knl_Task_LD_block ti_sysbios_knl_Task_LD_block__C; /* LM_yield */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_yield; extern const CT__ti_sysbios_knl_Task_LM_yield ti_sysbios_knl_Task_LM_yield__C; /* LM_setPri */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_setPri; extern const CT__ti_sysbios_knl_Task_LM_setPri ti_sysbios_knl_Task_LM_setPri__C; /* LD_exit */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LD_exit; extern const CT__ti_sysbios_knl_Task_LD_exit ti_sysbios_knl_Task_LD_exit__C; /* LM_setAffinity */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_setAffinity; extern const CT__ti_sysbios_knl_Task_LM_setAffinity ti_sysbios_knl_Task_LM_setAffinity__C; /* LM_schedule */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_schedule; extern const CT__ti_sysbios_knl_Task_LM_schedule ti_sysbios_knl_Task_LM_schedule__C; /* LM_noWork */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Task_LM_noWork; extern const CT__ti_sysbios_knl_Task_LM_noWork ti_sysbios_knl_Task_LM_noWork__C; /* E_stackOverflow */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Task_E_stackOverflow; extern const CT__ti_sysbios_knl_Task_E_stackOverflow ti_sysbios_knl_Task_E_stackOverflow__C; /* E_spOutOfBounds */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Task_E_spOutOfBounds; extern const CT__ti_sysbios_knl_Task_E_spOutOfBounds ti_sysbios_knl_Task_E_spOutOfBounds__C; /* E_deleteNotAllowed */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Task_E_deleteNotAllowed; extern const CT__ti_sysbios_knl_Task_E_deleteNotAllowed ti_sysbios_knl_Task_E_deleteNotAllowed__C; /* E_moduleStateCheckFailed */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Task_E_moduleStateCheckFailed; extern const CT__ti_sysbios_knl_Task_E_moduleStateCheckFailed ti_sysbios_knl_Task_E_moduleStateCheckFailed__C; /* E_objectCheckFailed */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Task_E_objectCheckFailed; extern const CT__ti_sysbios_knl_Task_E_objectCheckFailed ti_sysbios_knl_Task_E_objectCheckFailed__C; /* E_objectNotInKernelSpace */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Task_E_objectNotInKernelSpace; extern const CT__ti_sysbios_knl_Task_E_objectNotInKernelSpace ti_sysbios_knl_Task_E_objectNotInKernelSpace__C; /* A_badThreadType */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_badThreadType; extern const CT__ti_sysbios_knl_Task_A_badThreadType ti_sysbios_knl_Task_A_badThreadType__C; /* A_badTaskState */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_badTaskState; extern const CT__ti_sysbios_knl_Task_A_badTaskState ti_sysbios_knl_Task_A_badTaskState__C; /* A_noPendElem */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_noPendElem; extern const CT__ti_sysbios_knl_Task_A_noPendElem ti_sysbios_knl_Task_A_noPendElem__C; /* A_taskDisabled */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_taskDisabled; extern const CT__ti_sysbios_knl_Task_A_taskDisabled ti_sysbios_knl_Task_A_taskDisabled__C; /* A_badPriority */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_badPriority; extern const CT__ti_sysbios_knl_Task_A_badPriority ti_sysbios_knl_Task_A_badPriority__C; /* A_badTimeout */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_badTimeout; extern const CT__ti_sysbios_knl_Task_A_badTimeout ti_sysbios_knl_Task_A_badTimeout__C; /* A_badAffinity */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_badAffinity; extern const CT__ti_sysbios_knl_Task_A_badAffinity ti_sysbios_knl_Task_A_badAffinity__C; /* A_sleepTaskDisabled */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_sleepTaskDisabled; extern const CT__ti_sysbios_knl_Task_A_sleepTaskDisabled ti_sysbios_knl_Task_A_sleepTaskDisabled__C; /* A_invalidCoreId */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Task_A_invalidCoreId; extern const CT__ti_sysbios_knl_Task_A_invalidCoreId ti_sysbios_knl_Task_A_invalidCoreId__C; /* numPriorities */ typedef xdc_UInt CT__ti_sysbios_knl_Task_numPriorities; extern const CT__ti_sysbios_knl_Task_numPriorities ti_sysbios_knl_Task_numPriorities__C; /* defaultStackSize */ typedef xdc_SizeT CT__ti_sysbios_knl_Task_defaultStackSize; extern const CT__ti_sysbios_knl_Task_defaultStackSize ti_sysbios_knl_Task_defaultStackSize__C; /* defaultStackHeap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Task_defaultStackHeap; extern const CT__ti_sysbios_knl_Task_defaultStackHeap ti_sysbios_knl_Task_defaultStackHeap__C; /* allBlockedFunc */ typedef ti_sysbios_knl_Task_AllBlockedFuncPtr CT__ti_sysbios_knl_Task_allBlockedFunc; extern const CT__ti_sysbios_knl_Task_allBlockedFunc ti_sysbios_knl_Task_allBlockedFunc__C; /* initStackFlag */ typedef xdc_Bool CT__ti_sysbios_knl_Task_initStackFlag; extern const CT__ti_sysbios_knl_Task_initStackFlag ti_sysbios_knl_Task_initStackFlag__C; /* checkStackFlag */ typedef xdc_Bool CT__ti_sysbios_knl_Task_checkStackFlag; extern const CT__ti_sysbios_knl_Task_checkStackFlag ti_sysbios_knl_Task_checkStackFlag__C; /* deleteTerminatedTasks */ typedef xdc_Bool CT__ti_sysbios_knl_Task_deleteTerminatedTasks; extern const CT__ti_sysbios_knl_Task_deleteTerminatedTasks ti_sysbios_knl_Task_deleteTerminatedTasks__C; /* hooks */ typedef ti_sysbios_knl_Task_HookSet __T1_ti_sysbios_knl_Task_hooks; typedef struct { int length; ti_sysbios_knl_Task_HookSet *elem; } ARRAY1_ti_sysbios_knl_Task_hooks; typedef struct { int length; ti_sysbios_knl_Task_HookSet const *elem; } CARRAY1_ti_sysbios_knl_Task_hooks; typedef CARRAY1_ti_sysbios_knl_Task_hooks __TA_ti_sysbios_knl_Task_hooks; typedef CARRAY1_ti_sysbios_knl_Task_hooks CT__ti_sysbios_knl_Task_hooks; extern const CT__ti_sysbios_knl_Task_hooks ti_sysbios_knl_Task_hooks__C; /* moduleStateCheckFxn */ typedef ti_sysbios_knl_Task_ModStateCheckFuncPtr CT__ti_sysbios_knl_Task_moduleStateCheckFxn; extern const CT__ti_sysbios_knl_Task_moduleStateCheckFxn ti_sysbios_knl_Task_moduleStateCheckFxn__C; /* moduleStateCheckValueFxn */ typedef ti_sysbios_knl_Task_ModStateCheckValueFuncPtr CT__ti_sysbios_knl_Task_moduleStateCheckValueFxn; extern const CT__ti_sysbios_knl_Task_moduleStateCheckValueFxn ti_sysbios_knl_Task_moduleStateCheckValueFxn__C; /* moduleStateCheckFlag */ typedef xdc_Bool CT__ti_sysbios_knl_Task_moduleStateCheckFlag; extern const CT__ti_sysbios_knl_Task_moduleStateCheckFlag ti_sysbios_knl_Task_moduleStateCheckFlag__C; /* objectCheckFxn */ typedef ti_sysbios_knl_Task_ObjectCheckFuncPtr CT__ti_sysbios_knl_Task_objectCheckFxn; extern const CT__ti_sysbios_knl_Task_objectCheckFxn ti_sysbios_knl_Task_objectCheckFxn__C; /* objectCheckValueFxn */ typedef ti_sysbios_knl_Task_ObjectCheckValueFuncPtr CT__ti_sysbios_knl_Task_objectCheckValueFxn; extern const CT__ti_sysbios_knl_Task_objectCheckValueFxn ti_sysbios_knl_Task_objectCheckValueFxn__C; /* objectCheckFlag */ typedef xdc_Bool CT__ti_sysbios_knl_Task_objectCheckFlag; extern const CT__ti_sysbios_knl_Task_objectCheckFlag ti_sysbios_knl_Task_objectCheckFlag__C; /* numConstructedTasks */ typedef xdc_UInt CT__ti_sysbios_knl_Task_numConstructedTasks; extern const CT__ti_sysbios_knl_Task_numConstructedTasks ti_sysbios_knl_Task_numConstructedTasks__C; /* startupHookFunc */ typedef void (*CT__ti_sysbios_knl_Task_startupHookFunc)(void ); extern const CT__ti_sysbios_knl_Task_startupHookFunc ti_sysbios_knl_Task_startupHookFunc__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Task_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_UArg arg0; xdc_UArg arg1; xdc_Int priority; xdc_Ptr stack; xdc_SizeT stackSize; xdc_runtime_IHeap_Handle stackHeap; xdc_Ptr env; xdc_Bool vitalTaskFlag; xdc_UInt affinity; xdc_Bool privileged; xdc_Ptr domain; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Task_Struct { ti_sysbios_knl_Queue_Elem f0; volatile xdc_Int f1; xdc_UInt f2; xdc_Ptr f3; ti_sysbios_knl_Task_Mode f4; ti_sysbios_knl_Task_PendElem *f5; xdc_SizeT f6; __TA_ti_sysbios_knl_Task_Instance_State__stack f7; xdc_runtime_IHeap_Handle f8; ti_sysbios_knl_Task_FuncPtr f9; xdc_UArg f10; xdc_UArg f11; xdc_Ptr f12; __TA_ti_sysbios_knl_Task_Instance_State__hookEnv f13; xdc_Bool f14; ti_sysbios_knl_Queue_Handle f15; xdc_UInt f16; xdc_UInt f17; xdc_Bool f18; xdc_Ptr f19; xdc_UInt32 f20; xdc_Ptr f21; xdc_runtime_Types_CordAddr __name; }; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_knl_Task_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_knl_Task_Module_startup__F( xdc_Int state ); /* Instance_init__E */ extern xdc_Int ti_sysbios_knl_Task_Instance_init__E(ti_sysbios_knl_Task_Object *obj, ti_sysbios_knl_Task_FuncPtr fxn, const ti_sysbios_knl_Task_Params *prms, xdc_runtime_Error_Block *eb); /* Instance_finalize__E */ extern void ti_sysbios_knl_Task_Instance_finalize__E(ti_sysbios_knl_Task_Object *obj, int ec); /* create */ extern ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_create( ti_sysbios_knl_Task_FuncPtr fxn, const ti_sysbios_knl_Task_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_knl_Task_construct(ti_sysbios_knl_Task_Struct *obj, ti_sysbios_knl_Task_FuncPtr fxn, const ti_sysbios_knl_Task_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_knl_Task_delete(ti_sysbios_knl_Task_Handle *instp); /* destruct */ extern void ti_sysbios_knl_Task_destruct(ti_sysbios_knl_Task_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Task_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Task_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_knl_Task_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_knl_Task_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Task_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Task_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Task_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Task_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* startup__E */ extern void ti_sysbios_knl_Task_startup__E( void ); /* enabled__E */ extern xdc_Bool ti_sysbios_knl_Task_enabled__E( void ); /* unlockSched__E */ extern void ti_sysbios_knl_Task_unlockSched__E( void ); /* disable__E */ extern xdc_UInt ti_sysbios_knl_Task_disable__E( void ); /* enable__E */ extern void ti_sysbios_knl_Task_enable__E( void ); /* restore__E */ extern void ti_sysbios_knl_Task_restore__E( xdc_UInt key ); /* restoreHwi__E */ extern void ti_sysbios_knl_Task_restoreHwi__E( xdc_UInt key ); /* self__E */ extern ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_self__E( void ); /* checkStacks__E */ extern void ti_sysbios_knl_Task_checkStacks__E( ti_sysbios_knl_Task_Handle oldTask, ti_sysbios_knl_Task_Handle newTask ); /* exit__E */ extern void ti_sysbios_knl_Task_exit__E( void ); /* sleep__E */ extern void ti_sysbios_knl_Task_sleep__E( xdc_UInt32 nticks ); /* yield__E */ extern void ti_sysbios_knl_Task_yield__E( void ); /* getIdleTask__E */ extern ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_getIdleTask__E( void ); /* getIdleTaskHandle__E */ extern ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_getIdleTaskHandle__E( xdc_UInt coreId ); /* startCore__E */ extern void ti_sysbios_knl_Task_startCore__E( xdc_UInt coreId ); /* getArg0__E */ extern xdc_UArg ti_sysbios_knl_Task_getArg0__E( ti_sysbios_knl_Task_Handle __inst ); /* getArg1__E */ extern xdc_UArg ti_sysbios_knl_Task_getArg1__E( ti_sysbios_knl_Task_Handle __inst ); /* getEnv__E */ extern xdc_Ptr ti_sysbios_knl_Task_getEnv__E( ti_sysbios_knl_Task_Handle __inst ); /* getFunc__E */ extern ti_sysbios_knl_Task_FuncPtr ti_sysbios_knl_Task_getFunc__E( ti_sysbios_knl_Task_Handle __inst, xdc_UArg *arg0, xdc_UArg *arg1 ); /* getHookContext__E */ extern xdc_Ptr ti_sysbios_knl_Task_getHookContext__E( ti_sysbios_knl_Task_Handle __inst, xdc_Int id ); /* getPri__E */ extern xdc_Int ti_sysbios_knl_Task_getPri__E( ti_sysbios_knl_Task_Handle __inst ); /* setArg0__E */ extern void ti_sysbios_knl_Task_setArg0__E( ti_sysbios_knl_Task_Handle __inst, xdc_UArg arg ); /* setArg1__E */ extern void ti_sysbios_knl_Task_setArg1__E( ti_sysbios_knl_Task_Handle __inst, xdc_UArg arg ); /* setEnv__E */ extern void ti_sysbios_knl_Task_setEnv__E( ti_sysbios_knl_Task_Handle __inst, xdc_Ptr env ); /* setHookContext__E */ extern void ti_sysbios_knl_Task_setHookContext__E( ti_sysbios_knl_Task_Handle __inst, xdc_Int id, xdc_Ptr hookContext ); /* setPri__E */ extern xdc_UInt ti_sysbios_knl_Task_setPri__E( ti_sysbios_knl_Task_Handle __inst, xdc_Int newpri ); /* stat__E */ extern void ti_sysbios_knl_Task_stat__E( ti_sysbios_knl_Task_Handle __inst, ti_sysbios_knl_Task_Stat *statbuf ); /* getMode__E */ extern ti_sysbios_knl_Task_Mode ti_sysbios_knl_Task_getMode__E( ti_sysbios_knl_Task_Handle __inst ); /* setAffinity__E */ extern xdc_UInt ti_sysbios_knl_Task_setAffinity__E( ti_sysbios_knl_Task_Handle __inst, xdc_UInt coreId ); /* getAffinity__E */ extern xdc_UInt ti_sysbios_knl_Task_getAffinity__E( ti_sysbios_knl_Task_Handle __inst ); /* block__E */ extern void ti_sysbios_knl_Task_block__E( ti_sysbios_knl_Task_Handle __inst ); /* unblock__E */ extern void ti_sysbios_knl_Task_unblock__E( ti_sysbios_knl_Task_Handle __inst ); /* blockI__E */ extern void ti_sysbios_knl_Task_blockI__E( ti_sysbios_knl_Task_Handle __inst ); /* unblockI__E */ extern void ti_sysbios_knl_Task_unblockI__E( ti_sysbios_knl_Task_Handle __inst, xdc_UInt hwiKey ); /* getPrivileged__E */ extern xdc_Bool ti_sysbios_knl_Task_getPrivileged__E( ti_sysbios_knl_Task_Handle __inst ); /* schedule__I */ extern void ti_sysbios_knl_Task_schedule__I( void ); /* enter__I */ extern void ti_sysbios_knl_Task_enter__I( void ); /* enterUnpriv__I */ extern void ti_sysbios_knl_Task_enterUnpriv__I( void ); /* sleepTimeout__I */ extern void ti_sysbios_knl_Task_sleepTimeout__I( xdc_UArg arg ); /* postInit__I */ extern xdc_Int ti_sysbios_knl_Task_postInit__I( ti_sysbios_knl_Task_Object *task, xdc_runtime_Error_Block *eb ); /* allBlockedFunction__I */ extern void ti_sysbios_knl_Task_allBlockedFunction__I( void ); /* deleteTerminatedTasksFunc__I */ extern void ti_sysbios_knl_Task_deleteTerminatedTasksFunc__I( void ); /* processVitalTaskFlag__I */ extern void ti_sysbios_knl_Task_processVitalTaskFlag__I( ti_sysbios_knl_Task_Object *task ); /* moduleStateCheck__I */ extern xdc_Int ti_sysbios_knl_Task_moduleStateCheck__I( ti_sysbios_knl_Task_Module_State *moduleState, xdc_UInt32 checkValue ); /* getModuleStateCheckValue__I */ extern xdc_UInt32 ti_sysbios_knl_Task_getModuleStateCheckValue__I( ti_sysbios_knl_Task_Module_State *moduleState ); /* objectCheck__I */ extern xdc_Int ti_sysbios_knl_Task_objectCheck__I( ti_sysbios_knl_Task_Handle handle, xdc_UInt32 checkValue ); /* getObjectCheckValue__I */ extern xdc_UInt32 ti_sysbios_knl_Task_getObjectCheckValue__I( ti_sysbios_knl_Task_Handle handle ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Task_Module__id ti_sysbios_knl_Task_Module_id(void); static inline CT__ti_sysbios_knl_Task_Module__id ti_sysbios_knl_Task_Module_id( void ) { return ti_sysbios_knl_Task_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_knl_Task_Module_hasMask(void); static inline xdc_Bool ti_sysbios_knl_Task_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_knl_Task_Module__diagsMask__C != (CT__ti_sysbios_knl_Task_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_knl_Task_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_knl_Task_Module_getMask(void) { return (ti_sysbios_knl_Task_Module__diagsMask__C != (CT__ti_sysbios_knl_Task_Module__diagsMask)0) ? *ti_sysbios_knl_Task_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_knl_Task_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_knl_Task_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_knl_Task_Module__diagsMask__C != (CT__ti_sysbios_knl_Task_Module__diagsMask)0) { *ti_sysbios_knl_Task_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_knl_Task_Params_init(ti_sysbios_knl_Task_Params *prms); static inline void ti_sysbios_knl_Task_Params_init( ti_sysbios_knl_Task_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Task_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Task_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Task_Params_copy(ti_sysbios_knl_Task_Params *dst, const ti_sysbios_knl_Task_Params *src); static inline void ti_sysbios_knl_Task_Params_copy(ti_sysbios_knl_Task_Params *dst, const ti_sysbios_knl_Task_Params *src) { if (dst != 0) { ti_sysbios_knl_Task_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Task_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_Object_get(ti_sysbios_knl_Task_Instance_State *oarr, int i); static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_Object_get(ti_sysbios_knl_Task_Instance_State *oarr, int i) { return (ti_sysbios_knl_Task_Handle)ti_sysbios_knl_Task_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_Object_first(void); static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_Object_first(void) { return (ti_sysbios_knl_Task_Handle)ti_sysbios_knl_Task_Object__first__S(); } /* Object_next */ static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_Object_next(ti_sysbios_knl_Task_Object *obj); static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_Object_next(ti_sysbios_knl_Task_Object *obj) { return (ti_sysbios_knl_Task_Handle)ti_sysbios_knl_Task_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_knl_Task_Handle_label(ti_sysbios_knl_Task_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_knl_Task_Handle_label(ti_sysbios_knl_Task_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_knl_Task_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_knl_Task_Handle_name(ti_sysbios_knl_Task_Handle inst); static inline xdc_String ti_sysbios_knl_Task_Handle_name(ti_sysbios_knl_Task_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_knl_Task_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_handle(ti_sysbios_knl_Task_Struct *str); static inline ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_handle(ti_sysbios_knl_Task_Struct *str) { return (ti_sysbios_knl_Task_Handle)str; } /* struct */ static inline ti_sysbios_knl_Task_Struct *ti_sysbios_knl_Task_struct(ti_sysbios_knl_Task_Handle inst); static inline ti_sysbios_knl_Task_Struct *ti_sysbios_knl_Task_struct(ti_sysbios_knl_Task_Handle inst) { return (ti_sysbios_knl_Task_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2012-2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== Task_selfMacro ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * MODULE-WIDE CONFIGS * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2012, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Id_00 */ /* Id_01 */ /* Id_02 */ /* Id_03 */ /* Id_04 */ /* Id_05 */ /* Id_06 */ /* Id_07 */ /* Id_08 */ /* Id_09 */ /* Id_10 */ /* Id_11 */ /* Id_12 */ /* Id_13 */ /* Id_14 */ /* Id_15 */ /* Id_16 */ /* Id_17 */ /* Id_18 */ /* Id_19 */ /* Id_20 */ /* Id_21 */ /* Id_22 */ /* Id_23 */ /* Id_24 */ /* Id_25 */ /* Id_26 */ /* Id_27 */ /* Id_28 */ /* Id_29 */ /* Id_30 */ /* Id_31 */ /* Id_NONE */ /* * ======== INTERNAL DEFINITIONS ======== */ /* PendState */ enum ti_sysbios_knl_Event_PendState { ti_sysbios_knl_Event_PendState_TIMEOUT = 0, ti_sysbios_knl_Event_PendState_POSTED = 1, ti_sysbios_knl_Event_PendState_CLOCK_WAIT = 2, ti_sysbios_knl_Event_PendState_WAIT_FOREVER = 3 }; typedef enum ti_sysbios_knl_Event_PendState ti_sysbios_knl_Event_PendState; /* PendElem */ struct ti_sysbios_knl_Event_PendElem { ti_sysbios_knl_Task_PendElem tpElem; volatile ti_sysbios_knl_Event_PendState pendState; xdc_UInt matchingEvents; xdc_UInt andMask; xdc_UInt orMask; }; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Event_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Event_Module__diagsEnabled ti_sysbios_knl_Event_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Event_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Event_Module__diagsIncluded ti_sysbios_knl_Event_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Event_Module__diagsMask; extern const CT__ti_sysbios_knl_Event_Module__diagsMask ti_sysbios_knl_Event_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Event_Module__gateObj; extern const CT__ti_sysbios_knl_Event_Module__gateObj ti_sysbios_knl_Event_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Event_Module__gatePrms; extern const CT__ti_sysbios_knl_Event_Module__gatePrms ti_sysbios_knl_Event_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Event_Module__id; extern const CT__ti_sysbios_knl_Event_Module__id ti_sysbios_knl_Event_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Event_Module__loggerDefined; extern const CT__ti_sysbios_knl_Event_Module__loggerDefined ti_sysbios_knl_Event_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Event_Module__loggerObj; extern const CT__ti_sysbios_knl_Event_Module__loggerObj ti_sysbios_knl_Event_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Event_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Event_Module__loggerFxn0 ti_sysbios_knl_Event_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Event_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Event_Module__loggerFxn1 ti_sysbios_knl_Event_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Event_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Event_Module__loggerFxn2 ti_sysbios_knl_Event_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Event_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Event_Module__loggerFxn4 ti_sysbios_knl_Event_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Event_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Event_Module__loggerFxn8 ti_sysbios_knl_Event_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Event_Object__count; extern const CT__ti_sysbios_knl_Event_Object__count ti_sysbios_knl_Event_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Event_Object__heap; extern const CT__ti_sysbios_knl_Event_Object__heap ti_sysbios_knl_Event_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Event_Object__sizeof; extern const CT__ti_sysbios_knl_Event_Object__sizeof ti_sysbios_knl_Event_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Event_Object__table; extern const CT__ti_sysbios_knl_Event_Object__table ti_sysbios_knl_Event_Object__table__C; /* LM_post */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Event_LM_post; extern const CT__ti_sysbios_knl_Event_LM_post ti_sysbios_knl_Event_LM_post__C; /* LM_pend */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Event_LM_pend; extern const CT__ti_sysbios_knl_Event_LM_pend ti_sysbios_knl_Event_LM_pend__C; /* A_nullEventMasks */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Event_A_nullEventMasks; extern const CT__ti_sysbios_knl_Event_A_nullEventMasks ti_sysbios_knl_Event_A_nullEventMasks__C; /* A_nullEventId */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Event_A_nullEventId; extern const CT__ti_sysbios_knl_Event_A_nullEventId ti_sysbios_knl_Event_A_nullEventId__C; /* A_eventInUse */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Event_A_eventInUse; extern const CT__ti_sysbios_knl_Event_A_eventInUse ti_sysbios_knl_Event_A_eventInUse__C; /* A_badContext */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Event_A_badContext; extern const CT__ti_sysbios_knl_Event_A_badContext ti_sysbios_knl_Event_A_badContext__C; /* A_pendTaskDisabled */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Event_A_pendTaskDisabled; extern const CT__ti_sysbios_knl_Event_A_pendTaskDisabled ti_sysbios_knl_Event_A_pendTaskDisabled__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Event_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Event_Struct { volatile xdc_UInt f0; ti_sysbios_knl_Queue_Struct f1; xdc_runtime_Types_CordAddr __name; }; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Instance_init__E */ extern void ti_sysbios_knl_Event_Instance_init__E(ti_sysbios_knl_Event_Object *obj, const ti_sysbios_knl_Event_Params *prms); /* create */ extern ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_create( const ti_sysbios_knl_Event_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_knl_Event_construct(ti_sysbios_knl_Event_Struct *obj, const ti_sysbios_knl_Event_Params *prms); /* delete */ extern void ti_sysbios_knl_Event_delete(ti_sysbios_knl_Event_Handle *instp); /* destruct */ extern void ti_sysbios_knl_Event_destruct(ti_sysbios_knl_Event_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Event_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Event_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_knl_Event_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_knl_Event_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Event_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Event_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Event_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Event_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* pend__E */ extern xdc_UInt ti_sysbios_knl_Event_pend__E( ti_sysbios_knl_Event_Handle __inst, xdc_UInt andMask, xdc_UInt orMask, xdc_UInt32 timeout ); /* post__E */ extern void ti_sysbios_knl_Event_post__E( ti_sysbios_knl_Event_Handle __inst, xdc_UInt eventMask ); /* getPostedEvents__E */ extern xdc_UInt ti_sysbios_knl_Event_getPostedEvents__E( ti_sysbios_knl_Event_Handle __inst ); /* sync__E */ extern void ti_sysbios_knl_Event_sync__E( ti_sysbios_knl_Event_Handle __inst, xdc_UInt eventId, xdc_UInt count ); /* pendTimeout__I */ extern void ti_sysbios_knl_Event_pendTimeout__I( xdc_UArg arg ); /* checkEvents__I */ extern xdc_UInt ti_sysbios_knl_Event_checkEvents__I( ti_sysbios_knl_Event_Object *event, xdc_UInt andMask, xdc_UInt orMask ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Event_Module__id ti_sysbios_knl_Event_Module_id(void); static inline CT__ti_sysbios_knl_Event_Module__id ti_sysbios_knl_Event_Module_id( void ) { return ti_sysbios_knl_Event_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_knl_Event_Module_hasMask(void); static inline xdc_Bool ti_sysbios_knl_Event_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_knl_Event_Module__diagsMask__C != (CT__ti_sysbios_knl_Event_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_knl_Event_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_knl_Event_Module_getMask(void) { return (ti_sysbios_knl_Event_Module__diagsMask__C != (CT__ti_sysbios_knl_Event_Module__diagsMask)0) ? *ti_sysbios_knl_Event_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_knl_Event_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_knl_Event_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_knl_Event_Module__diagsMask__C != (CT__ti_sysbios_knl_Event_Module__diagsMask)0) { *ti_sysbios_knl_Event_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_knl_Event_Params_init(ti_sysbios_knl_Event_Params *prms); static inline void ti_sysbios_knl_Event_Params_init( ti_sysbios_knl_Event_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Event_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Event_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Event_Params_copy(ti_sysbios_knl_Event_Params *dst, const ti_sysbios_knl_Event_Params *src); static inline void ti_sysbios_knl_Event_Params_copy(ti_sysbios_knl_Event_Params *dst, const ti_sysbios_knl_Event_Params *src) { if (dst != 0) { ti_sysbios_knl_Event_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Event_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_Object_get(ti_sysbios_knl_Event_Instance_State *oarr, int i); static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_Object_get(ti_sysbios_knl_Event_Instance_State *oarr, int i) { return (ti_sysbios_knl_Event_Handle)ti_sysbios_knl_Event_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_Object_first(void); static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_Object_first(void) { return (ti_sysbios_knl_Event_Handle)ti_sysbios_knl_Event_Object__first__S(); } /* Object_next */ static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_Object_next(ti_sysbios_knl_Event_Object *obj); static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_Object_next(ti_sysbios_knl_Event_Object *obj) { return (ti_sysbios_knl_Event_Handle)ti_sysbios_knl_Event_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_knl_Event_Handle_label(ti_sysbios_knl_Event_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_knl_Event_Handle_label(ti_sysbios_knl_Event_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_knl_Event_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_knl_Event_Handle_name(ti_sysbios_knl_Event_Handle inst); static inline xdc_String ti_sysbios_knl_Event_Handle_name(ti_sysbios_knl_Event_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_knl_Event_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_handle(ti_sysbios_knl_Event_Struct *str); static inline ti_sysbios_knl_Event_Handle ti_sysbios_knl_Event_handle(ti_sysbios_knl_Event_Struct *str) { return (ti_sysbios_knl_Event_Handle)str; } /* struct */ static inline ti_sysbios_knl_Event_Struct *ti_sysbios_knl_Event_struct(ti_sysbios_knl_Event_Handle inst); static inline ti_sysbios_knl_Event_Struct *ti_sysbios_knl_Event_struct(ti_sysbios_knl_Event_Handle inst) { return (ti_sysbios_knl_Event_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2012-2014, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* Mode */ enum ti_sysbios_knl_Semaphore_Mode { ti_sysbios_knl_Semaphore_Mode_COUNTING = 0x0, ti_sysbios_knl_Semaphore_Mode_BINARY = 0x1, ti_sysbios_knl_Semaphore_Mode_COUNTING_PRIORITY = 0x2, ti_sysbios_knl_Semaphore_Mode_BINARY_PRIORITY = 0x3 }; typedef enum ti_sysbios_knl_Semaphore_Mode ti_sysbios_knl_Semaphore_Mode; /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_knl_Semaphore_Args__create { xdc_Int count; } ti_sysbios_knl_Semaphore_Args__create; /* * ======== INTERNAL DEFINITIONS ======== */ /* PendState */ enum ti_sysbios_knl_Semaphore_PendState { ti_sysbios_knl_Semaphore_PendState_TIMEOUT = 0, ti_sysbios_knl_Semaphore_PendState_POSTED = 1, ti_sysbios_knl_Semaphore_PendState_CLOCK_WAIT = 2, ti_sysbios_knl_Semaphore_PendState_WAIT_FOREVER = 3 }; typedef enum ti_sysbios_knl_Semaphore_PendState ti_sysbios_knl_Semaphore_PendState; /* PendElem */ struct ti_sysbios_knl_Semaphore_PendElem { ti_sysbios_knl_Task_PendElem tpElem; ti_sysbios_knl_Semaphore_PendState pendState; }; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_knl_Semaphore_Module__diagsEnabled; extern const CT__ti_sysbios_knl_Semaphore_Module__diagsEnabled ti_sysbios_knl_Semaphore_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_knl_Semaphore_Module__diagsIncluded; extern const CT__ti_sysbios_knl_Semaphore_Module__diagsIncluded ti_sysbios_knl_Semaphore_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_knl_Semaphore_Module__diagsMask; extern const CT__ti_sysbios_knl_Semaphore_Module__diagsMask ti_sysbios_knl_Semaphore_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Semaphore_Module__gateObj; extern const CT__ti_sysbios_knl_Semaphore_Module__gateObj ti_sysbios_knl_Semaphore_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_knl_Semaphore_Module__gatePrms; extern const CT__ti_sysbios_knl_Semaphore_Module__gatePrms ti_sysbios_knl_Semaphore_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_knl_Semaphore_Module__id; extern const CT__ti_sysbios_knl_Semaphore_Module__id ti_sysbios_knl_Semaphore_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_knl_Semaphore_Module__loggerDefined; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerDefined ti_sysbios_knl_Semaphore_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_knl_Semaphore_Module__loggerObj; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerObj ti_sysbios_knl_Semaphore_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_knl_Semaphore_Module__loggerFxn0; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn0 ti_sysbios_knl_Semaphore_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_knl_Semaphore_Module__loggerFxn1; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn1 ti_sysbios_knl_Semaphore_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_knl_Semaphore_Module__loggerFxn2; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn2 ti_sysbios_knl_Semaphore_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_knl_Semaphore_Module__loggerFxn4; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn4 ti_sysbios_knl_Semaphore_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_knl_Semaphore_Module__loggerFxn8; extern const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn8 ti_sysbios_knl_Semaphore_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_knl_Semaphore_Object__count; extern const CT__ti_sysbios_knl_Semaphore_Object__count ti_sysbios_knl_Semaphore_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_knl_Semaphore_Object__heap; extern const CT__ti_sysbios_knl_Semaphore_Object__heap ti_sysbios_knl_Semaphore_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_knl_Semaphore_Object__sizeof; extern const CT__ti_sysbios_knl_Semaphore_Object__sizeof ti_sysbios_knl_Semaphore_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_knl_Semaphore_Object__table; extern const CT__ti_sysbios_knl_Semaphore_Object__table ti_sysbios_knl_Semaphore_Object__table__C; /* LM_post */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Semaphore_LM_post; extern const CT__ti_sysbios_knl_Semaphore_LM_post ti_sysbios_knl_Semaphore_LM_post__C; /* LM_pend */ typedef xdc_runtime_Log_Event CT__ti_sysbios_knl_Semaphore_LM_pend; extern const CT__ti_sysbios_knl_Semaphore_LM_pend ti_sysbios_knl_Semaphore_LM_pend__C; /* A_noEvents */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Semaphore_A_noEvents; extern const CT__ti_sysbios_knl_Semaphore_A_noEvents ti_sysbios_knl_Semaphore_A_noEvents__C; /* A_invTimeout */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Semaphore_A_invTimeout; extern const CT__ti_sysbios_knl_Semaphore_A_invTimeout ti_sysbios_knl_Semaphore_A_invTimeout__C; /* A_badContext */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Semaphore_A_badContext; extern const CT__ti_sysbios_knl_Semaphore_A_badContext ti_sysbios_knl_Semaphore_A_badContext__C; /* A_overflow */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Semaphore_A_overflow; extern const CT__ti_sysbios_knl_Semaphore_A_overflow ti_sysbios_knl_Semaphore_A_overflow__C; /* A_pendTaskDisabled */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_knl_Semaphore_A_pendTaskDisabled; extern const CT__ti_sysbios_knl_Semaphore_A_pendTaskDisabled ti_sysbios_knl_Semaphore_A_pendTaskDisabled__C; /* E_objectNotInKernelSpace */ typedef xdc_runtime_Error_Id CT__ti_sysbios_knl_Semaphore_E_objectNotInKernelSpace; extern const CT__ti_sysbios_knl_Semaphore_E_objectNotInKernelSpace ti_sysbios_knl_Semaphore_E_objectNotInKernelSpace__C; /* supportsEvents */ typedef xdc_Bool CT__ti_sysbios_knl_Semaphore_supportsEvents; extern const CT__ti_sysbios_knl_Semaphore_supportsEvents ti_sysbios_knl_Semaphore_supportsEvents__C; /* supportsPriority */ typedef xdc_Bool CT__ti_sysbios_knl_Semaphore_supportsPriority; extern const CT__ti_sysbios_knl_Semaphore_supportsPriority ti_sysbios_knl_Semaphore_supportsPriority__C; /* eventPost */ typedef void (*CT__ti_sysbios_knl_Semaphore_eventPost)(ti_sysbios_knl_Event_Handle arg1, xdc_UInt arg2); extern const CT__ti_sysbios_knl_Semaphore_eventPost ti_sysbios_knl_Semaphore_eventPost__C; /* eventSync */ typedef void (*CT__ti_sysbios_knl_Semaphore_eventSync)(ti_sysbios_knl_Event_Handle arg1, xdc_UInt arg2, xdc_UInt arg3); extern const CT__ti_sysbios_knl_Semaphore_eventSync ti_sysbios_knl_Semaphore_eventSync__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_knl_Semaphore_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_knl_Event_Handle event; xdc_UInt eventId; ti_sysbios_knl_Semaphore_Mode mode; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_knl_Semaphore_Struct { ti_sysbios_knl_Event_Handle f0; xdc_UInt f1; ti_sysbios_knl_Semaphore_Mode f2; volatile xdc_UInt16 f3; ti_sysbios_knl_Queue_Struct f4; xdc_runtime_Types_CordAddr __name; }; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Instance_init__E */ extern void ti_sysbios_knl_Semaphore_Instance_init__E(ti_sysbios_knl_Semaphore_Object *obj, xdc_Int count, const ti_sysbios_knl_Semaphore_Params *prms); /* Instance_finalize__E */ extern void ti_sysbios_knl_Semaphore_Instance_finalize__E(ti_sysbios_knl_Semaphore_Object *obj); /* create */ extern ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_create( xdc_Int count, const ti_sysbios_knl_Semaphore_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_knl_Semaphore_construct(ti_sysbios_knl_Semaphore_Struct *obj, xdc_Int count, const ti_sysbios_knl_Semaphore_Params *prms); /* delete */ extern void ti_sysbios_knl_Semaphore_delete(ti_sysbios_knl_Semaphore_Handle *instp); /* destruct */ extern void ti_sysbios_knl_Semaphore_destruct(ti_sysbios_knl_Semaphore_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_knl_Semaphore_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_knl_Semaphore_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_knl_Semaphore_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_knl_Semaphore_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_knl_Semaphore_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_knl_Semaphore_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_knl_Semaphore_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_knl_Semaphore_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* getCount__E */ extern xdc_Int ti_sysbios_knl_Semaphore_getCount__E( ti_sysbios_knl_Semaphore_Handle __inst ); /* pend__E */ extern xdc_Bool ti_sysbios_knl_Semaphore_pend__E( ti_sysbios_knl_Semaphore_Handle __inst, xdc_UInt32 timeout ); /* post__E */ extern void ti_sysbios_knl_Semaphore_post__E( ti_sysbios_knl_Semaphore_Handle __inst ); /* registerEvent__E */ extern void ti_sysbios_knl_Semaphore_registerEvent__E( ti_sysbios_knl_Semaphore_Handle __inst, ti_sysbios_knl_Event_Handle event, xdc_UInt eventId ); /* reset__E */ extern void ti_sysbios_knl_Semaphore_reset__E( ti_sysbios_knl_Semaphore_Handle __inst, xdc_Int count ); /* pendTimeout__I */ extern void ti_sysbios_knl_Semaphore_pendTimeout__I( xdc_UArg arg ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_knl_Semaphore_Module__id ti_sysbios_knl_Semaphore_Module_id(void); static inline CT__ti_sysbios_knl_Semaphore_Module__id ti_sysbios_knl_Semaphore_Module_id( void ) { return ti_sysbios_knl_Semaphore_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_knl_Semaphore_Module_hasMask(void); static inline xdc_Bool ti_sysbios_knl_Semaphore_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_knl_Semaphore_Module__diagsMask__C != (CT__ti_sysbios_knl_Semaphore_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_knl_Semaphore_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_knl_Semaphore_Module_getMask(void) { return (ti_sysbios_knl_Semaphore_Module__diagsMask__C != (CT__ti_sysbios_knl_Semaphore_Module__diagsMask)0) ? *ti_sysbios_knl_Semaphore_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_knl_Semaphore_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_knl_Semaphore_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_knl_Semaphore_Module__diagsMask__C != (CT__ti_sysbios_knl_Semaphore_Module__diagsMask)0) { *ti_sysbios_knl_Semaphore_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_knl_Semaphore_Params_init(ti_sysbios_knl_Semaphore_Params *prms); static inline void ti_sysbios_knl_Semaphore_Params_init( ti_sysbios_knl_Semaphore_Params *prms ) { if (prms != 0) { ti_sysbios_knl_Semaphore_Params__init__S(prms, 0, sizeof(ti_sysbios_knl_Semaphore_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_knl_Semaphore_Params_copy(ti_sysbios_knl_Semaphore_Params *dst, const ti_sysbios_knl_Semaphore_Params *src); static inline void ti_sysbios_knl_Semaphore_Params_copy(ti_sysbios_knl_Semaphore_Params *dst, const ti_sysbios_knl_Semaphore_Params *src) { if (dst != 0) { ti_sysbios_knl_Semaphore_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_knl_Semaphore_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_Object_get(ti_sysbios_knl_Semaphore_Instance_State *oarr, int i); static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_Object_get(ti_sysbios_knl_Semaphore_Instance_State *oarr, int i) { return (ti_sysbios_knl_Semaphore_Handle)ti_sysbios_knl_Semaphore_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_Object_first(void); static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_Object_first(void) { return (ti_sysbios_knl_Semaphore_Handle)ti_sysbios_knl_Semaphore_Object__first__S(); } /* Object_next */ static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_Object_next(ti_sysbios_knl_Semaphore_Object *obj); static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_Object_next(ti_sysbios_knl_Semaphore_Object *obj) { return (ti_sysbios_knl_Semaphore_Handle)ti_sysbios_knl_Semaphore_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_knl_Semaphore_Handle_label(ti_sysbios_knl_Semaphore_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_knl_Semaphore_Handle_label(ti_sysbios_knl_Semaphore_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_knl_Semaphore_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_knl_Semaphore_Handle_name(ti_sysbios_knl_Semaphore_Handle inst); static inline xdc_String ti_sysbios_knl_Semaphore_Handle_name(ti_sysbios_knl_Semaphore_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_knl_Semaphore_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_handle(ti_sysbios_knl_Semaphore_Struct *str); static inline ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_handle(ti_sysbios_knl_Semaphore_Struct *str) { return (ti_sysbios_knl_Semaphore_Handle)str; } /* struct */ static inline ti_sysbios_knl_Semaphore_Struct *ti_sysbios_knl_Semaphore_struct(ti_sysbios_knl_Semaphore_Handle inst); static inline ti_sysbios_knl_Semaphore_Struct *ti_sysbios_knl_Semaphore_struct(ti_sysbios_knl_Semaphore_Handle inst) { return (ti_sysbios_knl_Semaphore_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* proxies */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* ExtendedStats */ struct ti_sysbios_heaps_HeapBuf_ExtendedStats { xdc_UInt maxAllocatedBlocks; xdc_UInt numAllocatedBlocks; }; /* * ======== INTERNAL DEFINITIONS ======== */ /* Instance_State */ typedef xdc_Char __T1_ti_sysbios_heaps_HeapBuf_Instance_State__buf; typedef xdc_Char *ARRAY1_ti_sysbios_heaps_HeapBuf_Instance_State__buf; typedef const xdc_Char *CARRAY1_ti_sysbios_heaps_HeapBuf_Instance_State__buf; typedef ARRAY1_ti_sysbios_heaps_HeapBuf_Instance_State__buf __TA_ti_sysbios_heaps_HeapBuf_Instance_State__buf; /* Module_State */ typedef ti_sysbios_heaps_HeapBuf_Handle __T1_ti_sysbios_heaps_HeapBuf_Module_State__constructedHeaps; typedef ti_sysbios_heaps_HeapBuf_Handle *ARRAY1_ti_sysbios_heaps_HeapBuf_Module_State__constructedHeaps; typedef const ti_sysbios_heaps_HeapBuf_Handle *CARRAY1_ti_sysbios_heaps_HeapBuf_Module_State__constructedHeaps; typedef ARRAY1_ti_sysbios_heaps_HeapBuf_Module_State__constructedHeaps __TA_ti_sysbios_heaps_HeapBuf_Module_State__constructedHeaps; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_heaps_HeapBuf_Module__diagsEnabled; extern const CT__ti_sysbios_heaps_HeapBuf_Module__diagsEnabled ti_sysbios_heaps_HeapBuf_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_heaps_HeapBuf_Module__diagsIncluded; extern const CT__ti_sysbios_heaps_HeapBuf_Module__diagsIncluded ti_sysbios_heaps_HeapBuf_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_heaps_HeapBuf_Module__diagsMask; extern const CT__ti_sysbios_heaps_HeapBuf_Module__diagsMask ti_sysbios_heaps_HeapBuf_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapBuf_Module__gateObj; extern const CT__ti_sysbios_heaps_HeapBuf_Module__gateObj ti_sysbios_heaps_HeapBuf_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapBuf_Module__gatePrms; extern const CT__ti_sysbios_heaps_HeapBuf_Module__gatePrms ti_sysbios_heaps_HeapBuf_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_heaps_HeapBuf_Module__id; extern const CT__ti_sysbios_heaps_HeapBuf_Module__id ti_sysbios_heaps_HeapBuf_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_heaps_HeapBuf_Module__loggerDefined; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerDefined ti_sysbios_heaps_HeapBuf_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapBuf_Module__loggerObj; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerObj ti_sysbios_heaps_HeapBuf_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn0; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn0 ti_sysbios_heaps_HeapBuf_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn1; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn1 ti_sysbios_heaps_HeapBuf_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn2; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn2 ti_sysbios_heaps_HeapBuf_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn4; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn4 ti_sysbios_heaps_HeapBuf_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn8; extern const CT__ti_sysbios_heaps_HeapBuf_Module__loggerFxn8 ti_sysbios_heaps_HeapBuf_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_heaps_HeapBuf_Object__count; extern const CT__ti_sysbios_heaps_HeapBuf_Object__count ti_sysbios_heaps_HeapBuf_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_heaps_HeapBuf_Object__heap; extern const CT__ti_sysbios_heaps_HeapBuf_Object__heap ti_sysbios_heaps_HeapBuf_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_heaps_HeapBuf_Object__sizeof; extern const CT__ti_sysbios_heaps_HeapBuf_Object__sizeof ti_sysbios_heaps_HeapBuf_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_heaps_HeapBuf_Object__table; extern const CT__ti_sysbios_heaps_HeapBuf_Object__table ti_sysbios_heaps_HeapBuf_Object__table__C; /* A_nullBuf */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_nullBuf; extern const CT__ti_sysbios_heaps_HeapBuf_A_nullBuf ti_sysbios_heaps_HeapBuf_A_nullBuf__C; /* A_bufAlign */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_bufAlign; extern const CT__ti_sysbios_heaps_HeapBuf_A_bufAlign ti_sysbios_heaps_HeapBuf_A_bufAlign__C; /* A_invalidAlign */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_invalidAlign; extern const CT__ti_sysbios_heaps_HeapBuf_A_invalidAlign ti_sysbios_heaps_HeapBuf_A_invalidAlign__C; /* A_invalidRequestedAlign */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_invalidRequestedAlign; extern const CT__ti_sysbios_heaps_HeapBuf_A_invalidRequestedAlign ti_sysbios_heaps_HeapBuf_A_invalidRequestedAlign__C; /* A_invalidBlockSize */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_invalidBlockSize; extern const CT__ti_sysbios_heaps_HeapBuf_A_invalidBlockSize ti_sysbios_heaps_HeapBuf_A_invalidBlockSize__C; /* A_zeroBlocks */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_zeroBlocks; extern const CT__ti_sysbios_heaps_HeapBuf_A_zeroBlocks ti_sysbios_heaps_HeapBuf_A_zeroBlocks__C; /* A_zeroBufSize */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_zeroBufSize; extern const CT__ti_sysbios_heaps_HeapBuf_A_zeroBufSize ti_sysbios_heaps_HeapBuf_A_zeroBufSize__C; /* A_invalidBufSize */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_invalidBufSize; extern const CT__ti_sysbios_heaps_HeapBuf_A_invalidBufSize ti_sysbios_heaps_HeapBuf_A_invalidBufSize__C; /* A_noBlocksToFree */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_noBlocksToFree; extern const CT__ti_sysbios_heaps_HeapBuf_A_noBlocksToFree ti_sysbios_heaps_HeapBuf_A_noBlocksToFree__C; /* A_invalidFree */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_heaps_HeapBuf_A_invalidFree; extern const CT__ti_sysbios_heaps_HeapBuf_A_invalidFree ti_sysbios_heaps_HeapBuf_A_invalidFree__C; /* E_size */ typedef xdc_runtime_Error_Id CT__ti_sysbios_heaps_HeapBuf_E_size; extern const CT__ti_sysbios_heaps_HeapBuf_E_size ti_sysbios_heaps_HeapBuf_E_size__C; /* trackMaxAllocs */ typedef xdc_Bool CT__ti_sysbios_heaps_HeapBuf_trackMaxAllocs; extern const CT__ti_sysbios_heaps_HeapBuf_trackMaxAllocs ti_sysbios_heaps_HeapBuf_trackMaxAllocs__C; /* numConstructedHeaps */ typedef xdc_UInt CT__ti_sysbios_heaps_HeapBuf_numConstructedHeaps; extern const CT__ti_sysbios_heaps_HeapBuf_numConstructedHeaps ti_sysbios_heaps_HeapBuf_numConstructedHeaps__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_heaps_HeapBuf_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; xdc_SizeT align; xdc_UInt numBlocks; xdc_SizeT blockSize; xdc_runtime_Memory_Size bufSize; xdc_Ptr buf; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_heaps_HeapBuf_Struct { const ti_sysbios_heaps_HeapBuf_Fxns__ *__fxns; xdc_SizeT f0; xdc_SizeT f1; xdc_UInt f2; xdc_runtime_Memory_Size f3; __TA_ti_sysbios_heaps_HeapBuf_Instance_State__buf f4; xdc_UInt f5; xdc_UInt f6; ti_sysbios_knl_Queue_Struct f7; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_heaps_HeapBuf_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Ptr (*alloc)(ti_sysbios_heaps_HeapBuf_Handle inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block* eb); void (*free)(ti_sysbios_heaps_HeapBuf_Handle inst, xdc_Ptr block, xdc_SizeT size); xdc_Bool (*isBlocking)(ti_sysbios_heaps_HeapBuf_Handle inst); void (*getStats)(ti_sysbios_heaps_HeapBuf_Handle inst, xdc_runtime_Memory_Stats* stats); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_heaps_HeapBuf_Fxns__ ti_sysbios_heaps_HeapBuf_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_heaps_HeapBuf_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_heaps_HeapBuf_Module_startup__F( xdc_Int state ); /* Instance_init__E */ extern xdc_Int ti_sysbios_heaps_HeapBuf_Instance_init__E(ti_sysbios_heaps_HeapBuf_Object *obj, const ti_sysbios_heaps_HeapBuf_Params *prms, xdc_runtime_Error_Block *eb); /* Instance_finalize__E */ extern void ti_sysbios_heaps_HeapBuf_Instance_finalize__E(ti_sysbios_heaps_HeapBuf_Object *obj, int ec); /* create */ extern ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_create( const ti_sysbios_heaps_HeapBuf_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_heaps_HeapBuf_construct(ti_sysbios_heaps_HeapBuf_Struct *obj, const ti_sysbios_heaps_HeapBuf_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_heaps_HeapBuf_delete(ti_sysbios_heaps_HeapBuf_Handle *instp); /* destruct */ extern void ti_sysbios_heaps_HeapBuf_destruct(ti_sysbios_heaps_HeapBuf_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_heaps_HeapBuf_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_heaps_HeapBuf_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_heaps_HeapBuf_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_heaps_HeapBuf_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_heaps_HeapBuf_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_heaps_HeapBuf_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_heaps_HeapBuf_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_heaps_HeapBuf_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* free__E */ extern void ti_sysbios_heaps_HeapBuf_free__E( ti_sysbios_heaps_HeapBuf_Handle __inst, xdc_Ptr block, xdc_SizeT size ); /* getStats__E */ extern void ti_sysbios_heaps_HeapBuf_getStats__E( ti_sysbios_heaps_HeapBuf_Handle __inst, xdc_runtime_Memory_Stats *stats ); /* alloc__E */ extern xdc_Ptr ti_sysbios_heaps_HeapBuf_alloc__E( ti_sysbios_heaps_HeapBuf_Handle __inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ); /* isBlocking__E */ extern xdc_Bool ti_sysbios_heaps_HeapBuf_isBlocking__E( ti_sysbios_heaps_HeapBuf_Handle __inst ); /* getBlockSize__E */ extern xdc_SizeT ti_sysbios_heaps_HeapBuf_getBlockSize__E( ti_sysbios_heaps_HeapBuf_Handle __inst ); /* getAlign__E */ extern xdc_SizeT ti_sysbios_heaps_HeapBuf_getAlign__E( ti_sysbios_heaps_HeapBuf_Handle __inst ); /* getEndAddr__E */ extern xdc_Ptr ti_sysbios_heaps_HeapBuf_getEndAddr__E( ti_sysbios_heaps_HeapBuf_Handle __inst ); /* getExtendedStats__E */ extern void ti_sysbios_heaps_HeapBuf_getExtendedStats__E( ti_sysbios_heaps_HeapBuf_Handle __inst, ti_sysbios_heaps_HeapBuf_ExtendedStats *stats ); /* mergeHeapBufs__E */ extern void ti_sysbios_heaps_HeapBuf_mergeHeapBufs__E( ti_sysbios_heaps_HeapBuf_Handle __inst, ti_sysbios_heaps_HeapBuf_Handle heapBuf2 ); /* postInit__I */ extern void ti_sysbios_heaps_HeapBuf_postInit__I( ti_sysbios_heaps_HeapBuf_Object *heap ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline xdc_runtime_IHeap_Module ti_sysbios_heaps_HeapBuf_Module_upCast(void); static inline xdc_runtime_IHeap_Module ti_sysbios_heaps_HeapBuf_Module_upCast(void) { return (xdc_runtime_IHeap_Module)&ti_sysbios_heaps_HeapBuf_Module__FXNS__C; } /* Module_to_xdc_runtime_IHeap */ /* Handle_upCast */ static inline xdc_runtime_IHeap_Handle ti_sysbios_heaps_HeapBuf_Handle_upCast(ti_sysbios_heaps_HeapBuf_Handle i); static inline xdc_runtime_IHeap_Handle ti_sysbios_heaps_HeapBuf_Handle_upCast(ti_sysbios_heaps_HeapBuf_Handle i) { return (xdc_runtime_IHeap_Handle)i; } /* Handle_to_xdc_runtime_IHeap */ /* Handle_downCast */ static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Handle_downCast(xdc_runtime_IHeap_Handle i); static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Handle_downCast(xdc_runtime_IHeap_Handle i) { xdc_runtime_IHeap_Handle i2 = (xdc_runtime_IHeap_Handle)i; return ((const void*)i2->__fxns == (const void*)&ti_sysbios_heaps_HeapBuf_Module__FXNS__C) ? (ti_sysbios_heaps_HeapBuf_Handle)i : (ti_sysbios_heaps_HeapBuf_Handle)0; } /* Handle_from_xdc_runtime_IHeap */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_heaps_HeapBuf_Module__id ti_sysbios_heaps_HeapBuf_Module_id(void); static inline CT__ti_sysbios_heaps_HeapBuf_Module__id ti_sysbios_heaps_HeapBuf_Module_id( void ) { return ti_sysbios_heaps_HeapBuf_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_heaps_HeapBuf_Module_hasMask(void); static inline xdc_Bool ti_sysbios_heaps_HeapBuf_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_heaps_HeapBuf_Module__diagsMask__C != (CT__ti_sysbios_heaps_HeapBuf_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_heaps_HeapBuf_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_heaps_HeapBuf_Module_getMask(void) { return (ti_sysbios_heaps_HeapBuf_Module__diagsMask__C != (CT__ti_sysbios_heaps_HeapBuf_Module__diagsMask)0) ? *ti_sysbios_heaps_HeapBuf_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_heaps_HeapBuf_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_heaps_HeapBuf_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_heaps_HeapBuf_Module__diagsMask__C != (CT__ti_sysbios_heaps_HeapBuf_Module__diagsMask)0) { *ti_sysbios_heaps_HeapBuf_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_heaps_HeapBuf_Params_init(ti_sysbios_heaps_HeapBuf_Params *prms); static inline void ti_sysbios_heaps_HeapBuf_Params_init( ti_sysbios_heaps_HeapBuf_Params *prms ) { if (prms != 0) { ti_sysbios_heaps_HeapBuf_Params__init__S(prms, 0, sizeof(ti_sysbios_heaps_HeapBuf_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_heaps_HeapBuf_Params_copy(ti_sysbios_heaps_HeapBuf_Params *dst, const ti_sysbios_heaps_HeapBuf_Params *src); static inline void ti_sysbios_heaps_HeapBuf_Params_copy(ti_sysbios_heaps_HeapBuf_Params *dst, const ti_sysbios_heaps_HeapBuf_Params *src) { if (dst != 0) { ti_sysbios_heaps_HeapBuf_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_heaps_HeapBuf_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Object_get(ti_sysbios_heaps_HeapBuf_Instance_State *oarr, int i); static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Object_get(ti_sysbios_heaps_HeapBuf_Instance_State *oarr, int i) { return (ti_sysbios_heaps_HeapBuf_Handle)ti_sysbios_heaps_HeapBuf_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Object_first(void); static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Object_first(void) { return (ti_sysbios_heaps_HeapBuf_Handle)ti_sysbios_heaps_HeapBuf_Object__first__S(); } /* Object_next */ static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Object_next(ti_sysbios_heaps_HeapBuf_Object *obj); static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_Object_next(ti_sysbios_heaps_HeapBuf_Object *obj) { return (ti_sysbios_heaps_HeapBuf_Handle)ti_sysbios_heaps_HeapBuf_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_heaps_HeapBuf_Handle_label(ti_sysbios_heaps_HeapBuf_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_heaps_HeapBuf_Handle_label(ti_sysbios_heaps_HeapBuf_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_heaps_HeapBuf_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_heaps_HeapBuf_Handle_name(ti_sysbios_heaps_HeapBuf_Handle inst); static inline xdc_String ti_sysbios_heaps_HeapBuf_Handle_name(ti_sysbios_heaps_HeapBuf_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_heaps_HeapBuf_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_handle(ti_sysbios_heaps_HeapBuf_Struct *str); static inline ti_sysbios_heaps_HeapBuf_Handle ti_sysbios_heaps_HeapBuf_handle(ti_sysbios_heaps_HeapBuf_Struct *str) { return (ti_sysbios_heaps_HeapBuf_Handle)str; } /* struct */ static inline ti_sysbios_heaps_HeapBuf_Struct *ti_sysbios_heaps_HeapBuf_struct(ti_sysbios_heaps_HeapBuf_Handle inst); static inline ti_sysbios_heaps_HeapBuf_Struct *ti_sysbios_heaps_HeapBuf_struct(ti_sysbios_heaps_HeapBuf_Handle inst) { return (ti_sysbios_heaps_HeapBuf_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.family.arm.v7a.Pmu ======== */ typedef struct ti_sysbios_family_arm_v7a_Pmu_Module_State ti_sysbios_family_arm_v7a_Pmu_Module_State; /* * ======== module ti.sysbios.family.arm.v7a.Timer ======== */ typedef struct ti_sysbios_family_arm_v7a_Timer_Module_State ti_sysbios_family_arm_v7a_Timer_Module_State; typedef struct ti_sysbios_family_arm_v7a_Timer_Fxns__ ti_sysbios_family_arm_v7a_Timer_Fxns__; typedef const struct ti_sysbios_family_arm_v7a_Timer_Fxns__* ti_sysbios_family_arm_v7a_Timer_Module; typedef struct ti_sysbios_family_arm_v7a_Timer_Params ti_sysbios_family_arm_v7a_Timer_Params; typedef struct ti_sysbios_family_arm_v7a_Timer_Object ti_sysbios_family_arm_v7a_Timer_Object; typedef struct ti_sysbios_family_arm_v7a_Timer_Struct ti_sysbios_family_arm_v7a_Timer_Struct; typedef ti_sysbios_family_arm_v7a_Timer_Object* ti_sysbios_family_arm_v7a_Timer_Handle; typedef struct ti_sysbios_family_arm_v7a_Timer_Object__ ti_sysbios_family_arm_v7a_Timer_Instance_State; typedef ti_sysbios_family_arm_v7a_Timer_Object* ti_sysbios_family_arm_v7a_Timer_Instance; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2012-2017, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.hal.Cache ======== */ typedef struct ti_sysbios_hal_Cache_Fxns__ ti_sysbios_hal_Cache_Fxns__; typedef const struct ti_sysbios_hal_Cache_Fxns__* ti_sysbios_hal_Cache_Module; /* * ======== module ti.sysbios.hal.CacheNull ======== */ typedef struct ti_sysbios_hal_CacheNull_Fxns__ ti_sysbios_hal_CacheNull_Fxns__; typedef const struct ti_sysbios_hal_CacheNull_Fxns__* ti_sysbios_hal_CacheNull_Module; /* * ======== module ti.sysbios.hal.Core ======== */ typedef struct ti_sysbios_hal_Core_Fxns__ ti_sysbios_hal_Core_Fxns__; typedef const struct ti_sysbios_hal_Core_Fxns__* ti_sysbios_hal_Core_Module; /* * ======== module ti.sysbios.hal.CoreNull ======== */ typedef struct ti_sysbios_hal_CoreNull_Fxns__ ti_sysbios_hal_CoreNull_Fxns__; typedef const struct ti_sysbios_hal_CoreNull_Fxns__* ti_sysbios_hal_CoreNull_Module; /* * ======== module ti.sysbios.hal.Hwi ======== */ typedef struct ti_sysbios_hal_Hwi_Fxns__ ti_sysbios_hal_Hwi_Fxns__; typedef const struct ti_sysbios_hal_Hwi_Fxns__* ti_sysbios_hal_Hwi_Module; typedef struct ti_sysbios_hal_Hwi_Params ti_sysbios_hal_Hwi_Params; typedef struct ti_sysbios_hal_Hwi_Object ti_sysbios_hal_Hwi_Object; typedef struct ti_sysbios_hal_Hwi_Struct ti_sysbios_hal_Hwi_Struct; typedef ti_sysbios_hal_Hwi_Object* ti_sysbios_hal_Hwi_Handle; typedef struct ti_sysbios_hal_Hwi_Object__ ti_sysbios_hal_Hwi_Instance_State; typedef ti_sysbios_hal_Hwi_Object* ti_sysbios_hal_Hwi_Instance; /* * ======== module ti.sysbios.hal.MemProtect ======== */ /* * ======== module ti.sysbios.hal.Power ======== */ typedef struct ti_sysbios_hal_Power_Fxns__ ti_sysbios_hal_Power_Fxns__; typedef const struct ti_sysbios_hal_Power_Fxns__* ti_sysbios_hal_Power_Module; /* * ======== module ti.sysbios.hal.PowerNull ======== */ typedef struct ti_sysbios_hal_PowerNull_Fxns__ ti_sysbios_hal_PowerNull_Fxns__; typedef const struct ti_sysbios_hal_PowerNull_Fxns__* ti_sysbios_hal_PowerNull_Module; /* * ======== module ti.sysbios.hal.Seconds ======== */ typedef struct ti_sysbios_hal_Seconds_Fxns__ ti_sysbios_hal_Seconds_Fxns__; typedef const struct ti_sysbios_hal_Seconds_Fxns__* ti_sysbios_hal_Seconds_Module; /* * ======== module ti.sysbios.hal.SecondsCallback ======== */ typedef struct ti_sysbios_hal_SecondsCallback_Fxns__ ti_sysbios_hal_SecondsCallback_Fxns__; typedef const struct ti_sysbios_hal_SecondsCallback_Fxns__* ti_sysbios_hal_SecondsCallback_Module; /* * ======== module ti.sysbios.hal.SecondsClock ======== */ typedef struct ti_sysbios_hal_SecondsClock_Module_State ti_sysbios_hal_SecondsClock_Module_State; typedef struct ti_sysbios_hal_SecondsClock_Fxns__ ti_sysbios_hal_SecondsClock_Fxns__; typedef const struct ti_sysbios_hal_SecondsClock_Fxns__* ti_sysbios_hal_SecondsClock_Module; /* * ======== module ti.sysbios.hal.SysCall ======== */ typedef struct ti_sysbios_hal_SysCall_Fxns__ ti_sysbios_hal_SysCall_Fxns__; typedef const struct ti_sysbios_hal_SysCall_Fxns__* ti_sysbios_hal_SysCall_Module; /* * ======== module ti.sysbios.hal.SysCallNull ======== */ typedef struct ti_sysbios_hal_SysCallNull_Fxns__ ti_sysbios_hal_SysCallNull_Fxns__; typedef const struct ti_sysbios_hal_SysCallNull_Fxns__* ti_sysbios_hal_SysCallNull_Module; /* * ======== module ti.sysbios.hal.Timer ======== */ typedef struct ti_sysbios_hal_Timer_Fxns__ ti_sysbios_hal_Timer_Fxns__; typedef const struct ti_sysbios_hal_Timer_Fxns__* ti_sysbios_hal_Timer_Module; typedef struct ti_sysbios_hal_Timer_Params ti_sysbios_hal_Timer_Params; typedef struct ti_sysbios_hal_Timer_Object ti_sysbios_hal_Timer_Object; typedef struct ti_sysbios_hal_Timer_Struct ti_sysbios_hal_Timer_Struct; typedef ti_sysbios_hal_Timer_Object* ti_sysbios_hal_Timer_Handle; typedef struct ti_sysbios_hal_Timer_Object__ ti_sysbios_hal_Timer_Instance_State; typedef ti_sysbios_hal_Timer_Object* ti_sysbios_hal_Timer_Instance; /* * ======== module ti.sysbios.hal.TimerNull ======== */ typedef struct ti_sysbios_hal_TimerNull_Fxns__ ti_sysbios_hal_TimerNull_Fxns__; typedef const struct ti_sysbios_hal_TimerNull_Fxns__* ti_sysbios_hal_TimerNull_Module; typedef struct ti_sysbios_hal_TimerNull_Params ti_sysbios_hal_TimerNull_Params; typedef struct ti_sysbios_hal_TimerNull_Object ti_sysbios_hal_TimerNull_Object; typedef struct ti_sysbios_hal_TimerNull_Struct ti_sysbios_hal_TimerNull_Struct; typedef ti_sysbios_hal_TimerNull_Object* ti_sysbios_hal_TimerNull_Handle; typedef struct ti_sysbios_hal_TimerNull_Object__ ti_sysbios_hal_TimerNull_Instance_State; typedef ti_sysbios_hal_TimerNull_Object* ti_sysbios_hal_TimerNull_Instance; /* * ======== module ti.sysbios.hal.Cache_CacheProxy ======== */ typedef struct ti_sysbios_hal_Cache_CacheProxy_Fxns__ ti_sysbios_hal_Cache_CacheProxy_Fxns__; typedef const struct ti_sysbios_hal_Cache_CacheProxy_Fxns__* ti_sysbios_hal_Cache_CacheProxy_Module; /* * ======== module ti.sysbios.hal.Core_CoreProxy ======== */ typedef struct ti_sysbios_hal_Core_CoreProxy_Fxns__ ti_sysbios_hal_Core_CoreProxy_Fxns__; typedef const struct ti_sysbios_hal_Core_CoreProxy_Fxns__* ti_sysbios_hal_Core_CoreProxy_Module; /* * ======== module ti.sysbios.hal.Hwi_HwiProxy ======== */ typedef struct ti_sysbios_hal_Hwi_HwiProxy_Fxns__ ti_sysbios_hal_Hwi_HwiProxy_Fxns__; typedef const struct ti_sysbios_hal_Hwi_HwiProxy_Fxns__* ti_sysbios_hal_Hwi_HwiProxy_Module; typedef struct ti_sysbios_hal_Hwi_HwiProxy_Params ti_sysbios_hal_Hwi_HwiProxy_Params; typedef struct ti_sysbios_interfaces_IHwi___Object *ti_sysbios_hal_Hwi_HwiProxy_Handle; /* * ======== module ti.sysbios.hal.Power_PowerProxy ======== */ typedef struct ti_sysbios_hal_Power_PowerProxy_Fxns__ ti_sysbios_hal_Power_PowerProxy_Fxns__; typedef const struct ti_sysbios_hal_Power_PowerProxy_Fxns__* ti_sysbios_hal_Power_PowerProxy_Module; /* * ======== module ti.sysbios.hal.Seconds_SecondsProxy ======== */ typedef struct ti_sysbios_hal_Seconds_SecondsProxy_Fxns__ ti_sysbios_hal_Seconds_SecondsProxy_Fxns__; typedef const struct ti_sysbios_hal_Seconds_SecondsProxy_Fxns__* ti_sysbios_hal_Seconds_SecondsProxy_Module; /* * ======== module ti.sysbios.hal.SysCall_SysCallProxy ======== */ typedef struct ti_sysbios_hal_SysCall_SysCallProxy_Fxns__ ti_sysbios_hal_SysCall_SysCallProxy_Fxns__; typedef const struct ti_sysbios_hal_SysCall_SysCallProxy_Fxns__* ti_sysbios_hal_SysCall_SysCallProxy_Module; /* * ======== module ti.sysbios.hal.Timer_TimerProxy ======== */ typedef struct ti_sysbios_hal_Timer_TimerProxy_Fxns__ ti_sysbios_hal_Timer_TimerProxy_Fxns__; typedef const struct ti_sysbios_hal_Timer_TimerProxy_Fxns__* ti_sysbios_hal_Timer_TimerProxy_Module; typedef struct ti_sysbios_hal_Timer_TimerProxy_Params ti_sysbios_hal_Timer_TimerProxy_Params; typedef struct ti_sysbios_interfaces_ITimer___Object *ti_sysbios_hal_Timer_TimerProxy_Handle; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef void (*ti_sysbios_interfaces_IHwi_FuncPtr)(xdc_UArg arg1); /* Irp */ typedef xdc_UArg ti_sysbios_interfaces_IHwi_Irp; /* HookSet */ struct ti_sysbios_interfaces_IHwi_HookSet { void (*registerFxn)(xdc_Int arg1); void (*createFxn)(ti_sysbios_interfaces_IHwi_Handle arg1, xdc_runtime_Error_Block* arg2); void (*beginFxn)(ti_sysbios_interfaces_IHwi_Handle arg1); void (*endFxn)(ti_sysbios_interfaces_IHwi_Handle arg1); void (*deleteFxn)(ti_sysbios_interfaces_IHwi_Handle arg1); }; /* MaskingOption */ enum ti_sysbios_interfaces_IHwi_MaskingOption { ti_sysbios_interfaces_IHwi_MaskingOption_NONE, ti_sysbios_interfaces_IHwi_MaskingOption_ALL, ti_sysbios_interfaces_IHwi_MaskingOption_SELF, ti_sysbios_interfaces_IHwi_MaskingOption_BITMASK, ti_sysbios_interfaces_IHwi_MaskingOption_LOWER }; typedef enum ti_sysbios_interfaces_IHwi_MaskingOption ti_sysbios_interfaces_IHwi_MaskingOption; /* StackInfo */ struct ti_sysbios_interfaces_IHwi_StackInfo { xdc_SizeT hwiStackPeak; xdc_SizeT hwiStackSize; xdc_Ptr hwiStackBase; }; /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_interfaces_IHwi_Args__create { xdc_Int intNum; ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn; } ti_sysbios_interfaces_IHwi_Args__create; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_interfaces_IHwi_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_interfaces_IHwi_MaskingOption maskSetting; xdc_UArg arg; xdc_Bool enableInt; xdc_Int eventId; xdc_Int priority; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_interfaces_IHwi_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*getStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth); xdc_Bool (*getCoreStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId); void (*startup)(void); xdc_UInt (*disable)(void); xdc_UInt (*enable)(void); void (*restore)(xdc_UInt key); void (*switchFromBootStack)(void); void (*post)(xdc_UInt intNum); xdc_Char *(*getTaskSP)(void); xdc_UInt (*disableInterrupt)(xdc_UInt intNum); xdc_UInt (*enableInterrupt)(xdc_UInt intNum); void (*restoreInterrupt)(xdc_UInt intNum, xdc_UInt key); void (*clearInterrupt)(xdc_UInt intNum); ti_sysbios_interfaces_IHwi_FuncPtr (*getFunc)(void* inst, xdc_UArg* arg); void (*setFunc)(void* inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg); xdc_Ptr (*getHookContext)(void* inst, xdc_Int id); void (*setHookContext)(void* inst, xdc_Int id, xdc_Ptr hookContext); ti_sysbios_interfaces_IHwi_Irp (*getIrp)(void* inst); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Interface__BASE__C */ extern const xdc_runtime_Types_Base ti_sysbios_interfaces_IHwi_Interface__BASE__C; /* * ======== FUNCTION STUBS ======== */ /* create */ extern ti_sysbios_interfaces_IHwi_Handle ti_sysbios_interfaces_IHwi_create(ti_sysbios_interfaces_IHwi_Module mod, xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_interfaces_IHwi_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_interfaces_IHwi_delete(ti_sysbios_interfaces_IHwi_Handle *inst); /* Handle_to_Module */ static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_interfaces_IHwi_Handle_to_Module(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_interfaces_IHwi_Handle_to_Module(ti_sysbios_interfaces_IHwi_Handle inst) { return inst->__fxns; } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_interfaces_IHwi_Handle_label(ti_sysbios_interfaces_IHwi_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_interfaces_IHwi_Handle_label(ti_sysbios_interfaces_IHwi_Handle inst, xdc_runtime_Types_Label *lab) { return inst->__fxns->__sysp->__label(inst, lab); } /* Module_id */ static inline xdc_runtime_Types_ModuleId ti_sysbios_interfaces_IHwi_Module_id(ti_sysbios_interfaces_IHwi_Module mod); static inline xdc_runtime_Types_ModuleId ti_sysbios_interfaces_IHwi_Module_id(ti_sysbios_interfaces_IHwi_Module mod) { return mod->__sysp->__mid; } /* getStackInfo */ static inline xdc_Bool ti_sysbios_interfaces_IHwi_getStackInfo(ti_sysbios_interfaces_IHwi_Module mod, ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth); static inline xdc_Bool ti_sysbios_interfaces_IHwi_getStackInfo( ti_sysbios_interfaces_IHwi_Module mod, ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth ) { return mod->getStackInfo(stkInfo, computeStackDepth); } /* getCoreStackInfo */ static inline xdc_Bool ti_sysbios_interfaces_IHwi_getCoreStackInfo(ti_sysbios_interfaces_IHwi_Module mod, ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId); static inline xdc_Bool ti_sysbios_interfaces_IHwi_getCoreStackInfo( ti_sysbios_interfaces_IHwi_Module mod, ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId ) { return mod->getCoreStackInfo(stkInfo, computeStackDepth, coreId); } /* startup */ static inline void ti_sysbios_interfaces_IHwi_startup(ti_sysbios_interfaces_IHwi_Module mod); static inline void ti_sysbios_interfaces_IHwi_startup( ti_sysbios_interfaces_IHwi_Module mod ) { mod->startup(); } /* disable */ static inline xdc_UInt ti_sysbios_interfaces_IHwi_disable(ti_sysbios_interfaces_IHwi_Module mod); static inline xdc_UInt ti_sysbios_interfaces_IHwi_disable( ti_sysbios_interfaces_IHwi_Module mod ) { return mod->disable(); } /* enable */ static inline xdc_UInt ti_sysbios_interfaces_IHwi_enable(ti_sysbios_interfaces_IHwi_Module mod); static inline xdc_UInt ti_sysbios_interfaces_IHwi_enable( ti_sysbios_interfaces_IHwi_Module mod ) { return mod->enable(); } /* restore */ static inline void ti_sysbios_interfaces_IHwi_restore(ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt key); static inline void ti_sysbios_interfaces_IHwi_restore( ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt key ) { mod->restore(key); } /* switchFromBootStack */ static inline void ti_sysbios_interfaces_IHwi_switchFromBootStack(ti_sysbios_interfaces_IHwi_Module mod); static inline void ti_sysbios_interfaces_IHwi_switchFromBootStack( ti_sysbios_interfaces_IHwi_Module mod ) { mod->switchFromBootStack(); } /* post */ static inline void ti_sysbios_interfaces_IHwi_post(ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum); static inline void ti_sysbios_interfaces_IHwi_post( ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum ) { mod->post(intNum); } /* getTaskSP */ static inline xdc_Char *ti_sysbios_interfaces_IHwi_getTaskSP(ti_sysbios_interfaces_IHwi_Module mod); static inline xdc_Char *ti_sysbios_interfaces_IHwi_getTaskSP( ti_sysbios_interfaces_IHwi_Module mod ) { return mod->getTaskSP(); } /* disableInterrupt */ static inline xdc_UInt ti_sysbios_interfaces_IHwi_disableInterrupt(ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum); static inline xdc_UInt ti_sysbios_interfaces_IHwi_disableInterrupt( ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum ) { return mod->disableInterrupt(intNum); } /* enableInterrupt */ static inline xdc_UInt ti_sysbios_interfaces_IHwi_enableInterrupt(ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum); static inline xdc_UInt ti_sysbios_interfaces_IHwi_enableInterrupt( ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum ) { return mod->enableInterrupt(intNum); } /* restoreInterrupt */ static inline void ti_sysbios_interfaces_IHwi_restoreInterrupt(ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum, xdc_UInt key); static inline void ti_sysbios_interfaces_IHwi_restoreInterrupt( ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum, xdc_UInt key ) { mod->restoreInterrupt(intNum, key); } /* clearInterrupt */ static inline void ti_sysbios_interfaces_IHwi_clearInterrupt(ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum); static inline void ti_sysbios_interfaces_IHwi_clearInterrupt( ti_sysbios_interfaces_IHwi_Module mod, xdc_UInt intNum ) { mod->clearInterrupt(intNum); } /* getFunc */ static inline ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_interfaces_IHwi_getFunc(ti_sysbios_interfaces_IHwi_Handle inst, xdc_UArg *arg); static inline ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_interfaces_IHwi_getFunc( ti_sysbios_interfaces_IHwi_Handle inst, xdc_UArg *arg ) { return inst->__fxns->getFunc((void*)inst, arg); } /* setFunc */ static inline void ti_sysbios_interfaces_IHwi_setFunc(ti_sysbios_interfaces_IHwi_Handle inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg); static inline void ti_sysbios_interfaces_IHwi_setFunc( ti_sysbios_interfaces_IHwi_Handle inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg ) { inst->__fxns->setFunc((void*)inst, fxn, arg); } /* getHookContext */ static inline xdc_Ptr ti_sysbios_interfaces_IHwi_getHookContext(ti_sysbios_interfaces_IHwi_Handle inst, xdc_Int id); static inline xdc_Ptr ti_sysbios_interfaces_IHwi_getHookContext( ti_sysbios_interfaces_IHwi_Handle inst, xdc_Int id ) { return inst->__fxns->getHookContext((void*)inst, id); } /* setHookContext */ static inline void ti_sysbios_interfaces_IHwi_setHookContext(ti_sysbios_interfaces_IHwi_Handle inst, xdc_Int id, xdc_Ptr hookContext); static inline void ti_sysbios_interfaces_IHwi_setHookContext( ti_sysbios_interfaces_IHwi_Handle inst, xdc_Int id, xdc_Ptr hookContext ) { inst->__fxns->setHookContext((void*)inst, id, hookContext); } /* getIrp */ static inline ti_sysbios_interfaces_IHwi_Irp ti_sysbios_interfaces_IHwi_getIrp(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_Irp ti_sysbios_interfaces_IHwi_getIrp( ti_sysbios_interfaces_IHwi_Handle inst ) { return inst->__fxns->getIrp((void*)inst); } /* * ======== FUNCTION SELECTORS ======== */ /* These functions return function pointers for module and instance functions. * The functions accept modules and instances declared as types defined in this * interface, but they return functions defined for the actual objects passed * as parameters. These functions are not invoked by any generated code or * XDCtools internal code. */ /* getStackInfo_{FxnT,fxnP} */ typedef xdc_Bool (*ti_sysbios_interfaces_IHwi_getStackInfo_FxnT)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth); static inline ti_sysbios_interfaces_IHwi_getStackInfo_FxnT ti_sysbios_interfaces_IHwi_getStackInfo_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_getStackInfo_FxnT ti_sysbios_interfaces_IHwi_getStackInfo_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_getStackInfo_FxnT)mod->getStackInfo; } /* getCoreStackInfo_{FxnT,fxnP} */ typedef xdc_Bool (*ti_sysbios_interfaces_IHwi_getCoreStackInfo_FxnT)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId); static inline ti_sysbios_interfaces_IHwi_getCoreStackInfo_FxnT ti_sysbios_interfaces_IHwi_getCoreStackInfo_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_getCoreStackInfo_FxnT ti_sysbios_interfaces_IHwi_getCoreStackInfo_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_getCoreStackInfo_FxnT)mod->getCoreStackInfo; } /* startup_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_startup_FxnT)(void); static inline ti_sysbios_interfaces_IHwi_startup_FxnT ti_sysbios_interfaces_IHwi_startup_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_startup_FxnT ti_sysbios_interfaces_IHwi_startup_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_startup_FxnT)mod->startup; } /* disable_{FxnT,fxnP} */ typedef xdc_UInt (*ti_sysbios_interfaces_IHwi_disable_FxnT)(void); static inline ti_sysbios_interfaces_IHwi_disable_FxnT ti_sysbios_interfaces_IHwi_disable_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_disable_FxnT ti_sysbios_interfaces_IHwi_disable_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_disable_FxnT)mod->disable; } /* enable_{FxnT,fxnP} */ typedef xdc_UInt (*ti_sysbios_interfaces_IHwi_enable_FxnT)(void); static inline ti_sysbios_interfaces_IHwi_enable_FxnT ti_sysbios_interfaces_IHwi_enable_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_enable_FxnT ti_sysbios_interfaces_IHwi_enable_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_enable_FxnT)mod->enable; } /* restore_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_restore_FxnT)(xdc_UInt key); static inline ti_sysbios_interfaces_IHwi_restore_FxnT ti_sysbios_interfaces_IHwi_restore_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_restore_FxnT ti_sysbios_interfaces_IHwi_restore_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_restore_FxnT)mod->restore; } /* switchFromBootStack_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_switchFromBootStack_FxnT)(void); static inline ti_sysbios_interfaces_IHwi_switchFromBootStack_FxnT ti_sysbios_interfaces_IHwi_switchFromBootStack_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_switchFromBootStack_FxnT ti_sysbios_interfaces_IHwi_switchFromBootStack_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_switchFromBootStack_FxnT)mod->switchFromBootStack; } /* post_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_post_FxnT)(xdc_UInt intNum); static inline ti_sysbios_interfaces_IHwi_post_FxnT ti_sysbios_interfaces_IHwi_post_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_post_FxnT ti_sysbios_interfaces_IHwi_post_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_post_FxnT)mod->post; } /* getTaskSP_{FxnT,fxnP} */ typedef xdc_Char *(*ti_sysbios_interfaces_IHwi_getTaskSP_FxnT)(void); static inline ti_sysbios_interfaces_IHwi_getTaskSP_FxnT ti_sysbios_interfaces_IHwi_getTaskSP_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_getTaskSP_FxnT ti_sysbios_interfaces_IHwi_getTaskSP_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_getTaskSP_FxnT)mod->getTaskSP; } /* disableInterrupt_{FxnT,fxnP} */ typedef xdc_UInt (*ti_sysbios_interfaces_IHwi_disableInterrupt_FxnT)(xdc_UInt intNum); static inline ti_sysbios_interfaces_IHwi_disableInterrupt_FxnT ti_sysbios_interfaces_IHwi_disableInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_disableInterrupt_FxnT ti_sysbios_interfaces_IHwi_disableInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_disableInterrupt_FxnT)mod->disableInterrupt; } /* enableInterrupt_{FxnT,fxnP} */ typedef xdc_UInt (*ti_sysbios_interfaces_IHwi_enableInterrupt_FxnT)(xdc_UInt intNum); static inline ti_sysbios_interfaces_IHwi_enableInterrupt_FxnT ti_sysbios_interfaces_IHwi_enableInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_enableInterrupt_FxnT ti_sysbios_interfaces_IHwi_enableInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_enableInterrupt_FxnT)mod->enableInterrupt; } /* restoreInterrupt_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_restoreInterrupt_FxnT)(xdc_UInt intNum, xdc_UInt key); static inline ti_sysbios_interfaces_IHwi_restoreInterrupt_FxnT ti_sysbios_interfaces_IHwi_restoreInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_restoreInterrupt_FxnT ti_sysbios_interfaces_IHwi_restoreInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_restoreInterrupt_FxnT)mod->restoreInterrupt; } /* clearInterrupt_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_clearInterrupt_FxnT)(xdc_UInt intNum); static inline ti_sysbios_interfaces_IHwi_clearInterrupt_FxnT ti_sysbios_interfaces_IHwi_clearInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod); static inline ti_sysbios_interfaces_IHwi_clearInterrupt_FxnT ti_sysbios_interfaces_IHwi_clearInterrupt_fxnP(ti_sysbios_interfaces_IHwi_Module mod) { return (ti_sysbios_interfaces_IHwi_clearInterrupt_FxnT)mod->clearInterrupt; } /* getFunc_{FxnT,fxnP} */ typedef ti_sysbios_interfaces_IHwi_FuncPtr (*ti_sysbios_interfaces_IHwi_getFunc_FxnT)(void *inst, xdc_UArg* arg); static inline ti_sysbios_interfaces_IHwi_getFunc_FxnT ti_sysbios_interfaces_IHwi_getFunc_fxnP(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_getFunc_FxnT ti_sysbios_interfaces_IHwi_getFunc_fxnP(ti_sysbios_interfaces_IHwi_Handle inst) { return (ti_sysbios_interfaces_IHwi_getFunc_FxnT)inst->__fxns->getFunc; } /* setFunc_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_setFunc_FxnT)(void *inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg); static inline ti_sysbios_interfaces_IHwi_setFunc_FxnT ti_sysbios_interfaces_IHwi_setFunc_fxnP(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_setFunc_FxnT ti_sysbios_interfaces_IHwi_setFunc_fxnP(ti_sysbios_interfaces_IHwi_Handle inst) { return (ti_sysbios_interfaces_IHwi_setFunc_FxnT)inst->__fxns->setFunc; } /* getHookContext_{FxnT,fxnP} */ typedef xdc_Ptr (*ti_sysbios_interfaces_IHwi_getHookContext_FxnT)(void *inst, xdc_Int id); static inline ti_sysbios_interfaces_IHwi_getHookContext_FxnT ti_sysbios_interfaces_IHwi_getHookContext_fxnP(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_getHookContext_FxnT ti_sysbios_interfaces_IHwi_getHookContext_fxnP(ti_sysbios_interfaces_IHwi_Handle inst) { return (ti_sysbios_interfaces_IHwi_getHookContext_FxnT)inst->__fxns->getHookContext; } /* setHookContext_{FxnT,fxnP} */ typedef void (*ti_sysbios_interfaces_IHwi_setHookContext_FxnT)(void *inst, xdc_Int id, xdc_Ptr hookContext); static inline ti_sysbios_interfaces_IHwi_setHookContext_FxnT ti_sysbios_interfaces_IHwi_setHookContext_fxnP(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_setHookContext_FxnT ti_sysbios_interfaces_IHwi_setHookContext_fxnP(ti_sysbios_interfaces_IHwi_Handle inst) { return (ti_sysbios_interfaces_IHwi_setHookContext_FxnT)inst->__fxns->setHookContext; } /* getIrp_{FxnT,fxnP} */ typedef ti_sysbios_interfaces_IHwi_Irp (*ti_sysbios_interfaces_IHwi_getIrp_FxnT)(void *inst); static inline ti_sysbios_interfaces_IHwi_getIrp_FxnT ti_sysbios_interfaces_IHwi_getIrp_fxnP(ti_sysbios_interfaces_IHwi_Handle inst); static inline ti_sysbios_interfaces_IHwi_getIrp_FxnT ti_sysbios_interfaces_IHwi_getIrp_fxnP(ti_sysbios_interfaces_IHwi_Handle inst) { return (ti_sysbios_interfaces_IHwi_getIrp_FxnT)inst->__fxns->getIrp; } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_hal_Hwi_HwiProxy_FuncPtr; /* Irp */ typedef ti_sysbios_interfaces_IHwi_Irp ti_sysbios_hal_Hwi_HwiProxy_Irp; /* HookSet */ typedef ti_sysbios_interfaces_IHwi_HookSet ti_sysbios_hal_Hwi_HwiProxy_HookSet; /* MaskingOption */ typedef ti_sysbios_interfaces_IHwi_MaskingOption ti_sysbios_hal_Hwi_HwiProxy_MaskingOption; /* StackInfo */ typedef ti_sysbios_interfaces_IHwi_StackInfo ti_sysbios_hal_Hwi_HwiProxy_StackInfo; /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_hal_Hwi_HwiProxy_Args__create { xdc_Int intNum; ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn; } ti_sysbios_hal_Hwi_HwiProxy_Args__create; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__diagsEnabled; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__diagsEnabled ti_sysbios_hal_Hwi_HwiProxy_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__diagsIncluded; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__diagsIncluded ti_sysbios_hal_Hwi_HwiProxy_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_hal_Hwi_HwiProxy_Module__diagsMask; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__diagsMask ti_sysbios_hal_Hwi_HwiProxy_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_HwiProxy_Module__gateObj; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__gateObj ti_sysbios_hal_Hwi_HwiProxy_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_HwiProxy_Module__gatePrms; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__gatePrms ti_sysbios_hal_Hwi_HwiProxy_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_hal_Hwi_HwiProxy_Module__id; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__id ti_sysbios_hal_Hwi_HwiProxy_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerDefined; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerDefined ti_sysbios_hal_Hwi_HwiProxy_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerObj; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerObj ti_sysbios_hal_Hwi_HwiProxy_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn0; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn0 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn1; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn1 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn2; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn2 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn4; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn4 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn8; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn8 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_hal_Hwi_HwiProxy_Object__count; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Object__count ti_sysbios_hal_Hwi_HwiProxy_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_hal_Hwi_HwiProxy_Object__heap; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Object__heap ti_sysbios_hal_Hwi_HwiProxy_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_hal_Hwi_HwiProxy_Object__sizeof; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Object__sizeof ti_sysbios_hal_Hwi_HwiProxy_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_HwiProxy_Object__table; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_Object__table ti_sysbios_hal_Hwi_HwiProxy_Object__table__C; /* dispatcherAutoNestingSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherAutoNestingSupport; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherAutoNestingSupport ti_sysbios_hal_Hwi_HwiProxy_dispatcherAutoNestingSupport__C; /* dispatcherSwiSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherSwiSupport; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherSwiSupport ti_sysbios_hal_Hwi_HwiProxy_dispatcherSwiSupport__C; /* dispatcherTaskSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherTaskSupport; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherTaskSupport ti_sysbios_hal_Hwi_HwiProxy_dispatcherTaskSupport__C; /* dispatcherIrpTrackingSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherIrpTrackingSupport; extern const CT__ti_sysbios_hal_Hwi_HwiProxy_dispatcherIrpTrackingSupport ti_sysbios_hal_Hwi_HwiProxy_dispatcherIrpTrackingSupport__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_hal_Hwi_HwiProxy_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_interfaces_IHwi_MaskingOption maskSetting; xdc_UArg arg; xdc_Bool enableInt; xdc_Int eventId; xdc_Int priority; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_hal_Hwi_HwiProxy_Struct { const ti_sysbios_hal_Hwi_HwiProxy_Fxns__ *__fxns; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_hal_Hwi_HwiProxy_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*getStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth); xdc_Bool (*getCoreStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId); void (*startup)(void); xdc_UInt (*disable)(void); xdc_UInt (*enable)(void); void (*restore)(xdc_UInt key); void (*switchFromBootStack)(void); void (*post)(xdc_UInt intNum); xdc_Char *(*getTaskSP)(void); xdc_UInt (*disableInterrupt)(xdc_UInt intNum); xdc_UInt (*enableInterrupt)(xdc_UInt intNum); void (*restoreInterrupt)(xdc_UInt intNum, xdc_UInt key); void (*clearInterrupt)(xdc_UInt intNum); ti_sysbios_interfaces_IHwi_FuncPtr (*getFunc)(ti_sysbios_hal_Hwi_HwiProxy_Handle inst, xdc_UArg* arg); void (*setFunc)(ti_sysbios_hal_Hwi_HwiProxy_Handle inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg); xdc_Ptr (*getHookContext)(ti_sysbios_hal_Hwi_HwiProxy_Handle inst, xdc_Int id); void (*setHookContext)(ti_sysbios_hal_Hwi_HwiProxy_Handle inst, xdc_Int id, xdc_Ptr hookContext); ti_sysbios_interfaces_IHwi_Irp (*getIrp)(ti_sysbios_hal_Hwi_HwiProxy_Handle inst); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_hal_Hwi_HwiProxy_Fxns__ ti_sysbios_hal_Hwi_HwiProxy_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* create */ extern ti_sysbios_hal_Hwi_HwiProxy_Handle ti_sysbios_hal_Hwi_HwiProxy_create( xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_HwiProxy_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_hal_Hwi_HwiProxy_delete(ti_sysbios_hal_Hwi_HwiProxy_Handle *instp); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_hal_Hwi_HwiProxy_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_Module__startupDone__S( void ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_hal_Hwi_HwiProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* Proxy__abstract__S */ extern xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_Proxy__abstract__S( void ); /* Proxy__delegate__S */ extern xdc_CPtr ti_sysbios_hal_Hwi_HwiProxy_Proxy__delegate__S( void ); /* getStackInfo__E */ extern xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_getStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth ); /* getCoreStackInfo__E */ extern xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_getCoreStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId ); /* startup__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_startup__E( void ); /* disable__E */ extern xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_disable__E( void ); /* enable__E */ extern xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_enable__E( void ); /* restore__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_restore__E( xdc_UInt key ); /* switchFromBootStack__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_switchFromBootStack__E( void ); /* post__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_post__E( xdc_UInt intNum ); /* getTaskSP__E */ extern xdc_Char *ti_sysbios_hal_Hwi_HwiProxy_getTaskSP__E( void ); /* disableInterrupt__E */ extern xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_disableInterrupt__E( xdc_UInt intNum ); /* enableInterrupt__E */ extern xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_enableInterrupt__E( xdc_UInt intNum ); /* restoreInterrupt__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_restoreInterrupt__E( xdc_UInt intNum, xdc_UInt key ); /* clearInterrupt__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_clearInterrupt__E( xdc_UInt intNum ); /* getFunc__E */ extern ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_hal_Hwi_HwiProxy_getFunc__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, xdc_UArg *arg ); /* setFunc__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_setFunc__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg ); /* getHookContext__E */ extern xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_getHookContext__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, xdc_Int id ); /* setHookContext__E */ extern void ti_sysbios_hal_Hwi_HwiProxy_setHookContext__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, xdc_Int id, xdc_Ptr hookContext ); /* getIrp__E */ extern ti_sysbios_interfaces_IHwi_Irp ti_sysbios_hal_Hwi_HwiProxy_getIrp__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_hal_Hwi_HwiProxy_Module_upCast(void); static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_hal_Hwi_HwiProxy_Module_upCast(void) { return (ti_sysbios_interfaces_IHwi_Module)ti_sysbios_hal_Hwi_HwiProxy_Proxy__delegate__S(); } /* Module_to_ti_sysbios_interfaces_IHwi */ /* Handle_upCast */ static inline ti_sysbios_interfaces_IHwi_Handle ti_sysbios_hal_Hwi_HwiProxy_Handle_upCast(ti_sysbios_hal_Hwi_HwiProxy_Handle i); static inline ti_sysbios_interfaces_IHwi_Handle ti_sysbios_hal_Hwi_HwiProxy_Handle_upCast(ti_sysbios_hal_Hwi_HwiProxy_Handle i) { return (ti_sysbios_interfaces_IHwi_Handle)i; } /* Handle_to_ti_sysbios_interfaces_IHwi */ /* Handle_downCast */ static inline ti_sysbios_hal_Hwi_HwiProxy_Handle ti_sysbios_hal_Hwi_HwiProxy_Handle_downCast(ti_sysbios_interfaces_IHwi_Handle i); static inline ti_sysbios_hal_Hwi_HwiProxy_Handle ti_sysbios_hal_Hwi_HwiProxy_Handle_downCast(ti_sysbios_interfaces_IHwi_Handle i) { ti_sysbios_interfaces_IHwi_Handle i2 = (ti_sysbios_interfaces_IHwi_Handle)i; if (ti_sysbios_hal_Hwi_HwiProxy_Proxy__abstract__S()) { return (ti_sysbios_hal_Hwi_HwiProxy_Handle)i; } return ((const void*)i2->__fxns == (const void*)ti_sysbios_hal_Hwi_HwiProxy_Proxy__delegate__S()) ? (ti_sysbios_hal_Hwi_HwiProxy_Handle)i : (ti_sysbios_hal_Hwi_HwiProxy_Handle)0; } /* Handle_from_ti_sysbios_interfaces_IHwi */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_hal_Hwi_HwiProxy_Module__id ti_sysbios_hal_Hwi_HwiProxy_Module_id(void); static inline CT__ti_sysbios_hal_Hwi_HwiProxy_Module__id ti_sysbios_hal_Hwi_HwiProxy_Module_id( void ) { return ti_sysbios_hal_Hwi_HwiProxy_Module__id__C; } /* Proxy_abstract */ /* Proxy_delegate */ /* Params_init */ static inline void ti_sysbios_hal_Hwi_HwiProxy_Params_init(ti_sysbios_hal_Hwi_HwiProxy_Params *prms); static inline void ti_sysbios_hal_Hwi_HwiProxy_Params_init( ti_sysbios_hal_Hwi_HwiProxy_Params *prms ) { if (prms != 0) { ti_sysbios_hal_Hwi_HwiProxy_Params__init__S(prms, 0, sizeof(ti_sysbios_hal_Hwi_HwiProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_hal_Hwi_HwiProxy_Params_copy(ti_sysbios_hal_Hwi_HwiProxy_Params *dst, const ti_sysbios_hal_Hwi_HwiProxy_Params *src); static inline void ti_sysbios_hal_Hwi_HwiProxy_Params_copy(ti_sysbios_hal_Hwi_HwiProxy_Params *dst, const ti_sysbios_hal_Hwi_HwiProxy_Params *src) { if (dst != 0) { ti_sysbios_hal_Hwi_HwiProxy_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_hal_Hwi_HwiProxy_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* * ======== EPILOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_hal_Hwi_FuncPtr; /* Irp */ typedef ti_sysbios_interfaces_IHwi_Irp ti_sysbios_hal_Hwi_Irp; /* HookSet */ typedef ti_sysbios_interfaces_IHwi_HookSet ti_sysbios_hal_Hwi_HookSet; /* MaskingOption */ typedef ti_sysbios_interfaces_IHwi_MaskingOption ti_sysbios_hal_Hwi_MaskingOption; /* StackInfo */ typedef ti_sysbios_interfaces_IHwi_StackInfo ti_sysbios_hal_Hwi_StackInfo; /* MaskingOption_NONE */ /* MaskingOption_ALL */ /* MaskingOption_SELF */ /* MaskingOption_BITMASK */ /* MaskingOption_LOWER */ /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_hal_Hwi_Args__create { xdc_Int intNum; ti_sysbios_hal_Hwi_FuncPtr hwiFxn; } ti_sysbios_hal_Hwi_Args__create; /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_hal_Hwi_Module__diagsEnabled; extern const CT__ti_sysbios_hal_Hwi_Module__diagsEnabled ti_sysbios_hal_Hwi_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_hal_Hwi_Module__diagsIncluded; extern const CT__ti_sysbios_hal_Hwi_Module__diagsIncluded ti_sysbios_hal_Hwi_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_hal_Hwi_Module__diagsMask; extern const CT__ti_sysbios_hal_Hwi_Module__diagsMask ti_sysbios_hal_Hwi_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_Module__gateObj; extern const CT__ti_sysbios_hal_Hwi_Module__gateObj ti_sysbios_hal_Hwi_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_Module__gatePrms; extern const CT__ti_sysbios_hal_Hwi_Module__gatePrms ti_sysbios_hal_Hwi_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_hal_Hwi_Module__id; extern const CT__ti_sysbios_hal_Hwi_Module__id ti_sysbios_hal_Hwi_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_Module__loggerDefined; extern const CT__ti_sysbios_hal_Hwi_Module__loggerDefined ti_sysbios_hal_Hwi_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_Module__loggerObj; extern const CT__ti_sysbios_hal_Hwi_Module__loggerObj ti_sysbios_hal_Hwi_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_hal_Hwi_Module__loggerFxn0; extern const CT__ti_sysbios_hal_Hwi_Module__loggerFxn0 ti_sysbios_hal_Hwi_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_hal_Hwi_Module__loggerFxn1; extern const CT__ti_sysbios_hal_Hwi_Module__loggerFxn1 ti_sysbios_hal_Hwi_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_hal_Hwi_Module__loggerFxn2; extern const CT__ti_sysbios_hal_Hwi_Module__loggerFxn2 ti_sysbios_hal_Hwi_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_hal_Hwi_Module__loggerFxn4; extern const CT__ti_sysbios_hal_Hwi_Module__loggerFxn4 ti_sysbios_hal_Hwi_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_hal_Hwi_Module__loggerFxn8; extern const CT__ti_sysbios_hal_Hwi_Module__loggerFxn8 ti_sysbios_hal_Hwi_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_hal_Hwi_Object__count; extern const CT__ti_sysbios_hal_Hwi_Object__count ti_sysbios_hal_Hwi_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_hal_Hwi_Object__heap; extern const CT__ti_sysbios_hal_Hwi_Object__heap ti_sysbios_hal_Hwi_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_hal_Hwi_Object__sizeof; extern const CT__ti_sysbios_hal_Hwi_Object__sizeof ti_sysbios_hal_Hwi_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_hal_Hwi_Object__table; extern const CT__ti_sysbios_hal_Hwi_Object__table ti_sysbios_hal_Hwi_Object__table__C; /* dispatcherAutoNestingSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport; extern const CT__ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport__C; /* dispatcherSwiSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_dispatcherSwiSupport; extern const CT__ti_sysbios_hal_Hwi_dispatcherSwiSupport ti_sysbios_hal_Hwi_dispatcherSwiSupport__C; /* dispatcherTaskSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_dispatcherTaskSupport; extern const CT__ti_sysbios_hal_Hwi_dispatcherTaskSupport ti_sysbios_hal_Hwi_dispatcherTaskSupport__C; /* dispatcherIrpTrackingSupport */ typedef xdc_Bool CT__ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport; extern const CT__ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport__C; /* E_stackOverflow */ typedef xdc_runtime_Error_Id CT__ti_sysbios_hal_Hwi_E_stackOverflow; extern const CT__ti_sysbios_hal_Hwi_E_stackOverflow ti_sysbios_hal_Hwi_E_stackOverflow__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_hal_Hwi_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_interfaces_IHwi_MaskingOption maskSetting; xdc_UArg arg; xdc_Bool enableInt; xdc_Int eventId; xdc_Int priority; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_hal_Hwi_Struct { const ti_sysbios_hal_Hwi_Fxns__ *__fxns; ti_sysbios_hal_Hwi_HwiProxy_Handle f0; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_hal_Hwi_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*getStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth); xdc_Bool (*getCoreStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId); void (*startup)(void); xdc_UInt (*disable)(void); xdc_UInt (*enable)(void); void (*restore)(xdc_UInt key); void (*switchFromBootStack)(void); void (*post)(xdc_UInt intNum); xdc_Char *(*getTaskSP)(void); xdc_UInt (*disableInterrupt)(xdc_UInt intNum); xdc_UInt (*enableInterrupt)(xdc_UInt intNum); void (*restoreInterrupt)(xdc_UInt intNum, xdc_UInt key); void (*clearInterrupt)(xdc_UInt intNum); ti_sysbios_interfaces_IHwi_FuncPtr (*getFunc)(ti_sysbios_hal_Hwi_Handle inst, xdc_UArg* arg); void (*setFunc)(ti_sysbios_hal_Hwi_Handle inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg); xdc_Ptr (*getHookContext)(ti_sysbios_hal_Hwi_Handle inst, xdc_Int id); void (*setHookContext)(ti_sysbios_hal_Hwi_Handle inst, xdc_Int id, xdc_Ptr hookContext); ti_sysbios_interfaces_IHwi_Irp (*getIrp)(ti_sysbios_hal_Hwi_Handle inst); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_hal_Hwi_Fxns__ ti_sysbios_hal_Hwi_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_hal_Hwi_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_hal_Hwi_Module_startup__F( xdc_Int state ); /* Instance_init__E */ extern xdc_Int ti_sysbios_hal_Hwi_Instance_init__E(ti_sysbios_hal_Hwi_Object *obj, xdc_Int intNum, ti_sysbios_hal_Hwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_Params *prms, xdc_runtime_Error_Block *eb); /* Instance_finalize__E */ extern void ti_sysbios_hal_Hwi_Instance_finalize__E(ti_sysbios_hal_Hwi_Object *obj, int ec); /* create */ extern ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_create( xdc_Int intNum, ti_sysbios_hal_Hwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_hal_Hwi_construct(ti_sysbios_hal_Hwi_Struct *obj, xdc_Int intNum, ti_sysbios_hal_Hwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_hal_Hwi_delete(ti_sysbios_hal_Hwi_Handle *instp); /* destruct */ extern void ti_sysbios_hal_Hwi_destruct(ti_sysbios_hal_Hwi_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_hal_Hwi_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_hal_Hwi_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_hal_Hwi_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_hal_Hwi_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_hal_Hwi_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* getStackInfo__E */ extern xdc_Bool ti_sysbios_hal_Hwi_getStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth ); /* getCoreStackInfo__E */ extern xdc_Bool ti_sysbios_hal_Hwi_getCoreStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId ); /* startup__E */ extern void ti_sysbios_hal_Hwi_startup__E( void ); /* switchFromBootStack__E */ extern void ti_sysbios_hal_Hwi_switchFromBootStack__E( void ); /* post__E */ extern void ti_sysbios_hal_Hwi_post__E( xdc_UInt intNum ); /* getTaskSP__E */ extern xdc_Char *ti_sysbios_hal_Hwi_getTaskSP__E( void ); /* disableInterrupt__E */ extern xdc_UInt ti_sysbios_hal_Hwi_disableInterrupt__E( xdc_UInt intNum ); /* enableInterrupt__E */ extern xdc_UInt ti_sysbios_hal_Hwi_enableInterrupt__E( xdc_UInt intNum ); /* restoreInterrupt__E */ extern void ti_sysbios_hal_Hwi_restoreInterrupt__E( xdc_UInt intNum, xdc_UInt key ); /* clearInterrupt__E */ extern void ti_sysbios_hal_Hwi_clearInterrupt__E( xdc_UInt intNum ); /* getFunc__E */ extern ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_hal_Hwi_getFunc__E( ti_sysbios_hal_Hwi_Handle __inst, xdc_UArg *arg ); /* setFunc__E */ extern void ti_sysbios_hal_Hwi_setFunc__E( ti_sysbios_hal_Hwi_Handle __inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg ); /* getIrp__E */ extern ti_sysbios_interfaces_IHwi_Irp ti_sysbios_hal_Hwi_getIrp__E( ti_sysbios_hal_Hwi_Handle __inst ); /* getHookContext__E */ extern xdc_Ptr ti_sysbios_hal_Hwi_getHookContext__E( ti_sysbios_hal_Hwi_Handle __inst, xdc_Int id ); /* setHookContext__E */ extern void ti_sysbios_hal_Hwi_setHookContext__E( ti_sysbios_hal_Hwi_Handle __inst, xdc_Int id, xdc_Ptr hookContext ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_hal_Hwi_Module_upCast(void); static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_hal_Hwi_Module_upCast(void) { return (ti_sysbios_interfaces_IHwi_Module)&ti_sysbios_hal_Hwi_Module__FXNS__C; } /* Module_to_ti_sysbios_interfaces_IHwi */ /* Handle_upCast */ static inline ti_sysbios_interfaces_IHwi_Handle ti_sysbios_hal_Hwi_Handle_upCast(ti_sysbios_hal_Hwi_Handle i); static inline ti_sysbios_interfaces_IHwi_Handle ti_sysbios_hal_Hwi_Handle_upCast(ti_sysbios_hal_Hwi_Handle i) { return (ti_sysbios_interfaces_IHwi_Handle)i; } /* Handle_to_ti_sysbios_interfaces_IHwi */ /* Handle_downCast */ static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Handle_downCast(ti_sysbios_interfaces_IHwi_Handle i); static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Handle_downCast(ti_sysbios_interfaces_IHwi_Handle i) { ti_sysbios_interfaces_IHwi_Handle i2 = (ti_sysbios_interfaces_IHwi_Handle)i; return ((const void*)i2->__fxns == (const void*)&ti_sysbios_hal_Hwi_Module__FXNS__C) ? (ti_sysbios_hal_Hwi_Handle)i : (ti_sysbios_hal_Hwi_Handle)0; } /* Handle_from_ti_sysbios_interfaces_IHwi */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_hal_Hwi_Module__id ti_sysbios_hal_Hwi_Module_id(void); static inline CT__ti_sysbios_hal_Hwi_Module__id ti_sysbios_hal_Hwi_Module_id( void ) { return ti_sysbios_hal_Hwi_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_hal_Hwi_Module_hasMask(void); static inline xdc_Bool ti_sysbios_hal_Hwi_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_hal_Hwi_Module__diagsMask__C != (CT__ti_sysbios_hal_Hwi_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_hal_Hwi_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_hal_Hwi_Module_getMask(void) { return (ti_sysbios_hal_Hwi_Module__diagsMask__C != (CT__ti_sysbios_hal_Hwi_Module__diagsMask)0) ? *ti_sysbios_hal_Hwi_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_hal_Hwi_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_hal_Hwi_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_hal_Hwi_Module__diagsMask__C != (CT__ti_sysbios_hal_Hwi_Module__diagsMask)0) { *ti_sysbios_hal_Hwi_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_hal_Hwi_Params_init(ti_sysbios_hal_Hwi_Params *prms); static inline void ti_sysbios_hal_Hwi_Params_init( ti_sysbios_hal_Hwi_Params *prms ) { if (prms != 0) { ti_sysbios_hal_Hwi_Params__init__S(prms, 0, sizeof(ti_sysbios_hal_Hwi_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_hal_Hwi_Params_copy(ti_sysbios_hal_Hwi_Params *dst, const ti_sysbios_hal_Hwi_Params *src); static inline void ti_sysbios_hal_Hwi_Params_copy(ti_sysbios_hal_Hwi_Params *dst, const ti_sysbios_hal_Hwi_Params *src) { if (dst != 0) { ti_sysbios_hal_Hwi_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_hal_Hwi_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Object_get(ti_sysbios_hal_Hwi_Instance_State *oarr, int i); static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Object_get(ti_sysbios_hal_Hwi_Instance_State *oarr, int i) { return (ti_sysbios_hal_Hwi_Handle)ti_sysbios_hal_Hwi_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Object_first(void); static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Object_first(void) { return (ti_sysbios_hal_Hwi_Handle)ti_sysbios_hal_Hwi_Object__first__S(); } /* Object_next */ static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Object_next(ti_sysbios_hal_Hwi_Object *obj); static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_Object_next(ti_sysbios_hal_Hwi_Object *obj) { return (ti_sysbios_hal_Hwi_Handle)ti_sysbios_hal_Hwi_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_hal_Hwi_Handle_label(ti_sysbios_hal_Hwi_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_hal_Hwi_Handle_label(ti_sysbios_hal_Hwi_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_hal_Hwi_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_hal_Hwi_Handle_name(ti_sysbios_hal_Hwi_Handle inst); static inline xdc_String ti_sysbios_hal_Hwi_Handle_name(ti_sysbios_hal_Hwi_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_hal_Hwi_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_handle(ti_sysbios_hal_Hwi_Struct *str); static inline ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_handle(ti_sysbios_hal_Hwi_Struct *str) { return (ti_sysbios_hal_Hwi_Handle)str; } /* struct */ static inline ti_sysbios_hal_Hwi_Struct *ti_sysbios_hal_Hwi_struct(ti_sysbios_hal_Hwi_Handle inst); static inline ti_sysbios_hal_Hwi_Struct *ti_sysbios_hal_Hwi_struct(ti_sysbios_hal_Hwi_Handle inst) { return (ti_sysbios_hal_Hwi_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2015-2018, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Use intrinsics for ALL C6x and ARM 32bit targets (excluding arm M3) */ /* * ======== Hwi_disable ======== */ /* * ======== Hwi_enable ======== */ /* * ======== Hwi_restore ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* IntHandlerFuncPtr */ typedef void (*ti_sysbios_family_arm_v7a_Pmu_IntHandlerFuncPtr)(xdc_UArg arg1); /* * ======== INTERNAL DEFINITIONS ======== */ /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsEnabled; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsEnabled ti_sysbios_family_arm_v7a_Pmu_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsIncluded; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsIncluded ti_sysbios_family_arm_v7a_Pmu_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7a_Pmu_Module__gateObj; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__gateObj ti_sysbios_family_arm_v7a_Pmu_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7a_Pmu_Module__gatePrms; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__gatePrms ti_sysbios_family_arm_v7a_Pmu_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_family_arm_v7a_Pmu_Module__id; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__id ti_sysbios_family_arm_v7a_Pmu_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerDefined; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerDefined ti_sysbios_family_arm_v7a_Pmu_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerObj; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerObj ti_sysbios_family_arm_v7a_Pmu_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn0; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn0 ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn1; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn1 ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn2; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn2 ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn4; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn4 ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn8; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn8 ti_sysbios_family_arm_v7a_Pmu_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_family_arm_v7a_Pmu_Object__count; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Object__count ti_sysbios_family_arm_v7a_Pmu_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_family_arm_v7a_Pmu_Object__heap; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Object__heap ti_sysbios_family_arm_v7a_Pmu_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_family_arm_v7a_Pmu_Object__sizeof; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Object__sizeof ti_sysbios_family_arm_v7a_Pmu_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7a_Pmu_Object__table; extern const CT__ti_sysbios_family_arm_v7a_Pmu_Object__table ti_sysbios_family_arm_v7a_Pmu_Object__table__C; /* intNum */ typedef xdc_UInt CT__ti_sysbios_family_arm_v7a_Pmu_intNum; extern const CT__ti_sysbios_family_arm_v7a_Pmu_intNum ti_sysbios_family_arm_v7a_Pmu_intNum__C; /* A_badIntNum */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_family_arm_v7a_Pmu_A_badIntNum; extern const CT__ti_sysbios_family_arm_v7a_Pmu_A_badIntNum ti_sysbios_family_arm_v7a_Pmu_A_badIntNum__C; /* A_invalidCounterId */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_family_arm_v7a_Pmu_A_invalidCounterId; extern const CT__ti_sysbios_family_arm_v7a_Pmu_A_invalidCounterId ti_sysbios_family_arm_v7a_Pmu_A_invalidCounterId__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_family_arm_v7a_Pmu_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_family_arm_v7a_Pmu_Module_startup__F( xdc_Int state ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_family_arm_v7a_Pmu_Module__startupDone__S( void ); /* setInterruptFunc__E */ extern void ti_sysbios_family_arm_v7a_Pmu_setInterruptFunc__E( ti_sysbios_family_arm_v7a_Pmu_IntHandlerFuncPtr interruptFunc ); /* startCounter__E */ extern void ti_sysbios_family_arm_v7a_Pmu_startCounter__E( xdc_UInt counterId ); /* stopCounter__E */ extern void ti_sysbios_family_arm_v7a_Pmu_stopCounter__E( xdc_UInt counterId ); /* resetCount__E */ extern void ti_sysbios_family_arm_v7a_Pmu_resetCount__E( xdc_UInt counterId ); /* setCount__E */ extern void ti_sysbios_family_arm_v7a_Pmu_setCount__E( xdc_UInt counterId, xdc_UInt32 counterVal ); /* configureCounter__E */ extern void ti_sysbios_family_arm_v7a_Pmu_configureCounter__E( xdc_UInt counterId, xdc_UInt eventNum, xdc_Bool interruptEnable ); /* enableInterrupt__E */ extern void ti_sysbios_family_arm_v7a_Pmu_enableInterrupt__E( xdc_UInt counterId ); /* disableInterrupt__E */ extern void ti_sysbios_family_arm_v7a_Pmu_disableInterrupt__E( xdc_UInt counterId ); /* clearOverflowStatus__E */ extern void ti_sysbios_family_arm_v7a_Pmu_clearOverflowStatus__E( xdc_UInt counterId ); /* getCount__E */ extern xdc_UInt32 ti_sysbios_family_arm_v7a_Pmu_getCount__E( xdc_UInt counterId ); /* getNumCounters__E */ extern xdc_UInt ti_sysbios_family_arm_v7a_Pmu_getNumCounters__E( void ); /* getOverflowStatus__E */ extern xdc_Bool ti_sysbios_family_arm_v7a_Pmu_getOverflowStatus__E( xdc_UInt counterId ); /* getEnabled__E */ extern xdc_UInt32 ti_sysbios_family_arm_v7a_Pmu_getEnabled__E( void ); /* startCounterI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_startCounterI__E( xdc_UInt counterId ); /* stopCounterI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_stopCounterI__E( xdc_UInt counterId ); /* resetCountI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_resetCountI__E( xdc_UInt counterId ); /* setCountI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_setCountI__E( xdc_UInt counterId, xdc_UInt32 counterVal ); /* enableInterruptI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_enableInterruptI__E( xdc_UInt counterId ); /* disableInterruptI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_disableInterruptI__E( xdc_UInt counterId ); /* clearOverflowStatusI__E */ extern void ti_sysbios_family_arm_v7a_Pmu_clearOverflowStatusI__E( xdc_UInt counterId ); /* getCountI__E */ extern xdc_UInt32 ti_sysbios_family_arm_v7a_Pmu_getCountI__E( xdc_UInt counterId ); /* getOverflowStatusI__E */ extern xdc_UInt32 ti_sysbios_family_arm_v7a_Pmu_getOverflowStatusI__E( xdc_UInt counterId ); /* configureCounterI__I */ extern void ti_sysbios_family_arm_v7a_Pmu_configureCounterI__I( xdc_UInt counterId, xdc_UInt eventNum ); /* clearOverflowStatusReg__I */ extern void ti_sysbios_family_arm_v7a_Pmu_clearOverflowStatusReg__I( xdc_UInt32 clearMask ); /* getOverflowStatusReg__I */ extern xdc_UInt32 ti_sysbios_family_arm_v7a_Pmu_getOverflowStatusReg__I( void ); /* initCounters__I */ extern void ti_sysbios_family_arm_v7a_Pmu_initCounters__I( xdc_UInt32 counterMask ); /* interruptHandler__I */ extern void ti_sysbios_family_arm_v7a_Pmu_interruptHandler__I( xdc_UArg arg ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_family_arm_v7a_Pmu_Module__id ti_sysbios_family_arm_v7a_Pmu_Module_id(void); static inline CT__ti_sysbios_family_arm_v7a_Pmu_Module__id ti_sysbios_family_arm_v7a_Pmu_Module_id( void ) { return ti_sysbios_family_arm_v7a_Pmu_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_family_arm_v7a_Pmu_Module_hasMask(void); static inline xdc_Bool ti_sysbios_family_arm_v7a_Pmu_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask__C != (CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_family_arm_v7a_Pmu_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_family_arm_v7a_Pmu_Module_getMask(void) { return (ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask__C != (CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask)0) ? *ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_family_arm_v7a_Pmu_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_family_arm_v7a_Pmu_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask__C != (CT__ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask)0) { *ti_sysbios_family_arm_v7a_Pmu_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION DECLARATIONS * CONVERTORS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.family.arm.v7r.vim.Hwi ======== */ typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_VIM ti_sysbios_family_arm_v7r_vim_Hwi_VIM; typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Module_State ti_sysbios_family_arm_v7r_vim_Hwi_Module_State; typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Fxns__ ti_sysbios_family_arm_v7r_vim_Hwi_Fxns__; typedef const struct ti_sysbios_family_arm_v7r_vim_Hwi_Fxns__* ti_sysbios_family_arm_v7r_vim_Hwi_Module; typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Params ti_sysbios_family_arm_v7r_vim_Hwi_Params; typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Object ti_sysbios_family_arm_v7r_vim_Hwi_Object; typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Struct ti_sysbios_family_arm_v7r_vim_Hwi_Struct; typedef ti_sysbios_family_arm_v7r_vim_Hwi_Object* ti_sysbios_family_arm_v7r_vim_Hwi_Handle; typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Object__ ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State; typedef ti_sysbios_family_arm_v7r_vim_Hwi_Object* ti_sysbios_family_arm_v7r_vim_Hwi_Instance; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_family_arm_v7r_vim_Hwi_FuncPtr; /* Irp */ typedef ti_sysbios_interfaces_IHwi_Irp ti_sysbios_family_arm_v7r_vim_Hwi_Irp; /* HookSet */ typedef ti_sysbios_interfaces_IHwi_HookSet ti_sysbios_family_arm_v7r_vim_Hwi_HookSet; /* MaskingOption */ typedef ti_sysbios_interfaces_IHwi_MaskingOption ti_sysbios_family_arm_v7r_vim_Hwi_MaskingOption; /* StackInfo */ typedef ti_sysbios_interfaces_IHwi_StackInfo ti_sysbios_family_arm_v7r_vim_Hwi_StackInfo; /* VectorFuncPtr */ typedef void (*ti_sysbios_family_arm_v7r_vim_Hwi_VectorFuncPtr)(void ); /* PlugFuncPtr */ typedef void (*ti_sysbios_family_arm_v7r_vim_Hwi_PlugFuncPtr)(void ); /* Type */ enum ti_sysbios_family_arm_v7r_vim_Hwi_Type { ti_sysbios_family_arm_v7r_vim_Hwi_Type_IRQ, ti_sysbios_family_arm_v7r_vim_Hwi_Type_FIQ }; typedef enum ti_sysbios_family_arm_v7r_vim_Hwi_Type ti_sysbios_family_arm_v7r_vim_Hwi_Type; /* VIM */ typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__RES00; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__RES00[2]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__RES00[2]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__RES00 __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__RES00; typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__FIRQPR; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__FIRQPR[4]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__FIRQPR[4]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__FIRQPR __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__FIRQPR; typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__INTREQ; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__INTREQ[4]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__INTREQ[4]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__INTREQ __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__INTREQ; typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENASET; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENASET[4]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENASET[4]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENASET __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENASET; typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENACLR; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENACLR[4]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENACLR[4]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENACLR __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENACLR; typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENASET; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENASET[4]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENASET[4]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENASET __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENASET; typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENACLR; typedef xdc_UInt32 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENACLR[4]; typedef xdc_UInt32 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENACLR[4]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENACLR __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENACLR; typedef xdc_UInt8 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__CHANCTRL; typedef xdc_UInt8 ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__CHANCTRL[128]; typedef xdc_UInt8 CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__CHANCTRL[128]; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__CHANCTRL __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__CHANCTRL; struct ti_sysbios_family_arm_v7r_vim_Hwi_VIM { xdc_UInt32 ECCSTAT; xdc_UInt32 ECCCTL; xdc_UInt32 UERRADDR; xdc_UInt32 FBVECADDR; xdc_UInt32 SBERRADDR; xdc_UInt32 IRQINDEX; xdc_UInt32 FIQINDEX; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__RES00 RES00; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__FIRQPR FIRQPR; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__INTREQ INTREQ; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENASET REQENASET; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__REQENACLR REQENACLR; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENASET WAKEENASET; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__WAKEENACLR WAKEENACLR; xdc_UInt32 IRQVECREG; xdc_UInt32 FIQVECREG; xdc_UInt32 CAPEVT; xdc_UInt32 RES01; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_VIM__CHANCTRL CHANCTRL; }; /* vim */ extern volatile ti_sysbios_family_arm_v7r_vim_Hwi_VIM ti_sysbios_family_arm_v7r_vim_Hwi_vim; /* MaskingOption_NONE */ /* MaskingOption_ALL */ /* MaskingOption_SELF */ /* MaskingOption_BITMASK */ /* MaskingOption_LOWER */ /* * ======== CREATE ARGS ======== */ /* Args__create */ typedef struct ti_sysbios_family_arm_v7r_vim_Hwi_Args__create { xdc_Int intNum; ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn; } ti_sysbios_family_arm_v7r_vim_Hwi_Args__create; /* * ======== INTERNAL DEFINITIONS ======== */ /* Instance_State */ typedef xdc_Ptr __T1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__hookEnv; typedef xdc_Ptr *ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__hookEnv; typedef const xdc_Ptr *CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__hookEnv; typedef ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__hookEnv __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__hookEnv; typedef xdc_UInt __T1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__disableMask; typedef xdc_UInt ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__disableMask[4]; typedef xdc_UInt CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__disableMask[4]; typedef ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__disableMask __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__disableMask; /* Module_State */ typedef xdc_Char __T1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__fiqStack; typedef xdc_Char *ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__fiqStack; typedef const xdc_Char *CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__fiqStack; typedef ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__fiqStack __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__fiqStack; typedef ti_sysbios_family_arm_v7r_vim_Hwi_Handle __T1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__dispatchTable; typedef ti_sysbios_family_arm_v7r_vim_Hwi_Handle *ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__dispatchTable; typedef const ti_sysbios_family_arm_v7r_vim_Hwi_Handle *CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__dispatchTable; typedef ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__dispatchTable __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__dispatchTable; typedef xdc_UInt __T1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__zeroLatencyFIQMask; typedef xdc_UInt ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__zeroLatencyFIQMask[4]; typedef xdc_UInt CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__zeroLatencyFIQMask[4]; typedef ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__zeroLatencyFIQMask __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Module_State__zeroLatencyFIQMask; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsEnabled; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsEnabled ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsIncluded; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsIncluded ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__gateObj; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__gateObj ti_sysbios_family_arm_v7r_vim_Hwi_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__gatePrms; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__gatePrms ti_sysbios_family_arm_v7r_vim_Hwi_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__id; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__id ti_sysbios_family_arm_v7r_vim_Hwi_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerDefined; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerDefined ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerObj; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerObj ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn0; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn0 ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn1; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn1 ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn2; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn2 ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn4; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn4 ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn8; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn8 ti_sysbios_family_arm_v7r_vim_Hwi_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__count; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__count ti_sysbios_family_arm_v7r_vim_Hwi_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__heap; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__heap ti_sysbios_family_arm_v7r_vim_Hwi_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__sizeof; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__sizeof ti_sysbios_family_arm_v7r_vim_Hwi_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__table; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_Object__table ti_sysbios_family_arm_v7r_vim_Hwi_Object__table__C; /* dispatcherAutoNestingSupport */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherAutoNestingSupport; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherAutoNestingSupport ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherAutoNestingSupport__C; /* dispatcherSwiSupport */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherSwiSupport; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherSwiSupport ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherSwiSupport__C; /* dispatcherTaskSupport */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherTaskSupport; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherTaskSupport ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherTaskSupport__C; /* dispatcherIrpTrackingSupport */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherIrpTrackingSupport; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherIrpTrackingSupport ti_sysbios_family_arm_v7r_vim_Hwi_dispatcherIrpTrackingSupport__C; /* NUM_INTERRUPTS */ typedef xdc_UInt CT__ti_sysbios_family_arm_v7r_vim_Hwi_NUM_INTERRUPTS; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_NUM_INTERRUPTS ti_sysbios_family_arm_v7r_vim_Hwi_NUM_INTERRUPTS__C; /* core0VectorTableAddress */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_core0VectorTableAddress; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_core0VectorTableAddress ti_sysbios_family_arm_v7r_vim_Hwi_core0VectorTableAddress__C; /* core1VectorTableAddress */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_core1VectorTableAddress; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_core1VectorTableAddress ti_sysbios_family_arm_v7r_vim_Hwi_core1VectorTableAddress__C; /* phantomFunc */ typedef ti_sysbios_family_arm_v7r_vim_Hwi_VectorFuncPtr CT__ti_sysbios_family_arm_v7r_vim_Hwi_phantomFunc; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_phantomFunc ti_sysbios_family_arm_v7r_vim_Hwi_phantomFunc__C; /* fiqStack */ typedef xdc_Ptr CT__ti_sysbios_family_arm_v7r_vim_Hwi_fiqStack; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_fiqStack ti_sysbios_family_arm_v7r_vim_Hwi_fiqStack__C; /* errataInitEsm */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_errataInitEsm; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_errataInitEsm ti_sysbios_family_arm_v7r_vim_Hwi_errataInitEsm__C; /* resetVIM */ typedef xdc_Bool CT__ti_sysbios_family_arm_v7r_vim_Hwi_resetVIM; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_resetVIM ti_sysbios_family_arm_v7r_vim_Hwi_resetVIM__C; /* A_badChannelId */ typedef xdc_runtime_Assert_Id CT__ti_sysbios_family_arm_v7r_vim_Hwi_A_badChannelId; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_A_badChannelId ti_sysbios_family_arm_v7r_vim_Hwi_A_badChannelId__C; /* E_alreadyDefined */ typedef xdc_runtime_Error_Id CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_alreadyDefined; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_alreadyDefined ti_sysbios_family_arm_v7r_vim_Hwi_E_alreadyDefined__C; /* E_badIntNum */ typedef xdc_runtime_Error_Id CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_badIntNum; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_badIntNum ti_sysbios_family_arm_v7r_vim_Hwi_E_badIntNum__C; /* E_undefined */ typedef xdc_runtime_Error_Id CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_undefined; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_undefined ti_sysbios_family_arm_v7r_vim_Hwi_E_undefined__C; /* E_unsupportedMaskingOption */ typedef xdc_runtime_Error_Id CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_unsupportedMaskingOption; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_unsupportedMaskingOption ti_sysbios_family_arm_v7r_vim_Hwi_E_unsupportedMaskingOption__C; /* E_phantomInterrupt */ typedef xdc_runtime_Error_Id CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_phantomInterrupt; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_E_phantomInterrupt ti_sysbios_family_arm_v7r_vim_Hwi_E_phantomInterrupt__C; /* LM_begin */ typedef xdc_runtime_Log_Event CT__ti_sysbios_family_arm_v7r_vim_Hwi_LM_begin; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_LM_begin ti_sysbios_family_arm_v7r_vim_Hwi_LM_begin__C; /* LD_end */ typedef xdc_runtime_Log_Event CT__ti_sysbios_family_arm_v7r_vim_Hwi_LD_end; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_LD_end ti_sysbios_family_arm_v7r_vim_Hwi_LD_end__C; /* channelMap */ typedef xdc_UInt8 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_channelMap; typedef xdc_UInt8 *ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_channelMap; typedef const xdc_UInt8 *CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_channelMap; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_channelMap __TA_ti_sysbios_family_arm_v7r_vim_Hwi_channelMap; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_channelMap CT__ti_sysbios_family_arm_v7r_vim_Hwi_channelMap; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_channelMap ti_sysbios_family_arm_v7r_vim_Hwi_channelMap__C; /* intReqEnaSet */ typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet; typedef xdc_UInt32 *ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet; typedef const xdc_UInt32 *CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet __TA_ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet CT__ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet ti_sysbios_family_arm_v7r_vim_Hwi_intReqEnaSet__C; /* wakeEnaSet */ typedef xdc_UInt32 __T1_ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet; typedef xdc_UInt32 *ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet; typedef const xdc_UInt32 *CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet __TA_ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet CT__ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet ti_sysbios_family_arm_v7r_vim_Hwi_wakeEnaSet__C; /* swiDisable */ typedef xdc_UInt (*CT__ti_sysbios_family_arm_v7r_vim_Hwi_swiDisable)(void); extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_swiDisable ti_sysbios_family_arm_v7r_vim_Hwi_swiDisable__C; /* swiRestoreHwi */ typedef void (*CT__ti_sysbios_family_arm_v7r_vim_Hwi_swiRestoreHwi)(xdc_UInt arg1); extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_swiRestoreHwi ti_sysbios_family_arm_v7r_vim_Hwi_swiRestoreHwi__C; /* taskDisable */ typedef xdc_UInt (*CT__ti_sysbios_family_arm_v7r_vim_Hwi_taskDisable)(void); extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_taskDisable ti_sysbios_family_arm_v7r_vim_Hwi_taskDisable__C; /* taskRestoreHwi */ typedef void (*CT__ti_sysbios_family_arm_v7r_vim_Hwi_taskRestoreHwi)(xdc_UInt arg1); extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_taskRestoreHwi ti_sysbios_family_arm_v7r_vim_Hwi_taskRestoreHwi__C; /* hooks */ typedef ti_sysbios_family_arm_v7r_vim_Hwi_HookSet __T1_ti_sysbios_family_arm_v7r_vim_Hwi_hooks; typedef struct { int length; ti_sysbios_family_arm_v7r_vim_Hwi_HookSet *elem; } ARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_hooks; typedef struct { int length; ti_sysbios_family_arm_v7r_vim_Hwi_HookSet const *elem; } CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_hooks; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_hooks __TA_ti_sysbios_family_arm_v7r_vim_Hwi_hooks; typedef CARRAY1_ti_sysbios_family_arm_v7r_vim_Hwi_hooks CT__ti_sysbios_family_arm_v7r_vim_Hwi_hooks; extern const CT__ti_sysbios_family_arm_v7r_vim_Hwi_hooks ti_sysbios_family_arm_v7r_vim_Hwi_hooks__C; /* * ======== PER-INSTANCE TYPES ======== */ /* Params */ struct ti_sysbios_family_arm_v7r_vim_Hwi_Params { size_t __size; const void *__self; void *__fxns; xdc_runtime_IInstance_Params *instance; ti_sysbios_interfaces_IHwi_MaskingOption maskSetting; xdc_UArg arg; xdc_Bool enableInt; xdc_Int eventId; xdc_Int priority; ti_sysbios_family_arm_v7r_vim_Hwi_Type type; xdc_runtime_IInstance_Params __iprms; }; /* Struct */ struct ti_sysbios_family_arm_v7r_vim_Hwi_Struct { const ti_sysbios_family_arm_v7r_vim_Hwi_Fxns__ *__fxns; ti_sysbios_family_arm_v7r_vim_Hwi_Type f0; xdc_UArg f1; ti_sysbios_family_arm_v7r_vim_Hwi_FuncPtr f2; xdc_Int f3; ti_sysbios_family_arm_v7r_vim_Hwi_Irp f4; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__hookEnv f5; __TA_ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State__disableMask f6; xdc_runtime_Types_CordAddr __name; }; /* * ======== VIRTUAL FUNCTIONS ======== */ /* Fxns__ */ struct ti_sysbios_family_arm_v7r_vim_Hwi_Fxns__ { const xdc_runtime_Types_Base* __base; const xdc_runtime_Types_SysFxns2* __sysp; xdc_Bool (*getStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth); xdc_Bool (*getCoreStackInfo)(ti_sysbios_interfaces_IHwi_StackInfo* stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId); void (*startup)(void); xdc_UInt (*disable)(void); xdc_UInt (*enable)(void); void (*restore)(xdc_UInt key); void (*switchFromBootStack)(void); void (*post)(xdc_UInt intNum); xdc_Char *(*getTaskSP)(void); xdc_UInt (*disableInterrupt)(xdc_UInt intNum); xdc_UInt (*enableInterrupt)(xdc_UInt intNum); void (*restoreInterrupt)(xdc_UInt intNum, xdc_UInt key); void (*clearInterrupt)(xdc_UInt intNum); ti_sysbios_interfaces_IHwi_FuncPtr (*getFunc)(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst, xdc_UArg* arg); void (*setFunc)(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg); xdc_Ptr (*getHookContext)(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst, xdc_Int id); void (*setHookContext)(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst, xdc_Int id, xdc_Ptr hookContext); ti_sysbios_interfaces_IHwi_Irp (*getIrp)(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst); xdc_runtime_Types_SysFxns2 __sfxns; }; /* Module__FXNS__C */ extern const ti_sysbios_family_arm_v7r_vim_Hwi_Fxns__ ti_sysbios_family_arm_v7r_vim_Hwi_Module__FXNS__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ extern xdc_Int ti_sysbios_family_arm_v7r_vim_Hwi_Module_startup__E( xdc_Int state ); extern xdc_Int ti_sysbios_family_arm_v7r_vim_Hwi_Module_startup__F( xdc_Int state ); /* Instance_init__E */ extern xdc_Int ti_sysbios_family_arm_v7r_vim_Hwi_Instance_init__E(ti_sysbios_family_arm_v7r_vim_Hwi_Object *obj, xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_family_arm_v7r_vim_Hwi_Params *prms, xdc_runtime_Error_Block *eb); /* Instance_finalize__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_Instance_finalize__E(ti_sysbios_family_arm_v7r_vim_Hwi_Object *obj, int ec); /* create */ extern ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_create( xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_family_arm_v7r_vim_Hwi_Params *prms, xdc_runtime_Error_Block *eb); /* construct */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_construct(ti_sysbios_family_arm_v7r_vim_Hwi_Struct *obj, xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_family_arm_v7r_vim_Hwi_Params *prms, xdc_runtime_Error_Block *eb); /* delete */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_delete(ti_sysbios_family_arm_v7r_vim_Hwi_Handle *instp); /* destruct */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_destruct(ti_sysbios_family_arm_v7r_vim_Hwi_Struct *obj); /* Handle__label__S */ extern xdc_runtime_Types_Label *ti_sysbios_family_arm_v7r_vim_Hwi_Handle__label__S( xdc_Ptr obj, xdc_runtime_Types_Label *lab ); /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_family_arm_v7r_vim_Hwi_Module__startupDone__S( void ); /* Object__create__S */ extern xdc_Ptr ti_sysbios_family_arm_v7r_vim_Hwi_Object__create__S( xdc_CPtr aa, const xdc_UChar *pa, xdc_SizeT psz, xdc_runtime_Error_Block *eb ); /* Object__delete__S */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_Object__delete__S( xdc_Ptr instp ); /* Object__get__S */ extern xdc_Ptr ti_sysbios_family_arm_v7r_vim_Hwi_Object__get__S( xdc_Ptr oarr, xdc_Int i ); /* Object__first__S */ extern xdc_Ptr ti_sysbios_family_arm_v7r_vim_Hwi_Object__first__S( void ); /* Object__next__S */ extern xdc_Ptr ti_sysbios_family_arm_v7r_vim_Hwi_Object__next__S( xdc_Ptr obj ); /* Params__init__S */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ); /* getStackInfo__E */ extern xdc_Bool ti_sysbios_family_arm_v7r_vim_Hwi_getStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth ); /* getCoreStackInfo__E */ extern xdc_Bool ti_sysbios_family_arm_v7r_vim_Hwi_getCoreStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId ); /* startup__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_startup__E( void ); /* switchFromBootStack__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_switchFromBootStack__E( void ); /* post__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_post__E( xdc_UInt intNum ); /* getTaskSP__E */ extern xdc_Char *ti_sysbios_family_arm_v7r_vim_Hwi_getTaskSP__E( void ); /* disableInterrupt__E */ extern xdc_UInt ti_sysbios_family_arm_v7r_vim_Hwi_disableInterrupt__E( xdc_UInt intNum ); /* enableInterrupt__E */ extern xdc_UInt ti_sysbios_family_arm_v7r_vim_Hwi_enableInterrupt__E( xdc_UInt intNum ); /* restoreInterrupt__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_restoreInterrupt__E( xdc_UInt intNum, xdc_UInt key ); /* clearInterrupt__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_clearInterrupt__E( xdc_UInt intNum ); /* getFunc__E */ extern ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_family_arm_v7r_vim_Hwi_getFunc__E( ti_sysbios_family_arm_v7r_vim_Hwi_Handle __inst, xdc_UArg *arg ); /* setFunc__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_setFunc__E( ti_sysbios_family_arm_v7r_vim_Hwi_Handle __inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg ); /* getHookContext__E */ extern xdc_Ptr ti_sysbios_family_arm_v7r_vim_Hwi_getHookContext__E( ti_sysbios_family_arm_v7r_vim_Hwi_Handle __inst, xdc_Int id ); /* setHookContext__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_setHookContext__E( ti_sysbios_family_arm_v7r_vim_Hwi_Handle __inst, xdc_Int id, xdc_Ptr hookContext ); /* getIrp__E */ extern ti_sysbios_interfaces_IHwi_Irp ti_sysbios_family_arm_v7r_vim_Hwi_getIrp__E( ti_sysbios_family_arm_v7r_vim_Hwi_Handle __inst ); /* getHandle__E */ extern ti_sysbios_family_arm_v7r_vim_Hwi_Object *ti_sysbios_family_arm_v7r_vim_Hwi_getHandle__E( xdc_UInt intNum ); /* enableIRQ__E */ extern xdc_UInt ti_sysbios_family_arm_v7r_vim_Hwi_enableIRQ__E( void ); /* disableIRQ__E */ extern xdc_UInt ti_sysbios_family_arm_v7r_vim_Hwi_disableIRQ__E( void ); /* restoreIRQ__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_restoreIRQ__E( xdc_UInt key ); /* setType__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_setType__E( xdc_UInt intNum, ti_sysbios_family_arm_v7r_vim_Hwi_Type type ); /* reconfig__E */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_reconfig__E( ti_sysbios_family_arm_v7r_vim_Hwi_Handle __inst, ti_sysbios_family_arm_v7r_vim_Hwi_FuncPtr fxn, const ti_sysbios_family_arm_v7r_vim_Hwi_Params *params ); /* initEsm__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_initEsm__I( void ); /* postInit__I */ extern xdc_Int ti_sysbios_family_arm_v7r_vim_Hwi_postInit__I( ti_sysbios_family_arm_v7r_vim_Hwi_Object *hwi, xdc_runtime_Error_Block *eb ); /* initIntController__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_initIntController__I( void ); /* init__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_init__I( void ); /* dispatchIRQ__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_dispatchIRQ__I( void ); /* dispatchIRQC__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_dispatchIRQC__I( ti_sysbios_family_arm_v7r_vim_Hwi_Irp irp ); /* phantomIntHandler__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_phantomIntHandler__I( void ); /* mapChannel__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_mapChannel__I( xdc_UInt channelId, xdc_UInt intRequestId ); /* nonPluggedHwiHandler__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_nonPluggedHwiHandler__I( xdc_UArg arg ); /* plug__I */ extern void ti_sysbios_family_arm_v7r_vim_Hwi_plug__I( xdc_UInt intNum, ti_sysbios_family_arm_v7r_vim_Hwi_PlugFuncPtr fxn ); /* * ======== CONVERTORS ======== */ /* Module_upCast */ static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_family_arm_v7r_vim_Hwi_Module_upCast(void); static inline ti_sysbios_interfaces_IHwi_Module ti_sysbios_family_arm_v7r_vim_Hwi_Module_upCast(void) { return (ti_sysbios_interfaces_IHwi_Module)&ti_sysbios_family_arm_v7r_vim_Hwi_Module__FXNS__C; } /* Module_to_ti_sysbios_interfaces_IHwi */ /* Handle_upCast */ static inline ti_sysbios_interfaces_IHwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Handle_upCast(ti_sysbios_family_arm_v7r_vim_Hwi_Handle i); static inline ti_sysbios_interfaces_IHwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Handle_upCast(ti_sysbios_family_arm_v7r_vim_Hwi_Handle i) { return (ti_sysbios_interfaces_IHwi_Handle)i; } /* Handle_to_ti_sysbios_interfaces_IHwi */ /* Handle_downCast */ static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Handle_downCast(ti_sysbios_interfaces_IHwi_Handle i); static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Handle_downCast(ti_sysbios_interfaces_IHwi_Handle i) { ti_sysbios_interfaces_IHwi_Handle i2 = (ti_sysbios_interfaces_IHwi_Handle)i; return ((const void*)i2->__fxns == (const void*)&ti_sysbios_family_arm_v7r_vim_Hwi_Module__FXNS__C) ? (ti_sysbios_family_arm_v7r_vim_Hwi_Handle)i : (ti_sysbios_family_arm_v7r_vim_Hwi_Handle)0; } /* Handle_from_ti_sysbios_interfaces_IHwi */ /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__id ti_sysbios_family_arm_v7r_vim_Hwi_Module_id(void); static inline CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__id ti_sysbios_family_arm_v7r_vim_Hwi_Module_id( void ) { return ti_sysbios_family_arm_v7r_vim_Hwi_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_family_arm_v7r_vim_Hwi_Module_hasMask(void); static inline xdc_Bool ti_sysbios_family_arm_v7r_vim_Hwi_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask__C != (CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_family_arm_v7r_vim_Hwi_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_family_arm_v7r_vim_Hwi_Module_getMask(void) { return (ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask__C != (CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask)0) ? *ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_family_arm_v7r_vim_Hwi_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_family_arm_v7r_vim_Hwi_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask__C != (CT__ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask)0) { *ti_sysbios_family_arm_v7r_vim_Hwi_Module__diagsMask__C = mask; } } /* Params_init */ static inline void ti_sysbios_family_arm_v7r_vim_Hwi_Params_init(ti_sysbios_family_arm_v7r_vim_Hwi_Params *prms); static inline void ti_sysbios_family_arm_v7r_vim_Hwi_Params_init( ti_sysbios_family_arm_v7r_vim_Hwi_Params *prms ) { if (prms != 0) { ti_sysbios_family_arm_v7r_vim_Hwi_Params__init__S(prms, 0, sizeof(ti_sysbios_family_arm_v7r_vim_Hwi_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Params_copy */ static inline void ti_sysbios_family_arm_v7r_vim_Hwi_Params_copy(ti_sysbios_family_arm_v7r_vim_Hwi_Params *dst, const ti_sysbios_family_arm_v7r_vim_Hwi_Params *src); static inline void ti_sysbios_family_arm_v7r_vim_Hwi_Params_copy(ti_sysbios_family_arm_v7r_vim_Hwi_Params *dst, const ti_sysbios_family_arm_v7r_vim_Hwi_Params *src) { if (dst != 0) { ti_sysbios_family_arm_v7r_vim_Hwi_Params__init__S(dst, (const void *)src, sizeof(ti_sysbios_family_arm_v7r_vim_Hwi_Params), sizeof(xdc_runtime_IInstance_Params)); } } /* Object_count */ /* Object_sizeof */ /* Object_get */ static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Object_get(ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State *oarr, int i); static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Object_get(ti_sysbios_family_arm_v7r_vim_Hwi_Instance_State *oarr, int i) { return (ti_sysbios_family_arm_v7r_vim_Hwi_Handle)ti_sysbios_family_arm_v7r_vim_Hwi_Object__get__S(oarr, i); } /* Object_first */ static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Object_first(void); static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Object_first(void) { return (ti_sysbios_family_arm_v7r_vim_Hwi_Handle)ti_sysbios_family_arm_v7r_vim_Hwi_Object__first__S(); } /* Object_next */ static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Object_next(ti_sysbios_family_arm_v7r_vim_Hwi_Object *obj); static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_Object_next(ti_sysbios_family_arm_v7r_vim_Hwi_Object *obj) { return (ti_sysbios_family_arm_v7r_vim_Hwi_Handle)ti_sysbios_family_arm_v7r_vim_Hwi_Object__next__S(obj); } /* Handle_label */ static inline xdc_runtime_Types_Label *ti_sysbios_family_arm_v7r_vim_Hwi_Handle_label(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst, xdc_runtime_Types_Label *lab); static inline xdc_runtime_Types_Label *ti_sysbios_family_arm_v7r_vim_Hwi_Handle_label(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst, xdc_runtime_Types_Label *lab) { return ti_sysbios_family_arm_v7r_vim_Hwi_Handle__label__S(inst, lab); } /* Handle_name */ static inline xdc_String ti_sysbios_family_arm_v7r_vim_Hwi_Handle_name(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst); static inline xdc_String ti_sysbios_family_arm_v7r_vim_Hwi_Handle_name(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst) { xdc_runtime_Types_Label lab; return ti_sysbios_family_arm_v7r_vim_Hwi_Handle__label__S(inst, &lab)->iname; } /* handle */ static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_handle(ti_sysbios_family_arm_v7r_vim_Hwi_Struct *str); static inline ti_sysbios_family_arm_v7r_vim_Hwi_Handle ti_sysbios_family_arm_v7r_vim_Hwi_handle(ti_sysbios_family_arm_v7r_vim_Hwi_Struct *str) { return (ti_sysbios_family_arm_v7r_vim_Hwi_Handle)str; } /* struct */ static inline ti_sysbios_family_arm_v7r_vim_Hwi_Struct *ti_sysbios_family_arm_v7r_vim_Hwi_struct(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst); static inline ti_sysbios_family_arm_v7r_vim_Hwi_Struct *ti_sysbios_family_arm_v7r_vim_Hwi_struct(ti_sysbios_family_arm_v7r_vim_Hwi_Handle inst) { return (ti_sysbios_family_arm_v7r_vim_Hwi_Struct*)inst; } /* * ======== EPILOGUE ======== */ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== Hwi_disable ======== */ /* * ======== Hwi_enable ======== */ /* * ======== Hwi_restore ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== INCLUDES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:30; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== module ti.sysbios.utils.Load ======== */ typedef struct ti_sysbios_utils_Load_Stat ti_sysbios_utils_Load_Stat; typedef struct ti_sysbios_utils_Load_HookContext ti_sysbios_utils_Load_HookContext; typedef struct ti_sysbios_utils_Load_Module_State ti_sysbios_utils_Load_Module_State; /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * PER-INSTANCE TYPES * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E10 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * VIRTUAL FUNCTIONS * FUNCTION STUBS * FUNCTION SELECTORS * * EPILOGUE * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== PREFIX ALIASES ======== */ /* * @(#) xdc.runtime; 2, 1, 0,0; 7-31-2018 11:49:29; /db/ztree/library/trees/xdc/xdc-E10/src/packages/ */ /* * ======== AUXILIARY DEFINITIONS ======== */ /* FuncPtr */ typedef void (*ti_sysbios_utils_Load_FuncPtr)(void); /* Stat */ struct ti_sysbios_utils_Load_Stat { xdc_UInt32 threadTime; xdc_UInt32 totalTime; }; /* * ======== INTERNAL DEFINITIONS ======== */ /* HookContext */ struct ti_sysbios_utils_Load_HookContext { ti_sysbios_knl_Queue_Elem qElem; xdc_UInt32 totalTimeElapsed; xdc_UInt32 totalTime; xdc_UInt32 nextTotalTime; xdc_UInt32 timeOfLastUpdate; xdc_Ptr threadHandle; }; /* Module_State */ typedef xdc_UInt32 __T1_ti_sysbios_utils_Load_Module_State__taskStartTime; typedef xdc_UInt32 *ARRAY1_ti_sysbios_utils_Load_Module_State__taskStartTime; typedef const xdc_UInt32 *CARRAY1_ti_sysbios_utils_Load_Module_State__taskStartTime; typedef ARRAY1_ti_sysbios_utils_Load_Module_State__taskStartTime __TA_ti_sysbios_utils_Load_Module_State__taskStartTime; typedef ti_sysbios_knl_Task_Handle __T1_ti_sysbios_utils_Load_Module_State__runningTask; typedef ti_sysbios_knl_Task_Handle *ARRAY1_ti_sysbios_utils_Load_Module_State__runningTask; typedef const ti_sysbios_knl_Task_Handle *CARRAY1_ti_sysbios_utils_Load_Module_State__runningTask; typedef ARRAY1_ti_sysbios_utils_Load_Module_State__runningTask __TA_ti_sysbios_utils_Load_Module_State__runningTask; typedef ti_sysbios_utils_Load_HookContext __T1_ti_sysbios_utils_Load_Module_State__taskEnv; typedef ti_sysbios_utils_Load_HookContext *ARRAY1_ti_sysbios_utils_Load_Module_State__taskEnv; typedef const ti_sysbios_utils_Load_HookContext *CARRAY1_ti_sysbios_utils_Load_Module_State__taskEnv; typedef ARRAY1_ti_sysbios_utils_Load_Module_State__taskEnv __TA_ti_sysbios_utils_Load_Module_State__taskEnv; /* * ======== MODULE-WIDE CONFIGS ======== */ /* Module__diagsEnabled */ typedef xdc_Bits32 CT__ti_sysbios_utils_Load_Module__diagsEnabled; extern const CT__ti_sysbios_utils_Load_Module__diagsEnabled ti_sysbios_utils_Load_Module__diagsEnabled__C; /* Module__diagsIncluded */ typedef xdc_Bits32 CT__ti_sysbios_utils_Load_Module__diagsIncluded; extern const CT__ti_sysbios_utils_Load_Module__diagsIncluded ti_sysbios_utils_Load_Module__diagsIncluded__C; /* Module__diagsMask */ typedef xdc_Bits16 *CT__ti_sysbios_utils_Load_Module__diagsMask; extern const CT__ti_sysbios_utils_Load_Module__diagsMask ti_sysbios_utils_Load_Module__diagsMask__C; /* Module__gateObj */ typedef xdc_Ptr CT__ti_sysbios_utils_Load_Module__gateObj; extern const CT__ti_sysbios_utils_Load_Module__gateObj ti_sysbios_utils_Load_Module__gateObj__C; /* Module__gatePrms */ typedef xdc_Ptr CT__ti_sysbios_utils_Load_Module__gatePrms; extern const CT__ti_sysbios_utils_Load_Module__gatePrms ti_sysbios_utils_Load_Module__gatePrms__C; /* Module__id */ typedef xdc_runtime_Types_ModuleId CT__ti_sysbios_utils_Load_Module__id; extern const CT__ti_sysbios_utils_Load_Module__id ti_sysbios_utils_Load_Module__id__C; /* Module__loggerDefined */ typedef xdc_Bool CT__ti_sysbios_utils_Load_Module__loggerDefined; extern const CT__ti_sysbios_utils_Load_Module__loggerDefined ti_sysbios_utils_Load_Module__loggerDefined__C; /* Module__loggerObj */ typedef xdc_Ptr CT__ti_sysbios_utils_Load_Module__loggerObj; extern const CT__ti_sysbios_utils_Load_Module__loggerObj ti_sysbios_utils_Load_Module__loggerObj__C; /* Module__loggerFxn0 */ typedef xdc_runtime_Types_LoggerFxn0 CT__ti_sysbios_utils_Load_Module__loggerFxn0; extern const CT__ti_sysbios_utils_Load_Module__loggerFxn0 ti_sysbios_utils_Load_Module__loggerFxn0__C; /* Module__loggerFxn1 */ typedef xdc_runtime_Types_LoggerFxn1 CT__ti_sysbios_utils_Load_Module__loggerFxn1; extern const CT__ti_sysbios_utils_Load_Module__loggerFxn1 ti_sysbios_utils_Load_Module__loggerFxn1__C; /* Module__loggerFxn2 */ typedef xdc_runtime_Types_LoggerFxn2 CT__ti_sysbios_utils_Load_Module__loggerFxn2; extern const CT__ti_sysbios_utils_Load_Module__loggerFxn2 ti_sysbios_utils_Load_Module__loggerFxn2__C; /* Module__loggerFxn4 */ typedef xdc_runtime_Types_LoggerFxn4 CT__ti_sysbios_utils_Load_Module__loggerFxn4; extern const CT__ti_sysbios_utils_Load_Module__loggerFxn4 ti_sysbios_utils_Load_Module__loggerFxn4__C; /* Module__loggerFxn8 */ typedef xdc_runtime_Types_LoggerFxn8 CT__ti_sysbios_utils_Load_Module__loggerFxn8; extern const CT__ti_sysbios_utils_Load_Module__loggerFxn8 ti_sysbios_utils_Load_Module__loggerFxn8__C; /* Object__count */ typedef xdc_Int CT__ti_sysbios_utils_Load_Object__count; extern const CT__ti_sysbios_utils_Load_Object__count ti_sysbios_utils_Load_Object__count__C; /* Object__heap */ typedef xdc_runtime_IHeap_Handle CT__ti_sysbios_utils_Load_Object__heap; extern const CT__ti_sysbios_utils_Load_Object__heap ti_sysbios_utils_Load_Object__heap__C; /* Object__sizeof */ typedef xdc_SizeT CT__ti_sysbios_utils_Load_Object__sizeof; extern const CT__ti_sysbios_utils_Load_Object__sizeof ti_sysbios_utils_Load_Object__sizeof__C; /* Object__table */ typedef xdc_Ptr CT__ti_sysbios_utils_Load_Object__table; extern const CT__ti_sysbios_utils_Load_Object__table ti_sysbios_utils_Load_Object__table__C; /* LS_cpuLoad */ typedef xdc_runtime_Log_Event CT__ti_sysbios_utils_Load_LS_cpuLoad; extern const CT__ti_sysbios_utils_Load_LS_cpuLoad ti_sysbios_utils_Load_LS_cpuLoad__C; /* LS_hwiLoad */ typedef xdc_runtime_Log_Event CT__ti_sysbios_utils_Load_LS_hwiLoad; extern const CT__ti_sysbios_utils_Load_LS_hwiLoad ti_sysbios_utils_Load_LS_hwiLoad__C; /* LS_swiLoad */ typedef xdc_runtime_Log_Event CT__ti_sysbios_utils_Load_LS_swiLoad; extern const CT__ti_sysbios_utils_Load_LS_swiLoad ti_sysbios_utils_Load_LS_swiLoad__C; /* LS_taskLoad */ typedef xdc_runtime_Log_Event CT__ti_sysbios_utils_Load_LS_taskLoad; extern const CT__ti_sysbios_utils_Load_LS_taskLoad ti_sysbios_utils_Load_LS_taskLoad__C; /* postUpdate */ typedef ti_sysbios_utils_Load_FuncPtr CT__ti_sysbios_utils_Load_postUpdate; extern const CT__ti_sysbios_utils_Load_postUpdate ti_sysbios_utils_Load_postUpdate__C; /* updateInIdle */ typedef xdc_Bool CT__ti_sysbios_utils_Load_updateInIdle; extern const CT__ti_sysbios_utils_Load_updateInIdle ti_sysbios_utils_Load_updateInIdle__C; /* windowInMs */ typedef xdc_UInt CT__ti_sysbios_utils_Load_windowInMs; extern const CT__ti_sysbios_utils_Load_windowInMs ti_sysbios_utils_Load_windowInMs__C; /* hwiEnabled */ typedef xdc_Bool CT__ti_sysbios_utils_Load_hwiEnabled; extern const CT__ti_sysbios_utils_Load_hwiEnabled ti_sysbios_utils_Load_hwiEnabled__C; /* swiEnabled */ typedef xdc_Bool CT__ti_sysbios_utils_Load_swiEnabled; extern const CT__ti_sysbios_utils_Load_swiEnabled ti_sysbios_utils_Load_swiEnabled__C; /* taskEnabled */ typedef xdc_Bool CT__ti_sysbios_utils_Load_taskEnabled; extern const CT__ti_sysbios_utils_Load_taskEnabled ti_sysbios_utils_Load_taskEnabled__C; /* autoAddTasks */ typedef xdc_Bool CT__ti_sysbios_utils_Load_autoAddTasks; extern const CT__ti_sysbios_utils_Load_autoAddTasks ti_sysbios_utils_Load_autoAddTasks__C; /* * ======== FUNCTION DECLARATIONS ======== */ /* Module_startup */ /* Module__startupDone__S */ extern xdc_Bool ti_sysbios_utils_Load_Module__startupDone__S( void ); /* getTaskLoad__E */ extern xdc_Bool ti_sysbios_utils_Load_getTaskLoad__E( ti_sysbios_knl_Task_Handle task, ti_sysbios_utils_Load_Stat *stat ); /* update__E */ extern void ti_sysbios_utils_Load_update__E( void ); /* updateCPULoad__E */ extern void ti_sysbios_utils_Load_updateCPULoad__E( void ); /* updateLoads__E */ extern void ti_sysbios_utils_Load_updateLoads__E( void ); /* updateContextsAndPost__E */ extern void ti_sysbios_utils_Load_updateContextsAndPost__E( void ); /* updateCurrentThreadTime__E */ extern void ti_sysbios_utils_Load_updateCurrentThreadTime__E( void ); /* updateThreadContexts__E */ extern void ti_sysbios_utils_Load_updateThreadContexts__E( void ); /* reset__E */ extern void ti_sysbios_utils_Load_reset__E( void ); /* getGlobalSwiLoad__E */ extern xdc_Bool ti_sysbios_utils_Load_getGlobalSwiLoad__E( ti_sysbios_utils_Load_Stat *stat ); /* getGlobalHwiLoad__E */ extern xdc_Bool ti_sysbios_utils_Load_getGlobalHwiLoad__E( ti_sysbios_utils_Load_Stat *stat ); /* getCPULoad__E */ extern xdc_UInt32 ti_sysbios_utils_Load_getCPULoad__E( void ); /* calculateLoad__E */ extern xdc_UInt32 ti_sysbios_utils_Load_calculateLoad__E( ti_sysbios_utils_Load_Stat *stat ); /* setMinIdle__E */ extern xdc_UInt32 ti_sysbios_utils_Load_setMinIdle__E( xdc_UInt32 newMinIdleTime ); /* addTask__E */ extern void ti_sysbios_utils_Load_addTask__E( ti_sysbios_knl_Task_Handle task, ti_sysbios_utils_Load_HookContext *env ); /* removeTask__E */ extern xdc_Bool ti_sysbios_utils_Load_removeTask__E( ti_sysbios_knl_Task_Handle task ); /* idleFxn__E */ extern void ti_sysbios_utils_Load_idleFxn__E( void ); /* idleFxnPwr__E */ extern void ti_sysbios_utils_Load_idleFxnPwr__E( void ); /* startup__E */ extern void ti_sysbios_utils_Load_startup__E( void ); /* taskCreateHook__E */ extern void ti_sysbios_utils_Load_taskCreateHook__E( ti_sysbios_knl_Task_Handle task, xdc_runtime_Error_Block *eb ); /* taskDeleteHook__E */ extern void ti_sysbios_utils_Load_taskDeleteHook__E( ti_sysbios_knl_Task_Handle task ); /* taskSwitchHook__E */ extern void ti_sysbios_utils_Load_taskSwitchHook__E( ti_sysbios_knl_Task_Handle curTask, ti_sysbios_knl_Task_Handle nextTask ); /* swiBeginHook__E */ extern void ti_sysbios_utils_Load_swiBeginHook__E( ti_sysbios_knl_Swi_Handle swi ); /* swiEndHook__E */ extern void ti_sysbios_utils_Load_swiEndHook__E( ti_sysbios_knl_Swi_Handle swi ); /* hwiBeginHook__E */ extern void ti_sysbios_utils_Load_hwiBeginHook__E( ti_sysbios_interfaces_IHwi_Handle hwi ); /* hwiEndHook__E */ extern void ti_sysbios_utils_Load_hwiEndHook__E( ti_sysbios_interfaces_IHwi_Handle hwi ); /* taskRegHook__E */ extern void ti_sysbios_utils_Load_taskRegHook__E( xdc_Int id ); /* logLoads__I */ extern void ti_sysbios_utils_Load_logLoads__I( void ); /* logCPULoad__I */ extern void ti_sysbios_utils_Load_logCPULoad__I( void ); /* * ======== SYSTEM FUNCTIONS ======== */ /* Module_startupDone */ /* Object_heap */ /* Module_heap */ /* Module_id */ static inline CT__ti_sysbios_utils_Load_Module__id ti_sysbios_utils_Load_Module_id(void); static inline CT__ti_sysbios_utils_Load_Module__id ti_sysbios_utils_Load_Module_id( void ) { return ti_sysbios_utils_Load_Module__id__C; } /* Module_hasMask */ static inline xdc_Bool ti_sysbios_utils_Load_Module_hasMask(void); static inline xdc_Bool ti_sysbios_utils_Load_Module_hasMask(void) { return (xdc_Bool)(ti_sysbios_utils_Load_Module__diagsMask__C != (CT__ti_sysbios_utils_Load_Module__diagsMask)0); } /* Module_getMask */ static inline xdc_Bits16 ti_sysbios_utils_Load_Module_getMask(void); static inline xdc_Bits16 ti_sysbios_utils_Load_Module_getMask(void) { return (ti_sysbios_utils_Load_Module__diagsMask__C != (CT__ti_sysbios_utils_Load_Module__diagsMask)0) ? *ti_sysbios_utils_Load_Module__diagsMask__C : (xdc_Bits16)0; } /* Module_setMask */ static inline void ti_sysbios_utils_Load_Module_setMask(xdc_Bits16 mask); static inline void ti_sysbios_utils_Load_Module_setMask(xdc_Bits16 mask) { if (ti_sysbios_utils_Load_Module__diagsMask__C != (CT__ti_sysbios_utils_Load_Module__diagsMask)0) { *ti_sysbios_utils_Load_Module__diagsMask__C = mask; } } /* * ======== EPILOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* module prefix */ /* mmWave SDK Include Files: */ /** * @file sys_common.h * * @brief * This is the common header file used by the various mmWave SDK * modules. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file sys_types.h * * @brief * This is the common header file that contains types for mmwave SDK * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Although below header is not needed to be included for this header file, it lets * user include only sys_types.h to get all the standard types as well as types defines * in this file */ /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /* If this file is included in C99 mode, _Bool is a builtin, so no definition. */ /* If this is C89 mode and this file is included, _Bool is pre-defined in C89 */ /* relaxed mode by the EDG parser, so it needs to be defined in strict mode. */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") _Pragma("CHECK_MISRA(\"-19.11\")") _Pragma("diag_pop") /*! @brief Complex data type. This type of input, (first real than * imaginary part), is required for DSP lib FFT functions */ typedef struct cmplx16ReIm_t_ { int16_t real; /*!< @brief real part */ int16_t imag; /*!< @brief imaginary part */ } cmplx16ReIm_t; /*! @brief Complex data type, natural for C674x complex * multiplication instructions. */ typedef struct cmplx16ImRe_t_ { int16_t imag; /*!< @brief imaginary part */ int16_t real; /*!< @brief real part */ } cmplx16ImRe_t; /*! @brief Complex data type. This type of input, (first real than * imaginary part), is required for DSP lib FFT functions */ typedef struct cmplx32ReIm_t_ { int32_t real; /*!< @brief real part */ int32_t imag; /*!< @brief imaginary part */ } cmplx32ReIm_t; /*! @brief Complex data type, natural for C674x complex * multiplication instructions */ typedef struct cmplx32ImRe_t_ { int32_t imag; /*!< @brief imaginary part */ int32_t real; /*!< @brief real part */ } cmplx32ImRe_t; /** * @file sys_defs.h * * @brief * This is the common header file that contains definitions that are usable * across mmwave SDK. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /****************************************************************************** * Inline Functions: ******************************************************************************/ static inline uint32_t CSL_FMKR(uint8_t msb, uint8_t lsb, uint32_t val); static inline uint32_t CSL_FEXTR(uint32_t reg, uint8_t msb, uint8_t lsb); static inline uint32_t CSL_FINSR(uint32_t reg, uint8_t msb, uint8_t lsb, uint32_t val); /* the Field MaKe (Raw) macro */ static inline uint32_t CSL_FMKR(uint8_t msb, uint8_t lsb, uint32_t val) { uint32_t mask; uint8_t bits; uint32_t newVal; bits = (msb - lsb + 1U); mask = (1U << bits); mask = mask - 1U; newVal = val & mask; return (newVal << lsb); } /* the Field EXTract (Raw) macro */ static inline uint32_t CSL_FEXTR(volatile uint32_t reg, uint8_t msb, uint8_t lsb) { uint32_t mask; uint8_t bits; uint32_t value; bits = (msb - lsb + 1U); mask = (1U << bits); mask = mask - 1U; value = (reg >> lsb) & mask; return value; } /* the Field INSert (Raw) macro */ static inline uint32_t CSL_FINSR(volatile uint32_t reg, uint8_t msb, uint8_t lsb, uint32_t val) { uint32_t mask; uint8_t bits; uint32_t value; uint32_t tmp; bits = (msb - lsb + 1U); mask = (1U << bits); mask = mask - 1U; value = (mask << lsb); tmp = (reg & ~value); reg = tmp | CSL_FMKR(msb, lsb, val); return reg; } /************************************************************* * Common MACROs *************************************************************/ /*! Max macro */ /*! Min macro */ /*! Memory alignment */ /*! Check for memory non-alignment, returns 1 if not aligned, 0 otherwise */ /*! Check for memory alignment, returns 1 if aligned, 0 otherwise */ /*! Macro for memory alignment to double word (= 2x32-bit = 64-bit). Typically in signal processing the datum sizes are 16 or 32-bits, but optimized code tends to manipulate this data in chunks of 64-bits which are more optimally implemented if the data is aligned to 64-bits even though the underlying datum sizes are less than 64-bits. Such requirements are present for example in several mmwavelib functions. */ /*! Maximum structure alignment on DSP. Assumes the largest sized field is present in the structure, which is 64-bit. Note actual structure may need less alignment because the largest size of a field in the structure may be less than 64-bit. */ /*! Maximum structure alignment on R4F. Assumes the largest sized field is present in the structure, which is 64-bit. Note actual structure may need less alignment because the largest size of a field in the structure may be less than 64-bit. */ /*! Find the next multiple of y for x */ /** * @file sys_common_xwr18xx.h * * @brief * This is the common header file used by the various mmWave SDK * modules for XWR18XX device. * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file sys_common_xwr18xx_mss.h * * @brief * This is the common header file used by the various mmWave SDK * modules for XWR18xx Master subsystem. */ /* \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*! @brief Ensures that data transfer has finished. */ static inline void MEM_BARRIER(void) { asm(" dsb "); } /*********************************************************************** * MSS - Memory Map ************************************************************************/ /** * @defgroup SOC_XWR18XX_MSS_BASE_ADDRESS SOC_XWR18XX_MSS_BASE_ADDRESS * @brief Macros that define Base Addresses of various modules * @{ */ /* MSS System Memory */ /* EDMA defines */ /* CC0 defines */ /* CC1 defines */ /* DSS Controller Register */ /* CBUFF */ /* HWA */ /* L3 RAM, size and num bank definition in sys_common_18xx.h */ /* ADC Buffer, size definition in sys_common_18xx.h */ /* CQ Buffer, size definition in sys_common_18xx.h */ /* HWA Memory, size, num banks, window ram size, num param sets definitions in sys_common_18xx.h */ /* HSRAM, size definition in sys_common_18xx.h */ /* EXT FLASH */ /* System Peripheral Registers */ /*Next 4 defines: MSS mailbox base addresses to communicate with BSS*/ /*Next 4 defines: MSS mailbox base addresses to communicate with DSS*/ /** @}*/ //SOC_XWR18XX_MSS_BASE_ADDRESS /*********************************************************************** * MSS DMA Request Line Mapping ************************************************************************/ /** * @defgroup SOC_XWR18XX_DMA_REQLINES SOC_XWR18XX_DMA_REQLINES * @brief Macros that define values for XWR18xx DMA request lines * @{ */ /** @}*/ //SOC_XWR18XX_DMA_REQLINES /*********************************************************************** * MSS VIM Interrupt Mapping ************************************************************************/ /** * @defgroup SOC_XWR18XX_MSS_INTERRUPTS_MAP SOC_XWR18XX_MSS_INTERRUPTS_MAP * @brief Macros that define VIM Interrupt Mapping * @{ */ /* The following share same interrupt line */ /** @}*/ //SOC_XWR18XX_MSS_INTERRUPTS_MAP /* * MSS ESM Interrupt mapping */ /* Group 1 Errors */ /* Group 2 Errors */ /* Group 3 Errors */ /*********************************************************************** * MSS - CLOCK settings ***********************************************************************/ /* Sys_vclk : 200MHz */ /*********************************************************************** * MSS - Peripheral number of instance definition ***********************************************************************/ /*! @brief R4F to Hardware Accelerator address translation macro. */ /** @defgroup EDMA_HW_DEFS EDMA Hardware Definitions. * * @brief * EDMA hardware definitions consisting of : * - CC and TC base addresses. * - Event mappings into the 64 EDMA lines. * - Interrupt numbers out of EDMA. * - Number of instances of CC, TC, param sets. * @{ */ /* Note: Number of instances of CC, TC, param sets are defined in sys_common_xwr18xx.h */ /** @}*/ /* end defgroup EDMA_HW_DEFS */ /*********************************************************************** * Peripheral number of instance definition ***********************************************************************/ /************************************************************* * BASE Address for the various module as seen by EDMA3 *************************************************************/ /************************************************************* * BASE Address used in the Single Chirp Mode to get the * Chirp Profile Data *************************************************************/ /************************************************************* * BASE Address used in the Multiple Chirp Mode to get the * Chirp Profile Data *************************************************************/ /** @defgroup EDMA_HW_DEFS EDMA Hardware Definitions. * * @brief * EDMA hardware definitions consisting of : * - CC and TC base addresses. * - Event mappings into the 64 EDMA lines. * - Interrupt numbers out of EDMA. * - Number of instances of CC, TC, param sets. * @{ */ /* NOTE: EDMA numInstance, base address, interrupt number are defined in * sys_common_xwr18xx_mss/sys_common_xwr18xx_dss.h */ /*! Note even though EDMA's CCCFG register indicates 6 TCs for CC1, only first 2 * are verified for radar processing flows, hence we limit to 2 TCs. */ /*! @brief EDMA event interrupt mapping for CC 0 */ /*! @brief EDMA event interrupt mapping for CC 1 */ /** @}*/ /* end defgroup EDMA_HW_DEFS */ /* System Memory sizes, address are in corresponding _dss/_mss.h files */ /************************************************************* * MMWAVE System level defines *************************************************************/ /* This is the size of the Chirp Parameters (CP) in CBUFF Units */ /** * * @file mmwave_sdk_version.h * * @brief * This is the cfg header file for the Millimeter Wave Demo * * \par * NOTE: * (C) Copyright 2016-2020 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file soc.h * * @brief * This is the header file for the SOC driver which exposes the * data structures and exported API which can be used by the * applications to use the SOC driver. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage SOC Driver * * The SOC Driver allows the application developers to use the following * sub-modules: * - MSS RCM * - MSS TOP RCM * - DSS/DSS2 REG * - MSS GPCFG * * The SOC header file should be included in an application as follows: * @code #include @endcode * * ## Initializing the driver # * The SOC Driver needs to be initialized once across the System. This is * done using the #SOC_init. None of the SOC API can be used without invoking * this API * * ## Register Layer # * Refer to the soc/include directory for the register layers definitons for * the following modules: * RCM : soc/include/reg_rcm.h * TOP RCM : soc/include/reg_toprcm.h * DSS : soc/include/reg_dssreg.h * GPCFG : soc/include/reg_gpcfg.h */ /** @defgroup SOC_DRIVER SOC Driver */ /** * @file mmwave_error.h * * @brief * Base error codes for the mmWave modules. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** * Base Error Code for the mmWave modules **************************************************************************/ /************************************************************************** * Base Error Code for the mmWave data path (-30000 - -59999) **************************************************************************/ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @defgroup HWIP_OSAL HwiP OSAL Porting Layer * * @brief Hardware Interrupt module for the RTOS Porting Interface * * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order * of the HwiP_restore calls, must be in reversed order. For example: * @code * uintptr_t key1, key2; * key1 = HwiP_disable(); * key2 = HwiP_disable(); * HwiP_restore(key2); * HwiP_restore(key1); * @endcode */ /** @defgroup HWIP_OSAL_EXTERNAL_FUNCTION HwiP OSAL External Functions @ingroup HWIP_OSAL @brief * The section documents the external API exposed by the OSAL Porting layer. */ /** @defgroup HWIP_OSAL_EXTERNAL_DATA_STRUCTURES HwiP OSAL External Data Structures @ingroup HWIP_OSAL @brief * The section has a list of all the definitions which are exposed to the developers */ /** @addtogroup HWIP_OSAL_EXTERNAL_DATA_STRUCTURES @{ */ /*! * @brief Opaque client reference to an instance of a HwiP * * A HwiP_Handle returned from the ::HwiP_create represents that instance. */ typedef void *HwiP_Handle; /*! * @brief Status codes for HwiP APIs */ typedef enum HwiP_Status_e { HwiP_OK = 0, HwiP_FAILURE = -1 } HwiP_Status; /*! * @brief Interrupt Type for HwiP APIs */ typedef enum HwiP_Type_e { HwiP_Type_IRQ = 0, HwiP_Type_FIQ = 1 } HwiP_Type; /*! * @brief Prototype for the entry function for a hardware interrupt */ typedef void (*HwiP_Fxn)(uintptr_t arg); /*! * @brief Basic HwiP Parameters * * Structure that contains the parameters passed into ::HwiP_create * when creating a HwiP instance. The ::HwiP_Params_init function should * be used to initialize the fields to default values before the application sets * the fields manually. The HwiP default parameters are noted in * HwiP_Params_init. */ typedef struct HwiP_Params_t { char *name; /*!< Name of the HWI instance. Memory must persist for the life of the HWI instance. This can be used for debugging purposes, or set to NULL if not needed. */ uintptr_t arg; /*!< Argument passed into the Hwi function. */ uint32_t priority; /*!< Device specific priority. */ HwiP_Type type; /*!< Device specific interrupt type - FIQ, IRQ (default) */ uint8_t enableInt; /*!< Flag to enable this interrupt when object is created. Default is true */ } HwiP_Params; /** @} */ /*! * @brief Function to clear a single interrupt * * @param interruptNum interrupt number to clear * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern void HwiP_clearInterrupt(int32_t interruptNum); /*! * @brief Function to create an interrupt * * @param interruptNum Interrupt Vector Id * * @param hwiFxn entry function of the hardware interrupt * * @param params Pointer to the instance configuration parameters. NULL * denotes to use the default parameters. The HwiP default * parameters are noted in ::HwiP_Params_init. * * @return A HwiP_Handle on success or a NULL on an error * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params); /*! * @brief Function to delete an interrupt * * @param handle returned from the HwiP_create call * * @return * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern HwiP_Status HwiP_delete(HwiP_Handle handle); /*! * @brief Function to disable interrupts to enter a critical region * * This function can be called multiple times, but must unwound in the reverse * order. For example * @code * uintptr_t key1, key2; * key1 = HwiP_disable(); * key2 = HwiP_disable(); * HwiP_restore(key2); * HwiP_restore(key1); * @endcode * * @return A key that must be passed to HwiP_restore to re-enable interrupts. * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern uintptr_t HwiP_disable(void); /*! * @brief Function to disable a single interrupt * * @param interruptNum interrupt number to disable * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern void HwiP_disableInterrupt(int32_t interruptNum); /*! * @brief Function to enable a single interrupt * * @param interruptNum interrupt number to enable * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern void HwiP_enableInterrupt(int32_t interruptNum); /*! * @brief Initialize params structure to default values. * * The default parameters are: * - name: NULL * - arg: 0 * - priority: ~0 * * @param params Pointer to the instance configuration parameters. * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern void HwiP_Params_init(HwiP_Params *params); /*! * @brief Function to restore interrupts to exit a critical region * * @param key return from HwiP_disable * * \ingroup HWIP_OSAL_EXTERNAL_FUNCTION */ extern void HwiP_restore(uintptr_t key); /** @defgroup SOC_DRIVER_EXTERNAL_FUNCTION SOC Driver External Functions @ingroup SOC_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup SOC_DRIVER_EXTERNAL_DATA_STRUCTURE SOC Driver External Data Structures @ingroup SOC_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup SOC_DRIVER_ERROR_CODE SOC Driver Error Codes @ingroup SOC_DRIVER @brief * The section has a list of all the error codes which are generated by the CRC Driver * module */ /** @defgroup SOC_DRIVER_INTERNAL_FUNCTION SOC Driver Internal Functions @ingroup SOC_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup SOC_DRIVER_INTERNAL_DATA_STRUCTURE SOC Driver Internal Data Structures @ingroup SOC_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the SOC module. */ /** @defgroup SOC_DRIVER_INTERNAL_DEFINITION SOC Driver Internal Definitions @ingroup SOC_DRIVER @brief * The section has a list of all internal definitions which are used internally * by the SOC module. */ /** * @file soc_common.h * * @brief * This is the header file for the SOC driver which exposes the * data structures which can be used by the applications to use * the SOC driver. * * \par * NOTE: * (C) Copyright 2016 - 2020 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @addtogroup SOC_DRIVER_ERROR_CODE * Base error code for the SOC module is defined in the * \include ti/common/mmwave_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Internal error */ /** * @brief Error Code: Limits have been exceeded. */ /** * @brief Error Code: BL error. */ /** * @brief Error Code: SOC_translateAddress couldn't translate the provided address * This value is chosen since all other values can map to a valid address in * some domain. */ /** @} */ /** @addtogroup SOC_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief * SOC Driver Handle */ typedef void* SOC_Handle; /** * @brief * SOC System Interrupt Listener Handle */ typedef void* SOC_SysIntListenerHandle; /** * @brief * SOC System Interrupt Listener Function */ typedef void (*SOC_SysIntListenerFxn)(uintptr_t arg); /** * @brief * Enumeration for system clocks * * @details * The enumeration describes the configuration of the system clock. * - On the MSS in the XWR14xx; the System clocks need to be initialized * and setup during SOC Initialization. * - On the XWR16xx/XWR18xx/XWR68xx; either the MSS *OR* DSS can perform clock initialization * Application developers need to determine upfront the system responsible * for doing so. */ typedef enum SOC_SysClock_e { /** * @brief * System Clocks need to be initialized */ SOC_SysClock_INIT = 0x1, /** * @brief * System Clocks initialization is bypassed */ SOC_SysClock_BYPASS_INIT }SOC_SysClock; /** * @brief * Enumeration for address translation from one domain to the other * * @details * The enumeration describes the direction of address translation. */ typedef enum SOC_TranslateAddr_Dir_e { /** * @brief * CPU to EDMA address translation */ SOC_TranslateAddr_Dir_TO_EDMA, /** * @brief * EDMA to CPU address translation */ SOC_TranslateAddr_Dir_FROM_EDMA, /** * @brief * Cross CPU address translation (XWR16xx/XWR18xx/XWR68xx only - MSS to DSS or DSS to MSS) * From the running core to the other core */ SOC_TranslateAddr_Dir_TO_OTHER_CPU, /** * @brief * Cross CPU address translation (XWR16xx/XWR18xx/XWR68xx only - MSS to DSS or DSS to MSS) * From the other core to the running core */ SOC_TranslateAddr_Dir_FROM_OTHER_CPU }SOC_TranslateAddr_Dir; /** * @brief * SOC RCM Module clock Source * * @details * The enumeration defines the module clock source supported by XWR1xxx device. */ typedef enum SOC_PeripheralClkSource_e { /*! VCLK */ SOC_CLKSOURCE_VCLK = 0U, /*! RCCLK */ SOC_CLKSOURCE_RCCLK = 1U, /*! 600MPLL */ SOC_CLKSOURCE_600MPLL = 2U, /*! 240MPLL */ SOC_CLKSOURCE_240MPLL = 3U, /*! CPUCLK */ SOC_CLKSOURCE_CPUCLK = 4U, /*! REFCLK */ SOC_CLKSOURCE_REFCLK = 6U }SOC_PeripheralClkSource; /** * @brief * Enumeration for MPU configuration. * * @details * The enumeration describes the configuration of the memory protection unit. * MPU can be intialized with default values as determined by the SOC_mpu_config() function. * OR * Application can bypass the default MPU initialization and configure MPU as per the application requirement. * In this case, MPU MUST be configured by the application immediately after calling SOC_init(). */ typedef enum SOC_MPUCfg_e { /** * @brief * Memory protection unit to be initialized */ SOC_MPUCfg_CONFIG = 0x0, /** * @brief * Memory protection unit initialization is bypassed */ SOC_MPUCfg_BYPASS_CONFIG }SOC_MPUCfg; /** * @brief * Enumeration for DSS configuration. * * @details * The enumeration describes the desired state of DSP subsystem. * It can be configured to unhalt/power up the DSS or leave in its original state - un-halted state (post ROM BL) * or spinning in while loop (post ccsdebug) . * Note: * - If the DSS is left in the halted state, it is the application's responsibility to unhalt and power up DSS when required. * - For xwr64xx (device with no DSP), the value of this field is ignored */ typedef enum SOC_DSSCfg_e { /** * @brief * Unhalt and powerup DSS. */ SOC_DSSCfg_UNHALT = 0x0, /** * @brief * No action is done when this option is provided * So DSS is left in the original state - either halted or spinning. */ SOC_DSSCfg_HALT }SOC_DSSCfg; /** * @brief * SOC Configuration * * @details * The structure describes the configuration information which is needed * to open and initialize the SOC Driver. */ typedef struct SOC_Cfg_t { /** * @brief * System clock configuration */ SOC_SysClock clockCfg; /** * @brief * MSS: Memory protection unit configuration */ SOC_MPUCfg mpuCfg; /** * @brief * DSP sub system configuration for MSS to act on. * For device with no DSP (ex: xwr14xx, xwr64xx), the value of this field is ignored */ SOC_DSSCfg dssCfg; }SOC_Cfg; /** * @brief * SOC Interrupt Listener Configuration * * @details * The structure describes the configuration information which is need to initialize * the system interrupt listener */ typedef struct SOC_SysIntListenerCfg_t { /** * @brief * System interrupt on which the listener is to be registered */ uint32_t systemInterrupt; /** * @brief * Listener Function to be registered */ SOC_SysIntListenerFxn listenerFxn; /** * @brief * Optional argument with which the listener function is to be invoked on * an ISR */ uintptr_t arg; }SOC_SysIntListenerCfg; /** * @brief * SOC Secure device firewall capable modules * * @details * The bitmap enum defines the modules that can have firewall enabled/disabled on a secure device * Please note that secure variant may not be available for all device types */ typedef enum SOC_SecureFirewallModule_e { /*! JTAG */ SOC_SECURE_FIREWALL_JTAG = 0x1U, /*! Secure RAM */ SOC_SECURE_FIREWALL_SECURERAM = 0x2U, /*! Logger */ SOC_SECURE_FIREWALL_LOGGER = 0x4U, /*! Trace */ SOC_SECURE_FIREWALL_TRACE = 0x8U, /*! CRYPTO */ SOC_SECURE_FIREWALL_CRYPTO = 0x10U, /*! CEK1, CEK2 firewall */ SOC_SECURE_FIREWALL_CUSTCEK = 0x20U, /*! DMM */ SOC_SECURE_FIREWALL_DMM = 0x40U }SOC_SecureFirewallModule; /** * @brief * SOC device part number definition * * @details * The enum defines the supported radar devices' part number reading from TOPRCM efuse register */ typedef enum SOC_PartNumber_e { /*! AWR14xx devices */ SOC_AWR14XX_nonSecure_PartNumber = 0x40U, /*! IWR14xx devices */ SOC_IWR14XX_nonSecure_PartNumber = 0xA0U, /*! AWR16xx non secure device */ SOC_AWR16XX_nonSecure_PartNumber = 0x60U, /*! IWR16xx non secure device */ SOC_IWR16XX_nonSecure_PartNumber = 0xC0U, /*! AWR16xx secure devices */ SOC_AWR16XX_Secure_PartNumber = 0x61U, /*! IWR16xx secure devices */ SOC_IWR16XX_Secure_PartNumber = 0xC1U, /*! AWR18xx non-secure devices */ SOC_AWR18XX_nonSecure_PartNumber = 0x70U, /*! AWR18xx non-secure devices */ SOC_AWR18XX_Secure_PartNumber = 0x71U, /*! IWR18xx non-secure devices */ SOC_IWR18XX_nonSecure_PartNumber = 0xD0U, /*! AWR18xxAOP non-secure devices */ SOC_AWR18XXAOP_nonSecure_PartNumber = 0xB0U, /*! AWR18xxAOP non-secure devices */ SOC_AWR18XXAOP_Secure_PartNumber = 0xB1U, /*! IWR68xx ES1 non-secure devices */ SOC_IWR68XX_ES1_nonSecure_PartNumber = 0xE0U, /*! AWR64XX nonSecure devices */ SOC_AWR64XX_nonSecure_PartNumber = 0x50U, /*! AWR68XX_QM nonSecure devices */ SOC_AWR68XX_QM_nonSecure_PartNumber = 0x52U, /*! AWR68XX nonSecure devices */ SOC_AWR68XX_nonSecure_PartNumber = 0x51U, /*! AWR68XX Secure devices */ SOC_AWR68XX_Secure_PartNumber = 0x53U, /*! IWR64XX nonSecure devices */ SOC_IWR64XX_nonSecure_PartNumber = 0xE1U, /*! IWR68XX nonSecure devices */ SOC_IWR68XX_ES2_nonSecure_PartNumber = 0xE2U, /*! IWR68xx non-secure devices */ SOC_IWR68XX_nonSecure_PartNumber = SOC_IWR68XX_ES2_nonSecure_PartNumber, /*! IWR68XX Secure devices */ SOC_IWR68XX_Secure_PartNumber = 0xE3U, /*! IWR68XX_SIL2 nonSecure devices */ SOC_IWR68XX_SIL2_nonSecure_PartNumber = 0xE4U, /*! IWR68XX_AOP nonSecure devices */ SOC_IWR68XX_AOP_nonSecure_PartNumber = 0xF0U, /*! IWR68XX_AOP Secure devices */ SOC_IWR68XX_AOP_Secure_PartNumber = 0xF1U, /*! IWR68XX_AOP_SIL2 nonSecure devices */ SOC_IWR68XX_AOP_SIL2_nonSecure_PartNumber= 0xF2U, /*! AWR68XX_AOP nonSecure devices */ SOC_AWR68XX_AOP_nonSecure_PartNumber = 0xF3U, /*! AWR68XX_AOP Secure devices */ SOC_AWR68XX_AOP_Secure_PartNumber = 0xF4U }SOC_PartNumber; /** * @brief * SOC Warm Reset Type * * @details * The enum defines the supported Warm Reset type for the SOC in software */ typedef enum SOC_WarmResetRequestType_e { /*! MSS Watchdog will trigger SOC reset if it expires. This request type will not immediately trigger a warm reset. Warm reset will happen only when and if MSS watchdog expires */ SOC_WARMRESET_REQUEST_TYPE_ON_MSSWATCHDOG_EXPIRY = 0x1U }SOC_WarmResetRequestType; /** @} */ /*! * @file soc_mpu.h * * @brief * The file has MPU (Memory Protection Unit) APIs for programming the MPU. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @def SOC_MPU_REGION1 * @brief MPU region 1 * * Alias for MPU region 1 */ /** @def SOC_MPU_REGION2 * @brief MPU region 2 * * Alias for MPU region 1 */ /** @def SOC_MPU_REGION3 * @brief MPU region 3 * * Alias for MPU region 3 */ /** @def SOC_MPU_REGION4 * @brief MPU region 4 * * Alias for MPU region 4 */ /** @def SOC_MPU_REGION5 * @brief MPU region 5 * * Alias for MPU region 5 */ /** @def SOC_MPU_REGION6 * @brief MPU region 6 * * Alias for MPU region 6 */ /** @def SOC_MPU_REGION7 * @brief MPU region 7 * * Alias for MPU region 7 */ /** @def SOC_MPU_REGION8 * @brief MPU region 8 * * Alias for MPU region 8 */ /** @def SOC_MPU_REGION9 * @brief MPU region 9 * * Alias for MPU region 9 */ /** @def SOC_MPU_REGION10 * @brief MPU region 10 * * Alias for MPU region 10 */ /** @def SOC_MPU_REGION11 * @brief MPU region 11 * * Alias for MPU region 11 */ /** @def SOC_MPU_REGION12 * @brief MPU region 12 * * Alias for MPU region 12 */ /** @def SOC_MPU_REGION_ENABLE * @brief Enable MPU Region * * Alias for MPU region enable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_REGION_DISABLE * @brief Disable MPU Region * * Alias for MPU region disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION0_DISABLE * @brief Disable MPU Sub Region0 * * Alias for MPU subregion0 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION1_DISABLE * @brief Disable MPU Sub Region1 * * Alias for MPU subregion1 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION2_DISABLE * @brief Disable MPU Sub Region2 * * Alias for MPU subregion2 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION3_DISABLE * @brief Disable MPU Sub Region3 * * Alias for MPU subregion3 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION4_DISABLE * @brief Disable MPU Sub Region4 * * Alias for MPU subregion4 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION5_DISABLE * @brief Disable MPU Sub Region5 * * Alias for MPU subregion5 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /** @def SOC_MPU_SUBREGION6_DISABLE * @brief Disable MPU Sub Region6 * * Alias for MPU subregion6 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister_ */ /** @def SOC_MPU_SUBREGION7_DISABLE * @brief Disable MPU Sub Region7 * * Alias for MPU subregion7 disable. * * @note This should be used as the parameter of the API SOC_MPUSetRegionSizeRegister */ /*! @brief Alignment macro for MPU programming purposes */ /** @enum SOC_MPURegionAccessPermission_e * @brief Alias names for MPU region access permissions * * This enumeration is used to provide alias names for the MPU region access permission: * - SOC_MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and execute * - SOC_MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode and execute * - SOC_MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode and execute * - SOC_MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode and execute * - SOC_MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and execute * - SOC_MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and execute * - SOC_MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode and no execution * - SOC_MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode and no execution * - SOC_MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode and no execution * - SOC_MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode and no execution * - SOC_MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode and no execution * - SOC_MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode and no execution * */ typedef enum SOC_MPURegionAccessPermission_e { SOC_MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access in user mode and execute */ SOC_MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias read/write in privileged mode, no access in user mode and execute */ SOC_MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias read/write in privileged mode, read only in user mode and execute */ SOC_MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias read/write in privileged mode, read/write in user mode and execute */ SOC_MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias read only in privileged mode, no access in user mode and execute */ SOC_MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias read only in privileged mode, read only in user mode and execute */ SOC_MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no access in user mode and no execution */ SOC_MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias read/write in privileged mode, no access in user mode and no execution */ SOC_MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias read/write in privileged mode, read only in user mode and no execution */ SOC_MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias read/write in privileged mode, read/write in user mode and no execution */ SOC_MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias read only in privileged mode, no access in user mode and no execution */ SOC_MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias read only in privileged mode, read only in user mode and no execution */ }SOC_MPURegionAccessPermission; /** @enum SOC_MPURegionType_e * @brief Alias names for MPU region type * * This enumeration is used to provide alias names for the MPU region type: * - SOC_MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable * - SOC_MPU_DEVICE_SHAREABLE Memory type device and sharable * - SOC_MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, no write allocate and non shared * - SOC_MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, no write allocate and shared * - SOC_MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no write allocate and non shared * - SOC_MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no write allocate and shared * - SOC_MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cachable and non shared * - SOC_MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cachable and shared * - SOC_MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, write allocate and non shared * - SOC_MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, write allocate and shared * - SOC_MPU_DEVICE_NONSHAREABLE Memory type device and non sharable */ typedef enum SOC_MPURegionType_e { SOC_MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and sharable */ SOC_MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */ SOC_MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner write-through, no write allocate and non shared */ SOC_MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner write-back, no write allocate and non shared */ SOC_MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner write-through, no write allocate and shared */ SOC_MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner write-back, no write allocate and shared */ SOC_MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner non-cachable and non shared */ SOC_MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner write-back, write allocate and non shared */ SOC_MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner non-cachable and shared */ SOC_MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner write-back, write allocate and shared */ SOC_MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */ }SOC_MPURegionType; /** @enum SOC_MPURegionSize_e * @brief Alias names for MPU region type * * This enumeration is used to provide alias names for the MPU region type: * - SOC_MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable * - SOC_MPU_32_BYTES Memory size in bytes * - SOC_MPU_64_BYTES Memory size in bytes * - SOC_MPU_128_BYTES Memory size in bytes * - SOC_MPU_256_BYTES Memory size in bytes * - SOC_MPU_512_BYTES Memory size in bytes * - SOC_MPU_1_KB Memory size in kB * - SOC_MPU_2_KB Memory size in kB * - SOC_MPU_4_KB Memory size in kB * - SOC_MPU_8_KB Memory size in kB * - SOC_MPU_16_KB Memory size in kB * - SOC_MPU_32_KB Memory size in kB * - SOC_MPU_64_KB Memory size in kB * - SOC_MPU_128_KB Memory size in kB * - SOC_MPU_256_KB Memory size in kB * - SOC_MPU_512_KB Memory size in kB * - SOC_MPU_1_MB Memory size in MB * - SOC_MPU_2_MB Memory size in MB * - SOC_MPU_4_MB Memory size in MB * - SOC_MPU_8_MBv Memory size in MB * - SOC_MPU_16_MB Memory size in MB * - SOC_MPU_32_MB Memory size in MB * - SOC_MPU_64_MB Memory size in MB * - SOC_MPU_128_MB Memory size in MB * - SOC_MPU_256_MB Memory size in MB * - SOC_MPU_512_MB Memory size in MB * - SOC_MPU_1_GB Memory size in GB * - SOC_MPU_2_GB Memory size in GB * - SOC_MPU_4_GB Memory size in GB */ typedef enum SOC_MPURegionSize_e { SOC_MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */ SOC_MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */ SOC_MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */ SOC_MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */ SOC_MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */ SOC_MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */ SOC_MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */ SOC_MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */ SOC_MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */ SOC_MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */ SOC_MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */ SOC_MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */ SOC_MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */ SOC_MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */ SOC_MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */ SOC_MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */ SOC_MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */ SOC_MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */ SOC_MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */ SOC_MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */ SOC_MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */ SOC_MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */ SOC_MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */ SOC_MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */ SOC_MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */ SOC_MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */ SOC_MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */ SOC_MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */ }SOC_MPURegionSize; /* SOC MPU configuration APIs */ /** @fn void SOC_MPUInit(void) * @brief Initialize MPU * * This function initializes memory protection unit. */ void SOC_MPUInit(void); /** @fn void SOC_MPUEnable(void) * @brief Enable MPU * * This function enables memory protection unit. */ void SOC_MPUEnable(void); /** @fn void SOC_MPUDisable(void) * @brief Disable MPU * * This function disables memory protection unit. */ void SOC_MPUDisable(void); /** @fn void SOC_MPUEnableBackgroundRegion(void) * @brief Enable MPU background region * * This function enables background region of the memory protection unit. */ void SOC_MPUEnableBackgroundRegion(void); /** @fn void SOC_MPUDisableBackgroundRegion(void) * @brief Disable MPU background region * * This function disables background region of the memory protection unit. */ void SOC_MPUDisableBackgroundRegion(void); /** @fn uint32_t SOC_MPUGetNumberOfRegions(void) * @brief Returns number of implemented MPU regions * @return Number of implemented MPU regions * * This function returns the number of implemented MPU regions. */ uint32_t SOC_MPUGetNumberOfRegions(void); /** @fn uint32_t SOC_MPUAreRegionsSeparate(void) * @brief Returns the type of the implemented MPU regions * @return MPU type of regions * * This function returns 0 when MPU regions are of type unified otherwise regions are of type separate. */ uint32_t SOC_MPUAreRegionsSeparate(void); /** @fn void SOC_MPUSetRegion(uint32_t region) * @brief Set MPU region number * @param[in] region Region number: SOC_MPU_REGION1..SOC_MPU_REGION12 * * This function selects one of the implemented MPU regions. */ void SOC_MPUSetRegion(uint32_t region); /** @fn uint32_t SOC_MPUGetRegion(void) * @brief Returns the currently selected MPU region * @return MPU region number * * This function returns currently selected MPU region number. */ uint32_t SOC_MPUGetRegion(void); /** @fn void SOC_MPUSetRegionBaseAddress(uint32_t address) * @brief Set base address of currently selected MPU region * @param[in] address Base address of the MPU region * @note The base address must always aligned with region size * * This function sets the base address of currently selected MPU region. */ void SOC_MPUSetRegionBaseAddress(uint32_t address); /** @fn uint32_t SOC_MPUGetRegionBaseAddress(void) * @brief Returns base address of currently selected MPU region * @return Current base address of selected MPU region * * This function returns the base address of currently selected MPU region. */ uint32_t SOC_MPUGetRegionBaseAddress(void); /** @fn void SOC_MPUSetRegionTypeAndPermission(uint32_t type, uint32_t permission) * @brief Set type of currently selected MPU region * @param[in] type Region Type * - SOC_MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and sharable * - SOC_MPU_DEVICE_SHAREABLE : Memory type device and sharable * - SOC_MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and inner write-through, no write allocate and non shared * - SOC_MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and inner write-back, no write allocate and non shared * - SOC_MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and inner write-through, no write allocate and shared * - SOC_MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and inner write-back, no write allocate and shared * - SOC_MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and inner non-cachable and non shared * - SOC_MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and inner write-back, write allocate and non shared * - SOC_MPU_NORMAL_OINC_SHARED : Memory type normal outer and inner non-cachable and shared * - SOC_MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and inner write-back, write allocate and shared * - SOC_MPU_DEVICE_NONSHAREABLE : Memory type device and non sharable * * @param[in] permission Region Access permission * - SOC_MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged mode, no access in user mode and execute * - SOC_MPU_PRIV_RW_USER_NA_EXEC : Alias read/write in privileged mode, no access in user mode and execute * - SOC_MPU_PRIV_RW_USER_RO_EXEC : Alias read/write in privileged mode, read only in user mode and execute * - SOC_MPU_PRIV_RW_USER_RW_EXEC : Alias read/write in privileged mode, read/write in user mode and execute * - SOC_MPU_PRIV_RO_USER_NA_EXEC : Alias read only in privileged mode, no access in user mode and execute * - SOC_MPU_PRIV_RO_USER_RO_EXEC : Alias read only in privileged mode, read only in user mode and execute * - SOC_MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged mode, no access in user mode and no execution * - SOC_MPU_PRIV_RW_USER_NA_NOEXEC : Alias read/write in privileged mode, no access in user mode and no execution * - SOC_MPU_PRIV_RW_USER_RO_NOEXEC : Alias read/write in privileged mode, read only in user mode and no execution * - SOC_MPU_PRIV_RW_USER_RW_NOEXEC : Alias read/write in privileged mode, read/write in user mode and no execution * - SOC_MPU_PRIV_RO_USER_NA_NOEXEC : Alias read only in privileged mode, no access in user mode and no execution * - SOC_MPU_PRIV_RO_USER_RO_NOEXEC : Alias read only in privileged mode, read only in user mode and no execution * * This function sets the type of currently selected MPU region. */ void SOC_MPUSetRegionTypeAndPermission(uint32_t type, uint32_t permission); /** @fn uint32_t SOC_MPUGetRegionType(void) * @brief Returns the type of currently selected MPU region * @return Current type of selected MPU region * * This function returns the type of currently selected MPU region. */ uint32_t SOC_MPUGetRegionType(void); /** @fn uint32_t SOC_MPUGetRegionPermission(void) * @brief Returns permission of currently selected MPU region * @return Current type of selected MPU region * * This function returns permission of currently selected MPU region. */ uint32_t SOC_MPUGetRegionPermission(void); /** @fn void SOC_MPUSetRegionSizeRegister(uint32_t value) * @brief Set MPU region size register value * @param[in] value Value to be written in the MPU Region Size and Enable register * * This function sets MPU region size register value. * * Sample usuage: * SOC_MPUSetRegion(SOC_MPUREGION5); * SOC_MPUSetRegionSizeRegister(SOC_MPU_REGION_ENABLE | SOC_MPU_16_KB | SOC_MPU_SUBREGION3_DISABLE | SOC_MPU_SUBREGION4_DISABLE); */ void SOC_MPUSetRegionSizeRegister(uint32_t value); /** * @file soc_xwr18xx.h * * @brief * This is the header file for the XWR18XX specific definitions needed by * SOC driver. * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @brief * Enumeration for system peripheral module id * * @details * The enumeration defines the system peripheral module id to be used to * configure clock, memory initialization etc. */ typedef enum SOC_ModuleId_e { /** * @brief * DCAN module */ SOC_MODULE_DCAN = 1U, /** * @brief * DMA module */ SOC_MODULE_DMA, /** * @brief * DMA2 module */ SOC_MODULE_DMA2, /** * @brief * MCAN module */ SOC_MODULE_MCAN, /** * @brief * QSPI module */ SOC_MODULE_QSPI, /** * @brief * SPIA module */ SOC_MODULE_SPIA, /** * @brief * SPIB module */ SOC_MODULE_SPIB, /** * @brief * RadarSS (BSS) */ SOC_MODULE_BSS, /** * @brief * CBUFF module */ SOC_MODULE_CBUFF, /** * @brief * Chirp Info (CQ) module */ SOC_MODULE_CQ, /** * @brief * LVDS module */ SOC_MODULE_LVDS }SOC_ModuleId; /******************************************************************************************************* * SOC Driver platform specific Exported APIs: *******************************************************************************************************/ extern int32_t SOC_enableHWA(SOC_Handle handle, int32_t* errCode); /* These functions are exported for use by the mmWave module. */ extern int32_t SOC_isMMWaveMSSOperational(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_setMMWaveMSSLinkState(SOC_Handle handle, uint8_t state, int32_t* errCode); extern int32_t SOC_isMMWaveDSSOperational(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_setMMWaveDSSLinkState(SOC_Handle handle, uint8_t state, int32_t* errCode); extern int32_t SOC_setMSSLinkState(SOC_Handle handle, uint8_t state, int32_t* errCode); extern int32_t SOC_isMSSOperational(SOC_Handle handle, int32_t* errCode); extern uint32_t SOC_getMSSVCLKFrequency(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_setDSSLinkState(SOC_Handle handle, uint8_t state, int32_t* errCode); extern int32_t SOC_isDSSOperational(SOC_Handle handle, int32_t* errCode); /******************************************************************************************************* * SOC Driver Exported API: * (these are APIs common across all platforms. Platform specific apis are in include/soc_.h *******************************************************************************************************/ extern SOC_Handle SOC_init(SOC_Cfg* ptrCfg, int32_t* errCode); extern int32_t SOC_ungateClock(SOC_Handle handle, SOC_ModuleId module, int32_t* errCode); extern int32_t SOC_gateClock(SOC_Handle handle, SOC_ModuleId module, int32_t* errCode); extern int32_t SOC_unhaltBSS(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_haltBSS(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_enableLVDS(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_SPIOutputCtrl (SOC_Handle handle, uint8_t spiInst, uint8_t enable, int32_t* errCode); extern int32_t SOC_waitBSSPowerUp(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_deinit(SOC_Handle handle, int32_t* errCode); extern SOC_SysIntListenerHandle SOC_registerSysIntListener(SOC_Handle handle, SOC_SysIntListenerCfg* ptrListenerCfg, int32_t* errCode); extern int32_t SOC_deregisterSysIntListener(SOC_Handle handle, uint32_t systemInterrupt, SOC_SysIntListenerHandle listenerHandle, int32_t* errCode); extern uint32_t SOC_translateAddress(uint32_t inAddr, SOC_TranslateAddr_Dir direction, int32_t* errCode); extern int32_t SOC_setPeripheralClock( SOC_Handle handle, SOC_ModuleId module, SOC_PeripheralClkSource clkSource, uint8_t clkDivisor, int32_t* errCode); extern int32_t SOC_initPeripheralRam(SOC_Handle handle, SOC_ModuleId module, int32_t* errCode); extern void SOC_microDelay (uint32_t delayInMircoSecs); extern int32_t SOC_triggerWarmReset(SOC_Handle handle, SOC_WarmResetRequestType resetRequestType, int32_t* errCode); extern int32_t SOC_enableWatchdog(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_disableWatchdog(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_getDevicePartNumber(SOC_Handle handle, SOC_PartNumber *devicePartNum, int32_t* errCode); extern double SOC_getDeviceRFFreqScaleFactor(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_softReset(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_isSecureDevice(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_hasDSPCore(SOC_Handle handle, int32_t* errCode); extern int32_t SOC_controlSecureFirewall(SOC_Handle handle, uint32_t firewallModulesBitmap, uint8_t control, int32_t* errCode); extern int32_t SOC_resetDMA(SOC_Handle handle, int32_t* errCode); /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @file esm.h * * @brief ESM driver interface * */ /** @mainpage ESM Driver * * The ESM driver provides APIs to configure and handle errors coming from the ESM H/W module * * The ESM header file should be included in an application as follows: * @code * #include * @endcode * * ## Initializing the driver # * The ESM Driver is initialized using the #ESM_init. * None of the ESM API can be used without invoking * this API.
* **Note**: If you using TI RTOS, then ESM errors are cleared before * entering main and this flag can be set to 0. For any other RTOS, check the * the RTOS implementation or set this flag to 1 * * ## Using the driver # * Following is a psuedo code for using the ESM driver * * @code * ESM_init(0); //ClearErrors is set to 0 i.e. false * @endcode * * ## Handling Interrupts on MSS# * The ESM drivers when run on R4F, registers for high priority FIQ to handle the MSS ESM errors. * When ESM errors occurs on DSS, the MSS is notified via a Group2 error signal. The ESM driver * registers for low priority IRQ to handle these errors. * * ## Handling Interrupts on DSS# * The DSS ESM errors have to be unmasked for them to generate an NMI. Note: This is applicable for xWR16xx/xWR18xx/xWR68xx DSS only. * The API SOC_configureDSSESMMask is provided. Drivers/Applications will have to unmask the bits for the error * signals it is interested in. e.g., Watchdog driver internally unmasks the watchdog expiry NMI * error bits to generate the NMI. * * The DSS ESM errors generate a NMI that is first captured by the RTOS NMI exception handler. * Hence applications have to populate the NMI exception handler to use the ESM driver's high * priority FIQ processing API in the .cfg file. * * @code * Exception.nmiHook = "&ESM_highpriority_FIQ"; * @endcode * ## Registering the notifiers # * The application can register callback functions for the ESM errors that need additional handling. One * such example is the watch dog timeout on the DSS. * When the watchdog timeout causes a NMI to occur on DSS, that event inturn generates a group1 ESM error * on the MSS. The application can register a callback using the ESM notifier to handle these errors. * * ## Instrumentation # * Uses DebugP_log functions for debug messages * * ## Hardware Register Map # * The hardware register map used by this driver can be found at include/reg_esm.h * * ============================================================================ */ /** @defgroup ESM_DRIVER_EXTERNAL_FUNCTION ESM Driver External Functions @ingroup ESM_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup ESM_DRIVER_EXTERNAL_DATA_STRUCTURE ESM Driver External Data Structures @ingroup ESM_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup ESM_DRIVER_ERROR_CODE ESM Driver Error Codes @ingroup ESM_DRIVER @brief * The section has a list of all the error codes which are generated by the ESM Driver * module */ /** @addtogroup ESM_DRIVER_ERROR_CODE * * @brief * Base error code for the ESM module is defined in the * \include ti/common/mmwave_error.h * @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Operation cannot be done as ESM_init is not done. */ /** * @brief Error Code: Operation cannot be done as ESM_init is already done and re-init is not permitted */ /** * @brief Error Code: Out of memory */ /** @}*/ /** @addtogroup CAN_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /*! * @brief ESM module handle returned by the ESM_init() API call. */ typedef void* ESM_Handle; /** * @brief * Callback function which is invoked by the ESM module if a notify function is registered * using the ESM_registerNotifier() API. * * @param[in] arg * Argument passed back when the Notify function is invoked. * * @retval * Not applicable */ typedef void (*ESM_CallBack)(void* arg); /*! * @brief * Parameters used to register the ESM notify function to handle * Group1 and Group2 errors. The notify function will be invoked post * the ESM FIQ interrupt handler processing. */ typedef struct ESM_NotifyParams_t { /*! Group number to which the following error number belongs. */ uint32_t groupNumber; /*! Error number for which the notify function is registered. */ uint32_t errorNumber; /*! Argument passed back when the Notify function is invoked. */ void* arg; /*! Notify function called by the ESM driver. */ ESM_CallBack notify; } ESM_NotifyParams; /** @}*/ /** @addtogroup ESM_DRIVER_EXTERNAL_FUNCTION * * @brief * External APIs for ESM driver * @{ */ /** @brief Function intializes the ESM driver * * @param[in] bClearErrors: boolean value to indicate if old ESM pending errors should be cleared or not * value = 0: do not clear * value = 1: clear all ESM group errors * hint: If you using TI RTOS, then ESM errors are cleared before * entering main and this flag can be set to 0. For any other RTOS, check the * the RTOS implementation or set this flag to 1 * * @return Success - Handle to the ESM Driver * Error - NULL * */ extern ESM_Handle ESM_init(uint8_t bClearErrors); /** @fn int32_t ESM_close(void) * @brief Close the ESM driver * * @param[in] handle: Handle to the ESM Driver * * * @return Value < 0 - in case of error * Value > 0 - Success * */ extern int32_t ESM_close(ESM_Handle handle); /** @brief Register the notifers the ESM module will call back if error interrupt is detected. * * @param[in] handle: Handle to the ESM Driver. * * @param[in] params: Notifier error number and callback function. * * @param[out] errCode * Error code populated on error. * * @return Success - Notifier index. Used when deregistering the notifier. * Error - ESM Error code * */ extern int32_t ESM_registerNotifier(ESM_Handle handle, ESM_NotifyParams* params, int32_t* errCode); /** @brief Deregister the ESM notifers. * * @param[in] handle: Handle to the ESM Driver. * * @param[in] notifyIndex: Notifier index returned when the notifier was registered. * * @param[out] errCode * Error code populated on error. * * @return Success - 0 * Error - ESM Error code * */ extern int32_t ESM_deregisterNotifier(ESM_Handle handle, int32_t notifyIndex, int32_t* errCode); /** @}*/ /** * @file crc.h * * @brief * This is the header file for the CRC driver which exposes the * data structures and exported API which can be used by the * applications to use the CRC driver. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage CRC Driver * * The CRC Driver allows the calculation of the CRC on a specified data. * * The CRC header file should be included in an application as follows: * @code #include @endcode * * The crc/include/reg_crc.h has the register layer definitons for the * CRC Module. * * ## Opening the driver # * Once the CRC Driver has been initialized; the CRC Driver instance can be opened * using the #CRC_open. The helper function #CRC_initConfigParams can be used to * populate the default parameters * * ## Transaction Id # * Each driver requires access to a unique transaction identifier before it can * start using the driver. Transaction identifiers ensure that if the CRC Driver * instance is shared between multiple threads the usage from one thread does not * corrupt the usage from another thread. * * Use the #CRC_getTransactionId to get a unique transaction identifer. On success * the driver is marked as owned and belongs to the callee. The function can fail * with an error code CRC_EINUSE to indicate the driver belongs to another enrity * and cannot be used right now. * * Transaction identifiers are released on a call to #CRC_getSignature when the computed * CRC signature is passed back to the callee *OR* on the #CRC_cancelSignature when * the callee is no longer interested in calculating the CRC operation. * * ## Using the driver # * * As mentioned above a successful call to #CRC_getTransactionId will return a unique * transaction id. Applications can then invoke the #CRC_computeSignature API from 1 to N * times passing different data buffers over which the CRC is to be computed. The following * pseudo code reflects the API usage:- * * @code // Acquire a unique transaction identifer status = CRC_getTransactionId (crcDriverHandle, &transId, ...) if (status == 0) { // Successfully retreived a transaction id. We own the CRC // driver now! // Perform signature computation for Data Buffer-1 sigGenCfg.transactionId = transId; sigGenCfg.ptrData = &data_buffer1[0]; sigGenCfg.dataLen = 128; CRC_computeSignature (crcDriverHandle, ) ... // Perform signature computation for Data Buffer-2 sigGenCfg.transactionId = transId; sigGenCfg.ptrData = &data_buffer2[0]; sigGenCfg.dataLen = 512; CRC_computeSignature (crcDriverHandle, ) ... // Get the CRC Signature. This will also release the transaction identifer CRC_getSignature (crcDriverHandle, transId, &crc, ...) } @endcode * * The results of the CRC signature can be retreived using the #CRC_getSignature API. * This will also release the transaction identifier and another user of the CRC Driver * can start using the driver now. * * It is also possible to cancel requests for CRC signature generation by using the * #CRC_cancelSignature API. The API will also release the transaction identifer. */ /** @defgroup CRC_DRIVER CRC Driver */ /** @defgroup CRC_DRIVER_EXTERNAL_FUNCTION CRC Driver External Functions @ingroup CRC_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup CRC_DRIVER_EXTERNAL_DATA_STRUCTURE CRC Driver External Data Structures @ingroup CRC_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup CRC_DRIVER_ERROR_CODE CRC Driver Error Codes @ingroup CRC_DRIVER @brief * The section has a list of all the error codes which are generated by the CRC Driver * module */ /** @defgroup CRC_DRIVER_INTERNAL_FUNCTION CRC Driver Internal Functions @ingroup CRC_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup CRC_DRIVER_INTERNAL_DATA_STRUCTURE CRC Driver Internal Data Structures @ingroup CRC_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the CRC module. */ /** @addtogroup CRC_DRIVER_ERROR_CODE * Base error code for the CRC module is defined in the * \include ti/common/mmwave_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Operation cannot be implemented because the CRC driver * is in use */ /** @} */ /** @addtogroup CRC_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief * CRC Driver Handle */ typedef void* CRC_Handle; /** * @brief * CRC Channel * * @details * Enumeration which describes the CRC channel numbers which are available */ typedef enum CRC_Channel_e { /** * @brief Channel-1 */ CRC_Channel_CH1 = 0x1, /** * @brief Channel-2 */ CRC_Channel_CH2 }CRC_Channel; /** * @brief * CRC Operational Mode * * @details * Enumeration which describes the operational mode. */ typedef enum CRC_Operational_Mode_e { /** * @brief CRC channel is operating in FULL CPU Mode. The CPU is * responsible for the data pattern tranfers and signature verification */ CRC_Operational_Mode_FULL_CPU = 0x1 }CRC_Operational_Mode; /** * @brief * CRC Type * * @details * Enumeration which describes the different CRC polynomials which * are supported by the CRC driver. */ typedef enum CRC_Type_e { /** * @brief CCITT */ CRC_Type_16BIT = 0x1, /** * @brief Ethernet */ CRC_Type_32BIT, /** * @brief ISO 3309 */ CRC_Type_64BIT }CRC_Type; /** * @brief * CRC Data Length * * @details * Enumeration which describes the data lengths which are supported by * the CRC Driver. */ typedef enum CRC_DataLen_e { /** * @brief 16-bit */ CRC_DataLen_16_BIT = 1, /** * @brief 32-bit */ CRC_DataLen_32_BIT, /** * @brief 64-bit */ CRC_DataLen_64_BIT }CRC_DataLen; /** * @brief * Bit Swapping * * @details * Enumeration which describes the supported bit swapping modes */ typedef enum CRC_BitSwap_t { /** * @brief Most Significant Bit is first */ CRC_BitSwap_MSB = 1, /** * @brief Least Significant Bit is first */ CRC_BitSwap_LSB }CRC_BitSwap; /** * @brief * Byte Swapping * * @details * Enumeration which describes the supported byte swapping modes */ typedef enum CRC_ByteSwap_t { /** * @brief Byte swap is disabled */ CRC_ByteSwap_DISABLED = 1, /** * @brief Byte swap is enabled */ CRC_ByteSwap_ENABLED }CRC_ByteSwap; /** * @brief * CRC Configuration * * @details * The structure describes the configuration information which is needed * to open the handle to the CRC module. */ typedef struct CRC_Config_t { /** * @brief CRC Channel number */ CRC_Channel channel; /** * @brief Operational Mode */ CRC_Operational_Mode mode; /** * @brief CRC Polynomial type */ CRC_Type type; /** * @brief CRC Bit Swapping mode */ CRC_BitSwap bitSwap; /** * @brief CRC Byte Swapping mode */ CRC_ByteSwap byteSwap; /** * @brief Data Length */ CRC_DataLen dataLen; }CRC_Config; /** * @brief * CRC signature generation configuration * * @details * The structure describes the configuration which needs to be provided * to generate the signature. */ typedef struct CRC_SigGenCfg_t { /** * @brief Transaction identifier which has been allocated * @sa CRC_getTransactionId */ uint32_t transactionId; /** * @brief Pointer to the data buffer for which the CRC is to be * computed */ uint8_t* ptrData; /** * @brief Data buffer length (in bytes) */ uint32_t dataLen; }CRC_SigGenCfg; /** @} */ /******************************************************************************************************* * CRC Exported API: *******************************************************************************************************/ extern CRC_Handle CRC_open (const CRC_Config* ptrCRCCfg, int32_t* errCode); extern int32_t CRC_close (CRC_Handle crcHandle, int32_t* errCode); extern int32_t CRC_getTransactionId(CRC_Handle crcHandle, uint32_t* transactionId, int32_t* errCode); extern int32_t CRC_computeSignature(CRC_Handle crcHandle, CRC_SigGenCfg* ptrSigGenCfg, int32_t* errCode); extern int32_t CRC_getSignature (CRC_Handle crcHandle, uint32_t transactionId, uint64_t* ptrSignature, int32_t* errCode); extern int32_t CRC_cancelSignature (CRC_Handle crcHandle, uint32_t transactionId, int32_t* errCode); extern void CRC_initConfigParams(CRC_Config* ptrCRCCfg); /* * Copyright (c) 2015-2016, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage GPIO Driver * * The GPIO header file should be included in an application as follows: * @code * #include * @endcode * * The drivers/gpio/include/reg_gio.h has the register layer definitons for the * GPIO Module. * * # Operation # * * The GPIO module allows you to manage General Purpose I/O pins via * simple and portable APIs. * * The application is required to call GPIO_init() before invoking any other * driver API. * * Asserts are used to verify that the driver has been initialized and * to validate pin indexes within the various APIs. * * Each platform will have its own GPIO Index which are defined in the * corresponding platform header file. For example: Please refer to the * drivers/gpio/include/gpio_xwr14xx.h for the GPIO pins available on the * XWR14xx platform. */ /** @defgroup GPIO_DRIVER GPIO Driver */ /** @defgroup GPIO_DRIVER_EXTERNAL_FUNCTION GPIO Driver External Functions @ingroup GPIO_DRIVER @brief * The section has a list of all external API which are exposed to the applications */ /** @defgroup GPIO_DRIVER_EXTERNAL_DATA_STRUCTURE GPIO Driver External Data structures @ingroup GPIO_DRIVER @brief * The section has a list of all external data structures which are exposed to the * application. */ /** @defgroup GPIO_DRIVER_INTERNAL_DATA_STRUCTURE GPIO Driver Internal Data Structures @ingroup GPIO_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the GPIO module. */ /** @defgroup GPIO_DRIVER_INTERNAL_FUNCTION GPIO Driver Internal Functions @ingroup GPIO_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** * @file gpio_xwr18xx.h * * @brief * GPIO Platform specific definitions for XWR18xx * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file gpio_internal.h * * @brief * This is the internal header file used by the GPIO Driver. The * file is NOT exposed to the application developers and should * not be directly included. * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Copyright (c) 2015-2016, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage GPIO Driver * * The GPIO header file should be included in an application as follows: * @code * #include * @endcode * * The drivers/gpio/include/reg_gio.h has the register layer definitons for the * GPIO Module. * * # Operation # * * The GPIO module allows you to manage General Purpose I/O pins via * simple and portable APIs. * * The application is required to call GPIO_init() before invoking any other * driver API. * * Asserts are used to verify that the driver has been initialized and * to validate pin indexes within the various APIs. * * Each platform will have its own GPIO Index which are defined in the * corresponding platform header file. For example: Please refer to the * drivers/gpio/include/gpio_xwr14xx.h for the GPIO pins available on the * XWR14xx platform. */ /** @defgroup GPIO_DRIVER GPIO Driver */ /** @defgroup GPIO_DRIVER_EXTERNAL_FUNCTION GPIO Driver External Functions @ingroup GPIO_DRIVER @brief * The section has a list of all external API which are exposed to the applications */ /** @defgroup GPIO_DRIVER_EXTERNAL_DATA_STRUCTURE GPIO Driver External Data structures @ingroup GPIO_DRIVER @brief * The section has a list of all external data structures which are exposed to the * application. */ /** @defgroup GPIO_DRIVER_INTERNAL_DATA_STRUCTURE GPIO Driver Internal Data Structures @ingroup GPIO_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the GPIO module. */ /** @defgroup GPIO_DRIVER_INTERNAL_FUNCTION GPIO Driver Internal Functions @ingroup GPIO_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** * @file reg_gio.h * * @brief * This file gives register definitions of MSS_GIO module. * * This file is auto-generated on 8/22/2019. * */ /* * (C) Copyright 2016, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /**************************************************************************************** * INCLUDE FILES ****************************************************************************************/ /** @addtogroup GPIO_DRIVER_INTERNAL_DATA_STRUCTURE @{ */ /* Definition for field RESET in Register GIOGCR */ /* Definition for field NU0 in Register GIOGCR */ /* Definition for field GIOPWDN in Register GIOPWDN */ /* Definition for field NU in Register GIOPWDN */ /* Definition for field GIOINTDET_0 in Register GIOINTDET */ /* Definition for field GIOINTDET_1 in Register GIOINTDET */ /* Definition for field GIOINTDET_2 in Register GIOINTDET */ /* Definition for field GIOINTDET_3 in Register GIOINTDET */ /* Definition for field GIOPOL_0 in Register GIOPOL */ /* Definition for field GIOPOL_1 in Register GIOPOL */ /* Definition for field GIOPOL_2 in Register GIOPOL */ /* Definition for field GIOPOL_3 in Register GIOPOL */ /* Definition for field GIOENASET_0 in Register GIOENASET */ /* Definition for field GIOENASET_1 in Register GIOENASET */ /* Definition for field GIOENASET_2 in Register GIOENASET */ /* Definition for field GIOENASET_3 in Register GIOENASET */ /* Definition for field GIOENACLR_0 in Register GIOENACLR */ /* Definition for field GIOENACLR_1 in Register GIOENACLR */ /* Definition for field GIOENACLR_2 in Register GIOENACLR */ /* Definition for field GIOENACLR_3 in Register GIOENACLR */ /* Definition for field GIOLVLSET_0 in Register GIOLVLSET */ /* Definition for field GIOLVLSET_1 in Register GIOLVLSET */ /* Definition for field GIOLVLSET_2 in Register GIOLVLSET */ /* Definition for field GIOLVLSET_3 in Register GIOLVLSET */ /* Definition for field GIOLVLCLR_0 in Register GIOLVLCLR */ /* Definition for field GIOLVLCLR_1 in Register GIOLVLCLR */ /* Definition for field GIOLVLCLR_2 in Register GIOLVLCLR */ /* Definition for field GIOLVLCLR_3 in Register GIOLVLCLR */ /* Definition for field GIOFLG_0 in Register GIOFLG */ /* Definition for field GIOFLG_1 in Register GIOFLG */ /* Definition for field GIOFLG_2 in Register GIOFLG */ /* Definition for field GIOFLG_3 in Register GIOFLG */ /* Definition for field GIOOFFA in Register GIOOFFA */ /* Definition for field NU1 in Register GIOOFFA */ /* Definition for field GIOOFFB in Register GIOOFFB */ /* Definition for field NU2 in Register GIOOFFB */ /* Definition for field GIOEMUA in Register GIOEMUA */ /* Definition for field NU3 in Register GIOEMUA */ /* Definition for field GIOEMUB in Register GIOEMUB */ /* Definition for field NU4 in Register GIOEMUB */ /* Definition for field GIODIRA in Register GIODIRA */ /* Definition for field NU5 in Register GIODIRA */ /* Definition for field GIODINA in Register GIODINA */ /* Definition for field NU11 in Register GIODINA */ /* Definition for field GIODOUTA in Register GIODOUTA */ /* Definition for field NU17 in Register GIODOUTA */ /* Definition for field GIODSETA in Register GIOSETA */ /* Definition for field NU23 in Register GIOSETA */ /* Definition for field GIODCLRA in Register GIOCLRA */ /* Definition for field NU29 in Register GIOCLRA */ /* Definition for field GIOPDRA in Register GIOPDRA */ /* Definition for field NU35 in Register GIOPDRA */ /* Definition for field GIOPULDISA in Register GIOPULDISA */ /* Definition for field NU in Register GIOPULDISA */ /* Definition for field GIOPSLA in Register GIOPSLA */ /* Definition for field NU35 in Register GIOPSLA */ /* Definition for field GIODIRB in Register GIODIRB */ /* Definition for field NU6 in Register GIODIRB */ /* Definition for field GIODINB in Register GIODINB */ /* Definition for field NU12 in Register GIODINB */ /* Definition for field GIODOUTB in Register GIODOUTB */ /* Definition for field NU18 in Register GIODOUTB */ /* Definition for field GIODSETB in Register GIOSETB */ /* Definition for field NU24 in Register GIOSETB */ /* Definition for field GIODCLRB in Register GIOCLRB */ /* Definition for field NU30 in Register GIOCLRB */ /* Definition for field GIOPDRB in Register GIOPDRB */ /* Definition for field NU36 in Register GIOPDRB */ /* Definition for field GIOPULDISB in Register GIOPULDISB */ /* Definition for field NU36 in Register GIOPULDISB */ /* Definition for field GIOPSLB in Register GIOPSLB */ /* Definition for field NU36 in Register GIOPSLB */ /* Definition for field GIODIRC in Register GIODIRC */ /* Definition for field NU7 in Register GIODIRC */ /* Definition for field GIODINC in Register GIODINC */ /* Definition for field NU13 in Register GIODINC */ /* Definition for field GIODOUTC in Register GIODOUTC */ /* Definition for field NU19 in Register GIODOUTC */ /* Definition for field GIODSETC in Register GIOSETC */ /* Definition for field NU25 in Register GIOSETC */ /* Definition for field GIODCLRC in Register GIOCLRC */ /* Definition for field NU31 in Register GIOCLRC */ /* Definition for field GIOPDRC in Register GIOPDRC */ /* Definition for field NU37 in Register GIOPDRC */ /* Definition for field GIOPULDISC in Register GIOPULDISC */ /* Definition for field NU37 in Register GIOPULDISC */ /* Definition for field GIOPSLC in Register GIOPSLC */ /* Definition for field NU37 in Register GIOPSLC */ /* Definition for field GIODIRD in Register GIODIRD */ /* Definition for field NU8 in Register GIODIRD */ /* Definition for field GIODIND in Register GIODIND */ /* Definition for field NU14 in Register GIODIND */ /* Definition for field GIODOUTD in Register GIODOUTD */ /* Definition for field NU20 in Register GIODOUTD */ /* Definition for field GIODSETD in Register GIOSETD */ /* Definition for field NU26 in Register GIOSETD */ /* Definition for field GIODCLRD in Register GIOCLRD */ /* Definition for field NU32 in Register GIOCLRD */ /* Definition for field GIOPDRD in Register GIOPDRD */ /* Definition for field NU38 in Register GIOPDRD */ /* Definition for field GIOPULDISD in Register GIOPULDISD */ /* Definition for field NU38 in Register GIOPULDISD */ /* Definition for field GIOPSLD in Register GIOPSLD */ /* Definition for field NU38 in Register GIOPSLD */ /* Definition for field GIODIRE in Register GIODIRE */ /* Definition for field NU9 in Register GIODIRE */ /* Definition for field GIODINE in Register GIODINE */ /* Definition for field NU15 in Register GIODINE */ /* Definition for field GIODOUTE in Register GIODOUTE */ /* Definition for field NU21 in Register GIODOUTE */ /* Definition for field GIODSETE in Register GIOSETE */ /* Definition for field NU27 in Register GIOSETE */ /* Definition for field GIODCLRE in Register GIOCLRE */ /* Definition for field NU33 in Register GIOCLRE */ /* Definition for field GIOPDRE in Register GIOPDRE */ /* Definition for field NU39 in Register GIOPDRE */ /* Definition for field GIOPULDISE in Register GIOPULDISE */ /* Definition for field NU39 in Register GIOPULDISE */ /* Definition for field GIOPSLE in Register GIOPSLE */ /* Definition for field NU39 in Register GIOPSLE */ /* Definition for field GIODIRF in Register GIODIRF */ /* Definition for field NU10 in Register GIODIRF */ /* Definition for field GIODINF in Register GIODINF */ /* Definition for field NU16 in Register GIODINF */ /* Definition for field GIODOUTF in Register GIODOUTF */ /* Definition for field NU22 in Register GIODOUTF */ /* Definition for field GIODSETF in Register GIOSETF */ /* Definition for field NU28 in Register GIOSETF */ /* Definition for field GIODCLRF in Register GIOCLRF */ /* Definition for field NU34 in Register GIOCLRF */ /* Definition for field GIOPDRF in Register GIOPDRF */ /* Definition for field NU40 in Register GIOPDRF */ /* Definition for field GIOPULDISF in Register GIOPULDISF */ /* Definition for field NU40 in Register GIOPULDISF */ /* Definition for field GIOPSLF in Register GIOPSLF */ /* Definition for field NU40 in Register GIOPSLF */ /* Definition for field GIODIRG in Register GIODIRG */ /* Definition for field NU9 in Register GIODIRG */ /* Definition for field GIODING in Register GIODING */ /* Definition for field NU15 in Register GIODING */ /* Definition for field GIODOUTG in Register GIODOUTG */ /* Definition for field NU21 in Register GIODOUTG */ /* Definition for field GIODSETG in Register GIOSETG */ /* Definition for field NU27 in Register GIOSETG */ /* Definition for field GIODCLRG in Register GIOCLRG */ /* Definition for field NU33 in Register GIOCLRG */ /* Definition for field GIOPDRG in Register GIOPDRG */ /* Definition for field NU39 in Register GIOPDRG */ /* Definition for field GIOPULDISG in Register GIOPULDISG */ /* Definition for field NU39 in Register GIOPULDISG */ /* Definition for field GIOPSLG in Register GIOPSLG */ /* Definition for field NU39 in Register GIOPSLG */ /* Definition for field GIODIRH in Register GIODIRH */ /* Definition for field NU10 in Register GIODIRH */ /* Definition for field GIODINH in Register GIODINH */ /* Definition for field NU16 in Register GIODINH */ /* Definition for field GIODOUTH in Register GIODOUTH */ /* Definition for field NU22 in Register GIODOUTH */ /* Definition for field GIODSETH in Register GIOSETH */ /* Definition for field NU28 in Register GIOSETH */ /* Definition for field GIODCLRH in Register GIOCLRH */ /* Definition for field NU34 in Register GIOCLRH */ /* Definition for field GIOPDRH in Register GIOPDRH */ /* Definition for field NU40 in Register GIOPDRH */ /* Definition for field GIOPULDISH in Register GIOPULDISH */ /* Definition for field NU40 in Register GIOPULDISH */ /* Definition for field GIOPSLH in Register GIOPSLH */ /* Definition for field NU40 in Register GIOPSLH */ /* Definition for field GIOSRCA in Register GIOSRCA */ /* Definition for field NU35 in Register GIOSRCA */ /* Definition for field GIOSRCB in Register GIOSRCB */ /* Definition for field NU36 in Register GIOSRCB */ /* Definition for field GIOSRCC in Register GIOSRCC */ /* Definition for field NU37 in Register GIOSRCC */ /* Definition for field GIOSRCD in Register GIOSRCD */ /* Definition for field NU38 in Register GIOSRCD */ /* Definition for field GIOSRCE in Register GIOSRCE */ /* Definition for field NU39 in Register GIOSRCE */ /* Definition for field GIOSRCF in Register GIOSRCF */ /* Definition for field NU40 in Register GIOSRCF */ /* Definition for field GIOSRCG in Register GIOSRCG */ /* Definition for field NU39 in Register GIOSRCG */ /* Definition for field GIOSRCH in Register GIOSRCH */ /* Definition for field NU40 in Register GIOSRCH */ /** * @brief * Only Ports A, B are capable of interrupts. * This is a system limit on the GPIO IP Block * for the devices supported so far. */ /** * @brief * This is the maximum number of pins per GPIO port * This is a system limit on the GPIO IP Block. */ /** * @brief * This is the maximum number of interrupts which can be supported. * Only Ports A, B, C and D are capable of interrupts. Also since * each port can have a maximum of 8 pins this is the maximum number * of interrupts which can be supported * * This is a system limit on the GPIO IP Block. */ /** * @brief * This is used to define the number of GPIO ports which are available * and this is device specific. */ /** * @brief * GPIO Port Registers * * @details * This structure defines the register overlay used for each * GPIO Port. */ typedef volatile struct GIOPortRegs_t { uint32_t GIODIR; uint32_t GIODIN; uint32_t GIODOUT; uint32_t GIODSET; uint32_t GIODCLR; uint32_t GIOPDR; uint32_t GIOPULDIS; uint32_t GIOPSL; }GIOPortRegs; /** * @struct GIORegs_t * @brief * Module MSS_GIO Register Definition * @details * This structure is used to access the MSS_GIO module registers. */ /** * @typedef GIORegs * @brief * Module MSS_GIO Register Frame type Definition * @details * This type is used to access the MSS_GIO module registers. */ typedef volatile struct GIORegs_t { uint32_t GIOGCR ; /* Offset = 0x000 */ uint32_t GIOPWDN ; /* Offset = 0x004 */ uint32_t GIOINTDET ; /* Offset = 0x008 */ uint32_t GIOPOL ; /* Offset = 0x00C */ uint32_t GIOENASET ; /* Offset = 0x010 */ uint32_t GIOENACLR ; /* Offset = 0x014 */ uint32_t GIOLVLSET ; /* Offset = 0x018 */ uint32_t GIOLVLCLR ; /* Offset = 0x01C */ uint32_t GIOFLG ; /* Offset = 0x020 */ uint32_t GIOOFFA ; /* Offset = 0x024 */ uint32_t GIOOFFB ; /* Offset = 0x028 */ uint32_t GIOEMUA ; /* Offset = 0x02C */ uint32_t GIOEMUB ; /* Offset = 0x030 */ /* NOTE: Modification done manually. The GPIO Port can be written as a structure * with N elements. The number of elements can be platform specific. This allows * the GPIO driver to work across multiple platforms */ GIOPortRegs portRegs[6U]; uint32_t GIOSRCA ; /* Offset = 0x134 */ uint32_t GIOSRCB ; /* Offset = 0x138 */ uint32_t GIOSRCC ; /* Offset = 0x13C */ uint32_t GIOSRCD ; /* Offset = 0x140 */ uint32_t GIOSRCE ; /* Offset = 0x144 */ uint32_t GIOSRCF ; /* Offset = 0x148 */ uint32_t GIOSRCG ; /* Offset = 0x14C */ uint32_t GIOSRCH ; /* Offset = 0x150 */ } GIORegs; /** @} */ /* END OF REG_GIO_H */ /** @addtogroup GPIO_DRIVER_INTERNAL_DATA_STRUCTURE @{ */ inline void GPIO_DECODE_INDEX(uint8_t index, uint8_t* port, uint8_t* pin); /** * @b Description * @n * Utility function which is used to decode the index provided * to the GPIO exported API into a GPIO Port & Pin which can be * used to program the GPIO registers. * * The implementation of this function and the macro GPIO_CREATE_INDEX * should always be maintained. * * @param[in] index * GPIO Index * @param[out] port * Translated Port * @param[out] pin * Translated Pin * * @retval * Not applicable */ inline void GPIO_DECODE_INDEX(uint8_t index, uint8_t* port, uint8_t* pin) { *port = (index / 8U); *pin = (index % 8U); } /** * @b Description * @n * Helper macro which is used to create a unique index given the GPIO * Port & Pin. * * @param[in] PORT * GPIO Port * @param[in] PIN * GPIO Pin * * @retval * Unique Index */ /** * @brief * GPIO Hardware Attributes * * @details * The structure contains the hardware atrributes which are used * to specify the platform specific configurations. */ typedef struct GPIO_Hw_Attrib_t { /** * @brief Pointer to the GPIO registers */ GIORegs* ptrGPIORegs; /** * @brief Interrupt number associated with the high interrupts */ uint8_t highInterruptNum; /** * @brief Interrupt number associated with the low interrupts */ uint8_t lowInterruptNum; }GPIO_Hw_Attrib; /***************************************************************************** * Extern Platform specific definition *****************************************************************************/ extern GPIO_Hw_Attrib gGPIOHwAtrrib; /** @} */ /*************************************************************************** * GPIO Index for XWR18xx: * - This is the GPIO Index which needs to be passed to the GPIO Driver API ***************************************************************************/ /* Port 0 (A) */ /* Port 1 (B) */ /* Port 2 (C) */ /* Port 3 (D)*/ /* Port 4 (E)*/ /* Port 5 (F) */ /** @addtogroup GPIO_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /*! * @brief GPIO pin configuration settings * * The upper 16 bits of the 32 bit PinConfig is reserved * for pin configuration settings. * * The lower 16 bits are reserved for device-specific * port/pin identifications * * The figures below represent the distribution of the higher * order 32 bits. * * @verbatim Input/Output Field: [Refer to the Input/Output configuration macros] ------------------------------------------ | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ------------------------------------------ Interrupt Fields: [Refer to the Interrupt configuration macros] -------------------------------- | 29 | 28 | 27 | 26 | 25 | 24 | -------------------------------- Internally used [Reserved fields] ------------- | 31 | 30 | ------------- @endverbatim * */ typedef uint32_t GPIO_PinConfig; /*! * @cond NODOC * Internally used configuration bit access macros. */ /* GPIO_CFG_INT_MASK should not include GPIO_CFG_IN_INT_NONE(bit 24) bit to avoid asserts */ /*! @endcond */ /** @name GPIO_PinConfig pin Input/Output configuration macros * @{ * * These macros define the Input/Output properties associated with the GPIO pin. */ /** * @brief Pin is an output. */ /** * @brief Output pin is Open Drain */ /** * @brief Pin is an input. */ /** @} */ /** @name GPIO_PinConfig Interrupt configuration macros * @{ * * These macros define the Interrupt properties associated with the GPIO pin. * Not all GPIO pins have interrupt capability in a given device. */ /** * @brief No Interrupt */ /** * @brief Interrupt on falling edge */ /** * @brief Interrupt on rising edge */ /** * @brief Interrupt on both edges */ /** * @brief Low priority interrupt: Set to 1 for Low Priority Pin interrupt * else the Pin is automatically configured as a High Priority interrupt */ /** @} */ /*! * @brief GPIO callback function type * * @param index GPIO index. This is the same index that * was passed to GPIO_setCallback(). This allows * you to use the same callback function for multiple * GPIO interrupts, by using the index to identify * the GPIO that caused the interrupt. * * \ingroup GPIO_DRIVER_EXTERNAL_DATA_STRUCTURE */ typedef void (*GPIO_CallbackFxn)(uint32_t index); /*! * @brief Clear a GPIO pin interrupt flag * * Clears the GPIO interrupt for the specified index. * Not all GPIO pins have interrupt capability in a given device. * * Note: It is not necessary to call this API within a * callback assigned to a pin. * * @param index GPIO index * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_clearInt(uint32_t index); /*! * @brief Disable a GPIO pin interrupt * Not all GPIO pins have interrupt capability in a given device. * * Disables interrupts for the specified GPIO index. * * @param index GPIO index * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_disableInt(uint32_t index); /*! * @brief Enable a GPIO pin interrupt * * Enables GPIO interrupts for the selected index to occur. * Not all GPIO pins have interrupt capability in a given device. * * Note: Prior to enabling a GPIO pin interrupt, make sure * that a corresponding callback function has been provided. * Use the GPIO_setCallback() API for this purpose at runtime. * Alternatively, the callback function can be statically * configured in the GPIO_CallbackFxn array provided. * * @param index GPIO index * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_enableInt(uint32_t index); /*! * @brief Get the current configuration for a gpio pin * * @param index GPIO index * @param pinConfig Location to store device specific pin * configuration settings * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_getConfig(uint32_t index, GPIO_PinConfig *pinConfig); /*! * @brief Initializes the GPIO module * * @pre This function must also be called before any other GPIO driver APIs. * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_init(void); /*! * @brief Reads the value of a GPIO pin * * The value returned will either be zero or one depending on the * state of the pin. * * @param index GPIO index * * @return 0 or 1, depending on the state of the pin. * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern uint32_t GPIO_read(uint32_t index); /*! * @brief Bind a callback function to a GPIO pin interrupt * * Associate a callback function with a particular GPIO pin interrupt. * * Callbacks can be changed at any time, making it easy to switch between * efficient, state-specific interrupt handlers. * * Note: The callback function is called within the context of an interrupt * handler. * * Note: This API does not enable the GPIO pin interrupt. * Use GPIO_enableInt() and GPIO_disableInt() to enable * and disable the pin interrupt as necessary. * * Note: it is not necessary to call GPIO_clearInt() within a callback. * That operation is performed internally before the callback is invoked. * * @param index GPIO index * @param callback address of the callback function * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_setCallback(uint32_t index, GPIO_CallbackFxn callback); /*! * @brief Configure the gpio pin * * Dynamically configure a gpio pin to a device specific setting. * * For input pins with interrupt configurations, a corresponding interrupt * object will be created as needed. * * @param index GPIO index * @param pinConfig device specific pin configuration settings * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_setConfig(uint32_t index, GPIO_PinConfig pinConfig); /*! * @brief Toggles the current state of a GPIO * * @param index GPIO index * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_toggle(uint32_t index); /*! * @brief Writes the value to a GPIO pin * * @param index GPIO index * @param value must be either 0 or 1 * * \ingroup GPIO_DRIVER_EXTERNAL_FUNCTION */ extern void GPIO_write(uint32_t index, uint32_t value); /** @} */ /* * Copyright (c) 2016, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @file mailbox.h * * @brief Mailbox driver interface * */ /** @mainpage Mailbox Driver * * The Mailbox driver simplifies reading and writing to the Mailbox * peripherals on the board with multiple modes of operation and performance. * These include blocking, non-blocking, callback. * Throughout this document the term local endpoint refers to the subsystem that instantiates the mailbox driver. * The term remote endpoint refers to the subsystem that communicates to the local endpoint through the mailbox instance.\n * The application initializes the Mailbox driver by calling Mailbox_init() and it is then ready to * open a Mailbox instance to a remote endpoint by calling Mailbox_open(). Once the mailbox instance is open, * read and write operations can be performed.\n * * The Mailbox header file should be included in an application as follows: * @code #include @endcode * * The mailbox/include/reg_mailbox.h has the register layer definitions for the * Mailbox Module. * * ## Initializing the driver # * The Mailbox Driver needs to be initialized once per master (MSS or DSS). This is * done using the #Mailbox_init. None of the Mailbox APIs can be used before invoking * this API. * * ## Opening the driver # * Once the Mailbox Driver has been initialized, the Mailbox Driver instance can be opened * using the #Mailbox_open. \n * For XWR14xx: \n * Between MSS<->BSS only one instance of the driver can be opened.\n * Note that the mailbox driver is instantiated in the MSS only. In the BSS, the BSS firmware handles the mailbox operations.\n * For XWR16xx/XWR18xx/XWR68xx: \n * Between MSS<->BSS only one instance of the driver can be opened.\n * Note that the mailbox driver is instantiated in the MSS only. In the BSS, the BSS firmware handles the mailbox operations.\n * Between DSS<->BSS only one instance of the driver can be opened.\n * Note that the mailbox driver is instantiated in the DSS only. In the BSS, the BSS firmware handles the mailbox operations.\n * Between MSS<->DSS multiple instances of the driver can be opened (each instance controls one virtual channel).\n * Note that the mailbox driver is instantiated both in the MSS and DSS.\n * * * Example 1:\n * The example below applies for XWR14xx and XWR16xx/XWR18xx/XWR68xx SoCs.\n * Following is pseudo code for opening the Mailbox driver for MSS to talk to BSS.\n * In this example the mailbox write mode is set to be polling and mailbox read * mode is set to be callback. * * @code * Mbox_Handle handle; int32_t errCode; Mailbox_Config cfg; Mailbox_init(MAILBOX_TYPE_MSS); if(Mailbox_Config_init(&cfg) < 0) { Error: Unable to initialize configuration } cfg.writeMode = MAILBOX_MODE_POLLING; cfg.readMode = MAILBOX_MODE_CALLBACK; cfg.readCallback = myApp_mboxCallbackFxn; handle = Mailbox_open(MAILBOX_TYPE_BSS, &cfg, &errCode); if((handle == NULL) || (errCode != 0)) { Error: Unable to open mailbox between MSS and BSS. } * @endcode * * * Example 2:\n * The example below applies for XWR16xx/XWR18xx/XWR68xx SoC only.\n * Following is pseudo code for opening the Mailbox driver for MSS to talk to DSS.\n * In this example the mailbox write mode is set to be polling and mailbox read * mode is set to be callback. Also, in this example, MSS and DSS applications are using * multi-channels to communicate and the specific channels used in this case have ID * MAILBOX_CH_ID_0 and MAILBOX_CH_ID_1.\n * Note that both endpoints need to use the same ID so that the channels are connected correctly.\n * Note that all mailbox channels are bi-directional. In this example, 2 bi-directional channels * are open to show the configuration of multiple mailbox channels. * * The following code runs on MSS: * * @code * Mbox_Handle handle[2]; int32_t errCode; Mailbox_Config cfg; Mailbox_init(MAILBOX_TYPE_MSS); if(Mailbox_Config_init(&cfg) < 0) { Error: Unable to initialize configuration } cfg.writeMode = MAILBOX_MODE_POLLING; cfg.readMode = MAILBOX_MODE_CALLBACK; cfg.readCallback = myApp_mboxCallbackFxn_MSS_ch0; cfg.chType = MAILBOX_CHTYPE_MULTI; cfg.chId = MAILBOX_CH_ID_0; handle[0] = Mailbox_open(MAILBOX_TYPE_DSS, &cfg, &errCode); if((handle == NULL) || (errCode != 0)) { Error: Unable to open mailbox channel 0 between MSS and DSS. } cfg.writeMode = MAILBOX_MODE_POLLING; cfg.readMode = MAILBOX_MODE_CALLBACK; cfg.readCallback = myApp_mboxCallbackFxn_MSS_ch1; cfg.chType = MAILBOX_CHTYPE_MULTI; cfg.chId = MAILBOX_CH_ID_1; handle[1] = Mailbox_open(MAILBOX_TYPE_DSS, &cfg, &errCode); if((handle == NULL) || (errCode != 0)) { Error: Unable to open mailbox channel 1 between MSS and DSS. } * @endcode * * The following code runs on DSS: * * @code * Mbox_Handle handle[2]; int32_t errCode; Mailbox_Config cfg; Mailbox_init(MAILBOX_TYPE_DSS); if(Mailbox_Config_init(&cfg) < 0) { Error: Unable to initialize configuration } cfg.writeMode = MAILBOX_MODE_POLLING; cfg.readMode = MAILBOX_MODE_CALLBACK; cfg.readCallback = myApp_mboxCallbackFxn_DSS_ch0; cfg.chType = MAILBOX_CHTYPE_MULTI; cfg.chId = MAILBOX_CH_ID_0; handle[0] = Mailbox_open(MAILBOX_TYPE_MSS, &cfg, &errCode); if((handle == NULL) || (errCode != 0)) { Error: Unable to open mailbox channel 0 between DSS and MSS. } cfg.writeMode = MAILBOX_MODE_POLLING; cfg.readMode = MAILBOX_MODE_CALLBACK; cfg.readCallback = myApp_mboxCallbackFxn_DSS_ch1; cfg.chType = MAILBOX_CHTYPE_MULTI; cfg.chId = MAILBOX_CH_ID_1; handle[1] = Mailbox_open(MAILBOX_TYPE_MSS, &cfg, &errCode); if((handle == NULL) || (errCode != 0)) { Error: Unable to open mailbox channel 1 between DSS and MSS. } * @endcode * * ## Writing a message # * Once the Mailbox Driver has been opened, the application can write a message to the remote * endpoint using #Mailbox_write. * * ## Reading a message # * Once the Mailbox Driver has been opened, the application can read a message from the remote * endpoint using #Mailbox_read followed by #Mailbox_readFlush after the message is fully read. * ** @defgroup MAILBOX_DRIVER MAILBOX Driver */ /** @defgroup MAILBOX_DRIVER_EXTERNAL_FUNCTION Mailbox Driver External Functions @ingroup MAILBOX_DRIVER @brief * This section has a list of all the exported API which the application needs to * invoke in order to use the driver */ /** @defgroup MAILBOX_DRIVER_EXTERNAL_DATA_STRUCTURE Mailbox Driver External Data Structures @ingroup MAILBOX_DRIVER @brief * This section has a list of all the data structures which are exposed to the application */ /** @defgroup MAILBOX_DRIVER_ERROR_CODE Mailbox Driver Error Codes @ingroup MAILBOX_DRIVER @brief * This section has a list of all the error codes which are generated by the Mailbox Driver * module */ /** @defgroup MAILBOX_DRIVER_INTERNAL_FUNCTION Mailbox Driver Internal Functions @ingroup MAILBOX_DRIVER @brief * This section has a list of all internal API which are not exposed to the external * application. */ /** @defgroup MAILBOX_DRIVER_INTERNAL_DATA_STRUCTURE Mailbox Driver Internal Data Structures @ingroup MAILBOX_DRIVER @brief * This section has a list of all internal data structures which are used internally * by the Mailbox module. */ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @defgroup SEMAPHOREP_OSAL SemaphoreP OSAL Porting Layer * * @brief Semaphore module for the RTOS Porting Interface * * Semaphores can be counting semaphores or binary semaphores. Counting * semaphores keep track of the number of times the semaphore has been posted * with post functions. This is useful, for example, if you have a group of * resources that are shared between tasks. Such tasks might call pend() to see * if a resource is available before using one. A count of zero for a counting * semaphore denotes that it is not available. A positive count denotes * how many times a SemaphoreP_pend can be called before it is blocked (or * returns SemaphoreP_TIMEOUT). * * Binary semaphores can have only two states: available (count = 1) and * unavailable (count = 0). They can be used to share a single resource * between tasks. They can also be used for a basic signalling mechanism, where * the semaphore can be posted multiple times. Binary semaphores do not keep * track of the count; they simply track whether the semaphore has been posted * or not. * * ============================================================================ */ /** @defgroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION SemaphoreP OSAL External Functions @ingroup SEMAPHOREP_OSAL @brief * The section documents the external API exposed by the OSAL Porting layer. */ /** @defgroup SEMAPHOREP_OSAL_EXTERNAL_DATA_STRUCTURE SemaphoreP OSAL External Data Structures @ingroup SEMAPHOREP_OSAL @brief * The section has a list of all the data structures which are exposed to the application */ /** @addtogroup SEMAPHOREP_OSAL_EXTERNAL_DATA_STRUCTURE @{ */ /*! * @brief Status codes for SemaphoreP APIs */ typedef enum { /*! API completed successfully */ SemaphoreP_OK = 0, /*! API failed */ SemaphoreP_FAILURE = -1, /*! API failed because of a timeout */ SemaphoreP_TIMEOUT = -2 } SemaphoreP_Status; /*! * @brief Wait forever define */ /*! * @brief No wait define */ /*! * @brief Opaque client reference to an instance of a SemaphoreP * * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that * instance and is used in the other instance based functions (e.g. * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). */ typedef void *SemaphoreP_Handle; /*! * @brief Mode of the semaphore */ typedef enum { SemaphoreP_Mode_COUNTING = 0x0, SemaphoreP_Mode_BINARY = 0x1 }SemaphoreP_Mode; /*! * @brief Basic SemaphoreP Parameters * * Structure that contains the parameters are passed into ::SemaphoreP_create * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function * should be used to initialize the fields to default values before the * application sets the fields manually. The SemaphoreP default parameters are * noted in SemaphoreP_Params_init. */ typedef struct { char* name; /*!< Name of the semaphore instance. Memory must persist for the life of the semaphore instance */ SemaphoreP_Mode mode; /*!< Mode for the semaphore */ uint32_t maxCount; /*!< The max count allowed for counting semaphore */ } SemaphoreP_Params; /** @} */ /*! * @brief Function to create a semaphore. * * @param count Initial count of the semaphore. For binary semaphores, * only values of 0 or 1 are valid. * * @param params Pointer to the instance configuration parameters. NULL * denotes to use the default parameters (SemaphoreP default * parameters as noted in ::SemaphoreP_Params_init. * * @return A SemaphoreP_Handle on success or a NULL on an error * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern SemaphoreP_Handle SemaphoreP_create(uint32_t count, SemaphoreP_Params *params); /*! * @brief Function to delete a semaphore. * * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create * * @return Status of the functions * - SemaphoreP_OK: Deleted the semaphore instance * - SemaphoreP_FAILED: Failed to delete the semaphore instance * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern SemaphoreP_Status SemaphoreP_delete(SemaphoreP_Handle handle); /*! * @brief Initialize params structure to default values. * * The default parameters are: * - mode: SemaphoreP_Mode_COUNTING * - name: NULL * * @param params Pointer to the instance configuration parameters. * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern void SemaphoreP_Params_init(SemaphoreP_Params *params); /*! * @brief Function to pend (wait) on a semaphore. * * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create * * @param timeout Timeout (in milliseconds) to wait for the semaphore to * be posted (signalled). * * @return Status of the functions * - SemaphoreP_OK: Obtain the semaphore * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. * - SemaphoreP_FAILED: Non-time out failure. * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout); /*! * @brief Function to post (signal) a semaphore. * * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create * * @return Status of the functions * - SemaphoreP_OK: Released the semaphore * - SemaphoreP_FAILED: Failed to post the semaphore * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern SemaphoreP_Status SemaphoreP_post(SemaphoreP_Handle handle); /*! * @brief Function to post (signal) a semaphore from an ClockP function. * * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create * * @return Status of the functions * - SemaphoreP_OK: Released the semaphore * - SemaphoreP_FAILED: Failed to post the semaphore * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern SemaphoreP_Status SemaphoreP_postFromClock(SemaphoreP_Handle handle); /*! * @brief Function to post (signal) a semaphore from an ISR. * * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create * * @return Status of the functions * - SemaphoreP_OK: Released the semaphore * - SemaphoreP_FAILED: Failed to post the semaphore * * \ingroup SEMAPHOREP_OSAL_EXTERNAL_FUNCTION */ extern SemaphoreP_Status SemaphoreP_postFromISR(SemaphoreP_Handle handle); /** @addtogroup MAILBOX_DRIVER_ERROR_CODE * * @brief * Base error code for the Mailbox module is defined below * \include ti/common/mmwave_error.h * @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Operation cannot be implemented because a previous * operation is still not complete. */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Invalid configuration */ /** * @brief Error Code: TX mailbox full. Application tried to send a message before ACK of * the previously TX message was received. * * This ACK is part of the mailbox peripheral protocol layer and is * transparent to the application. */ /** * @brief Error Code: Write Acknowledge timed out. Driver was pending on semaphore * waiting for an acknowledge and the semaphore timed out. */ /** * @brief Error Code: Blocking read timed out. */ /** * @brief Error Code: Mailbox driver already initialized. */ /** * @brief Error Code: Osal call failed. */ /** * @brief Error Code: Invalid channel type. * Indicates that the channel type is invalid, OR * Indicates that a mailbox instance is tried to be * opened with a channel type different than other instances (for the same endpoint). */ /** * @brief Error Code: Invalid channel type. * Indicates that the channel ID is invalid, OR * Indicates that a channel ID is already in use. */ /** * @brief Error Code: Mailbox channel in use by another instance. */ /** @}*/ /** * @brief Number of possible endpoint types */ /** * @brief Mailbox buffer size (in bytes) for data transfer (per direction). */ /*! * @brief Wait forever define */ /** @addtogroup MAILBOX_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /*! * @brief A handle that is returned from a Mailbox_open() call. */ typedef void* Mbox_Handle; /*! * @brief Mailbox Type settings * * This enum defines the types of Mailbox. * Must use the enum values listed below as these values are used in expressions. * A mailbox connects a "local endpoint" to a "remote endpoint". * Each endpoint is of a type defined by this enum. */ typedef enum { /*! * BSS Mailbox type */ MAILBOX_TYPE_BSS = 0, /*! * MSS Mailbox type */ MAILBOX_TYPE_MSS = 1 , /*! * DSS Mailbox type */ MAILBOX_TYPE_DSS = 2, /*! * Last Mailbox type */ MAILBOX_TYPE_LAST = MAILBOX_TYPE_DSS } Mailbox_Type; /*! * @brief Mailbox mode settings * * This enum defines the read and write modes for the configured Mailbox. * Note that not all types are supported by read/write APIs. */ typedef enum { /*! * Blocking mode. * Driver uses a semaphore to block while data is being sent or received. Context of the call * must be a Task. Please refer to Mailbox_write() and Mailbox_read() APIs for specific information. */ MAILBOX_MODE_BLOCKING, /*! * Polling mode. * Please refer to Mailbox_write() and Mailbox_read() APIs for specific information. */ MAILBOX_MODE_POLLING, /*! * Call back mode. * Valid only for Mailbox_read API. * Application call back functions are called when interrupt is received * for a new message to be read or when interrupted is received from an acknowledge of a * previously transmitted message. Application still needs to call the Mailbox_read() API * to handle the received message. */ MAILBOX_MODE_CALLBACK } Mailbox_Mode; /*! * @brief Mailbox operation mode settings * * This enum defines the operation modes for the configured Mailbox. */ typedef enum { /*! * Current only one available operation mode. In this mode the driver allows for a partial * read of a received message. #Mailbox_readFlush() needs to be used once application finishes * reading the message. */ MAILBOX_OPERATION_MODE_PARTIAL_READ_ALLOWED } Mailbox_OpMode; /*! * @brief Mailbox data transfer mode * * This enum defines the data transfer mode for the mailbox instance.\n * It configures how the data is transferred from the application buffer * to the mailbox peripheral and from the mailbox peripheral to the * application buffer in the #Mailbox_write and #Mailbox_read APIs. * The configuration applies to both directions.\n */ typedef enum { /*! * Data transfer between maibox memory and application memory done through memcpy() */ MAILBOX_DATA_TRANSFER_MEMCPY, /*! * Data transfer between maibox memory and application memory done through DMA * @warning This mode is currently not supported. */ MAILBOX_DATA_TRANSFER_DMA } Mailbox_DataTransferMode; /*! * @brief Mailbox channel type * * This enum defines the mailbox channel type.\n Used between MSS and DSS only.\n * This field allows MSS<->DSS to use multiple (virtual) mailbox channels to communicate.\n * As there is only one mailbox physical channel, even when multiple channels are open, only one * channel can be used at a time by the application.\n * When multiple channels are used, each channel is identified by a #Mailbox_ChID.\n * The maximum number of channels (or mailbox instances) between MSS and DSS is given by #MAILBOX_CH_ID_MAX.\n * Each channel is created by opening a new instance of the mailbox driver between MSS and DSS using * a different Mailbox_ChID.\n * If a channel is opened as #MAILBOX_CHTYPE_SINGLE then only one MSS<->DSS channel is allowed and Mailbox_ChID * does not need to be populated.\n * Note that the channel types can not be mixed. That is, a channel of type #MAILBOX_CHTYPE_SINGLE in * MSS (or DSS) can not communicate with a channel of type #MAILBOX_CHTYPE_MULTI on DSS (or MSS).\n * Also note that if a channel is opened of type #MAILBOX_CHTYPE_MULTI, then all channels must be of #MAILBOX_CHTYPE_MULTI. * @warning * On XWR14xx this field is NOT used. Application does not need to set this field in XWR14xx.\n * On XWR16xx/XWR18xx/XWR68xx this field is used for the communication between MSS<->DSS only and needs to be set * accordingly by the application when opening channels between MSS<->DSS.\n * On XWR16xx/XWR18xx/XWR68xx this field is NOT used for the communication between MSS<->BSS or between DSS<->BSS. * Therefore, application does not need to set this field when MSS or DSS open a channel with BSS. */ typedef enum { /*! * Only one mailbox channel (in each direction) allowed between DSS and MSS.\n * In this case, the field Mailbox_ChID does NOT need to be specified. */ MAILBOX_CHTYPE_SINGLE, /*! * Multiple mailbox channels (in each direction) allowed between DSS and MSS.\n * In this case, the field Mailbox_ChID needs to be specified. */ MAILBOX_CHTYPE_MULTI } Mailbox_ChType; /*! * @brief Mailbox channel ID * * This enum defines the possible mailbox channel IDs.\n Used between MSS and DSS only.\n * IDs are used only when #Mailbox_ChType is of type #MAILBOX_CHTYPE_MULTI. * * @warning * On XWR14xx this field is NOT used. Application does not need to set this field in XWR14xx.\n * On XWR16xx/XWR18xx/XWR68xx this field is used for the communication between MSS<->DSS only and needs to be set * accordingly by the application when opening channels between MSS<->DSS.\n * On XWR16xx/XWR18xx/XWR68xx this field is NOT used for the communication between MSS<->BSS or between DSS<->BSS. * Therefore, application does not need to set this field when MSS or DSS open a channel with BSS. */ typedef enum { /*! * ID = 0 */ MAILBOX_CH_ID_0 = 0, /*! * ID = 1 */ MAILBOX_CH_ID_1 = 1, /*! * ID = 2 */ MAILBOX_CH_ID_2 = 2, /*! * ID = 3 */ MAILBOX_CH_ID_3 = 3, /*! * ID = 4 */ MAILBOX_CH_ID_4 = 4, /*! * ID = 5 */ MAILBOX_CH_ID_5 = 5, /*! * ID = 6 */ MAILBOX_CH_ID_6 = 6, /*! * ID = 7 */ MAILBOX_CH_ID_7 = 7, /*! * Maximum ID value, which is #MAILBOX_CH_ID_7 */ MAILBOX_CH_ID_MAX = MAILBOX_CH_ID_7 } Mailbox_ChID; /*! * @brief The definition of a callback function used by the MAILBOX driver * when used in MAILBOX_MODE_CALLBACK. * The callback can occur in task or HWI context. * * @warning Making Mailbox_read() calls within its own callback * routines are STRONGLY discouraged as it will impact Task and * System stack size requirements! * * @param handle Mbox_Handle * @param remoteEndpoint Remote endpoint * */ typedef void (*Mailbox_Callback) (Mbox_Handle handle, Mailbox_Type remoteEndpoint); /*! * @brief Mailbox Configuration Parameters * * Mailbox configuration parameters are used with the Mailbox_open() call. Default values for * these parameters are set using Mailbox_Config_init(). * * @sa Mailbox_Config_init() * */ typedef struct Mailbox_Config_t { /** * @brief Mailbox read mode */ Mailbox_Mode readMode; /** * @brief Mailbox write mode */ Mailbox_Mode writeMode; /** * @brief Timeout for read semaphore */ uint32_t readTimeout; /** * @brief Timeout for write semaphore */ uint32_t writeTimeout; /** * @brief Pointer to read callback */ Mailbox_Callback readCallback; /** * @brief Driver mode of operation */ Mailbox_OpMode opMode; /** * @brief Data transfer mode */ Mailbox_DataTransferMode dataTransferMode; /** * @brief Mailbox channel type. * Used only when remote endpoint is MSS or DSS. * * @warning * On XWR14xx this field is NOT used. Application does not need to set this field in XWR14xx.\n * On XWR16xx/XWR18xx/XWR68xx this field is used for the communication between MSS<->DSS only and needs to be set accordingly. * For MSS<->BSS or DSS<->BSS communication in XWR16xx/XWR18xx/XWR68xx application does not need to set this field. */ Mailbox_ChType chType; /** * @brief Channel ID for this instance of the driver. * Used only when remote endpoint is MSS or DSS and when chType is set to MAILBOX_CHTYPE_MULTI. * * @warning * On XWR14xx this field is NOT used. Application does not need to set this field in XWR14xx.\n * On XWR16xx/XWR18xx/XWR68xx this field is used for the communication between MSS<->DSS only and needs to be set accordingly. * For MSS<->BSS or DSS<->BSS communication in XWR16xx/XWR18xx/XWR68xx application does not need to set this field. */ Mailbox_ChID chId; } Mailbox_Config; /** * @brief * Mailbox Statistics * * @details * The structure describes the Mailbox statistics information * */ typedef struct Mailbox_Stats_t { /** * @brief Status of TX box (full or empty) */ uint32_t txBoxStatus; /** * @brief Number of TX messages successfully sent (acknowledgement has been received) */ uint16_t txCount; /** * @brief Number of RX messages received */ uint16_t rxCount; /** * @brief Flag used for read polling mode. Indicate if a new message has arrived. */ uint32_t newMessageFlag; /** * @brief Number of bytes already read by past calls to the read API in current message */ uint32_t numBytesRead; /** * @brief Number of full box ISR received */ uint16_t boxFullIsrCount; /** * @brief Number of empty box ISR received */ uint16_t boxEmptyIsrCount; /** * @brief Number of times the readFlush API was called. */ uint16_t readFlushCount; /** * @brief Number of full box ISR received with invalid arg */ uint8_t boxFullIsrErrCount; /** * @brief Number of empty box ISR received with invalid arg */ uint8_t boxEmptyIsrErrCount; /** * @brief Mailbox register */ uint32_t regLclToRemRaw; /** * @brief Mailbox register */ uint32_t regRemToLocRaw; /** * @brief Mailbox register */ uint32_t regLclToRemMask; /** * @brief Mailbox register */ uint32_t regRemToLocMask; }Mailbox_Stats; /** @} */ /*! * @brief Function to close a Mailbox peripheral specified by the Mailbox handle * * @pre Mailbox_open() has been called. * * @param[in] handle A Mbox_Handle returned from Mailbox_open() * * @sa Mailbox_open() * * @return Returns error code in case of failure. * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern int32_t Mailbox_close(Mbox_Handle handle); /*! * @brief Function to initialize the Mailbox module.\n * It must be called only once per local endpoint. * * @pre This function must be called before * any other Mailbox driver API is used. * * @param[in] localEndpoint Type of local mailbox endpoint. * * @return Returns error code in case of failure. * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern int32_t Mailbox_init(Mailbox_Type localEndpoint); /*! * @brief Function to initialize an instance of the mailbox driver. * * For XWR14xx: \n * Between MSS<->BSS only one instance of the driver can be opened.\n * For XWR16xx/XWR18xx/XWR68xx: \n * Between MSS<->BSS only one instance of the driver can be opened.\n * Between DSS<->BSS only one instance of the driver can be opened.\n * Between MSS<->DSS multiple instances of the driver can be opened (each instance controls one virtual mailbox channel).\n * @sa Mailbox_ChType Mailbox_ChID * * @pre Mailbox_init() has been called * * @param[in] cfg Pointer to configuration block. * @param[in] remoteEndpoint Remote endpoint that this mailbox instance will communicate with. * @param[out] errCode Pointer to error code value/status to be returned by the function * * * @return A Mbox_Handle upon success. NULL if an error occurs. * * @sa Mailbox_init() * @sa Mailbox_close() * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern Mbox_Handle Mailbox_open(Mailbox_Type remoteEndpoint, const Mailbox_Config *cfg, int32_t* errCode); /*! * @brief Function to initialize the Mailbox_Config struct to its defaults * * @param[in] cfg A pointer to Mailbox_Config structure for * initialization * * Defaults values are: * @code readMode = Mailbox_MODE_BLOCKING writeMode = Mailbox_MODE_BLOCKING readTimeout = MAILBOX_WAIT_FOREVER writeTimeout = MAILBOX_WAIT_FOREVER readCallback = NULL opMode = MAILBOX_OPERATION_MODE_PARTIAL_READ_ALLOWED dataTransferMode = MAILBOX_DATA_TRANSFER_MEMCPY chType = MAILBOX_CHTYPE_SINGLE chId = MAILBOX_CH_ID_0 @endcode * * @warning * On XWR14xx the fields chType and chId are NOT used. Application does not need to set these * fields in XWR14xx.\n * On XWR16xx/XWR18xx/XWR68xx the fields chType and chId are used for the communication between MSS<->DSS only * and need to be set accordingly.\n * For MSS<->BSS or DSS<->BSS communication in XWR16xx/XWR18xx/XWR68xx application does not need to set these * fields. * * @return Returns error code in case of failure. * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern int32_t Mailbox_Config_init(Mailbox_Config *cfg); /*! * @brief Function that writes data to a Mailbox. * * Mailbox can only send one message at a time to a remote endpoint. * After data is copied to mailbox buffer, driver triggers interrupt to remote endpoint. * This means that a call to the Mailbox_write() is always a complete mailbox transaction. * A new message can only be sent after the previous message has been acknowledged by the remote endpoint. * The acknowledgement process is handled internally by the driver. * All interrupts related to the write operations are managed by the driver and are not exposed to the application. * If called with data that will surpass the maximum size of the mailbox buffer, the write operation will fail with an error * code and nothing will be written to the mailbox buffer. Returns number of bytes written or error.\n * The maximum size of the mailbox buffer is given by #MAILBOX_DATA_BUFFER_SIZE. Application code is responsible for * fragmentation of the message if the size is bigger than the mailbox buffer. * * Write modes: * * In Mailbox_MODE_BLOCKING: \n * Mailbox_write() will block task execution until the message has been copied from application to the mailbox buffer * and an acknowledgement is received from the remote endpoint. * If a new Mailbox_write() is issued before the acknowledgement is received, the write will fail with an error * code returned to application. * * In Mailbox_MODE_POLLING: \n * Mailbox_write() will block task execution until the message has been copied from application to the mailbox buffer * but it does not wait for an acknowledgement from the remote endpoint. * If a new Mailbox_write() is issued before the acknowledgement is received, the write will fail with an error code * returned to application. * In this mode, application does not know when acknowledgement is received and it may try to write the next message * multiple times until it succeeds as if it is polling for the status of the acknowledgement. * * @pre Mailbox_open() has been called * * * @param[in] handle A Mbox_Handle * * @param[in] buffer A pointer to buffer containing data to * be written to the Mailbox. * * @param[in] size The number of bytes in the buffer that should be written * to the Mailbox. * * @return Returns the number of bytes that have been written to the Mailbox. * If an error occurs, one of the Mailbox Error codes is returned. * * @sa Mailbox_writeReset() * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ /* Code review: Input variable "size" can be 16bit but 32bit matches the RL interface*/ extern int32_t Mailbox_write(Mbox_Handle handle, const uint8_t *buffer, uint32_t size); /*! * @brief Function that reads data from a Mailbox. * * * Mailbox can only read one message at a time from a remote endpoint. * Multiple Mailbox_read() calls can be done for the same message in the mailbox. * * E.g. Application can read part of the message to figure out full message length and issue a subsequent Mailbox_read(). * * Mailbox driver keeps track internally of number of bytes read for a message. * The first Mailbox_read() for a message always starts at byte zero. * In case of multiple Mailbox_read() calls for the same message, the subsequent reads start in the * next byte from where the previous read stopped. * Once application finishes reading the message it must issue a Mailbox_readFlush() * to release the mailbox buffer and notify the remote endpoint.\n * The maximum size of the mailbox buffer is given by #MAILBOX_DATA_BUFFER_SIZE. Application code is responsible for * fragmentation of the message if the size is bigger than the mailbox buffer. * * All interrupts related to the read operation are managed by the driver and are not exposed to the application. * Returns number of bytes read or error. * * Read modes: * * In Mailbox_MODE_BLOCKING: \n * If this is the first read on a new message, Mailbox_read() will block task execution until a new message has arrived * in the local Mailbox buffer * and it is copied to the application buffer. * If this is not a new message, Mailbox_read() will block task execution until "size" bytes are copied to the application buffer. * * In Mailbox_MODE_POLLING: \n * If this is the first read on a new message and the new message has not arrived, Mailbox_read() will return size * zero to indicate no bytes were read. * If the new message has arrived or if this is not a new message, Mailbox_read() will copy the data to application buffer. * Mailbox_read() will return after "size" bytes are copied to the application buffer. * * In Mailbox_MODE_CALLBACK: \n * The driver will invoke the application callback function once a new message is received in the mailbox. * Application is responsible for calling Mailbox_read() to read the new message. * Mailbox_read() copies the data into the application buffer and then exit. * * In any of the modes described above, Mailbox_readFlush() needs to be issued after the message is fully read by the application. * * @pre Mailbox_open() has been called * * @param[in] handle A Mbox_Handle * * @param[in] buffer A pointer to an empty buffer in which * received data should be written to. * * @param[in] size The number of bytes to be written into buffer * * @return Returns the number of bytes that have been read from the Mailbox. * If an error occurs, one of the Mailbox Error codes is returned. * * @sa Mailbox_readFlush() * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ /* Code review: Input variable "size" can be 16bit but 32bit matches the RL interface*/ extern int32_t Mailbox_read(Mbox_Handle handle, uint8_t *buffer, uint32_t size); /*! * @brief Function that should be called after application is done reading the message. * * Notifies the remote endpoint that the local mailbox is ready to receive a new message after the previous message was read.\n * Remote endpoint can not send a new message to the local endpoint until Mailbox_readFlush() is issued by the local endpoint. * Once Mailbox_readFlush() is issued, the local endpoint must assume that the previously received message * is no longer in the mailbox buffer and subsequent Mailbox_read() will return no data until a new message arrives in the mailbox. * * @pre Mailbox_open() has been called * * @param[in] handle A Mbox_Handle * * @return Returns error code in case of failure. * * @sa Mailbox_read() * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern int32_t Mailbox_readFlush(Mbox_Handle handle); /*! * @brief Function that should be called if application is unable to write to mailbox. * * This function is used to handle the abnormal situation when an acknowledgement was never received for the previous * message sent in the mailbox. This acknowledgement is at the internal Mailbox Peripheral protocol layer and * the application perceives this situation when a call to Mailbox_write() returns error code #MAILBOX_ETXFULL. * * This condition can arise in two circumstances: * 1. Not enough processing time: The local endpoint is sending a message before the remote endpoint had * chance to acknowledge the previous message (not enough time). * 2. Enough processing time: The remote endpoint did not acknowledge the previous message even though enough time has elapsed. * This indicates an error condition in the remote endpoint. * * Mailbox_writeReset() resets the mailbox driver state machine so that application can send a new message to the remote endpoint. * * After invoking this function, the application can proceed to write a new message to the remote endpoint using Mailbox_write(). * * @pre Mailbox_open() has been called * * @param[in] handle A Mbox_Handle * * @return Returns error code in case of failure. * * @sa Mailbox_write() * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern int32_t Mailbox_writeReset(Mbox_Handle handle); /*! * @brief Function that collects mailbox driver statistics * * This function is used to collect mailbox driver statistics. * It's main purpose is debugging of mailbox driver. * * @pre Mailbox_open() has been called * * @param[in] handle A Mbox_Handle * @param[out] stats Pointer to mailbox stats structure to be filled * * * @return Returns error code in case of failure. * * \ingroup MAILBOX_DRIVER_EXTERNAL_FUNCTION * */ extern int32_t Mailbox_getStats(Mbox_Handle handle, Mailbox_Stats * stats); /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @file pinmux.h * * @brief PINMUX driver interface * */ /** @mainpage Pinmux Driver * * The pinmux driver provides set/get APIs for the various PADs available on a device * * The PINMUX header file should be included in an application as follows: * @code * #include * @endcode * * ## Initializing the driver # * None is required. The pad under consideration can be configured directly by calling * any of the Set APIs * * * @code // Setup the PINMUX Pinmux_Set_FuncSel(SOC_XWR16XX_PINN5_PADBE, SOC_XWR16XX_PINN5_PADBE_MSS_UARTA_TX); Pinmux_Set_FuncSel(SOC_XWR16XX_PINN4_PADBD, SOC_XWR16XX_PINN4_PADBD_MSS_UARTA_RX); * @endcode * * ## Instrumentation # * Uses DebugP_log functions for debug messages * * ## Hardware Register Map # * The hardware register map used by this driver can be found at include/reg_pinmux.h * * ============================================================================ */ /** @defgroup PINMUX_DRIVER_EXTERNAL_FUNCTION PINMUX Driver External Functions @ingroup PINMUX_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup PINMUX_DRIVER_EXTERNAL_DATA_STRUCTURE PINMUX Driver External Data Structures @ingroup PINMUX_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup PINMUX_DRIVER_ERROR_CODE PINMUX Driver Error Codes @ingroup PINMUX_DRIVER @brief * The section has a list of all the error codes which are generated by the PINMUX Driver * module */ /** @defgroup PINMUX_DRIVER_PAD_FUNCTIONS_16XX PINMUX Driver Available PAD functionality for 16xx @ingroup PINMUX_DRIVER @brief * The section has a list of all the functionality available at the various pads for 16xx */ /** @defgroup PINMUX_DRIVER_PAD_FUNCTIONS_14XX PINMUX Driver Available PAD functionality for 14xx @ingroup PINMUX_DRIVER @brief * The section has a list of all the functionality available at the various pads for 14xx */ /** @defgroup PINMUX_DRIVER_PAD_FUNCTIONS_18XX PINMUX Driver Available PAD functionality for 18xx @ingroup PINMUX_DRIVER @brief * The section has a list of all the functionality available at the various pads for 18xx */ /** @defgroup PINMUX_DRIVER_PAD_FUNCTIONS_68XX PINMUX Driver Available PAD functionality for 68xx @ingroup PINMUX_DRIVER @brief * The section has a list of all the functionality available at the various pads for 68xx */ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @file pinmux_xwr18xx.h * * @brief PINMUX pad settings for 18xx device * * ============================================================================ */ /** @addtogroup PINMUX_DRIVER_PAD_FUNCTIONS_18XX * * @brief * PAD Functionality * @{ */ /** @name PINP13_PADAA * PINP13_PADAA functionality * Equivalent to PINB2_PADAA on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP13_PADAA*/ /** @name PINH13_PADAB * PINH13_PADAB functionality * Equivalent to PINM2_PADAB on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINH13_PADAB*/ /** @name PINJ13_PADAC * PINJ13_PADAC functionality * Equivalent to PINL3_PADAC on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINJ13_PADAC*/ /** @name PIND13_PADAD * PIND13_PADAD functionality * Equivalent to PINF2_PADAD on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PIND13_PADAD*/ /** @name PINE14_PADAE * PINE14_PADAE functionality * Equivalent to PIND1_PADAE on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINE14_PADAE*/ /** @name PINE13_PADAF * PINE13_PADAF functionality * Equivalent to PIND2_PADAF on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINE13_PADAF*/ /** @name PINE15_PADAG * PINE15_PADAG functionality * Equivalent to PINC2_PADAG on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINE15_PADAG*/ /** @name PINF13_PADAH * PINF13_PADAH functionality * Equivalent to PING1_PADAH on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINF13_PADAH*/ /** @name PING14_PADAI * PING14_PADAI functionality * Equivalent to PING3_PADAI on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PING14_PADAI*/ /** @name PINF14_PADAJ * PINF14_PADAJ functionality * Equivalent to PINE2_PADAJ on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINF14_PADAJ*/ /** @name PINH14_PADAK * PINH14_PADAK functionality * Equivalent to PIND3_PADAK on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINH14_PADAK*/ /** @name PINR13_PADAL * PINR13_PADAL functionality * Equivalent to PINH3_PADAL on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR13_PADAL*/ /** @name PINN12_PADAM * PINN12_PADAM functionality * Equivalent to PING2_PADAM on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN12_PADAM*/ /** @name PINR14_PADAN * PINR14_PADAN functionality * Equivalent to PINJ3_PADAN on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR14_PADAN*/ /** @name PINP12_PADAO * PINP12_PADAO functionality * Equivalent to PINK2_PADAO on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP12_PADAO*/ /** @name PINR12_PADAP * PINR12_PADAP functionality * Equivalent to PINH2_PADAP on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR12_PADAP*/ /** @name PINP11_PADAQ * PINP11_PADAQ functionality * Equivalent to PINJ2_PADAQ on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP11_PADAQ*/ /** @name PINN7_PADAR * PINN7_PADAR functionality * Equivalent to PINU14_PADAR on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN7_PADAR_*/ /** @name PINN9_PADAS * PINN9_PADAS functionality * Equivalent to PINU13_PADAS on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN9_PADAS_*/ /** @name PINN6_PADAT * PINN6_PADAT functionality * Equivalent to PINU15_PADAT on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN6_PADAT_*/ /** @name PINP10_PADAU * PINP10_PADAU functionality * Equivalent to PINT3_PADAU on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP10_PADAU*/ /** @name PINN10_PADAV * PINN10_PADAV functionality * Equivalent to PINU8_PADAV on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN10_PADAV*/ /** @name PINR11_PADAW * PINR11_PADAW functionality * Equivalent to PINU9_PADAW on XWR18XXAOP Device */ /**@{*/ /**@}*/ //Subsystem - /** @name PINN13_PADAX * PINN13_PADAX functionality * Equivalent to PINU10_PADAX on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN13_PADAX*/ /** @name PINN8_PADAY * PINN8_PADAY functionality * Equivalent to PINV13_PADAY on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN8_PADAY_*/ /** @name PINK13_PADAZ * PINK13_PADAZ functionality * Equivalent to PINK3_PADAZ on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINK13_PADAZ*/ /** @name PINP9_PADBA * PINP9_PADBA functionality * Equivalent to PINV10_PADBA on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP9_PADBA_*/ /** @name PINP4_PADBB * PINP4_PADBB functionality * Equivalent to PINU12_PADBB on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP4_PADBB_*/ /** @name PING13_PADBC * PING13_PADBC functionality * Equivalent to PINM3_PADBC on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PING13_PADBC*/ /** @name PINN4_PADBD * PINN4_PADBD functionality * Equivalent to PINV16_PADBD on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN4_PADBD_*/ /** @name PINN5_PADBE * PINN5_PADBE functionality * Equivalent to PINU16_PADBE on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN5_PADBE_*/ /** @name PINR4_PADBF * PINR4_PADBF functionality * Equivalent to PINU7_PADBF on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR4_PADBF_*/ /** @name PINP5_PADBG * PINP5_PADBG functionality * Equivalent to PINU6_PADBG on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP5_PADBG_*/ /** @name PINR5_PADBH * PINR5_PADBH functionality * Equivalent to PINV5_PADBH on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR5_PADBH_*/ /** @name PINP6_PADBI * PINP6_PADBI functionality * Equivalent to PINU5_PADBI on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP6_PADBI_*/ /** @name PINR7_PADBJ * PINR7_PADBJ functionality * Equivalent to PINV3_PADBJ on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR7_PADBJ_*/ /** @name PINP7_PADBK * PINP7_PADBK functionality * Equivalent to PINM1_PADBK on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP7_PADBK_*/ /** @name PINR8_PADBL * PINR8_PADBL functionality * Equivalent to PINL2_PADBL on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINR8_PADBL_*/ /** @name PINP8_PADBM * PINP8_PADBM functionality * Equivalent to PINL1_PADBM on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINP8_PADBM_*/ /** @name PINNC3_PADBN Valid for 1843 AOP * PINNC3_PADBN functionality */ /**@{*/ /* PIN C3, PADBN functionality */ /**@}*/ /*PINNC3_PADBN*/ /** @name PINB3_PADBO Valid for 1843 AOP * PINB3_PADBO functionality */ /**@{*/ /* PIN B3, PADBO functionality */ /**@}*/ /*PINB3_PADBO*/ /** @name PINC4_PADBP Valid for 1843 AOP * PINC4_PADBP functionality */ /**@{*/ /* PIN C4, PADBP functionality */ /**@}*/ /*PINC4_PADBP*/ /** @name PINA3_PADBQ Valid for 1843 AOP * PINA3_PADBQ functionality */ /**@{*/ /* PIN A3, PADBQ functionality */ /**@}*/ /*PINA3_PADBQ*/ /** @name PINB4_PADBR Valid for 1843 AOP * PINB4_PADBR functionality */ /**@{*/ /* PIN B4, PADBR functionality */ /**@}*/ /*PINB4_PADBR*/ /** @name PINA4_PADBS Valid for 1843 AOP * PINA4_PADBS functionality */ /**@{*/ /* PIN A4, PADBS functionality */ /**@}*/ /*PINA4_PADBS*/ /** @name PINC5_PADBT Valid for 1843 AOP * PINC5_PADBT functionality */ /**@{*/ /* PIN C5 PADBT functionality */ /**@}*/ /*PINC5_PADBT*/ /** @name PINB5_PADBU Valid for 1843 AOP * PINB5_PADBU functionality */ /**@{*/ /* PIN B5, PADBU functionality */ /**@}*/ /*PINB5_PADBU*/ /** @name PINN15_PADBV * PINN15_PADBV functionality * Equivalent to PINU3_PADBV on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN15_PADBV*/ /** @name PINN14_PADBW * PINN14_PADBW functionality * Equivalent to PINU4_PADBW on XWR18XXAOP Device */ /**@{*/ /**@}*/ /*PINN14_PADBW*/ /** @}*/ /** @addtogroup PINMUX_DRIVER_ERROR_CODE * * @brief * Base error code for the PINMUX module is defined in the * \include ti/common/mmwave_error.h * @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Operation cannot be done as pinmux base address is not defined. */ /** @}*/ /** @addtogroup PINMUX_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /*! * @brief PINMUX Output Override Enum * * Enum for setting output override functionality * * * @sa Pinmux_Set_OverrideCtrl() */ typedef enum Pinmux_Output_Override { PINMUX_OUTPUT_DIS=0x0U, /*! 0 - value read from the Pi and pupdsel bits of a given valid pin (Pinmux_Pull_e) * */ extern int32_t Pinmux_Get_Pull(uint32_t pin); /** @fn int32_t Pinmux_Get_SlewRate(uint32_t pin) * @brief Get the pin slew rate. * * This function gets the configured functionality of the pin. * * @param[in] pin: Pin number to be queried * * @return Value < 0 - in case of error * Value > 0 - value read from the SC1 bits of a given valid pin (Pinmux_SlewRate_e) * */ extern int32_t Pinmux_Get_SlewRate(uint32_t pin); /** @fn int32_t Pinmux_Get_FuncSel(uint32_t pin) * @brief Get the pin functionality. * * This function gets the configured functionality of the pin. * * @param[in] pin: Pin number to be configured * * @return Value < 0 - in case of error * Value > 0 - value read from the Func_Sel bits of a given valid pin * */ extern int32_t Pinmux_Get_FuncSel(uint32_t pin); /** @}*/ /** * @file mmwave.h * * @brief * This is the high level API which is used to abstract the mmWave * link API and allow application developers to be abstracted from * the lower level complexities. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @defgroup MMWAVE mmWave API */ /* mmWave SDK Include Files: */ /************************************************************************************************* * FileName : mmwavelink.h * * Description : This file includes all the header files which needs to be included by application * ************************************************************************************************* * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *------------------------------------------------------------------------------------------------ * * Redistribution and use in source and binary forms, with or without modification, are permitted * provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, this list of * conditions and the following disclaimer in the documentation and/or other materials provided * with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its contributors may be * used to endorse or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ /************************************************************************************************* * FILE INCLUSION PROTECTION ************************************************************************************************* */ /*LDRA_NOANALYSIS*/ /*! \mainpage mmWaveLink Framework \section intro_sec Introduction TI Automotive and Industrial mmWave Radar products are highly-integrated 77GHz CMOS millimeter wave devices.The devices integrate all of the RF and Analog functionality, including VCO, PLL, PA, LNA, Mixer and ADC for multiple TX/RX channels into a single chip.\n -# The AWR1243 is an RF transceiver device and it includes 4 receiver channels and 3 transmit channels in a single chip. AWR1243 also support multi-chip cascading. \n -# The AWR1443/IWR1443 is a mmwave radar-on-a-chip device, which includes 4 receive channels and 3 transmit channels and additionally an Cortex R4F and hardware FFT accelerator.\n -# AWR1642 and IWR1642 are mmwave radar-on-a-chip device, which includes 4 receive channels and 2 transmit channels and additionally an Cortex R4F and C674x DSP for signal processing TI mmWave radar devices include a mmwave front end or BIST (Built-in Self-Test) processor, which is responsible to configure the RF/Analog and digital front-end in real-time, as well as to periodically schedule calibration and functional safety monitoring.This enables the mmwave front-end(BIST processor) to be self-contained and capable of adapting itself to handle temperature and ageing effects, and to enable significant ease-of-use from an external host perspective. TI mmwave front end is a closed subsystem whose internal blocks are configurable using messages coming over mailbox.\n TI mmWaveLink provides APIs generates these message and sends it to mmwave front end over mailbox. It also includes acknowledement and CRC for each message to provide a reliable communication TI mmWaveLink Framework: - Is a link between application and mmwave front end. - Provides low level APIs to configure the front end and handles the communication with the front end. - Is platform and OS independent which means it can be ported into any processor which provides communication interface such as SPI and basic OS routines. The mmWaveLink framework can also run in single threaded environment - Is integrated into mmWave SDK and can run on R4F or DSP and communicates with mmwave front end over Mailbox interface * @image html mmwl_block_diagram.png \section modules_sec Modules To make it simple, TI's mmWaveLink framework capabilities are divided into modules.\n These capabilities include device control, RF/Analog configuration, ADC configuration, Data path(LVDS/CSI2) cofiguration, FMCW chirp configuration and more.\n Listed below are the various modules in the mmWaveLink framework: -# \ref Device - Controls mmwave radar device which include: * Initialization, such as: mmwave device power On/Off, Firmware Patch download * Cascade device configuration such as Add/Connect multiple mmWave devices -# \ref Sensor - The RF/Sensor Configuration module controls the different HW blocks inside mmWave Front end. * @image html mmwave_frontend.png * mmWave Front End has below key blocks -# Chirp sequencer (Radar Timing Engine) - This block is responsible for constructing the sequence of FMCW chirps or frames and programming the timing engine -# Rx/Tx Channel - This defines how many Rx and Tx channel needs to be enabled. Also it defines how to configure the mmWave front end in cascade mode for Imaging Radar -# Rx Analog Chain - This defines how the received signal is mixed and how different filters in the chain can be configured -# ADC and Digital Front End Configuration - This defines how the IF data is digitized and how it is sampled for further processing in the DSP or Hardware Accelerator. Same ADC data can be sent over LVDS/CSI2 interface to an extenal processor * The configuration APIs can further be categorized as.\n -# mmwave static configuration, such as: Tx and Rx channel, ADC configuration etc -# mmwave dynamic configuration, such as FMCW Chirp configuration, profile configuration -# mmwave advance configuration such as Binary phase modulation, Dynamic power save etc -# mmwave sensor control, such as: Frame start/stop -# \ref Data_Path - The Data path Configuration module controls the high speed interface in mmWave device. * @image html data_path.png * The configuration APIs include.\n -# High Speed interface(LVDS/CSI2) selection -# Data format and rate configuration -# ADC, Chirp Profile(CP), Chirp Quality(CQ) data transfer sequence -# Lane configurations -# LVDS/CSI2 specific configuration -# \ref Monitoring - The Monitoring/Calibration module configures the calibration and functional safety monitoring in mmWave device * TI mmWave Front end includes built-in processor that is programmed by TI to handle RF calibrations and functional safety monitoring. The RF calibrations ensure that the performance of the device is maintained across temperature and process corners -# \ref Communication_Protocol - The mmWave communication protocol ensures reliable communication between host(internal or external) and mmWave Front end. -# It is a simple stop and wait protocol. Each message needs to be acknowledged by receiver before next message can be sent. -# Messages are classifieds as "Command", "Response" and "Asynchronous Event" -# If Command can not be processed immediately, ACK response is sent immediately (If requested). "Asynchronous Event" is sent upon completion of the command execution. * @image html comm_prot.png \section proting_sec Porting Guide The porting of the mmWaveLink driver to any new platform is based on few simple steps. This guide takes you through this process step by step. Please follow the instructions carefully to avoid any problems during this process and to enable efficient and proper work with the device. Please notice that all modifications and porting adjustments of the driver should be made in the application only and driver should not be modified. Changes in the application file will ensure smoothly transaction to new versions of the driver at the future! \subsection porting_step1 Step 1 - Define mmWaveLink client callback structure The mmWaveLink framework is ported to different platforms using mmWaveLink client callbacks. These callbacks are grouped as different structures such as OS callbacks, Communication Interface callbacks and others. Application needs to define these callbacks and initialize the mmWaveLink framework with the structure. * @code * rlClientCbs_t clientCtx = { 0 }; * rlReturnVal_t retVal; * rlUInt32_t deviceMap = RL_DEVICE_MAP_CASCADED_1; * @endcode Refer to \ref rlClientCbs_t for more details \subsection porting_step2 Step 2 - Implement Communication Interface Callbacks The mmWaveLink device support several standard communication protocol among SPI and MailBox Depending on device variant, one need to choose the communication channel. For e.g xWR1443/xWR1642/xWR1843 requires Mailbox interface and AWR1243 supports SPI interface. The interface for this communication channel should include 4 simple access functions: -# rlComIfOpen -# rlComIfClose -# rlComIfRead -# rlComIfWrite * @code * clientCtx.comIfCb.rlComIfOpen = Host_spiOpen; * clientCtx.comIfCb.rlComIfClose = Host_spiClose; * clientCtx.comIfCb.rlComIfRead = Host_spiRead; * clientCtx.comIfCb.rlComIfWrite = Host_spiWrite; * @endcode Refer to \ref rlComIfCbs_t for interface details \subsection porting_step3 Step 3 - Implement Device Control Interface The mmWaveLink driver internally powers on/off the mmWave radar device. The exact implementation of these interface is platform dependent, hence you need to implement below functions: -# rlDeviceEnable -# rlDeviceDisable -# rlRegisterInterruptHandler * @code * clientCtx.devCtrlCb.rlDeviceDisable = Host_disableDevice; * clientCtx.devCtrlCb.rlDeviceEnable = Host_enableDevice; * clientCtx.devCtrlCb.rlDeviceMaskHostIrq = Host_spiIRQMask; * clientCtx.devCtrlCb.rlDeviceUnMaskHostIrq = Host_spiIRQUnMask; * clientCtx.devCtrlCb.rlRegisterInterruptHandler = Host_registerInterruptHandler; * clientCtx.devCtrlCb.rlDeviceWaitIrqStatus = Host_deviceWaitIrqStatus; * @endcode Refer to \ref rlDeviceCtrlCbs_t for interface details \subsection porting_step4 Step 4 - Implement Event Handlers The mmWaveLink driver reports asynchronous event indicating mmwave radar device status, exceptions etc. Application can register this callback to receive these notification and take appropriate actions * @code * clientCtx.eventCb.rlAsyncEvent = Host_asyncEventHandler; * @endcode Refer to \ref rlEventCbs_t for interface details \subsection porting_step5 Step 5 - Implement OS Interface The mmWaveLink driver can work in both OS and NonOS environment. If Application prefers to use operating system, it needs to implement basic OS routines such as tasks, mutex and Semaphore. In Case of Non-OS environment application needs to implement equivalent form of mutex & semaphore. * @code * clientCtx.osiCb.mutex.rlOsiMutexCreate = Host_osiLockObjCreate; * clientCtx.osiCb.mutex.rlOsiMutexLock = Host_osiLockObjLock; * clientCtx.osiCb.mutex.rlOsiMutexUnLock = Host_osiLockObjUnlock; * clientCtx.osiCb.mutex.rlOsiMutexDelete = Host_osiLockObjDelete; * * clientCtx.osiCb.sem.rlOsiSemCreate = Host_osiSyncObjCreate; * clientCtx.osiCb.sem.rlOsiSemWait = Host_osiSyncObjWait; * clientCtx.osiCb.sem.rlOsiSemSignal = Host_osiSyncObjSignal; * clientCtx.osiCb.sem.rlOsiSemDelete = Host_osiSyncObjDelete; * * clientCtx.osiCb.queue.rlOsiSpawn = Host_osiSpawn; * * clientCtx.timerCb.rlDelay = Host_osiSleep; * @endcode Refer to \ref rlOsiCbs_t for interface details \subsection porting_step6 Step 6 - Implement CRC Interface and Type The mmWaveLink driver uses CRC for message integrity. If Application prefers to use CRC, it needs to implement CRC routine and provides the CRC type. * @code * clientCtx.crcCb.rlComputeCRC = Host_computeCRC; * clientCtx.crcType = RL_CRC_TYPE_32BIT; * @endcode Refer to \ref rlCrcCbs_t for interface details @note : Recommended CRC type is RL_CRC_TYPE_32BIT for AWR1243 device. \subsection porting_step7 Step 7 - Implement Debug Interface The mmWaveLink driver can print the debug message. If Application prefers to enable debug messages, it needs to implement debug callback. Refer to \ref rlDbgCb_t for interface details \subsection porting_final Final Step - Initializing mmWaveLink Driver Once all the above Interfaces are implemented, Application need to fill these callbacks in \ref rlClientCbs_t and Initialize mmWaveLink by passing the client callbacks. Application also need to define where the mmWaveLink driver is running, for e.g, External Host in case of AWR1243 or MSS/DSS in case of xWR1642/xWR1843. * * @code * clientCtx.platform = RL_PLATFORM_HOST; * clientCtx.arDevType = RL_AR_DEVICETYPE_12XX; * * retVal = rlDevicePowerOn(deviceMap, clientCtx); * @endcode * \subsection porting_crc CRC Type Implementation Device sets same CRC type as recieved command to response message. So change to command's CRC type will cause a change to response's CRC type as well. [Refer to \ref porting_step7]. mmWave device(MasterSS & RadarSS) uses 16-bit CRC type by default for async-event messages. If Host needs to set different CRC type to Async-event then it must implement the following code snippet. * * @code * rlRfDevCfg_t rfDevCfg = {0x0}; * // set global and monitoring async event direction to Host * rfDevCfg.aeDirection = 0x05; * // Set the CRC type of Async event received from RadarSS * rfDevCfg.aeCrcConfig = RL_CRC_TYPE_32BIT; * retVal = rlRfSetDeviceCfg(deviceMap, &rfDevCfg); * * rlDevMiscCfg_t devMiscCfg = {0}; * // Set the CRC Type for Async Event from MSS * devMiscCfg.aeCrcConfig = RL_CRC_TYPE_32BIT; * retVal = rlDeviceSetMiscConfig(deviceMap, &devMiscCfg); * @endcode * \subsection porting_be Big Endian Support The mmWaveLink driver by default is enabled for Little Endian host. Support for Big Endian is provided as compile time option using a Pre-processor Macro MMWL_BIG_ENDIAN. \n For memory optimizations, mmWaveLink doesn't swap the data elements in structure buffer. It is the responsibility of the application to swap multi byte data elements before passing the structure buffer to mmWaveLink API. Since SPI word-size is 16bit, Swap of 32 bit fields such as integer needs to be done at 16bit boundary. @note 1: Please refer latest mmWave device DFP release notes for all known issues and de-featured APIs. \n @note 2: All reserved bits/bytes in API sub blocks shall be programmed with value zero. The functionality of radar device is not guaranteed if reserved bytes are not zero. \n @note 3: All reserved bits/bytes in API message reports shall be masked off. \n * \subsection notes General Notes -# Host should ensure that there is a delay of at least 2 SPI clocks between CS going low and start of SPI clock. -# Host should ensure that CS is toggled for every 16 bits of transfer via SPI. -# There should be a delay of at least 2 SPI Clocks between consecutive CS. -# SPI needs to be operated at Mode 0 (Phase 1, Polarity 0). -# SPI word length should be 16 bit (Half word). * \subsection appl_notes Application Care Abouts -# Retry of RF Power up message is unsupported. -# HOST is recommended to wait for RF Power Async msg before any further APIs are issued. Lack of RF Power up Async msg should be treated as bootup failure. -# It is recommended to wait for Async event for Latent fault injection API before the next CMD is issued. -# HOST to ensure a delay of 30us in response to the HOST_IRQ interrupt, to allow for a SPI DMA configuration in device post HOST_IRQ set high. -# It is recommended to use 232 as the chunk size in mmWavelink/HOST when firmware download is done through SPI. */ /*LDRA_ANALYSIS*/ /**************************************************************************************** * INCLUDE FILES ***************************************************************************************** */ /**************************************************************************************** * FileName : rl_datatypes.h * * Description : This file defines the datatypes. * **************************************************************************************** * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * **************************************************************************************** * Revision History : *--------------------------------------------------------------------------------------- * Version Date Author Defect No Description *--------------------------------------------------------------------------------------- * 0.1 12May2015 Kaushal - Initial Version * **************************************************************************************** */ /**************************************************************************************** * FILE INCLUSION PROTECTION ****************************************************************************** */ /****************************************************************************** * INCLUDE FILES ****************************************************************************** */ /****************************************************************************** * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS ******************************************************************************* */ /*! \brief * Standard C data types typedef */ typedef unsigned char rlUInt8_t; typedef unsigned short rlUInt16_t; typedef unsigned int rlUInt32_t; typedef unsigned long long rlUInt64_t; typedef signed long long rlInt64_t; typedef char rlInt8_t; typedef signed char rlSInt8_t; typedef signed short rlInt16_t; typedef signed int rlInt32_t; typedef void rlVoid_t; /*! \brief * Communication Interface Handle */ typedef void* rlComIfHdl_t; /*! \brief * OS Message Queue Object Handle */ typedef void* rlOsiMsgQHdl_t; /*! \brief * OS Semaphore Object Handle */ typedef void* rlOsiSemHdl_t; /*! \brief * OS Mutex Object Handle */ typedef void* rlOsiMutexHdl_t; /*! \brief * OS Time data type */ typedef rlUInt32_t rlOsiTime_t; /****************************************************************************** * MACRO DEFINITIONS ******************************************************************************* */ /*! \brief * Standard MACROs */ /*! \brief * mmWaveLink Constants for numberic values */ /*! \brief * mmWaveLink Constants for OS delay in milliseconds */ /*! \brief * MACRO for API error checks */ /*! \brief * MACRO for OS Interface error checks */ /*! \brief * MACRO for Communication Interface error checks */ /*! \brief * MACRO for Driver Assert with Line Number */ /*! \brief * Assert Macro */ /*! \brief * MACRO for error checks */ /*! \brief * MACRO for protocol error checks */ /* * END OF RL_DATATYPES_H */ /***************************************************************************************** * MACRO DEFINITIONS ***************************************************************************************** */ /* Export Macro for DLL */ /*! mmWaveLink Version */ /*! mmWaveLink Error Codes */ /*! RF Error Codes */ /*! Frame start stop API */ /*! Channel Config API */ /*! ADC out API */ /*! Low power ADC API */ /*! Dynamic power save API */ /*! HSI config API */ /*! Profile config API */ /*! Chirp config API */ /*! Frame config API */ /*! Advance Frame config API */ /*! Test source config API */ /*! Programmable filter config API */ /*! Per chirp phase shifter API */ /*! Calibration config APIs */ /*! Loopback burst error */ /*! Inter Chirp Block Control Config */ /*! Monitoring config APIs */ /* ADC Config API */ /* Data Path Config API */ /* Lane Enable config API */ /* Lane Clock config API */ /* LVDS config API */ /* Continuous Streaming Mode API */ /* CSI2 Lane Config API */ /* Frame Config Apply API */ /* Advanced Frame Config API */ /*! \brief * mmwavelink MACRO to enable/disable logging. * To enable logging set this MACRO to '0' and set proper function pointer * dbgCb.rlPrint and debug level dbgCb.dbgLevel out of RL_DBG_LEVEL_* during rlDevicePowerOn */ /* mmwavelink MACROs for Error Checks */ /** @note : \n * 1. When Running On MSS: \n * RL_DEVICE_INDEX_INTERNAL_BSS: for radarSS communication \n * RL_DEVICE_INDEX_INTERNAL_DSS_MSS: for DSS communication \n * RL_DEVICE_INDEX_INTERNAL_HOST: for SPI communication \n * 2. When Running On DSS: \n * RL_DEVICE_INDEX_INTERNAL_BSS: for radarSS communication \n * RL_DEVICE_INDEX_INTERNAL_DSS_MSS: for MSS communication \n */ /* AWR1243 Device Map - Max Cascading */ /* Device Index for SubSystem */ /*! \brief * mmWaveLink CRC Types */ /*! \brief * mmWaveLink Execution Home type */ /*! \brief * mmWave Device Types */ /*! \brief * mmWaveLink Debug Levels */ /*! \brief * GPADC sensors macros */ /*! \brief * Swap 2 half words in 32 bit Integer. Required for Big Endian Host */ /****************************************************************************** * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS ****************************************************************************** */ /* DesignId : MMWL_DesignId_001 */ /* Requirements : AUTORADAR_REQ-697, AUTORADAR_REQ-698, AUTORADAR_REQ-699, AUTORADAR_REQ-700, AUTORADAR_REQ-701, AUTORADAR_REQ-702, AUTORADAR_REQ-703, AUTORADAR_REQ-704, AUTORADAR_REQ-705, AUTORADAR_REQ-706, AUTORADAR_REQ-830, AUTORADAR_REQ-831, AUTORADAR_REQ-832, AUTORADAR_REQ-889, AUTORADAR_REQ-890, AUTORADAR_REQ-1002, AUTORADAR_REQ-1006 */ /*! \brief * mmWaveLink API return type */ typedef rlInt32_t rlReturnVal_t; /*! \brief * mmWaveLink Support CRC type */ typedef rlUInt8_t rlCrcType_t; /* Function pointers for spawn task function and event handlers*/ /*! \brief * mmWaveLink Spawn Task Function */ typedef void (*RL_P_OSI_SPAWN_ENTRY)(const void* pValue); /*! \brief * mmWaveLink Event Handler callback */ typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex, void* pValue); /*! \brief * Communication interface(SPI, MailBox, UART etc) callback functions */ typedef struct rlComIfCbs { /** @fn rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags) * *...@brief Open Communication interface * @param[in] deviceIndex - Communication Interface to Open * @param[in] flags - Flags to configure the interface * * @return rlComIfHdl_t Handle to access the communication interface * * Open Communication interface */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-785 */ rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags); /** @fn rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len) * * @brief Read Data from Communication interface * @param[in] fd - Handle to access the communication interface * @param[out] pBuff - Buffer to store data from communication interface * @param[in] len - Read size in bytes * * @return rlInt32_t Length of received data * * Read Data from Communication interface */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-785 */ rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len); /** @fn rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len) * * @brief Write Data over Communication interface * @param[in] fd - Handle to access the communication interface * @param[in] pBuff - Buffer containing data to write over communication interface * @param[in] len - write size in bytes * * @return rlInt32_t Length of data sent * * Write Data over Communication interface */ /* DesignId : */ /* Requirements : AUTORADAR_REQ-785 */ rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len); /** @fn rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd) * * @brief Close the Communication interface * @param[in] fd - Handle to access the communication interface * * @return rlInt32_t Success - 0, Failure - Error code * * Close the Communication interface */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-785 */ rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd); }rlComIfCbs_t; /*! \brief * OS mutex callback functions */ typedef struct rlOsiMutexCbs { /** @fn rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name) * * @brief Create Mutex Object * @param[in] name - Name to associate with Mutex Object * @param[out] mutexHdl - Pointer to Mutex object * * @return rlInt32_t Success - 0, Failure - Error code * * Create Mutex Object */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name); /** @fn rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout) * * @brief Lock Mutex Object * @param[in] mutexHdl - Pointer to Mutex object * @param[in] timeout - Maximum Time to wait for Mutex Lock * * @return rlInt32_t Success - 0, Failure - Error code * * OSI Lock Mutex Object. * mmWaveLink requires this Mutex object to be locked to avoid any parallel API * call for the same device instance. In one of the case when mmWaveLink is * underway for a command-response and device sends Async-event message in between, * so at this instance mmWaveLink will try to lock the same Mutex again. Expectation * is that command-response sequence should complete first and that flow unlocks this Mutex * and then only at other context mmWaveLink will cater the Async-event (HostIrq) request. * mmWaveLink passes timeout as max value, where it expects to lock the Mutex for max period. * Any non-zero return value will be treated as error and mmWaveLink will generate * async-event message [SBID RL_RET_CODE_RADAR_OSIF_ERROR] with payload of error code (-10). * This error async-event will be generated only in the interrupt context while catering any * AWR device's async-event message whereas during the CMD-RSP flow that API will return with * error code (-10). */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout); /** @fn rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl) * * @brief Unlock Mutex Object * @param[in] mutexHdl - Pointer to Mutex object * * @return rlInt32_t Success - 0, Failure - Error code * * Unlock Mutex Object. Any non-zero return value will be treated as error and mmWaveLink * will return its own error code (-10). */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl); /** @fn rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl) * * @brief Destroy Mutex Object * @param[in] mutexHdl - Pointer to Mutex object * * @return rlInt32_t Success - 0, Failure - Error code * * Destroy Mutex Object */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl); }rlOsiMutexCbs_t; /*! \brief * OS semaphore callback functions */ typedef struct rlOsiSemCbs { /** @fn rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name) * * @brief Create Semaphore Object * @param[in] name - Name to associate with Sem Object * @param[out] semHdl - Pointer to Sem object * * @return rlInt32_t Success - 0, Failure - Error code * * Create Semaphore Object */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name); /** @fn rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout) * * @brief Wait for Semaphore * @param[in] semHdl - Pointer to Sem object * @param[in] timeout - Maximum Time to wait for Semaphore * * @return rlInt32_t Success - 0, Failure - Error code * * Wait for Semaphore */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout); /** @fn rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl) * * @brief Release Semaphore * @param[in] semHdl - Pointer to Sem object * * @return rlInt32_t Success - 0, Failure - Error code * * Release Semaphore */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl); /** @fn rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl) * * @brief Destroy Semaphore Object * @param[in] semHdl - Pointer to Sem object * * @return rlInt32_t Success - 0, Failure - Error code * * Destroy Semaphore Object */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl); }rlOsiSemCbs_t; /*! \brief * OS message queue/Spawn callback functions */ typedef struct rlOsiMsgQCbs { /** @fn rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry, void* pValue, rlUInt32_t flags) * * @brief Calls a function in a different context * @param[in] pEntry - Pointer to Entry Function * @param[in] pValue - Pointer to data passed to function * @param[in] flags - Flag to indicate preference * * @return rlInt32_t Success - 0, Failure - Error code * * Calls a function in a different context. mmWaveLink Driver Interrupt handler function * invokes this interface to switch context so that Interrupt Service Routine is executed * immediately. mmWaveLink uses this callback function to invoke 'rlDriverMsgReadSpawnCtx' * funtion to read the async-event message in different interrupt context. Host should * able to handle the error code generated by 'rlDriverMsgReadSpawnCtx' spawned function. */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-784 */ rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry, const void* pValue, rlUInt32_t flags); }rlOsiMsgQCbs_t; /*! \brief * OS services callback functions */ typedef struct rlOsiCbs { /*! \brief * Mutex callback functions. */ rlOsiMutexCbs_t mutex; /*! \brief * Semaphore callback functions. */ rlOsiSemCbs_t sem; /*! \brief * OS message queue/Spawn callback functions. */ rlOsiMsgQCbs_t queue; }rlOsiCbs_t; /*! \brief * mmWaveLink Asynchronous event callback function */ typedef struct rlEventCbs { /** @fn void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t sbId, rlUInt16_t sbLen, * rlUInt8_t *payload) * * @brief Reports Asynchronous events from mmwave radar device such as * device status, exceptions etc * @param[in] devIndex - Device Index to identify source of event * @param[in] subId - Sub-block Id * @param[in] subLen - Sub-block data length * @param[in] payload - Sub-block data starting memory address * * Reports Asynchronous events from mmwave radar device such as * device status, exceptions etc */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-783 */ void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen, rlUInt8_t *payload); }rlEventCbs_t; /*! \brief * mmWaveLink Timer callback functions */ typedef struct rlTimerCbs { rlInt32_t (*rlDelay)(rlUInt32_t delay); }rlTimerCbs_t; /*! \brief * mmWaveLink callback functions for Command parser */ typedef struct rlCmdParserCbs { rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal); rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex); }rlCmdParserCbs_t; /*! \brief * mmWaveLink CRC callback function * @note : Device SPI protocol Limitation for AWR1243: The CRC length of the message * or Async-event shall be multiple of 4 bytes to enable reliable retry recovery * mechanism in case of any checksum failure in a message. */ typedef struct rlCrcCbs { /** @fn rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType, * rlUInt8_t* crc) * * @brief Compute CRC on the input message * @param[in] data - input message * @param[in] dataLen - size of input message in bytes * @param[in] crcType - CRC type (0:RL_CRC_TYPE_16BIT_CCITT, 1:RL_CRC_TYPE_32BIT, * 2:RL_CRC_TYPE_64BIT_ISO) * @param[out] crc - Computed CRC * * @return rlInt32_t Success - 0, Failure - Error code * * Compute CRC on the input message */ /* DesignId : */ /* Requirements : */ rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType, rlUInt8_t* crc); }rlCrcCbs_t; /*! \brief * mmWaveLink Device Control, Interrupt callback functions */ typedef struct rlDeviceCtrlCbs { /** @fn rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex) * * @brief Bring mmWave radar device out of Reset * @param[in] deviceIndex - Index of the device to be enabled * * @return rlInt32_t Success - 0, Failure - Error code * * Bring mmWave radar device out of Reset. Implement this function to assert the nReset * Pin in mmWave device. Optionally It might require to assert Sense on Power(SOP) Pins */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-786 */ rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex); /** @fn rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex) * * @brief Power off mmWave radar device * @param[in] deviceIndex - Index of the device to be disbaled * * @return rlInt32_t Success - 0, Failure - Error code * * Power off mmWave radar device. Implement this function to de-assert the Reset * Pin in mmWave device */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-786 */ rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex); /** @fn void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd) * * @brief Masks Host Interrupt * @param[in] fd - Handle of the device for which interrupt need to be masked * * Masks Host Interrupt. If GPIO Interrupt is Level Triggered, * host need to mask the interrupt until the interrupt is serviced */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-787 */ void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd); /** @fn void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd) * * @brief Unmask Host Interrupt * @param[in] fd - Handle of the device for which interrupt need to be unmasked * * Unmask Host Interrupt. If GPIO Interrupt is Level Triggered, * host need to unmask the interrupt once interrupt is processed */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-787 */ void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd); /** @fn rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow) * * @brief Polls Host Interrupt Status * @param[in] fd - Handle of the device for which interrupt need to be polled * @param[in] highLow - Wait for IRQ Level(high/low) * * @return rlInt32_t IRQ Line Low - 0, IRQ Line High - 1 * * mmWave Radar device asserts host IRQ pin to get Host attention. After receiving host * interrupt, host polls Host Interrupt Status, Low on Host IRQ indicate that mmWave device * has written data on communication Interface. This callback should Wait for the IRQ status. * The function waits for the IRQ Level(low/high) based on second argument returns once the * IRQ Level occurs. If HostIRQ is not toggled within timeout (less than ackTimeout), it * should return '-1' value so that it won't be blocked for infinite duration. */ /* DesignId :MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-787 */ rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow); /** @fn rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow) * * @brief It assert/de-assert Host IRQ hig/low on MSS to Host for SPI communication * @param[in] highLow - High/low value for Host IRQ * * @return rlUInt16_t Success - 0, Failure - Error code * * It assert/de-assert Host IRQ hig/low on MSS to Host for SPI communication */ /* DesignId : MMWL_DesignId_004 */ /* Requirements : AUTORADAR_REQ-787 */ rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow); /** @fn rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex, * RL_P_EVENT_HANDLER pHandler, void* pValue) * * @brief Register Host Interrupt Handler * @param[in] deviceIndex - Device Index to identify source of Host Interrupt * @param[in] pHandler - Interrupt Handler routine * @param[in] pValue - To Pass any additional data * * @return rlInt32_t Success - 0, Failure - Error code * * Register Host Interrupt Handler. The Application should store this function handler * and invoke when it receives host Interrupt. The application need to enable GPIO interrupt * in this callback. Event Handler Callback doesn't process the interrupt in the same context * so it is safe to call this handler from ISR directly. */ /* DesignId : MMWL_DesignId_026 */ /* Requirements : AUTORADAR_REQ-777 */ rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex, RL_P_EVENT_HANDLER pHandler, void* pValue); }rlDeviceCtrlCbs_t; /*! \brief * mmWaveLink print function prototype */ typedef rlInt32_t (*rlPrintFptr)(const rlInt8_t* format, ...); /*! \brief * mmWaveLink debug callback structure */ typedef struct rlDbgCb { /** @fn rlInt32_t (*rlPrint)(const rlInt8_t* format, ...) * * @brief Print input message as per the format in the input arguments * @param[in] format - Format of message and arguments to be printed * @param[in] ... - Multiple input arguments to be printed * * @return rlInt32_t Success- Length of the message written in user's output console in bytes * Failure- Negative value * * Print input message as per the format in the input arguments */ /* DesignId : */ /* Requirements : */ rlPrintFptr rlPrint; /** * @brief User needs to set debug level such as error, warning, debug, verbose */ rlUInt8_t dbgLevel; }rlDbgCb_t; /*! \brief * mmWaveLink client callback structure */ typedef struct rlClientCbs { /** * @brief Comunication Interface Callback */ rlComIfCbs_t comIfCb; /** * @brief Operating System Callback */ rlOsiCbs_t osiCb; /** * @brief Event Callback, required to receive notification */ rlEventCbs_t eventCb; /** * @brief Device Control Callback */ rlDeviceCtrlCbs_t devCtrlCb; /** * @brief Timer Callback, required when ACK is enabled */ rlTimerCbs_t timerCb; /** * @brief Call back for parsing the Command received at MSS from the Host TI Internal Use only */ rlCmdParserCbs_t cmdParserCb; /** * @brief CRC Callback, required when CRC is enabled */ rlCrcCbs_t crcCb; /** * @brief CRC Types rlCrcType_t 16/32/64 */ rlCrcType_t crcType; /** * @brief ACK wait timeout in Milliseconds, 0 - No ACK Configuration of the timeout should consider interrupt latency in the processor. */ rlUInt32_t ackTimeout; /** * @brief 0x0: mmWaveLink runs on Ext Host, \n 0x1: mmWaveLink runs on MSS, \n 0x2: mmWaveLink runs on DSS \n */ rlUInt8_t platform; /** * @brief xWR1243 + HOST = 0x0, xWR1443 MSS = 0x1, xWR1642 MSS/DSS = 0x2, \n xWR1843 MSS/DSS = 0x3, xWR6843 MSS/DSS = 0x4 \n */ rlUInt8_t arDevType; /** * @brief Debug Callback, required to receive Debug information */ rlDbgCb_t dbgCb; }rlClientCbs_t; /*! \brief * mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB * @note : The functional APIs shall be sent to radar device only after receiving * RL_DEV_AE_MSSPOWERUPDONE_SB Async-event after power cycle. * In case of boot over SPI then functional APIs shall be sent to radar device only after * receiving AWR_AE_MSS_BOOTERRORSTATUS_SB Async-event. */ typedef struct rlInitComplete { /** * @brief masterSS powerup time, 1LSB = 5ns */ rlUInt32_t powerUpTime; /** * @brief masterSS Bootup Status over SPI, 0 - PASS, 1- Fail \n Bit Error-description \n 0 certificate authentication failure \n 1 certificate parser failure \n 2 Rprc image1 authentication failure \n 3 Rprc image2 authentication failure \n 4 Rprc image3 authentication failure \n 5 Rprc header not found \n 6 Meta header not found \n 7 S/W anti roll back check failure \n 8 Efuse integrity failure \n 9 certificate field validity failure \n 10 certificate field invalid authentication key index \n 11 certificate field invalid hash type \n 12 certificate field invalid subsystem \n 13 certificate field invalid decrypt key index \n 14 certificate field check efuse mismatch \n 15 certificate field check 1 efuse mismatch \n 16 certificate field check 2 efuse mismatch \n 17 certificate field invalid subsystem bank allocation \n 18 certificate field invalid total banks allocation \n 19 Rprc parser file length mismatch \n 20 Rprc parser MSS file offset mismatch \n 21 Rprc parser BSS file offset mismatch \n 22 Rprc parser DSS file offset mismatch \n 23 certificate field invalid decrypt key \n 24 certificate field invalid authentication key \n 25 HS device certificate not present \n 26 Error in 2K image \n 27 Shared memory allocation failed \n 28 MSS image not found \n 29 Meta header num files error \n 30 Meta header CRC failure \n 31 Rprc image authentication failure \n */ rlUInt32_t powerUpStatus1; /** * @brief masterSS Bootup Status over SPI, 0 - PASS, 1- Fail \n Bit Error-description \n 0 Rprc parser config file offset mismatch \n 1 Boot extension extraction failure \n 2 Device user ID bad size \n 3 Key derived function bad size \n 4 HMAC bad size \n 5 AES initialization vector bad size \n 6 Secure dev TI key erase failure \n 7 SOP5 SFlash not found \n 16 XTAL clock detection failure \n 17 Continue bootup on XTAL \n 18 DSP powerup timeout error \n 19 MSS LBIST failure \n 20 DSP LBIST PBIST failure \n 21 PBIST single port memory failure \n 22 PBIST two port memory failure \n 23 Memory init failure \n 24 MSS ROM PBIST CRC computation failure \n 25 VMON error detected \n 31 ESM NERROR detected \n */ rlUInt32_t powerUpStatus2; /** * @brief masterSS Boot Test Status, 0 - PASS, 1 - FAIL \n Bit Status Information \n 0 MibSPI self-test \n 1 DMA self-test \n 2 RESERVED \n 3 RTI self-test \n 4 ESM self-test \n 5 EDMA self-test \n 6 CRC self-test \n 7 VIM self-test \n 8 MPU self-test \n 9 Mailbox self-test \n 10 RESERVED \n 11 RESERVED \n 12 RESERVED \n 13 MibSPI single bit error test \n 14 MibSPI double bit error test \n 15 DMA Parity error test \n 16 TCMA Single bit error test \n 17 TCMB Single bit error test \n 18 RESERVED \n 19 RESERVED \n 20 RESERVED \n 21 RESERVED \n 22 VIM lockstep test \n 23 CCM R4 lockstep test \n 24 DMA MPU region test \n 25 MSS Mailbox single bit error test \n 26 MSS Mailbox double bit error test \n 27 BSS Mailbox single bit error test \n 28 BSS Mailbox double bit error test \n 29 EDMA MPU test \n 30 EDMA parity test \n 31 RESERVED \n */ rlUInt32_t bootTestStatus1; /** * @brief masterSS Boot Test Status, 0 - PASS, 1 - FAIL \n Bit Status Information \n 0 RESERVED \n 1 RESERVED \n 2 PCR test \n 3 VIM RAM parity test \n 4 SCI boot time test \n 31:5 RESERVED \n */ rlUInt32_t bootTestStatus2; }rlInitComplete_t; /*! \brief * mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB * @note : Bootup digital monitoring status are not applicable for QM devices */ typedef struct rlStartComplete { /** * @brief radarSS Boot Status, 1 - PASS, 0 - FAIL \n Bit Status Information \n 0 ROM CRC check \n 1 CR4 and VIM lockstep test \n 2 RESERVED \n 3 VIM test (Not supported in 1st Gen devices, refer latest release note) \n 4 STC test of diagnostic \n 5 CR4 STC \n 6 CRC test \n 7 RAMPGEN memory ECC test \n 8 DFE Parity test (RESERVED in xWR6x43 devices) \n 9 DFE memory ECC \n 10 RAMPGEN lockstep test \n 11 FRC lockstep test \n 12 DFE memory PBIST \n 13 RAMPGEN memory PBIST \n 14 PBIST test \n 15 WDT test \n 16 ESM test \n 17 DFE STC \n 18 RESERVED \n 19 ATCM, BTCM ECC test \n 20 ATCM, BTCM parity test \n 21 RESERVED \n 22 RESERVED \n 23 RESERVED \n 24 FFT test \n 25 RTI test \n 26 PCR test \n 27-31 RESERVED */ rlUInt32_t status; /** * @brief radarSS powerup time, 1LSB = 5ns */ rlUInt32_t powerUpTime; /** * @brief Reserved for future use */ rlUInt32_t reserved0; /** * @brief Reserved for future use */ rlUInt32_t reserved1; }rlStartComplete_t; /*! \brief * Structure to hold the MSS ESM Fault data structure for event RL_DEV_AE_MSS_ESMFAULT_SB * @note : The FRC lockstep fatal error(BSS module error) is connected to MSS ESM Group 1 lines, * This fatal error must be handled in Host in AWR1243 device (MSS or DSS in xWR1642, * xWR1843 and xWR6843 devices) */ typedef struct rlMssEsmFault { /** * @brief Bits Definition (0 -- No Error , 1 -- ESM Error) 0 NERROR in sync \n 1 RESERVED \n 2 DMA MPU Region tests \n 3 DMA Parity error \n 4 RESERVED \n 5 RESERVED \n 6 DSS CSI parity error \n 7 TPCC parity error \n 8 CBUF ECC single bit error \n 9 CBUF ECC double bit error \n 10 RESERVED \n 11 RESERVED \n 12 RESERVED \n 13 Error response from the Peripheral when a DMA transfer is done \n 14 RESERVED \n 15 VIM RAM double bit errors \n 16 RESERVED \n 17 MibSPI double bit error test \n 18 DSS TPTC0 read MPU error \n 19 RESERVED \n 20 VIM RAM single bit errors \n 21 RESERVED \n 22 FRC Lockstep error \n 23 RESERVED \n 24 RESERVED \n 25 MibSPI single bit error test \n 26 TCMB0 RAM single bit errors \n 27 STC error \n 28 TCMB1 RAM single bit errors \n 29 DSS TPTC0 write MPU error \n 30 DCC compare error \n 31 CR4F self-test error.(test of error path by error forcing) \n */ rlUInt32_t esmGrp1Err; /** * @brief Bits Definition \n 0 TCMA RAM single bit errors \n 1 RESERVED \n 2 RESERVED \n 3 DSS TPTC1 read MPU error \n 4 DSS TPTC1 write MPU error \n 5 RESERVED \n 6 Access error interrupt from FFT ACC \n 7 VIM Self-Test Error \n 8 RESERVED \n 9 RESERVED \n 10 RESERVED \n 11 RESERVED \n 12 RESERVED \n 13 RESERVED \n 14 RESERVED \n 15 RESERVED \n 16 RESERVED \n 17 RESERVED \n 18 RESERVED \n 19 RESERVED \n 20 RESERVED \n 21 RESERVED \n 22 RESERVED \n 23 RESERVED \n 24 RESERVED \n 25 radarSS to MSS ESM G2 Trigger \n 26 radarSS Mailbox single bit errors \n 27 radarSS Mailbox double bit errors \n 28 MSS Mailbox single bit errors \n 29 MSS Mailbox double bit errors \n 30 RESERVED \n 31 RESERVED \n */ rlUInt32_t esmGrp2Err; /** * @brief Reserved for future use */ rlUInt32_t reserved0; /** * @brief Reserved for future use */ rlUInt32_t reserved1; }rlMssEsmFault_t; /*! \brief * Structure to hold the MSS Boot error status data strucutre when booted over SPI * for event RL_DEV_AE_MSS_BOOTERRSTATUS_SB * @note : The functional APIs shall be sent to radar device only after receiving * RL_DEV_AE_MSS_BOOTERRSTATUS_SB Async-event after boot over SPI (Flash is not connected). */ typedef struct rlMssBootErrStatus { /** * @brief masterSS powerup time, 1LSB = 5ns */ rlUInt32_t powerUpTime; /** * @brief masterSS Bootup Status over SPI, 0 - PASS, 1- Fail \n Bit Error-description \n 0 certificate authentication failure \n 1 certificate parser failure \n 2 Rprc image1 authentication failure \n 3 Rprc image2 authentication failure \n 4 Rprc image3 authentication failure \n 5 Rprc header not found \n 6 Meta header not found \n 7 S/W anti roll back check failure \n 8 Efuse integrity failure \n 9 certificate field validity failure \n 10 certificate field invalid authentication key index \n 11 certificate field invalid hash type \n 12 certificate field invalid subsystem \n 13 certificate field invalid decrypt key index \n 14 certificate field check efuse mismatch \n 15 certificate field check 1 efuse mismatch \n 16 certificate field check 2 efuse mismatch \n 17 certificate field invalid subsystem bank allocation \n 18 certificate field invalid total banks allocation \n 19 Rprc parser file length mismatch \n 20 Rprc parser MSS file offset mismatch \n 21 Rprc parser BSS file offset mismatch \n 22 Rprc parser DSS file offset mismatch \n 23 certificate field invalid decrypt key \n 24 certificate field invalid authentication key \n 25 HS device certificate not present \n 26 Error in 2K image \n 27 Shared memory allocation failed \n 28 MSS image not found \n 29 Meta header num files error \n 30 Meta header CRC failure \n 31 Rprc image authentication failure \n */ rlUInt32_t powerUpStatus1; /** * @brief masterSS Bootup Status over SPI, 0 - PASS, 1- Fail \n Bit Error-description \n 0 Rprc parser config file offset mismatch \n 1 Boot extension extraction failure \n 2 Device user ID bad size \n 3 Key derived function bad size \n 4 HMAC bad size \n 5 AES initialization vector bad size \n 6 Secure dev TI key erase failure \n 7 SOP5 SFlash not found \n 16 XTAL clock detection failure \n 17 Continue bootup on XTAL \n 18 DSP powerup timeout error \n 19 MSS LBIST failure \n 20 DSP LBIST PBIST failure \n 21 PBIST single port memory failure \n 22 PBIST two port memory failure \n 23 Memory init failure \n 24 MSS ROM PBIST CRC computation failure \n 25 VMON error detected \n 31 ESM NERROR detected \n */ rlUInt32_t powerUpStatus2; /** * @brief masterSS Boot Test Status, 0 - PASS, 1 - FAIL \n Bit Status Information \n 0 MibSPI self-test \n 1 DMA self-test \n 2 RESERVED \n 3 RTI self-test \n 4 ESM self-test \n 5 EDMA self-test \n 6 CRC self-test \n 7 VIM self-test \n 8 MPU self-test \n 9 Mailbox self-test \n 10 RESERVED \n 11 RESERVED \n 12 RESERVED \n 13 MibSPI single bit error test \n 14 MibSPI double bit error test \n 15 DMA Parity error test \n 16 TCMA Single bit error test \n 17 TCMB Single bit error test \n 18 RESERVED \n 19 RESERVED \n 20 RESERVED \n 21 RESERVED \n 22 VIM lockstep test \n 23 CCM R4 lockstep test \n 24 DMA MPU region test \n 25 MSS Mailbox single bit error test \n 26 MSS Mailbox double bit error test \n 27 BSS Mailbox single bit error test \n 28 BSS Mailbox double bit error test \n 29 EDMA MPU test \n 30 EDMA parity test \n 31 RESERVED \n */ rlUInt32_t bootTestStatus1; /** * @brief masterSS Boot Test Status, 0 - PASS, 1 - FAIL \n Bit Status Information \n 0 RESERVED \n 1 RESERVED \n 2 PCR test \n 3 VIM RAM parity test \n 4 SCI boot time test \n 31:5 RESERVED \n */ rlUInt32_t bootTestStatus2; }rlMssBootErrStatus_t; /*! \brief * Structure to hold the test status report of the latent fault tests data strucutre * for event RL_DEV_AE_MSS_LATENTFLT_TEST_REPORT_SB */ typedef struct rlMssLatentFaultReport { /** * @brief 1 - PASS, 0 - FAIL \n Bits Definition \n 0 RESERVED \n 1 DMA self-test \n 2 RESERVED \n 3 RTI self-test \n 4 RESERVED \n 5 EDMA self-test \n 6 CRC self-test \n 7 VIM self-test \n 8 RESERVED \n 9 Mailbox self-test \n 10 RESERVED \n 11 RESERVED \n 12 Generating NERROR \n 13 MibSPI single bit error test \n 14 MibSPI double bit error test \n 15 DMA Parity error \n 16 TCMA RAM single bit errors (Not supported, refer latest release note) \n 17 TCMB RAM single bit errors (Not supported, refer latest release note) \n 18 TCMA RAM double bit errors (Not supported, refer latest release note) \n 19 TCMB RAM double bit errors (Not supported, refer latest release note) \n 20 TCMA RAM parity errors (Not supported, refer latest release note) \n 21 TCMB RAM parity errors (Not supported, refer latest release note) \n 22 RESERVED \n 23 RESERVED \n 24 DMA MPU Region tests \n 25 MSS Mailbox single bit errors \n 26 MSS Mailbox double bit errors \n 27 radarSS Mailbox single bit errors \n 28 radarSS Mailbox double bit errors \n 29 EDMA MPU test \n 30 EDMA parity test \n 31 CSI2 parity test \n */ rlUInt32_t testStatusFlg1; /** * @brief 1 - PASS, 0 - FAIL \n Bits Definition \n 0 RESERVED \n 1 RESERVED \n 2 RESERVED \n 3 VIM RAM parity test \n 4 SCI boot time test \n 31:5 RESERVED \n */ rlUInt32_t testStatusFlg2; /** * @brief Reserved for future use */ rlUInt32_t reserved; }rlMssLatentFaultReport_t; /*! \brief * Structure to hold data strucutre for test status of the periodic tests * for event RL_DEV_AE_MSS_PERIODIC_TEST_STATUS_SB */ typedef struct rlMssPeriodicTestStatus { /** * @brief 1 - PASS, 0 - FAIL \n Bits Definition \n 0 Periodic read back of static registers \n 1 ESM self-test \n 31:2 RESERVED \n */ rlUInt32_t testStatusFlg; /** * @brief Reserved for future use */ rlUInt32_t reserved; }rlMssPeriodicTestStatus_t; /*! \brief * Structure to hold data strucutre for RF-error status send by MSS * for event RL_DEV_AE_MSS_RF_ERROR_STATUS_SB */ typedef struct rlMssRfErrStatus { /** * @brief Value Definition \n 0 No fault \n 1 radarSS FW assert \n 2 radarSS FW abort \n 3 radarSS ESM GROUP1 ERROR \n 4 radarSS ESM GROUP2 ERROR \n 6:5 RESERVED \n 7 BSS monitoring failure in Mode 1(Quiet mode) \n 31:8 RESERVED \n */ rlUInt32_t errStatusFlg; /** * @brief Reserved for future use */ rlUInt32_t reserved; }rlMssRfErrStatus_t; /*! \brief * Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB * @note : The Programmable filter Parity error and double bit ECC errors are fatal errors but * connected to ESM Group 1 lines, these shuld be treated as fatal errors on the Host . * (MSS or DSS in xWR1642, xWR1843 and xWR6843 devices) */ typedef struct rlBssEsmFault { /** * @brief Bits Definition (0 -- No Error , 1 -- ESM Error) 0 Ramp gen sub block error \n 1 RESERVED \n 2 GPADC RAM sub block error \n 3 VIM RAM sub block error \n 4 DFE self test error (RESERVED in xWR6x43 devices) \n 5 VIM self test error \n 6 B0 TCM sub block error \n 7 B1 TCM sub block error \n 8 CCMR4 selftest error \n 9 ATCM sub block error \n 10 Ramp gen self test error \n 11 Ramp gen parity self test error \n 12 Sequence extinguisher self test error \n 13 Sequence extinguisher sub block error \n 14 Programmable Filter Fatal Parity error (RESERVED in xWR6x43 devices) \n 15 AGC RAM sub block error \n 16 B1 TCM parity check error \n 17 B0 TCM parity check error \n 18 ATCM parity check error \n 19 Mailbox MSS to BSS sub block error \n 20 Mailbox BSS to MSS sub block error \n 24:21 RESERVED \n 25 Programmable Filter Fatal DB ECC error \n 31:26 RESERVED \n */ rlUInt32_t esmGrp1Err; /** * @brief Bits Definition \n 0 DFE STC error \n 1 CR4 STC error \n 2 CCMR4 comparator error \n 3 B0TCM DB error \n 4 B1TCM DB error \n 5 ATCM DB error \n 6 DCC error \n 7 Sequence extinguisher error \n 8 Synthesizer frequency monitoring error \n 9 DFE parity error \n 10 Ramp gen DB error \n 11 Bubble correctin fail \n 12 Ramp gen lockstep error \n 13 RTI reset error \n 14 GPADC RAM DB error \n 15 VIM comparator error \n 16 CR4 live clock error \n 17 Watch dog timer NMI error \n 18 VIM RAM DB error \n 19 Ramp gen parity error \n 20 Sequence extinguisher DB error \n 21 DMA MPU error \n 22 AGC RAM DB error \n 23 CRC comparator error \n 24 Wakeup status error \n 25 Short circuit error \n 26 B1 TCM parity error \n 27 B0 TCM parity error \n 28 ATCM parity error \n 29 Mailbox MSS to BSS DB error \n 30 Mailbox BSS to MSS DB error \n 31 CCC error \n */ rlUInt32_t esmGrp2Err; }rlBssEsmFault_t; /*! \brief * This sub block indicates fault in analog supplies or LDO short circuit condition. Once a fault * is detected the functionality cannot be resumed from then on and the sensor needs to be * re-started. This Async Event is generated with SB-ID RL_DEV_AE_MSS_VMON_ERROR_STATUS_SB. * @note : This API Async Event is not supported. */ typedef struct rlVmonErrStatus { /** * @brief Value Definition \n * 0 NO FAULT \n * 1 ANALOG_SUPPLY_FAULT \n * Others RESERVED \n */ rlUInt8_t faultType; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief Fault signature \n * Bit Definition \n * 0 VDDIN under voltage indication \n * 1 VDDIN over voltage indication \n * 2 VIN_18CLK supply fault \n * 3 VIOIN supply fault (Unable to resolve between 1.8V and 3.3V) \n * 4 VIN_SRAM under voltage indication \n * 5 VIOIN_18 supply fault \n * 6 APLL_VCO_LDO short circuit \n * 31:7 RESERVED */ rlUInt32_t faultSig; /** * @brief Reserved for future use */ rlUInt32_t reserved2; }rlVmonErrStatus_t; /*! \brief * This async event is in response to the command (RL_DEV_CONFIG_SET_MSG: * RL_DEV_RX_DATA_PATH_CONF_SET_SB) which indicates ADC data needs to be transferred over * SPI. This async event contains the ADC data followed by more such async events for * additional data. SB-ID : RL_DEV_AE_MSS_ADC_DATA_SB */ typedef struct rlRcvAdcData { /** * @brief Number of remaining chunks expected. (Remaining length / 220 bytes) */ rlUInt16_t remChunks; /** * @brief ADC data captured by the MMIC. Variable length [4-220] Bytes. */ rlSInt8_t adcData[220U]; }rlRcvAdcData_t; /*! \brief * mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB */ typedef struct rlRfInitComplete { /** * @brief RF Calibration Status, bit value: 1 - SUCCESS, 0 - FAILURE \n Bit Calibration \n 0 RESERVED \n 1 APLL tuning \n 2 SYNTH VCO1 tuning \n 3 SYNTH VCO2 tuning \n 4 LODIST calibration \n 5 RX ADC DC offset calibration \n 6 HPF cutoff calibration \n 7 LPF cutoff calibration \n 8 Peak detector calibration \n 9 TX Power calibration \n 10 RX gain calibration \n 11 TX Phase calibration \n 12 RX IQMM calibration \n 31:13 [Reserved] \n @note : CALIBRATION_STATUS should be checked only if CALIBRATION_ENABLE \n bit is set to 1. \n */ rlUInt32_t calibStatus; /** * @brief this field is set only for updated calibration. It has same bit definition as \n CALIBRATION_STATUS \n */ rlUInt32_t calibUpdate; /** * @brief Measured temperature, based on average of temperature sensors near all enabled TX \n and RX channels at the time of calibration. \n 1 LSB = 1o Celsius \n */ rlUInt16_t temperature; /** * @brief Reserved for future use */ rlUInt16_t reserved0; /** * @brief This field indicates when the calibration updates were performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; /** * @brief Reserved for future use */ rlUInt32_t reserved1; }rlRfInitComplete_t; /*! \brief * mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB */ typedef struct rlRfRunTimeCalibReport { /** * @brief 1 = calibration is passed, 0 = calibration is failed or not enabled/performed at \n least once. \n Bit: Calibration \n 0: [Reserved] \n 1: APLL tuning \n 2: SYNTH VCO1 tuning \n 3: SYNTH VCO2 tuning \n 4: LODIST calibration \n 5: [Reserved] \n 6: [Reserved] \n 7: [Reserved] \n 8: PD calibration \n 9: TX Power calibration \n 10: RX gain calibration \n 11: [Reserved] \n 12: [Reserved] \n 31:13: [Reserved] \n */ rlUInt32_t calibErrorFlag; /** * @brief Whether each calibration resulted in a reconfiguration of RF is indicated by a \n value of 1 in the respective bit in this field. It has bit definition as \n above \n */ rlUInt32_t calibUpdateStatus; /** * @brief Measured temperature, based on average of temperature sensors near all enabled \n TX and RX channels at the time of calibration. \n Note that this temperature will be updated only when a run-time calibration is executed due to a change in temperature by more than 10 deg C. \n 1 LSB = 1 degree Celsius \n */ rlInt16_t temperature; /** * @brief Reserved for future use */ rlUInt16_t reserved0; /** * @brief This field indicates when the calibration updates were performed. \n 1 LSB = 1 millisecond \n (the stamp rolls over upon exceeding allotted bit width) \n */ rlUInt32_t timeStamp; /** * @brief Reserved for future use */ rlUInt32_t reserved1; }rlRfRunTimeCalibReport_t; /*! \brief * API APLL closed loop cal Status Get Sub block structure */ typedef struct rlRfApllCalDone { rlUInt16_t apllClCalStatus; /** * @brief Tolerance */ rlUInt16_t cccTolerance; /** * @brief Window */ rlUInt16_t cccCount0; /** * @brief Measured 0.1/3 MHz Unit */ rlUInt16_t measFreqCount; /** * @brief Expected */ rlUInt32_t cccCount1; }rlRfApllCalDone_t; /*! \brief * Structure to hold the MSS/radarSS CPU Fault data strucutre for * event RL_DEV_AE_MSS_CPUFAULT_SB and RL_RF_AE_CPUFAULT_SB * @note : All the Monitoring Async events will be sent out periodically at calibMonTimeUnit * frame rate (FTTI). The RadarSS/BSS has a queue to hold max 8 transmit API messages * (AEs or Responses), the host shall service all the AEs before start of the next FTTI * epoch to avoid RadarSS Queue full CPU fault fatal error. */ typedef struct rlCpuFault { /** * @brief 0x0 RF Processor Undefined Instruction Abort \n 0x1 RF Processor Instruction pre-fetch Abort \n 0x2 RF Processor Data Access Abort \n 0x3 RF Processor Firmware Fatal Error \n 0x4 - 0xFF Reserved \n */ rlUInt8_t faultType; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Valid only in case of FAULT type is 0x3, provides the source \n line number at which fatal error occurred. \n */ rlUInt16_t lineNum; /** * @brief The instruction PC address at which Fault occurred */ rlUInt32_t faultLR; /** * @brief The return address of the function from which fault function \n has been called (Call stack LR) \n */ rlUInt32_t faultPrevLR; /** * @brief The CPSR register value at which fault occurred */ rlUInt32_t faultSpsr; /** * @brief The SP register value at which fault occurred */ rlUInt32_t faultSp; /** * @brief The address access at which Fault occurred (valid only for fault \n type 0x0 to 0x2) \n */ rlUInt32_t faultAddr; /** * @brief The status of Error (Error Cause type - valid only for \n fault type 0x0 to 0x2) \n 0x000 BACKGROUND_ERR \n 0x001 ALIGNMENT_ERR \n 0x002 DEBUG_EVENT \n 0x00D PERMISSION_ERR \n 0x008 SYNCH_EXTER_ERR \n 0x406 ASYNCH_EXTER_ERR \n 0x409 SYNCH_ECC_ERR \n 0x408 ASYNCH_ECC_ERR \n */ rlUInt16_t faultErrStatus; /** * @brief The Source of the Error (Error Source type- valid only for fault type 0x0 to 0x2)\n 0x0 ERR_SOURCE_AXI_MASTER \n 0x1 ERR_SOURCE_ATCM \n 0x2 ERR_SOURCE_BTCM \n */ rlUInt8_t faultErrSrc; /** * @brief The AXI Error type (Error Source type - valid only for fault type 0x0 to 0x2) \n 0x0 AXI_DECOD_ERR \n 0x1 AXI_SLAVE_ERR \n */ rlUInt8_t faultAxiErrType; /** * @brief The Error Access type (Error Access type- valid only for fault type 0x0 to 0x2) \n 0x0 READ_ERR \n 0x1 WRITE_ERR \n */ rlUInt8_t faultAccType; /** * @brief The Error Recovery type (Error Recovery type - Valid only for fault \n type 0x0 to 0x2) \n 0x0 UNRECOVERY \n 0x1 RECOVERY \n */ rlUInt8_t faultRecovType; /** * @brief Reserved for future use */ rlUInt16_t reserved1; }rlCpuFault_t; /*! \brief * mmWaveLink firmware version structure */ typedef struct rlFwVersionParam { /** * @brief HW variant number */ rlUInt8_t hwVarient; /** * @brief HW version major number */ rlUInt8_t hwMajor; /** * @brief HW version minor number */ rlUInt8_t hwMinor; /** * @brief FW version major number */ rlUInt8_t fwMajor; /** * @brief FW version major number */ rlUInt8_t fwMinor; /** * @brief FW version build number */ rlUInt8_t fwBuild; /** * @brief FW version debug number */ rlUInt8_t fwDebug; /** * @brief FW Release Year */ rlUInt8_t fwYear; /** * @brief FW Release Month */ rlUInt8_t fwMonth; /** * @brief FW Release Day */ rlUInt8_t fwDay; /** * @brief Patch version major number */ rlUInt8_t patchMajor; /** * @brief Patch version minor number */ rlUInt8_t patchMinor; /** * @brief Patch Release Year */ rlUInt8_t patchYear; /** * @brief Patch Release Month */ rlUInt8_t patchMonth; /** * @brief Patch Release Day */ rlUInt8_t patchDay; /** * @brief Debug and build version * b3:0 Debug version * b7:4 Build version */ rlUInt8_t patchBuildDebug; }rlFwVersionParam_t; /*! \brief * mmwavelink software version structure */ typedef struct rlSwVersionParam { /** * @brief SW version major number */ rlUInt8_t major; /** * @brief SW version minor number */ rlUInt8_t minor; /** * @brief SW version buid number */ rlUInt8_t build; /** * @brief SW version debug number */ rlUInt8_t debug; /** * @brief Software Release Year */ rlUInt8_t year; /** * @brief Software Release Month */ rlUInt8_t month; /** * @brief Software Release Day */ rlUInt8_t day; /** * @brief Reserved for future use */ rlUInt8_t reserved; }rlSwVersionParam_t; /*! \brief * mmwavelink version structure */ typedef struct rlVersion { /** * @brief Master Sub System version */ rlFwVersionParam_t master; /** * @brief RF Sub System version */ rlFwVersionParam_t rf; /** * @brief mmWaveLink version */ rlSwVersionParam_t mmWaveLink; }rlVersion_t; /*! \brief * GPADC measurement data for sensors */ typedef struct rlGpAdcData { /** * @brief Min value of GP ADC data */ rlUInt16_t min; /** * @brief Max value of GP ADC data */ rlUInt16_t max; /** * @brief Avg value of GP ADC data */ rlUInt16_t avg; } rlGpAdcData_t; /*! \brief * Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB */ typedef struct rlRecvdGpAdcData { /** * @brief collected all GP ADC data */ rlGpAdcData_t sensor[(6U)]; /** * @brief Reserved for future use */ rlUInt16_t reserved0[4U]; /** * @brief Reserved for future use */ rlUInt32_t reserved1[7U]; } rlRecvdGpAdcData_t; /*! \brief * Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB */ typedef struct rlAnalogFaultReportData { /** * @brief Indicates the analog fault type * Value Definition * 0 No fault * 1 Analog supply fault * Others RESERVED */ rlUInt8_t faultType; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief Indicates which analog supply is in fault * Bit Definition * 0 1.8V BB Analog supply fault * 1 1.3V/1.0V RF supply fault * 2 Synth VCO LDO short circuit detected * 3 PA LDO short circuit detected * 31:4 RESERVED */ rlUInt32_t faultSig; /** * @brief Reserved for future use */ rlUInt32_t reserved2; } rlAnalogFaultReportData_t; /*! \brief * Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB * @note : In QM devices (non safety), Periodic Digital and Analog Monitoring are not supported. */ typedef struct rlCalMonTimingErrorReportData { /** * @brief [b0] 1 = Total monitoring time does not fit in one CALIB_MON_TIME_UNIT when one \n time calibration is enabled, \n 0 = No failure \n [b1] 1 = Total monitoring and calibration time don't fit in one calibMonTimeUnit \n when periodic calibration is enabled, \n 0 = No failure \n [b2] 1 = Runtime timing violation: Monitoring functions or calibrations could \n not be completed in one calibMonTimeUnit, \n 0 = No failure \n [b3-b15] RESERVED \n */ rlUInt16_t timingFailCode; rlUInt16_t reserved; }rlCalMonTimingErrorReportData_t; /*! \brief * Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB */ typedef struct rlDigLatentFaultReportData { /** * @brief 1 - PASS, 0 - FAIL \n Bit Definition \n 0 RESERVED \n 1 CR4_VIM_LOCKSTEP_MONITORING \n 2 RESERVED \n 3 VIM_MONITORING \n 4 RESERVED \n 5 RESERVED \n 6 CRC_MONITORING \n 7 RAMPGEN_ECC_MONITORING (Not supported in 1st Gen devices, refer latest release note) \n 8 DFE_PARITY_MONITORNG (RESERVED in xWR6x43 devices) \n 9 DFE_ECC_MONITORING \n 10 RAMPGEN_LOCKSTEP_MONITORING \n 11 FRC_LOCKSTEP_MONITORING \n 12 RESERVED \n 13 RESERVED \n 14 RESERVED \n 15 RESERVED \n 16 ESM_MONITORING \n 17 DFE_STC_MONITORING \n 18 RESERVED \n 19 ATCM_BTCM_ECC_MONITORING \n 20 ATCM_BTCM_PARITY_MONITORING \n 21 RESERVED \n 22 RESERVED \n 23 RESERVED \n 24 FFT_MONITORING \n 25 RTI_MONITORING \n 31:26 RESERVED \n */ rlUInt32_t digMonLatentFault; }rlDigLatentFaultReportData_t; /*! \brief * The report header includes common information across all enabled monitors * like current FTTI number and current temperature. event: RL_RF_AE_MON_REPORT_HEADER_SB */ typedef struct rlMonReportHdrData { /** * @brief FTTI free running counter value, incremented every CAL_MON_TIME_UNIT */ rlUInt32_t fttiCount; /** * @brief Average temperature at which was monitoring performed \n * 1 LSB = 1 deg C */ rlUInt16_t avgTemp; /** * @brief Reserved for future use \n */ rlUInt16_t reserved0; /** * @brief Reserved for future use */ rlUInt32_t reserved1; }rlMonReportHdrData_t; /*! \brief * This async event is sent periodically to indicate the status of periodic * digital monitoring tests.Event: RL_RF_AE_MON_DIG_PERIODIC_REPORT_SB */ typedef struct rlDigPeriodicReportData { /** * @brief 1 - PASS, 0 - FAIL \n Bit Monitoring type \n [0] PERIODIC_CONFG_REGISTER_READ \n [1] RESERVED \n [2] DFE_STC \n [3] FRAME_TIMING_MONITORING \n [31:4] RESERVED \n */ rlUInt32_t digMonPeriodicStatus; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlDigPeriodicReportData_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, * containing the measured temperature near various RF analog and digital modules. * The xWR device sends this to host at the programmed periodicity or when failure occurs, * as programmed by the configuration API SB. Event:RL_RF_AE_MON_TEMPERATURE_REPORT_SB */ typedef struct rlMonTempReportData { /** * @brief Status flags indicating pass fail results corresponding to \n various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_ANA_TEMP_MIN \n [1] STATUS_ANA_TEMP_MAX \n [2] STATUS_DIG_TEMP_MIN \n [3] STATUS_DIG_TEMP_MAX \n [4] STATUS_TEMP_DIFF_THRESH \n [15:5]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief The measured onchip temperatures are reported here. \n Byte numbers corresponding to different temperature sensors \n reported in this field are here: \n Bytes SIGNAL \n [1:0] TEMP_RX0 \n [3:2] TEMP_RX1 \n [5:4] TEMP_RX2 \n [7:6] TEMP_RX3 \n [9:8] TEMP_TX0 \n [11:10] TEMP_TX1 \n [13:12] TEMP_TX2 \n [15:14] TEMP_PM \n [17:16] TEMP_DIG1 \n [19:18] TEMP_DIG2 (Applicable only in xWR1642 & xWR1843) \n 1 LSB = 1 degree C, signed number \n */ rlInt16_t tempValues[10U]; /** * @brief Reserved for future use */ rlUInt32_t reserved; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond \n (the stamp rolls over upon exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonTempReportData_t; /*! \brief * This API is a Monitoring report which RadarSS sends to the host, * containing the measured RX gain and phase values,Loopback Power and Noise Power. Noise Power can * be used by the Host to detect the presence of interference. RadarSS sends this to host at the \n * programmed periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_RX_GAIN_PHASE_REPORT */ typedef struct rlMonRxGainPhRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_RX_GAIN_ABS \n [1] STATUS_RX_GAIN_MISMATCH \n [2] STATUS_RX_GAIN_FLATNESS \n [3] STATUS_RX_PHASE_MISMATCH \n [15:4]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief The measured average loop-back power across RX channels at each enabled * RF1 frequency (i.e. Lowest, center and highest with 60MHz dither in the * profile's RF band) at LNA input is reported here. \n * b4:b0 RF1 \n * b7-b5: reserved \n * 1LSB = -2 dBm \n * Valid range = -62dBm to 0dBm. \n * Only the entries of enabled RF frequencies are valid. \n * The LB power might be bad/corrupted under interference conditions, and unreliable * at temperatures far away from room temperature. So, their usage is discouraged and * not supported for production usage. \n */ rlUInt8_t loopbackPowerRF1; /** * @brief The measured average loop-back power across RX channels at each enabled * RF2 frequency (i.e. Lowest, center and highest with 60MHz dither in the * profile's RF band) at LNA input is reported here. \n * b4:b0 RF2 \n * b7-b5: reserved \n * 1LSB = -2 dBm \n * Valid range = -62dBm to 0dBm. \n * Only the entries of enabled RF frequencies are valid. \n * The LB power might be bad/corrupted under interference conditions, and unreliable * at temperatures far away from room temperature. So, their usage is discouraged and * not supported for production usage. \n */ rlUInt8_t loopbackPowerRF2; /** * @brief The measured average loop-back power across RX channels at each enabled * RF3 frequency (i.e. Lowest, center and highest with 60MHz dither in the * profile's RF band) at LNA input is reported here. \n * b4:b0 RF3 \n * b7-b5: reserved \n * 1LSB = -2 dBm \n * Valid range = -62dBm to 0dBm. \n * Only the entries of enabled RF frequencies are valid. \n * The LB power might be bad/corrupted under interference conditions, and unreliable * at temperatures far away from room temperature. So, their usage is discouraged and * not supported for production usage. \n */ rlUInt8_t loopbackPowerRF3; /** * @brief The measured RX gain for each enabled channel, at each enabled RF frequency \n (i.e., lowest, center and highest in the profile's RF band) is reported \n here. Byte numbers corresponding to different RX and RF, in this field \n are here: \n RF1 RF2 RF3 \n RX0 1:0 9:8 17:16 \n RX1 3:2 11:10 19:18 \n RX2 5:4 13:12 21:20 \n RX3 7:6 15:14 23:22 \n 1 LSB = 0.1 dB \n Only the entries of enabled RF Frequencies and enabled RX channels are \n valid. \n The RX gain is measured using only ADC power and under assumption of a fixed LB power for all RF1, RF2 and RF3 frequencies to avoid interference impact. \n Therefore, RX gain shows around 10 dB deviation from programmed RX gain across full temperature range. \n For xWR1xxx devices: \n The actual Rx gain of the device in dB = RX GAIN VALUE(Rf freq, Rx) + (-38dBm) – LOOPBACK_POWER_TEMP_dBm(Temp[C]) \n Where LOOPBACK_POWER_TEMP_dBm (Temp[C]) = -0.07*Temp[C] – 34 \n Loopback power is -38 dBm around 50 C, and decreases with slope of -7 dBm/100C. These formulae can be used for monitoring reports not affected by interference. \n For xWR6x43 devices: \n RX gain value reported by the device assumes a constant loopback power. Please refer to monitoring application notes for more information on computing the actual RX gain from the device reported gain value. \n */ rlUInt16_t rxGainVal[12U]; /** * @brief The measured RX phase for each enabled channel, at each enabled RF frequency is \n reported here. Byte numbers corresponding to different RX and RF, \n in this field are here: \n RF1 RF2 RF3 \n RX0 1:0 9:8 17:16 \n RX1 3:2 11:10 19:18 \n RX2 5:4 13:12 21:20 \n RX3 7:6 15:14 23:22 \n LSB = 360 (degree)/2^16. \n Only the entries of enabled RF Frequencies and enabled RX channels are \n valid. \n @note : these phases include an unknown bias common to all RX channels. \n */ rlUInt16_t rxPhaseVal[12U]; /** * @brief The measured RX noise power for each enabled channel, at RF1 & RF2 frequencies \n (i.e., lowest and center in the profile's RF band) are reported here. Bit \n numbers corresponding to different RX and RF, in this field are here: \n | Bit | 4:0 | 9:5 | 14:10 | 19:15 | 24:20 | 29:25 | | ----------: | | | | | | | | **RX & RF** | RX0.RF1 | RX1.RF1 | RX2.RF1 | RX3.RF1 | RX0.RF2 | RX1.RF2 | bit 31:30 - Reserved \n 1 LSB = -2 dBm. \n Range: 0 to -62dBm \n Noise Power shows a decreasing trend with temperature with average noise power being -43 dBm at 50 C and decreasing with slope = -8 dBm/100C. \n Noise_Power_dBm (Temp[C]) =-0.08 * Temp [C] - 39 \n Noise Power can be used for detecting the monitoring reports impacted by interference. \n */ rlUInt32_t rxNoisePower1; /** * @brief The measured RX noise power for each enabled channel, at RF2 & RF3 frequencies \n (i.e., center and highest in the profile's RF band) are reported here. Bit \n numbers corresponding to different RX and RF, in this field are here: \n | Bit | 4:0 | 9:5 | 14:10 | 19:15 | 24:20 | 29:25 | | ------: | | | | | | | | **RX & RF** | RX2.RF2 | RX3.RF2 | RX0.RF3 | RX1.RF3 | RX2.RF3 | RX3.RF3 | bit 31:30 - Reserved \n 1 LSB = -2 dBm. \n Range: 0 to -62dBm \n Noise Power shows a decreasing trend with temperature with average noise power being -43 dBm at 50 C and decreasing with slope = -8 dBm/100C. \n Noise_Power_dBm (Temp[C]) =-0.08 * Temp [C] - 39 \n Noise Power can be used for detecting the monitoring reports impacted by interference. \n */ rlUInt32_t rxNoisePower2; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonRxGainPhRep_t; /*! \brief * This is the Monitoring report which RadarSS sends * to the host, containing the measured RX noise figure values * corresponding to the full IF band of a profile. RadarSS sends * this to host at the programmed periodicity or when failure occurs, * as programmed by the configuration API SB. Event: RL_RF_AE_MON_RX_NOISE_FIG_REPORT */ typedef struct rlMonRxNoiseFigRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_RX_NOISE_FIGURE \n [15:1]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief TThe measured RX input referred for each enabled channel, at each enabled RF \n frequency is reported here. Byte numbers corresponding to different RX \n and RF, in this field are here: \n RF1 RF2 RF3 \n RX0 1:0 9:8 17:16 \n RX1 3:2 11:10 19:18 \n RX2 5:4 13:12 21:20 \n RX3 7:6 15:14 23:22 \n 1 LSB = 0.1 dB \n Only the entries of enabled RF Frequencies and enabled RX channels are \n valid. \n */ rlUInt16_t rxNoiseFigVal[12U]; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief Reserved for future use */ rlUInt32_t reserved3; /** * @brief Reserved for future use */ rlUInt32_t reserved4; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon \n exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonRxNoiseFigRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the measured * RX IF filter attenuation values at the given IF frequencies. RadarSS sends this to host * at the programmed periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_RX_IF_STAGE_REPORT */ typedef struct rlMonRxIfStageRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_RX_HPF_ERROR \n [1] RESERVED \n [2] STATUS_RX_IFA_GAIN_ERROR \n [15:3]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief The deviations of RX IFA HPF cutoff frequency from the ideally expected values \n for all the enabled RX channels are reported here. \n HPF_CUTOFF_FREQ_ERROR = 100*(Measured Cutoff Frequency / \n Expected Cutoff Frequency) - 100, \n for RX IF filter in the HPF region. \n Byte numbers corresponding to measured cutoff frequency error \n on different RX channels, in this field are here: \n I channel Q channel \n RX0 0 4 \n RX1 1 5 \n RX2 2 6 \n RX3 3 7 \n 1 LSB = 1%, signed number \n Applicable only for the enabled channels. \n */ rlInt8_t hpfCutOffFreqEr[8U]; /** * @brief The deviations of RX IFA LPF cutoff frequency \n from the ideally expected values for all the enabled \n RX channels are reported here. \n LPF_CUTOFF_FREQ_ERROR = 100*(Measured Cutoff Frequency / \n Expected Cutoff Frequency) - 100, for RX IF filter in the LPF \n region. \n Byte numbers corresponding to measured cutoff frequency error \n on different RX channels, in this field are here: \n I channel Q channel \n RX0 0 4 \n RX1 1 5 \n RX2 2 6 \n RX3 3 7 \n 1 LSB = 1%, signed number \n Applicable only for the enabled channels. \n @note : This field is not applicable in this release for all devices. This is a RESERVED field and will be set to 0. */ rlInt8_t lpfCutOffFreqEr[8U]; /** * @brief The deviations of RX IFA Gain from the ideally expected \n values for all the enabled RX channels are reported here. \n Byte numbers corresponding to measured cutoff frequency error \n on different RX channels and HPF/LPF, in this field are here: \n I channel Q channel \n RX0 0 4 \n RX1 1 5 \n RX2 2 6 \n RX3 3 7 \n 1 LSB = 0.1dB, signed number \n Applicable only for the enabled channels. \n */ rlInt8_t rxIfaGainErVal[8U]; /** * @brief Expected IF gain * 1 LSB = 1 dB, 8 bit signed number */ rlInt8_t ifGainExp; /** * @brief Reserved for future use */ rlUInt8_t reserved2; /** * @brief Reserved for future use */ rlUInt16_t reserved3; /** * @brief Reserved for future use */ rlUInt32_t reserved4; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonRxIfStageRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the * measured TX power values during an explicit monitoring chirp. RadarSS sends this to * host at the programmed periodicity or when failure occurs, as programmed by the * configuration API SB. Same structure is application for Tx0/Tx1/Tx2 power report. * Event: RL_RF_AE_MON_TXn_POWER_REPORT */ typedef struct rlMonTxPowRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_ABS_ERR \n [1] STATUS_FLATNESS_ERR \n [15:2]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief The measured TX power for each enabled channel, at each enabled RF frequency is \n reported here. Byte numbers corresponding to different TX and RF, in this \n field are here: \n RF1 RF2 RF3 \n TX 1:0 3:2 5:4 \n (other bytes are reserved) \n 1 LSB = 0.1 dBm, signed number \n Only the entries of enabled RF Frequencies and enabled RX \n channels are valid. \n */ rlInt16_t txPowVal[3U]; /** * @brief Reserved for future use */ rlUInt16_t reserved2; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon \n exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonTxPowRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the measured * TX reflection coefficient's magnitude values, meant for detecting TX ball break. RadarSS sends * this to host at the programmed periodicity or when failure occurs, as programmed by the * configuration API SB. * Same strucuture is applicable for Tx0/Tx1/Tx2 ball break report. * Event: RL_RF_AE_MON_TXn_BALLBREAK_REPORT */ typedef struct rlMonTxBallBreakRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_TXn_BALLBREAK \n [15:1]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief The TX reflection coefficient's magnitude for this channel is reported here. \n 1 LSB = 0.1 dB, signed number \n */ rlInt16_t txReflCoefVal; /** * @brief Reserved for future use */ rlUInt16_t reserved0; /** * @brief Reserved for future use */ rlUInt32_t reserved1; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon \n exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonTxBallBreakRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the measured Tx * gain and phase mismatch values during an explicit monitoring chirp. RadarSS sends this to host * at the programmed periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_TX_GAIN_MISMATCH_REPORT */ typedef struct rlMonTxGainPhaMisRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_TX_GAIN_MISMATCH \n [1] STATUS_TX_PHASE_MISMATCH \n [15:2]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief The measured TX PA loopback tone power at the RX ADC input, \n for each enabled TX channel, at each enabled RF frequency is reported \n here. Byte numbers corresponding to different TX and RF, in this field are \n here: \n RF1 RF2 RF3 \n TX0 1:0 7:6 13:12 \n TX1 3:2 9:8 15:14 \n TX2 5:4 11:10 17:16 \n 1 LSB = 0.1dBm, signed number \n Only the entries of enabled RF Frequencies and enabled TX channels are valid. \n */ rlInt16_t txGainVal[9U]; /** * @brief The measured TX phase for each enabled channel, at each enabled RF \n frequency is reported here.Byte numbers corresponding to different TX and \n RF, in this field are here: \n RF1 RF2 RF3 \n TX0 1:0 7:6 13:12 \n TX1 3:2 9:8 15:14 \n TX2 5:4 11:10 17:16 \n 1 LSB = 360(degree)/2^16. \n Only the entries of enabled RF Frequencies and enabled TX channels are \n valid. \n Note: these phases include an unknown bias common to all TX channels. \n */ rlUInt16_t txPhaVal[9U]; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief Reserved for future use */ rlUInt32_t reserved3; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonTxGainPhaMisRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the measured * TX1 BPM error values. RadarSS sends this to host at the programmed periodicity or when failure * occurs, as programmed by the configuration API SB. Same structure is applicable for * Tx0/Tx1/Tx2 BPM report data. * Event: RL_RF_AE_MON_TXn_BPM_REPORT */ typedef struct rlMonTxBpmRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_TXn_BPM_PHASE \n [1] STATUS_TXn_BPM_AMPLITUDE \n [2] RESERVED \n [15:3]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief MSB of phase shifter monitor 2 for TX. \n phaseShifterMonVal2 = phaseShifterMonVal2Msb * pow(2,8) + \n phaseShifterMonVal2Lsb \n 1 LSB = (360 degree) / pow(2,16) \n */ rlUInt8_t phaseShifterMonVal2Msb; /** * @brief Monitored phase shift for phase shifter monitor 1 for TX 1 LSB = (360 degree) / pow(2,16) \n */ rlUInt16_t phaseShifterMonVal1; /** * @brief The TX output phase difference between the two BPM settings (phase for TX BPM \n setting 0 - phase for TX BPM setting 1) is reported here. \n 1 LSB = 360(degree)/2^16. \n */ rlUInt16_t txBpmPhaDiff; /** * @brief The deviation of the TX output amplitude difference between the two \n BPM settings (amplitude for TX BPM setting 0 - amplitude for TX \n BPM setting 1) from the ideal 0dB is reported here. \n 1 LSB = 0.1dB, signed number \n */ rlInt8_t txBpmAmpDiff; /** * @brief LSB of phase shifter monitor 2 for TX. \n phaseShifterMonVal2 = phaseShifterMonVal2Msb * pow(2,8) + \n phaseShifterMonVal2Lsb \n 1 LSB = (360 degree) / pow(2,16) \n */ rlUInt8_t phaseShifterMonVal2Lsb; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonTxBpmRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing information * related to measured frequency error during the chirp. RadarSS sends this to host at the * programmed periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_SYNTHESIZER_FREQ_REPORT */ typedef struct rlMonSynthFreqRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_SYNTH_FREQ_ERR \n [15:1]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief This field indicates the maximum instantaneous frequency error measured \n during the chirps for which frequency monitoring has been enabled in the \n previous monitoring period. \n Bits Parameter \n 31:0 Maximum frequency error value, signed number. 1 LSB = 1kHz. \n */ rlInt32_t maxFreqErVal; /** * @brief This field indicates the number of times during chirping in the previous \n monitoring period in which the measured frequency error violated the \n allowed threshold. Frequency error threshold violation is counted every \n 10ns. \n Bits Parameter \n 31:19 RESERVED \n 18:0 Failure count, unsigned number. \n */ rlUInt32_t freqFailCnt; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief Reserved for future use */ rlUInt32_t reserved3; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonSynthFreqRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the external * signal voltage values measured using the GPADC. RadarSS sends this to host at the programmed * periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_EXT_ANALOG_SIG_REPORT */ typedef struct rlMonExtAnaSigRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_ANALOGTEST1 \n 1 STATUS_ANALOGTEST2 \n 2 STATUS_ANALOGTEST3 \n 3 STATUS_ANALOGTEST4 \n 4 STATUS_ANAMUX \n 5 STATUS_VSENSE \n 15:3 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief MEASURED_VALUE \n Bytes SIGNAL \n 1:0 ANALOGTEST1 \n 3:2 ANALOGTEST2 \n 5:4 ANALOGTEST3 \n 7:6 ANALOGTEST4 \n 9:8 ANAMUX \n 11:10 VSENSE \n 1 LSB = 1.8V/1024 \n */ rlInt16_t extAnaSigVal[6U]; /** * @brief Reserved for future use */ rlUInt32_t reserved; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonExtAnaSigRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing information * about Internal TX internal analog signals. RadarSS sends this to host at the programmed * periodicity or when failure occurs, as programmed by the configuration API SB. Same structure * is applicable for Tx0/Tx1/Tx2 monitoring report. Event: RL_RF_AE_MON_TXn_INT_ANA_SIG_REPORT */ typedef struct rlMonTxIntAnaSigRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n [0] STATUS_SUPPLY_TXn \n [1] STATUS_DCBIAS_TXn \n [2] STATUS_PS_DAC_TXn \n [15:3]RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Phase shifter DAC I arm delta min value across different DAC settings 1 LSB = 1.8V/1024 @note : This field is applicable only for xWR6843 and xWR1843 devices only. */ rlUInt8_t phShiftDacIdeltaMin; /** * @brief Phase shifter DAC Q arm delta min value across different DAC settings 1 LSB = 1.8V/1024 @note : This field is applicable only for xWR6843 and xWR1843 devices only. */ rlUInt8_t phShiftDacQdeltaMin; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon \n exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonTxIntAnaSigRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing information * about Internal RX internal analog signals. RadarSS sends this to host at the programmed * periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_RX_INT_ANALOG_SIG_REPORT */ typedef struct rlMonRxIntAnaSigRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_SUPPLY_RX0 \n 1 STATUS_SUPPLY_RX1 \n 2 STATUS_SUPPLY_RX2 \n 3 STATUS_SUPPLY_RX3 \n 4 STATUS_DCBIAS_RX0 \n 5 STATUS_DCBIAS_RX1 \n 6 STATUS_DCBIAS_RX2 \n 7 STATUS_DCBIAS_RX3 \n 15:8 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonRxIntAnaSigRep_t; /*! \brief * This API is a Monitoring Report API which the AWR device sends to the host, containing * information about Internal PM, CLK and LO subsystems' internal analog signals and in cascade * devices the 20GHz SYNC IN/OUT power. The AWR device sends this to host at the programmed * periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_PMCLKLO_INT_ANA_SIG_REPORT */ typedef struct rlMonPmclkloIntAnaSigRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_SUPPLY_PMCLKLO \n 1 STATUS_DCBIAS_PMCLKLO \n 2 STATUS_LVDS_PMCLKLO (Use this status bit only if LVDS is used, \n else ignorethis) \n 3 RESERVED \n 15:4 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Monitored 20GHz signal power, signed number \n * 1 LSB = 0.5 dBm \n * The 20GHz SYNC monitor is done at 77GHz RF frequency. \n * @note : This field is not supported in xWR6x43 devices. */ rlInt8_t sync20GPower; /** * @brief Reserved for future use */ rlUInt16_t reserved; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon \n exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonPmclkloIntAnaSigRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing information * about the measured value of the GPADC input DC signals whose measurements were enabled. * RadarSS sends this to host at the programmed periodicity or when failure occurs, as programmed * by the configuration API. * SB. Event: RL_RF_AE_MON_GPADC_INT_ANA_SIG_REPORT */ typedef struct rlMonGpadcIntAnaSigRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_GPADC_REF1 \n 1 STATUS_GPADC_REF2 \n 15:2 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief The measured GPADC outputs corresponding to internal DC signal (GPADC_REF1, \n expected level 0.45V) is reported here. \n 1 LSB = 1.8V/1024 \n */ rlInt16_t gpadcRef1Val; /** * @brief The measured GPADC outputs corresponding to internal DC signal (GPADC_REF2, \n expected level 1.2V) is reported here. \n 1 LSB = 1.8V/1024 \n */ rlUInt16_t gpadcRef2Val; /** * @brief Reserved for future use */ rlUInt32_t reserved; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonGpadcIntAnaSigRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing the measured PLL * control voltage values during explicit monitoring chirps. RadarSS sends this to host at the * programmed periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_PLL_CONTROL_VOLT_REPORT */ typedef struct rlMonPllConVoltRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_APLL_VCTRL \n 1 STATUS_SYNTH_VCO1_VCTRL_MAX_ FREQ \n 2 STATUS_SYNTH_VCO1_VCTRL_MIN_ FREQ \n 3 RESERVED \n 4 STATUS_SYNTH_VCO2_VCTRL_MAX_ FREQ \n 5 STATUS_SYNTH_VCO2_VCTRL_MIN_ FREQ \n 6 RESERVED \n 15:7 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief The measured values of PLL control voltage levels and Synthesizer VCO slopes are \n reported here. Byte numbers corresponding to different control voltage \n values reported in this field are here: \n Bytes SIGNAL 1 LSB \n 1:0 APLL_VCTRL 1mV \n 3:2 SYNTH_VCO1_VCTRL_MAX_ FREQ 1mV \n 5:4 SYNTH_VCO1_VCTRL_MIN_ FREQ 1mV \n 7:6 SYNTH_VCO1_SLOPE 1MHz/V \n 9:8 SYNTH_VCO2_VCTRL_MAX_ FREQ 1mV \n 11:10 SYNTH_VCO2_VCTRL_MIN_ FREQ 1mV \n 13:12 SYNTH_VCO2_SLOPE 1MHz/V \n 15:14 RESERVED RESERVED \n Only the fields corresponding to the enabled monitors are valid. \n The failure thresholds are based on the following: \n Valid VCTRL values are [140 to 1400] mV. \n Valid VCO1_SLOPE values are [1760 to 2640] MHz/V. \n Valid VCO2_SLOPE values are [3520 to 5280] MHz/V. \n @note : The VCOx SLOPE should be ignored when synth fault is injected. \n */ rlInt16_t pllContVoltVal[8U]; /** * @brief Reserved for future use */ rlUInt32_t reserved; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) */ rlUInt32_t timeStamp; }rlMonPllConVoltRep_t; /*! \brief * This is the Monitoring report which RadarSS sends to the host, containing information about * the relative frequency measurements. RadarSS sends this to host at the programmed periodicity or * when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_DCC_CLK_FREQ_REPORT */ typedef struct rlMonDccClkFreqRep { /** * @brief Status flags indicating pass fail results corresponding to various threshold \n checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_CLK_PAIR0 \n 1 STATUS_CLK_PAIR1 \n 2 STATUS_CLK_PAIR2 \n 3 STATUS_CLK_PAIR3 \n 4 STATUS_CLK_PAIR4 \n 15:5 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief The measured clock frequencies from the enabled clock pair measurements are \n reported here.Byte numbers corresponding to different frequency measurement \n values reported in this field are here: \n Bytes CLOCK PAIR MEASURED CLOCK FREQUENCY \n 1:0 0 BSS_600M \n 3:2 1 BSS_200M \n 5:4 2 BSS_100M \n 7:6 3 GPADC_10M \n 9:8 4 RCOSC_10M \n 15:10 RESERVED RESERVED \n 1 LSB = 0.1 MHz, unsigned number \n */ rlUInt16_t freqMeasVal[8U]; /** * @brief Reserved for future use */ rlUInt32_t reserved; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit \n width) \n */ rlUInt32_t timeStamp; }rlMonDccClkFreqRep_t; /*! \brief * This is the Monitoring report which the xWR device sends to the host, containing the * measured RX mixer input voltage swing values. The xWR device sends this to host at the * programmed periodicity or when failure occurs, as programmed by the configuration API SB. * Event: RL_RF_AE_MON_RX_MIXER_IN_PWR_REPORT */ typedef struct rlMonRxMixrInPwrRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 STATUS_MIXER_IN_POWER_RX0 \n 1 STATUS_MIXER_IN_POWER_RX1 \n 2 STATUS_MIXER_IN_POWER_RX2 \n 3 STATUS_MIXER_IN_POWER_RX3 \n 15:4 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief Profile Index for which this monitoring report applies. */ rlUInt8_t profIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief The measured RX mixer input voltage swing values are \n reported here. The byte location of the value for each \n receivers is tabulated here- \n Byte location \n Rx0 0 \n Rx1 1 \n Rx2 2 \n Rx3 3 \n 1 LSB = 1800 mV/256, unsigned number \n Only the entries of enabled RX channels are valid. \n */ rlUInt32_t rxMixInVolt; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonRxMixrInPwrRep_t; /*! \brief * This is a Non live Monitoring report which device sends to the host, containing information * related to measured frequency error during the monitoring chirp for two profiles * configurations. The device sends this to host at the programmed periodicity or when failure * occurs, as programmed by the configuration API SB. * This is a new feature addition in xWR6843 device only. * Event: RL_RF_AE_MON_SYNTH_FREQ_NONLIVE_REPORT */ typedef struct rlMonSynthFreqNonLiveRep { /** * @brief Status flags indicating pass fail results corresponding \n to various threshold checks under this monitor. \n Bit STATUS_FLAG for monitor \n 0 VCO1_SYNTH_FREQ_ERR_STATUS \n 1 VCO2_SYNTH_FREQ_ERR_STATUS \n 15:2 RESERVED \n 0 - FAIL or check wasn't done, 1 - PASS \n */ rlUInt16_t statusFlags; /** * @brief Indicates any error reported during monitoring Value of 0 indicates no error */ rlUInt16_t errorCode; /** * @brief VCO1 Profile index for which this monitoring report applies. */ rlUInt8_t profIndex0; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief This field indicates the maximum instantaneous frequency error measured during the monitoring chirp for which frequency monitoring has been enabled in the previous monitoring period for VCO1 profile. \n Bits Parameter \n 31:0 Maximum frequency error value, signed number. 1 LSB = 1kHz. \n */ rlInt32_t maxFreqErVal0; /** * @brief This field indicates the number of times during chirping in the previous monitoring period in which the measured frequency error violated the allowed threshold for VCO1 profile. Frequency error threshold violation is counted every 10 ns. \n Bits Parameter \n 31:19 RESERVED \n 18:0 Failure count, unsigned number. \n */ rlUInt32_t freqFailCnt0; /** * @brief This field indicates the time at which error occurred for VCO1 profile w.r.t. knee of the ramp. \n 1 LSB = 10ns \n */ rlUInt32_t maxFreqFailTime0; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief VCO2 Profile index for which this monitoring report applies. */ rlUInt8_t profIndex1; /** * @brief Reserved for future use */ rlUInt8_t reserved3; /** * @brief Reserved for future use */ rlUInt16_t reserved4; /** * @brief This field indicates the maximum instantaneous frequency error measured during the monitoring chirp for which frequency monitoring has been enabled in the previous monitoring period for VCO2 profile. \n Bits Parameter \n 31:0 Maximum frequency error value, signed number. 1 LSB = 1kHz. \n */ rlInt32_t maxFreqErVal1; /** * @brief This field indicates the number of times during chirping in the previous monitoring period in which the measured frequency error violated the allowed threshold for VCO2 profile. Frequency error threshold violation is counted every 10 ns. \n Bits Parameter \n 31:19 RESERVED \n 18:0 Failure count, unsigned number. \n */ rlUInt32_t freqFailCnt1; /** * @brief This field indicates the time at which error occurred for VCO2 profile w.r.t. knee of the ramp. \n 1 LSB = 10ns \n */ rlUInt32_t maxFreqFailTime1; /** * @brief Reserved for future use */ rlUInt32_t reserved5; /** * @brief This field indicates when the last monitoring in the enabled set was performed. \n 1 LSB = 1 millisecond (the stamp rolls over upon exceeding allotted bit width) \n */ rlUInt32_t timeStamp; }rlMonSynthFreqNonLiveRep_t; /*! \brief * This is an error status report internally generated from mmWaveLink when it finds any * issue with the recieved message or communication. Currently errorVal can be * RL_RET_CODE_CRC_FAILED, RL_RET_CODE_CHKSUM_FAILED or RL_RET_CODE_HOSTIRQ_TIMEOUT. * Event: RL_MMWL_AE_MISMATCH_REPORT, RL_MMWL_AE_INTERNALERR_REPORT * ErroVal: RL_RET_CODE_CRC_FAILED, RL_RET_CODE_CHKSUM_FAILED or RL_RET_CODE_HOSTIRQ_TIMEOUT * for RL_MMWL_AE_MISMATCH_REPORT Event and RL_RET_CODE_RADAR_OSIF_ERROR for * RL_MMWL_AE_INTERNALERR_REPORT Event */ typedef struct rlMmwlErrorStatus { rlInt32_t errorVal; }rlMmwlErrorStatus_t; /**************************************************************************************** * FileName : rl_device.h * * Description : This file defines the functions required to Control mmwave radar Device. * **************************************************************************************** * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ /**************************************************************************************** * FILE INCLUSION PROTECTION **************************************************************************************** */ /**************************************************************************************** * INCLUDE FILES **************************************************************************************** */ /**************************************************************************************** * FileName : rl_protocol.h * * Description : This file defines the functions required for Communication Protocol * **************************************************************************************** * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /**************************************************************************************** * FILE INCLUSION PROTECTION **************************************************************************************** */ /****************************************************************************** * INCLUDE FILES ****************************************************************************** */ /* RHCP Length Constants*/ /**< Max Payload Len (256 - 16(HDR) - 8(CRC)) */ /*! \brief * mmWaveLink API Error Type */ typedef rlUInt16_t rlSysNRespType_t; /*! \brief * mmWaveLink API Error Sub block structure */ typedef struct rlErrorResp { /** *@ brief 16 bits error type */ rlSysNRespType_t errorType; /** *@ brief 16 bits SBC ID */ rlUInt16_t sbcID; }rlErrorResp_t; /*! \brief * RHCP SYNC Pattern Structure */ typedef struct rlSyncPattern { rlUInt16_t sync1; rlUInt16_t sync2; }rlSyncPattern_t; /*! \brief * Command op-code ID contains 4 fields (16 bits) * Bit 10-15: Reserved * Bit 8-9: Operation - Set/Get. * Bit 4-7: Operation Type * Bit 0-3: Direction */ typedef struct rlOpcode { /** * @brief Direction */ rlUInt16_t b4Direction : 4; /** * @brief Msg Type */ rlUInt16_t b2MsgType : 2; /** * @brief Message ID */ rlUInt16_t b10MsgId : 10; }rlOpcode_t; /*! \brief * Command op-code ID contains 4 fields (16 bits) * Bit 10-15: Reserved * Bit 8-9: Operation - Set/Get. * Bit 4-7: Operation Type * Bit 0-3: Direction */ typedef struct rlHdrFlags { /** * @brief 00- No Retry, 11 - Retry */ rlUInt16_t b2RetryFlag : 2; /** * @brief 00- ACK requested, 11 - No ACK Requested */ rlUInt16_t b2AckFlag : 2; /** * @brief 0000 - Invalid, 0001 - 1111 - Valid Range */ rlUInt16_t b4Version : 4; /** * @brief 00 - CRC present, 11 - CRC not Present */ rlUInt16_t b2Crc : 2; /** * @brief Length of CRC appended to the message 00 16-bit CRC 01 32-bit CRC 10 64-bit CRC 11 Reserved */ rlUInt16_t b2CrcLen : 2; /** * @brief Sequence Number */ rlUInt16_t b4SeqNum : 4; }rlHdrFlags_t; /*! \brief * RHCP protocol header structure */ typedef struct rlProtHeader { /** * @brief rlUInt16_t, rlApiActionType,rlApiGetSetType */ rlOpcode_t opcode; rlUInt16_t len; rlHdrFlags_t flags; rlUInt16_t remChunks; rlUInt16_t nsbc; rlUInt16_t chksum; }rlProtHeader_t; /*! \brief * RHCP message structure */ typedef struct rlRhcpMsg { rlSyncPattern_t syncPattern; rlProtHeader_t hdr; rlUInt8_t payload[(((256U) - ((4U) + (12U) + (8U)))) + (8U)]; }rlRhcpMsg_t; /* * END OF RL_PROTOCOL_H FILE */ /**************************************************************************************** * MACRO DEFINITIONS **************************************************************************************** */ /****************************************************************************** * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS ****************************************************************************** */ /*! \brief * IQ Swap Selection */ /*! \brief * Channel Interleave Selection */ /*! \brief * File Dowload data structure */ typedef struct rlFileData { /** * @brief File data length */ rlUInt32_t chunkLen; /** * @brief File data buffer */ rlUInt16_t fData[(((256U) - ((4U) + (12U) + (8U))))/2U]; }rlFileData_t; /*! \brief * mmwave radar device MCU Clock output */ typedef struct rlMcuClkCfg { /** * @brief This field controls the enable - disable of the MCU clock. \n Value Description \n 0x0 Disable MCU clock \n 0x1 Enable MCU clock \n */ rlUInt8_t mcuClkCtrl; /** * @brief This field specifies the source of the MCU clock. Applicable only in case of MCU \n clock enable.Else ignored. \n Value Description \n 0x0 XTAL(as connected to the device) \n 0x1 RESERVED \n 0x2 600MHz PLL divided clock \n */ rlUInt8_t mcuClkSrc; /** * @brief This field specifies the division factor to be applied to source clock. \n Applicable only in case of MCU \n clock enable. Else ignored. \n Value Description \n 0x0 Divide by 1 \n 0x1 Divide by 2 \n ... ... \n 0xFF Divide by 256 \n */ rlUInt8_t srcClkDiv; /** * @brief Reserved for future use */ rlUInt8_t reserved; }rlMcuClkCfg_t; /*! \brief * mmwave radar device PMIC Clock output */ typedef struct rlPmicClkCfg { /** * @brief This field controls the enable - disable of the PMIC clock. \n Value Description \n 0x0 Disable PMIC clock \n 0x1 Enable PMIC clock \n */ rlUInt8_t pmicClkCtrl; /** * @brief This field specifies the source of the PMIC clock. Applicable only in case of \n PMIC clock enable. Else ignored. \n Value Description \n 0x0 XTAL (as connected to the device) \n 0x2 600MHz PLL divided clock \n */ rlUInt8_t pmicClkSrc; /** * @brief This field specifies the division factor to be applie to source clock. \n Applicable only in case of PMIC clock \n enable. Else ignored. \n Value Description \n 0x0 Divide by 1 (Not supported) \n 0x1 Divide by 2 \n ... ... \n 0xFF Divide by 256 \n */ rlUInt8_t srcClkDiv; /** * @brief This field specifies the mode of operation for the PMIC clock generation. \n Applicable only in case of PMIC clock \n enable. Else ignored. \n Value Description \n 0x0 Continuous mode (free running mode where the frequency \n change/jump is triggered based on configured number of \n internal clock ticks) \n 0x1 Chirp-to-Chirp staircase mode (frequency change/jump is \n triggered at every chirp boundary) \n */ rlUInt8_t modeSel; /** * @brief Applicable only in case of PMIC clock enable. Else ignored. \n Bit[25:0] - Frequency slope value to be applied in [8.18] format. \n 1 LSB = 1/218 \n In continuous mode this value is accumulated every PMIC clock tick \n with the seed as MIN_NDIV_VAL till MAX_NDIV_VAL is reached \n In the stair case mode this value is accumulated every chirp with the \n seed as MIN_NDIV_VAL till MAX_NDIV_VAL is reached \n */ rlUInt32_t freqSlope; /** * @brief Applicable only in case of PMIC clock enable. Else ignored. Min allowed divider \n value (depends upon the highest desired clock frequency) \n */ rlUInt8_t minNdivVal; /** * @brief Applicable only in case of PMIC clock enable. Else ignored. Max allowed divider \n value (depends upon the lowest desired clock frequency) \n */ rlUInt8_t maxNdivVal; /** * @brief Applicable only in case of PMIC clock enable. Else ignored. This field controls \n the enable-disable of the clock dithering. Adds a pseudo random real number \n (0 or 1) to the accumulated divide value. Hence it brings a random dithering \n of 1 LSB. \n Value Description \n 0x0 Clock dithering disabled \n 0x1 Clock dithering enabled \n */ rlUInt8_t clkDitherEn; /** * @brief Reserved for future use */ rlUInt8_t reserved; }rlPmicClkCfg_t; /*! \brief * mmwave radar device latent fault test */ typedef struct rllatentFault { /** * @brief Bits Definition \n 0 RESERVED \n 1 DMA self-test \n 2 RESERVED \n 3 RTI self-test \n 4 RESERVED \n 5 EDMA self-test \n 6 CRC self-test \n 7 VIM self-test \n 8 RESERVED \n 9 Mailbox self-test \n 10 RESERVED \n 11 RESERVED \n 12 Generating NERROR \n 13 MibSPI single bit error test \n 14 MibSPI double bit error test \n 15 DMA Parity error \n 16 TCMA RAM single bit errors (Not supported, refer latest release note) \n 17 TCMB RAM single bit errors (Not supported, refer latest release note) \n 18 TCMA RAM double bit errors (Not supported, refer latest release note) \n 19 TCMB RAM double bit errors (Not supported, refer latest release note) \n 20 TCMA RAM parity errors (Not supported, refer latest release note) \n 21 TCMB RAM parity errors (Not supported, refer latest release note) \n 22 RESERVED \n 23 RESERVED \n 24 DMA MPU Region tests \n 25 MSS Mailbox Single bit errors \n 26 MSS Mailbox double bit errors \n 27 radarSS Mailbox Single bit errors \n 28 radarSS Mailbox double bit errors \n 29 EDMA MPU test \n 30 EDMA parity test \n 31 CSI2 parity test \n */ rlUInt32_t testEn1; /** * @brief Bits Definition \n 0 RESERVED \n 1 RESERVED \n 2 RESERVED \n 3 VIM RAM parity test \n 4 SCI boot time test \n 31:5 RESERVED \n */ rlUInt32_t testEn2; /** * @brief Value Definition \n 0 Report is sent after test completion \n 1 Report is send only upon a failure \n */ rlUInt8_t repMode; /** * @brief Value Definition \n 0 Production mode. Latent faults are tested and any failures are reported \n 1 Characterization mode. Faults are injected and failures are reported which \n allows testing of the failure reporting \n */ rlUInt8_t testMode; /** * @brief Reserved for future use */ rlUInt16_t reserved; }rllatentFault_t; /*! \brief * mmwave radar periodicity test config */ typedef struct rlperiodicTest { /** * @brief 1 LSB = 1 ms Periodicity at which tests need to be run \n Minimum value is 40 ms \n Maximum value is 150ms \n @note : MSS Windowed WDT period is set to this periodicity and WDT can not \n support period more than 150ms. \n */ rlUInt32_t periodicity; /** * @brief Bit value definition: 1 - Enable, 0 - Disable \n Bit Monitoring type \n 0 PERIODIC_CONFG_REGISTER_READ_EN \n 1 ESM_MONITORING_EN \n 31:2 RESERVED \n */ rlUInt32_t testEn; /** * @brief Value Definition \n 0 Report is sent every monitoring period \n 1 Report is sent only on a failure \n */ rlUInt8_t repMode; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; }rlperiodicTest_t; /*! \brief * mmwave radar test pattern config */ typedef struct rltestPattern { /** * @brief This field controls the enable-disable of the generation of the test pattern. \n Value Description \n 0x0 Disable test pattern generation \n 0x1 Enable test pattern generation \n */ rlUInt8_t testPatGenCtrl; /** * @brief Number of system clocks (200 MHz) between successive samples for the test pattern \n gen. Applicable only in case of Test pattern enable. Else ignored. \n */ rlUInt8_t testPatGenTime; /** * @brief Number of ADC samples to capture for each RX Valid range: 64 to MAX_NUM_SAMPLES, Where MAX_NUM_SAMPLES is such that all the enabled RX channels’ data fits into \n 16 kB memory, with each sample consuming 2 bytes for real ADC output case and 4 \n bytes for complex 1x and complex 2x ADC output cases. For example: 4 RX, Complex ADC output -> MAX_NUM_SAMPLES = 1024 4 RX, Real ADC output -> MAX_NUM_SAMPLES = 2048 2 RX, Complex ADC output -> MAX_NUM_SAMPLES = 2048 2 RX, Real ADC output -> MAX_NUM_SAMPLES = 4096 */ rlUInt16_t testPatrnPktSize; /** * @brief Number of test pattern packets to send, for infinite packets set it to 0 */ rlUInt32_t numTestPtrnPkts; /** * @brief This field specifies the values for Rx0, I channel. Applicable only in case of \n test pattern enable. Else ignored. Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data \n [31:16] Value to be added for each successive sample for the test pattern \n data \n */ rlUInt32_t testPatRx0Icfg; /** * @brief This field specifies the values for Rx0, Q channel. Applicable only in case of \n test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data \n */ rlUInt32_t testPatRx0Qcfg; /** * @brief This field specifies the values for Rx1, I channel. Applicable only in case of \n test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data */ rlUInt32_t testPatRx1Icfg; /** * @brief This field specifies the values for Rx1, Q channel. \n Applicable only in case of test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data */ rlUInt32_t testPatRx1Qcfg; /** * @brief This field specifies the values for Rx2, I channel. \n Applicable only in case of test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data */ rlUInt32_t testPatRx2Icfg; /** * @brief This field specifies the values for Rx2, Q channel. \n Applicable only in case of test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data */ rlUInt32_t testPatRx2Qcfg; /** * @brief This field specifies the values for Rx3, I channel. \n Applicable only in case of test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data */ rlUInt32_t testPatRx3Icfg; /** * @brief This field specifies the values for Rx3, Q channel. \n Applicable only in case of test pattern enable. Else ignored. \n Bits Description \n [15:0] Start offset value to be used for the first sample for the test \n pattern data [31:16] Value to be added for each successive sample for the test pattern \n data */ rlUInt32_t testPatRx3Qcfg; /** * @brief Reserved for future use */ rlUInt32_t reserved; }rltestPattern_t; /*! \brief * mmwave radar data format config */ typedef struct rlDevDataFmtCfg { /** * @brief RX Channel Bitmap \n b0 RX0 Channel Enable \n 0 Disable RX Channel 0 \n 1 Enable RX Channel 0 \n b1 RX1 Channel Enable \n 0 Disable RX Channel 1 \n 1 Enable RX Channel 1 \n b2 RX2 Channel Enable \n 0 Disable RX Channel 2 \n 1 Enable RX Channel 2 \n b3 RX3 Channel Enable \n 0 Disable RX Channel 3 \n 1 Enable RX Channel 3 \n */ rlUInt16_t rxChannelEn; /** * @brief ADC out bits - 0(12 Bits), 1(14 Bits), 2(16 Bits) */ rlUInt16_t adcBits; /** * @brief ADC out format - 0(Real), 1(Complex), 2(Complex with Image band), 3(Pseudo Real) */ rlUInt16_t adcFmt; /** * @brief I/Q Swap selection for complex outputs \n 0 Sample interleave mode - I first \n 1 Sample interleave mode - Q first \n others reserved \n */ rlUInt8_t iqSwapSel; /** * @brief Channel interleaving of the samples stored in \n the ADC buffer to be transferred out on the data path \n 0 - Interleaved \n 1 - Non Interleaved \n others reserved \n */ rlUInt8_t chInterleave; /** * @brief Reserved for future use */ rlUInt32_t reserved; }rlDevDataFmtCfg_t; /*! \brief * mmwave radar data path config. */ typedef struct rlDevDataPathCfg { /** * @brief Data Path Interface, \n 0x0 CSI2 interface selected \n 0x1 LVDS interface selected \n */ rlUInt8_t intfSel; /** * @brief Data out Format, \n b5:0 Packet 0 content selection \n 000001 - ADC_DATA_ONLY \n 000110 - CP_ADC_DATA \n 001001 - ADC_CP_DATA \n 110110 - CP_ADC_CQ_DATA \n b7:6 Packet 0 virtual channel number (valid only for CSI2) \n 00 Virtual channel number 0 (Default) \n 01 Virtual channel number 1 \n 10 Virtual channel number 2 \n 11 Virtual channel number 3 \n */ rlUInt8_t transferFmtPkt0; /** * @brief Data out Format, \n b5:0 Packet 1 content selection \n 000000 - Suppress Packet 1 \n 001110 - CP_CQ_DATA \n 001011 - CQ_CP_DATA \n b7:6 Packet 1 virtual channel number (valid only for CSI2) \n 00 Virtual channel number 0 (Default) \n 01 Virtual channel number 1 \n 10 Virtual channel number 2 \n 11 Virtual channel number 3 \n */ rlUInt8_t transferFmtPkt1; /** * @brief This field specifies the data size of CQ samples on the lanes. \n b1:0 Data size \n 00 12 bits \n 01 14 bits \n 10 16 bits \n b7:2 Reserved */ rlUInt8_t cqConfig; /** * @brief Number of samples (in 16 bit halfwords) of CQ0 data to be transferred. Valid range [32 halfwords to 128 halfwords] \n Value 0 = Disabled \n @note : Ensure that the number of halfwords specified are a multiple of the number of lanes selected. */ rlUInt8_t cq0TransSize; /** * @brief Number of samples (in 16 bit halfwords) of CQ1 data to be transferred. Valid range [32 halfwords to 128 halfwords] \n Value 0 = Disabled \n @note : Ensure that the number of halfwords specified are a multiple of the number of lanes selected. */ rlUInt8_t cq1TransSize; /** * @brief Number of samples (in 16 bit halfwords) of CQ2 data to be transferred. Valid range [32 halfwords to 128 halfwords] \n Value 0 = Disabled \n @note : Ensure that the number of halfwords specified are a multiple of the number of lanes selected. */ rlUInt8_t cq2TransSize; /** * @brief Reserved for future use */ rlUInt8_t reserved; }rlDevDataPathCfg_t; /*! \brief * mmwave radar data path lane enable */ typedef struct rlDevLaneEnable { /** * @brief Lane Enable Bitmap \n b0 Lane 0 Enable \n 0 Disable lane 0 \n 1 Enable lane 0 \n b1 Lane 1 Enable \n 0 Disable lane 1 \n 1 Enable lane 1 \n b2 Lane 2 Enable \n 0 Disable lane 2 \n 1 Enable lane 2 \n b3 Lane 3 Enable \n 0 Disable lane 3 \n 1 Enable lane 3 \n b15:4 Reserved \n */ rlUInt16_t laneEn; /** * @brief Reserved for future use */ rlUInt16_t reserved; }rlDevLaneEnable_t; /*! \brief * DataPath clock configuration */ typedef struct rlDevDataPathClkCfg { /** * @brief Clock COnfiguration \n 0 -SDR Clock \n 1 - DDR Clock (Only valid value for CSI2) \n */ rlUInt8_t laneClkCfg; /** * @brief Data rate selection \n 0001b - 600 Mbps (DDR only) \n 0010b - 450 Mbps (SDR, DDR) \n 0011b - 400 Mbps (DDR only) \n 0100b - 300 Mbps (SDR, DDR) \n 0101b - 225 Mbps (DDR only) \n 0110b - 150 Mbps (DDR only) \n Others - Reserved \n */ rlUInt8_t dataRate; /** * @brief Reserved for future use */ rlUInt16_t reserved; }rlDevDataPathClkCfg_t; /*! \brief * LVDS Lane configuration */ typedef struct rlDevLvdsLaneCfg { /** * @brief Lane format \n 0x0000 Format map 0 (Rx0,Rx1,...) \n 0x0001 Format map 1 (Rx3,Rx2,...) \n */ rlUInt16_t laneFmtMap; /** * @brief Lane Parameter configurations \n b0 - 0(LSB first), 1(MSB first) \n b1 - 0(Packet End Pulse Disable), 1(enable) \n b2 - 0(CRC disabled), 1(CRC enabled) \n b7:3 - Reserved \n b8 - Configures LSB/MSB first for CRC \n 0(CRC value swapped wrt to MSB_FIRST setting) \n 1(CRC value follows MSB_FIRST setting) \n b9 - Frame clock state during idle \n 0(Frame clock is held low) \n 1(Frame clock is held high) \n b10 - Frame clock period for CRC(when CRC enabled - b2) \n 0(32-bit CRC is trasmitted as single sample with frame clock set to \n 16high, 16low configuration) \n 1(32-bit CRC is trasmitted as single sample with frame clock set to \n 8high, 8low configuration) \n b11 - Bit clock state during idle \n 0(Bit clock toggles during idle when there are no transmission) \n 1(Bit clock doesn't toggle during idle when there are no transmission, \n the value of bit clock is held low) \n b12 - CRC inversion control(when CRC enabled - b2) \n 0(The calcualted value of 32-bit ethernet polynomial CRC is inverted and \n sent out) \n 1(The calcualted value of 32-bit ethernet polynomial CRC is sent without \n inversion) \n b15:13 - Reserved \n */ rlUInt16_t laneParamCfg; }rlDevLvdsLaneCfg_t; /*! \brief * Continous streaming mode configuration */ typedef struct rlDevContStreamingModeCfg { /** * @brief Enable - 1, Disable - 0 */ rlUInt16_t contStreamModeEn; /** * @brief Reserved for future use \n */ rlUInt16_t reserved; }rlDevContStreamingModeCfg_t; /*! \brief * CSI2 configuration */ typedef struct rlDevCsi2Cfg { /** * @brief b2:0 - DATA_LANE0_POS \n Valid values (Should be a unique position if lane 0 is enabled, ignored if \n lane 0 is not enabled): \n 000b - Unused, 001b - Position 1 (default), \n 010b - Position 2, 011b - Position 3, \n 100b - Position 4, 101b - Position 5 \n b3 DATA_LANE0_POL \n 0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order \n b6:4 DATA_LANE1_POS \n Valid values (Should be a unique position if lane 1 is \n enabled, ignored if lane 1 is not enabled): \n 000b - Unused, 001b - Position 1, \n 010b - Position 2 (default), 011b - Position 3, \n 100b - Position 4, 101b - Position 5 \n b7 DATA_LANE1_POL \n 0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order \n b10:8 DATA_LANE2_POS \n Valid values (Should be a unique position if lane 2 is \n enabled, ignored if lane 2 is not enabled): \n 000b - Unused, 001b - Position 1, \n 010b - Position 2, 011b - Position 3, \n 100b - Position 4 (default), 101b - Position 5 \n b11 DATA_LANE2_POL \n 0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order \n b14:12 DATA_LANE3_POS \n Valid values (Should be a unique position if lane 3 is \n enabled, ignored if lane 3 is not enabled): \n 000b - Unused, 001b - Position 1, \n 010b - Position 2, 011b - Position 3, \n 100b - Position 4, 101b - Position 5 (default) \n b15 DATA_LANE3_POL \n 0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order \n b18:16 CLOCK_POS \n Valid values (Should be a unique position): \n 001b - Position 1, \n 010b - Position 2, 011b - Position 3 (default), \n 100b - Position 4 \n b19 CLOCK_POL \n 0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order \n b31:20 RESERVED \n */ rlUInt32_t lanePosPolSel; /** * @brief Reserved for future use */ rlUInt32_t reserved1; }rlDevCsi2Cfg_t; /*! \brief * mmwave radar high speed clock configuration */ typedef struct rlDevHsiClk { /** * @brief High Speed Interface Clock configurations. Below table indicates possible values for different data rate supported \n HSICLKRATECODE (corresponding datarate in Mbps): \n SDR - 0x5(900 mbps), 0xA(600 mbps), 0x6(450 mbps), 0x2(400 mbps), 0xB(300 mbps), 0x7(225 mbps) \n DDR - 0xD(900 mbps), 0x9(600 mbps), 0x5(450 mbps), 0x1(400 mbps), 0xA(300 mbps), 0x6(225 mbps ), 0xB(150 mbps) \n */ rlUInt16_t hsiClk; /** * @brief Reserved for future use */ rlUInt16_t reserved; }rlDevHsiClk_t; /*! \brief * mmwave radar high speed Data path configuraiton */ typedef struct rlDevHsiCfg { /** * @brief Data format config */ rlDevDataFmtCfg_t *datafmt; /** * @brief Data path config */ rlDevDataPathCfg_t *dataPath; /** * @brief Data path clock configuration */ rlDevDataPathClkCfg_t *dataPathClk; }rlDevHsiCfg_t; /*! \brief * mmwave radar device config */ typedef struct rlDevConfig { /** * @brief Set CRC type of Async Event message from MSS to Host \n 0 - 16 Bit CRC \n 1 - 32 Bit CRC \n 2 - 64 Bit CRC \n */ rlUInt8_t aeCrcConfig; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief Reserved for future use */ rlUInt32_t reserved3; }rlDevMiscCfg_t; /****************************************************************************** * FUNCTION PROTOTYPES ****************************************************************************** */ /** * @defgroup Device Device * @brief Radar Device Management Module. * * The Device module has interface for Enabling and controlling Radar device. * Configures the callbacks(SPI, Interrupt, OS etc) for communication with device * It also allows Firmware download over SPI. * * Related Files * - rl_device.c * @addtogroup Device * @{ */ /* Device Interface Functions */ rlReturnVal_t rlDevicePowerOn(rlUInt8_t deviceMap, rlClientCbs_t clientCb); rlReturnVal_t rlDeviceAddDevices(rlUInt8_t deviceMap); rlReturnVal_t rlDeviceRemoveDevices(rlUInt8_t deviceMap); rlReturnVal_t rlDevicePowerOff(void); /* RF/DSP Start Functions */ rlReturnVal_t rlDeviceRfStart(rlUInt8_t deviceMap); /* File Download Functions */ rlReturnVal_t rlDeviceFileDownload(rlUInt8_t deviceMap, rlFileData_t *data, rlUInt16_t remChunks); /* Get Version Functions */ rlReturnVal_t rlDeviceGetMssVersion(rlUInt8_t deviceMap, rlFwVersionParam_t *data); rlReturnVal_t rlDeviceGetRfVersion(rlUInt8_t deviceMap, rlFwVersionParam_t *data); rlReturnVal_t rlDeviceGetVersion(rlUInt8_t deviceMap, rlVersion_t *data); rlReturnVal_t rlDeviceGetMmWaveLinkVersion(rlSwVersionParam_t *data); /* MCU Clock configuration Functions */ rlReturnVal_t rlDeviceMcuClkConfig(rlUInt8_t deviceMap, rlMcuClkCfg_t *data); /* PMIC Clock configuration Functions */ rlReturnVal_t rlDevicePmicClkConfig(rlUInt8_t deviceMap, rlPmicClkCfg_t *data); /* Latetnt fault test configuration Functions */ rlReturnVal_t rlDeviceLatentFaultTests(rlUInt8_t deviceMap, rllatentFault_t *data); /* Periodic test configuration Functions */ rlReturnVal_t rlDeviceEnablePeriodicTests(rlUInt8_t deviceMap, rlperiodicTest_t *data); /* Test pattern configuration Functions */ rlReturnVal_t rlDeviceSetTestPatternConfig(rlUInt8_t deviceMap, rltestPattern_t *data); /* mmWaveLink Protocol configuration Functions */ rlReturnVal_t rlDeviceConfigureCrc(rlCrcType_t crcType); rlReturnVal_t rlDeviceConfigureAckTimeout(rlUInt32_t ackTimeout); rlReturnVal_t rlDeviceSetRetryCount(rlUInt8_t retryCnt); /* Continuous streaming mode Functions */ rlReturnVal_t rlDeviceSetContStreamingModeConfig(rlUInt8_t deviceMap, rlDevContStreamingModeCfg_t *data); rlReturnVal_t rlDeviceGetContStreamingModeConfig(rlUInt8_t deviceMap, rlDevContStreamingModeCfg_t *data); rlReturnVal_t rlDeviceSetMiscConfig(rlUInt8_t deviceMap, rlDevMiscCfg_t *data); /* Get different fault status functions */ rlReturnVal_t rlDeviceGetCpuFault(rlUInt8_t deviceMap, rlCpuFault_t *data); rlReturnVal_t rlDeviceGetEsmFault(rlUInt8_t deviceMap, rlMssEsmFault_t *data); /*! Close the Doxygen group. @} */ /** * @defgroup Data_Path Data Path * @brief mmWave Radar Data Path(LVDS/CSI2) Module. * * The Data path module has interface for Enabling and controlling high speed * data interface such as CSI2 and LVDS. Configures the data format, data rate, * lane parameters. \n * Below diagram shows the data transfer for different data formats and lanes * on high speed interface * * @image html data_path_lanes.png * * Related Files * - rl_device.c * @addtogroup Data_Path * @{ */ /*data Path(LVDS/CSI2) configuration Functions */ rlReturnVal_t rlDeviceSetDataFmtConfig(rlUInt8_t deviceMap, rlDevDataFmtCfg_t*data); rlReturnVal_t rlDeviceGetDataFmtConfig(rlUInt8_t deviceMap, rlDevDataFmtCfg_t*data); rlReturnVal_t rlDeviceSetDataPathConfig(rlUInt8_t deviceMap, rlDevDataPathCfg_t*data); rlReturnVal_t rlDeviceGetDataPathConfig(rlUInt8_t deviceMap, rlDevDataPathCfg_t*data); rlReturnVal_t rlDeviceSetLaneConfig(rlUInt8_t deviceMap, rlDevLaneEnable_t*data); rlReturnVal_t rlDeviceGetLaneConfig(rlUInt8_t deviceMap, rlDevLaneEnable_t*data); rlReturnVal_t rlDeviceSetDataPathClkConfig(rlUInt8_t deviceMap, rlDevDataPathClkCfg_t*data); rlReturnVal_t rlDeviceGetDataPathClkConfig(rlUInt8_t deviceMap, rlDevDataPathClkCfg_t*data); rlReturnVal_t rlDeviceSetLvdsLaneConfig(rlUInt8_t deviceMap, rlDevLvdsLaneCfg_t*data); rlReturnVal_t rlDeviceGetLvdsLaneConfig(rlUInt8_t deviceMap, rlDevLvdsLaneCfg_t*data); rlReturnVal_t rlDeviceSetHsiConfig(rlUInt8_t deviceMap, rlDevHsiCfg_t*data); rlReturnVal_t rlDeviceSetHsiClk(rlUInt8_t deviceMap, rlDevHsiClk_t*data); rlReturnVal_t rlDeviceSetCsi2Config(rlUInt8_t deviceMap, rlDevCsi2Cfg_t*data); rlReturnVal_t rlDeviceGetCsi2Config(rlUInt8_t deviceMap, rlDevCsi2Cfg_t*data); /*! Close the Doxygen group. @} */ /* * END OF RL_DEVICE_H */ /**************************************************************************************** * FileName : rl_sensor.h * * Description : This file defines the functions to configure RF/Sensor in mmwave radar device. * **************************************************************************************** * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /**************************************************************************************** * FILE INCLUSION PROTECTION **************************************************************************************** */ /****************************************************************************** * INCLUDE FILES ****************************************************************************** */ /**************************************************************************************** * MACRO DEFINITIONS **************************************************************************************** */ /* Count of Test Sources*/ /* Number of chunks in Calibration data generated by radarSS */ /*! \brief * Supported maximum number of RX channels */ /*! \brief * Supported maximum number of TX channels */ /*! \brief * Enable/Disable RX/TX Channels */ /*! \brief * Start/Stop Frame Trigger constants */ /*! \brief * Supported maximum number of subframes in a frame */ /*! \brief * Supported maximum number of chirp profiles */ /*! \brief * Supported noise figure modes */ /*! \brief * Supported ADC data bitwidths */ /*! \brief * Supported ADC modes of operation */ /*! \brief * Supported ADC modes of operation */ /*! \brief * Supported Rx baseband bandwidths */ /*! \brief * Supported HPF-1 corner frequencies */ /*! \brief * Supported HPF-2 corner frequencies */ /*! \brief * Supported Rx gains */ /*! \brief * Supported frame sync modes */ /*! \brief * Supported frame start trigger modes */ /*! \brief * Supported Rx analog configurations */ /*! \brief * Supported Temperature Sensor Range in step of 10C */ /****************************************************************************** * GLOBAL VARIABLES/DATA-TYPES DEFINITIONS ****************************************************************************** */ /*! \brief * Rx/Tx Channel Configuration */ typedef struct rlChanCfg { /** * @ brief RX Channel Bitmap \n b0 RX0 Channel Enable \n 0 Disable RX Channel 0 \n 1 Enable RX Channel 0 \n b1 RX1 Channel Enable \n 0 Disable RX Channel 1 \n 1 Enable RX Channel 1 \n b2 RX2 Channel Enable \n 0 Disable RX Channel 2 \n 1 Enable RX Channel 2 \n b3 RX3 Channel Enable \n 0 Disable RX Channel 3 \n 1 Enable RX Channel 3 \n b15:4 - RESERVED \n */ rlUInt16_t rxChannelEn; /** * @brief TX Channel Bitmap \n b0 TX0 Channel Enable \n 0 Disable TX Channel 0 \n 1 Enable TX Channel 0\n b1 TX1 Channel Enable \n 0 Disable TX Channel 1 \n 1 Enable TX Channel 1 \n b2 TX2 Channel Enable \n 0 Disable TX Channel 2 \n 1 Enable TX Channel 2 \n b15:3 - RESERVED \n @note : TX2 is supported only on some of the devices, Please refer device data \n sheet. \n */ rlUInt16_t txChannelEn; /** * @brief Enable Cascading \n 0x0000 SINGLECHIP: Single mmWave sensor application\n 0x0001 MULTICHIP_MASTER: Multiple mmwave sensor application. This mmwave is \n the master chip and generates LO and conveys to other mmwave sensor. \n This is applicable only in AWR1243.\n 0x0002 MULTICHIP_SLAVE: Multiple mmwave sensor application. This mmwave is a \n slave chip and uses LO conveyed to it by the master mmwave sensor. \n This is applicable only in AWR1243 \n @note : Please refer device data sheet for cascading capability and 20G SYNC pins \n */ rlUInt16_t cascading; /** * @brief Cascading pinout config \n * b0 - CLKOUT_MASTER_DIS \n * 0 - 20G FM_CW_CLKOUT from master is enabled \n * 1 - 20G FM_CW_CLKOUT from master is disabled \n * b1 - SYNCOUT_MASTER_DIS \n * 0 - 20G FM_CW_SYNCOUT from master is enabled \n * 1 - 20G FM_CW_SYNCOUT from master is disabled \n * b2 - CLKOUT_SLAVE_EN \n * 0 - 20G FM_CW_CLKOUT from slave is disabled \n * 1 - 20G FM_CW_CLKOUT from slave is enabled \n * b3 - SYNCOUT_SLAVE_EN \n * 0 - 20G FM_CW_SYNCOUT from slave is disabled \n * 1 - 20G FM_CW_SYNCOUT from slave is enabled \n * b4 - INTLO_MASTER_EN \n * 0 - Master uses looped back LO \n * 1 - Master uses internal LO \n * b5 - OSCCLKOUT_MASTER_DIS \n * 0 - OSCCLKOUT from master is enabled \n * 1 - OSCCLKOUT from master is disabled \n * b15:6 - RESERVED \n */ rlUInt16_t cascadingPinoutCfg; }rlChanCfg_t; /*! \brief * ADC Bit and ADC Output format Configuration */ typedef struct rlAdcBitFormat { /** * @brief ADC out bits - 0(12 Bits), 1(14 Bits), 2(16 Bits) */ rlUInt32_t b2AdcBits :2; /** * @brief Reserved for Future use */ rlUInt32_t b6Reserved0 :6; /** * @brief Number of bits to reduce ADC full scale by Valid range: 0 to (16 - Number of ADC bits) For e.g. for 12 bit ADC output, this field can take values 0, 1, 2 or 3 \n For 14 bit ADC output, this field can take values 0, 1 or 2 \n For 16 bit ADC output, this field can take only value 0 \n */ rlUInt32_t b8FullScaleReducFctr:8; /** * @brief ADC out format- 0(Real), 1(Complex), 2(Complex with Image band), 3(Pseudo Real) */ rlUInt32_t b2AdcOutFmt :2; /** * @brief Reserved for Future use */ rlUInt32_t b14Reserved1 :14; }rlAdcBitFormat_t; /*! \brief * ADC format and payload justification Configuration */ typedef struct rlAdcOutCfg { /** * @brief ADC Data format */ rlAdcBitFormat_t fmt; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; }rlAdcOutCfg_t; /*! \brief * Binary phase modulation mode configuration */ typedef struct rlBpmModeCfg { /** * @brief BPM_SRC_SEL (select source of BPM pattern) \n 00 CHIRP_CONFIG_BPM (refer to rlBpmChirpCfg_t\n 01 RESERVED \n 10 RESERVED \n 11 RESERVED \n */ rlUInt16_t b2SrcSel :2; /** * @brief Reserved for Future use */ rlUInt16_t b1Reserved0 :1; /** * @brief Reserved for Future use */ rlUInt16_t b13Reserved1 :13; }rlBpmModeCfg_t; /*! \brief * Binary phase modulation KCounter configuration */ typedef struct rlBpmKCounterSel { /** * @brief K Counter Start Select (Reserved for future) */ rlUInt16_t b1BpmKStart :1; /** * @brief K Counter End Select (Reserved for future) */ rlUInt16_t b1BpmKEnd :1; /** * @brief Reserved for Future use */ rlUInt16_t b14Reserved :14; }rlBpmKCounterSel_t; /*! \brief * Binary phase modulation common configuration */ typedef struct rlBpmCommonCfg { /** * @brief BPM Mode configuration */ rlBpmModeCfg_t mode; /** * @brief Reserved for future, should set to zero. */ rlUInt16_t reserved0; /** * @brief Reserved for future, should set to zero. */ rlUInt16_t reserved1; /** * @brief Reserved for future, should set to zero. */ rlUInt16_t reserved2; /** * @brief Reserved for future, should set to zero. */ rlUInt32_t reserved3; /** * @brief Reserved for future, should set to zero. */ rlUInt32_t reserved4; }rlBpmCommonCfg_t; /*! \brief * Binary phase modulation common configuration */ typedef struct rlBpmChirpCfg { /** * @brief Chirp Start Index, Valid Range 0 -511 */ rlUInt16_t chirpStartIdx; /** * @brief Chirp End Index, Valid Range from chirpStartIdx to 511 */ rlUInt16_t chirpEndIdx; /** * @brief b0 CONST_BPM_VAL_TX0_TXOFF \n Value of Binary Phase Shift value for TX0, when during idle time \n b1 CONST_BPM_VAL_TX0_TXON \n Value of Binary Phase Shift value for TX0, during chirp \n b2 CONST_BPM_VAL_TX1_TXOFF \n Value of Binary Phase Shift value for TX1, when during idle time \n b3 CONST_BPM_VAL_TX1_TXON \n Value of Binary Phase Shift value for TX1, during chirp \n b4 CONST_BPM_VAL_TX2_TXOFF \n Value of Binary Phase Shift value for TX2, when during idle time \n b5 CONST_BPM_VAL_TX2_TXON \n Value of Binary Phase Shift value for TX2, during chirp \n b15:6 Reserved \n */ rlUInt16_t constBpmVal; /** * @brief Reserved for future */ rlUInt16_t reserved; }rlBpmChirpCfg_t; /*! \brief * Low Power mode configuration */ typedef struct rlLowPowerModeCfg { /** * @brief Reserved for future */ rlUInt16_t reserved; /** ADC Mode \n * @brief 0x00 : Regular ADC mode \n 0x01 : Low poer ADC mode \n */ rlUInt16_t lpAdcMode; }rlLowPowerModeCfg_t; /*! \brief * Power saving mode configuration */ typedef struct rlPowerSaveModeCfg { /** * @brief Low power state transition commands are defined as below \n Mode Definition \n 0 RESERVED \n 1 ENTER_RF_PWR_DOWN, device enters RF power down state from normal active state. \n 2 EXIT_RF_PWR_DOWN, device exits the RF power down state back to its previous state. \n 3 ENTER_APLL_PWR_DOWN, device enters APLL power down state from RF power down state. \n Application has to ensure, the device MSS and DSS clock system is switched to XTAL clock before powering down APLL. \n 4 EXIT_APLL_PWR_DOWN, device exits the APLL power down state. \n Application has to ensure, the device MSS and DSS clock system is switched back to APLL clock after powering up APLL. \n 5 ENTER_APLL_GPADC_PWR_DOWN, device enters APLL and GPADC power down state from RF power down state. \n Application has to ensure, the device MSS and DSS clock system is switched to XTAL clock before powering down APLL. \n 6 EXIT_APLL_GPADC_PWR_DOWN, device exits the APLL and GPADC power down state. \n Application has to ensure, the device MSS and DSS clock system is switched back to APLL clock after powering up APLL. \n 7-65535 RESERVED \n */ rlUInt16_t lowPwrStateTransCmd; /** * @brief Reserved for future use */ rlUInt16_t reserved0; /** * @brief Reserved for future use */ rlUInt32_t reserved[4U]; }rlPowerSaveModeCfg_t; /*! \brief * Profile config API parameters. A profile contains coarse parameters of FMCW chirp such as * start frequency, chirp slope, ramp time, idle time etc. Fine dithering values need * to be programmed in chirp configuration \ref rlChirpCfg_t * \note Maximum of 4 profiles can be configured. */ typedef struct rlProfileCfg { /** * @brief Profile index (0-3) */ rlUInt16_t profileId; /** * @brief Bit Description \n b0 FORCE_VCO_SEL (Not supported for production, debug purpose only) \n 0 - Use internal VCO selection \n 1 - Forced external VCO selection \n b1 VCO_SEL (Not supported for production, debug purpose only) \n 0 - VCO1 (77G:76 - 78 GHz or 60G:57 - 61 GHz) \n 1 - VCO2 (77G:77 - 81 GHz or 60G:60 - 64 GHz) \n @note 1: xWR1xxx devices: There is an overlap region of 77-78 GHz in which any \n of the VCOs can be used, for other regions use only the VCO which can \n work in that region. For e.g. for 76-78 GHz use only VCO1 and for \n 77-81GHz use only VCO2, for 77-78 GHz, any VCO can be used. Also note \n that users can inter-mix chirps from different VCOs within the same \n frame. @note 2: xWR6843 device: There is an overlap region of 60-61 GHz in which \n any of the VCOs can be used. \n b7:2 RESERVED \n */ rlUInt8_t pfVcoSelect; /** * @brief Bit Description \n b0 RETAIN_TXCAL_LUT \n 0 - Update TX calibration LUT \n 1 - Do not update TX calibration LUT \n b1 RETAIN_RXCAL_LUT \n 0 - Update RX calibration LUT and update RX IQMM correction \n 1 - Do not update RX calibration LUT \n b7:2 RESERVED \n If PF_TX_OUTPUT_POWER_BACKOFF is changed then set RETAIN_TXCAL_LUT to 0, \n else set it to 1 and if PF_RX_GAIN is changed, then set RETAIN_RXCAL_LUT to 0 \n else set them to 1. */ rlUInt8_t pfCalLutUpdate; /** * @brief Start frequency for each profile \n For 77GHz devices (76 GHz - 81 GHz): \n 1 LSB = 3.6e9 / 2^26 Hz = 53.644 Hz \n Valid range: 0x5471C71B to 0x5A000000 \n For 60GHz devices (57 GHz - 64 GHz): \n 1 LSB = 2.7e9 / 2^26 Hz = 40.233 Hz \n Valid range: Only even numbers from 0x5471C71C to 0x5ED097B4 \n */ rlUInt32_t startFreqConst; /** * @brief Idle time\n 1 LSB = 10 ns \n Valid range: 0 to 524287 \n */ rlUInt32_t idleTimeConst; /** * @brief Time of starting of ADC capture relative to the knee of the ramp\n 1 LSB = 10 ns \n Valid range: 0 to 4095 \n */ rlUInt32_t adcStartTimeConst; /** * @brief End of ramp time relative to the knee of the ramp\n 1 LSB = 10 ns\n Valid range: 0 to 500000 \n Ensure that the total frequency sweep is either within these ranges: \n 77G : 76 - 78 GHz or 77 - 81 GHz \n 60G : 57 - 60.75 GHz or 60 - 64 GHz \n */ rlUInt32_t rampEndTime; /** * @brief Concatenated code for output power backoff for TX0, TX1, TX2\n Bit Description \n b7:0 TX0 output power back off \n b15:8 TX1 output power back off \n b23:16 TX2 output power back off \n b31:24 Reserved \n This field defines how much the transmit power should be reduced from the maximum \n 1 LSB = 1 dB \n Valid Range for xWR1xxx devices: 0 to 20 \n Valid Range for xWR6x43 devices: 0 to 26 \n 0dB back-off corresponds to typically 12dBm power level in 1st gen xWR1xxx devices. 0dB back-off corresponds to typically 13dBm power level in xWR6843 devices. \n @note : For best inter-TX channel matching performance, same chirp profile and \n same TX backoff value should be used for all the TXs that are used in \n beam-forming */ rlUInt32_t txOutPowerBackoffCode; /** * @brief Concatenated phase shift for TX0/1/2,\n Bit Description \n b1:0 Reserved (set to 0b00) \n b7:2 TX0 phase shift value \n b9:8 Reserved (set to 0b00) \n b15:10 TX1 phase shift value \n b17:16 Reserved (set to 0b00) \n b23:18 TX2 phase shift value \n b31:24 Reserved \n 1 LSB = 360/2^6 = 5.625 degrees \n This field defines the additional phase shift to be introduced on each \n transmitter output. \n @note : Chirps corresponding to different profiles are not guaranteed to have \n phase coherency. */ rlUInt32_t txPhaseShifter; /** * @brief Ramp slope frequency, \n For 77GHz devices (76GHz to 81GHz): \n 1 LSB = (3.6e6 * 900) / 2^26 = 48.279 kHz/uS \n Valid range: -2072 to 2072 (Max 100MHz/uS) \n For 60GHz devices (57GHz to 64GHz): \n 1 LSB = (2.7e6 * 900) / 2^26 = 36.21 kHz/uS for 60GHz devices \n Valid range: Only even numbers in -6905 to 6905 (Max 250 MHz/uS) \n @note : Refer \ref rlRfApllSynthBwControl_t bandwidth control API for \n constraints on max slope. */ rlInt16_t freqSlopeConst; /** * @brief Time of start of transmitter relative to the knee of the ramp \n 1 LSB = 10ns \n Valid range: -4096 to 4095 \n */ rlInt16_t txStartTime; /** * @brief Number of ADC samples to capture in a chirp for each RX \n Valid range: 2 to MAX_NUM_SAMPLES\n Where MAX_NUM_SAMPLES is such that all the enabled RX channels' data fits \n into 16 kB memory memory in AWR1243/xWR1443 or 32 kB memory in xWR1642/ \n xWR6843/xWR1843, with each sample consuming 2 bytes for real ADC output \n case and 4 bytes for complex 1x and complex 2x ADC output cases \n number of RX chains ADC format Maximum Number of samples \n 4 complex 1024 \n 4 Real 2048 \n 2 Complex 2048 \n 2 Real 4096 \n */ rlUInt16_t numAdcSamples; /** * @brief ADC Sampling rate for each profile is encoded in \n 2 bytes (16 bit unsigned number) \n 1 LSB = 1 ksps \n Valid range: xWR1xxx devices: 2000 to 37500 (Max 15MHz IF bandwidth) \n xWR6x43 devices: 2000 to 25000 (Max 10MHz IF bandwidth) \n The maximum sampling rate supported is limited based on the information below. \n
When device supports 15 MHz IF bandwidth (refer device data sheet)
ADC mode Real/PseudoReal Complex1x Complex2x
Regular ADC mode37.5 Msps18.75 Msps37.5 Msps
Low power ADC mode(xWR1xxx)18.75 Msps9.375 Msps18.75 Msps
When device supports 10 MHz IF bandwidth (refer device data sheet)
ADC mode Real/PseudoReal Complex1x Complex2x
Regular ADC mode25 Msps12.5 Msps25 Msps
Low power ADC mode(xWR6x43)25 Msps12.5 Msps25 Msps
Low power ADC mode(xWR1xxx)18.75 Msps9.375 Msps18.75 Msps
When device supports 5 MHz IF bandwidth (refer device data sheet)
ADC mode Real/PseudoReal Complex1x Complex2x
Regular ADC mode12.5 Msps6.25 Msps12.5 Msps
Low power ADC mode(xWR6x43)12.5 Msps6.25 Msps12.5 Msps
Low power ADC mode(xWR1xxx)12.5 Msps6.25 Msps12.5 Msps
*/ rlUInt16_t digOutSampleRate; /** * @brief Code for HPF1 corner frequency\n 0x00 175 kHz \n 0x01 235 kHz \n 0x02 350 kHz \n 0x03 700 kHz \n */ rlUInt8_t hpfCornerFreq1; /** * @brief Code for HPF2 corner frequency\n 0x00 350 kHz \n 0x01 700 kHz \n 0x02 1.4 MHz \n 0x03 2.8 MHz \n */ rlUInt8_t hpfCornerFreq2; /** * @brief Number of transmitters to turn on during TX power \n calibration. During actual operation, if more than \n 1 TXs are enabled during the chirp, then enabling \n the same TXs during calibration will have better TX \n output power accuracy \n b2:0 TX enabled during TX0 calibration \n b0 - TX0, b1 - TX1, b2 - TX2 \n b5:3 TX enabled during TX1 calibration \n b3 - TX0, b4 - TX1, b5 - TX2 \n b8:6 TX enabled during TX2 calibration \n b6 - TX0, b7 - TX1, b8 - TX2 \n b14:9 RESERVED \n b15 Enable multi TX enable during TX power calibration. \n @note 1: If this bit is not set, only 1 TX is enabled \n during the TX power calibration. For e.g. during TX0 \n calibration, only TX0 will be enabled; during TX1 \n calibration, only TX1 will be enabled and so on. \n NOTE: This field is not applcicable for IWR6843 ES 1.0 */ rlUInt16_t txCalibEnCfg; /** * @brief b5:0 Code for Rx VGA gain\n 1 LSB = 1 dB\n Valid values: For xWR1xxx : all even values from 24 to 52 For xWR6x43 : all even values from 30 to 48 b7:6 Code for RF gain target (Not applicable for IWR6843 ES1.0, \n RF gain is fixed to 34dB). \n For xWR1243/xWR1443/xWR1642/xWR1843: 00 - 30 dB \n 01 - 34 dB \n 10 - RESERVED \n 11 - 26 dB \n For xWR6843 ES 2.0: 00 - 30 dB \n 01 - 33 dB \n 10 - 36 dB \n 11 - RESERVED \n b15:8 RESERVED \n In IWR6843 ES1.0 device, Rx Gain is not accurate and not calibrated. \n The RF gain is 34dB and total Rx gain can be varied from 28dB to 56dB \n */ rlUInt16_t rxGain; /** * @brief Reserved for Future use */ rlUInt16_t reserved; } rlProfileCfg_t; /*! \brief * Chirp config API parameters. This structure contains fine dithering to coarse profile * defined in \ref rlProfileCfg_t. It also includes the selection of Transmitter and * binary phase modulation for a chirp.\n * @note : One can define upto 512 unique chirps.These chirps need to be included in * frame configuration structure \ref rlFrameCfg_t to create FMCW frame */ typedef struct rlChirpCfg { /** * @brief Chirp start index (0-511) */ rlUInt16_t chirpStartIdx; /** * @brief Chirp end index (0-511) */ rlUInt16_t chirpEndIdx; /** * @brief Associated profile id (0-3) */ rlUInt16_t profileId; /** * @brief Reserved for Future use */ rlUInt16_t reserved; /** * @brief Ramp start frequency, \n For 77GHz devices(76GHz to 81GHz): \n 1 LSB = 3.6e9/2^26 = 53.644 Hz \n valid range = 0-8388607 \n For 60GHz devices(57GHz to 64GHz): \n 1 LSB = 2.7e9/2^26 = 40.233 Hz \n valid range = Only even numbers from 0-8388607 \n */ rlUInt32_t startFreqVar; /** * @brief Ramp slope\n For 77GHz devices(76GHz to 81GHz): \n 1 LSB = 3.6e6 * 900/2^26 = 48.279 KHz/us \n valid range = 0-63 \n For 60GHz devices(57GHz to 64GHz): \n 1 LSB = 2.7e6 * 900/2^26 = 36.21 KHz/us \n valid range = Only even numbers between 0 to 63 \n */ rlUInt16_t freqSlopeVar; /** * @brief Idle time for each chirp\n 1 LSB = 10ns\n valid range = 0-4096 \n */ rlUInt16_t idleTimeVar; /** * @brief Adc start time for each chirp \n 1 LSB = 10ns \n valid range = 0-4096 \n */ rlUInt16_t adcStartTimeVar; /** * @brief Tx enable selection bit mask \n b0 Enable TX0 \n 0 Tx0 Disable \n 1 Tx0 Enable \n b1 Enable TX1 \n 0 Tx1 Disable \n 1 Tx1 Enable \n b2 Enable TX2 \n 0 Tx2 Disable \n 1 Tx2 Enable \n @note : Maximum of only 2 TX can be turned in a chirp \n */ rlUInt16_t txEnable; }rlChirpCfg_t; /*! \brief * Chirp start, end Index parameters for rlGetChirpConfig */ typedef struct rlWordParam { rlUInt16_t halfWordOne; rlUInt16_t halfWordTwo; }rlWordParam_t; /*! \brief * Frame config API parameters */ typedef struct rlFrameCfg { /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Start Index of Chirp Valid range = 0-511 */ rlUInt16_t chirpStartIdx; /** * @brief End Index of Chirp Valid range = chirpStartIdx-511 */ rlUInt16_t chirpEndIdx; /** * @brief Number of times to repeat from chirpStartIdx to chirpStartIdx in each frame, \n valid range = 1 to 255 \n */ rlUInt16_t numLoops; /** * @brief Number of frame to transmit \n Valid Range 0 to 65535 (0 for infinite frames) \n */ rlUInt16_t numFrames; /** * @brief Number of ADC samples to capture This parameter is required only for AWR1243 and \n configures the size of ADC samples per chirp to be sent on LVDS/CSI2 \n interface.\n It should be configured as: For real/pseudo real ADC data - numADCSamples = rlProfileCfg_t.numAdcSamples \n For complex1x/complex2x ADC data - \n numADCSamples = (rlProfileCfg_t.numAdcSamples ) * 2 \n */ rlUInt16_t numAdcSamples; /** * @brief Frame repitition period \n PERIOD >= Sum total time of all chirps + InterFrameBlankTime, where, Sum total time of all chirps = Num Loops * Num chirps * Chirp Period. \n InterFrameBlankTime is primarily for sensor calibration/monitoring, thermal control, transferring out any safety monitoring data if requested, hardware reconfiguration for next frame, re-triggering of next frame. \n InterFrameBlankTime >= 300 μs typically. \n Add 150 us to InterFrameBlankTime if data-path reconfiguration needed in frame boundary due to change in profile. \n 1 LSB = 5 ns \n Valid range : 300 us to 1.342 s \n */ rlUInt32_t framePeriodicity; /** * @brief Selects the mode for triggering start of transmission of frame \n 0x0001 SWTRIGGER (Software API based triggering): \n Frame is triggered upon receiving rlSensorStart\n There could be several tens of micro seconds uncertainty in triggering. \n @note : This mode is not applicable if this mmwave device is configured as \n MULTICHIP_SLAVE in rlChanCfg_t \n 0x0002 HWTRIGGER (Hardware SYNC_IN based triggering): \n Each frame is triggered by rising edge of pulse in SYNC_IN pin, after receiving rlSensorStart (this is to prevent spurious transmission). W.r.t. the SYNC_IN pulse, the actual transmission has ~160ns delay and 5ns uncertainty in SINGLECHIP and only a 300 ps uncertainty (due to tight inter-chip synchronization needed) in MULTICHIP sensor applications as defined in rlChanCfg_t. \n For more details please refer to device datasheet. \n */ rlUInt16_t triggerSelect; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Number of dummy chirps which will run in the rampgen at the end of the frame. The * ADC data, CP and CQ data for these chirps will not be sent out from the \n * device/DFE. \n * 1LSB = 1 dummy chirp in the end of frame. \n * valid range: 0 to 128 (should be less than the total number of chirps in a \n * frame). \n */ rlUInt8_t numDummyChirpsAtEnd; /** * @brief Optional time delay from sync_in trigger to the occurance of frame chirps \n Applicable only in SINGLECHIP sensor applications, as defined in rlChanCfg_t.\n It is recommended only for staggering the transmission of multiple mmwave \n sensors around the car for interference avoidance, if needed.\n 1 lsb = 5 ns \n Typical range is 0 to 100 micro seconds. \n */ rlUInt32_t frameTriggerDelay; }rlFrameCfg_t; /*! \brief * Advance Frame config API Subframe configuration */ typedef struct rlSubFrameCfg { /** * @brief Force profile index. This is applicable only if FORCE_SINGLE_PROFILE is set to 1 */ rlUInt16_t forceProfileIdx; /** * @brief Start Index of Chirp Valid range = 0-511 */ rlUInt16_t chirpStartIdx; /** * @brief Num of unique Chirps per burst including start index Valid range = 1 - 512 */ rlUInt16_t numOfChirps; /** * @brief No. of times to loop through the unique chirps in each burst, without gaps, \n using HW.\n valid range = 1 to 255 \n */ rlUInt16_t numLoops; /** * @brief burstPeriodicity >= (numLoops)* (sum total of all unique chirp times per burst) + InterBurstBlankTime, \n where InterBurstBlankTime is primarily for sensor calibration / monitoring, \n thermal control, and some minimum time needed for triggering next burst. \n InterBurstBlankTime >= 100 us. Refer a NOTE at end of this API for more info. \n With loop back enabled, InterBurstBlankTime >= 500 us \n @note : Across bursts, if the value numOfChirps, is not a constant, then the \n actual available blank time can vary and needs to be accounted for \n 1 LSB = 5 ns \n */ rlUInt32_t burstPeriodicity; /** * @brief Chirp Start address increment for next burst, \n next_burst_chirp_start_idx = last_chirp_end_index + \n h_ChirpStartIdxIncr 0 - 511, 0 = 2nd burst = 1st burst \n */ rlUInt16_t chirpStartIdxOffset; /** * @brief Num of bursts in the sub-frame. Valid Range: 1 - 512 \n * Valid range: 1 to 16 for loop-back sub-frame \n */ rlUInt16_t numOfBurst; /** * @brief Number of times to loop over the set of above defined bursts, in the sub frame. \n Valid Range: 1 - 64 \n This field is not applicable for loop-back sub-frame \n */ rlUInt16_t numOfBurstLoops; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief subFramePeriodicity >= Sum total time of all bursts + InterSubFrameBlankTime, \n Where, Sum total time of all bursts = numOfBurstLoops * numOfBurst * \n burstPeriodicity. \n InterSubFrameBlankTime is primarily for sensor calibration / monitoring, \n thermal control, transferring out any safety monitoring data if requested, \n hardware reconfiguration for next sub frame, re-triggering of next SF (~10us). \n The hardware reconfiguration time, which is needed to transfer out the SF's \n InterSubFrameBlankTime >= 300 us. \n Add 150 us to InterSubFrameBlankTime if data-path re-configuration needed in sub-frame boundary due to change in profile. \n 1 LSB = 5 ns \n Valid range 300 us to 1.342 s. \n */ rlUInt32_t subFramePeriodicity; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; }rlSubFrameCfg_t; /*! \brief * Advance Frame Sequence config API parameters rlAdvFrameCfg, 148 bytes */ typedef struct rlAdvFrameSeqCfg { /** * @brief Number of sub frames enabled in this frame Valid range: 1 to 4 */ rlUInt8_t numOfSubFrames; /** * @brief Force profile. \n 0x0 The profile index set in rlSetChirpConfig API governs which profile is \n used when that chirp is transmitted \n 0x1 The profile index indicated in rlSetChirpConfig API is ignored and all \n the chirps in each sub frame use a single profile as indicated by that sub \n frame's profile forceProfileIdx. \n @note : This Field is not used/applicable for loop-back sub-frame. \n */ rlUInt8_t forceProfile; /** * @brief Bit Definition \n b0 LOOPBACK_CFG_EN \n 0 - Disable \n 1 - Enable \n b2:1 SUB_FRAME_ID for which the loop-back configuration applies \n b7:3 RESERVED \n */ rlUInt8_t loopBackCfg; /** * @brief Sub frame trigger * 0 - Disabled (default mode, i.e no trigger is required in Frame SW triggered \n * mode and a pulse trigger is required for every burst start in frame HW \n * triggered mode) \n * 1 - Enabled (Need to trigger each sub-frame either by SW in \n * software triggered mode through AWR_SUBFRAME_START_CONF_SB API or HW \n * pulse in hardware triggered mode) \n * @note : Disable WDT if this mode is enabled. */ rlUInt8_t subFrameTrigger; /** * @brief Subframe config for 4 sub frames */ rlSubFrameCfg_t subFrameCfg[(4U)]; /** * @brief Number of frames to transmit (1 frame = all enabled sub frames). If set to 0, \n frames are transmitted endlessly till Frame Stop message is received.\n Valid range: 0 to 65535 \n */ rlUInt16_t numFrames; /** * @brief Selects the mode for triggering start of transmission of frame \n 0x0001 SWTRIGGER (Software API based triggering): \n Frame is triggered upon receiving rlSensorStart There could be several tens \n of micro seconds uncertainty in triggering. \n @note :This mode is not applicable if this mmwave device is configured as \n MULTICHIP_SLAVE in rlChanCfg_t \n 0x0002 HWTRIGGER (Hardware SYNC_IN based triggering): \n Each frame is triggered by rising edge of pulse in SYNC_IN pin, after \n receiving rlSensorStart (this is to \n prevent spurious transmission). \n W.r.t. the SYNC_IN pulse, the actual transmission has 5ns uncertainty in \n SINGLECHIP and only a 300 ps uncertainty (due to tight inter-chip \n synchronization needed) in MULTICHIP sensor applications as defined in \n rlChanCfg_t. \n */ rlUInt16_t triggerSelect; /** * @brief Optional time delay from sync_in trigger to the occurance of frame chirps \n Applicable only in SINGLECHIP sensor applications, as defined in rlChanCfg_t.\n It is recommended only for staggering the transmission of multiple mmwave \n sensors around the car for interference avoidance, if needed. \n 1 lsb = 5 ns \n Typical range is 0 to few tens of micro seconds. \n */ rlUInt32_t frameTrigDelay; /** * @brief Reserved for Future use */ rlUInt32_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; }rlAdvFrameSeqCfg_t; /*! \brief * Frame config API parameters */ typedef struct rlFrameApplyCfg { /** * @brief Number of Chirps per Frame */ rlUInt32_t numChirps; /** * @brief Number of half words in ADC buffer per chirp \n Example 1: In real mode, if number of ADC samples per chirp is 256 then this \n value will be 256 \n Example 2: In complex1x or complex2x modes,if number of ADC samples per chirp \n is 256 then this value will be 512 \n */ rlUInt16_t numAdcSamples; /** * @brief Reserved for Future use */ rlUInt16_t reserved; }rlFrameApplyCfg_t; /*! \brief * Sub Frame data config API parameters */ typedef struct rlSubFrameDataCfg { /** * @brief Number of Chirps in Sub-Frame = numOfChirps * numLoops * numOfBurst * burstLoop */ rlUInt32_t totalChirps; /** * @brief Number of half words of ADC samples per data packet in sub frame 1 \n Example 1: In real mode, if number of ADC samples per chirp in subframe1 is 256 then this value will be 256 \n Example 2: In complex1x or complex2x modes, if number of ADC samples per chirp in subframe1 is 256 then this value will be 512 \n In AWR1243/xWR1443: Program this as number of ADC samples in each chirp of this sub frame (required to be the same) \n Exception: Can do number of chirps based ping-pong as in xWR1642 (see below), if CP/CQ are not needed. Useful for chirp stitching use case. \n In xWR1642/xWR1843(For reference only): The ADC samples corresponding to one or more chirps can be grouped and sent to the DSP as a single packet. Program this as the number of half words of ADC samples per packet. Ensure that in one sub frame, there is integer number of such packets. \n Maximum size of a data packet: (16384 - 1) half words */ rlUInt16_t numAdcSamples; /** * @brief Number of Chirps Per Data Packet to process at a time in sub frame 1. \n In AWR1243/xWR1443: Program this as 1. \n Exception: Can be > 1 as in 16xx if CP/CQ is not needed. Useful for chirp stitching use case. \n In xWR1642/xWR1843(For reference only): The ADC samples corresponding to one or more chirps can be grouped and sent to the DSP as a single packet. Program this as the corresponding number of chirps per packet. \n Maximum value = 8. \n Note on maximum size: 8 chirps for CP and BPM. */ rlUInt8_t numChirpsInDataPacket; /** * @brief Reserved for Future use */ rlUInt8_t reserved; }rlSubFrameDataCfg_t; /*! \brief * Advance Frame data config API parameters. * This structure is only applicable when mmWaveLink instance is running on * External Host and connected to AWR1243 device. */ typedef struct rlAdvFrameDataCfg { /** * @brief Number of Sub Frames, Valid Range (1 - 4) */ rlUInt8_t numSubFrames; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Sub Frame data configuration array. */ rlSubFrameDataCfg_t subframeDataCfg[(4U)]; }rlAdvFrameDataCfg_t; /*! \brief * Advance Frame Sequence config API parameters rlAdvFrameCfg, 148 bytes */ typedef struct rlAdvFrameCfg { /** * @brief Advance Frame sequence and Subframe configuration */ rlAdvFrameSeqCfg_t frameSeq; /** * @brief Advance Frame data configuration. Applicable with AWR1243 device only */ rlAdvFrameDataCfg_t frameData; }rlAdvFrameCfg_t; /*! \brief * Continous Mode config API parameters */ typedef struct rlContModeCfg { /** * @brief Start frequency \n For 77GHz devices (76 - 81 GHz): \n 1 LSB = 3.6e9 / 2^26 Hz = 53.644 Hz \n Valid range: 0x5471C71B to 0x5A000000 \n For 60GHz devices (57 - 64 GHz): \n 1 LSB = 2.7e9 / 2^26 Hz = 40.233 Hz \n Valid range: Only even numbers from 0x5471C71C to 0x5ED097B4 \n */ rlUInt32_t startFreqConst; /** * @brief Concatenated code for output power backoff for TX0, TX1, TX2 \n b7:0 TX0 output power back off \n b15:8 TX1 output power back off \n b23:16 TX2 output power back off \n b31:24 Reserved \n This field defines how much the transmit power should be reduced from the \n maximum. \n 1 LSB = 1 dB \n */ rlUInt32_t txOutPowerBackoffCode; /** * @brief Concatenated phase shift for TX0/1/2, \n Bit Description \n b1:0 Reserved (set to 0b00) \n b7:2 TX0 phase shift value \n b9:8 Reserved (set to 0b00) \n b15:10 TX1 phase shift value \n b17:16 Reserved (set to 0b00) \n b23:18 TX2 phase shift value \n b31:24 Reserved \n 1 LSB = 360/2^6 = 5.625 degrees \n This field defines the additional phase shift to be introduced on each \n transmitter output. \n In IWR6843 ES1.0, only 0 degree phase is supported. \n */ rlUInt32_t txPhaseShifter; /** * @brief ADC Sampling rate for each profile is encoded in \n 2 bytes (16 bit unsigned number) \n 1 LSB = 1 ksps \n Valid range 2000 to 37500 \n */ rlUInt16_t digOutSampleRate; /** * @brief Code for HPF1 corner frequency \n 0x00 175 kHz \n 0x01 235 kHz \n 0x02 350 kHz \n 0x03 700 kHz \n */ rlUInt8_t hpfCornerFreq1; /** * @brief Code for HPF2 corner frequency \n 0x00 350 kHz \n 0x01 700 kHz \n 0x02 1.4 MHz \n 0x03 2.8 MHz \n */ rlUInt8_t hpfCornerFreq2; /** * @brief This field defines RX gain for continuous streaming mode. Bit Definition [5:0] RX_GAIN This field defines RX gain for each profile. 1 LSB = 1 dB Valid values: For xWR1xxx : all even values from 24 to 52 For xWR6x43 : all even values from 30 to 48 [7:6] RF_GAIN_TARGET (Not applicable for IWR6843 ES1.0, In IWR6843 ES1.0 \n RF gain is fixed to 36 dB) \n For xWR1243/xWR1443/xWR1642/xWR1843: Value RF gain target 00 30 dB \n 01 34 dB \n 10 RESERVED \n 11 26 dB \n For xWR6843 ES 2.0: Value RF gain target 00 30 dB \n 01 33 dB \n 10 36 dB \n 11 RESERVED \n */ rlUInt8_t rxGain; /** * @brief Bit Description b0 FORCE_VCO_SEL 0 - Use internal VCO selection 1 - Forced external VCO selection b1 VCO_SEL 0 - VCO1 (77G:76 - 78 GHz or 60G:57 - 60.75 GHz) 1 - VCO2 (77G:77 - 81 GHz or 60G:60 - 64 GHz) b7:2 RESERVED */ rlUInt8_t vcoSelect; /** * @brief Reserved for Future use */ rlUInt16_t reserved; }rlContModeCfg_t; /*! \brief * Continous Mode Enable API parameters */ typedef struct rlContModeEn { /** * @brief Enable continuous steaming mode \n 0x00 Disable continuous streaming mode \n 0x01 Enable continuous streaming mode \n */ rlUInt16_t contModeEn; /** * @brief Reserved for Future use */ rlUInt16_t reserved; }rlContModeEn_t; /*! \brief * Frame Trigger API parameters RL_RF_FRAMESTARTSTOP_CONF_SB */ typedef struct rlFrameTrigger { /** * @brief Start/Stop Frame \n 0x0000 - Stop the transmission of frames after the current frame is over at the frame boundary \n 0x0001 - Trigger a frame in software triggered mode. In hardware SYNC_IN \n triggered mode, this command allows subsequent SYNC_IN trigger to \n be honored \n */ rlUInt16_t startStop; /** * @brief Reserved for Future use */ rlUInt16_t reserved; }rlFrameTrigger_t; /*! \brief * The Object position and signal strength parameter structure */ typedef struct rlTestSourceObject { /** * @brief Relative position in Cartesian coordinate from sensor to objects \n X position of object 1lsb = 1cm, -32768cm to 32767cm \n */ rlInt16_t posX; /** * @brief Relative position in Cartesian coordinate from sensor to objects \n Y position of object 1lsb = 1cm, 0 -32767 cm \n */ rlInt16_t posY; /** * @brief Relative position in Cartesian coordinate from sensor to objects \n Z position of object 1lsb = 1cm, -32768cm to 32767cm \n */ rlInt16_t posZ; /** * @brief Relative velocity in Cartesian coordinate \n X velocity of object 1lsb = 1 cm/s, Valid Range -5000 to +5000 \n */ rlInt16_t velX; /** * @brief Relative velocity in Cartesian coordinate \n Y velocity of object 1lsb = 1cm/s, Valid Range -5000 to +5000 \n */ rlInt16_t velY; /** * @brief Relative velocity in Cartesian coordinate \n Z velocity of object 1lsb = 1cm/s, Valid Range -5000 to +5000 \n */ rlInt16_t velZ; /** * @brief Reflecting obj' sig level at ADC o/p, relative to ADC Full Scale \n 1 LSB = -0.1 dBFS, Valid Range 0 to 950 \n */ rlUInt16_t sigLvl; /** * @brief Boundary min limit, Obj location resets to posX if cross boundary \n X position of min boundary 1lsb = 1cm, -32768cm to 32767cm \n */ rlInt16_t posXMin; /** * @brief Boundary min limit, Obj location resets to posY if cross boundary \n Y position of min boundary 1lsb = 1cm, 0 to 32767cm \n */ rlInt16_t posYMin; /** * @brief Boundary min limit, Obj location resets to posZ if cross boundary \n Z position of min boundary 1lsb = 1cm, -32768cm to 32767cm \n */ rlInt16_t posZMin; /** * @brief Boundary max limit, Obj location resets to posX if cross boundary \n X position of max boundary 1lsb = 1cm, -32768cm to 32767cm \n */ rlInt16_t posXMax; /** * @brief Boundary max limit, Obj location resets to posX if cross boundary \n Y position of max boundary 1lsb = 1cm, 0 to 32767cm \n */ rlInt16_t posYMax; /** * @brief Boundary max limit, Obj location resets to posX if cross boundary \n Z position of max boundary 1lsb = 1cm, -32768cm to 32767cm \n */ rlInt16_t posZMax; }rlTestSourceObject_t; /*! \brief * The Antenna position parameter structure */ typedef struct rlTestSourceAntPos { /** * @brief Antenna position X 1lsb=wavelength/8 Valid range = +/-15 wave lengths */ rlInt8_t antPosX; /** * @brief Antenna position Z 1lsb=wavelength/8 Valid range = +/-15 wave lengths */ rlInt8_t antPosZ; }rlTestSourceAntPos_t; /*! \brief * Test source config API parameters E_API_AR_TEST_SOURCE_CONF_SB */ typedef struct rlTestSource { /** * @brief Arary of test Objects */ rlTestSourceObject_t testObj[(2U)]; /** * @brief Simulated Position of Rx Antennas */ rlTestSourceAntPos_t rxAntPos[(4U)]; /** * @brief Reserved for Future use */ rlUInt32_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; }rlTestSource_t; /*! \brief * Test source Enable API parameters RL_RF_TEST_SOURCE_ENABLE_SB */ typedef struct rlTestSourceEn { /** * @brief Test source Enable - 1, Disable - 0 */ rlUInt16_t tsEnable; /** * @brief Reserved for Future use */ rlUInt16_t reserved; }rlTestSourceEnable_t; /*! \brief * RF characterization Time and Temperature data structure */ typedef struct rlRfTempData { /** * @brief radarSS local Time from device powerup. 1 LSB = 1 ms */ rlUInt32_t time; /** * @brief RX0 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpRx0Sens; /** * @brief RX1 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpRx1Sens; /** * @brief RX2 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpRx2Sens; /** * @brief RX3 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpRx3Sens; /** * @brief TX0 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpTx0Sens; /** * @brief TX1 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpTx1Sens; /** * @brief TX2 temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpTx2Sens; /** * @brief PM temperature sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpPmSens; /** * @brief Digital temp sensor reading (signed value). 1 LSB = 1 deg C */ rlInt16_t tmpDig0Sens; /** * @brief Second digital temp sensor reading (signed value).( applicable only in \n * xWR1642/xWR6843/xWR1843.) \n * 1 LSB = 1 deg C \n */ rlInt16_t tmpDig1Sens; }rlRfTempData_t; /*! \brief * The DFE Statistics for Rx Channel for particular profile */ typedef struct rlDfeRxdStatReport { /** * @brief Average DC value in I chain for profile x, RX channel x */ rlInt16_t iAvgDC; /** * @brief Average DC value in Q chain for profile x, RX channel x */ rlInt16_t qAvgDC; /** * @brief Average power in I chain for profile x, RX channel x */ rlUInt16_t iAvgPwr; /** * @brief Average power in Q chain for profile x, RX channel x */ rlUInt16_t qAvgPwr; /** * @brief Average cross correlation between I and Q chains for profile x, RX channel x */ rlInt32_t iqAvgCroCorrel; } rlDfeRxStatReport_t; /*! \brief * The DFE Statistics Report Contents */ typedef struct rlDfeStatReport { /** * @brief Contain DFE statistic report for all profile and receiver */ rlDfeRxStatReport_t dfeStatRepo[(4U)][(4U)]; }rlDfeStatReport_t; /*! \brief * Dynamic power saving API parameters */ typedef struct rlDynPwrSave { /** * @brief Enable dynamic power saving during inter-chirp IDLE times by \n * turning off various circuits e.g. TX, RX, LO. 3 LSB is vaild \n * b0 Enable power save by switching off TX during inter-chirp IDLE period \n * 0 Disable \n * 1 Enable \n * b1 Enable power save by switching off RX during inter-chirp IDLE period \n * 0 Disable \n * 1 Enable \n * b2 Enable power save by switching off LO distribution during inter-chirp IDLE\n * period \n * 0 Disable \n * 1 Enable \n */ rlUInt16_t blkCfg; /** * @brief Reserved for Future use */ rlUInt16_t reserved; } rlDynPwrSave_t; /*! \brief * API RF device Config SBC M_API_AR_RF_DEV_CONF_SBC */ typedef struct rlRfDevCfg { /** * @brief Bit Definition \n * b1:0 Global Async event direction \n * 00 - radarSS to MSS 01 - radarSS to HOST\n * 10 - radarSS to DSS 11 - RESERVED \n * The ASYNC_EVENT_DIR controls the direction for following ASYNC_EVENTS \n * [1.] CPU_FAULT [2.] ESM_FAULT [3.] ANALOG_FAULT \n * All other ASYNC_EVENTs are sent to the subsystem which issues the API \n * b3:2 Monitoring Async Event direction * 00 - radarSS to MSS 01 - radarSS to HOST\n * 10 - radarSS to DSS 11 - RESERVED \n * b31:4 Reserved */ rlUInt32_t aeDirection; /** * @brief Bit Definition \n * b0: FRAME_START_ASYNC_EVENT_DIS \n * 0 Frame Start async event enable \n * 1 Frame Start async event disable \n * b1: FRAME_STOP_ASYNC_EVENT_DIS \n * 0 Frame Stop async event enable \n * 1 Frame Stop async event disable \n * b7:2 Reserved */ rlUInt8_t aeControl; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Bit Definition \n * b0: Watchdog enable/disable \n * 0 Keep watchdog disabled \n * 1 Enable watch dog \n * b7:1: Reserved \n * @note :The Windowed WDT can be enabled only in SW triggered framing Mode or in \n * cascade mode where frames of all the devices synchronized with same clock \n * source, if frames are triggered from Hw trigger pulse generated from \n * unsynchronized clock then WDT can not be enabled. \n */ rlUInt8_t bssDigCtrl; /** * @brief CRC Config for Asynchornous event message \n * Value Description \n * 0 16 bit CRC for radarSS async events \n * 1 32 bit CRC for radarSS async events \n * 2 64 bit CRC for radarSS async events \n * */ rlUInt8_t aeCrcConfig; /** * @brief Reserved for Future use */ rlUInt8_t reserved2; /** * @brief Reserved for Future use */ rlUInt16_t reserved3; } rlRfDevCfg_t; /*! \brief * Num of samples to collect for API GPADC sensors * sampleCnt : Number of samples to collect @625KHz */ typedef struct rlGpAdcSamples { /** * @brief Number of samples to collect */ rlUInt8_t sampleCnt; /** * @brief Number of samples to skip before collecting the data * 1 LSB = 0.8 us, Valid range: 0 to 12 us */ rlUInt8_t settlingTime; }rlGpAdcSamples_t; /*! \brief * API radarSS GPADC API MEAS SET SBC M_API_AR_RF_GPADC_API_SET_SB */ typedef struct rlGpAdcCfg { /** * @brief Enable different sensors \n [b0] 1: ANATEST1 Enable, 0: ANATEST1 Disable \n [b1] 1: ANATEST2 Enable, 0: ANATEST2 Disable \n [b2] 1: ANATEST3 Enable, 0: ANATEST3 Disable \n [b3] 1: ANATEST4 Enable, 0: ANATEST4 Disable \n [b4] 1: ANAMUX Enable, 0: ANAMUX Disable \n [b5] 1: VSENSE Enable, 0: VSENSE Disable \n [b7:6] Reserved \n */ rlUInt8_t enable; /** * @brief Enable buffer for each input \n [b0] 1: ANATEST1 buffer enable, 0: ANATEST1 buffer disable \n [b1] 1: ANATEST2 buffer enable, 0: ANATEST2 buffer disable \n [b2] 1: ANATEST3 buffer enable, 0: ANATEST3 buffer disable \n [b3] 1: ANATEST4 buffer enable, 0: ANATEST4 buffer disable \n [b4] 1: ANAMUX buffer enable, 0: ANAMUX buffer disable \n [b7:5] Reserved \n */ rlUInt8_t bufferEnable; /** * @brief Configure number of sample to be \n collected for each sensor This array of numOfSamples is for the sensors \n which are enabled in above parameter 'enable' \n */ rlGpAdcSamples_t numOfSamples[(6U)]; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1[3U]; } rlGpAdcCfg_t; /*! \brief * Radar RF LDO bypass enable/disable configuration */ typedef struct rlRfLdoBypassCfg { /** * @brief Enable LDO bypass \n [b0] 1: RF LDO bypassed, Should be used only when 1.0V RF supply is provided 0: RF LDO not bypassed(default), Should be used only when 1.3V RF supply is provided \n [b1] 0: PA LDO input is enabled\n 1: PA LDO input is disabled (3 TX use case). (To be used only when VIN_RF2 is shorted to VOUT_PA on board and VIN_RF2 is 1.0V) \n [b15:2] Reserved \n usecase LDO bypass PA LDO disable \n 1.3V RF supply 1 and 1.3V RF supply 2 0 0 1.0V RF supply 1 and 1.0V RF supply 2 1 0 1.0V RF supply 1 and 1.0V RF supply 2 1 1 and RF supply 1 shorted to Vout PA */ rlUInt16_t ldoBypassEnable; /** * @brief IR drop is the voltage drop from the PMIC output to the device pin. The user should program the voltage drop in percentage units which will be used for measuring the external supplies. \n Value Description \n 0 IR drop of 0% \n 1 IR drop of 3% \n 2 IR drop of 6% \n 3 IR drop of 9% \n */ rlUInt8_t supplyMonIrDrop; /** * @brief IO supply indicator. This is used to indicate the IO supply to the MMIC device * for setting the correct voltage monitor thresholds * Value Description \n * 0 3.3 V IO supply \n * 1 1.8 V IO supply \n */ rlUInt8_t ioSupplyIndicator; }rlRfLdoBypassCfg_t; /*! \brief * Radar RF Phase Shift enable/disable configuration */ typedef struct rlRfPhaseShiftCfg { /** * @brief Chirp Start Index, Valid Range 0 -511 */ rlUInt16_t chirpStartIdx; /** * @brief Chirp End Index, Valid Range from chirpStartIdx to 511 */ rlUInt16_t chirpEndIdx; /** * @brief TX0 phase shift definition \n [b1:0] reserved (set it to 0b00) \n [b7:2] TX0 phase shift value \n 1 LSB = 360/2^6 = 5.625 degrees\n Valid range: 0 to 63 \n */ rlUInt8_t tx0PhaseShift; /** * @brief TX1 phase shift definition \n [b1:0] reserved (set it to 0b00) \n [b7:2] TX1 phase shift value \n 1 LSB = 360/2^6 = 5.625 degrees\n Valid range: 0 to 63 \n */ rlUInt8_t tx1PhaseShift; /** * @brief TX2 phase shift definition \n [b1:0] reserved (set it to 0b00) \n [b7:2] TX2 phase shift value \n 1 LSB = 360/2^6 = 5.625 degrees\n Valid range: 0 to 63 \n */ rlUInt8_t tx2PhaseShift; /** * @brief Reserved for Future use */ rlUInt8_t reserved; }rlRfPhaseShiftCfg_t; /*! \brief * Radar RF PA loopback configuration */ typedef struct rlRfPALoopbackCfg { /** * @brief value is a 100MHz divider which sets the loopback frequency \n For e.g. for a 1 MHz frequency, set this to 10 \n For a 2 MHz frequency, set this to 50 \n @note : To ensure no leakage of signal power, user has to ensure that \n 100MHz/LOOPBACK_FREQ is an integer multiple of bin width For e.g. if user \n choses 25Msps sampling rate and 2048 samples/chirp, then \n LOOPBACK_FREQ of 64 (=1.5625MHz) will ensure no leakage \n */ rlUInt16_t paLoopbackFreq; /** * @brief Enable/Disable PA loopback \n 1: PA loopback Enable, 0: PA loopback Disable \n */ rlUInt8_t paLoopbackEn; /** * @brief Reserved for Future use */ rlUInt8_t reserved; }rlRfPALoopbackCfg_t; /*! \brief * Radar RF Phase shift loopback configuration */ typedef struct rlRfPSLoopbackCfg { /** * @brief Loop back frequency in kHz, 1 LSB = 1kHz */ rlUInt16_t psLoopbackFreq; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Enable/Disable PA loopback \n 1: PS loopback Enable, 0: PS loopback Disable \n */ rlUInt8_t psLoopbackEn; /** * @brief Tx used for loopback \n * [b0] 1: Tx0 is used for loopback \n * [b1] 1: Tx1 is used for loopback \n * [b7:2] : reserved \n */ rlUInt8_t psLoopbackTxId; /** * @brief PGA gain value \n * 0 : PGA is OFF \n * 1 : -22 dB \n * 2 : -16 dB \n * 3 : -15 dB \n * 4 : -14 dB \n * 5 : -13 dB \n * 6 : -12 dB \n * 7 : -11 dB \n * 8 : -10 dB \n * 9 : -9 dB \n * 10: -8 dB \n * 11: -7 dB \n * 12: -6 dB \n * 13: -5 dB \n * 14: -4 dB \n * 15: -3 dB \n * 16: -2 dB \n * 17: -1 dB \n * 18: 0 dB \n * 19: 1 dB \n * 20: 2 dB \n * 21: 3 dB \n * 22: 4 dB \n * 23: 5 dB \n * 24: 6 dB \n * 25: 7 dB \n * 26: 8 dB \n * 27: 9 dB \n * 255-28:RESERVED \n */ rlUInt8_t pgaGainIndex; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; }rlRfPSLoopbackCfg_t; /*! \brief * Radar RF IF loopback configuration. */ typedef struct rlRfIFLoopbackCfg { /** * @brief IF loopback frequency value \n * 0: 180 kHz \n * 1 : 240 kHz \n * 2 : 360 kiHz \n * 3 : 720 kHz \n * 4 : 1 MHz \n * 5 : 2 MHz \n * 6 : 2.5 MHz \n * 7 : 3 MHz \n * 8 : 4.017857 MHz \n * 9 : 5 MHz \n * 10 : 6 MHz \n * 11: 8.035714 MHz \n * 12: 9 MHz \n * 13: 10 MHz \n * 65535-14:RESERVED \n */ rlUInt16_t ifLoopbackFreq; /** * @brief Enable/Disable IF loopback \n * [b7:0] 1: IF loopback Enable, 0: IF loopback Disable \n */ rlUInt8_t ifLoopbackEn; /** * @brief Reserved for Future use */ rlUInt8_t reserved; }rlRfIFLoopbackCfg_t; /*! \brief * Array of coefficients for the RF programmable filter */ typedef struct rlRfProgFiltCoeff { /** * @brief The array of coefficients for the programmable filter, across all profiles, to be stored in the coefficient RAM. Each tap is a 16-bit signed number. The exact set of taps to be used for a given profile can be specified through rlRfProgFiltConf. \n For each profile Maximum of 26 taps can be configured. If multiple profiles are used, all the filter taps across profiles are to be provided in one shot. \n There is a HW constraint that each profile's filter taps should start at an even address. \n For e.g If b[i,j] is filter coefficient For Profile i(0,1,2,3) and tap j(0...25), if numProfile = 4 and below is configured in rlRfProgFiltConf \n rlRfProgFiltConf[profileId = 0]. progFiltLen = 26 \n rlRfProgFiltConf[profileId = 1]. progFiltLen = 26, \n rlRfProgFiltConf[profileId = 2]. progFiltLen = 26, \n rlRfProgFiltConf[profileId = 3]. progFiltLen = 26, \n rlRfProgFiltConf[profileId = 0]. coeffStartIdx = 0 \n rlRfProgFiltConf[profileId = 1]. coeffStartIdx = 26 \n rlRfProgFiltConf[profileId = 2]. coeffStartIdx = 52 \n rlRfProgFiltConf[profileId = 3]. coeffStartIdx = 78 \n one need to define this array as following:\n coeffArray[0:103] = b[0,0], b[0,1]....b[0,25],b[1,0],b[1,1].... b[1,25],b[2,0],b[2,1]....b[2,25],b[3,0],b[3,1]....b[3,25]\n if numProfile = 1 and below is configured in rlRfProgFiltConf \n rlRfProgFiltConf[profileId = 0]. coeffStartIdx = 0 \n rlRfProgFiltConf[profileId = 0]. progFiltLen = 10, \n then one need to define this array as following: \n coeffArray[0:103] = b[0,0], b[0,1]....b[0,9],0,0,0,.....0 \n if numProfile = 2 and below is configured in rlRfProgFiltConf \n rlRfProgFiltConf[profileId = 0]. progFiltLen = 10, \n rlRfProgFiltConf[profileId = 1]. progFiltLen = 20, \n rlRfProgFiltConf[profileId = 1]. coeffStartIdx = 10 \n then one need to define this array as following: \n coeffArray[0:103] = b[0,0], b[0,1]....b[0,9], b[1,0],b[1,1]....b[1,29],0,0,0...0 \n @note : All the filter taps across profiles are to be provided in one shot. \n There is a HW constraint that each profile’s filter taps should start \n at four 32-bit word aligned address (i.e., the coefficients corresp- \n onding to any profile should start at array index which is a multiple \n of 8). \n */ rlInt16_t coeffArray[104]; }rlRfProgFiltCoeff_t; /*! \brief * Radar RF programmable filter configuration */ typedef struct rlRfProgFiltConf { /** * @brief Profile Index for which this configuration applies. */ rlUInt8_t profileId; /** * @brief The index of the first coefficient of the programmable filter taps corresponding to this profile in the coefficient RAM programmed using rlRfProgFiltCoeff @note 1: This has to be an even number. For odd-length filters, a 0 (zero) tap needs to be appended at the end to make the length even. This is a HW constraint. @note 2: The profile’s filter tap start index shall be 8 tap aligned (four 32-bit word aligned address). */ rlUInt8_t coeffStartIdx; /** * @brief The length (number of taps) of the filter corresponding to this profile. Together with the previous field, this determines the set of coefficients picked up from the coefficient RAM to form the filter taps for this profile. @note : This has to be an even number. For odd-length filters, a 0 (zero) tap needs to be appended at the end to make the length even. This is a HW constraint. */ rlUInt8_t progFiltLen; /** * @brief Determines the magnitude of the frequency shift do be done before filtering using the real-coefficient programmable filter. 1 LSB = 0.01*Fs shift, where Fs is the output sampling rate, specified as rlProfileCfg_t.digOutSampleRate @note : Applicable only on the Complex output mode */ rlUInt8_t progFiltFreqShift; }rlRfProgFiltConf_t; /*! \brief * Radar RF Miscconfiguration */ typedef struct rlRfMiscConf { /** * @brief b0 PERCHIRP_PHASESHIFTER_EN \n * 0 Per chirp phase shifter is disabled \n * 1 Per chirp phase shifter is enabled \n * This control is applicable only in devices which support phase shifter. \n * For other devices, this is a RESERVED bit and should be set to 0. */ rlUInt32_t miscCtl; /** * @brief Reserved for Future use */ rlUInt32_t reserved; }rlRfMiscConf_t; /*! \brief * Radar RF Calibration monitoring time unit configuration */ typedef struct rlRfCalMonTimeUntConf { /** * @brief Defines the basic time unit, in terms of which calibration and/or monitoring \n periodicities are to be defined. \n If any monitoring functions are desired and enabled, the monitoring infrastructure automatically inherits this time unit as the period over which the various monitors are cyclically executed; so this should be set to the desired FTTI. \n For calibrations, a separate rlRunTimeCalibConf.calibPeriodicity can be specified, as a multiple of this time unit, in rlRfRunTimeCalibConfig. \n 1 LSB = Duration of one frame. \n @note : Even though calibrations many not be desired every time unit, every time unit shall be made long enough to include active chirping time, time required for all enabled calibrations and monitoring functions. Default value in device: 100 \n Valid range : 40ms to 250ms (Derive actual count value from programmed frame \n period) \n */ rlUInt16_t calibMonTimeUnit; /** * @brief Defines the number of cascaded devices. For non-cascade systems (single-chip), * use the default value of 1 */ rlUInt8_t numOfCascadeDev; /** * @brief Applicable only only in cascaded mode, default value = 0 */ rlUInt8_t devId; /** * @brief Reserved for Future use */ rlUInt32_t reserved; }rlRfCalMonTimeUntConf_t; /*! \brief * Radar RF Calibration monitoring Frequency Limit configuration */ typedef struct rlRfCalMonFreqLimitConf { /** * @brief The sensor's lower frequency limit for calibrations and monitoring is encoded \n * in 2 bytes (16 bit unsigned number) \n * 1 LSB = 100 MHz \n * For 77GHz devices(76GHz to 81GHz) \n * Valid range: 760 to 810 * Default value : 760 (If API is not issued) * For 60GHz devices(57GHz to 64GHz) \n * Valid range: 570 to 640 * Default value : 570 (If API is not issued) */ rlUInt16_t freqLimitLow; /** * @brief The sensor's higher frequency limit for calibrations and monitoring is encoded \n * in 2 bytes (16 bit unsigned number) \n * 1 LSB = 100 MHz \n * For 77GHz devices(76GHz to 81GHz) \n * Valid range: 760 to 810 * Default value : 810 (If API is not issued) * For 60GHz devices(57GHz to 64GHz) \n * Valid range: 570 to 640 * Default value : 640 (If API is not issued) * @note : FREQ_LIMIT_HIGH should be strictly greater than FREQ_LIMIT_LOW \n */ rlUInt16_t freqLimitHigh; /** * @brief Reserved for Future use */ rlUInt32_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; }rlRfCalMonFreqLimitConf_t; /*! \brief * Radar RF Init Calibration configuration */ typedef struct rlRfInitCalConf { /** * @brief Allowed values = 0x000 or 0xFFF Normally, upon receiving RF INIT message, the \n * radarSS performs all relevant initial calibrations. This step can be disabled \n * by the host by setting this field to 0x00. If disabled, the host needs to send \n * the INJECT CALIB DATA message so that the radarSS can operate using the \n * calibration data thus injected. Each of these calibrations can be selectively \n * disabled by issuing this message before RF INIT message. \n * * Bit Calibration \n * 0 [Reserved] \n * 1 [Reserved] \n * 2 [Reserved] \n * 3 [Reserved] \n * 4 Enable LODIST calibration \n * 5 Enable RX ADC DC offset calibration \n * 6 Enable HPF cutoff calibration \n * 7 Enable LPF cutoff calibration \n * 8 Enable Peak detector calibration \n * 9 Enable TX Power calibration \n * 10 Enable RX gain calibration \n * 11 Enable TX phase calibration (Device dependent feature, please refer data * sheet) \n * 12 Enable RX IQMM calibration \n * 31:13 [Reserved] \n * @note : If calibrations are disabled then it is mandatory to restore the same. \n */ rlUInt32_t calibEnMask; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Reserved for Future use */ rlUInt16_t reserved2; /** * @brief Reserved for Future use */ rlUInt32_t reserved3; }rlRfInitCalConf_t; /*! \brief * Radar RF Run time calibration configuration */ typedef struct rlRunTimeCalibConf { /** * @brief Upon receiving this trigger message, one time calibration of various RF/analog \n * aspects are triggered if the corresponding bits in this field are set to 1. The \n * response is in the form of an asynchronous event sent to the host. The \n * calibrations, if enabled, are performed after the completion of any ongoing \n * calibration cycle, and the calibration results take event from the frame that \n * begins after the asynchronous event response is sent from the BSS. \n * APLL and SYNTH calibrations are done always internally irrespective of bits are \n * enabled or not, the time required for these calibrations must be allocated. \n * Bit: Calibration \n * 0:[Reserved] \n * 1:[Reserved] \n * 2:[Reserved] \n * 3:[Reserved] \n * 4: Enable LODIST calibration \n * 5: [Reserved] \n * 6: [Reserved] \n * 7: [Reserved] \n * 8: Enable PD_CALIBRATION_EN \n * 9: Enable TX Power calibration \n * 10:Enable RX gain calibration \n * 11:[Reserved] \n * 12:[Reserved] \n * 31:13:[Reserved] \n * NOTE: In IWR6843 ES 1.0, only internal calibrations (APLL & SYNTH) and LODIST \n * calibrations are supported. \n */ rlUInt32_t oneTimeCalibEnMask; /** * @brief Automatic periodic triggering of calibrations of various RF/analog aspects. \n It has same bit definition as above \n */ rlUInt32_t periodicCalibEnMask; /** * @brief This field is applicable only for those calibrations which are enabled to be \n * done periodically in the periodicCalibEnMask field. This field indicates the \n * desired periodicity of calibrations. If this field is set to N, the results of \n * the first calibration (based on oneTimeCalibEnMask) are applicable for the first \n * N calibMonTimeUnits. The results of the next calibration are applicable for \n * the next N calibMonTimeUnits, and so on. * Recommendation: Set calibPeriodicity such that frequency of calibrations is \n * greater than or equal to 1 second. 1 LSB = 1 calibMonTimeUnit, as specified \n * in rlRfSetCalMonTimeUnitConfig. If the user does not wish to receive \n * calibration reports when periodic calibrations are not enabled, then the user \n * should set calibPeriodicity to 0. * Default value: 0 * Valid Range: 0 (Disable), 4 to 100 (value 1 is not a valid value, this will cause \n * internal APLL and SYNTH calibrations to stop) */ rlUInt32_t calibPeriodicity; /** * @brief Calibration Report Enable Configuration \n [b0] Enable Calibration Reports Bitmap \n 0 - Disable Calibration Reports \n 1 - Enable Calibration Reports \n [b7:1] Reserved \n @note 1: If calibration reports are enabled, the reports will be sent every 1 second whenever internal calibrations (APLL and SYNTH) are triggered \n and at every CALIBRATION PERIODICITY when the user enabled calibrations are triggered. \n @note 2: If user has not enabled any one time calibrations, but if calibration report is enabled, then after issuing this API, the firmware will \n attempt to run the APLL and SYNTH calibrations and the calibration report will be immediately sent out. \n */ rlUInt8_t reportEn; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief TX Power Calibration Mode [b0] Enable Calibration Reports Bitmap (Not valid for IWR6843 ES1.0) \n 0 - Update TX gain setting from LUT and do a closed loop calibration \n (OLPC + CLPC) \n 1 - Update TX gain settings from LUT only (OLPC only) \n OLPC: Open Loop Power Control. In this mode the TX stage codes are set \n based on a coarse measurement and a LUT generated for every temperature \n and the stage codes are picked from the LUT CLPC: Closed Loop Power \n Control. In this mode the TX stage codes are picked from the coarse LUT \n as generated in OLPC step. Later the TX power is measured and the TX \n stage codes are corrected to achieve the desired TX power accuracy. \n Default value: 0 \n [b7:1] Reserved \n */ rlUInt8_t txPowerCalMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; }rlRunTimeCalibConf_t; /*! \brief * RX gain temperature LUT read */ typedef struct rlRxGainTempLutReadReq { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; } rlRxGainTempLutReadReq_t; /*! \brief * TX gain temperature LUT read */ typedef struct rlTxGainTempLutReadReq { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; } rlTxGainTempLutReadReq_t; /*! \brief * RX gain temperature LUT inject */ typedef struct rlRxGainTempLutData { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Byte0: RX gain code for temperature < -30 deg C \n * Byte1: RX gain code for temperature [-30, -20) deg C \n * Byte2: RX gain code for temperature [-20, -10) deg C \n * Byte3: RX gain code for temperature [-10, 0) deg C \n * Byte4: RX gain code for temperature [0, 10) deg C \n * Byte5: RX gain code for temperature [10, 20) deg C \n * Byte6: RX gain code for temperature [20, 30) deg C \n * Byte7: RX gain code for temperature [30, 40) deg C \n * Byte8: RX gain code for temperature [40, 50) deg C \n * Byte9: RX gain code for temperature [50, 60) deg C \n * Byte10: RX gain code for temperature [60, 70) deg C \n * Byte11: RX gain code for temperature [70, 80) deg C \n * Byte12: RX gain code for temperature [80, 90) deg C \n * Byte13: RX gain code for temperature [90, 100) deg C \n * Byte14: RX gain code for temperature [100, 110) deg C \n * Byte15: RX gain code for temperature [110, 120) deg C \n * Byte16: RX gain code for temperature [120, 130) deg C \n * Byte17: RX gain code for temperature [130, 140) deg C \n * Byte18: RX gain code for temperature >= 140 deg C \n * Byte19: RESERVED. Set it to 0x00 \n * Each byte is encoded as follows \n * Bits Definition\n * [4:0] IF_GAIN_CODE \n * IF gain is IF_GAIN_CODE * 2 - 6 dB \n * Valid values for xWR1xxx devices : 0 to 17 \n * Valid values for xWR6x43 device : \n * For temperatures < 10C, the max IFA gain supported is 12 (24dBm). \n * For temperatures >=10C, the max IFA gain supported is 15 (30dBm). \n * 1 LSB = 2 dB \n * [7:5] RF_GAIN_CODE \n * For xWR1xxx devices: \n * Value RF Gain \n * 0 Maximum RF gain \n * 1 Maximum RF gain -2dB \n * 2 Maximum RF gain -4dB \n * 3 Maximum RF gain -6dB \n * 4 Maximum RF gain -8dB \n * For xWR6843 ES2.0: \n * Value RF Gain \n * 0 Maximum RF gain \n * 1 Maximum RF gain -3.5dB \n * 2 Maximum RF gain -6dB \n */ rlUInt8_t rxGainTempLut[(19U) + 1U]; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; } rlRxGainTempLutData_t; /*! \brief * TX gain temperature LUT inject */ typedef struct rlTxGainTempLutData { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Gain code for Tx0/1/2 \n * Byte0: TX gain code for temperature < -30 deg C \n * Byte1: TX gain code for temperature [-30, -20) deg C \n * Byte2: TX gain code for temperature [-20, -10) deg C \n * Byte3: TX gain code for temperature [-10, 0) deg C \n * Byte4: TX gain code for temperature [0, 10) deg C \n * Byte5: TX gain code for temperature [10, 20) deg C \n * Byte6: TX gain code for temperature [20, 30) deg C \n * Byte7: TX gain code for temperature [30, 40) deg C \n * Byte8: TX gain code for temperature [40, 50) deg C \n * Byte9: TX gain code for temperature [50, 60) deg C \n * Byte10: TX gain code for temperature [60, 70) deg C \n * Byte11: TX gain code for temperature [70, 80) deg C \n * Byte12: TX gain code for temperature [80, 90) deg C \n * Byte13: TX gain code for temperature [90, 100) deg C \n * Byte14: TX gain code for temperature [100, 110) deg C \n * Byte15: TX gain code for temperature [110, 120) deg C \n * Byte16: TX gain code for temperature [120, 130) deg C \n * Byte17: TX gain code for temperature [130, 140) deg C \n * Byte18: TX gain code for temperature >= 140 deg C \n * Byte19: RESERVED. Set it to 0x00 \n * Each byte is encoded as follows \n * Bits Definition \n * [5:0] STG_CODE \n * Higher values for higher gain \n * [7:6] RESERVED \n */ rlUInt8_t txGainTempLut[(3U)][(19U) + 1U]; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; } rlTxGainTempLutData_t; /*! \brief * Tx freq and power limit configuration */ typedef struct rlRfTxFreqPwrLimitMonConf { /** * @ brief The sensor's lower frequency limit for calibrations and monitoring for TX0 is \n encoded in 2 bytes (16 bit unsigned number) \n 1 LSB = 10 MHz \n For 77GHz devices(76GHz to 81GHz) \n Valid range: 7600 to 8100 Default value : 7600 (If API is not issued) For 60GHz devices(57GHz to 64GHz) \n Valid range: 5700 to 6400 Default value : 5700 (If API is not issued) */ rlUInt16_t freqLimitLowTx0; /** * @ brief The sensor's lower frequency limit for calibrations and monitoring for TX1 is \n encoded in 2 bytes (16 bit unsigned number) \n 1 LSB = 10 MHz \n For 77GHz devices(76GHz to 81GHz) \n Valid range: 7600 to 8100 Default value : 7600 (If API is not issued) For 60GHz devices(57GHz to 64GHz) \n Valid range: 5700 to 6400 Default value : 5700 (If API is not issued) */ rlUInt16_t freqLimitLowTx1; /** * @ brief The sensor's lower frequency limit for calibrations and monitoring for TX2 is \n encoded in 2 bytes (16 bit unsigned number) \n 1 LSB = 10 MHz \n For 77GHz devices(76GHz to 81GHz) \n Valid range: 7600 to 8100 Default value : 7600 (If API is not issued) For 60GHz devices(57GHz to 64GHz) \n Valid range: 5700 to 6400 Default value : 5700 (If API is not issued) */ rlUInt16_t freqLimitLowTx2; /** * @brief The sensor's higher frequency limit for calibrations and monitoring for TX0 is \n encoded in 2 bytes (16 bit unsigned number) \n 1 LSB = 10 MHz \n For 77GHz devices(76GHz to 81GHz) \n Valid range: 7600 to 8100 Default value : 8100 (If API is not issued) For 60GHz devices(57GHz to 64GHz) \n Valid range: 5700 to 6400 Default value : 6400 (If API is not issued) @note : FREQ_LIMIT_HIGH_TXn should be strictly greater than FREQ_LIMIT_LOW_TXn \n */ rlUInt16_t freqLimitHighTx0; /** * @brief The sensor's higher frequency limit for calibrations and monitoring for TX1 is \n encoded in 2 bytes (16 bit unsigned number) \n 1 LSB = 10 MHz \n For 77GHz devices(76GHz to 81GHz) \n Valid range: 7600 to 8100 Default value : 8100 (If API is not issued) For 60GHz devices(57GHz to 64GHz) \n Valid range: 5700 to 6400 Default value : 6400 (If API is not issued) @note : FREQ_LIMIT_HIGH_TXn should be strictly greater than FREQ_LIMIT_LOW_TXn \n */ rlUInt16_t freqLimitHighTx1; /** * @brief The sensor's higher frequency limit for calibrations and monitoring for TX2 is \n encoded in 2 bytes (16 bit unsigned number) \n 1 LSB = 10 MHz \n For 77GHz devices(76GHz to 81GHz) \n Valid range: 7600 to 8100 Default value : 8100 (If API is not issued) For 60GHz devices(57GHz to 64GHz) \n Valid range: 5700 to 6400 Default value : 6400 (If API is not issued) @note : FREQ_LIMIT_HIGH_TXn should be strictly greater than FREQ_LIMIT_LOW_TXn \n */ rlUInt16_t freqLimitHighTx2; /** * @brief TX0 output power back off \n 1LSB = 1dB Valid Value: 0, 3, 6, 9 */ rlUInt8_t tx0PwrBackOff; /** * @brief TX1 output power back off \n 1LSB = 1dB Valid Value: 0, 3, 6, 9 */ rlUInt8_t tx1PwrBackOff; /** * @brief TX2 output power back off \n 1LSB = 1dB Valid Value: 0, 3, 6, 9 */ rlUInt8_t tx2PwrBackOff; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Reserved for Future use */ rlUInt16_t reserved2; /** * @brief Reserved for Future use */ rlUInt16_t reserved3; /** * @brief Reserved for Future use */ rlUInt16_t reserved4; }rlRfTxFreqPwrLimitMonConf_t; /*! \brief * Loopback burst set configuration */ typedef struct rlLoopbackBurst { /** * @brief Loopback selection \n * Value Definition \n * 0 No loopback \n * 1 IF loopback \n * 2 PS loopback \n * 3 PA loopback \n * Others RESERVED \n */ rlUInt8_t loopbackSel; /** * @brief Base profile used for loopback chirps \n * Valid values 0 to 3 \n */ rlUInt8_t baseProfileIndx; /** * @brief Indicates the index of the burst in the loopback sub-frame for which \n * this configuration applies \n * Valid values 0 to 15 \n */ rlUInt8_t burstIndx; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Start frequency for loopback \n * For 77GHz devices (76 GHz to 81 GHz): \n * 1 LSB = 3.6e9 / 2^26 Hz = 53.644 Hz \n * Valid range: 0x5471C71B to 0x5A000000 \n * For 60GHz devices (57 GHz to 64 GHz): \n * 1 LSB = 2.7e9 / 2^26 Hz = 40.233 Hz \n * Valid range: Only even numbers from 0x5471C71C to 0x5ED097B4 \n */ rlUInt32_t freqConst; /** * @brief Ramp slope for loopback burst \n * For 77GHz devices (76 GHz to 81 GHz): \n * 1 LSB = (3.6e6 * 900) / 2^26 = 48.279 kHz/uS \n * Valid range: -2072 to 2072 (Max 100MHz/uS) \n * For 60GHz devices (57 GHz to 64 GHz): \n * 1 LSB = (2.7e6 * 900) / 2^26 = 36.21 kHz/uS \n * Valid range: Only even numbers between -6905 and 6905 (Max 250 MHz/uS) \n */ rlInt16_t slopeConst; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Concatenated code for output power backoff for TX0, TX1, TX2\n b7:0 TX0 output power back off \n b15:8 TX1 output power back off \n b23:16 TX2 output power back off \n b31:24 Reserved \n This setting is applicable only in PA loop-back mode. \n */ rlUInt32_t txBackoff; /** * @brief Bit Definition \n * 5:0 Rx gain \n * This field defined RX gain for each profile \n * 1 LSB = 1 dB \n * For xWR1xxx : all even values from 24 to 52 \n * For xWR6x43 : all even values from 30 to 48 \n * 7:6 RF Gain Target \n * For xWR1243/xWR1443/xWR1642/xWR1843: * Value RF gain target * 00 30 dB \n * 01 34 dB \n * 10 RESERVED \n * 11 26 dB \n * For xWR6843 ES 2.0: * Value RF gain target * 00 30 dB \n * 01 33 dB \n * 10 36 dB \n * 11 RESERVED \n * 15:8 Reserved \n */ rlUInt16_t rxGain; /** * @brief Tx enable selection bit mask \n * b0 Enable TX0 \n * 0 Tx0 Disable \n * 1 Tx0 Enable \n * b1 Enable TX1 \n * 0 Tx1 Disable \n * 1 Tx1 Enable \n * b2 Enable TX2 (PS LB not supported for TX2) \n * 0 Tx2 Disable \n * 1 Tx2 Enable \n * This setting is applicable in all loop-back modes. \n */ rlUInt8_t txEn; /** * @brief Reserved for Future use */ rlUInt8_t reserved2; /** * @brief Bit Definition \n * b0 CONST_BPM_VAL_TX0_OFF \n * Value of Binary Phase Shift value for TX0, during idle time \n * b1 CONST_BPM_VAL_TX0_ON \n * Value of Binary Phase Shift value for TX0, during chirp \n * b2 CONST_BPM_VAL_TX1_OFF \n * Value of Binary Phase Shift value for TX1, during idle time \n * b3 CONST_BPM_VAL_TX1_ON \n * Value of Binary Phase Shift value for TX1, during chirp \n * b4 CONST_BPM_VAL_TX2_OFF \n * Value of Binary Phase Shift value for TX2, during idle time \n * b5 CONST_BPM_VAL_TX2_ON \n * Value of Binary Phase Shift value for TX2, during chirp \n * b15:6 RESERVED \n * This setting is applicable only in PA and PS loop-back modes. \n */ rlUInt16_t bpmConfig; /** * @brief Bits Digital corrections \n b0 IQMM correction disable \n 0 - Enable, 1- Disable \n b1 RX Gain and Phase correction disable \n 0 - Enable, 1- Disable \n b15:2 RESERVED \n This setting is applicable in all loop-back modes \n */ rlUInt16_t digCorrDis; /** * @brief Value IF Loopback frequency value \n * 0 180 kHz \n * 1 240 kHz \n * 2 360 kHz \n * 3 720 kHz \n * 4 1 MHz \n * 5 2 MHz \n * 6 2.5 MHz \n * 7 3 MHz \n * 8 4.02 MHz \n * 9 5 MHz \n * 10 6 MHz \n * 11 8.03 MHz \n * 12 9 MHz \n * 13 10 MHz \n * 255-14 RESERVED \n */ rlUInt8_t ifLbFreq; /** * @brief 1 LSB = 10 mV Valid range: 1 to 63 */ rlUInt8_t ifLbMag; /** * @brief Value PGA gain value \n * 0 PGA is OFF \n * 1 -22 dB \n * 2 -16 dB \n * 3 -15 dB \n * 4 -14 dB \n * 5 -13 dB \n * 6 -12 dB \n * 7 -11 dB \n * 8 -10 dB \n * 9 -9 dB \n * 10 -8 dB \n * 11 -7 dB \n * 12 -6 dB \n * 13 -5 dB \n * 14 -4 dB \n * 15 -3 dB \n * 16 -2 dB \n * 17 -1 dB \n * 18 0 dB \n * 19 1 dB \n * 20 2 dB \n * 21 3 dB \n * 22 4 dB \n * 23 5 dB \n * 24 6 dB \n * 25 7 dB \n * 26 8 dB \n * 27 9 dB \n * 255-28 RESERVED \n */ rlUInt8_t ps1PgaIndx; /** * @brief Same as above definition */ rlUInt8_t ps2PgaIndx; /** * @brief Phase shifter loop back frequency in kHz\n 1 LSB = 1 kHz \n Bits Definition \n b15:0 TX0 Loopback Frequency \n b31:16 TX1 Loopback Frequency \n */ rlUInt32_t psLbFreq; /** * @brief Reserved for Future use */ rlUInt32_t reserved3; /** * @brief This value is a 100MHz divider which sets the loopback frequency \n For e.g. for a 1 MHz frequency, set this to 100 \n for a 2 MHz frequency, set this to 50 \n @note : To ensure no leakage of signal power, user has to ensure that 100MHz/LOOPBACK_FREQ is an integer multiple of bin width. \n For e.g. if user choses 25Msps sampling rate and 2048 samples/chirp, then LOOPBACK_FREQ of 64 (=1.5625MHz) will ensure no leakage. */ rlUInt16_t paLbFreq; /** * @brief Reserved for Future use */ rlUInt16_t reserved4[3U]; } rlLoopbackBurst_t; /*! \brief * Chirp row configuration, radarSS stores each chirp config in memory in 3 rows. */ typedef struct rlChirpRow { /** * @brief Nth Chirp config Row 1 Bits Definition 3:0 PROFILE_INDX Valid range 0 to 3 7:4 RESERVED 13:8 FREQ_SLOPE_VAR For 77GHz Devices (76GHz to 81GHz): 1 LSB = 3.6e9*900 /2^26 ~48.279kHz Valid range: 0 to 63 For 60GHz Devices (57GHz to 64GHz): 1 LSB = 2.7e9*900 /2^26 ~36.21kHz Valid range: Only even numbers from 0 to 63 15:14 RESERVED 18:16 TX_ENABLE Bit Definition b0 TX0 Enable b1 TX1 Enable b2 TX2 Enable 23:19 RESERVED 29:24 BPM_CONSTANT_BITS Bit Definition b0 CONST_BPM_VAL_TX0_OFF Value of Binary Phase Shift value for TX0, when during idle time b1 CONST_BPM_VAL_TX0_ON Value of Binary Phase Shift value for TX0, during chirp b2 CONST_BPM_VAL_TX1_OFF For TX1 b3 CONST_BPM_VAL_TX1_ON For TX1 b4 CONST_BPM_VAL_TX2_OFF For TX2 b5 CONST_BPM_VAL_TX2_ON For TX2 31:30 RESERVED */ rlUInt32_t chirpNR1; /** * @brief Nth Chirp config Row 2 Bits Definition b22:0 FREQ_START_VAR For 77GHz Devices (76GHz to 81GHz): 1 LSB = 3.6e9/2^26 ~53.644 Hz Valid range: 0 to 8388607 For 60GHz Devices (57GHz to 64GHz): 1 LSB = 2.7e9 /2^26 ~40.233 Hz Valid range: Only even numbers from 0 to 8388607 b31:23 RESERVED */ rlUInt32_t chirpNR2; /** * @brief Nth Chirp config Row 3 Bits Definition b11:0 IDLE_TIME_VAR 1 LSB = 10 ns Valid range: 0 to 4095 b15:12 RESERVED b27:16 ADC_START_TIME_VAR 1 LSB = 10 ns Valid range: 0 to 4095 b31:28 RESERVED */ rlUInt32_t chirpNR3; } rlChirpRow_t; /*! \brief * Dynamic chirp configuration for 16 chirp configurations. */ typedef struct rlDynChirpCfg { /** * @brief Reserved for Future use Bits Definition b3:0 Reserved b7:4 If user does not wish to reconfigure all 3 chirp rows, then the following \n mode can be used to configure only one row per chirp which enables the \n user to configure 48 chirps in one API, efectively saving on the \n reconfiguration time. If chirpRowSelect[b7:4] is non-zero, then the API \n parameters chirp_xR1, chirp_xR2 and chirp_xR3 for 1 <= x <= 16 in this \n API would mean CHIRP(3x - 2)Ry, CHIRP(3x - 1) Ry and CHIRP(3x)Ry where y \n is as per the below table \n Value Definition \n 0b0000 Enables all 3 chirp rows to be reconfigured \n 0b0001 Enables only chirp row 1 to be reconfigured \n 0b0010 Enables only chirp row 2 to be reconfigured \n 0b0011 Enables only chirp row 3 to be reconfigured \n Others Reserved \n @note : Value(1 - 3) is not applcicable in xWR6843. */ rlUInt8_t chirpRowSelect; /** * @brief Indicates the segment of the chirp RAM that the 16 chirps definitions in this sub \n * block map to any of one segment out of 32 segments of SW chirp RAM. * Valid range 0 to 31. */ rlUInt8_t chirpSegSel; /** * @brief Indicates when the configuration needs to be applied \n * Bit Definition \n * 0 Program the new configuration when rlSetDynChirpEn API is issued \n * 1 Program the new configuration immediately \n * @note : User has to ensure that the chirps which are being reconfigured are * not the ones which are currently in use for chirping */ rlUInt16_t programMode; /** * @brief Chirp row configurations for 16 chirps. */ rlChirpRow_t chirpRow[16U]; } rlDynChirpCfg_t; /*! \brief * Dynamic chirp enable configuration */ typedef struct rlDynChirpEnCfg { /** * @brief Reserved for Future use */ rlUInt32_t reserved; }rlDynChirpEnCfg_t; /*! \brief * Dynamic per chirp phase shifter configuration for each TX */ typedef struct rlChirpPhShiftPerTx { /** * @brief Nth Chirp TX0 phase shift value Bits TX0 phase shift definition b1:0 RESERVED (set it to 0b00) b7:2 TX0 phase shift value 1 LSB = 360/2^6 = 5.625 (degree) Valid range: 0 to 63 */ rlUInt8_t chirpNTx0PhaseShifter; /** * @brief Nth Chirp TX1 phase shift value Bits TX1 phase shift definition b1:0 RESERVED (set it to 0b00) b7:2 TX1 phase shift value 1 LSB = 360/2^6 = 5.625 (degree) Valid range: 0 to 63 */ rlUInt8_t chirpNTx1PhaseShifter; /** * @brief Nth Chirp TX2 phase shift value \n Bits TX2 phase shift definition \n b1:0 RESERVED (set it to 0b00) \n b7:2 TX2 phase shift value 1 LSB = 360/2^6 = 5.625 (degree) Valid range: 0 to 63 */ rlUInt8_t chirpNTx2PhaseShifter; } rlChirpPhShiftPerTx_t; /*! \brief * Dynamic per chirp phase shifter configuration */ typedef struct rlDynPerChirpPhShftCfg { /** * @brief Reserved for Future use */ rlUInt8_t reserved; /** * @brief Indicates the segment of the chirp RAM that the 16 chirps definitions in this sub \n * block map to any of one segment out of 32 segments of SW chirp RAM. \n * Valid range 0 to 31. */ rlUInt8_t chirpSegSel; /** * @brief Tx phase shifter configurations for 16 chirps. @note : User need to take care of data for endianess. */ rlChirpPhShiftPerTx_t phShiftPerTx[16U]; /** * @brief Indicates when the configuration needs to be applied \n * Bit Definition \n * 0 Program the new configuration when rlSetDynChirpEn API is issued \n * 1 Program the new configuration immediately \n * @note : User has to ensure that the chirps which are being reconfigured are * not the ones which are currently in use for chirping */ rlUInt16_t programMode; } rlDynPerChirpPhShftCfg_t; /*! \brief * Get calibration data configuration structure */ typedef struct rlCalDataGetCfg { /** * @brief Reserved for Future use */ rlUInt16_t reserved; /** * @brief Get Calibration Data Chunk Id */ rlUInt16_t chunkId; }rlCalDataGetCfg_t; /*! \brief * Calibration data which application will receive from radarSS and will feed in to the Device * in next power up to avoid calibration. */ typedef struct rlCalDataStore { /** * @brief Number of calibration data chunks Available in device */ rlUInt16_t numOfChunk; /** * @brief Current Calibration Data Chunk Id. Valid range 0-2 */ rlUInt16_t chunkId; /** * @brief Calibration data chunk which was stored in non-volatile memory \n */ rlUInt8_t calData[224U]; } rlCalDataStore_t; /*! \brief * Structure to store all Calibration data chunks which device provides in response of * rlRfCalibDataStore API. Applcation needs to provide same structure to rlRfCalibDataRestore API * to restore calibration data to the device. \n * Accumulative calData for 3 chunks (3 * 224 bytes) looks like as mentioned. \n * For xWR1243/xWR1443/xWR1642/xWR1843 devices: * Field Name Num.of bytes Description \n * calValidStatus 4 This field indicates the status of each calibration (0 – FAIL, * 1 – PASS). If a particular calibration was not enabled, then its * corresponding field should be ignored. \n * Bit Definition (0 – FAIL, 1 – PASS) \n * b0 RESERVED \n * b1 APLL tuning (Ignore while restore) \n * b2 SYNTH VCO1 tuning (Ignore while restore) \n * b3 SYNTH VCO2 tuning (Ignore while restore) \n * b4 LODIST calibration (Ignore while restore) \n * b5 RX ADC DC offset calibration \n * b6 HPF cutoff calibration \n * b7 LPF cutoff calibration \n * b8 Peak detector calibration (optional) \n * b9 TX Power calibration (optional) \n * b10 RX gain calibration \n * b11 TX Phase calibration (Ignore while restore) \n * b12 RX IQMM calibration \n * b31:13 RESERVED * The recommended Validity status bits while restoring * is 0x000014E0, assuming only rxAdcDcCalData, * hpfCalData, lpfCalData, rxRfGainCalData and IQMM * iqmmCalData are stored and restored. \n * calValidStatusCpy 4 Redundant calValidStatus value, this value should match with * calValidStatus. \n * ifStageCalStatus 4 This field indicates the status of IF stage calibration (0 – FAIL, * 1 – PASS). If a particular calibration was not enabled, then its * corresponding field should be ignored. \n * Bit Definition (0 – FAIL, 1 – PASS) \n * b0 HPF1 \n * b1 HPF2 \n * b2 LPF1 \n * b3 LPF2 \n * b31:4 RESERVED \n * This value shall be set to 0xF if HPF and LPF * calibration validity status are PASS. \n * reserved 4 Reserved for Future use \n * calTemperature 2 Temperature at which boot calibration is done. \n * reserved 14 Reserved for Future use \n * rxAdcDcCalibData 16 RX chain ADC DC calibration data \n * hpf1CalData 1 HPF1 calibration data \n * hpf2CalData 1 HPF2 calibration data \n * reserved 2 Reserved for Future use \n * lpf1CalData 24 LPF1 calibration data \n * lpf2CalData 24 LPF2 calibration data \n * rxRfGainCalData 12 RX RF gain calibration data \n * iqmmCalibData 72 RX IQMM calibration data \n * txPowCalData 84 TX Power calibration data \n * powDetCalData 348 Power detector calibration data \n * reserved 56 Reserved for Future use \n * * For xWR6843 device: * Field Name Num.of bytes Description \n * calValidStatus 4 This field indicates the status of each calibration (0 – FAIL, * 1 – PASS). If a particular calibration was not enabled, then its * corresponding field should be ignored. \n * Bit Definition (0 – FAIL, 1 – PASS) \n * b0 RESERVED \n * b1 APLL tuning (Ignore while restore) \n * b2 SYNTH VCO1 tuning (Ignore while restore) \n * b3 SYNTH VCO2 tuning (Ignore while restore) \n * b4 LODIST calibration (Ignore while restore) \n * b5 RX ADC DC offset calibration \n * b6 HPF cutoff calibration \n * b7 LPF cutoff calibration \n * b8 Peak detector calibration (optional) \n * b9 TX Power calibration (optional) \n * b10 RX gain calibration \n * b11 TX Phase calibration (optional) \n * b12 RX IQMM calibration \n * b31:13 RESERVED * The recommended Validity status bits while restoring * is 0x000014E0, assuming only rxAdcDcCalData, * hpfCalData, lpfCalData, rxRfGainCalData and IQMM * iqmmCalData are stored and restored. \n * calValidStatusCpy 4 Redundant calValidStatus value, this value should match with * calValidStatus. \n * reserved 8 Reserved for Future use \n * calTemperature 2 Temperature at which boot calibration is done. \n * reserved 14 Reserved for Future use \n * rxAdcDcCalibData 16 RX chain ADC DC calibration data \n * hpf1CalData 1 HPF1 calibration data \n * hpf2CalData 1 HPF2 calibration data \n * loDistBiasCode 1 LODIST calibration data \n * reserved 1 Reserved for Future use \n * rxRfGainCalData 8 RX RF gain calibration data \n * iqmmCalibData 104 RX IQMM calibration data \n * txPowCalData 122 TX Power calibration data \n * powDetCalData 344 Power detector calibration data \n * reserved 42 Reserved for Future use \n */ typedef struct rlCalibrationData { rlCalDataStore_t calibChunk[(3U)]; }rlCalibrationData_t; /*! \brief * Inter-Rx gain and phase offset configuration */ typedef struct rlInterRxGainPhConf { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief One byte per RX (8-bit signed number) \n Byte Assignment \n 0 RX0 digital gain \n 1 RX1 digital gain \n 2 RX2 digital gain \n 3 RX3 digital gain \n 1 LSB = 0.1 dB \n Valid Range: -120 to 119 \n */ rlInt8_t digRxGain[(4U)]; /** * @brief Two bytes per RX \n Bits Assignment \n b15:0 RX0 digital phase shift \n b31:16 RX1 digital phase shift \n b47:32 RX2 digital phase shift \n b63:48 RX3 digital phase shift \n 1 LSB = 360 degree / 2^16 ~ 0.0055 (degree) \n Valid Range: 0 to 65535 \n NOTE: This field is NOT applicable when ADC_OUT_FMT is 00 (real output) \n */ rlUInt16_t digRxPhShift[(4U)]; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; /** * @brief Reserved for Future use */ rlUInt32_t reserved3; } rlInterRxGainPhConf_t; /*! \brief * BSS Bootup status data structure */ typedef struct rlRfBootStatusCfg { /** * @brief radarSS bootup status Bit definition [1: pass, 0: fail] 0 image CRC validation 1 CPU and VIM self-test status 2 Reserved 3 VIM test 4 STC self-test 5 CR4 STC 6 CRC test 7 Pampgen ECC 8 DFE Parity (RESERVED in xWR6x43 devices) 9 DFE ECC 10 Rampgen Lockstep 11 FRC lockstep 12 DFE PBIST 13 Rampgen lockstep 14 PBIST test 15 WDT test 16 ESM test 17 DFE STC 18 FRC test 19 TCM ECC 20 TCM parity 21 DCC test 22 SOCC test 23 GPADC test 24 FFT test 25 RTI test 26 PCR test 31:27 reserved */ rlUInt32_t bssSysStatus; /** * @brief RF BIST SS power up time \n 1 LSB = 5ns */ rlUInt32_t bssBootUpTime; /** * @brief Reserved for Future use */ rlUInt32_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; }rlRfBootStatusCfg_t; /*! \brief * Inter Chirp block control configuration */ typedef struct rlInterChirpBlkCtrlCfg { /** * @brief Time to wait after ramp end before turning off RX0 and RX2 RF stages. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx02RfTurnOffTime; /** * @brief Time to wait after ramp end before turning off RX1 and RX3 RF stages. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx13RfTurnOffTime; /** * @brief Time to wait after ramp end before turning off RX0 and RX2 baseband stages. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx02BbTurnOffTime; /** * @brief Time to wait after ramp end before turning off RX1 and RX3 baseband stages. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx12BbTurnOffTime; /** * @brief Time before TX Start Time when RX0 and RX2 RF stages are to be put in fast-charge state. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx02RfPreEnTime; /** * @brief Time before TX Start Time when RX1 and RX3 RF stages are to be put in fast-charge state. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx13RfPreEnTime; /** * @brief Time before TX Start Time when RX0 and RX2 baseband stages are to be put in fast-charge state. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx02BbPreEnTime; /** * @brief Time before TX Start Time when RX1 and RX3 baseband stages are to be put in fast-charge state. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx13BbPreEnTime; /** * @brief Time before TX Start Time when RX0 and RX2 RF stages are to be enabled. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx02RfTurnOnTime; /** * @brief Time before TX Start Time when RX1 and RX3 RF stages are to be enabled. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx13RfTurnOnTime; /** * @brief Time before TX Start Time when RX0 and RX2 baseband stages are to be enabled. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx02BbTurnOnTime; /** * @brief Time before TX Start Time when RX1 and RX3 baseband stages are to be enabled. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rx13BbTurnOnTime; /** * @brief Time to wait after ramp end before turning off RX LO chain. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rxLoChainTurnOffTime; /** * @brief Time to wait after ramp end before turning off TX LO chain. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t txLoChainTurnOffTime; /** * @brief Time to wait after ramp end before turning on RX LO chain. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t rxLoChainTurnOnTime; /** * @brief Time to wait after ramp end before turning on TX LO chain. \n 1 LSB = 10 ns \n Valid range: -1024 to 1023 \n */ rlInt16_t txLoChainTurnOnTime; /** * @brief Reserved for Future use */ rlInt32_t reserved0; /** * @brief Reserved for Future use */ rlInt32_t reserved1; } rlInterChirpBlkCtrlCfg_t; /*! \brief * Sub-frame trigger API */ typedef struct rlSubFrameStartCfg { /** * @brief Command for sub-frame trigger \n Value 0 = No effect \n Value 1 = Trigger next sub-frame \n */ rlUInt16_t startCmd; /** * @brief Reserved for future use */ rlUInt16_t reserved; } rlSubFrameStartCfg_t; /*! \brief * Get phase shift calibration data configuration structure */ typedef struct rlPhShiftCalDataGetCfg { /** * @brief Index of the transmitter channel for which the phase shift is desired \n Valid range: 0 to (Number of Tx channels enabled at rlSetChannelConfig) - 1 \n e.g: 0 to 1 (For xWR1642), 0 to 2 (For xWR1843, xWR1443 & xWR1243 & xWR6x43). \n */ rlUInt8_t txIndex; /** * @brief Reserved for future use */ rlUInt8_t reserved0; /** * @brief Reserved for future use */ rlUInt16_t reserved1; }rlPhShiftCalDataGetCfg_t; /*! \brief * Phase shift calibration data which application will receive from radarSS and will feed in to the * Device in next power up to avoid calibration. */ typedef struct rlPhShiftCalibrationStore { /** * @brief Index of the transmitter channel for which the phase shift is desired \n Valid range: 0 to (Number of Tx channels enabled at rlSetChannelConfig) - 1 \n e.g: 0 to 1 (For xWR1642), 0 to 2 (For xWR1843, xWR1443 & xWR1243). \n */ rlUInt8_t txIndex; /** * @brief Set this to 1 after injecting calibration data for all Txs to enable the firmware \n calibration. For example, if we need to inject calibration data for 3 TX channels, \n we would have to issue the RL_RF_STATIC_CONF_SET_MSG with \n RL_RF_PH_SHIFT_CAL_DATA_RD_WR_SB three times, each time with the calibration data \n for one TX channel. We need to ensure that for the first two instances of the API, \n we set the calibApply field to '0'. When issuing the last instance of the API, \n when the radarss has complete calibration data for all 3 TX channels, set the \n calibApply field to '1'. \n */ rlUInt8_t calibApply; /** * @brief Observed phase shift corresponding to each desired phase shift. Index n \n corresponds to desired phase shift of n * 5.625 degree. \n For TX0, for phase shifter setting/index n=0 to 63 corresponding to functional APIs (e.g. Profile Config, Per Chirp Phase Shifter, etc), the calibration data needs to be retrieved from/restored to following byte locations of TX0 phase calibration data save/restore API: \n n Desired phase shift Observed phase shift is injected in the following bytes \n 17 17*5.625 degrees byte[1], byte[0] \n 18 18*5.625 degrees byte[3], byte[2] \n : : : \n : : : \n 62 62*5.625 degrees byte[91], byte[90] \n 63 63*5.625 degrees byte[93], byte[92] \n 0 0*5.625 degrees byte[95], byte[94] \n 1 1*5.625 degrees byte[97], byte[96] \n : : : \n : : : \n 15 15*5.625 degrees byte[125], byte[124] \n 16 16*5.625 degrees byte[127], byte[126] \n For TX1 and TX2, for phase shifter setting/index n=0 to 63 corresponding to functional APIs (e.g. Profile Config, Per Chirp Phase Shifter, etc), the calibration data needs to be retrieved from/restored to following byte locations of TX1 and TX2 phase calibration data save/restore API: \n n Desired phase shift Observed phase shift is injected in the following bytes \n 49 49*5.625 degrees byte[1], byte[0] \n 50 50*5.625 degrees byte[3], byte[2] \n : : : \n : : : \n 62 62*5.625 degrees byte[27], byte[26] \n 63 63*5.625 degrees byte[29], byte[28] \n 0 0*5.625 degrees byte[31], byte[30] \n 1 1*5.625 degrees byte[33], byte[32] \n : : : \n : : : \n 47 47*5.625 degrees byte[125], byte[124] \n 48 48*5.625 degrees byte[127], byte[126] \n 1 LSB = (360 degree)/pow(2,10). \n */ rlUInt8_t observedPhShiftData[128U]; /** * @brief Reserved for future use */ rlUInt16_t reserved; } rlPhShiftCalibrationStore_t; /*! \brief * Structure to store all Phase shifter calibration data chunks which device provides in response of * rlRfPhShiftCalibDataStore API. Applcation needs to provide same structure to * rlRfPhShiftCalibDataRestore API to restore calibration data to the device. */ typedef struct rlPhShiftCalibrationData { rlPhShiftCalibrationStore_t PhShiftcalibChunk[(3U)]; }rlPhShiftCalibrationData_t; /*! \brief * Die ID data structure */ typedef struct rlRfDieIdCfg { /** * @brief Lot number */ rlUInt32_t lotNo; /** * @brief Wafer number */ rlUInt32_t waferNo; /** * @brief X cordinate of the die in the wafer */ rlUInt32_t devX; /** * @brief Y cordinate of the die in the wafer */ rlUInt32_t devY; /** * @brief Reserved for future use */ rlUInt32_t reserved0; /** * @brief Reserved for future use */ rlUInt32_t reserved1; /** * @brief Reserved for future use */ rlUInt32_t reserved2; /** * @brief Reserved for future use */ rlUInt32_t reserved3; }rlRfDieIdCfg_t; /*! \brief * APLL Synthesizer Bandwidth Control */ typedef struct rlRfApllSynthBwControl { /** * @brief Synth ICP trim code \n */ rlUInt8_t synthIcpTrim; /** * @brief Synth RZ trim code \n */ rlUInt8_t synthRzTrim; /** * @brief APLL ICP trim code \n */ rlUInt8_t apllIcpTrim; /** * @brief APLL RZ trim LPF code \n */ rlUInt8_t apllRzTrimLpf; /** * @brief APLL RZ trim VCO code \n */ rlUInt8_t apllRzTrimVco; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved[5U]; }rlRfApllSynthBwControl_t; /** * @defgroup Sensor Sensor * @brief mmwave radar RF/Sensor Configuration Module * * @image html mmwave_frontend.png * * The RF/Sensor Configuration module controls the different HW blocks inside mmWave Front end. * mmWave Front End has below key blocks * -# Chirp sequencer (Radar Timing Engine) - This block is responsible for constructing * the sequence of FMCW chirps or frames and programming the timing engine * -# Rx/Tx Channel - This defines how many Rx and Tx channel needs to be enabled. Also it * defines how to configure the mmWave front end in cascade mode for Imaging Radar * -# Rx Analog Chain - This defines how the received signal is mixed and how different filters * in the chain can be configured * -# ADC and Digital Front End Configuration - This defines how the IF data is digitized and how * it is sampled for further processing in the DSP or Hardware Accelerator. Same ADC data can be * sent over LVDS/CSI2 interface to an extenal processor * The Sensor Control APIs needs to be called by application in below sequence * ## Initial/Static Configuration # * Application should first configure the mmWave Front end or Radar SS with below Static * configurations * - Channel Configuration - \ref rlSetChannelConfig * - ADC output Configuration - \ref rlSetAdcOutConfig * - Low power mode Configuration - \ref rlSetLowPowerModeConfig * * ## Initialization and Calibration # * After initial static configurations, application should initialize RF * and shall wait for calibration complete Asynchornous event * RL_RF_AE_INITCALIBSTATUS_SB * - \ref rlRfInit * * ## FMCW chirp Configuration # * After RF initilization, Application can configure chirps and frame using * below APIs * - Profile Configuration - \ref rlSetProfileConfig * - Chirp Configuraiton - \ref rlSetChirpConfig * - Frame Configuration - \ref rlSetFrameConfig or rlSetAdvFrameConfig * Note about HW SYNC_IN pulse in hardware triggered mode * * a. The SYNC_IN pulse must not arrive before the frame end boundary * b. If frame trigger delay is used with hardware triggered mode, then external SYNC_IN pulse * periodicity should take care of the configured frame trigger delay and frame periodicity. * The external pulse should be issued only after the sum total of frame trigger delay and * frame periodicity. See figure below * @image html mmwave_hwsyncincareabout.png * c. The inter frame blank time should be at least 250 uS(100 uS for frame preparation and 150 * uS for any calibration updates to hardware). Add 150 uS to inter-frame blank time for test * source configuration if test source is enabled. * d.With respect to the SYNC-IN pulse, the actual transmission has 160ns delay and 5ns * uncertainty in single-chip and only a 300 ps uncertainty (due to tight inter-chip * synchronization needed) in multi-chip sensor applications as defined in rlSetChannelConfig. * * ## Frame Trigger # * After All the configuration, Application can use Sensor Start API * to start Frame and shall wait for Frame Ready Asynchronous event * RL_RF_AE_FRAME_TRIGGER_RDY_SB * - \ref rlSensorStart * * ## Below is the list of advance features in mmWave Front end # * ## Advance Frame # * Legacy frame config API \ref rlSetFrameConfig supports looping of the same FMCW frame. * In order to configure multiple FMCW frames with different chirp profiles, user needs * to use \ref rlSetAdvFrameConfig API. Advance Frame consists of one or upto 4 Sub-Frames * Each Sub-Frame consists of multiple bursts. Each burst consists of multiple chirps as * shown in diagram below.\n * To enable Advance Frame, Application needs to follow below * sequence * - Profile Configuration - \ref rlSetProfileConfig * - Chirp Configuraiton - \ref rlSetChirpConfig * - Advance Frame Configuration - \ref rlSetAdvFrameConfig * * @image html adv_frame_seq.png * * ## Dynamic Chirp Configuration # * Using Legacy chirp configuration API \ref rlSetChirpConfig, chirps can't be re-configure * without stopping the ongoing FMCW frame using \ref rlSensorStop API. \n * If user needs to re-configure chirp during the frame, it needs to use Dynamic chirp * config APIs. Once the API is received by mmWave Front end, it would re-configure the * chirps for next FMCW frame. Dynamic Chirps can be defined using below APIs * - Dynamic Chirp Configuration - \ref rlSetDynChirpCfg * - Enable Dynamic Chirps - \ref rlSetDynChirpEn * * Diagram below shows the Dynamic Chirp behaviour. Note that since dynamic chirps are * configured at run time, there is not error checks done on the input data. If input data * is out of range or invalid, device might misbehave. * * @image html dyn_chip_seq.png * * ## Calibration # * TI mmWave Front end includes built-in processor that is programmed by TI to handle RF calibrations and functional safety monitoring. The RF calibrations ensure that the performance of the device is maintained across temperature and process corners -# Some of the calibrations are just temperature and process based look-up-tables, which are used to update the RF/Analog components -# Built-in temperature sensors enable the device to monitor the temperature every few seconds and update the relevant components accordingly * * ## Power Save Modes State Diagram # * xWR6x43 devices support 3 power down states, RF POWER DOWN, APLL POWER DOWN and * APLL/GPADC POWER DOWN. The state transitions allowed are shown in the below figure. * Any invalid state transition command would result in the device returning an error. * * @image html PowerSaveModesStateDiagram.png * * Below is the list of calibrations and corresponding duration in microseconds \n * Boot Time Calibration
Calibration Duration
Calibration Duration for xWR1xxx(us)Duration for xWR6843(us)
APLL330330
Synth VCO25002500
LO DIST1212
ADC DC 600600
HPF cutoff 35003500
LPF cut off 9000200
Peak detector60008000
TX power (assumes 2 TX use-case)60006000
RX gain 23001500
TX phase 3600036000
RX IQMM (Not applcicable for Real ADC mode)2600042000
* Run Time Calibration
Calibration Duration
Calibration Duration(us)Duration for xWR6843 (us)
APLL150150
Synth VCO350350
LO DIST3030
Peak detector500600
TX power (assumes 1 TX, 1 profile CLPC)800800
TX power (assumes 1 TX, 1 profile OLPC)3030
RX gain 3030
Application of calibration to hardware (This needs to be included always) 100100
* * ## Chirp, Burst and Frame timings # * The minimum chirp cycle time, inter-burst time, inter sub-frame/frame time requirements for 1st gen xWR1xxx and xWR6843 devices are documented in this section. * Chirp Cycle Time
Minimum chirp cycle time
Use case Min Chirp cycle time(us) for xWR1xxxMin Chirp cycle time(us) for xWR6843Description
Typical chirps in normal mode of operation1513The normal chirps used in a burst or a frame using legacy chirp configuration API
WDT enable configuration time10NAAdd WDT configure time to minimum chirp cycle time if it is enabled.By default WDT is disabled,it can be enabled using \ref rlRfSetDeviceCfg API
Per chirp phase shifter(PS) configuration time10NAAdd per chirp PS configure time to minimum chirp cycle time if it is enabled. By default per chirp PS is disabled, it can be enabled using AWR_RF_RADAR_MISC_CTL_SB API
Chirps in Continuous framing modeNA20A single chirp used in a burst. Continuous framing mode is a mode in which a single chirp is programmed in a burst using advanced frame configuration API. In this mode it is recommended to set idle time of chirp minimum 10us to save Inter chirp power save override time (Refer below table)
* Minimum Inter Burst Time
Minimum Inter Burst Time
Min inter burst time Time(us) for xWR1xxxTime(us) for xWR6843Description
Typical inter burst time100 (inter burst pwr save default enabled)55The minimum inter burst idle time required in normal bursts with legacy chirps configured in a advanced frame configuration API with inter burst power save disabled.
Inter burst power save timeNA55Add inter burst power save time to minimum inter burst time if it is enabled. By default inter-burst power save is enabled, it can be disabled using \ref rlRfSetDeviceCfg API
Inter chirp power save override time (power save disable)1515Add inter chirp power save override time to minimum inter burst time if chirp idle time < 10us in a burst or can be controlled using \ref rlRfDynamicPowerSave API
Calibration or Monitoring chirp time150145Add calibration or Monitoring chirp time to minimum inter burst time if calibration or monitors intended to be run in inter burst idle time. The calibration and monitoring chirps can run only in inter sub-frame or inter-frame interval if this time is not allocated in inter-burst time. Add calibration or Monitoring duration to minimum inter burst or sub-frame/frame time based on \ref runTimeCalibration and \ref AnalogMonitoringDuration .
Normal chirps (Continuous framing mode)NA10Add Continuous framing mode normal chirp configuration time to minimum inter burst time. Continuous framing mode is a mode in which a single chirp is programmed in a burst using advanced frame configuration API.
* Minimum Inter Sub-frame or Frame Time
Minimum Inter Sub-frame or Frame Time
Min inter subframe/frame timeTime(us) for xWR1xxx and xWR6843Description
Typical inter subframe/frame time300The minimum inter sub-frame/frame idle time required in normal sub-frames with legacy chirps configured in a advanced frame configuration API or in a legacy frame config API. This time includes time required for minimum inter-burst idle time, inter burst power save, inter chirp power save override and single calibration/monitoring chirp time.
Calibration or Monitoring durationTable 12.2 and Table 12.3Add calibration or Monitoring duration to minimum inter sub-frame/frame time
Loop-back burst configuration time300Add Loop-back burst configuration time to minimum inter sub-frame time for loop back sub-frames if it is enabled in advance frame config API
Dynamic legacy chirp configuration time (for 16 chirps)20 for 16 chirps + 500Add dynamic legacy chirp configuration time to minimum inter frame time if dynamic chirp/phase-shifter APIs are issued in runtime
Dynamic profile configuration time (for 1 profile)1200Add dynamic profile configuration time to minimum inter frame time if dynamic profile API is issued in runtime.
Test source config time150 for xWR1xxx devices and 170 for xWR6843 devicesAdd test source configuration time to minimum inter sub-frame time if test source API is issued.
* Typical APLL and Synth BW settings
Typical APLL and Synth BW settings
Synth ICPSynth RtrimAPLL ICPAPLL Rtrim LPF APLL Rtrim VCOVCO1_BWVCO2_BWAPLL_BWEmission Improv 1M PN Degrad at 60G100K PN Improv at 60GMax Slope (MHz/us)
180x260x981.5M1.5M150K2 dB2 dB0 dB250
380x260x980.75M0.75M150K2 dB2 dB0 dB125
180x3F0x981.5M1.5M300K2 dB4 dB5 dB250
180x260x951.5M1.5M150K8 dB1.5 dB0 dB250
380x260x950.75M0.75M150K8 dB1.5 dB0 dB125
180x3F0x951.5M1.5M300K8 dB3.5 dB5 dB250
180x260x961.5M1.5M150K5 dB1 dB0 dB250
380x260x960.75M0.75M150K5 dB1 dB0 dB125
180x3F0x961.5M1.5M300K5 dB3 dB5 dB250
180x260x9181.5M1.5M150K0 dB0 dB0 dB250
380x260x9180.75M0.75M150K0 dB0 dB0 dB125
180x3F0x9181.5M1.5M300K0 dB2 dB5 dB250
* Related Files * - rl_sensor.c * @addtogroup Sensor * @{ */ /****************************************************************************** * FUNCTION DECLARATIONS ****************************************************************************** */ /* RF/Sensor Configuration Functions */ /*Rx and Tx Channel Configuration */ rlReturnVal_t rlSetChannelConfig(rlUInt8_t deviceMap, rlChanCfg_t* data); /*ADC Out Configuration */ rlReturnVal_t rlSetAdcOutConfig(rlUInt8_t deviceMap, rlAdcOutCfg_t* data); /*Low Power Mode */ rlReturnVal_t rlSetLowPowerModeConfig(rlUInt8_t deviceMap, rlLowPowerModeCfg_t* data); /*RF Init */ rlReturnVal_t rlRfInit(rlUInt8_t deviceMap); /*Profile Configuration */ rlReturnVal_t rlGetProfileConfig(rlUInt8_t deviceMap, rlUInt16_t profileId, rlProfileCfg_t* data); rlReturnVal_t rlSetProfileConfig(rlUInt8_t deviceMap, rlUInt16_t cnt, rlProfileCfg_t* data); /*Chirp Configuration */ rlReturnVal_t rlGetChirpConfig(rlUInt8_t deviceMap, rlUInt16_t chirpStartIdx, rlUInt16_t chirpEndIdx, rlChirpCfg_t* data); rlReturnVal_t rlSetChirpConfig(rlUInt8_t deviceMap, rlUInt16_t cnt, rlChirpCfg_t* data); rlReturnVal_t rlSetMultiChirpCfg(rlUInt8_t deviceMap, rlUInt16_t cnt, rlChirpCfg_t **data); /*Frame Configuration */ rlReturnVal_t rlGetFrameConfig(rlUInt8_t deviceMap, rlFrameCfg_t* data); rlReturnVal_t rlSetFrameConfig(rlUInt8_t deviceMap, rlFrameCfg_t* data); /*Sensor Trigger */ rlReturnVal_t rlSensorStart(rlUInt8_t deviceMap); rlReturnVal_t rlSensorStop(rlUInt8_t deviceMap); /*Advance Frame Configuration */ rlReturnVal_t rlGetAdvFrameConfig(rlUInt8_t deviceMap, rlAdvFrameCfg_t* data); rlReturnVal_t rlSetAdvFrameConfig(rlUInt8_t deviceMap, rlAdvFrameCfg_t* data); /*Continous mode Configuration */ rlReturnVal_t rlSetContModeConfig(rlUInt8_t deviceMap, rlContModeCfg_t* data); rlReturnVal_t rlEnableContMode(rlUInt8_t deviceMap, rlContModeEn_t* data); /*BPM Configuration */ rlReturnVal_t rlSetBpmCommonConfig(rlUInt8_t deviceMap, rlBpmCommonCfg_t* data); rlReturnVal_t rlSetBpmChirpConfig(rlUInt8_t deviceMap, rlBpmChirpCfg_t* data); rlReturnVal_t rlSetMultiBpmChirpConfig(rlUInt8_t deviceMap, rlUInt16_t cnt, rlBpmChirpCfg_t** data); /*Test Source Configuration */ rlReturnVal_t rlSetTestSourceConfig(rlUInt8_t deviceMap, rlTestSource_t* data); rlReturnVal_t rlTestSourceEnable(rlUInt8_t deviceMap, rlTestSourceEnable_t* data); /*Get RF Characterization Time and Temperature information */ rlReturnVal_t rlRfGetTemperatureReport(rlUInt8_t deviceMap, rlRfTempData_t* data); /*Get RF Digital Front End Statistics */ rlReturnVal_t rlRfDfeRxStatisticsReport(rlUInt8_t deviceMap, rlDfeStatReport_t* data); /*Dynamic Power save Configuration */ rlReturnVal_t rlRfDynamicPowerSave(rlUInt8_t deviceMap, rlDynPwrSave_t* data); /*RadarSS Device configuration */ rlReturnVal_t rlRfSetDeviceCfg(rlUInt8_t deviceMap, rlRfDevCfg_t* data); /*GPADC Read(From external Input) configuration */ rlReturnVal_t rlSetGpAdcConfig(rlUInt8_t deviceMap, rlGpAdcCfg_t* data); /* LDO bypass Configuration */ rlReturnVal_t rlRfSetLdoBypassConfig(rlUInt8_t deviceMap, rlRfLdoBypassCfg_t* data); /*Per Chirp Phase Shifter Configuration */ rlReturnVal_t rlRfSetPhaseShiftConfig(rlUInt8_t deviceMap, rlUInt16_t cnt, rlRfPhaseShiftCfg_t* data); /* PA loopback Configuration */ rlReturnVal_t rlRfSetPALoopbackConfig(rlUInt8_t deviceMap, rlRfPALoopbackCfg_t* data); /* Phase Shift Loopback Configuration */ rlReturnVal_t rlRfSetPSLoopbackConfig(rlUInt8_t deviceMap, rlRfPSLoopbackCfg_t* data); /* IF loopback Configuration */ rlReturnVal_t rlRfSetIFLoopbackConfig(rlUInt8_t deviceMap, rlRfIFLoopbackCfg_t* data); /* Programmable Filter RAM coefficients */ rlReturnVal_t rlRfSetProgFiltCoeffRam(rlUInt8_t deviceMap, rlRfProgFiltCoeff_t* data); /* programmable Filter Configuration */ rlReturnVal_t rlRfSetProgFiltConfig(rlUInt8_t deviceMap, rlRfProgFiltConf_t* data); /*Radar Misc Configuration */ rlReturnVal_t rlRfSetMiscConfig(rlUInt8_t deviceMap, rlRfMiscConf_t* data); /*Calibration/monitoring Time Unit Configuration */ rlReturnVal_t rlRfSetCalMonTimeUnitConfig(rlUInt8_t deviceMap, rlRfCalMonTimeUntConf_t* data); /*Calibration/monitoring Freq Limit Configuration */ rlReturnVal_t rlRfSetCalMonFreqLimitConfig(rlUInt8_t deviceMap, rlRfCalMonFreqLimitConf_t* data); /*Init time calibration Configuration */ rlReturnVal_t rlRfInitCalibConfig(rlUInt8_t deviceMap, rlRfInitCalConf_t* data); /*Run time calibration Configuration */ rlReturnVal_t rlRfRunTimeCalibConfig(rlUInt8_t deviceMap, rlRunTimeCalibConf_t* data); /*Rx Gain Look up Table (LUT) Update APIs */ rlReturnVal_t rlRxGainTempLutSet(rlUInt8_t deviceMap, rlRxGainTempLutData_t *data); rlReturnVal_t rlRxGainTempLutGet(rlUInt8_t deviceMap, rlRxGainTempLutReadReq_t *inData, rlRxGainTempLutData_t *outData); /*Tx Gain Look up Table (LUT) Update APIs */ rlReturnVal_t rlTxGainTempLutSet(rlUInt8_t deviceMap, rlTxGainTempLutData_t *data); rlReturnVal_t rlTxGainTempLutGet(rlUInt8_t deviceMap, rlTxGainTempLutReadReq_t *inData, rlTxGainTempLutData_t *outData); /*TX freq and power limits monitoring configuration */ rlReturnVal_t rlRfTxFreqPwrLimitConfig(rlUInt8_t deviceMap, rlRfTxFreqPwrLimitMonConf_t* data); /*Looback chirp configuration API */ rlReturnVal_t rlSetLoopBckBurstCfg(rlUInt8_t deviceMap, rlLoopbackBurst_t *data); /*Dynamic chirp configuration API */ rlReturnVal_t rlSetDynChirpCfg(rlUInt8_t deviceMap, rlUInt16_t segCnt, rlDynChirpCfg_t **data); rlReturnVal_t rlSetDynChirpEn(rlUInt8_t deviceMap, rlDynChirpEnCfg_t *data); /*Dynamic per-chirp phase shifter configuration API(AWR1243P) */ rlReturnVal_t rlSetDynPerChirpPhShifterCfg(rlUInt8_t deviceMap, rlUInt16_t segCnt, rlDynPerChirpPhShftCfg_t **data); /*Calibration data store/restore configuration */ rlReturnVal_t rlRfCalibDataStore(rlUInt8_t deviceMap, rlCalibrationData_t *data); rlReturnVal_t rlRfCalibDataRestore(rlUInt8_t deviceMap, rlCalibrationData_t *data); /*Update Inter Rx Gain/Phase offsets for Inter-RX mismatch compensation */ rlReturnVal_t rlRfInterRxGainPhaseConfig(rlUInt8_t deviceMap, rlInterRxGainPhConf_t* data); /*Get RadarSS/BSS bootup(Boot time monitoring tests) status */ rlReturnVal_t rlGetRfBootupStatus(rlUInt8_t deviceMap, rlRfBootStatusCfg_t *data); /*Update Inter Rx Gain/Phase offsets for Inter-RX mismatch compensation */ rlReturnVal_t rlSetInterChirpBlkCtrl(rlUInt8_t deviceMap, rlInterChirpBlkCtrlCfg_t *data); /*Sub frame trigger API */ rlReturnVal_t rlSetSubFrameStart(rlUInt8_t deviceMap, rlSubFrameStartCfg_t *data); /*Phase shifter calibration data store/restore configuration*/ rlReturnVal_t rlRfPhShiftCalibDataStore(rlUInt8_t deviceMap, rlPhShiftCalibrationData_t *data); rlReturnVal_t rlRfPhShiftCalibDataRestore(rlUInt8_t deviceMap, rlPhShiftCalibrationData_t *data); /*Get device die ID status*/ rlReturnVal_t rlGetRfDieId(rlUInt8_t deviceMap, rlRfDieIdCfg_t *data); /* Get RadarSS CPU/ESM fault status functions */ rlReturnVal_t rlRfGetEsmFault(rlUInt8_t deviceMap, rlBssEsmFault_t *data); rlReturnVal_t rlRfGetCpuFault(rlUInt8_t deviceMap, rlCpuFault_t *data); /* APLL and Synthesizer Bandwidth control API */ rlReturnVal_t rlRfApllSynthBwCtlConfig(rlUInt8_t deviceMap, rlRfApllSynthBwControl_t* data); /*Power Saving Mode configuration */ rlReturnVal_t rlSetPowerSaveModeConfig(rlUInt8_t deviceMap, rlPowerSaveModeCfg_t* data); /*! Close the Doxygen group. @} */ /* * END OF RL_SENSOR_H FILE */ /**************************************************************************************** * FileName : rl_monitoring.h * * Description : This file defines the functions required for Monitoring. * **************************************************************************************** * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /**************************************************************************************** * FILE INCLUSION PROTECTION **************************************************************************************** */ /****************************************************************************** * INCLUDE FILES ****************************************************************************** */ /*! \brief * Supported maximum number of RF frequencies for monitoring */ /*! \brief * Max Number of (primary + secondary) slices to monitor */ /****************************************************************************** * GLOBAL VARIABLES/DATA-TYPES DEFINITIONS ****************************************************************************** */ /*! \brief * Digital monitoring configuration */ typedef struct rlMonDigEnables { /** * @brief Bit: Dig Monitoring \n 0 Reserved \n 1 CR4 and VIM lockstep test of diagnostic \n 2 Reserved \n 3 VIM test (Not supported in 1st Gen devices, refer latest release note) \n 4 Reserved \n 5 Reserved \n 6 CRC test of diagnostic \n 7 RAMPGEN memory ECC test of diagnostic (Not supported in 1st Gen devices, refer latest release note) \n 8 DFE Parity test of diagnostic (RESERVED in xWR6x43 devices) \n 9 DFE memory ECC test of diagnostic \n 10 RAMPGEN lockstep test of diagnostic \n 11 FRC lockstep test of diagnostic \n 12 Reserved \n 13 Reserved \n 14 Reserved \n 15 Reserved \n 16 ESM test of diagnostic \n 17 DFE STC \n 18 Reserved \n 19 ATCM, BTCM ECC test of diagnostic \n 20 ATCM, BTCM parity test of diagnostic \n 21 Reserved \n 22 Reserved \n 23 Reserved \n 24 FFT test of diagnostic \n 25 RTI test of diagnostic \n 31:26 RESERVED \n */ rlUInt32_t enMask; /** * @brief Value Definition \n 0 Production mode. Latent faults are tested and any failures are reported \n 1 Characterization mode. Faults are injected and failures are reported which allows testing of the failure reporting path \n */ rlUInt8_t testMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlMonDigEnables_t; /*! \brief * Digital monitoring latent fault reporting configuration */ typedef struct rlDigMonPeriodicConf { /** * @brief Value Definition \n 0 Report is sent every monitoring period \n 1 Report is sent only on a failure \n 2 RESERVED \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Bit Monitoring \n 0 PERIODIC_CONFG_REGISTER_READ_EN \n 1 RESERVED \n 2 DFE_STC_EN \n 3 FRAME_TIMING_MONITORING_EN \n 31:4 RESERVED \n */ rlUInt32_t periodicEnableMask; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlDigMonPeriodicConf_t; /*! \brief * Analog monitoring configuration */ typedef struct rlMonAnaEnables { /** * @brief Bit Analog monitoring control \n 0 TEMPERATURE_MONITOR_EN \n 1 RX_GAIN_PHASE_MONITOR_EN \n 2 RX_NOISE_MONITOR_EN \n 3 RX_IFSTAGE_MONITOR_EN \n 4 TX0_POWER_MONITOR_EN \n 5 TX1_POWER_MONITOR_EN \n 6 TX2_POWER_MONITOR_EN \n 7 TX0_BALLBREAK_MONITOR_EN \n 8 TX1_BALLBREAK_MONITOR_EN \n 9 TX2_BALLBREAK_MONITOR_EN \n 10 TX_GAIN_PHASE_MONITOR_EN \n 11 TX0_BPM_MONITOR_EN \n 12 TX1_BPM_MONITOR_EN \n 13 TX2_BPM_MONITOR_EN \n 14 SYNTH_FREQ_MONITOR_LIVE_EN \n 15 EXTERNAL_ANALOG_SIGNALS_MONITOR_EN \n 16 INTERNAL_TX0_SIGNALS_MONITOR_EN \n 17 INTERNAL_TX1_SIGNALS_MONITOR_EN \n 18 INTERNAL_TX2_SIGNALS_MONITOR_EN \n 19 INTERNAL_RX_SIGNALS_MONITOR_EN \n 20 INTERNAL_PMCLKLO_SIGNALS_MONITOR_EN \n 21 INTERNAL_GPADC_SIGNALS_MONITOR_EN \n 22 PLL_CONTROL_VOLTAGE_MONITOR_EN \n 23 DCC_CLOCK_FREQ_MONITOR_EN \n 24 RX_IF_SATURATION_MONITOR_EN \n 25 RX_SIG_IMG_BAND_MONITORING_EN \n 26 RX_MIXER_INPUT_POWER_MONITOR \n 27 RESERVED \n 28 SYNTH_FREQ_MONITOR_NON_LIVE_EN \n 31:29 RESERVED \n */ rlUInt32_t enMask; /** * @brief LDO short circuit monitoring enable. There are no reports for these monitors. \n If there is any fault, the asyncevent RL_RF_AE_ANALOG_FAULT_SB will be sent. \n Bit Description \n b0 APLL LDO short circuit monitoring \n 0 - disable, 1 - enable \n b1 SYNTH VCO LDO short circuit monitoring \n 0 - disable, 1 - enable \n b2 PA LDO short circuit monitoring \n 0 - disable, 1 - enable \n b31:3 RESERVED \n @note : This feature is not supported in DFP 1.x (1st generation devices). Please refer latest DFP release note for more details. \n */ rlUInt32_t ldoScEn; } rlMonAnaEnables_t; /*! \brief * Temperature sensor monitoring configuration */ typedef struct rlTempMonConf { /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief The temperatures read from near the sensors near the RF analog modules are compared against a minimum threshold. The comparison result is part of the monitoring report message (Error bit is set if any measurement is outside this (minimum, maximum) range).\n 1 LSB = 1 degree Celsius, signed number \n Valid range: -99 degree Celsius to 199 degree Celsius \n */ rlInt16_t anaTempThreshMin; /** * @brief The temperatures read from near the sensors near the RF analog modules are compared against a maximum threshold. The comparison result is part of the monitoring report message (Error bit is set if any measurement is outside this (minimum, maximum) range). \n 1 LSB = 1 degree Celsius, signed number \n Valid range: -99 degree Celsius to 199 degree Celsius \n */ rlInt16_t anaTempThreshMax; /** * @brief The temperatures read from near the sensor near the digital module are compared against a minimum threshold. The comparison result is part of the monitoring report message (Error bit is set if any measurement is outside this (minimum, maximum) range). \n 1 LSB = 1 degree Celsius, signed number \n Valid range: -99 degree Celsius to 199 degree Celsius \n In xWR6x43, value 0 disables the monitor threshold check (together with DIG_TEMP_THRESH_MAX=0) \n */ rlInt16_t digTempThreshMin; /** * @brief The temperatures read from near the sensor near the digital module are compared against a maximum threshold. The comparison result is part of the monitoring report message (Error bit is set if any measurement is outside this (minimum, maximum) range). \n 1 LSB = 1 degree Celsius, signed number \n Valid range: -99 degree Celsius to 199 degree Celsius \n In xWR6x43, value 0 disables the monitor threshold check (together with DIG_TEMP_THRESH_MIN=0) \n */ rlInt16_t digTempThreshMax; /** * @brief The maximum difference across temperatures read from all the enabled sensors is compared against this threshold.The comparison result is part of the monitoring report message(Error bit is set if the measured difference exceeds this field). \n 1 LSB = 1o Celsius, unsigned number \n Valid range: 0 degree Celsius to 100 degree Celsius \n In xWR6x43, digital temperature sensors can be excluded from this check by setting DIG_TEMP_THRESH_MIN and DIG_TEMP_THRESH_MAX to value 0. \n */ rlUInt16_t tempDiffThresh; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlTempMonConf_t; /*! \brief * RX gain and phase monitoring configuration */ typedef struct rlRxGainPhaseMonConf { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief This field indicates the RF frequencies inside the profile's RF band at which to measure the required parameters. When each bit in this field is set, the measurement at the corresponding RF frequency is enabled w.r.t. the profile's RF band. \n Bit number RF frequency RF name \n 0 Lowest RF frequency RF1 \n in profile's sweep bandwidth \n 1 Center RF frequency in profile's RF2 \n sweep bandwidth \n 2 Highest RF frequency in RF3 \n profile's sweep bandwidth \n The RF name column is mentioned here to set the convention for the purpose of reporting and describing many monitoring packets. \n */ rlUInt8_t rfFreqBitMask; /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n @note : It is recommended not to use quiet mode, as Host has to compute actual RX gain and need to monitor Noise power to detect presence of interference. \n 2 Report is sent every monitoring period with threshold check \n */ rlUInt8_t reportMode; /** * @brief Value Definition \n 0 TX0 is used for generating loopback signal for RX gain measurement \n 1 TX1 is used for generating loopback signal for RX gain measurement. \n */ rlUInt8_t txSel; /** * @brief The magnitude of difference between the programmed and measured RX gain for each \n enabled channel at each enabled RF frequency, is compared against this \n threshold. The comparison result is part of the monitoring report message \n (Error bit is set if any measurement is above this threshold). Before the \n comparison, the measured gains for each RF and RX are adjusted by subtracting \n the offset given in the RX_GAIN_MISMATCH_OFFSET_VALUE field \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlUInt16_t rxGainAbsThresh; /** * @brief The magnitude of difference between measured RX gains across the enabled channels \n at each enabled RF frequency is compared against this threshold. The comparison \n result is part of the monitoring report message (Error bit is set if the \n measurement is above this threshold). Before the comparison, the measured gains \n for each RF and RX are adjusted by subtracting the offset given in the \n RX_GAIN_MISMATCH_OFFSET_VALUE field. \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlUInt16_t rxGainMismatchErrThresh; /** * @brief The magnitude of measured RX gain flatness error, for each enabled channel, is \n compared against this threshold. The flatness error for a channel is defined as \n the peak to peak variation across RF frequencies. The comparison result is part \n of the monitoring report message (Error bit is set if any measurement is above \n this threshold). Before the comparison, the measured gains for each RF and RX \n are adjusted by subtracting the offset given in the \n RX_GAIN_MISMATCH_OFFSET_VALUE field. \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n This flatness check is applicable only if multiple RF Frequencies are enabled, \n i.e., RF_FREQ_BITMASK has bit numbers 0,1,2 set \n */ rlUInt16_t rxGainFlatnessErrThresh; /** * @brief The magnitude of measured RX phase mismatch across the enabled channels at each \n enabled RF frequency is compared against this threshold. The comparison result \n is part of the monitoring report message (Error bit is set if any measurement \n is above this threshold). Before the comparison, the measured phases for each \n RF and RX are adjusted by subtracting the offset given in the \n RX_PHASE_MISMATCH_OFFSET_VALUE field. \n 1 LSB = 360(degree) / 2^16 . \n Valid range: corresponding to 0 degree to 359.9 degree. \n */ rlUInt16_t rxGainPhaseMismatchErrThresh; /** * @brief The offsets to be subtracted from the measured RX gain for each RX and RF before \n the relevant threshold comparisons are given here. \n Byte numbers corresponding to different RX and RF, in this field are \n here: \n RF1 RF2 RF3 \n RX0 [1:0] [9:8] [17:16] \n RX1 [3:2] [11:10] [19:18] \n RX2 [5:4] [13:12] [21:20] \n RX3 [7:6] [15:14] [23:22] \n 1 LSB = 0.1 dB, signed number \n Only the entries of enabled RF Frequencies and enabled RX channels are \n considered. \n */ rlInt16_t rxGainMismatchOffsetVal[(4U)][(3U)]; /** ** @brief The offsets to be subtracted from the measured RX phase for each RX and RF \n before the relevant threshold comparisons are given here. Byte numbers \n corresponding to different RX and RF, in this field are here: \n RF1 RF2 RF3 \n RX0 [1:0] [9:8] [17:16] \n RX1 [3:2] [11:10] [19:18] \n RX2 [5:4] [13:12] [21:20] \n RX3 [7:6] [15:14] [23:22] \n 1 LSB = 360(degree) / 2^16 , unsigned number \n Only the entries of enabled RF Frequencies and enabled RX channels are \n considered. \n */ rlUInt16_t rxGainPhaseMismatchOffsetVal[(4U)][(3U)]; /** * @brief Reserved for Future use */ rlUInt32_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlRxGainPhaseMonConf_t; /*! \brief * RX noise monitoring configuration */ typedef struct rlRxNoiseMonConf { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief This field indicates the exact RF frequencies inside the profile's RF band at \n which to measure the required parameters. When each bit in this field is set, \n the measurement at the corresponding RF frequency is enabled w.r.t. the \n profile's RF band. \n Bit number RF frequency RF name \n 0 Lowest RF frequency in RF1 \n profile's sweep bandwidth \n 1 Center RF frequency in RF2 \n profile's sweep bandwidth \n 2 Highest RF frequency in RF3 \n profile's sweep bandwidth \n The RF name column is mentioned here to set the convention for the purpose of \n reporting and describing many monitoring packets. \n */ rlUInt8_t rfFreqBitMask; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief The measured RX input referred noise figure at the enabled RF frequencies, for \n all channels, is compared against this threshold. The comparison result is part \n of the monitoring report message (Error bit is set if any measurement is above \n this threshold). \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlUInt16_t noiseThresh; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlRxNoiseMonConf_t; /*! \brief * RX IF stage monitoring configuration */ typedef struct rlRxIfStageMonConf { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief The absolute values of RX IF HPF cutoff percentage frequency errors are \n compared against the corresponding thresholds given in this field. The \n comparison results are part of the monitoring report message (Error bit is set \n if the absolute value of the errors exceeds respective thresholds). \n 1 LSB = 1%, unsigned number \n Valid range: 1% to 128% \n */ rlUInt16_t hpfCutoffErrThresh; /** * @brief The absolute values of RX IF LPF cutoff percentage frequency errors are compared \n against the corresponding thresholds given in this field. The comparison \n results are part of the monitoring report message (Error bit is set if the \n absolute value of the errors exceeds respective thresholds). \n 1 LSB = 1%, unsigned number \n Valid range: 1% to 128% \n @note 1: This feature is not supported in AWR1243, xWR1443, xWR1642 and \n xWR1843 devices. \n @note 2: This feature is not supported in this release. Please refer latest \n DFP release note for more details. \n */ rlUInt16_t lpfCutoffErrThresh; /** * @brief The absolute deviation of RX IFA Gain from the expected gain for each enabled RX \n channel is compared against the thresholds given in this field. The comparison \n result is part of the monitoring report message (Error bit is set if the \n absolute \n value of the errors exceeds respective thresholds). \n 1 LSB = 0.1dB, unsigned number \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlUInt16_t ifaGainErrThresh; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlRxIfStageMonConf_t; /*! \brief * TX power monitoring configuration */ typedef struct rlTxPowMonConf { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief This field indicates the exact RF frequencies inside the profile's RF band at \n which to measure the required parameters. When each bit in this field is set, \n the measurement at the corresponding RF frequency is enabled w.r.t. the \n profile's RF band. \n Bit number RF frequency RF \n 0 Lowest RF frequency in profile's RF1 \n sweep bandwidth \n 1 Center RF frequency in profile's RF2 \n sweep bandwidth \n 2 Highest RF frequency in profile's RF3 \n sweep bandwidth \n The RF Name column is mentioned here to set the convention for the purpose \n of reporting and describing many monitoring packets. \n */ rlUInt8_t rfFreqBitMask; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /*!< Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent everymonitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief The magnitude of difference between the programmed and measured TX power for \n each enabled channel at each enabled RF frequency, is compared against this \n threshold. The comparison result is part of the monitoring report message(Error \n bit is set if any measurement is above this threshold). \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlUInt16_t txPowAbsErrThresh; /** * @brief The magnitude of measured TX power flatness error, for each enabled channel, is \n compared against this threshold. The flatness error for a channel is defined as \n the peak to peak variation across RF frequencies. The comparison result is part \n of the monitoring report message(Error bit is set if any measurement is above \n this threshold). \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n This flatness check is applicable only if multiple RF Frequencies are enabled. \n */ rlUInt16_t txPowFlatnessErrThresh; /** * @brief Reserved for Future use */ rlUInt16_t reserved2; /** * @brief Reserved for Future use */ rlUInt32_t reserved3; } rlTxPowMonConf_t; /*! \brief * TX power monitoring configuration */ typedef struct rlAllTxPowMonConf { /** * @brief Power Monitoring Configuration for Tx0 */ rlTxPowMonConf_t *tx0PowrMonCfg; /** * @brief Power Monitoring Configuration for Tx1 */ rlTxPowMonConf_t *tx1PowrMonCfg; /** * @brief Power Monitoring Configuration for Tx2 */ rlTxPowMonConf_t *tx2PowrMonCfg; }rlAllTxPowMonConf_t; /*! \brief * TX ballbreak monitoring configuration */ typedef struct rlTxBallbreakMonConf { /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /*!< The TX reflection coefficient's magnitude for each enabled channel is compared against \n the threshold given here. The comparison result is part of the monitoring report \n message (Error bit is set if the measurement is higher than or equal to this \n threshold, with the units of both quantities being the same). \n 1 LSB = 0.1 dB, signed number \n Valid range: -32767 to +32767 (-3276dB to +3276dB) \n */ rlInt16_t txReflCoeffMagThresh; /** * @brief For xWR1xxx devices: \n This field is reserved. Set to 0x0. \n For xWR6x43 devices: \n Start frequency of the monitoring chirp. \n For 60GHz Devices (57GHz to 63.8Ghz): 1 LSB = 2.7e9/2^26 = 40.233 Hz \n Valid range: Only even numbers from 0x5471C71C to 0x5E84BDA1 \n */ rlUInt32_t monStartFreqConst; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlTxBallbreakMonConf_t; /*! \brief * TX ballbreak monitoring configuration */ typedef struct rlAllTxBallBreakMonCfg { /** * @brief Tx ballbreak monitoring config for Tx0 */ rlTxBallbreakMonConf_t *tx0BallBrkMonCfg; /** * @brief Tx ballbreak monitoring config for Tx1 */ rlTxBallbreakMonConf_t *tx1BallBrkMonCfg; /** * @brief Tx ballbreak monitoring config for Tx2. */ rlTxBallbreakMonConf_t *tx2BallBrkMonCfg; }rlAllTxBallBreakMonCfg_t; /*! \brief * TX gain and phase mismatch monitoring configuration */ typedef struct rlTxGainPhaseMismatchMonConf { /** * @brief This field indicates the Profile Index for which this monitoring configuration \n applies. The TX settings corresponding to this profile index are used during \n the monitoring. The RX gain used in this measurement may differ from the given \n profile's RX gain. \n */ rlUInt8_t profileIndx; /** * @brief This field indicates the exact RF frequencies inside the profile's RF band at \n which to measure the required parameters. When each bit in this field is set, \n the measurement at the corresponding RF frequency is enabled wrt the profile's \n RF band. \n Bit RF frequency RF \n number name \n 0 Lowest RF frequency in profile's RF1 \n sweep bandwidth \n 1 Center RF frequency in profile's RF2 \n sweep bandwidth \n 2 Highest RF frequency in profile's RF3 \n sweep bandwidth \n The RF Name column is mentioned here to set the convention for the purpose of \n reporting and describing many monitoring packets. \n */ rlUInt8_t rfFreqBitMask; /** * @brief This field indicates the TX channels that should be compared for gain and phase \n balance. Setting the corresponding bit to 1 enables that channel for imbalance \n measurement \n Bit number TX Channel \n 0 TX0 \n 1 TX1 \n 2 TX2 \n */ rlUInt8_t txEn; /** * @brief This field indicates the RX channels that should be enabled for TX to RX loopback measurement. Setting the corresponding bit to 1 enables that channel for imbalance measurement. Bit RX Channel 0 RX0 1 RX1 2 RX2 3 RX3 */ rlUInt8_t rxEn; /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief The magnitude of difference between measured TX powers across the enabled \n channels at each enabled RF frequency is compared against this threshold. The \n comparison result is part of the monitoring report message(Error bit is set if \n the measurement is above this threshold). Before the comparison, the measured \n gains for each RF and RX are adjusted by subtracting the offset given in the \n TX_GAIN_MISMATCH_OFFSET_VALUE field. \n 1 LSB = 0.1dB, signed number \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlInt16_t txGainMismatchThresh; /** * @brief The magnitude of measured TX phase mismatch across the enabled channels at each \n enabled RF frequency is compared against this threshold. The comparison result \n is part of the monitoring report message (Error bit is set if any measurement \n is above this threshold). Before the comparison, the measured gains for each RF \n and RX are adjusted by subtracting the offset given in the \n TX_PHASE_MISMATCH_OFFSET_VALUE field. \n 1 LSB = 360(degree)/ 2^16 , unsigned number \n Valid range: corresponding to 0 degree to 359.9 degree. \n */ rlUInt16_t txPhaseMismatchThresh; /** * @brief The offsets to be subtracted from the measured TX gain for each TX and RF before \n the relevant threshold comparisons are given here. Byte numbers corresponding \n to different RX and RF, in this field are here: \n RF1 RF2 RF3 \n TX0 [1:0] [7:6] [13:12] \n TX1 [3:2] [9:8] [15:14] \n TX2 [5:4] [11:10] [17:16] \n 1 LSB = 0.1 dB \n Only the entries of enabled RF Frequencies and enabled TX \n channels are considered. \n */ rlUInt16_t txGainMismatchOffsetVal[(3U)][(3U)]; /** * @brief The offsets to be subtracted from the measured TX phase for each TX and RF before \n the \n relevant threshold comparisons are given here. Byte numbers corresponding to \n different RX and RF, in this field are here: \n RF1 RF2 RF3 \n TX0 [1:0] [7:6] [13:12] \n TX1 [3:2] [9:8] [15:14] \n TX2 [5:4] [11:10] [17:16] \n 1 LSB = 360(degree)/216. \n Only the entries of enabled RF Frequencies and enabled TX channels \n are considered. \n */ rlUInt16_t txPhaseMismatchOffsetVal[(3U)][(3U)]; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlTxGainPhaseMismatchMonConf_t; /*! \brief * TX BPM monitoring configuration */ typedef struct rlTxBpmMonConf { /** * @brief This field indicates the Profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief This field indicates the phase shifter monitoring configuration. \n Bit Definition \n 5:0 Phase shifter monitoring increment value \n 1 LSB = 5.625 degree \n 6 Phase shifter monitoring auto increment enabled. On each FTTI phase shift \n value increment by mentioned increment value at bit 0:5 \n 7 Phase shifter monitoring enabled \n @note : Phase shifter monitoring control is not supported in this release for all devices. This is a RESERVED field and should be set to 0. \n */ rlUInt8_t phaseShifterMonCnfg; /** * @brief Phase1 of the phase shifter of TX which needs to be monitored 1 LSB = 5.625 degree */ rlUInt8_t phaseShifterMon1; /** * @brief Phase2 of the phase shifter of TX which needs to be monitored 1 LSB = 5.625 degree */ rlUInt8_t phaseShifterMon2; /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief This field indicates the RX channels that should be enabled for TX to RX loopback measurement. Setting the corresponding bit to 1 enables that channel for imbalance measurement. Bit RX Channel 0 RX0 1 RX1 2 RX2 3 RX3 */ rlUInt8_t rxEn; /** * @brief The deviation of the TX output phase difference between the two BPM settings from \n the ideal 180o is compared against the threshold given here. The comparison \n result is part of the monitoring report message (Error bit is set if the \n measurement is lower than this threshold, with the units of both quantities \n being the same). \n 1 LSB = 360(degree) /2^16. \n Valid range: corresponding 0 degree to 359.9 degree \n */ rlUInt16_t txBpmPhaseErrThresh; /** * @brief The deviation of the TX output amplitude difference between the two BPM settings \n is compared against the threshold given here. The comparison result is part of \n the monitoring report message (Error bit is set if the measurement is lower \n than this threshold, with the units of both quantities being the same). \n 1 LSB = 0.1 dB \n Valid range: 0 to 65535 (0 to 6553dB) \n */ rlUInt16_t txBpmAmplErrThresh; /** * @brief Maximum threshold for the difference in the 2 configured phase shift values 1 LSB = 5.625 degree */ rlUInt16_t phaseShifterThreshMax; /** * @brief Minimum threshold for the difference in the 2 configured phase shift values 1 LSB = 5.625 degree */ rlUInt16_t phaseShifterThreshMin; /** * @brief Reserved for Future use */ rlUInt16_t reserved; } rlTxBpmMonConf_t; /*! \brief * TX BPM monitoring configuration */ typedef struct rlAllTxBpmMonConf { /** * @brief Tx-0 BPM monitoring config */ rlTxBpmMonConf_t *tx0BpmMonCfg; /** * @brief Tx-1 BPM monitoring config */ rlTxBpmMonConf_t *tx1BpmMonCfg; /** * @brief Tx-2 BPM monitoring config */ rlTxBpmMonConf_t *tx2BpmMonCfg; }rlAllTxBpmMonConf_t; /*! \brief * Synthesizer frequency monitoring configuration */ typedef struct rlSynthFreqMonConf { /** * @brief This field indicates the Profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check \n */ rlUInt8_t reportMode; /** * @brief During the chirp, the error of the measured instantaneous chirp frequency w.r.t. \n the desired value is continuously compared against this threshold. \n The comparison result is part of the monitoring report message (Error bit is \n set if the measurement is above this threshold, ever during the previous \n monitoring period). \n 1 LSB = 10 kHz \n Valid range: 0 to 65535 (0 to 655 MHz) \n */ rlUInt16_t freqErrThresh; /** * @brief This field determines when the monitoring starts in each \n chirp relative to the start of the ramp. \n 1 LSB = 0.2us, signed number \n Valid range: -25us to 25us \n Recommended value: 6us or above \n */ rlInt8_t monStartTime; /** * @brief This field configures whether this monitor should be done \n for functional active chirps (mode 0) or non live monitor chirps. In case of non \n live monitor, the configuration needs to be sent twice for two VCOs \n (use mode 1 and 2). \n Value Definition \n 0 LIVE_CONFIG, The profile configuration for live mode is picked from this API, supported only in master/single-chip mode. \n 1 VCO1_CONFIG, The profile configuration for Non-live mode is picked from this API for VCO1 monitor profile, supported in all modes (master, slave and single-chip). \n 2 VCO2_CONFIG, The profile configuration for Non-live mode is picked from this API for VCO2 monitor profile, supported in all modes (master, slave and single-chip). \n @note : This feature is supported only on xWR6843 device. \n */ rlUInt8_t monitorMode; /** * @brief This bit mask can be used to enable/disable the monitoring of non-live VCO profiles, this helps to control monitoring of only single VCO if needed. This setting should be same in both VCO settings. \n Bits Definition \n b0 Enable VCO1 non-live monitor \n b1 Enable VCO2 non-live monitor \n b31:2 RESERVED \n @note : This field is applicable only on xWR6843 device. \n */ rlUInt8_t vcoMonEn; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlSynthFreqMonConf_t; /*! \brief * External analog signals monitoring configuration */ typedef struct rlExtAnaSignalsMonConf { /** * @brief Value Definition \n 0 Report is sent every monitoring period without threshold check \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief This field indicates the sets of externally fed DC signals which are to be \n monitored using GPADC. When each bit in this field is set, the corresponding \n signal is monitored. The monitored signals are compared against programmed \n limits. The comparison result is part of the monitoring report message. \n Bit Location SIGNAL \n 0 ANALOGTEST1 \n 1 ANALOGTEST2 \n 2 ANALOGTEST3 \n 3 ANALOGTEST4 \n 4 ANAMUX \n 5 VSENSE \n Others RESERVED \n */ rlUInt8_t signalInpEnables; /** * @brief This field indicates the sets of externally fed DC signals which are to be \n buffered before being fed to the GPADC. When each bit in this field is set, the \n corresponding signal is buffered before the GPADC. The monitored signals are \n compared against programmed limits. The comparison result is part of the \n monitoring report message. \n Bit SIGNAL \n 0 ANALOGTEST1 \n 1 ANALOGTEST2 \n 2 ANALOGTEST3 \n 3 ANALOGTEST4 \n 4 ANAMUX \n Others RESERVED \n */ rlUInt8_t signalBuffEnables; /** * @brief After connecting an external signal to the GPADC, the amount of time to wait for \n it to settle before taking GPADC samples is programmed in this field. For each \n signal, after that settling time, GPADC measurements take place for 6.4us \n (averaging 4 samples of the GPADC output).The byte locations of the settling \n times for each signal are tabulated here: \n Byte Location SIGNAL \n 0 ANALOGTEST1 \n 1 ANALOGTEST2 \n 2 ANALOGTEST3 \n 3 ANALOGTEST4 \n 4 ANAMUX \n 5 VSENSE \n 1 LSB = 0.8us \n Valid range: 0 to 12us \n Valid programming condition: all the signals that are enabled \n should take a total of <100us, including the programmed settling \n times and a fixed 6.4us of measurement time per enabled signal. \n */ rlUInt8_t signalSettlingTime[6U]; /** * @brief The external DC signals measured on GPADC are compared against these minimum and \n maximum thresholds. The comparison result is part of the monitoring report \n message (Error bit is set if any measurement is outside this (minimum, maximum) \n range). \n Byte Location Threshold SIGNAL \n 0 Minimum ANALOGTEST1 \n 1 Minimum ANALOGTEST2 \n 2 Minimum ANALOGTEST3 \n 3 Minimum ANALOGTEST4 \n 4 Minimum ANAMUX \n 5 Minimum VSENSE \n 6 Maximum ANALOGTEST1 \n 7 Maximum ANALOGTEST2 \n 8 Maximum ANALOGTEST3 \n 9 Maximum ANALOGTEST4 \n 10 Maximum ANAMUX \n 11 Maximum VSENSE \n 1 LSB = 1.8V / 256 \n Valid range: 0 to 255(0 to 1.79V) \n */ rlUInt8_t signalThresh[12U]; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; /** * @brief Reserved for Future use */ rlUInt32_t reserved3; } rlExtAnaSignalsMonConf_t; /*! \brief * Internal signals in the TX path monitoring configuration */ typedef struct rlTxIntAnaSignalsMonConf { /** * @brief The RF analog settings corresponding to this profile are used for monitoring the \n enabled signals, using test chirps (static frequency, at the center of the \n profile's RF frequency band). \n */ rlUInt8_t profileIndx; /** * @brief Value Definition \n 0 RESERVED \n 1 Report is send only upon a failure(after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief The TX phase shifter DAC monitor delta threshold \n 1 LSB = 1.8V/1024 \n This field is applicable only for xWR6843 and xWR1843 devices. \n Value 0: TX_PS_DAC_MON is disabled \n Valid range: 1 to 1023 \n */ rlUInt16_t txPhShiftDacMonThresh; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlTxIntAnaSignalsMonConf_t; /*! \brief * Internal signals in the TX path monitoring configuration */ typedef struct rlAllTxIntAnaSignalsMonConf { /** * @brief Internal signals in the Tx-0 path monitoring config */ rlTxIntAnaSignalsMonConf_t *tx0IntAnaSgnlMonCfg; /** * @brief Internal signals in the Tx-1 path monitoring config */ rlTxIntAnaSignalsMonConf_t *tx1IntAnaSgnlMonCfg; /** * @brief Internal signals in the Tx-2 path monitoring config */ rlTxIntAnaSignalsMonConf_t *tx2IntAnaSgnlMonCfg; }rlAllTxIntAnaSignalsMonConf_t; typedef struct rlRxIntAnaSignalsMonConf { /** * @brief The RF analog settings corresponding to this profile are used for monitoring the \n enabled signals, using test chirps(static frequency,at the center of the \n profile's RF frequency band). \n */ rlUInt8_t profileIndx; /** * @brief Value Definition \n 0 RESERVED \n 1 Report is send only upon a failure(after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlRxIntAnaSignalsMonConf_t; /*! \brief * Internal signals for PM, CLK and LO monitoring configuration */ typedef struct rlPmClkLoIntAnaSignalsMonConf { /** * @brief The RF analog settings corresponding to this profile are used for monitoring the \n enabled signals, using test chirps(static frequency, at the center of the \n profile's RF frequency band). \n */ rlUInt8_t profileIndx; /** * @brief Value Definition \n 0 RESERVED \n 1 Report is send only upon a failure(after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Value Definition \n 0 20GHz SYNC monitoring disabled \n 1 FMCW_SYNC_IN monitoring enabled \n 2 FMCW_SYNC_OUT monitoring enabled \n 3 FMCW_SYNC_CLKOUT monitoring enabled \n @note : 20G signal monitoring control is not supported in this release for all devices. This is a RESERVED field and should be set to 0. \n */ rlUInt8_t sync20GSigSel; /** * @brief Minimum threshold for 20GHz monitoring\n 1 LSB = 1 dBm */ rlInt8_t sync20GMinThresh; /** * @brief Maximum threshold for 20GHz monitoring\n 1 LSB = 1 dBm */ rlInt8_t sync20GMaxThresh; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; } rlPmClkLoIntAnaSignalsMonConf_t; /*! \brief * Internal signals for GPADC monitoring configuration */ typedef struct rlGpadcIntAnaSignalsMonConf { /** * @brief Value Definition \n 0 RESERVED \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; } rlGpadcIntAnaSignalsMonConf_t; /*! \brief * Internal signals for PLL control voltage monitoring configuration */ typedef struct rlPllContrlVoltMonConf { /** * @brief Value Definition \n 0 RESERVED \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief This field indicates the sets of signals which are to be monitored. When each bit \n in this field is set, the corresponding signal set is monitored using test \n chirps. Rest of the RF analog may not be ON during these test chirps. The APLL \n VCO control voltage can be monitored. The Synthesizer VCO control voltage for \n both VCO1 and VCO2 can be monitored, while operating at their respective \n minimum and maximum frequencies, and their respective VCO slope (Hz/V) can be \n monitored if both frequencies are enabled for that VCO. The monitored signals \n are compared against internally chosen valid limits. The comparison results are \n part of the monitoring \n report message. \n Bit Location SIGNAL \n 0 APLL_VCTRL \n 1 SYNTH_VCO1_VCTRL \n 2 SYNTH_VCO2_VCTRL \n 15:3 RESERVED \n The synthesizer VCO extreme frequencies are: \n Synthesizer VCO Frequency Limits (Min, Max) \n VCO1 (76GHz, 78GHz) \n VCO2 (77GHz, 81GHz) \n Synthesizer measurements are done with TX switched off to avoid emissions. \n */ rlUInt16_t signalEnables; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlPllContrVoltMonConf_t; /*! \brief * Internal signals for DCC based clock monitoring configuration */ typedef struct rlDualClkCompMonConf { /** * @brief Value Definition \n 0 RESERVED \n 1 Report is send only upon a failure (after checking for thresholds) \n 2 Report is sent every monitoring period with threshold check. \n */ rlUInt8_t reportMode; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief This field indicates which pairs of clocks to monitor. When a bit in the field is \n set to 1, the firmware monitors the corresponding clock pair by deploying the \n hardware's Dual Clock Comparator in the corresponding DCC mode. \n Bit CLOCK PAIR \n 0 BSS_600M \n 1 BSS_200M \n 2 BSS_100M \n 3 GPADC_10M \n 4 RCOSC_10M \n 15:5 RESERVED \n The comparison results are part of the monitoring report message. The \n definition of the clock pairs and their error thresholds for failure reporting \n are given in the table below the message definition. \n */ rlUInt16_t dccPairEnables; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlDualClkCompMonConf_t; /*! \brief * RX saturation monitoring configuration */ typedef struct rlRxSatMonConf { /** * @brief This field indicates the profile Index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief 01 => Enable only the ADC saturation monitor \n 11 => Enable both the ADC and IFA1 saturation monitors \n */ rlUInt8_t satMonSel; /** * @brief Reserved for Future use */ rlUInt16_t reserved0; /** * @brief It specifies the duration of each (primary) time slice. \n 1 LSB = 0.16us. \n Valid range: 4 to floor(ADC sampling time us/0.16 us) \n @note : The minimum allowed duration of each (primary) time slice is \n 4 LSBs = 0.64us. Also, the maximum number of (primary) time slices that will \n be monitored in a chirp is 64 so the recommendation is to set this value to \n correspond to (ADC sampling time / 64). If the slice is smaller, such that the \n ADC sampling time is longer than 64 primary slices,some regions of the valid \n duration of a chirp may go un-monitored. \n */ rlUInt16_t primarySliceDuration; /** * @brief Number of (primary + secondary) time slices to monitor. \n Valid range: 1 to 127 \n @note 1: Together with primarySliceDuration, this determines the full \n duration of the ADC valid time that gets covered by the monitor \n Primary slices = (N+1) / 2 \n Secondary slices = Primary slices - 1 \n @note 2: The total monitoring duration is recommended to be programmed slightly \n smaller than ADC sampling time to avoid last primary slice miss in \n the CQ data. If this recommendation is not followed and if ADC \n sampling time is less than total requested monitoring duration then \n no error is generated but the total number of slices reported back in \n CQ buffer would be a different value M, which is less than user \n requested value of N. In such cases, there will be (M+1)/2 primary \n slices and (M-1)/2 secondary slices. However, if ADC sampling time is \n such that Secondary (M-1)/2 can be measured and not Primary (M+1)/2, \n then primary slice (M+1)/2 will not be present in the CQ buffer. In \n such scenario, CQ buffer will have the total number of slices reported \n back as M-1 instead of M. \n */ rlUInt16_t numSlices; /** * @brief This field is applicable only for SAT_MON_MODE = 0 Masks RX channels used for \n monitoring. In every slice, saturation counts for all unmasked channels are \n added together, and the total is capped to 127. The 8 bits are mapped \n (MSB->LSB) to: \n [RX3Q, RX2Q, RX1Q, RX0Q, RX3I, RX2I, RX1I, RX0I] \n 00000000 => All channels unmasked \n 11111111 => All channels masked. \n */ rlUInt8_t rxChannelMask; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Reserved for Future use */ rlUInt16_t reserved2; /** * @brief Reserved for Future use */ rlUInt32_t reserved3; /** * @brief Reserved for Future use */ rlUInt32_t reserved4; } rlRxSatMonConf_t; /*! \brief * Signal and image band energy monitoring configuration */ typedef struct rlSigImgMonConf { /** * @brief This field indicates the profile index for which this configuration applies. */ rlUInt8_t profileIndx; /** * @brief Number of (primary + secondary) slices to monitor Valid range: 1 to 127. */ rlUInt8_t numSlices; /** * @brief This field specifies the number of samples constituting each time slice. The \n minimum allowed value for this parameter is 4. \n Valid range: 4 to NUM_ADC_SAMPLES \n @note 1: The maximum number of (primary) time slices that will be monitored in \n a chirp is 64, so our recommendation is that this value should at \n least equal (NUM_ADC_SAMPLES / 64). If the slice is smaller, such \n that the number of ADC samples per chirp is larger than 64 primary \n slices, some regions of the valid duration of a chirp may go \n un-monitored. \n @note 2: In Complex1x mode, the minimum number of samples per slice is 4 and \n for other modes it is 8. Also note that number of samples should be \n an even number. \n @note 3: The total monitoring duration is recommended to program slightly \n smaller than ADC sampling time \n */ rlUInt16_t timeSliceNumSamples; /** * @brief Reserved for Future use */ rlUInt32_t reserved0; /** * @brief Reserved for Future use */ rlUInt32_t reserved1; } rlSigImgMonConf_t; /*! \brief * RX mixer input power monitoring configuration */ typedef struct rlRxMixInPwrMonConf { /** * @brief The RF analog settings corresponding to this profile are used for monitoring RX \n mixer input power using test chirps (static frequency, at the center of the \n profile's RF frequency band). \n */ rlUInt8_t profileIndx; /** * @brief Indicates the desired reporting verbosity and threshold usage. \n Value = 0 Report is sent every monitoring period without threshold check \n Value = 1 Report is send only upon a failure (after checking for thresholds) \n Value = 2 Report is sent every monitoring period with threshold check. \n Other values: RESERVED. \n */ rlUInt8_t reportMode; /** * @brief This field indicates if and which TX channels should be enabled while measuring \n RX mixer input power. Setting a bit to 1 enables the corresponding TX channel. \n Enabling a TX channel may help find reflection power while disabling may help \n find interference power. \n Bit number TX Channel \n 0 TX0 \n 1 TX1 \n 2 TX2 \n */ rlUInt8_t txEnable; /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief The measured RX mixer input voltage swings during this monitoring is compared \n against the minimum and maximum thresholds configured in this field. The comparison result is part of the monitoring report message (Error bit is set if \n any measurement is outside this (minimum, maximum) range). \n Byte number Threshold \n 0 Minimum Threshold \n 1 Maximum Threshold \n Only the RX channels enabled in the static configuration APIs are monitored. \n 1 LSB = 1800mV/256, unsigned number \n Valid range: 0 to 255 (0 to 1792.96 mV), maximum threshold >= minimum threshold \n */ rlUInt16_t thresholds; /** * @brief Reserved for Future use */ rlUInt16_t reserved1; /** * @brief Reserved for Future use */ rlUInt32_t reserved2; }rlRxMixInPwrMonConf_t; /*! \brief * RX signal and image band energy statistics */ typedef struct rlRfSigImgPowerCqData { /** * @brief Number of (primary + secondary) slices to monitor Valid range: 1 to 127. */ rlUInt16_t numSlices; /** * @brief The signal band and image band are separated using a two-channel filter bank and the ADC sampling time duration is monitored in terms of primary and secondary time slices as configured using rlRfRxSigImgMonConfig. If Number of Slices configured in rlRfRxSigImgMonConfig is N, then number of Primary slices = N+1/2 and number of secondary slices = N-1/2 \n For each of the two bands (signal and image), for each time slice, the input-referred average power in the slice in negative dBm is recorded as an 8-bit unsigned number, with 1 LSB = -0.5 dBm. CQ data is stored in 16bit format as follows: Pi[1] Ps[1], Si[1] Ss[1], Pi[2] Ps[2], Si[2] Ss[2]...... Pi[63] Ps[63], Si[63] Ss[63], Pi[64] Ps[64] Where, Pi = Primary Slice Image Band Power, 1LSB = -0.5dBm Ps = Primary Slice Signal Band Power, 1LSB = -0.5dBm Si = Secondary Slice Image Band Power, 1LSB = -0.5dBm Ss = Secondary Slice Signal Band Power, 1LSB = -0.5dBm This data is stored in CQ1 section of CQ RAM. If multiple chirps are defined, then this data is concatenated and stored in CQ RAM in ping pong manner @note : CQ0 section in CQ RAM will contain invalid data and the user should to ignore this. */ rlUInt16_t sigImgPowerCqVal[(127U)]; }rlRfSigImgPowerCqData_t; /*! \brief * RX ADC and IF saturation information */ typedef struct rlRfRxSaturationCqData { /** * @brief Number of (primary + secondary) slices to monitor Valid range: 1 to 127. */ rlUInt8_t numSlices; /** * @brief The analog to digital interface includes a 100 MHz bit stream indicating saturation events in the ADC/IF sections, for each channel. This one-bit indicator for each channel is monitored during the ADC sampling time duration in a time-sliced manner as defined in rlRfRxIfSatMonConfig.\n If Number of Slices configured in rlRfRxSigImgMonConfig is N, then number of Primary slices = (N+1)/2 and number of secondary slices = (N-1)/2 \n For each time slice, a saturation event count is recorded. This count is the sum of saturation event counts across all RX channels selected for monitoring, capped to a maximum count of 255 (8 bits).\n CQ data is stored in 16bit format as follows: P[1], S[1], P[2] S[2]......P[63], S[63], P[64] Where, P[n] = indicates the accumulated saturation count for all enabled RX channels in primary slice n S[n] = indicates the accumulated saturation count for all enabled RX channels in secondary slice n This data is stored in CQ2 section of CQ RAM. If multiple chirps are defined, then this data is concatenated and stored in CQ RAM in ping pong manner @note 1: CQ0 section in CQ RAM will contain invalid data. @note 2: This satCqVal data transfer happen through DMA not through SPI. So there is no problem of endianess. */ rlUInt8_t satCqVal[(127U)]; }rlRfRxSaturationCqData_t; typedef struct rlAnaFaultInj { /** * @brief Reserved for Future use */ rlUInt8_t reserved0; /** * @brief Primary Fault: RX Gain. This field indicates which RX RF sections should have \n fault injected. If the fault is enabled, the RX RF gain drops significantly. \n The fault can be used to cause significant gain change, inter-RX gain imbalance \n and an uncontrolled amount of inter-RX phase imbalance. \n This fault can be seen in RX_GAIN_PHASE_MONITOR. \n Bit RX Channel \n 0 RX0 \n 1 RX1 \n 2 RX2 \n 3 RX3 \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t rxGainDrop; /** * @brief Primary Fault: RX Phase. This field indicates which RX channels should have \n fault injected. If the fault is enabled, the RX phase gets inverted. The fault \n can be used to cause a controlled amount (180 deg) of inter-RX phase imbalance. \n This fault can be seen in RX_GAIN_PHASE_MONITOR. \n Bit RX Channel \n 0 RX0 \n 1 RX1 \n 2 RX2 \n 3 RX3 \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t rxPhInv; /** * @brief Primary Fault: RX Noise. This field indicates which RX channels should have fault \n injected. If the fault is enabled, the RX IFA square wave loopback paths are \n engaged to inject high noise at RX IFA input. The fault can be used to cause \n significant RX noise floor elevation. \n This fault can be seen in RX_GAIN_PHASE_MONITOR and RX_NOISE_FIGURE_MONITOR. \n Bit RX Channel \n 0 RX0 \n 1 RX1 \n 2 RX2 \n 3 RX3 \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t rxHighNoise; /** * @brief Primary Fault: Cutoff frequencies of RX IFA HPF & LPF, IFA Gain. This field \n indicates which RX channels should have fault injected. If the fault is enabled, \n the RX IFA HPF cutoff frequency becomes very high (about 15MHz). The fault can be \n used to cause the measured inband IFA gain, HPF and LPF attenuations to vary from \n ideal expectations. \n This fault can be seen in RX_IFSTAGE_MONITOR. \n Bit RX Channel \n 0 RX0 \n 1 RX1 \n 2 RX2 \n 3 RX3 \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault \n @note : during the execution of RX_IFSTAGE_MONITOR, the RX_HIGH_NOISE faults are \n temporarily removed. */ rlUInt8_t rxIfStagesFault; /** * @brief Primary Fault: RX Mixer LO input swing reduction. This field indicates which RX \n channels should have fault injected. If the fault is enabled, the RX mixer LO \n input swing is significantly reduced. The fault is primarily expected to be \n detected by RX_INTERNAL_ANALOG_SIGNALS_MONITOR (under PWRDET_RX category). \n Bit Channel \n 0 RX0 and RX1 \n 1 RX2 and RX3 \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault @note : This option is de-featured, please refer latest release note. \n */ rlUInt8_t rxLoAmpFault; /** * @brief Primary Fault: TX PA input signal generator turning off. This field indicates \n which TX channels should have fault injected. If the fault is enabled, the \n amplifier generating TX power amplifier's LO input signal is turned off. The \n fault is primarily expected to be detected by \n TX_INTERNAL_ANALOG_SIGNALS_MONITOR (under DCBIAS category). \n Bit Channel \n 0 TX0 and TX1 \n 1 TX2 (applicable only if available in the xWR device) \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault @note : This option is de-featured, please refer latest release note. \n */ rlUInt8_t txLoAmpFault; /** * @brief Primary Fault: TX Gain (power). This field indicates which TX RF sections should \n have fault injected. If the fault is enabled, the TX RF gain drops significantly. \n The fault can be used to cause significant TX output power change, inter-TX gain \n imbalance and an uncontrolled amount of inter-TX phase imbalance. \n This fault can be seen in TXn_POWER_MONITOR \n Bit TX Channel \n 0 TX0 \n 1 TX1 \n 2 TX2 \n Others RESERVED \n For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t txGainDrop; /** * @brief Primary Fault: TX Phase. This field indicates if TX channels should have fault \n injected, along with some further programmability. If the fault is enabled, the \n TX BPM polarity (phase) is forced to a constant value as programmed. The fault \n can be used to cause a controlled amount (180 degree) of inter-TX phase imbalance \n as well as BPM functionality failure. \n This fault can be seen in TX_GAIN_PHASE_MISMATCH_MONITOR and TXn_PHASE_SHIFTER_MONITOR. \n Bit TX Channel \n 0 TX fault (Common for all TX channels) \n 1 RESERVED \n 2 RESERVED \n 3 TX0 BPM VALUE \n 4 TX1 BPM VALUE \n 5 TX2 BPM VALUE \n Others RESERVED \n For each TX BPM VALUE: Applicable only if TX FAULT is enabled. \n Value = 0: force TX BPM polarity to 0 \n Value = 1: force TX BPM polarity to 1. */ rlUInt8_t txPhInv; /** * @brief Primary Fault: Synthesizer Frequency. This field indicates which Synthesizer \n faults should be injected. SYNTH_VCO_OPENLOOP: If the fault is enabled, the \n synthesizer is forced in open loop mode with the VCO control voltage forced to \n a constant. In order to avoid out of band emissions in this faulty state, this \n fault is injected just before the PLL_CONTROL_VOLTAGE_MONITOR is executed and \n released just after its completion. \n This fault can be seen in PLL_CONTROL_VOLTAGE_MONITOR. \n SYNTH_FREQ_MON_OFFSET: If the fault is enabled, the synthesizer frequency \n monitor's ideal frequency ramp waveform is forced to be offset from the actual \n ramp waveform by a constant, causing monitoring to detect failures. \n This fault can be seen in SYNTH_FREQ_MONITOR. \n Bit Enable Fault 0 SYNTH_VCO_OPENLOOP 1 SYNTH_FREQ_MON_OFFSET Others RESERVED For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t synthFault; /** * @brief This field indicates whether some LDO output voltage faults should be injected or not.\n Bit Enable Fault \n 0 SUPPLY_LDO_RX_LODIST_FAULT \n Others RESERVED\ n SUPPLY_LDO_RX_LODIST_FAULT: if enabled, the RX LO distribution sub system's LDO \n output voltage is slightly changed compared to normal levels to cause \n INTERNAL_PMCLKLO_SIGNALS_MONITOR to detect failure (under SUPPLY category). \n This fault can be seen in INTERNAL_PMCLKLO_SIGNALS_MONITOR. \n For each bit, 1 = inject fault, 0 = remove injected fault \n @note : This fault injection is ineffective under LDO bypass condition. */ rlUInt8_t supplyLdoFault; /** * @brief This field indicates whether a few miscellaneous faults should be injected or not. \n Bit Enable Fault \n 0 GPADC_CLK_FREQ_FAULT \n Others RESERVED \n GPADC_CLK_FREQ_FAULT: if enabled, the GPADC clock frequency is slightly increased \n compared to normal usage to cause BSS DCC_CLOCK_FREQ_MONITOR to detect failure. \n This fault can be seen in DCC_CLOCK_FREQ_MONITOR. \n For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t miscFault; /** * @brief This field indicates whether faults should be forced in the threshold comparisons \n in the software layer of some monitors. If a fault is enabled, the logic in the \n min-max threshold comparisons used for failure detection is inverted, causing a \n fault to be reported. During these faults, no hardware fault condition is \n injected in the device. This fault can be seen in GPADC_INTERNAL_SIGNALS_MONITOR. \n Bit Enable Fault 0 EXTERNAL_ANALOG_SIGNALS_MONITOR 1 GPADC_INTERNAL_SIGNALS_MONITOR Others RESERVED For each bit, 1 = inject fault, 0 = remove injected fault */ rlUInt8_t miscThreshFault; /** * @brief Reserved for Future use */ rlUInt8_t reserved1; /** * @brief Reserved for Future use */ rlUInt16_t reserved2; /** * @brief Reserved for Future use */ rlUInt16_t reserved3; /** * @brief Reserved for Future use */ rlUInt16_t reserved4; } rlAnaFaultInj_t; /** * @defgroup Monitoring Monitoring * @brief mmwave radar RF/Sensor Monitoring module * * mmWave Device monitoring can be configured through a set of APIs defined in this section. Note that these APIs cover the RF/Analog related monitoring mechanisms. There are separate monitoring mechanisms for the digital logic (including the processor, memory, etc.) which are internal to the device and not explicitly enabled through these APIs.\n The monitoring APIs are structured as follows:\n -# There are common configuration APIs that control the overall periodicity of monitoring, as well as, enable/disable control for each monitoring mechanism.\n -# Then, for each monitoring mechanism there is an individual API to allow the application to set an appropriate threshold for declaring failure from that monitoring.\n -# Also, for each monitoring mechanism, there is an individual API to report soft (raw) values from that monitoring.\n -# The Raw, Failure or Periodic Monitoring report are sent to application using asynchronous events. * Below is the list of Monitors and corresponding duration in microseconds \n
Analog Monitoring Duration
Monitors xWR1xxx(us)xWR6x43(us)
Temperature200200
RX gain phase (assumes 1 RF frequency)12501250
RX noise figure (assumes 1 RF frequency)250250
RX IF stage (assumes 1 RF frequency)10001400
TX power (assumes 1 TX, 1 RF frequency)200250
TX ballbreak (assumes 1 TX)250300
TX gain phase mismatch (assumes 1 TX, 1 RF frequency)400400
TX BPM575575
Synthesizer frequency 0100
External analog signals (all 6 GPADC channels enabled)150150
TX Internal analog signals (assumes 1 TX)200300
TX Phase shifter DAC monitor (assumes 1 TX),(applicable only for xWR1843/6843 devices) 22002300
RX internal analog signals17001900
PMCLKLO internal analog signals400550
GPADC internal signals5050
PLL control voltage 250300
Dual clock comparator (assumes 6 clock comparators)110300
RX saturation detector 0100
RX signal and image band monitor0100
RX mixer input power600700
Synthesizer frequency non-live monitorNA500
Digital Monitoring Duration
Monitors Duration(us)
Periodic configuration register readback70
DFE LBIST monitoring1000
Frame timing monitoring10
Software Overheads
Software Overhead Duration(us)
Periodic monitoring of stack usage20
Minimum monitoring duration (report formation, digital energy monitor at the end of FTTI, temperature read every FTTI)1000
Minimum calibration duration (report formation, temperature read every CAL_MON_TIME_UNIT) 500
Idle time needed per FTTI for windowed watchdog (WDT) Frame period * CALIB_MON_TIME_UNIT/8 i.e.~12.5% of Frame period * CALIB_MON_TIME_UNIT is reserved for watchdog clearing time
* * Related Files * - rl_monitoring.c * @addtogroup Monitoring * @{ */ /****************************************************************************** * FUNCTION DECLARATIONS ****************************************************************************** */ /* Digital Monitoring Configuration */ rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap, rlMonDigEnables_t* data); /* Digital Monitoring Periodic Configuration */ rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap, rlDigMonPeriodicConf_t* data); /* Analog Monitoring Configuration */ rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap, rlMonAnaEnables_t* data); /* TemperatureSsensor Monitoring Configuration */ rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t* data); /* RX Gain and Phase Monitoring Configuration */ rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap, rlRxGainPhaseMonConf_t* data); /* RX Noise Monitoring Configuration */ rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap, rlRxNoiseMonConf_t* data); /* RX IF Stage Monitoring Configuration */ rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap, rlRxIfStageMonConf_t* data); /* TX Power Monitoring Configuration */ rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap, rlAllTxPowMonConf_t *data); /* TX Ballbreak Monitoring Configuration */ rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap, rlAllTxBallBreakMonCfg_t* data); /* TX Gain Phase Mismatch Monitoring Configuration */ rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap, rlTxGainPhaseMismatchMonConf_t* data); /* TX BPM Monitoring Configuration */ rlReturnVal_t rlRfTxBpmMonConfig(rlUInt8_t deviceMap, rlAllTxBpmMonConf_t* data); /* Synth Freq Monitoring Configuration */ rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap, rlSynthFreqMonConf_t* data); /* External Analog Signals Monitoring Configuration */ rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap, rlExtAnaSignalsMonConf_t* data); /* TX Internal Analog Signals Monitoring Configuration */ rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlAllTxIntAnaSignalsMonConf_t* data); /* RX Internal Analog Signals Monitoring Configuration */ rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlRxIntAnaSignalsMonConf_t* data); /* PM, CLK, LO Internal Analog Signals Monitoring Configuration */ rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlPmClkLoIntAnaSignalsMonConf_t* data); /* GPADC Internal Analog Signals Monitoring Configuration */ rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlGpadcIntAnaSignalsMonConf_t* data); /* PLL Control Voltage Monitoring Configuration */ rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap, rlPllContrVoltMonConf_t* data); /* Dual Clock Comparator Monitoring Configuration */ rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap, rlDualClkCompMonConf_t* data); /* RX Saturation Monitoring Configuration */ rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap, rlRxSatMonConf_t* data); /* RX Signal Image band Monitoring Configuration */ rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap, rlSigImgMonConf_t* data); /* RX mixer input power monitoring.Configuration */ rlReturnVal_t rlRfRxMixerInPwrConfig(rlUInt8_t deviceMap, rlRxMixInPwrMonConf_t* data); /* Analog fault injection Configuration */ rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap, rlAnaFaultInj_t* data); /*! Close the Doxygen group. @} */ /* * END OF RL_MONITORING_H FILE */ /**************************************************************************************** * FileName : rl_messages.h * * Description : This file includes all the Messages that is communicated by the Radar APIs * **************************************************************************************** * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com *--------------------------------------------------------------------------------------- * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of Texas Instruments Incorporated nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /**************************************************************************************** * FILE INCLUSION PROTECTION **************************************************************************************** */ /**************************************************************************************** * INCLUDE FILES **************************************************************************************** */ /**************************************************************************************** * MACRO DEFINITIONS **************************************************************************************** */ /****************************************************************************** * GLOBAL VARIABLES/DATA-TYPES DEFINITIONS ****************************************************************************** */ /*! \brief * Command Message ID : Unique ID of each Command Messages - max 8 bits (0 - 191) */ /* radarSS Msg IDs */ /* DSS Msg IDs */ /* MSS Msg IDs */ /* Async Event Msg ID, generated internally by mmWavLink */ /*! \brief * Sub-block ID : - max 32 SBC * MsgID : RL_RF_RESP_ERROR_MSG */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_STATIC_CONF_SET_MSG/RL_RF_STATIC_CONF_GET_MSG * Static configuration sub-blocks are grouped as static messages. These messages are mostly static settings shall be configured once in radar transceiver after power cycle. * Static GET messages can be used to read the static configuration settings from the radar transceiver. */ /*! \brief * Sub-block ID : - max 32 SBC * MsgID : RL_RF_INIT_MSG * RF initialization message does the boot time calibration of the radar transceiver. */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_DYNAMIC_CONF_SET_MSG/RL_RF_DYNAMIC_CONF_GET_MSG * Dynamic configuration sub-blocks are grouped as dynamic messages. These messages are mostly dynamic settings configures the radar transceiver profiles, chirp and frames (waveform), these settings can be updated dynamically to achieve the dynamic waveform generation. * Dynamic GET messages can be used to read the dynamic configuration settings from the radar transceiver. */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_FRAME_TRIG_MSG Frame trigger message for the radar transceiver to start the waveform. */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_ADVANCED_FEATURES_SET_MSG/RL_RF_ADVANCED_FEATURES_GET_MSG * Advance configuration messages for radar transceiver. */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_MONITORING_CONF_SET_MSG/RL_RF_MONITORING_CONF_GET_MSG * Monitoring configuration message sub-blocks for radar transceiver. */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_STATUS_GET_MSG * Radar transceiver status GET messages. */ /*! \brief * GET Sub-block ID : - max 32 SBC * MsgID : RL_RF_MONITORING_REPO_GET_MSG * DFE statistics report GET message from Radar transceiver. */ /*! \brief * SET Sub-block ID : - max 32 SBC * MsgID : RL_RF_MONITORING_CONF_SET_MSG * Monitoring configuration message sub-blocks for radar transceiver. */ /*! \brief * SET Sub-block ID : - max 32 SBC * MsgID : RL_RF_MISC_CONF_SET_MSG * Miscellaneous configuration message sub-blocks for radar transceiver. */ /*! \brief * GET Sub-block ID : SB - max 32 SBC * MsgID : RL_RF_MISC_CONF_GET_MSG * Miscellaneous configuration GET messages from radar transceiver. */ /*! \brief * Sub-block ID : - max 32 SBC * MsgID : RL_RF_ASYNC_EVENT_MSG * @note : In reporting mode 1 (Quiet mode) if any failure in RadarSS analog or digital monitors * the AWR1243 device will send AWR AE MSS RFERROR STATUS SB AE with error code 0x7 along * with failure monitoring report. */ /*! \brief * Sub-block ID : - max 32 SBC * MsgID : RL_RF_ASYNC_EVENT_1_MSG * @note : In reporting mode 1 (Quiet mode) if any failure in RadarSS analog or digital monitors * the AWR1243 device will send AWR AE MSS RFERROR STATUS SB AE with error code 0x7 along * with failure monitoring report. */ /*! \brief * Unique ID of each SB - max 32 SBC * MsgId - RL_MMWL_ASYNC_EVENT_MSG */ /*! \brief * Unique ID of each SB - max 32 SBC * MsgId - RL_DEV_POWERUP_MSG * @note : All device config APIs having sub block ID >= 0x4000 are applicable only for MSS in * AWR1243 RF front end devices, for other xWR1443, xWR1642 and xWR1843 devices, these * APIs are for reference only. */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID - RL_DEV_FILE_DOWNLOAD_MSG */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID - RL_DEV_CONFIG_SET_MSG */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID - RL_DEV_CONFIG_APPLY_MSG */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID - RL_DEV_STATUS_GET_MSG */ /*! \brief * Sub-block ID : - max 32 SBC * Async Event Sub-Blocks from MSS. MsgID - RL_DEV_ASYNC_EVENT_MSG */ /*! \brief * rlSysAeFaultRepoMsgSbcId_t Sub-block ID : - max 32 SBC */ /*! \brief * Sub-block ID : - max 32 SBC * MsgID - RL_RF_MONITORING_REPO_GET_MSG */ /*! \brief * SET/GET Sub-block ID : - max 32 SBC * MsgID - RL_DEV_INTERNAL_CONF_SET_MSG, RL_DEV_INTERNAL_CONF_GET_MSG */ /*! \brief * Response Error types : 16 bits */ /****************************************************************************** * FUNCTION PROTOTYPES ****************************************************************************** */ /* * END OF RL_MESSAGES_H */ /****************************************************************************** * FUNCTION PROTOTYPES ****************************************************************************** */ /* * END OF MMWAVELINK_H */ /** @defgroup MMWAVE_CTRL_EXTERNAL_FUNCTION mmWave External Functions @ingroup MMWAVE @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup MMWAVE_EXTERNAL_DATA_STRUCTURE mmWave External Data Structures @ingroup MMWAVE @brief * The section has a list of all the data structures which are exposed to the * application */ /** @defgroup MMWAVE_EXTERNAL_DEFINITIONS mmWave External Defintions @ingroup MMWAVE @brief * The section has a list of all external definitions which are exposed by the * mmWave module. */ /** @defgroup MMWAVE_ERROR_CODE mmWave Error Codes @ingroup MMWAVE @brief * The section has a list of all the error codes which are generated by the module */ /** @defgroup MMWAVE_INTERNAL_FUNCTION mmWave Internal Functions @ingroup MMWAVE @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup MMWAVE_INTERNAL_DATA_STRUCTURE mmWave Internal Data Structures @ingroup MMWAVE @brief * The section has a list of all internal data structures which are used internally * by the mmWave module. */ /** @defgroup MMWAVE_INTERNAL_DEFINITIONS mmWave Internal Defintions @ingroup MMWAVE @brief * The section has a list of all internal definitions which are used internally * by the mmWave module. */ /** @addtogroup MMWAVE_ERROR_CODE * Base error code for the mmWave module is defined in the * \include ti/common/mmwave_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: mmWave link initialization failed */ /** * @brief Error Code: mmWave link not supported */ /** * @brief Error Code: mmWave link channel configuration failed */ /** * @brief Error Code: mmWave link ADC configuration failed */ /** * @brief Error Code: mmWave link Power configuration failed */ /** * @brief Error Code: mmWave link RF initialization failed */ /** * @brief Error Code: mmWave link profile configuration failed */ /** * @brief Error Code: mmWave link chirp configuration failed */ /** * @brief Error Code: mmWave link frame configuration failed */ /** * @brief Error Code: mmWave link PLL caliberation failed */ /** * @brief Error Code: mmWave link sensor failed */ /** * @brief Error Code: OS Porting layer services failed */ /** * @brief Error Code: mmWave Link version error */ /** * @brief Error Code: mmWave message processing error */ /** * @brief Error Code: mmWave deinitialization error */ /** * @brief Error Code: mmWave continuous mode configuration failed */ /** * @brief Error Code: mmWave continuous mode enabling failed */ /** * @brief Error Code: mmWave link BSS calibration configuration failed */ /** * @brief Error Code: mmWave link BSS calibration init */ /** * @brief Error Code: mmWave link BSS calibration periodicity failed */ /** * @brief Error Code: mmWave link BSS calibration trigger failed */ /** * @brief Error Code: Out of memory error */ /** * @brief Error Code: Not found */ /** * @brief Error Code: Asynchronous event configuration failed */ /** * @brief Error Code: Calibration failed. */ /** * @brief Error Code: mmWave link BPM common configuration failed */ /** * @brief Error Code: mmWave link BPM configuration failed */ /** * @brief Error Code: invalid value provided for calibMonTimeUnit * in MMWave_open() failed */ /** * @brief Error Code: Phase shift Calibration data restore failed. */ /** @} */ /** @addtogroup MMWAVE_EXTERNAL_DEFINITIONS @{ */ /** * @brief * mmWave Supported max profiles which can be configured on the BSS */ /** * @brief * This is the ACK wait timeout in msec. This is the time for which the * mmWave link module will wait for the reception on an ACK from the BSS. If * this is set to 0 then the mmWave link will not wait for an ACK. */ /** @} */ /** @addtogroup MMWAVE_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief * mmWave Profile Handle */ typedef void* MMWave_ProfileHandle; /** * @brief * mmWave Chirp Handle */ typedef void* MMWave_ChirpHandle; /** * @brief * mmWave BPM configuration Handle */ typedef void* MMWave_BpmChirpHandle; /** * @brief * Error Level * * @details * The mmWave module API can return different error levels. The enumeration * describes different error levels. Please refer to the MMWave error decode * function on the interpretation of this error level. * * @sa * MMWave_decodeError */ typedef enum MMWave_ErrorLevel_e { /** * @brief The mmWave API was successful. There were no errors detected. * There is no reason to perform any error decode here. */ MMWave_ErrorLevel_SUCCESS = 0, /** * @brief The mmWave API reported a warning. Application can either ignore this * error message *OR* can perform the error decoding to get more information * on the actual reason. */ MMWave_ErrorLevel_WARNING, /** * @brief The mmWave API reported an error and applications should perform * error decoding to get the exact reason for the failure. */ MMWave_ErrorLevel_ERROR }MMWave_ErrorLevel; /** * @brief * DFE Data Output Mode * * @details * The enumeration describes the mode in which the DFE outputs the data */ typedef enum MMWave_DFEDataOutputMode_e { /** * @brief The DFE is operating in Frame mode */ MMWave_DFEDataOutputMode_FRAME = 0xA0000000U, /** * @brief The DFE is operating in continuous mode */ MMWave_DFEDataOutputMode_CONTINUOUS, /** * @brief The DFE is operating in advanced frame mode */ MMWave_DFEDataOutputMode_ADVANCED_FRAME }MMWave_DFEDataOutputMode; /** * @brief * Default Asynchronous Event Handler * * @details * Enumeration describes the entity which is responsible for the reception * of asynchronous events from the BSS. By default the BSS assumes that the * MSS is the recepient of asynchronous events such as CPU & ESM Faults etc. */ typedef enum MMWave_DefaultAsyncEventHandler_e { /** * @brief The MSS is the default handler for the asynchronous event */ MMWave_DefaultAsyncEventHandler_MSS, /** * @brief The DSS is the default handler for the asynchronous event * Not a vallid option for xwr14xx/xwr64xx device */ MMWave_DefaultAsyncEventHandler_DSS }MMWave_DefaultAsyncEventHandler; /** * @brief * Chirp Calibration configuration * * @details * The structure is used to hold the information which is required * to setup the calibration of the RF while operating in the Chirp * mode */ typedef struct MMWave_ChirpCalibrationCfg_t { /** * @brief Flag which determines if calibration is to be enabled or * not. */ _Bool enableCalibration; /** * @brief Flag which determines if periodic calibration is to be enabled or * not. The mmWave will always do one time calibration. */ _Bool enablePeriodicity; /** * @brief This is valid only if periodicity is enabled and is the time in frames * when a calibration report is received by the application through an asynchrous * event. */ uint16_t periodicTimeInFrames; }MMWave_ChirpCalibrationCfg; /** * @brief * Continuous Calibration configuration * * @details * The structure is used to hold the information which is required * to setup the calibration of the RF while operating in continuous * mode */ typedef struct MMWave_ContCalibrationCfg_t { /** * @brief In continuous mode; only one shot calibration is supported * Set this flag to enable this feature. */ _Bool enableOneShotCalibration; }MMWave_ContCalibrationCfg; /** * @brief * Calibration configuration * * @details * The structure is used to hold the information which is required * to setup the calibration of the RF */ typedef struct MMWave_CalibrationCfg_t { /** * @brief DFE Data Output Mode: Chirp or Continuous * * NOTE: Please ensure that the DFE Data output mode passed during * control configuration and calibration configuration should be * the same. Failure to do so will result in unpredictable behavior */ MMWave_DFEDataOutputMode dfeDataOutputMode; union { /** * @brief This should be configured if the DFE Data output mode * is configured to operate in frame or advanced frame mode */ MMWave_ChirpCalibrationCfg chirpCalibrationCfg; /** * @brief This should be configured if the DFE Data output mode * is configured to operate in continuous mode */ MMWave_ContCalibrationCfg contCalibrationCfg; }u; }MMWave_CalibrationCfg; /** * @brief * Frame mode configuration * * @details * The structure specifies the configuration which is required to configure * the mmWave link to operate in frame mode */ typedef struct MMWave_FrameCfg_t { /** * @brief List of all the active profile handles which can be configured. * Setting to NULL indicates that the profile is skipped. */ MMWave_ProfileHandle profileHandle[4]; /** * @brief Configuration which is used to setup Frame */ rlFrameCfg_t frameCfg; }MMWave_FrameCfg; /** * @brief * Advanced frame configuration * * @details * The structure specifies the configuration which is required to configure * the mmWave link to operate in advanced frame mode */ typedef struct MMWave_AdvancedFrameCfg_t { /** * @brief List of all the active profile handles which can be configured. * Setting to NULL indicates that the profile is skipped. */ MMWave_ProfileHandle profileHandle[4]; /** * @brief Advanced Frame configuration */ rlAdvFrameCfg_t frameCfg; }MMWave_AdvancedFrameCfg; /** * @brief * Continuous mode configuration * * @details * The structure specifies the configuration which is required to configure * the mmWave link to operate in continuous mode */ typedef struct MMWave_ContModeCfg_t { /** * @brief Continuous mode configuration */ rlContModeCfg_t cfg; /** * @brief Sample count: This refers to the number of samples per * channel. */ uint16_t dataTransSize; }MMWave_ContModeCfg; /** * @brief * Control configuration * * @details * The structure specifies the configuration which is required to configure * and setup the BSS. */ typedef struct MMWave_CtrlCfg_t { /** * @brief DFE Data Output Mode: */ MMWave_DFEDataOutputMode dfeDataOutputMode; union { /** * @brief Chirp configuration to be used: This is only applicable * if the data output mode is set to Chirp */ MMWave_FrameCfg frameCfg; /** * @brief Continuous configuration to be used: This is only applicable * if the data output mode is set to Continuous */ MMWave_ContModeCfg continuousModeCfg; /** * @brief Advanced Frame configuration: This is only applicable * if the data output mode is set to Advanced Frame */ MMWave_AdvancedFrameCfg advancedFrameCfg; }u; }MMWave_CtrlCfg; /** * @brief * Open Configuration * * @details * The structure specifies the configuration which is required to open the * MMWave module. Once the MMWave module has been opened the mmWave link * to the BSS is operational. */ typedef struct MMWave_OpenCfg_t { /** * @brief Low Frequency Limit for calibrations: */ uint16_t freqLimitLow; /** * @brief High Frequency Limit for calibrations */ uint16_t freqLimitHigh; /** * @brief Configuration which is used to setup channel */ rlChanCfg_t chCfg; /** * @brief Low power mode configuration */ rlLowPowerModeCfg_t lowPowerMode; /** * @brief Configuration which is used to setup ADC */ rlAdcOutCfg_t adcOutCfg; /** * @brief Designate the default asynchronous event handler. By default * the BSS assumes that the default asynchronous event handler is the MSS. \n * Field Not valid for xwr14xx. */ MMWave_DefaultAsyncEventHandler defaultAsyncEventHandler; /** * @brief Flag that determines if frame start async event is disabled. * For more information refer to the mmWave Link documentation for:- * - RL_RF_AE_FRAME_TRIGGER_RDY_SB * - rlSensorStart */ _Bool disableFrameStartAsyncEvent; /** * @brief Flag that determines if frame stop async event is disabled. * For more information refer to the mmWave Link documentation for:- * - RL_RF_AE_FRAME_END_SB * - rlSensorStop */ _Bool disableFrameStopAsyncEvent; /** * @brief Set the flag to enable the application to specify the calibration * mask which is to be used. If the flag is set to false the MMWave module will * default and enable all the calibrations. */ _Bool useCustomCalibration; /** * @brief This is the custom calibration enable mask which is to be used and * is applicable only if the application has enabled "Custom Calibration" */ uint32_t customCalibrationEnableMask; /** * @brief Calibration Monitor time unit configuration in units of frame. * Value of 1 here means Calibration Monitor time unit = 1 frame duration. * See rlRfCalMonTimeUntConf_t for details on this configuration. */ rlUInt16_t calibMonTimeUnit; }MMWave_OpenCfg; /** * @brief * Calibration Configuration * * @details * The structure specifies the various calibration data that RadarSS needs * in case user desires to restore the calibration using factory values instead * of requesting RadarSS to calculate them on-the-fly. */ typedef struct MMWave_CalibrationData_t { /** * @brief Calibration data as received from RadarSS via rlRfCalibDataStore API */ rlCalibrationData_t* ptrCalibData; /** * @brief xwr18xx/xwr6xxx: Phase shifter calibration data as received from * RadarSS via rlRfPhShiftCalibDataStore API */ rlPhShiftCalibrationData_t* ptrPhaseShiftCalibData; } MMWave_CalibrationData; /** * @b Description * @n * Application registered callback function which hooks up with the mmWave Link * events generated by the BSS. Please refer to the mmWave Link documentation * on more information about these parameters. * * *NOTE*: On the XWR16xx/XWR18xx/XWR68xx (In cooperative mode) asynchronous events are received * and passed to the application. The event is also forwarded to the remote * domain. In certain cases application would like to reduce the overhead * of passing the message to the remote domain in which case the event handler * should return 1 which implies that the event is consumed (Hijacked) by the * application. Setting the return value to 0 would imply that the event is * passed to the remote peer. Applications can use this mechanism to ensure that * only certain events are passed between domains. * * @param[in] msgId * Message Identifier * @param[in] sbId * Subblock identifier * @param[in] sbLen * Length of the subblock * @param[in] payload * Pointer to the payload buffer * * @retval * 1 - Hijack the event and do not pass to the peer domain (If applicable) * @retval * 0 - Pass the event to the peer domain (If applicable) */ typedef int32_t (*MMWave_eventFxn)(uint16_t msgId, uint16_t sbId, uint16_t sbLen, uint8_t *payload); /** * @b Description * @n * Application registered callback function which is invoked after the configuration * has been used to configure the mmWave link and the BSS. This is applicable only for * the XWR16xx/XWR18xx/XWR68xx. The BSS can be configured only by the MSS *or* DSS. The callback API is * triggered on the remote execution domain (which did not configure the BSS) * * @param[in] ptrCtrlCfg * Pointer to the control configuration * * @retval * Not applicable */ typedef void (*MMWave_cfgFxn)(MMWave_CtrlCfg* ptrCtrlCfg); /** * @b Description * @n * Application registered callback function which is invoked after the domain * has opened the mmWave control module. The BSS has been initialized at this * point in time. Applications can use the link API from this point in time. * The callback API is only triggered in the remote execution domain. * * @param[in] ptrOpenCfg * Pointer to the open configuration * * @retval * Not applicable */ typedef void (*MMWave_openFxn)(MMWave_OpenCfg* ptrOpenCfg); /** * @b Description * @n * Application registered callback function which is invoked after the domain * has closed the mmWave control module. * * @retval * Not applicable */ typedef void (*MMWave_closeFxn)(void); /** * @b Description * @n * Application registered callback function which is invoked on the peer * domain just before the mmWave link is started on the BSS. * * @param[in] ptrCalibrationCfg * Pointer to the calibration configuration * * @retval * Not applicable */ typedef void (*MMWave_startFxn)(MMWave_CalibrationCfg* ptrCalibrationCfg); /** * @b Description * @n * Application registered callback function which is invoked the mmWave link on BSS * has been stopped. This is applicable only for the XWR16xx/XWR18xx/XWR68xx. The BSS can be configured * only by the MSS *or* DSS. The callback API is triggered on the remote execution * domain (which did not configure the BSS) * * @retval * Not applicable */ typedef void (*MMWave_stopFxn)(void); /** * @brief * mmWave Handle */ typedef void* MMWave_Handle; /** * @brief * Execution Domain * * @details * Enumeration describes the execution domain for the mmWave */ typedef enum MMWave_Domain_e { /** * @brief The mmWave is executing in the MSS domain */ MMWave_Domain_MSS = 0x1, /** * @brief The mmWave is executing in the DSS domain */ MMWave_Domain_DSS = 0x2 }MMWave_Domain; /** * @brief * Configuration Mode * * @details * The mmWave API can be used in either of the following configuration * modes. */ typedef enum MMWave_ConfigurationMode_e { /** * @brief Minimal configuration: * * In this mode the mmWave is responsible for the following:- * - Setting up the mmWave Link Transport to the BSS * - Start/Stop/Synch capability with the BSS & DSS(if applicable) * - Asynch BSS Event notification to the peer domain (if applicable) * - mmWave Link initialization * - *No* dynamic memory allocation * * The application is responsible for the following:- * - Using the mmWave Link to configure the BSS * - Configuration management for the Profile/Chirp and Frame * - Sending messages to the peer domain (if applicable) * * This mode is useful for advanced users. */ MMWave_ConfigurationMode_MINIMAL = 0x1, /** * @brief Full configuration: * * In this mode the mmWave is responsible for the following:- * - Setting up the mmWave Link Transport to the BSS * - Start/Stop/Synch capability with the BSS & DSS (if applicable) * - Asynch BSS Event notification to the peer domain (if applicable) * - mmWave Link initialization * - Using the mmWave Link to configure the BSS * - Configuration management for the Profile/Chirp and Frame * - Sending messages to the peer domain (if applicable) * - Dynamic memory allocation * * The application is only responsible for tracking mmWave * handles. * * This mode is useful for basic users. */ MMWave_ConfigurationMode_FULL, }MMWave_ConfigurationMode; /** * @brief * Execution Mode * * @details * The enumeration is valid only for the XWR16xx/XWR18xx/XWR68xx and indicates if the * mmWave module is executing in isolation or cooperative mode. */ typedef enum MMWave_ExecutionMode_e { /** * @brief Isolation mode: In this mode the mmWave executes only on * the DSS or MSS. There is no exchange of the MMWave configuration or * events between the DSS or MSS. */ MMWave_ExecutionMode_ISOLATION = 0, /** * @brief Cooperative mode: In this mode the mmWave executes on both * the DSS and MSS. MMWave configuration and events are shared between * the mmWave execution domains. * * NOTE: In order for the DSS and MSS realms to communicate with each other * the mmWave uses the Mailbox driver with Virtual channel 7. Please ensure * that this virtual channel is not used for any other purpose. */ MMWave_ExecutionMode_COOPERATIVE }MMWave_ExecutionMode; /** * @brief * mmWave Link CRC configuration * * @details * The structure is used to describe the CRC configuration. The mmWaveLink messages * exchanged between the MSS/DSS and BSS have a checksum applied. The configuration * determines if the checksum computation is to use the CRC Driver *OR* should the * computation be done in the software. */ typedef struct MMWave_LinkCRCCfg_t { /** * @brief Flag which if set is used to indicate that the CRC driver is * to be used to perform the CRC computation */ uint8_t useCRCDriver; /** * @brief The field is valid only if the CRC Driver is being used else * this is ignored. */ CRC_Channel crcChannel; }MMWave_LinkCRCCfg; /** * @brief * mmWave Cooperative mode configuration * * @details * The structure is used to describe configuration supported if the mmWave * is executing in cooperative mode. In this mode each mmWave module domain * is capable of executing the mmWave API and is also responsible for notifying * its peer execution domain on the reception of configuration/events. */ typedef struct MMWave_CooperativeModeCfg_t { /** * @brief This is callback function which is invoked on the remote execution * domain once the mmWave link has been configured. * * *NOTE*: This is available only while operating in FULL configuration mode * If operating in MINIMAL configuration the application is responsible for * the configuration of the BSS using the link API and for passing this * information between the peer domains. */ MMWave_cfgFxn cfgFxn; /** * @brief This is callback function which is invoked on the remote execution * domain once the mmWave link has been opened. */ MMWave_openFxn openFxn; /** * @brief This is callback function which is invoked on the remote execution * domain once the mmWave link has been opened. */ MMWave_closeFxn closeFxn; /** * @brief This is callback function which is invoked on the remote execution * domain once the mmWave link has been started. */ MMWave_startFxn startFxn; /** * @brief This is callback function which is invoked on the remote execution * domain once the mmWave link has been stopped. */ MMWave_stopFxn stopFxn; }MMWave_CooperativeModeCfg; /** * @brief * Initial Configuration * * @details * The structure specifies the configuration which is required to initialize * and setup the mmWave module. */ typedef struct MMWave_InitCfg_t { /** * @brief Execution domain on which the mmWave module is executing. */ MMWave_Domain domain; /** * @brief Handle to the SOC Driver */ SOC_Handle socHandle; /** * @brief Application supplied asynchronous event handler. This is invoked * on the reception of an asynchronous event from the BSS */ MMWave_eventFxn eventFxn; /** * @brief mmWave link messages exchanged with the BSS have a checksum. The * configuration specifies if the CRC hardware *or* software to be used for * checksum calculation and validation. */ MMWave_LinkCRCCfg linkCRCCfg; /** * @brief Configuration Mode: Full or Minimal */ MMWave_ConfigurationMode cfgMode; /** * @brief The execution mode of the mmWave module. On the XWR16xx/XWR18xx/XWR68xx the mmWave module * could execute in either of the following modes:- * (a) [Isolation Mode]: Only on the DSS * (b) [Isolation Mode]: Only on the MSS * (c) [Cooperative Mode]: Control Path on DSS and Data Path on MSS * (d) [Cooperative Mode]: Control Path on MSS and Data Path on DSS */ MMWave_ExecutionMode executionMode; /** * @brief In cooperative mode: The mmWave module is executing on both the DSS * and MSS. The module is responsible for passing the configuration and async * events between the domains. */ MMWave_CooperativeModeCfg cooperativeModeCfg; }MMWave_InitCfg; /** @} */ /*********************************************************************************************** * mmWave Exported API: ***********************************************************************************************/ extern MMWave_Handle MMWave_init (MMWave_InitCfg* ptrCtrlInitCfg, int32_t* errCode); extern int32_t MMWave_deinit (MMWave_Handle mmWaveHandle, int32_t* errCode); extern int32_t MMWave_open (MMWave_Handle mmWaveHandle, const MMWave_OpenCfg* ptrOpenCfg, MMWave_CalibrationData *ptrCalibrationData, int32_t* errCode); extern int32_t MMWave_close(MMWave_Handle mmWaveHandle, int32_t* errCode); extern int32_t MMWave_sync (MMWave_Handle mmWaveHandle, int32_t* errCode); extern int32_t MMWave_config (MMWave_Handle mmWaveHandle, MMWave_CtrlCfg* ptrControlCfg, int32_t* errCode); extern int32_t MMWave_start (MMWave_Handle mmWaveHandle, const MMWave_CalibrationCfg* ptrCalibrationCfg, int32_t* errCode); extern int32_t MMWave_stop (MMWave_Handle mmWaveHandle, int32_t* errCode); extern int32_t MMWave_execute (MMWave_Handle mmWaveHandle, int32_t* errCode); /*********************************************************************************************** * Configuration Management API: Available in FULL configuration mode ***********************************************************************************************/ extern MMWave_ChirpHandle MMWave_addChirp (MMWave_ProfileHandle profileHandle, const rlChirpCfg_t* ptrChirpCfg, int32_t* errCode); extern int32_t MMWave_delChirp(MMWave_ProfileHandle profileHandle, MMWave_ChirpHandle chirpHandle, int32_t* errCode); extern int32_t MMWave_getChirpCfg(MMWave_ChirpHandle chirpHandle, rlChirpCfg_t* ptrChirpCfg,int32_t* errCode); extern MMWave_ProfileHandle MMWave_addProfile (MMWave_Handle mmWaveHandle, const rlProfileCfg_t* ptrProfileCfg, int32_t* errCode); extern int32_t MMWave_getNumProfiles(MMWave_Handle mmWaveHandle, uint32_t* numProfiles, int32_t* errCode); extern int32_t MMWave_getProfileHandle(MMWave_Handle mmWaveHandle,uint8_t profileId, MMWave_ProfileHandle* profileHandle,int32_t* errCode); extern int32_t MMWave_delProfile (MMWave_Handle mmWaveHandle,MMWave_ProfileHandle profileHandle, int32_t* errCode); extern int32_t MMWave_getProfileCfg (MMWave_ProfileHandle profileHandle, rlProfileCfg_t* ptrProfileCfg, int32_t* errCode); extern int32_t MMWave_getNumChirps(MMWave_ProfileHandle profileHandle, uint32_t* numChirps, int32_t* errCode); extern int32_t MMWave_getChirpHandle(MMWave_ProfileHandle profileHandle, uint32_t chirpIndex, MMWave_ChirpHandle* chirpHandle, int32_t* errCode); extern MMWave_BpmChirpHandle MMWave_addBpmChirp (MMWave_Handle mmWaveHandle, const rlBpmChirpCfg_t* ptrBpmChirp, int32_t* errCode); extern int32_t MMWave_getNumBpmChirp(MMWave_Handle mmWaveHandle, uint32_t* numBpmChirps, int32_t* errCode); extern int32_t MMWave_getBpmChirpHandle(MMWave_Handle mmWaveHandle,uint32_t bpmChirpIndex,MMWave_BpmChirpHandle* bpmChirpHandle,int32_t* errCode); extern int32_t MMWave_delBpmChirp (MMWave_Handle mmWaveHandle,MMWave_BpmChirpHandle bpmChirpHandle, int32_t* errCode); extern int32_t MMWave_getBpmChirpCfg (MMWave_BpmChirpHandle bpmChirpHandle, rlBpmChirpCfg_t* ptrBpmChirp, int32_t* errCode); extern int32_t MMWave_flushCfg(MMWave_Handle mmWaveHandle, int32_t* errCode); /* Error Management API: */ extern void MMWave_decodeError (int32_t errCode, MMWave_ErrorLevel* errorLevel, int16_t* mmWaveError, int16_t* subSysError); /** * @file dpm.h * * @brief * Data Path Manager * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage Data Path Manager (DPM) * * The DPM Module provides a well defined IPC mechanism which allows * application and data path processing chains (DPC) to communicate with * each other. The applications and DPC could be located on the same subsystem * or could be located on different subsystems. The DPM was designed * for the following:- * * 1. Modularity * The framework provides a clear demarcation between the application * code and the data path processing chain. * * 2. Simple Intuitive API * The framework exposes a set of standard well defined API which allows * application developers to load, configure and execute the processing * chain * * Data Path Processing Chain (DPC) can be defined as any execution block which * receives input data, processes it and generates an output. Example: * The Low Level processing chain can be defined as a a block which * receives ADC data and generate a point cloud. * * Except the XWR14xx all the other supported platforms have the DSS and MSS * subsystem. In most use cases the MSS is defined as a control domain while * the DSS actually executes the DPC. The DPM module provides an ability to * exchange configuration between the MSS and DSS via the IPC. Application and * DPC developers are thus abstracted from this complexity. * * ## Processing Chain Developers # * * The DPM can be used by developers to create their own processing chains * in which case please refer to the processing chain exported API * @sa DPM_PROCESSING_CHAIN_API * * ## Reporting # * * Application using the framework need to register a report function which receives * status reports from the framework module. This is an important feedback mechanism * through which the framework can keep the application informed about the status of * operations. For a list of all the reports @sa DPM_Report * * ## Domains # * * The DPM module introduces a concept of domains which identifies the extent to * which the Control and Data Path processing chains are distributed * * ### Local Domains # * * In the local domain the control and DPC are executing on the same subsystem. * * @image html local_domain.png * * ### Remote Domains # * * In the remote domain the control is executing on one subsystem while the DPC * is executing on another subsystem * * @image html remote_domain.png * * ### Distributed Domains # * * In the distributed domain the control is executing on one subsystem while the DPC * is executing on both the subsystems * * @image html distributed_domain.png * * ## Restrictions # * The DPM framework is currently limited to a single remote/distributed domain. * Multiple local domains can be instantiated without any issues. * * Due to memory consideration, DPM has IPC local queue set to @ref DPM_MAX_LOCAL_QUEUE. * * In remote/distributed domain setup, messages delivered through report function to MSS/DSS is not serialized. * Hence the order (MSS gets it first or DSS gets it first) cannot be guaranteed. */ /** @defgroup DPM DPM API */ /* mmWave SDK Include Files: */ /** @defgroup DPM_EXTERNAL_FUNCTION DPM External Functions @ingroup DPM @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup DPM_EXTERNAL_DATA_STRUCTURE DPM External Data Structures @ingroup DPM @brief * The section has a list of all the data structures which are exposed to the * application */ /** @defgroup DPM_EXTERNAL_DEFINITIONS DPM External Defintions @ingroup DPM @brief * The section has a list of all external definitions which are exposed by the * module. */ /** @defgroup DPM_COMMAND DPM Commands @ingroup DPM @brief * The section has a list of all commands which are supported by the DPM framework * These commands are always available and can be used irrespective of the DPC. */ /** @defgroup DPM_ERROR_CODE DPM Error Codes @ingroup DPM @brief * The section has a list of all the error codes which are generated by the module */ /** @defgroup DPM_INTERNAL_FUNCTION DPM Internal Functions @ingroup DPM @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup DPM_INTERNAL_DATA_STRUCTURE DPM Internal Data Structures @ingroup DPM @brief * The section has a list of all internal data structures which are used internally * by the module. */ /** @defgroup DPM_INTERNAL_DEFINITIONS DPM Internal Defintions @ingroup DPM @brief * The section has a list of all internal definitions which are used internally * by the module. */ /** @defgroup DPM_PROCESSING_CHAIN_API DPM Processing Chain API @ingroup DPM @brief * The section has a list of all function which need to be populated by a developers * writing a custom processing chain to fit in with the DPM framework */ /** @addtogroup DPM_ERROR_CODE * Base error code for the mmWave module is defined in the * \include ti/common/mmwave_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Not supported */ /** * @brief Error Code: Processing chain configuration error */ /** * @brief Error Code: Invalid IOCTL command passed to the processing * chain. Processing chain developers should set the error code to this * if the command during the configuration does not fall between the * supported range. */ /** @} */ /** @addtogroup DPM_EXTERNAL_DEFINITIONS @{ */ /** * @brief * This is the maximum length of the file name on assertion */ /** * @brief * This is the maximum size of the informational message block which can * be passed by the DPC to the application */ /** * @brief * This is the common definition for the maximum number of buffers which * can be exchanged by the application with the DPC */ /** * @brief This is the maximum size of DPC configuration data which can be * transported by the DPM module. */ /** @} */ /** @addtogroup DPM_COMMAND @{ */ /** * @brief * This is the command which can be used by the application to notify * the processing chain that buffers are available to be processed. * arg = &DPM_Buffer * argLen = sizeof (DPM_Buffer) * This will only notify the local processing chain and will * not relay the request to the remote or distributed domain. * * *NOTE*: Please refer to the DPC documentation on the exact format * of data which is to be passed. */ /** * @brief * This is the command which can be used by the application to inform the * module that there was a CPU/ESM fault reported by the mmWave link layer. * This is passed to the processing chain to take appropriate action. * arg = NULL * argLen = 0 */ /** * @brief * This is the command which can be used by the processing chain to inform * the application about a fault/exception which the chain encountered. * The application is notified about the assertion via the reporting API. * arg = &assert * argLen = sizeof (DPM_DPCAssert) * @sa * DPM_Report_DPC_ASSERT */ /** * @brief * This is a generic command which can be used by the processing chain to send * any custom information to the application. The payload is not interpreted by * the framework and is passed to the application via the reporting mechanism * arg = &info * argLen <= sizeof(DPM_DPCInfo) * @sa * DPM_Report_DPC_INFO */ /** * @brief * Processing chain specific command start index: Command Index before this * are reserved for use by the core Module. All processing chains should use * this as a starting index for their own custom commmands. */ /** @} */ /** @addtogroup DPM_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief * DPM Handle */ typedef void* DPM_Handle; /** * @brief * DPM Processing Chain Handle */ typedef void* DPM_DPCHandle; /** * @brief * DPM Data Path Domain * * @details * The enumeration is used to describe the domains to which the data path * processing chains extend. */ typedef enum DPM_Domain_e { /** * @brief Localized Domain: The Control & Data Path chain * is executed in the context of single subsystem i.e. MSS * or DSS only. * */ DPM_Domain_LOCALIZED = 0x1, /** * @brief Remote Domain: The DPM Data Path Processing chain * is executed in the context of single subsystem i.e. MSS or DSS only. * However the DPM control can be executed from another subsystem. * * For example: On the XWR16xx the MSS could be controlling the DPM * while the data processing chain is entirely executing on the DSS */ DPM_Domain_REMOTE, /** * @brief Distributed Domain: The DPM Data Path Processing chain * is executed in the context of multiple subsystems. The DPM control * can be executed from either subsystem */ DPM_Domain_DISTRIBUTED }DPM_Domain; /** * @brief * Report Types * * @details * The enumeration is used to describe the various reports which are generated * by the Module. Applications are notified about the operational status * of the Module through these reports via the registered Reporting Function. * Applications are expected to interpret these reports and take appropriate * action. */ typedef enum DPM_Report_e { /** * @brief This is the report type to indicate that the processing chain * has been started. * * Argument | Value | Description * ---------|--------------|------------ * arg0 | 0 | Not Used * arg1 | 0 | Not Used * * This report is issued to all DPM entities * * Once the processing chain has been successfully started the application can start * the BSS via the MMWave API * * @ref DPM_start */ DPM_Report_DPC_STARTED = 0x1, /** * @brief This is the report type to indicate that the processing chain has * been stopped. * * Argument | Value | Description * ---------|--------------|------------ * arg0 | 0 | Not Used * arg1 | 0 | Not Used * * This report is issued to all DPM entities * * @ref DPM_stop */ DPM_Report_DPC_STOPPED, /** * @brief This is the report type to indicate that the processing chain * executing has detected a fault/exception * * Argument | Value | Description * ---------|----------------------|------------ * arg0 | &DPM_DPCAssert | Address of the assert information * arg1 | 0 | Not Used * * This report is issued to all DPM entities * * @ref DPM_DPCAssert */ DPM_Report_DPC_ASSERT, /** * @brief This is the report type to indicate that the processing chain * is being configured via the DPM_ioctl interface. The following is the * interpretation of the optional arguments:- * * Argument | Value | Description * ---------|-----------------------|------------ * arg0 | Command | Standard/DPC specific commands * arg1 | Command Specific Data | Refer to the command documentation * * This report is issued to all DPM entities * * @ref DPM_ioctl */ DPM_Report_IOCTL, /** * @brief This is the report type to indicate that the processing * chain has results which are available. * * Argument | Value | Description * ---------|-----------------------|------------ * arg0 | &DPM_Buffer | Address of the DPM Result * arg1 | 0 | Not Used * * This report is issued only to the remote DPM entity on which the DPC * is *not* executing. * * @ref DPM_Buffer */ DPM_Report_NOTIFY_DPC_RESULT, /** * @brief This is the report type to indicate that the remote DPM domain * has acknowledged the DPC results. * * Argument | Value | Description * ---------|-----------------------|------------ * arg0 | &DPM_Buffer | Address of the DPM Result * arg1 | 0 | Not Used * * This report is issued only to the DPM entity on which the DPC is executing. * * This is an acknowledgment that the results have been passed to the remote DPM * domain. This report is only generated if the "isAckNeeded" flag is set. * * @ref DPM_Buffer */ DPM_Report_NOTIFY_DPC_RESULT_ACKED, /** * @brief This is the report type to indicate that the DPC has passed * information to the application. Application developers would need to read * the processing chain specific documentation to interpret this information. * * Argument | Value | Description * ---------|------------------|------------ * arg0 | &DPM_DPCInfo | DPC Specific information * arg1 | 0 | Not Used * * This report is issued to all DPM entities. * * @ref DPM_DPCInfo */ DPM_Report_DPC_INFO }DPM_Report; /** * @b Description * @n * Applications can register a report function which is invoked by the module * to report the status of the processing chain to the application. The mechanism * can be used to inform the applications about the status of the processing chain. * * @param[in] reportType * Report Type * @param[in] instanceId * DPM Instance Identifier which generated the response. * @param[in] errCode * Error code associated with the status event. This will be set to 0 to indicate * that the report was successful. * @param[in] arg0 * Optional argument. * @param[in] arg1 * Optional argument. * * *NOTE*: Please refer to the @ref DPM_Report for more information * about the optional arguments and how to interpret them. * * @retval * Not applicable */ typedef void (*DPM_ReportFxn) (DPM_Report reportType, uint32_t instanceId, int32_t errCode, uint32_t arg0, uint32_t arg1); /** * @brief * Processing Chain Assert * * @details * Processing chains while executing on a core can encounter a fatal error. * In such a scenario the DPM entities would need to be notified * with information relevant to the error. The assertion information * block here can be exchanged */ typedef struct DPM_DPCAssert_t { /** * @brief Line Number: */ uint32_t lineNum; /** * @brief File Name: */ char fileName[32]; /** * @brief Processing Chain specific argument1 */ uint32_t arg0; /** * @brief Processing Chain specific argument2 */ uint32_t arg1; }DPM_DPCAssert; /** * @brief * Data Path Processing Chain Information * * @details * Processing Chain specific information which can be passed by DPC * developers to the application. The DPM Module does not define this * information but is DPC specific. Please refer to the DPC documentation * on how this information is interpreted. */ typedef struct DPM_DPCInfo_t { /** * @brief DPC Developers can populate the informational block * with custom information and can use the DPM to send this to * the application. Application are notified via the reporting mechanism */ uint8_t info[64]; }DPM_DPCInfo; /** * @brief * Initialization configuration * * @details * The structure is used to initialize the DPM module */ typedef struct DPM_InitCfg_t { /** * @brief Handle to the SOC Driver */ SOC_Handle socHandle; /** * @brief Execution domain. */ DPM_Domain domain; /** * @brief Each DPM Instance should be allocated a unique identifier * This will be reported to the application through the reporting mechanism * Unique DPM Instance identifiers are especially useful if operating in a * Distributed domain mode. */ uint32_t instanceId; /** * @brief This is an argument which is passed to the processing chain * during initialization. The DPM framework does not interpret this and * passes this as is to the processing chain. For more information please * refer to the processing chain documentation. */ void* arg; /** * @brief This is the size of the argument specified above. This is not * used by the DPM framework but is passed as is to the processing chain. * For more information please refer to the processing chain documentation. */ uint32_t argSize; /** * @brief Pointer to the processing configuration which is to be loaded * and executed in the DPM Instance. */ struct DPM_ProcChainCfg_t* ptrProcChainCfg; /** * @brief Report Function: The DPM module will invoke the application * registered function to report events and status about the processing * chain */ DPM_ReportFxn reportFxn; }DPM_InitCfg; /** * @brief * DPM Buffer Interface * * @details * The DPM processing chain receive data buffers which are to be * processed. The DPC processes these buffers and generates * the results which are then passed to the application. The structure * encompasses this information. */ typedef struct DPM_Buffer_t { /** * @brief Pointer to the buffer */ uint8_t* ptrBuffer[3]; /** * @brief Size of the result buffer */ uint32_t size[3]; }DPM_Buffer; /** * @b Description * @n * This is the DPC registered callback function which is * can be used to pass input data to the processing chain to be processed. * The format of the actual data buffers is DPC specific. * * This function could be invoked from any execution context. It could * be triggered by the application from an ISR or from another thread. * Internally the DPM will notify the processing chain immediately about * the buffer availability. DPC developers could either consume the buffer * immediately or could process it in the DPM Framework execution context * * @param[in] handle * Handle to the DPC * @param[in] ptrBuffer * Pointer to the data buffer * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - 0 * @retval * Error - one of @ref DPM_ERROR_CODE */ typedef int32_t (*DPM_ProcChainInjectDataFxn) (DPM_DPCHandle handle, DPM_Buffer* ptrBuffer); /** * @b Description * @n * This is the DPC registered function which is invoked once the * chirp available interrupt has been detected. * * This is a special case inject data function which indicates that * chirp data is available. This is always invoked in ISR context. * * @param[in] handle * Handle to the DPC * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Not applicable */ typedef void (*DPM_ProcChainChirpAvailableCallbackFxn) (DPM_DPCHandle handle); /** * @b Description * @n * This is the DPC registered function which is invoked once the * frame start interrupt has been detected * * @param[in] handle * Handle to the DPC * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Not applicable */ typedef void (*DPM_ProcChainFrameStartCallbackFxn) (DPM_DPCHandle handle); /** * @b Description * @n * This is the DPC registered function which is used to initialize * and setup the processing chain. This is invoked during the DPM * Initialization process. * * @param[in] dpmHandle * Handle to the DPM Module * @param[in] ptrInitCfg * Pointer to the initialization configuration * @param[out] errCode * Error code populated by the API * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - DPC Handle * @retval * Error - NULL */ typedef DPM_DPCHandle (*DPM_ProcChainInitFxn) (DPM_Handle dpmHandle, DPM_InitCfg* ptrInitCfg, int32_t* errCode); /** * @b Description * @n * This is the DPC registered function which is used to execute the processing * chain. * * @param[in] handle * DPC Handle * @param[out] ptrResult * Pointer to the result populated by the processing chain. * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - 0 * @retval * Error - one of @ref DPM_ERROR_CODE */ typedef int32_t (*DPM_ProcChainExecuteFxn) (DPM_DPCHandle handle, DPM_Buffer* ptrResult); /** * @b Description * @n * This is the DPC registered function which is used to configure the processing * chain. DPC developers can use this to provide the ability to provide additional * control capability. * * NOTE: Processing Chain developers should ensure that the custom commands be offset * by DPM_CMD_DPC_START_INDEX. This will ensure that there is no overlap * with the standard DPM framework provided commands. If the command provided * to the DPC is not within range; the DPC chain should return an error * with the error code set to DPM_EINVCMD. * * In addition to the DPC specific commands the following commands should also * be handled by the processing chain developers: * @sa DPM_CMD_BSS_FAULT * * @param[in] handle * DPC handle * @param[in] cmd * Command to be processed * @param[in] arg * Command specific argument. * @param[in] argLen * Command specific argument length * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - 0 * @retval * Error - one of @ref DPM_ERROR_CODE */ typedef int32_t (*DPM_ProcChainIoctlFxn) (DPM_DPCHandle handle, uint32_t cmd, void* arg, uint32_t argLen); /** * @b Description * @n * This is the DPC registered function which is used to start the processing * chain. * * @param[in] handle * DPC handle * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - 0 * @retval * Error - one of @ref DPM_ERROR_CODE */ typedef int32_t (*DPM_ProcChainStartFxn) (DPM_DPCHandle handle); /** * @b Description * @n * This is the DPC registered function which is used to stop the processing chain. * * @param[in] handle * DPC handle * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - 0 * @retval * Error - one of @ref DPM_ERROR_CODE */ typedef int32_t (*DPM_ProcChainStopFxn) (DPM_DPCHandle handle); /** * @b Description * @n * This is the DPC registered function which is used to deinitialize the processing * chain and is invoked during the DPM Deinitialization process. * * @param[in] handle * DPC handle * * \ingroup DPM_PROCESSING_CHAIN_API * * @retval * Success - 0 * @retval * Error - one of @ref DPM_ERROR_CODE */ typedef int32_t (*DPM_ProcChainDeinitFxn) (DPM_DPCHandle handle); /** * @brief * Processing Chain Configuration * * @details * The DPM module is responsible for the registeration and execution of * processing chains. Processing Chains can be created and registered by * populating the following configuration */ typedef struct DPM_ProcChainCfg_t { /** * @brief Initialization function: */ DPM_ProcChainInitFxn initFxn; /** * @brief Start function: */ DPM_ProcChainStartFxn startFxn; /** * @brief Execute function: */ DPM_ProcChainExecuteFxn executeFxn; /** * @brief IOCTL function: */ DPM_ProcChainIoctlFxn ioctlFxn; /** * @brief Stop function: */ DPM_ProcChainStopFxn stopFxn; /** * @brief Deinitialization function: */ DPM_ProcChainDeinitFxn deinitFxn; /** * @brief [Optional] Inject Data Function: */ DPM_ProcChainInjectDataFxn injectDataFxn; /** * @brief [Optional] Chirp Available Callback function: */ DPM_ProcChainChirpAvailableCallbackFxn chirpAvailableFxn; /** * @brief [Optional] Frame Start Callback function: */ DPM_ProcChainFrameStartCallbackFxn frameStartFxn; }DPM_ProcChainCfg; /** @} */ /*********************************************************************************************** * DPM Exported API: ***********************************************************************************************/ extern DPM_Handle DPM_init (DPM_InitCfg* ptrInitCfg, int32_t* errCode); extern int32_t DPM_synch (DPM_Handle handle, int32_t* errCode); extern int32_t DPM_ioctl (DPM_Handle handle, uint32_t cmd, void* arg, uint32_t argLen); extern int32_t DPM_start (DPM_Handle handle); extern int32_t DPM_stop (DPM_Handle handle); extern int32_t DPM_execute (DPM_Handle handle, DPM_Buffer* ptrResult); extern int32_t DPM_sendResult (DPM_Handle handle, _Bool isAckNeeded, DPM_Buffer* ptrResult); extern int32_t DPM_relayResult (DPM_Handle handle, DPM_DPCHandle dpcHandle, DPM_Buffer* ptrResult); extern int32_t DPM_notifyExecute (DPM_Handle handle, DPM_DPCHandle dpcHandle, _Bool isrContext); extern int32_t DPM_deinit (DPM_Handle handle); /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @defgroup DEBUGP_OSAL DebugP OSAL Porting Layer * * @brief Debug support * * The DebugP module allows application to do logging and assert checking. * * DebugP_assert calls can be added into code. If the code * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a * non-zero value, the call is passed onto the underlying assert checking. * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are * resolved to nothing. * * This module sits on top of the assert checking of the underlying * RTOS. Please refer to the underlying RTOS port implementation for * more details. * * Similarly, DebugP_logN calls can be added into code. If the code * is compiled with the compiler define DebugP_LOG_ENABLED set to a * non-zero value, the call is passed onto the underlying assert checking. * If DebugP_LOG_ENABLED is zero (or not defined), the calls are * resolved to nothing. * This module sits on top of the logging of the underlying * RTOS. Please refer to the underlying RTOS port implementation for * more details. */ /** @defgroup DEBUGP_OSAL_EXTERNAL_FUNCTION DebugP OSAL External Functions @ingroup DEBUGP_OSAL @brief * The section documents the external API exposed by the OSAL Porting layer. */ /** @defgroup DEBUGP_OSAL_DEFINTIONS DebugP OSAL Defintions @ingroup DEBUGP_OSAL @brief * The section has a list of all the definitions which are exposed to the developers */ /** @addtogroup DEBUGP_OSAL_DEFINTIONS @{ */ /*! * @brief Assert Enabled * * The defintion is used to control the feature if assertions are to be enabled * or not. This flag can be enabled for debug builds by changing the file *OR* * through the makefile. */ /*! * @brief Log Enabled * * The defintion is used to plug the logging API to the OS provided logging mechansim * Application developers can port the backend Logging API as per their requirements */ /** @} */ /*! * @brief Assert checking function * * If the expression is evaluated to true, the API does nothing. * If it is evaluated to false, the underlying RTOS port implementation * handles the assert via its mechanisms. * * @param expression Expression to evaluate * * \ingroup DEBUGP_OSAL_EXTERNAL_FUNCTION */ extern void _DebugP_assert(int expression, const char *file, int line); /*! * @brief Debug log function with 0 parameters * * The underlying RTOS port implementation handles the * logging via its mechanisms. * * @param format "printf" format string * * @sa DebugP_LOG_ENABLED * * \ingroup DEBUGP_OSAL_EXTERNAL_FUNCTION */ /*! * @brief Debug log function with 1 parameters * * The underlying RTOS port implementation handles the * logging via its mechanisms. * * @param format "printf" format string * @param p1 first parameter to format string * * \ingroup DEBUGP_OSAL_EXTERNAL_FUNCTION */ /*! * @brief Debug log function with 2 parameters * * The underlying RTOS port implementation handles the * logging via its mechanisms. * * @param format "printf" format string * @param p1 first parameter to format string * @param p2 second parameter to format string * * \ingroup DEBUGP_OSAL_EXTERNAL_FUNCTION */ /*! * @brief Debug log function with 3 parameters * * The underlying RTOS port implementation handles the * logging via its mechanisms. * * @param format "printf" format string * @param p1 first parameter to format string * @param p2 second parameter to format string * @param p3 third parameter to format string * * \ingroup DEBUGP_OSAL_EXTERNAL_FUNCTION */ /*! * @brief Debug log function with 4 parameters * * The underlying RTOS port implementation handles the * logging via its mechanisms. * * @param format "printf" format string * @param p1 first parameter to format string * @param p2 second parameter to format string * @param p3 third parameter to format string * @param p4 fourth parameter to format string * * \ingroup DEBUGP_OSAL_EXTERNAL_FUNCTION */ /** * @file UART.h * * @brief * This is the header file for the UART driver which exposes the * data structures and exported API which can be used by the * applications to use the UART driver. * * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage UART Driver * * The UART header file should be included in an application as follows: * @code #include @endcode * * The uart/include/reg_sci.h has the register layer definitons for the * UART SCI Module. * * ## Link Requirements # * The UART driver interface module is joined (at link time) to a * NULL-terminated array of UART_Config data structures named *UART_config*. * *UART_config* is implemented in the application with each entry being an * instance of a UART peripheral. Each entry in *UART_config* contains a: * - (UART_FxnTable *) to a set of functions that implement a UART peripheral * - (void *) data object that is associated with the UART_FxnTable * - (void *) hardware attributes that are associated with the UART_FxnTable * * There is a platform specific UART file present in the *ti/drivers/uart/platform* * directory. This file is built as a part of the UART Library for the specific * platform. * * ## Opening the driver # * * @code UART_Handle handle; UART_Params params; UART_Params_init(¶ms); params.baudRate = someNewBaudRate; params.writeDataMode = UART_DATA_BINARY; params.readDataMode = UART_DATA_BINARY; params.readReturnMode = UART_RETURN_FULL; params.readEcho = UART_ECHO_OFF; handle = UART_open(someUART_configIndexValue, ¶ms); if (!handle) { // Error: Unable to open the UART } @endcode * * ## Writing data # * * @code const unsigned char hello[] = "Hello World\n"; ret = UART_write(handle, hello, sizeof(hello)); @endcode * * ## Reading data # * * @code unsigned char rxBuffer[20]; ret = UART_read(handle, rxBuffer, sizeof(rxBuffer)); @endcode * * ## DMA Interface # * The UART driver can be hooked up with the DMA (MSS)/EDMA (DSS). In this case * case the read & write operations are done using the DMA/EDMA blocks. This would * make the UART driver require the DMA or EDMA drivers. On memory constrained * system this might not be acceptable; in which case the driver also provides a * default no-DMA layer. In order to use this please modify the hardware attributes * 'gUartSciHwCfg' defined in the platform specific file and replace the DMA functions * with the no-DMA variants. * * @sa * UartSci_noDMAIsDMAEnabled * UartSci_noDMAOpen * UartSci_noDMAClose * UartSci_noDMAInitiateRxDMA * UartSci_noDMAInitiateTxDMA * * Please rebuild the driver after this modification. * * While using the DMA interface in the read mode please be aware that the function * UART_read/UART_readPolling always operate in UART_RETURN_FULL mode. */ /** @defgroup UART_DRIVER UART Driver */ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @file dma.h * * @brief DMA driver interface * */ /** @mainpage DMA Driver * * The DMA driver provides functionaity to copy data around from one memory location * to the other using hardware thereby offloading the operation from CPU. * * The DMA header file should be included in an application as follows: * @code * #include * @endcode * * ## Initializing the driver # * The DMA Driver needs to be initialized once across the System. This is * done using the #DMA_init. None of the DMA API can be used without invoking * this API * * ## Opening the driver # * Once the DMA Driver has been initialized; the DMA Driver instance can be opened * using the #DMA_open. The helper function #DMA_Params_init can be used to * populate the default parameters. The #DMA_open can be called multiple times from different * context to obtain a valid DMA handle. However, only the first call to #DMA_open will * perform the hardware initialization. Other subsequent calls will just return the already * opened handle. * * @code * @endcode * * ## Using the driver # * Following is a psuedo code for using the DMA driver in software trigger mode * to copy 4 8-bit data at a time and repeat it for 10 times with PostIncrement addressing mode. * * @code * DMA_Params params; DMA_Handle handle; DMA_init(); DMA_Params_init(¶ms); handle = DMA_open(0, ¶ms, &errCode); // set the channel paramters ctrlPacket.srcAddr=(uint32_t)gDMATestSource; ctrlPacket.destAddr=(uint32_t)gDMATestDest; ctrlPacket.frameXferCnt=10; ctrlPacket.elemXferCnt=4; ctrlPacket.nextChannel=DMA_CHANNEL_NONE; ctrlPacket.srcElemSize=DMA_ElemSize_8bit; ctrlPacket.destElemSize=DMA_ElemSize_8bit; ctrlPacket.autoInitiation=0; ctrlPacket.xferType=DMA_XferType_Frame; ctrlPacket.srcAddrMode=DMA_AddrMode_PostIncrement; ctrlPacket.destAddrMode=DMA_AddrMode_PostIncrement; DMA_setChannelParams(handle, dmaChannelNum,&ctrlPacket); // enable completion Interrupt and provide a callback function DMA_enableInterrupt(handle,dmaChannelNum,DMA_IntType_FTC,DMA_TestInterruptCb,(void *)dmaTestContext); if (hardwareTriggered) { // if channel is to be hardware triggered, DMA_assignChannel() API need to be called // to hook up H/W request line to the channel DMA_assignChannel(handle,dmaChannelNum,dmaReqline,errCode); // enable the channel DMA_enableChannel(handle,dmaChannelNum,DMA_ChTriggerType_HW); } else { // enable the channel for software trigger DMA_enableChannel(handle,dmaChannelNum,DMA_ChTriggerType_SW); } // // // wait for DMA completion interrupt // // //Time to tear down when job is complete //disable interrupt DMA_disableInterrupt (handle,dmaChannelNum,DMA_IntType_FTC); // disable channel if (hardwareTriggered) { // if channel was hardware triggered, free the channel from h/w req line hook up DMA_freeChannel (handle, dmaChannelNum,dmaReqline); // disable the channel DMA_disableChannel(handle,dmaChannelNum,DMA_ChTriggerType_HW); } else { // disable the channel for software trigger DMA_disableChannel(handle,dmaChannelNum,DMA_ChTriggerType_SW); } // Close the driver errCode = DMA_close(handle); * @endcode * ## Instrumentation # * Uses DebugP_log functions for debug messages * * ## Hardware Register Map # * The hardware register map used by this driver can be found at include/reg_dma.h and reg_dmaram.h * * ============================================================================ */ /** @defgroup DMA_DRIVER_EXTERNAL_FUNCTION DMA Driver External Functions @ingroup DMA_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup DMA_DRIVER_EXTERNAL_DATA_STRUCTURE DMA Driver External Data Structures @ingroup DMA_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DMA_DRIVER_ERROR_CODE DMA Driver Error Codes @ingroup DMA_DRIVER @brief * The section has a list of all the error codes which are generated by the DMA Driver * module */ /** @addtogroup DMA_DRIVER_ERROR_CODE * * @brief * Base error code for the DMA module is defined in the ti/common/mmwave_error.h * \include ti/common/mmwave_error.h * @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Operation cannot be done as DMA_init is not done. */ /** * @brief Error Code: input argument out of range */ /** * @brief Error Code: input argument out of range */ /** * @brief Error Code: feature not supported */ /** * @brief Error Code: channel or resource in use */ /** * @brief Error Code: channel or resource in use */ /** * @brief Error Code: Polling and Interrupts are mutually exclusive */ /** @}*/ /** @addtogroup DMA_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /*! * @brief Define for an unspecified channel. */ /*! * @brief A handle that is returned from a DMA_open() call. */ typedef void* DMA_Handle; /*! * @brief DMA Interrupt Type * * Enum for DMA Interrupt type. * */ typedef enum DMA_IntType_e { DMA_IntType_FTC = 0U, /*! naming * convention.
* Commands supported by UART*.h follow a UART*_CMD_\ naming * convention.
* Each control command defines @b arg differently. The types of @b arg are * documented with each command. * * See @ref UART_CMD "UART_control command codes" for command codes. * * See @ref UART_DRIVER_ERROR_CODE "UART_control return status codes" for status codes. * * @pre UART_open() has to be called. * * @param handle A UART handle returned from UART_open() * * @param cmd UART.h or UART*.h commands. * * @param arg An optional R/W (read/write) command argument * accompanied with cmd * * @return Implementation specific return codes. Negative values indicate * unsuccessful operations. * * @sa UART_open() * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern int32_t UART_control(UART_Handle handle, uint32_t cmd, void *arg); /*! * @brief Function to initialize the UART module * * @pre The UART_config structure must exist and be persistent before this * function can be called. This function must also be called before * any other UART driver APIs. * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern void UART_init(void); /*! * @brief Function to initialize a given UART peripheral * * Function to initialize a given UART peripheral specified by the * particular index value. * * @pre UART_init() has been called * * @param index Logical peripheral number for the UART indexed into * the UART_config table * * @param params Pointer to a parameter block. If NULL, default * parameter values will be used. All the fields in * this structure are RO (read-only). * * @return A UART_Handle upon success. NULL if an error occurs, or if the * indexed UART peripheral is already opened. * * @sa UART_init() * @sa UART_close() * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern UART_Handle UART_open(uint32_t index, UART_Params *params); /*! * @brief Function to initialize the UART_Params struct to its defaults * * @param params An pointer to UART_Params structure for * initialization * * Defaults values are: * readTimeout = UART_WAIT_FOREVER; * writeTimeout = UART_WAIT_FOREVER; * readReturnMode = UART_RETURN_NEWLINE; * readDataMode = UART_DATA_TEXT; * writeDataMode = UART_DATA_TEXT; * readEcho = UART_ECHO_ON; * baudRate = 115200; * dataLength = UART_LEN_8; * stopBits = UART_STOP_ONE; * parityType = UART_PAR_NONE; * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern void UART_Params_init(UART_Params *params); /*! * @brief Function that writes data to a UART with interrupts enabled. Usage * of this API is mutually exclusive with usage of * UART_writePolling(). In other words, for an opened UART peripheral, * either UART_write() or UART_writePolling() may be used, but not * both. * * In UART_MODE_BLOCKING, UART_write() will block task execution until all * the data in buffer has been written. * * @sa UART_writePolling() * * @param handle A UART_Handle * * @param buffer A WO (write-only) pointer to buffer containing data to * be written to the UART. * * @param size The number of bytes in the buffer that should be written * to the UART. * * @return Returns the number of bytes that have been written to the UART. * If an error occurs, one of the UART Error codes is returned. * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern int32_t UART_write(UART_Handle handle, uint8_t *buffer, uint32_t size); /*! * @brief Function that writes data to a UART, polling the peripheral to * wait until new data can be written. Usage of this API is mutually * exclusive with usage of UART_write(). * * This function initiates an operation to write data to a UART controller. * * UART_writePolling() will not return until all the data was written to the * UART (or to its FIFO if applicable). * * @sa UART_write() * * @param handle A UART_Handle * * @param buffer A pointer to the buffer containing the data to * be written to the UART. * * @param size The number of bytes in the buffer that should be written * to the UART. * * @return Returns the number of bytes that have been written to the UART. * If an error occurs, one of the UART Error codes is returned. * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern int32_t UART_writePolling(UART_Handle handle, uint8_t *buffer, uint32_t size); /*! * @brief Function that cancels a UART_write() function call. * * This function cancels a UART_write() operation to a UART peripheral. * * @param handle A UART_Handle * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern void UART_writeCancel(UART_Handle handle); /*! * @brief Function that reads data from a UART with interrupt enabled. This * API must be used mutually exclusive with UART_readPolling(). * * This function initiates an operation to read data from a UART controller. * * In UART_MODE_BLOCKING, UART_read() will block task execution until all * the data in buffer has been read. * * @sa UART_readPolling() * * @param handle A UART_Handle * * @param buffer A RO (read-only) pointer to an empty buffer in which * received data should be written to. * * @param size The number of bytes to be written into buffer * * @return Returns the number of bytes that have been read from the UART, * one of the UART Error codes on an error. * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern int32_t UART_read(UART_Handle handle, uint8_t *buffer, uint32_t size); /*! * @brief Function that reads data from a UART without interrupts. This API * must be used mutually exclusive with UART_read(). * * This function initiates an operation to read data from a UART peripheral. * * UART_readPolling will not return until size data was read to the UART. * * @sa UART_read() * * @param handle A UART_Handle * * @param buffer A RO (read-only) pointer to an empty buffer in which * received data should be written to. * * @param size The number of bytes to be written into buffer * * @return Returns the number of bytes that have been read from the UART, * one of the UART Error codes on an error. * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern int32_t UART_readPolling(UART_Handle handle, uint8_t *buffer, uint32_t size); /*! * @brief Function that cancels a UART_read() function call. * This function cancels a UART_read() operation for a UART peripheral. * * @param handle A UART_Handle * * \ingroup UART_DRIVER_EXTERNAL_FUNCTION */ extern void UART_readCancel(UART_Handle handle); /** * @file cli.h * * @brief * This is the main header file for the CLI * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage CLI Utility * * The CLI utility library provides a simple CLI console over the specified * serial port. * * The CLI library provides the following features: * - Simple command parser * - Applications can register their own custom commands * - mmWave Extension support which handles the well defined mmWave control * commands. * * The CLI header file should be included in an application as follows: * @code #include @endcode * * The CLI library provides an mmWave extension library which provides predefined * CLI command handlers for the mmWave configuration commands. The mmWave configuration * is stored internally and an application can use #CLI_getMMWaveExtensionConfig * to get a copy of this configuration. This can then be used to configure the mmWave */ /** @defgroup CLI_UTIL CLI Utility */ /* mmWave SDK Include Files: */ /** @defgroup CLI_UTIL_EXTERNAL_FUNCTION CLI Utility External Functions @ingroup CLI_UTIL @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup CLI_UTIL_EXTERNAL_DATA_STRUCTURE CLI Utility External Data Structures @ingroup CLI_UTIL @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup CLI_UTIL_EXTERNAL_DEFINITION CLI Utility External Definitions @ingroup CLI_UTIL @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup CLI_UTIL_INTERNAL_FUNCTION CLI Utility Internal Functions @ingroup CLI_UTIL @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup CLI_UTIL_INTERNAL_DATA_STRUCTURE CLI Utility Internal Data Structures @ingroup CLI_UTIL @brief * The section has a list of all internal data structures which are used internally * by the CLI module. */ /************************************************************************** ************************* CLI Module Definitions ************************* **************************************************************************/ /** @addtogroup CLI_UTIL_EXTERNAL_DEFINITION @{ */ /** * @brief This is the maximum number of CLI commands which are supported */ /** * @brief * This is the maximum number of CLI arguments which can be passed to a * command. */ /** @} */ /************************************************************************** ************************** CLI Data Structures *************************** **************************************************************************/ /** @addtogroup CLI_UTIL_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief Handle to the CLI module: */ typedef void* CLI_Handle; /** * @brief CLI command handler: * * @param[in] argc * Number of arguments * @param[in] argv * Pointer to the arguments * * @retval * Success - 0 * @retval * Error - <0 */ typedef int32_t (*CLI_CmdHandler)(int32_t argc, char* argv[]); /** * @brief * CLI command table entry * * @details * This is command entry which holds information which maps a * command string to the corresponding command handler. */ typedef struct CLI_CmdTableEntry_t { /** * @brief Command string */ char* cmd; /** * @brief CLI Command Help string */ char* helpString; /** * @brief Command Handler to be executed */ CLI_CmdHandler cmdHandlerFxn; }CLI_CmdTableEntry; /** * @brief * CLI configuration * * @details * This is the configuration structure which is used to initialize and open * the CLI module. */ typedef struct CLI_Cfg_t { /** * @brief CLI Prompt string (if any to be displayed) */ char* cliPrompt; /** * @brief Optional banner string if any to be displayed on startup of the CLI */ char* cliBanner; /** * @brief UART Command Handle used by the CLI */ UART_Handle cliUartHandle; /** * @brief The CLI has an mmWave extension which can be enabled by this * field. The extension supports the well define mmWave link CLI command(s) * In order to use the extension the application should have initialized * and setup the mmWave. */ uint8_t enableMMWaveExtension; /** * @brief The SOC driver handle is used to acquire device part number */ SOC_Handle socHandle; /** * @brief The mmWave control handle which needs to be specified if * the mmWave extensions are being used. The CLI Utility works only * in the FULL configuration mode. If the handle is opened in * MINIMAL configuration mode the CLI mmWave extension will fail */ MMWave_Handle mmWaveHandle; /** * @brief Task Priority: The CLI executes in the context of a task * which executes with this priority */ uint8_t taskPriority; /** * @brief Flag which determines if the CLI Write should use the UART * in polled or blocking mode. */ _Bool usePolledMode; /** * @brief Flag which determines if the CLI should override the platform * string reported in @ref CLI_MMWaveVersion. */ _Bool overridePlatform; /** * @brief Optional platform string to be used in @ref CLI_MMWaveVersion */ char* overridePlatformString; /** * @brief This is the table which specifies the supported CLI commands */ CLI_CmdTableEntry tableEntry[32]; }CLI_Cfg; /** @} */ /************************************************************************** *************************** Extern Definitions *************************** **************************************************************************/ extern int32_t CLI_open (CLI_Cfg* ptrCLICfg); extern void CLI_write (const char* format, ...); extern int32_t CLI_close (void); extern void CLI_getMMWaveExtensionConfig(MMWave_CtrlCfg* ptrCtrlCfg); extern void CLI_getMMWaveExtensionOpenConfig(MMWave_OpenCfg* ptrOpenCfg); /************************************************************************** * @file mathutils.h * * @brief * This file contains math utility functions. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @defgroup MATHUTILS_EXTERNAL_FUNCTION Math Utility External Functions @ingroup RANGE_PROC_DPU @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the mathUtils */ /*! PI constant */ /** * @defgroup FFT_WINDOW_TYPES FFT_WINDOW_TYPES * @brief FFT Window Types supptored in mathutils library * @{ */ /*! @brief Hanning window */ /*! @brief Blackman window */ /*! @brief Rectangular window */ /** @}*/ /*FFT_WINDOW_TYPES*/ /*! Macro to round up input x to the nearest specified multiple m. * e.g if x = 13 and m = 5 then it returns 15. Input must be an unsigned type */ /*! Round macro used to round float to integer, integer can be any size depending * on usage e.g float y = 2.7; int32_t x = (int32_t)MATHUTILS_ROUND_FLOAT(y), x will be 3 */ /*! Saturate to 16-bit high macro. Usage y = MATHUTILS_SATURATE16_HIGH(x) */ /*! Saturate to 16-bit Low macro. Usage y = MATHUTILS_SATURATE16_HIGH(x) */ /*! Saturate to 16-bit macro. Usage MATHUTILS_SATURATE16(x), saturates x back to x */ /*! Rounding to Q15. Usage y = MATHUTILS_ROUND_Q15(x) */ /*! Round and saturate to Q15. Usage MATHUTILS_ROUND_AND_SATURATE_Q15(x), rounds * and saturates x back to itself */ /*! Converts (unsigned) 16-bit FFT index to signed 16-bit value. Input value greater than or equal * half the FFT size becomes negative. */ uint32_t mathUtils_ceilLog2(uint32_t x); uint32_t mathUtils_floorLog2(uint32_t x); uint32_t mathUtils_pow2roundup(uint32_t x); void mathUtils_genWindow(uint32_t *win, uint32_t winLen, uint32_t winGenLen, uint32_t winType, uint32_t qFormat); /* Demo Include Files */ /** * @file mmw_config.h * * @brief * This is the header file that describes configurations for the Millimeter * Wave Demo. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* MMWAVE library Include Files */ /** * @file objectdetection.h * * @brief * Object Detection DPC Header File * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* MMWAVE Driver Include Files */ /** @file edma.h * * @brief EDMA external driver interface. * * Copyright (c) 2016, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage EDMA (Enhanced DMA) Driver * * @section intro_sec Introduction * * The EDMA IP in the ARxxxx SoCs can be programmed at a high-level using * the EDMA driver software that allows hook-up with an operating system. * The EDMA driver exposes programming of most features provided by the IP. * Although the EDMA's user guide for ARxxxx SoCs is not available at present * on the TI public web, because this IP is used in many other older TI parts, * it can be referred to for example at the following url: * http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf * * Following is a high level description of the APIs/features: * * - Query number of EDMA instances on the SoC. * - Initialize a particular instance of EDMA to a known clean disabled state (a reset like state). * - Open an instance of EDMA, which returns instance information such as number * of transfer controllers on that instance. * - Configure a channel to desired configuration and optionally enable channel. * This includes PaRAM set choice and PaRAM set configuration. * User can optionally supply call-back function for channel transfer completion indication. * - Enable/disable a channel. * - Configure a PaRAM set. Typically useful for linked PaRAMs. * - Link PaRAM sets. * - Chain channels. * - Start transfer (manually-triggered) of a previously configured channel. * - Wait until transfer is complete (used in the case when call-back in configuration is not provided). * - APIs to set source or destination address of a PaRAM set, intended for some use * cases on XWR16XX (DSP). * - Error Monitoring configuration for error generation from CC (Channel Controller) * and all TCs (Transfer Controllers). Corresponding error status query for processors * on some devices in which error interrupts are not physically connected to the * processor interrupt map (e.g EDMA instance #1 on xWR16xx's R4F (MSS)). * - Status query. * - Performance control. * - Close an instance of EDMA. * * Here a channel can be a DMA or QDMA channel. * * @section limit Limitations * @subsection hwlimit Unsupported Hardware features. * Following features of the EDMA hardware are presently NOT supported: * - Programming of privilege level and privilege ID is not provided, * these are assumed to be always highest privilege (default settings). * - Querying of source active registers and destination FIFO register in * EDMA TC (Transfer Controller) for advanced debugging not supported. * * @subsection swlimit Unsupported Software features. * - No resource management of any sort is provided e.g no DMA or QDMA channel resource management. * User is required to do static or dynamic resource management outside of the driver. * On XWR16xx/XWR18xx/XWR68xx, the driver software does not prevent both (R4F and C674) processors from * operating the same physical EDMA instance, software instances are not shared * among the processors (software instances are in local memories of processors). * However, if both processors wish to operate on the same physical instance, * then they must coordinate their * activities outside the driver (say using mailbox messages) to ensure * only one is operating on the same physical instance at a time * (because read-modify-write operations would become inconsistent * without multi-processor semaphores) and also coordinate resource * management for resources like channels and transfer completion codes. * * @section api API * * The EDMA API header file should be included in an application as follows: * @code * #include * @endcode * * The documentation for all APIs can be referred by clicking at above file or * by going to @ref EDMA_DRIVER_EXTERNAL_FUNCTION. Example usage of the EDMA * driver can be seen by referring to the EDMA unit test code located at * @verbatim ti/drivers/edma/test/ti_rtos/main.c @endverbatim * * @section event EDMA Event Mapping Definitions. * * Event mapping definitions for the 64 DMA channels can be referred to in * the files: @verbatim ti/common/sys_common_*.h @endverbatim with names: * @verbatim *_REQ_* @endverbatim * For example (on XWR14xx): @verbatim #define EDMA_TPCC0_REQ_HWACC_0 (17U) @endverbatim * indicates that for instance 0 (CC0) of the EDMA, event number 17 (0-based) * is tied to Hardware Accelerator's channel 0 in the SoC. During programming the channelId * parameter when calling configuration API, these defines can be used depending * on what is desired e.g the above example define when used means that when the * Hardware Accelerator channel 0 output line fires, it will trigger the EDMA channel 17 * that was configured using this define. Note the * unit test code may not illustrate this because it picks particular numbers to * test certain boundary conditions. * * Channels that are not tied to any hardware event are available for * general usage (e.g for chaining purposes), * these channels are marked with the suffix: @verbatim FREE_ @endverbatim * For example: @verbatim EDMA_TPCC0_REQ_FREE_0 @endverbatim * * @section caution Caution * * It may be important to disable channels after transfers are done. One case is: * A QDMA channel with param X was programmed and transfer completed with a trigger word. * Then the same param X that is associated with a DMA channel is used for the DMA channel * configuration because it is free. * When configure API is issued, it will only deal with DMA channel registers * as the channel type is DMA and will leave the QDMA channel untouched (in this case enabled). * When the param is configured for * this DMA channel, it will prematurely trigger the QDMA channel when the trigger * word that was left armed is attempted to be configured. Disabling the QDMA * channel before the param associated with it is reused will prevent the problem. * * @section mem_footprint Memory Footprint * * The memory footprint of the driver depends on how many APIs are referred to * by an application (all are not necessary for basic operation). The unit test * code's generated memory map file may be used to get an estimate of * the memory foot-print when most APIs are used. * * * @section edma_silicon_errata EDMA silicon errata * @subsection edma_SIerrata_platform_14_16_18 Incorrect read, hang, or data integrity issues * This silicon errata applies to xWR14xx ES3.0, xWR16xx ES2.0 and xWR18xx ES1.0. * To analyze if the application is configuring EDMA in any of the documented errata scenarios, * user can set the fields in \ref gEDMA_4K_errata_check to true and assess if any error is * returned via the APIs: \ref EDMA_configParamSet and \ref EDMA_setSourceAddress. By default, * the checking is disabled but can be enabled and controlled through flags in * @ref gEDMA_4K_errata_check global structure. Build flag EDMA_4K_SILICON_ERRATA_CHECK is enabled in makefile based * on devices to which this errata applies. For more details, on the structures, checks * and error reported, refer to \ref EDMA_4K_errata_check_t_. * */ /* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** * \file edma_low_level.h * * \brief This file contains the function prototypes for the device * abstraction layer for EDMA. * * \details Please find the below detailed description of edma dal. * -# Programming sequence for initializing the edma controller * -# Perform the clock configuration of channel controller and * transfer controllers. * -# To perform initialization of controller use * -# #EDMA3Init for single CPU interface system. * -# #EDMAsetRegion for multi CPU interface system. * -# Programming sequence for setting up edma channel. * -# To configure the PaRAM sets use #EDMA3SetPaRAM. For * custom use * -# To start transfer use #EDMA3EnableTransfer. * -# To stop transfer use #EDMA3DisableTransfer. * **/ /* ========================================================================== */ /* Include Files */ /* ========================================================================== */ /* ============================================================================= * Copyright (c) Texas Instruments Incorporated 2014 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** * * \file hw_edma_tc.h * * \brief register-level header file for EDMA_TC * **/ /**************************************************************************************************** * Register Definitions ****************************************************************************************************/ /**************************************************************************************************** * Field Definition Macros ****************************************************************************************************/ /* ============================================================================= * Copyright (c) Texas Instruments Incorporated 2014 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** * * \file hw_edma_tpcc.h * * \brief register-level header file for EDMA_TPCC * **/ /**************************************************************************************************** * Register Definitions ****************************************************************************************************/ /**************************************************************************************************** * Field Definition Macros ****************************************************************************************************/ /* ========================================================================== */ /* Macros */ /* ========================================================================== */ /* \brief DMAQNUM bits Clear */ /* \brief DMAQNUM bits Set */ /* \brief QDMAQNUM bits Clear */ /* \brief QDMAQNUM bits Set * @{ */ /* @} */ /* \brief QCHMAP-PaRAMEntry bitfield Set */ /* \brief QCHMAP-TrigWord bitfield Clear */ /* \brief QCHMAP-TrigWord bitfield Set */ /* \brief OPT-TCC bitfield Clear */ /* \brief OPT-TCC bitfield Set * @{ */ /* @} */ /* \brief Values that can be used for parameter chType in API's * @{ */ /*! @brief DMA channel type */ /*! @brief QDMA channel type */ /* @} */ /* \brief Values that can be used to specify different event * status * @{ */ /* @} */ /** \defgroup EDMA_TRANSFER_TYPE_DEFS EDMA transfer type definitions * \brief Values that can be used to specify different * synchronization events * @{ */ /*! @brief Transfer Type "A" */ /*! @brief Transfer Type "AB" */ /* @} */ /* end defgroup EDMA_TRANSFER_TYPE_DEFS */ /** \defgroup EDMA_ADDRESSING_MODE_DEFS EDMA addressing modes definitions. * \brief Values that can be used to specify different * addressing modes (relevant for SAM and DAM sub-fields in OPT field). * @{ */ /*! @brief Incremental addressing (INCR), not FIFO */ /*! @brief Constant addressing (CONST) within the FIFO array, wraps around upon reaching FIFO width */ /* @} */ /* end defgroup EDMA_ADDRESSING_MODE_DEFS */ /** \defgroup EDMA_FIFO_WIDTH_DEFS EDMA FIFO width definitions. * \brief Values that can be used to specify different FIFO widths (FWID in OPT field). * @{ */ /*! @brief 8-bit FIFO width */ /*! @brief 16-bit FIFO width */ /*! @brief 32-bit FIFO width */ /*! @brief 64-bit FIFO width */ /*! @brief 128-bit FIFO width */ /*! @brief 256-bit FIFO width */ /* @} */ /* end defgroup EDMA_FIFO_WIDTH_DEFS */ /* \brief Values that can be user to Clear any Channel controller Errors * @{ */ /* @} */ /* \brief Values that is used to Chain the two specified channels * @{ */ /* @} */ /* \brief paRAMEntry Fields * @{ */ /* \brief The OPT field (Offset Address 0x0 Bytes) */ /* \brief The SRC field (Offset Address 0x4 Bytes)*/ /* \brief The (ACNT+BCNT) field (Offset Address 0x8 Bytes)*/ /* \brief The DST field (Offset Address 0xC Bytes)*/ /* \brief The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)*/ /* \brief The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)*/ /* \brief The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)*/ /* \brief The (CCNT+RSVD) field (Offset Address 0x1C Bytes)*/ /* \brief The offset for each PaRAM Entry field*/ /* \brief Number of PaRAM Entry fields * OPT, SRC, A_B_CNT, DST, SRC_DST_BIDX, LINK_BCNTRLD, SRC_DST_CIDX * and CCNT * @{ */ /* @} */ /* @} */ /* ========================================================================== */ /* Structures */ /* ========================================================================== */ /** * \brief EDMA3 Parameter RAM Set in User Configurable format * * This is a mapping of the EDMA3 PaRAM set provided to the user * for ease of modification of the individual fields */ typedef struct { /** OPT field of PaRAM Set */ uint32_t opt; /** * \brief Starting byte address of Source * For FIFO mode, srcAddr must be a 256-bit aligned address. */ uint32_t srcAddr; /** * \brief Number of bytes in each Array (ACNT) */ uint16_t aCnt; /** * \brief Number of Arrays in each Frame (BCNT) */ uint16_t bCnt; /** * \brief Starting byte address of destination * For FIFO mode, destAddr must be a 256-bit aligned address. * i.e. 5 LSBs should be 0. */ uint32_t destAddr; /** * \brief Index between consec. arrays of a Source Frame (SRCBIDX) */ int16_t srcBIdx; /** * \brief Index between consec. arrays of a Destination Frame (DSTBIDX) */ int16_t destBIdx; /** * \brief Address for linking (AutoReloading of a PaRAM Set) * This must point to a valid aligned 32-byte PaRAM set * A value of 0xFFFF means no linking */ uint16_t linkAddr; /** * \brief Reload value of the numArrInFrame (BCNT) * Relevant only for A-sync transfers */ uint16_t bCntReload; /** * \brief Index between consecutive frames of a Source Block (SRCCIDX) */ int16_t srcCIdx; /** * \brief Index between consecutive frames of a Dest Block (DSTCIDX) */ int16_t destCIdx; /** * \brief Number of Frames in a block (CCNT) */ uint16_t cCnt; }EDMA3CCPaRAMEntry; /* ========================================================================== */ /* Function Declarations */ /* ========================================================================== */ /** * \brief EDMA3 Initialization * * This function initializes the EDMA3 Driver * Clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) & * initialize the Queue Number Registers * * \param baseAddr Memory address of the EDMA instance used.\n * * \param queNum Event Queue Number to which the channel * will be mapped (valid only for the * Master Channel (DMA/QDMA) request).\n * * \return None * * \note The regionId is the shadow region(0 or 1) used and the, * Event Queue used is either (0 or 1). There are only four shadow * regions and only two event Queues */ void EDMA3Init(uint32_t baseAddr, uint32_t queNum); /** * \brief This API sets the region. * * \param i pass the regionId.\n * **/ void EDMAsetRegion(uint32_t i); /** * \brief Enable channel to Shadow region mapping * * This API allocates DMA/QDMA channels or TCCs, and the same resources are * enabled in the shadow region specific register (DRAE/DRAEH/QRAE). * Here only one shadow region is used since, there is only one Master. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chType (DMA/QDMA) Channel * For Example: For DMA it is, * EDMA3_CHANNEL_TYPE_DMA.\n * * \param chNum Allocated channel number.\n * * * chType can have values * EDMA3_CHANNEL_TYPE_DMA\n * EDMA3_CHANNEL_TYPE_QDMA * * \return None */ void EDMA3EnableChInShadowReg(uint32_t baseAddr, uint32_t chType, uint32_t chNum); /** * \brief Disable channel to Shadow region mapping * * This API allocates DMA/QDMA channels or TCCs, and the same resources are * enabled in the shadow region specific register (DRAE/DRAEH/QRAE). * Here only one shadow region is used since, there is only one Master. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chType (DMA/QDMA) Channel * * \param chNum Allocated channel number.\n * * * chType can have values * EDMA3_CHANNEL_TYPE_DMA\n * EDMA3_CHANNEL_TYPE_QDMA * * \return None */ void EDMA3DisableChInShadowReg(uint32_t baseAddr, uint32_t chType, uint32_t chNum); /** * \brief This function maps DMA channel to any of the PaRAM sets * in the PaRAM memory map. * * \param baseAddr Memory address of the EDMA instance used. * * \param channel The DMA channel number required to be mapped. * * \param paramSet It specifies the paramSet to which DMA channel * required to be mapped. * * \return None */ void EDMA3ChannelToParamMap(uint32_t baseAddr, uint32_t channel, uint32_t paramSet); /** * \brief Map channel to Event Queue * * This API maps DMA/QDMA channels to the Event Queue * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chType (DMA/QDMA) Channel * For Example: For QDMA it is * EDMA3_CHANNEL_TYPE_QDMA.\n * * \param chNum Allocated channel number.\n * * \param evtQNum Event Queue Number to which the channel * will be mapped (valid only for the * Master Channel (DMA/QDMA) request).\n * * chtype can have values * EDMA3_CHANNEL_TYPE_DMA\n * EDMA3_CHANNEL_TYPE_QDMA * * \return None */ void EDMA3MapChToEvtQ(uint32_t baseAddr, uint32_t chType, uint32_t chNum, uint32_t evtQNum); /** * \brief Remove Mapping of channel to Event Queue * * This API Unmaps DMA/QDMA channels to the Event Queue allocated * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chType (DMA/QDMA) Channel * For Example: For DMA it is * EDMA3_CHANNEL_TYPE_DMA.\n * * \param chNum Allocated channel number.\n * * chtype can have values * EDMA3_CHANNEL_TYPE_DMA\n * EDMA3_CHANNEL_TYPE_QDMA * * \return None */ void EDMA3UnmapChToEvtQ(uint32_t baseAddr, uint32_t chType, uint32_t chNum); /** * \brief Enables the user to map a QDMA channel to PaRAM set * This API Needs to be called before programming the paRAM sets for * the QDMA Channels.Application needs to maitain the paRAMId * provided by this API.This paRAMId is used to set paRAM and get * paRAM. Refer corresponding API's for more details. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated QDMA channel number.\n * * \param paRAMId PaRAM Id to which the QDMA channel will be * mapped to. * mapped to. * * \return None * * Note : The PaRAMId requested must be greater than 32(SOC_EDMA3_NUM_DMACH). * and lesser than SOC_EDMA3_NUM_DMACH + chNum Because, the first * 32 PaRAM's are directly mapped to first 32 DMA channels and (32 - 38) * for QDMA Channels. (32 - 38) is assigned by driver in this API. * */ void EDMA3MapQdmaChToPaRAM(uint32_t baseAddr, uint32_t chNum, const uint32_t *paRAMId); /** * \brief Assign a Trigger Word to the specified QDMA channel * * This API sets the Trigger word for the specific QDMA channel in the QCHMAP * Register. Default QDMA trigger word is CCNT. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum QDMA Channel which needs to be assigned * the Trigger Word * * \param trigWord The Trigger Word for the QDMA channel. * Trigger Word is the word in the PaRAM * Register Set which, when written to by CPU, * will start the QDMA transfer automatically. * * \return None */ void EDMA3SetQdmaTrigWord(uint32_t baseAddr, uint32_t chNum, uint32_t trigWord); /** * \brief Enables the user to Clear any missed event * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None */ void EDMA3ClrMissEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to Clear any QDMA missed event * * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * * \return None */ void EDMA3QdmaClrMissEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to Clear any Channel controller Errors * * \param baseAddr Memory address of the EDMA instance used.\n * * \param flags Masks to be passed.\n * * flags can have values: * * EDMA3CC_CLR_TCCERR Clears the TCCERR bit in the EDMA3CC * ERR Reg\n * EDMA3CC_CLR_QTHRQ0 Queue threshold error clear for queue 0.\n * EDMA3CC_CLR_QTHRQ1 Queue threshold error clear for queue 1. * * \return None */ void EDMA3ClrCCErr(uint32_t baseAddr, uint32_t flags); /** * \brief Enables the user to Set an event. This API helps user to manually * set events to initiate DMA transfer requests. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : This API is generally used during Manual transfers.\n */ void EDMA3SetEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to Clear an event. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : This API is generally used during Manual transfers.\n */ void EDMA3ClrEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to enable an DMA event. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : Writes of 1 to the bits in EESR sets the corresponding event * bits in EER. This is generally used for Event Based transfers.\n */ void EDMA3EnableDmaEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to Disable an DMA event. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * ** * \return None * * Note : Writes of 1 to the bits in EECR clear the corresponding event bits * in EER; writes of 0 have no effect.. This is generally used for * Event Based transfers.\n */ void EDMA3DisableDmaEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to enable an QDMA event. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : Writes of 1 to the bits in QEESR sets the corresponding event * bits in QEER.\n */ void EDMA3EnableQdmaEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to disable an QDMA event. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : Writes of 1 to the bits in QEECR clears the corresponding event * bits in QEER.\n */ void EDMA3DisableQdmaEvt(uint32_t baseAddr, uint32_t chNum); /** * \brief This function returns interrupts status of those events * which is less than 32. * * \param baseAddr Memory address of the EDMA instance used.\n * **/ uint32_t EDMA3GetIntrStatus(uint32_t baseAddr); /** * \brief Enables the user to enable the transfer completion interrupt * generation by the EDMA3CC for all DMA/QDMA channels. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : To set any interrupt bit in IER, a 1 must be written to the * corresponding interrupt bit in the interrupt enable set register. */ void EDMA3EnableEvtIntr(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to clear CC interrupts * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Allocated channel number.\n * * \return None * * Note : Writes of 1 to the bits in IECR clear the corresponding interrupt * bits in the interrupt enable registers (IER); writes of 0 have * no effect.\n */ void EDMA3DisableEvtIntr(uint32_t baseAddr, uint32_t chNum); /** * \brief Enables the user to Clear an Interrupt. * * \param baseAddr Memory address of the EDMA instance used. * * \param value Value to be set to clear the Interrupt * Status. * * \return None * */ void EDMA3ClrIntr(uint32_t baseAddr, uint32_t value); /** * \brief Retrieve existing PaRAM set associated with specified logical * channel (DMA/Link). * * \param baseAddr Memory address of the EDMA instance used.\n * * \param paRAMId paRAMset ID whose parameter set is * requested.\n * * \param currPaRAM User gets the existing PaRAM here.\n * * * \return None * */ void EDMA3GetPaRAM(uint32_t baseAddr, uint32_t paRAMId, EDMA3CCPaRAMEntry *currPaRAM); /** * \brief Retrieve existing PaRAM set associated with specified logical * channel (QDMA). * * \param baseAddr Memory address of the EDMA instance used.\n * * \param paRAMId paRAMset ID whose parameter set is * requested.\n * * \param currPaRAM User gets the existing PaRAM here.\n * * \return None * */ void EDMA3QdmaGetPaRAM(uint32_t baseAddr, uint32_t paRAMId, EDMA3CCPaRAMEntry *currPaRAM); /** * \brief Copy the user specified PaRAM Set onto the PaRAM Set associated * with the logical channel (DMA/Link). * * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set * associated with the logical channel. OPT field of the PaRAM Set is written * first and the CCNT field is written last. * * * \param baseAddr Memory address of the EDMA instance used.\n * * \param paRAMId paRAMset ID whose parameter set has to be * updated * * \param newPaRAM Parameter RAM set to be copied onto existing * PaRAM.\n * * \return None * */ void EDMA3SetPaRAM(uint32_t baseAddr, uint32_t paRAMId, EDMA3CCPaRAMEntry *newPaRAM); /** * \brief Copy the user specified PaRAM Set onto the PaRAM Set associated * with the logical channel (QDMA only). * * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set * associated with the logical channel. OPT field of the PaRAM Set is written * first and the CCNT field is written last. * * * \param baseAddr Memory address of the EDMA instance used.\n * * * \param paRAMId paRaMset ID whose parameter set has to be * updated * * \param newPaRAM Parameter RAM set to be copied onto existing * PaRAM.\n * * \return None * */ void EDMA3QdmaSetPaRAM(uint32_t baseAddr, uint32_t paRAMId, EDMA3CCPaRAMEntry *newPaRAM); /** * \brief Set a particular PaRAM set entry of the specified PaRAM set * * \param baseAddr Memory address of the EDMA instance used.\n * * \param paRAMId PaRAM Id to which the QDMA channel is * mapped to. * * \param paRAMEntry Specify the PaRAM set entry which needs * to be set. * * \param newPaRAMEntryVal The new field setting. Make sure this field is * packed for setting certain fields in paRAM. * * EDMA3CC_PARAM_ENTRY_OPT * EDMA3CC_PARAM_ENTRY_SRC * EDMA3CC_PARAM_ENTRY_ACNT_BCNT * EDMA3CC_PARAM_ENTRY_DST * EDMA3CC_PARAM_ENTRY_SRC_DST_BIDX * EDMA3CC_PARAM_ENTRY_LINK_BCNTRLD * EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX * EDMA3CC_PARAM_ENTRY_CCNT * * \return None * * \note This API should be used while setting the PaRAM set entry * for QDMA channels. If EDMA3QdmaSetPaRAMEntry() used, * it will trigger the QDMA channel before complete * PaRAM set entry is written. */ void EDMA3QdmaSetPaRAMEntry(uint32_t baseAddr, uint32_t paRAMId, uint32_t paRAMEntry, uint32_t newPaRAMEntryVal); /** * \brief Get a particular PaRAM entry of the specified PaRAM set * * \param baseAddr Memory address of the EDMA instance used.\n * * \param paRAMId PaRAM Id to which the QDMA channel is * mapped to. * * \param paRAMEntry Specify the PaRAM set entry which needs * to be read. * * paRAMEntry can have values: * * EDMA3CC_PARAM_ENTRY_OPT * EDMA3CC_PARAM_ENTRY_SRC * EDMA3CC_PARAM_ENTRY_ACNT_BCNT * EDMA3CC_PARAM_ENTRY_DST * EDMA3CC_PARAM_ENTRY_SRC_DST_BIDX * EDMA3CC_PARAM_ENTRY_LINK_BCNTRLD * EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX * EDMA3CC_PARAM_ENTRY_CCNT * * \return paRAMEntryVal The value of the paRAM field pointed by the * paRAMEntry. * * \note This API should be used while reading the PaRAM set entry * for QDMA channels. And the paRAMEntryVal is a packed value for * certain fields of paRAMEntry.The user has to make sure the value * is unpacked appropriately. * For example, the third field is A_B_CNT. Hence he will have to * unpack it to two 16 bit fields to get ACNT and BCNT. */ uint32_t EDMA3QdmaGetPaRAMEntry(uint32_t baseAddr, uint32_t paRAMId, uint32_t paRAMEntry); /** * \brief Request a DMA/QDMA/Link channel. * * Each channel (DMA/QDMA/Link) must be requested before initiating a DMA * transfer on that channel. * * This API is used to allocate a logical channel (DMA/QDMA/Link) along with * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are * also allocated along with the requested channel. * * User can request a specific logical channel by passing the channel number * in 'chNum'. * * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also * sets the event queue for the channel allocated. The event queue needs to * be specified by the user. * * For DMA channel, it also sets the DCHMAP register. * * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and * enables the QDMA channel by writing to the QEESR register. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chType (DMA/QDMA) Channel * For Example: For DMA it is * EDMA3_CHANNEL_TYPE_DMA.\n * * \param chNum This is the channel number requested for a * particular event.\n * * \param tccNum The channel number on which the * completion/error interrupt is generated. * Not used if user requested for a Link * channel.\n * * \param evtQNum Event Queue Number to which the channel * will be mapped (valid only for the * Master Channel (DMA/QDMA) request).\n * * \return TRUE if parameters are valid, else FALSE */ uint32_t EDMA3RequestChannel(uint32_t baseAddr, uint32_t chType, uint32_t chNum, uint32_t tccNum, uint32_t evtQNum); /** * \brief Free the specified channel (DMA/QDMA/Link) and its associated * resources (PaRAM Set, TCC etc) and removes various mappings. * * For Link channels, this API only frees the associated PaRAM Set. * * For DMA/QDMA channels, it does the following operations: * 1) Disable any ongoing transfer on the channel,\n * 2) Remove the channel to Event Queue mapping,\n * 3) For DMA channels, clear the DCHMAP register, if available\n * 4) For QDMA channels, clear the QCHMAP register,\n * 5) Frees the DMA/QDMA channel in the end.\n * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chType (DMA/QDMA) Channel * For Example: For QDMA it is, * EDMA3_CHANNEL_TYPE_QDMA.\n * * \param chNum This is the channel number requested for a * particular event.\n * * \param trigMode Mode of triggering start of transfer.\n * * \param tccNum The channel number on which the * completion/error interrupt is generated. * Not used if user requested for a Link * channel.\n * * \param evtQNum Event Queue Number to which the channel * will be unmapped (valid only for the * Master Channel (DMA/QDMA) request).\n * * trigMode can have values: * EDMA3_TRIG_MODE_MANUAL\n * EDMA3_TRIG_MODE_QDMA\n * EDMA3_TRIG_MODE_EVENT * * \return TRUE if parameters are valid else return FALSE */ uint32_t EDMA3FreeChannel(uint32_t baseAddr, uint32_t chType, uint32_t chNum, uint32_t trigMode, uint32_t tccNum, uint32_t evtQNum); /** * \brief Start EDMA transfer on the specified channel. * * There are multiple ways to trigger an EDMA3 transfer. The triggering mode * option allows choosing from the available triggering modes: Event, * Manual or QDMA. * * In event triggered, a peripheral or an externally generated event triggers * the transfer. This API clears the Event and Event Miss Register and then * enables the DMA channel by writing to the EESR. * * In manual triggered mode, CPU manually triggers a transfer by writing a 1 * in the Event Set Register ESR. This API writes to the ESR to start the * transfer. * * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set * that has been mapped to a QDMA channel (link triggered). This API enables * the QDMA channel by writing to the QEESR register. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Channel being used to enable transfer.\n * * \param trigMode Mode of triggering start of transfer (Manual, * QDMA or Event).\n * * trigMode can have values: * EDMA3_TRIG_MODE_MANUAL\n * EDMA3_TRIG_MODE_QDMA\n * EDMA3_TRIG_MODE_EVENT\n * * \return retVal TRUE or FALSE depending on the param passed.\n * */ uint32_t EDMA3EnableTransfer(uint32_t baseAddr, uint32_t chNum, uint32_t trigMode); /** * \brief Disable DMA transfer on the specified channel * * There are multiple ways by which an EDMA3 transfer could be triggered. * The triggering mode option allows choosing from the available triggering * modes. * * To disable a channel which was previously triggered in manual mode, * this API clears the Secondary Event Register and Event Miss Register, * if set, for the specific DMA channel. * * To disable a channel which was previously triggered in QDMA mode, this * API clears the QDMA Event Enable Register, for the specific QDMA channel. * * To disable a channel which was previously triggered in event mode, this API * clears the Event Enable Register, Event Register, Secondary Event Register * and Event Miss Register, if set, for the specific DMA channel. * * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum Channel being used to enable transfer.\n * * \param trigMode Mode of triggering start of transfer (Manual, * QDMA or Event).\n * \return retVal TRUE or FALSE depending on the param passed.\n * */ uint32_t EDMA3DisableTransfer(uint32_t baseAddr, uint32_t chNum, uint32_t trigMode); /** * \brief Clears Event Register and Error Register for a specific * DMA channel and brings back EDMA3 to its initial state. * * This API clears the Event register, Event Miss register, Event Enable * register for a specific DMA channel. It also clears the CC Error register. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chNum This is the channel number requested for a * particular event.\n * * \param evtQNum Event Queue Number to which the channel * will be unmapped (valid only for the * Master Channel (DMA/QDMA) request).\n * * \return none.\n */ void EDMA3ClearErrorBits(uint32_t baseAddr, uint32_t chNum, uint32_t evtQNum); /** * \brief This returns EDMA3 CC error status. * * \param baseAddr Memory address of the EDMA instance used.\n * * \return value Status of the Interrupt Pending Register * */ uint32_t EDMA3GetCCErrStatus(uint32_t baseAddr); /** * \brief This returns error interrupt status for those events whose * event number is less than 32. * * \param baseAddr Memory address of the EDMA instance used.\n * * \return value Status of the Interrupt Pending Register * */ uint32_t EDMA3GetErrIntrStatus(uint32_t baseAddr); /** * \brief This returns QDMA error interrupt status. * * \param baseAddr Memory address of the EDMA instance used.\n * * \return value Status of the QDMA Interrupt Pending Register * */ uint32_t EDMA3QdmaGetErrIntrStatus(uint32_t baseAddr); /** * \brief EDMA3 Deinitialization * * This function deinitializes the EDMA3 Driver * Clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) & * deinitialize the Queue Number Registers * * \param baseAddr Memory address of the EDMA instance used.\n * * \param queNum Event Queue used * \return None * * \note The regionId is the shadow region(0 or 1) used and the, * Event Queue used is either (0 or 1). There are only two shadow * regions and only two event Queues */ void EDMA3Deinit(uint32_t baseAddr, uint32_t queNum); /** Bug fix removed this function **/ uint32_t EDMAVersionGet(void); /** * \brief This API return the revision Id of the peripheral. * * \param baseAddr Memory address of the EDMA instance used.\n * **/ uint32_t EDMA3PeripheralIdGet(uint32_t baseAddr); /** * \brief This function returns interrupts status of those events * which is greater than 32. * * \param baseAddr Memory address of the EDMA instance used.\n * **/ uint32_t EDMA3IntrStatusHighGet(uint32_t baseAddr); /** * \brief This returns error interrupt status for those events whose * event number is greater than 32. * * \param baseAddr Memory address of the EDMA instance used.\n * \return value Status of the Interrupt Pending Register * */ uint32_t EDMA3ErrIntrHighStatusGet(uint32_t baseAddr); /** * \brief Chain the two specified channels * * This API is used to chain a DMA channel to a previously allocated DMA/QDMA * channel * * Chaining is different from Linking. The EDMA3 link feature reloads the * current channel parameter set with the linked parameter set. The EDMA3 * chaining feature does not modify or update any channel parameter set; * it provides a synchronization event (or trigger) to the chained DMA channel, * as soon as the transfer (final or intermediate) completes on the main * DMA/QDMA channel. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param chId1 DMA/QDMA channel to which a particular * DMA channel will be chained * * \param chId2 DMA channel which needs to be chained to * the first DMA/QDMA channel. * * \param chainOptions Options such as intermediate interrupts * are required or not, intermediate/final * chaining is enabled or not etc. * * \return none.\n */ void EDMA3ChainChannel(uint32_t baseAddr, uint32_t chId1, uint32_t chId2, uint32_t chainOptions); /** * \brief Link two channels. * * This API is used to link two previously allocated logical (DMA/QDMA/Link) * channels. * * It sets the Link field of the PaRAM set associated with first * channel (chId1) to point it to the PaRAM set associated with second * channel (chId2). * * It also sets the TCC field of PaRAM set of second channel to the * same as that of the first channel. * * \param baseAddr Memory address of the EDMA instance used.\n * * \param paRAMId1 PaRAM set ID of physical channel1 to which * particular paRAM set will be linked * or * PaRAM set ID in case another PaRAM set is being * linked to this PaRAM set * * \param paRAMId2 PaRAM set ID which is linked to * channel with parameter ID paRAMId1 * * After the transfer based on the PaRAM set * of channel1 is over, the PaRAM set paRAMId2 will * be copied to the PaRAM set of channel1 and * transfer will resume. * For DMA channels, another sync event is * required to initiate the transfer on the * Link channel. * * \return none.\n */ void EDMA3LinkChannel(uint32_t baseAddr, uint32_t paRAMId1, uint32_t paRAMId2); /********************************* End of file ******************************/ /* common among AR devices, don't waste memory to store these */ /*! @brief Total number of DMA channels */ /*! @brief Total number of transfer completion codes */ /*! @brief Total number of QDMA channels */ /* constants for EDMA IP in any device (not just mmwave ones) */ /*! @brief Maximum number of event queues in any EDMA IP */ /*! @brief Maximum number of transfer controllers in any EDMA IP */ /*! @brief Number of entries in each queue in any EDMA IP */ /******************************************************************************/ /************************ QDMA Trigger Word Offset defines*********************/ /******************************************************************************/ /** @defgroup EDMA_TRIG_WORDS QDMA Trigger Word Offset Definitions * * @brief * Base error code for the EDMA module is defined in the * \include ti/common/mmwave_error.h * @{ */ /*! @brief * Set the OPT field (Offset Address 0h Bytes) * as the QDMA trigger word */ /*! @brief * Set the SRC field (Offset Address 4h Bytes) * as the QDMA trigger word */ /*! @brief * Set the (ACNT + BCNT) field (Offset Address 8h Bytes) * as the QDMA trigger word */ /*! @brief * Set the DST field (Offset Address Ch Bytes) * as the QDMA trigger word */ /*! @brief * Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) * as the QDMA trigger word */ /*! @brief * Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) * as the QDMA trigger word */ /*! @brief * Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) * as the QDMA trigger word */ /*! @brief * Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes) * as the QDMA trigger word */ /*! @brief Default Trigger Word is CCNT */ /** @}*/ /* end defgroup EDMA_TRIG_WORDS */ /******************************************************************************/ /*! @brief NULL Link Address */ /******************************************************************************/ /************************ Error code defines **********************************/ /******************************************************************************/ /** @defgroup EDMA_ERROR_CODES Error Codes * * @brief * Base error code for the EDMA module is defined in the * \include ti/common/mmwave_error.h * @{ */ /*****EDMA_E_INVALID__ : Invalid API parameters or parameter combinations *****/ /*! @brief Handle argument is NULL pointer. */ /*! @brief Config argument is NULL pointer. */ /*! @brief Config's channelType is invalid. */ /*! @brief Config's channelId out of range. */ /*! @brief Config's paramId out of range. */ /*! @brief Config's eventQueueId out of range */ /*! @brief Config's both interrupt completion flags are false but transfer completion call back function is configured (non NULL). */ /*! @brief Config's transferCompletionCode is invalid. */ /*! @brief Config's transferType is invalid. */ /*! @brief Invalid Qdma channelId. */ /*! @brief Invalid Instance Id during open. */ /*! @brief Invalid QDMA trigger word. */ /*! @brief Invalid transfer controller Id. */ /*! @brief Invalid transfer controller read rate */ /*! @brief Invalid queue priority in performance config. */ /*! @brief During @ref EDMA_startTransfer, unexpected QDMA miss event detected. */ /*! @brief During @ref EDMA_configChannel, param ID must be same * as channel ID for DMA channel because channel mapping does not exist * in the hardware. */ /*! @brief Status argument is NULL pointer. */ /*! @brief InstanceInfo argument is NULL pointer. */ /*! @brief Error Call back function was expected to be NULL because error * interrupt is not connected to the CPU on the device */ /*! @brief TC error Call back function was expected to be NULL because at least * one of the TC error interrupts are not connected to the CPU on the device */ /************** EDMA_E_UNEXPECTED__ : Unexpected conditions *******************/ /*! @brief During @ref EDMA_startTransfer, unexpected DMA miss event detected. */ /*! @brief During @ref EDMA_startTransfer, unexpected QDMA miss event detected. */ /*! @brief Attempt to reopen and already opened instance. */ /*! @brief Attempt to issue @ref EDMA_isTransferComplete despite non-NULL completion call-back function. */ /************** EDMA_E_OSAL__ : OSAL API related error conditions *************/ /*! @brief HwiP_create returned NULL on transfer completion Isr creation. */ /*! @brief HwiP_create returned NULL on CC error Isr creation. */ /*! @brief HwiP_create returned NULL on one of transfer controller error Isrs creation. */ /*! @brief HwiP_delete returned NULL on transfer completion Isr deletion. */ /*! @brief HwiP_delete returned NULL on CC error Isr deletion. */ /*! @brief HwiP_delete returned NULL on one of transfer controller error Isrs deletion. */ /************** EDMA_E_SILICON_ERRATA__ : Silicon Errata related error conditions *************/ /*! @brief 4K source boundary cross-over related errata of data integrity violation or hang. */ /*! @brief 4K source boundary cross-over related errata of extra read (no data integrity) violation. */ /*! @brief Operation cannot be implemented because a previous operation is still not complete. */ /*! @brief Operation is not implemented. */ /** @}*/ /* end defgroup EDMA_ERROR_CODES */ /*! @brief No Error. */ /******************************************************************************/ /************************ Event queue threshold defines************************/ /******************************************************************************/ /** @defgroup EDMA_EVENT_QUEUE_THRESHOLD Event Queue Threshold Configuration Defines * * @brief * Special defines for event queue threshold configuration. * @{ */ /*! @brief Disable thresholding */ /*! @brief Queue ever used i.e queue had non-zero occupancy ever */ /*! @brief Queue ever full i.e was there ever a time when queue was full */ /*! @brief Max queue threshold, same as queue ever full */ /** @}*/ /* end defgroup EDMA_EVENT_QUEUE_THRESHOLD */ /******************************************************************************/ /************************ Read rate defines************************************/ /******************************************************************************/ /** @defgroup EDMA_READ_RATE_DEFINES Read Rate Definitions * * @brief * Read rate defines for performance configuration. * @{ */ /*! @brief as fast as possible */ /*! @brief 4 cycles between reads */ /*! @brief 8 cycles between reads */ /*! @brief 16 cycles between reads */ /*! @brief 32 cycles between reads */ /** @}*/ /* end defgroup EDMA_READ_RATE_DEFINES */ /*! * @brief A handle that is returned from a @ref EDMA_open call. */ typedef void *EDMA_Handle; /*! * @brief Transfer completion call back function definition. * @param[out] Argument that was registered during call back registeration during * configuration. * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[out] transferCompletionCode * Transfer completion code of the completed transfer. */ typedef void (*EDMA_transferCompletionCallbackFxn_t) (uintptr_t arg, uint8_t transferCompletionCode); /*! * @brief Error Information structure. Information is from EMR(H), QEMR, CCERR * registers as per EDMA UG. */ typedef struct EDMA_errorInfo_t_ { /*! @brief Each element of the array indicates whether a DMA channel event is missed * for the corresponding DMA channel index. */ _Bool isDmaChannelEventMiss[(64U)]; /*! @brief Each element of the array indicates whether a QDMA channel event is missed * for the corresponding QDMA channel index. */ _Bool isQdmaChannelEventMiss[((uint8_t)8)]; /*! @brief CCERR::TCERR in EDMA UG */ _Bool isOutstandingTransferCompletionTransfersExceededLimit; /*! @brief CCERR::QTHRXCDx bits in EDMA UG */ _Bool isEventQueueThresholdExceeded[((uint8_t)8)]; /*! @brief Number of event Queues of the opened CC provided as convenience these many elements will be relevent in the @ref isEventQueueThresholdExceeded array */ uint8_t numEventQueues; } EDMA_errorInfo_t; /*! * @brief Error call back function. * @param[out] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[out] errorInfo * Pointer to error information @ref EDMA_errorInfo_t_. */ typedef void (*EDMA_errorCallbackFxn_t) (EDMA_Handle handle, EDMA_errorInfo_t *errorInfo); /*! * @brief Transfer controller bus error information, relevant when * @ref EDMA_transferControllerErrorInfo_t_::isBusError is true. */ typedef struct EDMA_transferControllerBusErrorInfo_t_ { /*! @brief ERRDET::STAT in EDMA UG. */ uint8_t errorCode; /*! @brief ERRDET::TCC in EDMA UG. */ uint8_t transferCompletionCode; /*! @brief ERRDET::TCCHEN in EDMA UG. */ _Bool isFinalChainingEnabled; /*! @brief ERRDET::TCINTEN in EDMA UG. */ _Bool isFinalTransferInterruptEnabled; } EDMA_transferControllerBusErrorInfo_t; /*! * @brief Transfer controller error information. */ typedef struct EDMA_transferControllerErrorInfo_t_ { /*! @brief ERRSTAT::TRERR in EDMA UG. */ _Bool isTransferRequestError; /*! @brief ERRSTAT::MMRAERR in EDMA UG. */ _Bool isWriteToReservedConfigMemoryMap; /*! * @brief true if bus error, see @ref busErrorInfo for more details. */ _Bool isBusError; /*! * @brief Bus Error Information, relevant if @ref isBusError is true. */ EDMA_transferControllerBusErrorInfo_t busErrorInfo; /*! @brief Transfer controller Id of the errring transfer controller, can be between 0 and (number of transfer controllers on the opened CC - 1). */ uint8_t transferControllerId; } EDMA_transferControllerErrorInfo_t; /*! * @brief Transfer controller error call back function. Usually * transfer controller errors are fatal. * @param[out] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[out] errorInfo * Pointer to error information @ref EDMA_transferControllerErrorInfo_t_. */ typedef void (*edmaTransferControllerErrorCallbackFxn_t) (EDMA_Handle handle, EDMA_transferControllerErrorInfo_t *errorInfo); /*! * @brief PaRAM Set configuration. */ typedef struct EDMA_paramSetConfig_t_ { /** * \brief Starting byte address of source. */ uint32_t sourceAddress; /** * \brief Starting byte address of destination. */ uint32_t destinationAddress; /** * \brief Number of bytes in each Array (ACNT). */ uint16_t aCount; /** * \brief Number of Arrays in each Frame (BCNT). */ uint16_t bCount; /** * \brief Number of Frames in a block (CCNT). */ uint16_t cCount; /** * \brief Reload value of the numArrInFrame (BCNT) * Relevant only for A-sync transfers. */ uint16_t bCountReload; /** * \brief Index between consec. arrays of a Source Frame (SRCBIDX). */ int16_t sourceBindex; /** * \brief Index between consec. arrays of a Destination Frame (DSTBIDX). */ int16_t destinationBindex; /** * \brief Index between consecutive frames of a Source Block (SRCCIDX). */ int16_t sourceCindex; /** * \brief Index between consecutive frames of a Dest Block (DSTCIDX). */ int16_t destinationCindex; /** * \brief Address for linking (AutoReloading of a PaRAM Set) * This must point to a valid aligned 32-byte PaRAM set * A value of 0xFFFF means (@ref EDMA_NULL_LINK_ADDRESS) no linking. */ uint16_t linkAddress; /** * \brief transfer type which can be one of those defined in * @ref EDMA_TRANSFER_TYPE_DEFS. */ uint8_t transferType; /** * \brief transfer Completion Code, must be in the range [0,63]. */ uint8_t transferCompletionCode; /** * \brief Source addressing mode, see @ref EDMA_ADDRESSING_MODE_DEFS. */ uint8_t sourceAddressingMode; /** * \brief Destination addressing mode, see @ref EDMA_ADDRESSING_MODE_DEFS. */ uint8_t destinationAddressingMode; /** * \brief FIFO width, see @ref EDMA_FIFO_WIDTH_DEFS. */ uint8_t fifoWidth; /** * \brief STATIC bit of OPT as described in the EDMA UG. */ _Bool isStaticSet; /** * \brief This is bit TCCMODE of OPT as defined in EDMA UG. */ _Bool isEarlyCompletion; /** * \brief This is bit TCINTEN of OPT as defined in EDMA UG. */ _Bool isFinalTransferInterruptEnabled; /** * \brief This is bit ITCINTEN of OPT as defined in EDMA UG. */ _Bool isIntermediateTransferInterruptEnabled; /** * \brief This is bit TCCHEN of OPT as defined in EDMA UG. */ _Bool isFinalChainingEnabled; /** * \brief This is bit ITCCHEN of OPT as defined in EDMA UG. */ _Bool isIntermediateChainingEnabled; } EDMA_paramSetConfig_t; /*! * @brief Channel configuration. Specifies the full configuration for a DMA or * QDMA channel with associated paramId and param Set configuration. */ typedef struct EDMA_channelConfig_t_ { /** * \brief channelType can be either @ref EDMA3_CHANNEL_TYPE_DMA or * @ref EDMA3_CHANNEL_TYPE_QDMA */ uint8_t channelType; /** * \brief qdmaParamTriggerWordOffset represents the offset (0-7) * of the PaRAM that is used * when @ref channelType is @ref EDMA3_CHANNEL_TYPE_QDMA, * use one of @ref EDMA_TRIG_WORDS for * convenience of specifying which parameter in the Param is to be used * as the trigger word. */ uint8_t qdmaParamTriggerWordOffset; /** * \brief * 0 to (@ref EDMA_NUM_DMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_DMA. \n * 0 to (@ref EDMA_NUM_QDMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_QDMA. */ uint8_t channelId; /** * \brief Id of the PaRAM set, valid range is from 0 to (N - 1), * where N is the number of param sets in the EDMA's CC that is opened, * must be identical to @ref channelId for * DMA channel (@ref channelType is @ref EDMA3_CHANNEL_TYPE_DMA) if channel mapping does * not exist in the hardware. */ uint16_t paramId; /** * \brief Id of the event queue in which the channel transfer request is submitted, * valid range is from 0 to (Q - 1), * where Q is the number of event queues in the EDMA's CC that is opened. */ uint8_t eventQueueId; /** * \brief configuration of the PaRAM set */ EDMA_paramSetConfig_t paramSetConfig; /** * \brief call back function for intermediate or final transfer completion * depending on configuration of interrupt related flags in @ref paramSetConfig. * If NULL, it is assumed that the intent of the user is to poll for the * completion of the transfer using @ref EDMA_isTransferComplete. */ EDMA_transferCompletionCallbackFxn_t transferCompletionCallbackFxn; /** * \brief argument to be returned by the call back function @ref transferCompletionCallbackFxn. */ uintptr_t transferCompletionCallbackFxnArg; } EDMA_channelConfig_t; /*! * @brief Param configuration typically used for stand-alone param sets * (param sets not associated with any of the 64 DMA channels) such * as for QDMA channels or for linking purposes. */ typedef struct EDMA_paramConfig_t_ { /** * \brief configuration of the PaRAM set. */ EDMA_paramSetConfig_t paramSetConfig; /** * \brief call back function for intermediate or final transfer completion * depending on configuration of interrupt related flags in @ref paramSetConfig * if NULL, it is assumed that the intent of the user is to poll for the * completion of the transfer using @ref EDMA_isTransferComplete. */ EDMA_transferCompletionCallbackFxn_t transferCompletionCallbackFxn; /** * \brief argument to be returned by the call back function @ref transferCompletionCallbackFxn. */ uintptr_t transferCompletionCallbackFxnArg; } EDMA_paramConfig_t; /*! * @brief Error configuration for a transfer controller, allows enabling/disabling * of various error conditions. */ typedef struct EDMA_transferControllerErrorConfig_t_ { /*! @brief ERREN::BUSERR in EDMA UG. */ _Bool isBusErrorEnabled; /*! @brief ERREN::TRERR in EDMA UG. */ _Bool isTransferRequestErrorEnabled; /*! @brief ERREN:MMRAERR in EDMA UG. */ _Bool isWriteToReservedConfigMemoryMapEnabled; } EDMA_transferControllerErrorConfig_t; /*! * @brief Error configuration for transfer controller, allows enabling/disabling * of various error conditions. */ typedef struct EDMA_errorConfig_t_ { /*! @brief Set to true if want to configure all event queues. */ _Bool isConfigAllEventQueues; /*! @brief if @ref isConfigAllEventQueues is false, used to specify the event queue to be configured. */ uint8_t eventQueueId; /*! @brief Set to true if want to enable event queue thresholding. */ _Bool isEventQueueThresholdingEnabled; /*! @brief event Queue threshold, should be in the range * [0, @ref EDMA_EVENT_QUEUE_THRESHOLD_MAX], convenient defines in * @ref EDMA_EVENT_QUEUE_THRESHOLD */ uint8_t eventQueueThreshold; /*! @brief Set to true if want to configure all transfer controllers. */ _Bool isConfigAllTransferControllers; /*! @brief If @ref isConfigAllTransferControllers is false, used to specify the transfer controler Id to be configured. */ uint8_t transferControllerId; /*! @brief Set to true if want to enable all transfer controller errors, * this is provided for convenience so as not to have to specific each * error in @ref transferControllerErrorConfig. */ uint8_t isEnableAllTransferControllerErrors; /*! @brief If @ref isEnableAllTransferControllerErrors is false, used to * specify which errors to enable. */ EDMA_transferControllerErrorConfig_t transferControllerErrorConfig; /*! @brief Call back function associated with CC errors. */ EDMA_errorCallbackFxn_t callbackFxn; /*! @brief Call back function associated with queue/TC (Transfer Controller) * errors. */ edmaTransferControllerErrorCallbackFxn_t transferControllerCallbackFxn; } EDMA_errorConfig_t; /*! * @brief Queue entry information. */ typedef struct EDMA_queueEntryInfo_t_ { /*! @brief QxEy::ENUM in EDMA UG. */ uint8_t eventNumber; /*! @brief QxEy::ETYPE in EDMA UG. */ uint8_t eventType; } EDMA_queueEntryInfo_t; /*! * @brief Queue status information. */ typedef struct EDMA_queueStatusInfo_t_ { /*! @brief Outstanding entries are entries in the queue at the moment of status query that have not yet been serviced. The number of relevant entries in this array is @ref numOutstandingEntries. */ EDMA_queueEntryInfo_t outstandingEntries[((uint8_t)16)]; /*! @brief Dequeued entries are entries in the queue at the moment of querying the queue status that have been serviced, the number of relevant entries in this array is @ref EDMA_NUM_QUEUE_ENTRIES - @ref numOutstandingEntries. */ EDMA_queueEntryInfo_t dequeuedEntries[((uint8_t)16)]; /*! @brief status whether queue threshold is exceeded. */ _Bool isThresholdExceeded; /*! @brief Maximum number of entries ever in the queue since EDMA became operational (after reset), if this maximum ever exceeded the set queue threshold and queue thresholding were enabled, it would trigger error condition. */ uint8_t maxQueueEntries; /*! @brief Number of outstanding (not yet serviced) entries in the queue, QSTATN::NUMVAL in EDMA UG. */ uint8_t numOutstandingEntries; } EDMA_queueStatusInfo_t; /*! * @brief EDMA status information at the time of querying status * using @ref EDMA_getStatusInfo. This is not some software state but it is * hardware state, typically used for debugging purposes. * Note CCSTAT::QUEACTVx bits are not reported because they are redundant information * given the @ref EDMA_queueStatusInfo_t_. */ typedef struct EDMA_statusInfo_t_ { /*! @brief Queue status of each queue, number of entries that are relevant are the number of queues in the EDMA instance from call to @ref EDMA_open in the returned structure @ref EDMA_instanceInfo_t_::numEventQueues. */ EDMA_queueStatusInfo_t queue[((uint8_t)8)]; /*! @brief CCSTAT::COMPACTV in EDMA UG. */ uint8_t numOutstandingCompletionRequests; /*! @brief CCSTAT::EVTACTV in EDMA UG. */ _Bool isAnyDmaChannelActive; /*! @brief CCSTAT::QEVTACTV in EDMA UG. */ _Bool isAnyQdmaChannelActive; /*! @brief CCSTAT::WSTATACTV in EDMA UG. */ _Bool isWriteStatusActive; /*! @brief CCSTAT::TRACTV in EDMA UG. */ _Bool isAnyTransferActive; /*! @brief CCSTAT::ACTV in EDMA UG. */ _Bool isAnythingActive; } EDMA_statusInfo_t; /*! * @brief EDMA performance configuration. */ typedef struct EDMA_performanceConfig_t_ { /*! @brief If set to true, configures all transfer controllers with specified configuration (@ref transferControllerId is not relevant). */ _Bool isConfigAllTransferControllers; /*! @brief If @ref isConfigAllTransferControllers is false, then configures the transfer controller of this Id. */ uint8_t transferControllerId; /*! @brief Read rate is used to specify using @ref EDMA_READ_RATE_DEFINES the aggressiveness of read by the transfer controller, less cycles means more aggressive, see RDRATE in EDMA UG. */ uint8_t transferControllerReadRate; /*! @brief Queue priority, the defines EDMA_TPCC_QUEPRI_PRIQ0_PRIORITYX can be used here, where X is in the range [0,7], Note: 0 is highest priority and 7 is lowest. Refer to QUEPRI in EDMA UG. */ uint8_t queuePriority; } EDMA_performanceConfig_t; /*! * @brief EDMA instance properties information. */ typedef struct EDMA_instanceInfo_t_ { /*! @brief Number of event queues, same as number of transfer controllers */ uint8_t numEventQueues; /*! @brief Number of PaRAM sets. */ uint16_t numParamSets; /*! @brief Shows if channel mapping feature is supported. If this is supported (true) then it is possible to associate any DMA channel with any PaRAM set, otherwise (false), the PaRAM set must be identical to DMA channel i.e DMA channels 0 to 63 correspond to PaRAM sets 0 to 63 respectively. */ _Bool isChannelMapExist; /*! @brief true if transfer completion interrupt is routed from EDMA to the processor interrupt controller. */ _Bool isTransferCompletionInterruptConnected; /*! @brief true if error interrupt is is routed from EDMA to the processor interrupt controller. */ _Bool isErrorInterruptConnected; /*! @brief true if a transfer controller error interrupt is is routed from EDMA to the processor interrupt controller. */ _Bool isTransferControllerErrorInterruptConnected[((uint8_t)8)]; } EDMA_instanceInfo_t; /** @defgroup EDMA_DRIVER_EXTERNAL_FUNCTION EDMA Driver External Functions @brief * The section has a list of all the exported APIs which the application can * invoke in order to use the driver. @{ */ /** * @b Description * @n * Configure a channel. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] config * pointer to @ref EDMA_channelConfig_t_ * @param[in] isEnableChannel * set to true if you want to enable the channel after configuration * else set to false. For false case, it is expected that the * channel will be enabled at a later time * using @ref EDMA_enableChannel for event triggered DMA channel events or * QDMA channels. * Note for DMA events that are intended not to be event triggered i.e * manual triggered or chain triggered only, this flag should be set to * false else a real event appearing on the event line may unintentionally * trigger the DMA channel. * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_configChannel(EDMA_Handle handle, EDMA_channelConfig_t const *config, _Bool isEnableChannel); /** * @b Description * @n * Enable a channel. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] channelId * 0 to (@ref EDMA_NUM_DMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_DMA. \n * 0 to (@ref EDMA_NUM_QDMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_QDMA. * @param[in] channelType * channelType can be either @ref EDMA3_CHANNEL_TYPE_DMA or @ref EDMA3_CHANNEL_TYPE_QDMA. * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_enableChannel(EDMA_Handle handle, uint8_t channelId, uint8_t channelType); /** * @b Description * @n * Disable a channel. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] channelId * 0 to (@ref EDMA_NUM_DMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_DMA. \n * 0 to (@ref EDMA_NUM_QDMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_QDMA. * @param[in] channelType * channelType can be either @ref EDMA3_CHANNEL_TYPE_DMA or @ref EDMA3_CHANNEL_TYPE_QDMA. * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_disableChannel(EDMA_Handle handle, uint8_t channelId, uint8_t channelType); /** * @b Description * @n * Chain channels. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] fromParamId * Param Id of the channel from which to chain. * @param[in] toChannelId * channel Id of the channel to which to chain to. * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_chainChannels(EDMA_Handle handle, uint16_t fromParamId, uint8_t toChannelId); /** * @b Description * @n * Configure Param Set * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] paramId PaRAM Set Id of the PaRAM Set to be configured. * @param[in] config * Pointer to @ref EDMA_paramConfig_t * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_configParamSet(EDMA_Handle handle, uint16_t paramId, EDMA_paramConfig_t const *config); /** * @b Description * @n * Link Param Sets. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] fromParamId * Param Id from which to link * @param[in] toParamId * Param Id to which to link * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_linkParamSets(EDMA_Handle handle, uint16_t fromParamId, uint16_t toParamId); /** * @b Description * @n * Start a transfer. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] channelId * 0 to (@ref EDMA_NUM_DMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_DMA \n * 0 to (@ref EDMA_NUM_QDMA_CHANNELS - 1) when channelType is @ref EDMA3_CHANNEL_TYPE_QDMA * @param[in] channelType * channelType can be either @ref EDMA3_CHANNEL_TYPE_DMA or @ref EDMA3_CHANNEL_TYPE_QDMA * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_startTransfer(EDMA_Handle handle, uint8_t channelId, uint8_t channelType); /** * @b Description * @n * Start a DMA channel transfer. It is a simpler/faster version of @ref EDMA_startTransfer * when channel is known to be of type DMA. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] channelId * 0 to (@ref EDMA_NUM_DMA_CHANNELS - 1) * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_startDmaTransfer(EDMA_Handle handle, uint8_t channelId); /** * @b Description * @n * Start a QDMA channel transfer. It is a simpler/faster version of * @ref EDMA_startTransfer when channel is known to be of type QDMA. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] channelId * 0 to (@ref EDMA_NUM_QDMA_CHANNELS - 1) * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_startQdmaTransfer(EDMA_Handle handle, uint8_t channelId); /** * @b Description * @n * Start final QDMA transfer. It modifies OPT field's STATIC bit to 1 before * triggering QDMA, useful for multi-transfer type configurations (A-type transfer * where the product of bCount and cCount is greater than 1 or AB-type transfer where * cCount is greater than 1) where last but one transfer must have STATIC bit * to be 0 and the last transfer needs STATIC to be 1 to prevent a NULL transfer error. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] channelId * 0 to (@ref EDMA_NUM_QDMA_CHANNELS - 1) * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_startFinalQdmaTransfer(EDMA_Handle handle, uint8_t channelId); /** * @b Description * @n * Query for transfer completion. This function will return an error * if transfer completion callback function for the supplied transferCompletionCode * is configured as non NULL. This is because the burden of clearing the channel * is not in the call back but in the driver after the user supplied call back is called. * So polling on a cleared channel would give wrong result i.e indicate transfer * is not complete even when it has completed. The call back completion * and this API are exclusionary. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] transferCompletionCode * which transfer completion code to query, range is [0,(@ref EDMA_NUM_TCC - 1)] * @param[out] isTransferComplete * true if transfer is complete, false otherwise. NOTE: If true, then * IPR(H) bit of the completed transfer will be cleared, allowing for a new * transfer to complete. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_isTransferComplete(EDMA_Handle handle, uint8_t transferCompletionCode, _Bool *isTransferComplete); /** * @b Description * @n * Set Destination Address of PaRAM. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] paramId * Id of the the PaRAM * @param[in] destinationAddress * Destination address. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_setDestinationAddress(EDMA_Handle handle, uint16_t paramId, uint32_t destinationAddress); /** * @b Description * @n * Set Source Address of PaRAM. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] paramId * Id of the the PaRAM * @param[in] sourceAddress * Source address. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_setSourceAddress(EDMA_Handle handle, uint16_t paramId, uint32_t sourceAddress); /** * @b Description * @n * Set Acnt and Bcnt of PaRAM. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] paramId * Id of the the PaRAM * @param[in] Acnt * Acnt (number of contiguous bytes) * @param[in] Bcnt * Bcnt (number of repeats) * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ int32_t EDMA_setABcnt(EDMA_Handle handle, uint16_t paramId, uint16_t Acnt, uint16_t Bcnt); /** * @b Description * @n * Configure Error monitoring. The EDMA IP has several features * for monitoring errors in the CC and TC as described in EDMA UG : * - Missed events.\n * - Exceeding of queue threshold.\n * - Bus error caused due to read/writes in transfers where addresses go * out of bounds of physical memory (i.e where EDMA IP * does not get any ACK back).\n * - Read/writes to invalid/reserved addresses in CC/TC register memory map.\n * - Exceeding of outstanding transfer controller codes.\n * * This API allows selective control (where available in h/w) * of what to monitor. It should be called during init time. * It is important to issue this API for safety, besides being useful in debugging. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] config * pointer to error configuration @ref EDMA_errorConfig_t_. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_configErrorMonitoring(EDMA_Handle handle, EDMA_errorConfig_t const *config); /** * @b Description * @n * Query Error Status of EDMA. This API is used for polling and getting * EDMA error status if poll indicates there was an error. This is useful * in some devices where the EDMA's error interrupt is not physically wired * to the interrupt controller of the processor but EDMA peripheral registers are * accessible. When interrupt is connected, this API is not necessary because the error * ISR will call out the user provided call back function (@ref EDMA_errorConfig_t::callbackFxn) * when issuing @ref EDMA_configErrorMonitoring. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[out] isAnyError * true if any EDMA error is detected, else false * @param[out] errorInfo * Pointer to error information, this is populated if any EDMA error is detected. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES * */ extern int32_t EDMA_getErrorStatus(EDMA_Handle handle, _Bool *isAnyError, EDMA_errorInfo_t *errorInfo); /** * @b Description * @n * Query Error Status of EDMA's transfer controller. This API is used for * polling and getting EDMA transfer controller error status if poll indicates * there was an error. This is useful in some devices where the EDMA's transfer controller * interrupt is not physically wired to the interrupt controller of the processor * but EDMA peripheral registers are accessible. When interrupt is connected, * this API is not necessary because the error ISR will call out the user * provided call back function (@ref EDMA_errorConfig_t::transferControllerCallbackFxn) * when issuing @ref EDMA_configErrorMonitoring. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[in] transferControllerId * Transfer Controller Id * @param[out] isAnyError * true if any EDMA transfer controller error is detected, else false * @param[out] errorInfo * Pointer to error information, this is populated if any EDMA error is detected. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES * */ extern int32_t EDMA_getTransferControllerErrorStatus(EDMA_Handle handle, uint8_t transferControllerId, _Bool *isAnyError, EDMA_transferControllerErrorInfo_t *errorInfo); /** * @b Description * @n * Query Status of EDMA. This is useful for debugging/diagnostic purposes. * Typically called in the implementation of the error call back function * of the application supplied in the @ref EDMA_errorConfig_t_::callbackFxn * and/or @ref EDMA_errorConfig_t_::transferControllerCallbackFxn when * issuing @ref EDMA_configErrorMonitoring, for additional post-mortem analysis. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open * @param[out] status * status output * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_getStatusInfo(EDMA_Handle handle, EDMA_statusInfo_t *status); /** * @b Description * @n * Configure Performance parameters. This is useful for performance tuning * of transfer controllers relative to each other and priority of EDMA * issue on the bus with respect to rest of IPs for memory access. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * @param[in] config * Performance configuration input. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_configPerformance(EDMA_Handle handle, EDMA_performanceConfig_t const *config); /** * @b Description * @n * Open a specified EDMA instance. * * @param[in] instanceId * Instance Id to open, range is [0, number of instances-1], where * number of instances is obtained from a call to @ref EDMA_getNumInstances. * @param[out] errorCode * One of @ref EDMA_ERROR_CODES if there is an error, otherwise @ref EDMA_NO_ERROR. * @param[out] instanceInfo * Instance information. * * @retval * Handle to the EDMA instance. If errorCode returns an error i.e * is not @ref EDMA_NO_ERROR, then handle is NULL. */ extern EDMA_Handle EDMA_open(uint8_t instanceId, int32_t *errorCode, EDMA_instanceInfo_t *instanceInfo); /** * @b Description * @n * Close EDMA instance. * * @param[in] handle * Handle to the EDMA instance obtained through call to @ref EDMA_open. * * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_close(EDMA_Handle handle); /** * @b Description * @n * Get number of EDMA instances on the device. * @retval * Number of EDMA instances. */ extern uint8_t EDMA_getNumInstances(void); /** * @b Description * @n * Initialize specified EDMA instance. Performs the following: * - Disables and clears events. * - Disables and clears interrupts. * - Clears error state. * - Sets all PaRAM sets to all zeroes (hardware reset state). * * @param[in] instanceId * Id of the instance to be initialized. * @retval * Success - @ref EDMA_NO_ERROR * @retval * Error - one of @ref EDMA_ERROR_CODES */ extern int32_t EDMA_init(uint8_t instanceId); /** @}*/ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @file hwa.h * * @brief HWA driver interface * */ /** @mainpage HWA Driver * * The HWA driver provides APIs to configure, trigger and obtain results from the * hardware accelerator * * The HWA header file should be included in an application as follows: * @code * #include * @endcode * * ## Initializing the driver # * The HWA Driver needs to be initialized once across the System. This is * done using the #HWA_init. None of the HWA API can be used without invoking * this API * * ## Opening the driver # * Once the HWA Driver has been initialized; the HWA Driver instance can be opened * using the #HWA_open. The #HWA_open can be called multiple times from different * context to obtain a valid HWA handle. However, only the first call to #HWA_open will * perform the hardware initialization. Other subsequent calls will just return the already * open handle. * * @code * @endcode * * ## Using the driver # * Following is a psuedo code for using the HWA driver * * @code * HWA_Handle handle; HWA_init(); handle = HWA_open(0, &errCode); * @endcode * Refer to the API (function and structures) documentation for more details on how to * use the HWA driver. * * __Note:__ * All the API params which are output of the API have been marked with the keyword [__out__]. * If there is no such qualifier present, then it is safe to assume that that parameter is input only. * * ## Instrumentation # * Uses DebugP_log functions for debug messages * * ## Hardware Register Map # * The hardware register map used by this driver can be found at * include/reg_dsshwacc.h and include/reg_dsshwaccparam.h * * ============================================================================ */ /** @defgroup HWA_DRIVER_EXTERNAL_FUNCTION HWA Driver External Functions @ingroup HWA_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup HWA_DRIVER_EXTERNAL_DATA_STRUCTURE HWA Driver External Data Structures @ingroup HWA_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup HWA_DRIVER_ERROR_CODE HWA Driver Error Codes @ingroup HWA_DRIVER @brief * The section has a list of all the error codes which are generated by the HWA Driver * module */ /** @addtogroup HWA_DRIVER_ERROR_CODE * * @brief * Base error code for the HWA module is defined in the ti/common/mmwave_error.h * \include ti/common/mmwave_error.h * @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Operation cannot be done as HWA_init is not done. */ /** * @brief Error Code: input argument out of range */ /** * @brief Error Code: out of memory */ /** * @brief Error Code: feature not supported */ /** * @brief Error Code: channel or resource in use */ /** * @brief Error Code: address is not aligned to the expected boundary */ /** @}*/ /** @addtogroup HWA_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /** * @defgroup HWA_MACROS HWA_MACROS * @brief Lists all the macros used in HWA driver * @{ */ /** * @defgroup HWA_FEATURE_BIT HWA_FEATURE_BIT * @brief General macro to use for enable/disable bits * @{ */ /** @}*/ /*HWA_FEATURE_BIT*/ /** * @defgroup HWA_SAMPLES_WIDTH HWA_SAMPLES_WIDTH * @brief Macros that define values for 16bit or 32bit width of input/output samples * @{ */ /** @}*/ /*HWA_SAMPLES_WIDTH*/ /** * @defgroup HWA_SAMPLES_FORMAT HWA_SAMPLES_FORMAT * @brief Macros that define values for real/complex format of input/output samples * @{ */ /** @}*/ /*HWA_SAMPLES_FORMAT*/ /** * @defgroup HWA_SAMPLES_SIGN HWA_SAMPLES_SIGN * @brief Macros that define values for signed/unsigned property of input/output samples * @{ */ /** @}*/ /*HWA_SAMPLES_SIGN*/ /** * @defgroup HWA_WINDOW_SYMM HWA_WINDOW_SYMM * @brief Macros that define values for symmetric/non-symmetric property of the FFT window * @{ */ /** @}*/ /*HWA_WINDOW_SYMM*/ /** * @defgroup HWA_FFT_WINDOW_INTERPOLATE_MODE HWA_FFT_WINDOW_INTERPOLATE_MODE * @brief Macros that define values for interpolation property of the FFT window to * acheive larget FFT size using stitching * @{ */ /** @}*/ /*HWA_FFT_WINDOW_INTERPOLATE_MODE*/ /** * @defgroup HWA_FFT_MODE_MAGNITUDE_LOG2 HWA_FFT_MODE_MAGNITUDE_LOG2 * @brief Macros that define values for enabling/disabling the magniude and log2 computation in FFT block * @{ */ /** @}*/ /*HWA_FFT_MODE_MAGNITUDE_LOG2*/ /** * @defgroup HWA_FFT_MODE_OUTPUT HWA_FFT_MODE_OUTPUT * @brief Macros that define values for the various outputs of the FFT block * @{ */ /** @}*/ /*HWA_FFT_MODE_OUTPUT*/ /** * @defgroup HWA_NOISE_AVG_MODE_CFAR HWA_NOISE_AVG_MODE_CFAR * @brief Macros that define values for CFAR Noise Averaging mode * @{ */ /** @}*/ /*HWA_NOISE_AVG_MODE_CFAR*/ /** * @defgroup HWA_TRIG_MODE HWA_TRIG_MODE * @brief Macros that define values for the trigger mode of HWA paramsets * @{ */ /** @}*/ /*HWA_TRIG_MODE*/ /** * @defgroup HWA_ACCELMODE HWA_ACCELMODE * @brief Macros that define values for the operational/accelerator mode of HWA * @{ */ /** @}*/ /*HWA_ACCELMODE*/ /** * @defgroup HWA_CFAR_OPER_MODE HWA_CFAR_OPER_MODE * @brief Macros that define values for the combination of CFAR operational mode (log, mag, mag sqr) * and input samples type (real, complex) * * *Value |CFAR_LOG_MODE |CFAR_INP_MODE |CFAR_ABS_MODE |register bits|description *-------| --------------|---------------|--------------|-------------|------------- * 0 | 1| 1|dont care | 1100 |input are real, log-magnitude samples and no operation is needed inside HWA * 1 | 1| 0|3 | 0111 |input are complex samples and HWA should perform log-magnitude operation * 2 | 0| 1|dont care | 1000 |input are real, magnitude samples and no operation is needed inside HWA * 3 | 0| 0|2 | 0010 |input are complex samples and HWA should perform magnitude operation * 4 | 0| 1|dont care | 1000 |input are real, magnitude-sqr samples and no operation is needed inside HWA * 5 | 0| 0|0 | 0000 |input are complex samples and HWA should perform magnitude-sqr operation * @{ */ /** @}*/ /*HWA_CFAR_OPER_MODE*/ /** * @defgroup HWA_CFAR_OUTPUT_MODE HWA_CFAR_OUTPUT_MODE * @brief Macros that define values for the output of CFAR block * and input samples type (real, complex) * @details * Value | I channel | Q channel * ------ | ---------------------------------------|------------- * 0 | Noise average values for all cells | Cell under test * 1 | Noise average values for all cells | Binary detection flag * 2 | Peak Index | Surrounding noise value * 3 | Peak Index | Cell under test value * @{ */ /** @}*/ /*HWA_CFAR_OUTPUT_MODE*/ /** * @defgroup HWA_COMPRESS_MODE HWA_COMPRESS_MODE * @brief Macros that define values for the selecting either the * compression or the decompression mode of CMP_DCMP_Engine * @details * Value | Mode * ------ | ------------------ * 0 | Compression * 1 | Decompression * @{ */ /** @}*/ /*HWA_COMPRESS_MODE*/ /** * @defgroup HWA_CMP_MISC_PARAMS HWA_CMP_MISC_PARAMS[ * @brief Macro that defines the length of the EGE k-parameter array. * @{ */ /** @}*/ /*HWA_CMP_MISC_PARAMS*/ /** * @defgroup HWA_CMP_METHOD HWA_CMP_METHOD * @brief Macros that define the compression method * @details * Value | Mode * ------ | ------------------ * 0 | EGE Compression/Decompression * @{ */ /** @}*/ /*HWA_CMP_METHOD*/ /** * @defgroup HWA_COMPRESS_PATHSELECT HWA_COMPRESS_PATHSELECT * @brief Macros that allow/disallow two pass operation for compression. * the first pass (optimization step) finds the optimal parameters * for compression and the second pass compresses the data and writes * it to the output buffer. * Both first and second passes should be enabled. * @details * Value | Mode * ------ | ------------------ * 3 | 1st and 2nd pass are enabled * @{ */ /** @}*/ /*HWA_COMPRESS_PATHSELECT*/ /** * @defgroup HWA_RAM_TYPE HWA_RAM_TYPE * @brief Macros that define values for the ramType argument of HWA_configRam() function. * @{ */ /** @}*/ /*HWA_RAM_TYPE*/ /** * @defgroup HWA_PARAMDONE_INTERRUPT_TYPE HWA_PARAMDONE_INTERRUPT_TYPE * @brief Macros that define values for the destination of interrupt (CPU or DMA) when the paramset is completed. The interrupt type HWA_PARAMDONE_INTERRUPT_TYPE_CPU may not be supported on all versions of the IP - see value for \ref HWA_HWAttrs_t::isConcurrentAccessAllowed in hwa_ files. * @{ */ /** @}*/ /*HWA_PARAMDONE_INTERRUPT_TYPE*/ /** * @defgroup HWA_COMMONCONFIG_MASK HWA_COMMONCONFIG_MASK * @brief Macros that define values to use for \ref HWA_CommonConfig_t::configMask when specifying which values in * the \ref HWA_CommonConfig_t are valid. * @{ */ /** @}*/ /*HWA_COMMONCONFIG_MASK*/ /** * @defgroup HWA_COMPLEX_MULTIPLY_MODE HWA_COMPLEX_MULTIPLY_MODE * @brief Macros that define values for the various modes of the Complex multiply block * @{ */ /** @}*/ /*HWA_COMPLEX_MULTIPLY_MODE*/ /** * @defgroup HWA_FFT_STITCHING_TWID_PATTERN HWA_FFT_STITCHING_TWID_PATTERN * @brief Macros that define values for the various modes of the Complex multiply block block * @{ */ /** @}*/ /*HWA_FFT_STITCHING_TWID_PATTERN*/ /** @}*/ /*end of HWA_MACROS group*/ /*! * @brief A handle that is returned from a HWA_open() call. */ typedef void* HWA_Handle; /*! * @brief HWA Interrupt callback function after every paramset completion * * HWA Interrupt callback function to be used with HWA_enableParamSetInterrupt() call * */ typedef void (*HWA_ParamDone_IntHandlerFuncPTR)(uint32_t paramSet, void * arg); /*! * @brief HWA Interrupt callback function after all paramsets completion * * HWA Interrupt callback function to be used with HWA_enableDoneInterrupt() call * */ typedef void (*HWA_Done_IntHandlerFuncPTR)( void * arg); /*! * @brief HWA H/W Parameters * * HWA parameters are used to with the HWA_open() call. * */ typedef struct HWA_HWAttrs_t { uint32_t instanceNum; /*!< HWA Instance num - this is related to actual H/W instance of this IP */ volatile uint32_t ctrlBaseAddr; /*!< HWA Peripheral's base address for the control/common register space */ volatile uint32_t paramBaseAddr; /*!< HWA Peripheral's base address for the paramset space */ volatile uint32_t ramBaseAddr; /*!< HWA Peripheral's base address for the Window/Internal RAM space */ volatile uint32_t dssBaseAddr; /*!< DSS base address for the common settings */ uint32_t numHwaParamSets; /*!< Number of HWA paramsets in this instance */ uint32_t intNumParamSet; /*!< HWA Peripheral's interrupt vector for individual paramset completion*/ uint32_t intNumDone; /*!< HWA Peripheral's interrupt vector for completion of all programmed paramset*/ uint32_t numDmaChannels; /*!< Number of DMA channels available for HWA (src or dst) */ volatile uint32_t accelMemBaseAddr; /*!< HWA Accelerator processing memory base address */ uint32_t accelMemSize; /*!< HWA Accelerator processing memory size in bytes */ _Bool isConcurrentAccessAllowed; /*!< Flag to say if read access of Common Registers is allowed in hardware when HWA is executing paramsets */ _Bool isCompressionEnginePresent; /*!< Flag to say if the compression engine is present in hardware.*/ } HWA_HWAttrs; /*! * @brief Source trigger DMA parameters * * Source trigger DMA parameters that the user can use to configure a generic DMA channel to trigger the HWA * * Note: source and destination addresses represent CPU view of HWA address. * Depending on the SOC and the dma engine which is used for transfer, they may need to be translated by caller. * * Example: SOC_translateAddr API with SOC_TranslateAddr_Dir_TO_EDMA should be used * when passing it to EDMA API for configuration. */ typedef struct HWA_SrcDMAConfig_t { uint32_t srcAddr; /*!< source Address for the DMA programming */ uint32_t destAddr; /*!< destination Address for the DMA programming */ uint16_t aCnt; /*!< A count for the DMA programming */ uint16_t bCnt; /*!< B count for the DMA programming */ uint16_t cCnt; /*!< C count for the DMA programming */ } HWA_SrcDMAConfig; /*! * @brief HWA Common Config * * HWA common config parameters that are used with the HWA_ConfigCommon() call. * */ typedef struct HWA_CommonConfig_t { uint32_t configMask; /*!< See \ref HWA_COMMONCONFIG_MASK macros for correct values. Set this to specify which of the fields are valid when calling HWA_ConfigCommon API. */ uint16_t numLoops; /*!< number of loops to run from paramStartIdx to paramStopIdx valid value (12 bits): 0-4094; 4095 for infinitie. Sets the NUMLOOPS */ uint8_t paramStartIdx; /*!< start index of paramset through which state machine loops through valid value: 4bits (0-15) Sets the PARAMSTART */ uint8_t paramStopIdx; /*!< stop index of paramset through which state machine loops through valid value: 4bits (0-15) Sets the PARAMSTOP */ struct { uint8_t fft1DEnable; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Setting to 1 enables HWA in FFT1D mode - ACCEL_MEM0 and ACCEL_MEM1 are assumed to be shared with the ping-pong ADC buffers. At the end of the active transmission portion of a frame, this bit can be reset, so that the accelerator has access to all the four local memories independently. Sets FFT1DEN bit of HWACCREG1 */ uint16_t bpmRate; /*!< 10 bit value: specifies the number of input samples corresponding to each BPM chip. value of 0 is invalid Sets BPMRATE bits in HWACCREG7 */ uint32_t bpmPattern[2]; /*!< 64-bit value: specifies a Binary Phase Modulation (BPM) pattern to be removed on the input samples prior to FFT Sets HWACCREG5 (MSB,bpmPattern[1]) and HWACCREG6 (LSB,bpmPattern[0]) registers */ uint32_t interferenceThreshold; /*!< 24-bit value: Interference zero-out threshold - is used to zero-out sample(s), whose magnitude (24-bit absolute value of the 24-bit complex input) is very high, prior to computing the FFT The HWA_AccelModeFFT_t::interfZeroOutEn field should be enabled in the intended paramset for this threshold to be used*/ uint8_t twidDitherEnable; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Setting to 1 Enable Dithering for Twiddle Factors It is recommended to keep this register bit always set to 1 (i.e., dithering enabled) Sets the DITHERTWIDEN bit in HWACCREG7 register */ uint32_t lfsrSeed; /*!< 29-bit value: LFSR seed. Sets the LFSRSEED bits in HWACCREG11 */ uint8_t fftSumDiv; /*!< 5-bit value: specifies the number of bits to right-shift the sum statistic (36-bit) before it is written to destination memory (24-bit) Sets the FFTSUMDIV bits in HWACCREG8 register */ } fftConfig; struct { uint32_t cfarThresholdScale; /*!< 18-bit value: specifies the threshold scale factor that is used to either multiply or add to the 'surrounding noise average' to determine the threshold used for detection of the present cell under test in log mode, this value should be represented as 7.11. in mag/mag-sqr mode, this value should be represented as 14.4. Sets the CFAR_THRESH bits in HWACCREG13 register */ } cfarConfig; struct { uint32_t i_cmult_scale; /*!< 21 bit value: real part of the scalar complex number used for scalar mult mode i.e. \ref HWA_ComplexMultiply_t::mode=HWA_COMPLEX_MULTIPLY_MODE_SCALAR_MULT Sets the ICMULT_SCALE bits of HWACCREG9 */ uint32_t q_cmult_scale; /*!< 21 bit value: imaginary part of the scalar complex number used for scalar mult mode i.e. \ref HWA_ComplexMultiply_t::mode=HWA_COMPLEX_MULTIPLY_MODE_SCALAR_MULT Sets the ICMULT_SCALE bits of HWACCREG10 */ } scalarMult; struct { uint8_t EGEKparam[(8U)]; /*!< An Array of length 8 consisting of 5 bit values: list of k-parameters to be optimized during EGE compression. Sets the ICMULT_SCALE bits of HWACCREG9 */ } compressMode; } HWA_CommonConfig; /*! * @brief HWA Paramset Config for Input Formatter/Source block * * HWA paramset config parameters for the Input Formatter/Source block inside HWA_ParamConfig which is used with the HWA_ConfigParamSet() call. * */ typedef struct HWA_SourceConfig_t { uint16_t srcAddr; /*!< 16 bit value: specifies the starting address of the input samples in the accelerator memory. Value of 0x0000 points to the first byte of accelerator memory and 16-bit value covers the entire address space of the four memories (4x16KB=64 KB) Sets the SRCADDR bits of PARAM1_1 */ uint16_t srcAcnt; /*!< 12 bit value: specifies the number of samples (minus 1) from the source memory to process for every iteration. Note: The unit is samples and not bytes. Sets the SRCACNT bits of PARAM1_2 */ int16_t srcAIdx; /*!< 16 bit value: specifies the number of bytes separating successive samples in the source memory Sets the SRCAINDX bits of PARAM1_3 */ uint16_t srcBcnt; /*!< 12 bit value: specifies the number of times (minus 1) the processing should be iterated Sets the BCNT bits of PARAM1_5 */ int16_t srcBIdx; /*!< 16 bit value: Specifies the number of bytes separating the start address of samples for successive iterations in the source memory (in bytes, signed value) Sets the SRCBIDX bits in PARAM1_4 */ uint16_t srcShift; /*!< 12 bit value: specifies the circular shift (offset in samples) that should be applied on the sequence of input samples before feeding them to the Core Computational unit Sets the CIRCIRSHIFT bits of PARAM1_7 */ uint8_t srcCircShiftWrap; /*!< 4 bit value: indicates at what number (power-of-2) the sample count value should wraparound, when using circular shift. Sets the CIRCSHIFTWRAP bits of PARAM1_7 */ uint8_t srcRealComplex; /*!< 1 bit value: See \ref HWA_SAMPLES_FORMAT macros for correct values. Real or Complex data in the source memory. Sets the SRCREAL bits in PARAM1_2*/ uint8_t srcWidth; /*!< 1 bit value: See \ref HWA_SAMPLES_WIDTH macros for correct values. 16-bit or 32-bit data width in source memory. Sets the SRC16b32b bits in PARAM1_2 */ uint8_t srcSign; /*!< 1 bit value: See \ref HWA_SAMPLES_SIGN macros for correct values. Signed or Unsigned data in the source memory. This setting is only relevant for srcWidth=0 (16 bits), because that is when sign-extension may be required to convert to internal 24-bit width. Sets the SRCSIGNED bits in PARAM1_2 */ uint8_t srcConjugate; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable Conjugation of the input samples. 0: No conjugation 1: Enable conjugation This register only makes sense for srcRealComplex=0 (complex). It is useful in conjunction with DSTCONJ to derive an IFFT mode (by conjugating at both input and output) Sets the SRCCONJ bit of PARAM1_2 */ uint8_t srcScale; /*!< 4 bit value: Specifies a programmable scaling, via right bit-shift, from 0 bits to 8 bits, for the input samples. Sets the SRCSCAL bits of PARAM1_5 (0-8). if HWA_SourceConfig::srcWidth = HWA_SAMPLES_WIDTH_16BIT, the 24-bit sample is generated by padding (8-SRCSCAL) zeros at the LSB and SRCSCAL redundant MSBs (sign-extended based on \ref srcSign). if HWA_SourceConfig::srcWidth = HWA_SAMPLES_WIDTH_32BIT, the 24-bit sample is generated by dropping SRCSCAL bits at the LSB and clipping (8-SRCSCAL) bits at the MSB */ uint8_t bpmEnable; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable for BPM removal operation 0: disable 1: enable Sets the BPM_EN bits of PARAM1_0*/ uint8_t bpmPhase; /*!< 4 bit value: Specifies the starting phase of the BPM pattern to be applied Sets the BPMPHASE bits of PARAM1_6*/ } HWA_SourceConfig; /*! * @brief HWA Paramset Config for Output Formatter/Destination block * * HWA paramset config parameters for the Output Formatter/Destination block inside HWA_ParamConfig which is used with the HWA_ConfigParamSet() call. * */ typedef struct HWA_DestConfig_t { uint16_t dstAddr; /*!< 16 bit value: specifies the starting address of the output samples in the accelerator memory. Value of 0x0000 points to the first byte of accelerator memory and 16-bit value covers the entire address space of the four memories (4x16KB=64 KB) Sets the DSTADDR bits of PARAM1_1 */ uint16_t dstAcnt; /*!< 12 bit value: specifies the number of samples (minus 1) from the destination memory to process for every iteration. Note: The unit is samples and not bytes. Sets the DSTACNT bits of PARAM1_2 */ int16_t dstAIdx; /*!< 16 bit value: specifies the number of bytes separating successive samples in the destination memory Sets the DSTAINDX bits of PARAM1_3 */ int16_t dstBIdx; /*!< 16 bit value: Specifies the number of bytes separating the start address of samples for successive iterations in the destination memory (in bytes, signed value) Sets the DSTBIDX bits in PARAM1_4 */ uint8_t dstRealComplex; /*!< 1 bit value: See \ref HWA_SAMPLES_FORMAT macros for correct values. Real or Complex data in the destination memory. Sets the DSTREAL bits in PARAM1_2*/ uint8_t dstWidth; /*!< 1 bit value: See \ref HWA_SAMPLES_WIDTH macros for correct values. 16-bit or 32-bit alignment of data in destination memory. Sets the DST16b32b bits in PARAM1_2 */ uint8_t dstSign; /*!< 1 bit value: See \ref HWA_SAMPLES_SIGN macros for correct values. Signed or Unsigned data in the destination memory. This setting is only relevant for dstWidth=0, because that is when sign-extension may be required to convert to internal 24-bit width. Sets the DSTSIGNED bits in PARAM1_2 */ uint8_t dstConjugate; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable Conjugation of the output samples. 0: No conjugation 1: Enable conjugation This register only makes sense for dstRealComplex=0. It is useful in conjunction with DSTCONJ to derive an IFFT mode (by conjugating at both output and output) Sets the DSTCONJ bit of PARAM1_2 */ uint8_t dstScale; /*!< 4 bit value: Specifies a programmable scaling, via right bit-shift, from 0 bits to 8 bits, for the output samples. Sets the DSTSCAL bits of PARAM1_5 (0-8) The 24-bit complex samples are first converted to 32-bit complex samples by zero padding 8 LSBs. Then, based on the REG_DSTSCAL register value, a right bit-shift of 0 to 8 bits is applied (with MSB sign filling, if required).*/ uint16_t dstSkipInit; /*!<10 bit value: Number of samples to skip in the beginning (for each iteration) before writing samples to the destination memory. Sets the DST_SKIP_INIT bits of PARAM1_5*/ }HWA_DestConfig; /*! * @brief HWA Paramset Config for FFT block * * HWA paramset config parameters for the FFT block inside HWA_ParamConfig which is used with the HWA_ConfigParamSet() call. * */ typedef struct HWA_AccelModeFFT_t{ uint8_t fftEn; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable for FFT computation 0 - FFT disabled (Pipelined FFT sub-block bypassed) 1 - FFT enabled (Pipelined FFT sub-block enabled) Sets the FFT_EN bits of PARAM1_0 */ uint8_t fftSize; /*!< 4 bit value: Specifies FFT size. Actual FFT size is equal to 2^(fftSize) Supported values are [1..10], which correspond to FFT sizes [2..1024]. The actual FFT size should be equal to or larger than srcAcnt Sets the FFTSIZE bits of PARAM1_6 */ uint16_t butterflyScaling; /*!< 10 bit value: 1 bit per butterfly stage. LSB is for last stage and MSB is for the first stage for each bit, 0 - MSB is saturated 1 - convergent rounded at LSB (divide by 2) Number of valid bits in this field depends on the fftSize. Sets the BFLY_SCALING bits of PARAM1_6 */ uint8_t interfZeroOutEn; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable for interference zeroing out HWA_CommonConfig_t::interferenceThreshold field should be set to a valid value if this field is enabled. Sets the INTERF_THRESH_EN bits of PARAM1_6 */ uint8_t windowEn; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable for Windowing operation Sets the WINDOW_EN bits of PARAM1_0 */ uint16_t windowStart; /*!< 10 bit value: (0-1023) Specifies the offset from the actual Window RAM base address and represents the starting address of the window function in the Window RAM. A value of 0x0 means the starting address is the first 32-bit word in the Window RAM, 0x1 is the second 32-bit word and so on. Sets the WINDOW_START bits of PARAM1_6 */ uint8_t winSymm; /*!< 1 bit value: See \ref HWA_WINDOW_SYMM macros for correct values. Indicates whether the window function is symmetric or not Sets the WINSYMM bits of PARAM1_6 */ uint8_t winInterpolateMode; /*!< 2 bit value: See \ref HWA_FFT_WINDOW_INTERPOLATE_MODE macros for correct values. Configures linear interpolation for the window coefficients, which is relevant for large-size FFT computation (i.e., FFT sizes of 2K, 4K) that is obtained via stitching multiple smaller-size FFTs. (Note: winSymm should be set to 0 when using 4K or 2K mode( Sets the WINDOW_INTERP_FRACTION bits of PARAM1_7 */ uint8_t magLogEn; /*!< 2 bit value: See \ref HWA_FFT_MODE_MAGNITUDE_LOG2 macros for correct values. Enable/Disable for Magnitude and Log2 computation Sets the ABS_EN, LOG2EN bits of PARAM1_0 */ uint8_t fftOutMode; /*!< 2 bit value: See \ref HWA_FFT_MODE_OUTPUT macros for correct values. Configures the output mode of the FFT Engine path For stats mode, following parameters will be overriden in \ref HWA_DestConfig of that paramset dstAcnt=4095, dstAIdx=dstBIdx=8, dstWidth=1, dstRealComplex=0. Sets the FFT_OUTPUT_MODE bits of PARAM1_0 */ } HWA_AccelModeFFT; /*! * @brief HWA Paramset Config for Compression/Decompression block * * HWA paramset config parameters for the FFT block inside HWA_ParamConfig which is used with the HWA_ConfigParamSet() call. * Some registers (notably EGEkIdx) are not made visible, as they are primarily meant for debu. * */ typedef struct HWA_AccelModeCompress_t{ uint8_t compressDecompress; /*!< 1 bit value: See \ref HWA_COMPRESS_MODE macros for correct values. Compression/Decompression selection. 0 - Compression. 1 - Decompression. Sets the CMP_DCMP bitl of PARAM1_0 */ uint8_t method; /*!< 3 bit value: Specifies the compression method. See \ref HWA_CMP_METHOD macros for correct value. 0 - EGE Compression/Decompression. Sets the CMP_METHOD bits of PARAM1_0 */ uint8_t ditherEnable; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable for dither in the compression engine. Sets the CMP_DITHER_EN bit of PARAM1_0 */ uint8_t passSelect; /*!< 2 bit value: See \ref HWA_COMPRESS_PATHSELECT macros for correct values. Enable/Disables the different passes in the compression engine. Sets the CMP_PASS_SEL bits of PARAM1_6 */ uint8_t headerEnable; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. Enable/Disable for populating the header in the compression engine. For decompresion, it indicates whether the header is present in the compressed input. Sets the CMP_HEADER_EN bit of PARAM1_6 */ uint8_t scaleFactorBW; /*!< 4 bit value: (0-15) Specifies the size of scale factor (block exponent). In general, to be set to 4 for 16 bit input (Real or complex), and 5 for 32-bit input. Sets the CMP_SCALEFAC_BW bits of PARAM1_6 */ uint8_t EGEKarrayLength; /*!< 4 bit value: (0-3) Specifies the size of 'K parameter' array. Sets the CMP_EGE_K_ARR_LEN bits of PARAM1_6 */ } HWA_AccelModeCompress; /*! * @brief HWA Paramset Config for ComplexMultiply block * * HWA paramset config parameters for the ComplexMultiply block inside HWA_ParamConfig which is used with the HWA_ConfigParamSet() call. * */ typedef struct HWA_ComplexMultiply_t { uint8_t mode; /*!< 3 bit value: See \ref HWA_COMPLEX_MULTIPLY_MODE macros for correct values. Configuration for the Complex Multiplier block Sets the CMULT_MODE bits of PARAM1_0 */ union { uint16_t twidIncrement; /*!< 14 bit value: used when \ref HWA_ComplexMultiply_t::mode is HWA_COMPLEX_MULTIPLY_MODE_FREQ_SHIFTER and specifies how the LUT read index is incremented for every successive input sample and hence it controls the de-rotation frequency Sets the TWIDINCR bits of PARAM1_7 */ struct { uint16_t startFreq; /*!< 14 bit value: used when \ref HWA_ComplexMultiply_t::mode=HWA_COMPLEX_MULTIPLY_MODE_SLOW_DFT and specifies starting frequency for the DFT computation Sets the TWIDINCR bits of PARAM1_7 */ uint8_t freqIncrement; /*!< 4 bit value: used when \ref HWA_ComplexMultiply_t::mode=HWA_COMPLEX_MULTIPLY_MODE_SLOW_DFT and specifies the increment value by which the frequency increments in every iteration. Supported values are [0..14] The true increment value is 2^(14-freqIncrement). Sets the FFTSIZE bits of PARAM1_6 */ } dft; uint8_t twidFactorPattern; /*!< 2 bit value: See \ref HWA_FFT_STITCHING_TWID_PATTERN macros for correct values. This field is used when \ref HWA_ComplexMultiply_t::mode=HWA_COMPLEX_MULTIPLY_MODE_FFT_STITCHING and conveys the twid factor pattern to be used. 0: 2K (2x1024) size FFT stitching twiddle factor pattern 1: 4K (4x1024) size FFT stitching twiddle factor pattern other values are invalid Sets the TWIDINCR bits of PARAM1_7 */ }cmpMulArgs; }HWA_ComplexMultiply; /*! * @brief HWA Paramset Config for CFAR block * * HWA paramset config parameters for the CFAR block inside HWA_ParamConfig which is used with the HWA_ConfigParamSet() call. * */ typedef struct HWA_AccelModeCFAR_t{ uint8_t numNoiseSamplesLeft; /*!< 6 bit value: specify the number of samples used for noise averaging to the left of the cell under test. Note: The actual number of samples used for noise averaging in H/W is equal to the value of this field multiplied by 2 Sets the CFAR_AVG_LEFT (add note of factor of 2) bits of PARAM1_7 */ uint8_t numNoiseSamplesRight; /*!< 6 bit value: specify the number of samples used for noise averaging to the right of the cell under test. Note: The actual number of samples used for noise averaging in H/W is equal to the value of this field multiplied by 2 Sets the CFAR_AVG_RIGHT (add note of factor of 2) bits of PARAM1_7 */ uint8_t numGuardCells; /*!< 3 bit value: specifies the number of guard cells to ignore on either side of the cell under test Sets the CFAR_GUARD_INT bits of PARAM1_6 */ uint8_t nAvgDivFactor; /*!< 4 bit value: specifies the division factor by which the noise sum calculated from the left and right noise windows are divided by in order to get the final surrounding noise average value. The division factor is equal to 2^nAvgDivFactor Valid values: 0-8 Sets the CFAR_NOISEDIV (add note) bits of PARAM1_6 */ uint8_t nAvgMode; /*!< 2 bit value: See \ref HWA_NOISE_AVG_MODE_CFAR macros for correct values. configures the noise averaging mode in the CFAR detector Sets the CFAR_CA_MODE bits of PARAM1_7 */ uint8_t operMode; /*!< See \ref HWA_CFAR_OPER_MODE macros for correct values. Sets the CFAR_LOG_MODE, CFAR_INP_MODE, CFAR_ABS_MODE bits of PARAM1_0 */ uint8_t outputMode; /*!< 2 bit value: See \ref HWA_CFAR_OUTPUT_MODE macros for correct values. select the output mode of the CFAR engine Sets the CFAR_OUT_MODE bits of PARAM1_7 */ uint8_t peakGroupEn; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. specifies whether peak grouping should be enabled HWA_FEATURE_BIT_DISABLE - peak grouping is disabled, which means that a peak is declared as detected as long as the cell under test exceeds the threshold HWA_FEATURE_BIT_ENABLE - peak is declared as detected only if it the cell under test exceeds the threshold, as well as, if the cell under test exceeds the two neighboring cells to its immediate left and right Sets the CFAR_GROUPING_EN bits of PARAM1_0 */ uint8_t cyclicModeEn; /*!< 1 bit value: See \ref HWA_FEATURE_BIT macros for correct values. specifies whether the CFAR-CA detector needs to work in cyclic mode or in non-cyclic mode HWA_FEATURE_BIT_DISABLE=non-cyclic mode HWA_FEATURE_BIT_ENABLE=cyclic mode Sets the CFAR_CYCLIC bits of PARAM1_0 */ }HWA_AccelModeCFAR; /*! * @brief HWA Paramset Config * * HWA paramset config parameters that are used with the HWA_ConfigParamSet() call. * */ typedef struct HWA_ParamConfig_t { uint8_t triggerMode; /*!< See \ref HWA_TRIG_MODE macros for correct values. Sets the TRIGMODE bits of PARAM1_0*/ uint8_t dmaTriggerSrc; /*!< DMA channel number to be monitored for dma based trigger mode. this field is used only when \ref HWA_ParamConfig_t::triggerMode is set to \ref HWA_TRIG_MODE_DMA Sets the DMA2ACC_CHANNEL_TRIGSRC bits in PARAM1_0*/ uint8_t accelMode; /*!< 2 bit value: See \ref HWA_ACCELMODE macros for correct values. Configures the mode of operation of the accelerator for the current parameter-set. Sets the ACCEL_MODE bits of PARAM1_0*/ HWA_SourceConfig source; /*!< Source related params */ HWA_DestConfig dest; /*!< Dest related params */ union { HWA_AccelModeFFT fftMode; /*!< FFT mode related params */ HWA_AccelModeCFAR cfarMode; /*!< CFAR mode related params */ HWA_AccelModeCompress compressMode; /*!< Compression/Decompression mode related params */ }accelModeArgs; HWA_ComplexMultiply complexMultiply; /*!< Complex multiply related params used when \ref HWA_ParamConfig_t::accelMode is not \ref HWA_ACCELMODE_CFAR */ }HWA_ParamConfig; /*! * @brief HWA Interrupt Config * * HWA interrupt config parameters that are used with the HWA_enableParamSetInterrupt() call. * */ typedef struct HWA_InterruptConfig_t { uint8_t interruptTypeFlag; /*!< Flag to specify whether Interrupt to CPU and/or DMA is desired on completion of paramset. Defines for \ref HWA_PARAMDONE_INTERRUPT_TYPE can be ORed to specify this flag. Interrupt types HWA_PARAMDONE_INTERRUPT_TYPE_CPU may not be supported on all versions of the IP - see \ref HWA_HWAttrs_t::isConcurrentAccessAllowed */ struct { HWA_ParamDone_IntHandlerFuncPTR callbackFn; /*!< Callback function to be called when interrupt destination is CPU */ void *callbackArg; /*!< Callback function argument */ }cpu; struct { uint8_t dstChannel; /*!< DMA channel number to be triggered on paramset completion if interrupt destination to DMA is desired */ }dma; }HWA_InterruptConfig; /*! * @brief HWA Statistics from the STATISTICS block * * HWA statistics - MAX and SUM - that are output from the statistics block. * */ typedef struct HWA_Stats_t { uint32_t maxValue; /*!< 24 bits value from MAXnVALUE register */ uint16_t maxIndex; /*!< 24 bits value from MAXnINDEX register */ uint8_t iSumMSB; /*!< upper 4 bits of 36-bit value of iSUM; read from ISUMnMSB */ uint8_t qSumMSB; /*!< upper 4 bits of 36-bit value of qSUM; read from QSUMnMSB */ uint32_t iSumLSB; /*!< lower 32 bits of 36-bit value of iSUM; read from ISUMnLSB */ uint32_t qSumLSB; /*!< lower 32 bits of 36-bit value of qSUM; read from QSUMnLSB */ }HWA_Stats; /*! * @brief HWA Debug statistics * * HWA debug - current paramset, loopcount, trigger status - that are output from the statistics block. * */ typedef struct HWA_DebugStats_t { uint8_t currentParamSet; /*!< Index of the current paramset that is under execution. useful for debug, where parameter-sets can be executed one-by-one using SW trigger mode for each of them. In such a debug, this register indicates which parameter-set is currently waiting for the SW trigger*/ uint16_t currentLoopCount; /*!< the loop count that is presently running */ uint16_t dmaTrigStatus; /*!< indicates whether a trigger was received via DMA trigger method */ uint8_t dfePingPongStatus; /*!< the status of DFE ping-pong trigger */ uint8_t swTrigStatus; /*!< the status of software trigger */ }HWA_DebugStats; /*! * @brief HWA Local memory Information * * HWA Local processing memory info - base address and Size. * */ typedef struct HWA_MemInfo_t { uint32_t baseAddress; /*!< Base Address of HWA Local memory */ uint16_t bankSize; /*!< Total size in bytes of one bank */ uint16_t numBanks; /*!< number of banks can be used of HWA Local memory */ }HWA_MemInfo; /** @}*/ /** @addtogroup HWA_DRIVER_EXTERNAL_FUNCTION @{ */ /*! * @brief Function to initialize the HWA module * * @pre This function must be called once per system and before * any other HWA driver APIs. It resets the HWA H/W instances in the system. * */ extern void HWA_init(void); /*! * @brief Function to initialize HWA specified by the * particular index value. * * @pre HWA_init() has been called * * @param index HWA instance number * * @param socHandle SOC Handle (can be obtained used SOC_init by the caller) * * @param errCode [out] valid errorCode if NULL handle returned. * * @return A HWA_Handle upon success. NULL if an error occurs. * * @sa HWA_init() * @sa HWA_close() */ extern HWA_Handle HWA_open(uint32_t index, SOC_Handle socHandle, int32_t* errCode); /*! * @brief Function to close a HWA peripheral specified by the HWA handle * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_close(HWA_Handle handle); /*! * @brief Function to reset the internal state machine of the HWA * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_reset(HWA_Handle handle); /*! * @brief Function to set the common HWA configuration parameters * needed for the next operations/iterations/paramsets of HWA * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param commonConfig HWA Common Config Parameters * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig); /*! * @brief Function to set the HWA configuration parameters for a given paramSet * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param paramsetIdx A valid paramSet index for which the paramConfig is provided. * * @param paramConfig HWA ParamSet Config Parameters * * @param dmaConfig [out] This parameter is set by the driver with values that user * should use to program the source trigger DMA. user should provide * a valid buffer here if the triggerMode is set to DMA in paramConfig * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig); /*! * @brief Function to get the config to program the DMA for a given DMA Trigger channel. * Application should use the returned config to program the DMA so that it can then * in turn trigger the paramset. Application should make sure that the channel provided * here in dmaTriggerSrc should match the \ref HWA_ParamConfig_t::dmaTriggerSrc passed * to HWA_configParamSet() * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param dmaTriggerSrc Same as \ref HWA_ParamConfig_t::dmaTriggerSrc of the paramset for * whom this DMA is getting configured * * @param dmaConfig [out]This parameter is set by the driver with values that user * should use to program the source trigger DMA. user should provide * a valid buffer here if the triggerMode is set to DMA in paramConfig * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig); /*! * @brief Function to get the address of CFAR Peak Count register * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param peakCntAddr [out]This parameter is set by the driver with the * address of FFTPEAKCNT register which contains the number of CFAR detections. * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_getCfarPeakCntRegAddress(HWA_Handle handle, uint32_t *peakCntAddr); /*! * @brief Function to set the HWA RAM (either Internal RAM or window RAM) * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param ramType Use defines \ref HWA_RAM_TYPE * * @param data data pointer that needs to be copied to RAM * * @param dataSize Size of data to be copied * * @param startIdx start index (in bytes) within RAM where data needs to be copied * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx); /*! * @brief Function to enable the CPU and/or DMA interrupt after a paramSet completion. * The CPU interrupt for every paramset completion may not be supported on all * devices - see \ref HWA_HWAttrs_t::isConcurrentAccessAllowed * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param paramsetIdx A valid paramSet index for which the intrConfig is provided. * * @param intrConfig HWA Interrupt Config Parameters * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig); /*! * @brief Function to enable the CPU interrupt after all programmed paramSets have been completed. * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param callbackFn user defined callback function to be called when this interrupt is generated * * @param callbackArg user defined callback arg for the callback function * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_enableDoneInterrupt(HWA_Handle handle, HWA_Done_IntHandlerFuncPTR callbackFn, void * callbackArg ); /*! * @brief Function to disable the CPU and/or DMA interrupt after a paramSet completion. * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param paramsetIdx A valid paramSet index for which the interrupt is to be disabled * * @param interruptTypeFlag Flag to indicate if CPU and/or DMA interrupts are to be disabled * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag); /*! * @brief Function to disable the CPU interrupt after all programmed paramSets have been completed. * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_disableDoneInterrupt(HWA_Handle handle); /*! * @brief Function to enable the state machine of the HWA. This should be called after * paramset and RAM have been programmed * * @pre HWA_open() HWA_ConfigCommon() HWA_ConfigParamSet HWA_ConfigRam has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param flagEnDis Enable/Disable Flag: 0-disable, 1-enable * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis); /*! * @brief Function to manually trigger the execution of the state machine via software * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_setSoftwareTrigger(HWA_Handle handle); /*! * @brief Function to manually trigger the execution of the state machine waiting on DMA via software * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param idx DMA channel number for whom software should simulate the trigger * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint16_t idx); /*! * @brief Function to read the Clip Status registers * * @pre HWA_open() has been called and HWA is not executing paramsets. * * @param handle A HWA_Handle returned from HWA_open() * * @param pbuf pointer to a uint8_t size memory where value of Clip * Status Register would be copied * * @param size size (in bytes) of the pbuf register provided. * It should be atleast 2 bytes. * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open(), HWA_HWAttrs_t::isConcurrentAccessAllowed */ extern int32_t HWA_readClipStatus(HWA_Handle handle, uint8_t *pbuf, uint8_t size); /*! * @brief Function to clear the Clip Status registers * * @pre HWA_open() has been called and HWA is not executing paramsets. * * @param handle A HWA_Handle returned from HWA_open() * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open(), HWA_HWAttrs_t::isConcurrentAccessAllowed */ extern int32_t HWA_clearClipStatus(HWA_Handle handle); /*! * @brief Function to read the 4 sets of 'MAX' statistics register * * @pre HWA_open() has been called and HWA is not executing paramsets. * * @param handle A HWA_Handle returned from HWA_open() * * @param pStats pointer to a memory of type HWA_Stats where value of all the * Max and statistics Registers would be copied * * @param numIter number of iterations to read. Value 1-4 should be provided. * User is expected to provide enough space for the pStats to hold 'numIter' worth of HWA_Stats * Ex: HWA_Stats appHWAStats[3]; HWA_readStatsReg(appHWAhandle,appHWAStats,3); * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open(), HWA_HWAttrs_t::isConcurrentAccessAllowed */ extern int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter); /*! * @brief Function to read the PEAKCNT register * * @pre HWA_open() has been called and HWA is not executing paramsets. * * @param handle A HWA_Handle returned from HWA_open() * * @param pbuf pointer to a memory where value of the * PEAKCNT Registers would be copied * * @param size size (in bytes) of the pbuf register provided. * It should be atleast 2 bytes. * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open(), HWA_HWAttrs_t::isConcurrentAccessAllowed */ extern int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size); /*! * @brief Function to read the debug registers (paramcurr, loopcou, acc_trig_in_stat) * * @pre HWA_open() has been called and HWA is not executing paramsets. * * @param handle A HWA_Handle returned from HWA_open() * * @param pStats pointer to a memory of type HWA_debugStats where value of the * RDSTATUS and HWACCREG12 Registers would be copied * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open(), HWA_HWAttrs_t::isConcurrentAccessAllowed */ extern int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats); /*! * @brief Function to clear the debug registers (acc_trig_in_clr) * * @pre HWA_open() has been called and HWA is not executing paramsets. * * @param handle A HWA_Handle returned from HWA_open() * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open(), HWA_HWAttrs_t::isConcurrentAccessAllowed */ extern int32_t HWA_clearDebugReg(HWA_Handle handle); /*! * @brief Function to get HWA processing Memory information including address, * size and number of banks. * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param memInfo Pointer to save HWA processing memory information * * @return 0 upon success. error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo); /*! * @brief Function to get the dma destination index with a given EDMA channel number * This function assumes the EDMA channel number is from the first EDMA instance. * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param edmaChanId EDMA channell id * * @param hwaDestChan Pointer to save destination channel index * * @return =0 Success * <0 Error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan); /*! * @brief Function to get the edma EDMA channel number from a given HWA paramset destination channel. * This function assumes the EDMA channel number is from the first EDMA instance. * * @pre HWA_open() has been called. * * @param handle A HWA_Handle returned from HWA_open() * * @param hwaDMAdestChan Destination channle id set in a paramset * * @return >=0 Upon success, EDMA channel number * <0 Error code if an error occurs. * * @sa HWA_open() */ extern int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan); /** @}*/ /* * * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file rangeprochwa.h * * @brief * Implements range processing functionality using HWA. */ /** * @page dpu_rangehwa RangeProcHWA * [TOC] * @section toplevel_hwa Top Level Design * * Range FFT processing is done by HWA hardware. Based on the RF parameters, rangeProcHWA configures * hardware accelerator FFT engine accordingly. It also configures data input and output EDMA channels to * bring data in and out of range Processing memory. * * HWA FFT process is triggered by hardware based trigger -"chirp data available" which is hooked up to HWA internally in hardware. * * After FFT processing is done, HWA generates interrupt to rangeProcHWA DPU, at the same time triggers EDMA data * output channel to copy FFT results to radarCube in configured format. EDMA interrupt done interrupt is triggered by EDMA hardware * after the copy is completed. * * DC antenna signal calibration and removal is built into the rangeProcHWA Module. * If the feature is enabled, it is done after all chirps (in the frame) FFT * processing is completed. * * The following diagram shows the top level design for rangeProcHWA. * * @image html rangeprochwa_toplevel.png "rangeProcHWA Top Level" * * The following diagram shows a general timing diagram for a 3 tx antenna MIMO * case but can be imagined to hold for 1 or 2 tx cases as well. All use cases * described in later sections have this general timing flow. * * @image html datapath_1d_timing.png "Timing Diagram" * * @section config_hwa Data Interface Parameter Range * * Here are supported ADCBuf and radarCube interface configurations: * * ADCBuf Data Interface *---------------------- * * Parameter | Supported value * :----------|:----------------: * dataFmt | @ref DPIF_DATAFORMAT_COMPLEX16_IMRE only * interleave|interleave (@ref DPIF_RXCHAN_INTERLEAVE_MODE) and non-interleave (@ref DPIF_RXCHAN_NON_INTERLEAVE_MODE) * numChirpsPerChirpEvent|1 ONLY * numRxAntennas|1, 2 or 4 * numAdcSamples|64 - 1024 * * * Radar Cube Data Interface *---------------------- * * Parameter | Supported value * :----------|:----------------: * datafmt | @ref DPIF_RADARCUBE_FORMAT_1 and @ref DPIF_RADARCUBE_FORMAT_2 only * numTxAntennas|1, 2 and 3 * numRangeBins|64 - 1024 * numChirpsPerFrame|As AdcBuf and HWA memory permit, numChirpsPerFrame/numTxAntennas should be an even number * * @note For 1024 Range bins with 1 TX , 4 RX antenna and @ref DPIF_RADARCUBE_FORMAT_1, * it is not currently supported due to EDMA address jump limitation (jump < 32768). * @note For 1024 Range bins with 3 TX , 4 RX antenna and @ref DPIF_RADARCUBE_FORMAT_1, * it is not currently supported due to EDMA address jump limitation (jump < 32768). * @note Due to the Ping/Pong scheme implemented in rangeProcHWA DPU, numChirpsPerFrame/numTxAntennas should be an even number. * * @section input_hwa Data Input * * There are two HWA input mode supported (@ref DPU_RangeProcHWA_InputMode_e), * - @ref DPU_RangeProcHWA_InputMode_ISOLATED : \n * ADCBuf buffer and HWA memory are isolated in physical memory space. * Data input EDMA channel is configured to transfer data from ADCBuf to HWA M0/M1 memory * in ping/pong alternate order. * - @ref DPU_RangeProcHWA_InputMode_MAPPED :\n * ADCBuf buffer and HWA memory are mapped. HWA can read ADC data directly. No copy is needed. * * Depending on the RF configuration, the data in ADCBuf can be either interleaved or non-interleaved mode. * * @section output_hwa Data Output * * RangeProcHWA configures data output EDMA channels to transfer FFT results from HWA M2/M3 to radarCube memory. * * The following two radarCube formats are supported in rangeProcHWA. * - \ref DPIF_RADARCUBE_FORMAT_1 * - \ref DPIF_RADARCUBE_FORMAT_2 * * The following table describes the suppoted data input and output combinations: * * Interleave Mode | DPIF_RADARCUBE_FORMAT_1 | DPIF_RADARCUBE_FORMAT_2 * :----------|:----------------:|:-----------: * interleave | NOT supported | Supported * non-interleave|Supported | Supported * * * * @section process_hwa Data Processing * * Range FFT processing is done by HWA hardware. As shown in the following diagram, after @ref DPU_RangeProcHWA_config is completed, * in every frame, rangeProcHWA is triggered through @ref DPU_RangeProcHWA_control \n * using command @ref DPU_RangeProcHWA_Cmd_triggerProc. If the hardware resources are overlaid with other modules, * @ref DPU_RangeProcHWA_config can be called before the next frame start. \n * * DC signal removal configuration can be updated at inter-frame time before the next frame starts. * * @image html hwa_callflow.png "rangeProcHWA call flow" * * * @subsection hwa_calibDC_Range Antenna coupling signature removal * * This feature is controlled through configuration @ref DPU_RangeProc_CalibDcRangeSigCfg_t. * The configuration can be sent to rangeProcHWA DPU through API @ref DPU_RangeProcHWA_config. \n * The configuration can also be updated at runtime through control command @ref DPU_RangeProcHWA_Cmd_dcRangeCfg. * * DC signal calibration and compensation is operated on radarCube directly by the CPU. * * @image html hwa_dcremoval.png "rangeProcHWA Antenna DC signal removal" * * * @section hwa_usecase Use Cases and Implementation * * This Section describes some of the internal implementation for a few use cases with combination of input/output configurations. \n * * @subsection hwa_impl HWA param set Implementation * RangeProcHWA always use 4 consecutive HWA param sets(@ref DPU_RANGEPROCHWA_NUM_HWA_PARAM_SETS) starting from paramSetStartIdx, * these params will be labeled PARAM_0, PARAM_1, PARAM_2 and PARAM_3 from now onwards for convenience * of explanation and picture representation. * Param sets are used in two parallel processing chain in ping/pong alternate manner. * PARAM_0 and PARAM_1 are used for PING and PARAM_2 and PARAM_3 are used for PONG. * * PARAM_0 and PARAM_2 need to be activated by triggers to protect internal data memory integrity. There are initially triggered * by software when starting the very first chirp. Consequently they are triggered by data out hot signature channel. * PARAM_1 and PARAM_3 are Range FFT param sets for PING and PONG respectively. In directly mapped input mode, they are triggered by * frontend hardware when chirp data is available. In isolated input mode, they are triggered by data in hot signature. * After range FFT processing is done in HWA, HWA param sets automatically trigger data out EDMA channel to copy data to radar Cube in desired * radarCube format. * * @subsection hwa_dataIn EDMA Data In Implementation * When enabled, data input EDMA is constructed utilizing two EDMA channels. The first EDMA channel copies data from ADCBuf buffer to HWA memory. * The second EDMA channel is chained to the first channel. It copies hot signature to trigger range FFT param sets.\n * In summary, the data in EDMA requires the following resources: * * - 1 EDMA channel with 1 shadow channel * - 1 hot Signature channel with 1 shadow channel * * @subsection hwa_dataOut EDMA Data Out Implementation * Data out EDMA is responsible for copying data from HWA memory to radar Cube memory. * It has two formats (@ref DPU_RangeProcHWA_EDMAOutputConfig_t).\n * @ref DPU_RangeProcHWA_EDMAOutputConfigFmt2 is only for the following configuration: \n * * Setting | Note * :------------|:-----------: * @ref DPIF_RADARCUBE_FORMAT_1| Radar Cube format 1 * numTxAntenna| 3 TX antenna * @ref DPIF_RXCHAN_NON_INTERLEAVE_MODE|ADCBuf non interleave mode * * All other configurations should use @ref DPU_RangeProcHWA_EDMAOutputConfigFmt1_t. * * For EDMA dataOut Fmt1, it needs three EDMA channels, shown as follows: * * Ping: * - 1 EDMA channel with 1 shadow channel * * Pong: * - 1 EDMA channel with 1 shadow channel * * Signature channel: * - 1 HWA hot signature channel with 1 shadow channel * * Ping and Pong EDMA channels are triggered by PARAM_1 and PARAM_3 FFT automatically. Both Ping/pong EDMA channels are chained to data out * Hot Signature channel, which triggers HWA PARAM_0 AND PARAM_2 when EDMA channel copy is completed. * * For EDMA dataOut Fmt2, it requires the following resources:\n * * Ping: * - 1 dummy EDMA channel with 3 shadow channels * - 3 dataOut channel, each has a shadow channel * * Pong: * - 1 dummy EDMA channel with 3 shadow channels * - 3 dataOut channel, each has a shadow channel * * Signature channel: * - 1 HWA hot signature channel with 1 shadow channel * * The dummy EDMA channel is triggered by the HWA PARAM_1(trigger data out Ping EDMA channel) and PARAM_3(trigger data out pong EDMA channel) * after FFT operation is completed. * The dummy channel is linked to 3 shadow channels. The shadow channel is loaded to dummy channel in round robin order. Each dummy channel * is chained to one of the 3 dataOut channel that have different source and destination address. Details are as follows: * * Index | Source Address | Destination Address | sequence order in time * :------:|:------------:|:-----------:|:------------------------: * PING 1| HWA M2 | TX1 | 1 * PING 2| HWA M2 | TX3 | 3 * PING 3| HWA M2 | TX2 | 5 * PONG 1| HWA M3 | TX2 | 2 * PONG 2| HWA M3 | TX1 | 4 * PONG 3| HWA M3 | TX3 | 6 * * * @subsection hwa_usecase1 Interleaved RX channel data -> DPIF_RADARCUBE_FORMAT_2 * * This use case is for configuration with a directly mapped input buffer with interleaved ADC data. After Range FFT, data is saved in radar cube * with format:@ref DPIF_RADARCUBE_FORMAT_2. * * DataIn EDMA is NOT required, DataOut EDMA should be configured with format @ref DPU_RangeProcHWA_EDMAOutputConfigFmt2.\n * * Input params | Setting * :------------|:-----------: * InterleaveMode | Interleave * HWA input mode|Mapped * RadarCube format|DPIF_RADARCUBE_FORMAT_2 * numTxAnt| 1, 2, 3 * * @image html interleave_to_radarcubefmt2.png "Interleaved data input to DPIF_RADARCUBE_FORMAT_2" * * Above picture illustrates a case of three transmit antennas, chirping within the frame with * repeating pattern of (Tx1,Tx3,Tx2). * This is the 3D profile (velocity and x,y,z) case. There are 4 rx * antennas, the samples of which are color-coded and labeled as 1,2,3,4 with * unique coloring for each of chirps that are processed in ping-pong manner * to parallelize accelerator and EDMA processing with sample acquisition from ADC. * The hardware accelerator's parameter RAMs are setup to do FFT * which operates on the input ADC ping and pong buffers to produce output in M2 and M3 * memories of the HWA. * The processing needs to be given a kick every frame, this is done by the range DPU user * by issuing the IOCTL command code @ref DPU_RangeProcHWA_Cmd_triggerProc (this * invokes @ref rangeProcHWA_TriggerHWA) which activates the HWA's dummy * params PARAM_0 (ping) and PARAM_2 (pong) which in turn activate the processing PARAMs * PARAM_1 (ping) and PARAM_3 (pong), these are waiting on the ADC full signal. * When ADC has samples to process in the ADC buffer Ping or Pong memories, the corresponding * processing PARAM will trigger FFT calculation and transfer the FFT output into the M2 or M3 memories. * Before ADC samples are sent to FFT engine, the configured FFT window is applied to them in the HWA. * The completion of FFT triggers the Data Out Ping/Pong EDMAs which have been * setup to do a copy with * transposition from the M2/M3 memories to the L3 RAM (Radar Cube) as shown in the picture. * This HWA-EDMA ping-pong processing is done @ref DPU_RangeProcHWA_StaticConfig_t::numChirpsPerFrame/2(ping/pong) times so * that all chirps of the frame are processed. The EDMA * is setup such that Data Out EDMAs are both chained to the Data Out Signature EDMA. * So the Data Out Signature EDMA will trigger when the FFT result in M2/M3 memories * is transferred to the radar cube. This signature EDMA is setup to trigger the * dummy PARAMs. Even though the signature EDMA is a single EDMA channel, it is * setup to alternate between the two dummy PARAMs so in effect when ping data out transfer * is done, the ping dummy PARAM (PARAM_0) will be activated and when pong is done, * the pong dummy PARAM (PARAM_2) will be activated. * The signature EDMA is setup to give a completion interrupt after the last chirp * which notifies software that range DPU processing is complete and user can trigger * processing again for the next chirping period when the time comes. * The shadow (link) PaRAMs of EDMA are used for reloading the PaRAMs so reprogramming * is avoided. The blue arrows between EDMA blocks indicate linking and red arrows * indicate chaining. * * In further use cases, we do not describe the diagrams in such detail but * the the general flow is similar. Details differ mostly in the programming * of HWA and the amount of EDMA resources and their programming to * handle the desired input and output formats. * * @subsection hwa_usecase2 Non-Interleaved RX channel data -> DPIF_RADARCUBE_FORMAT_2 * * This use case is for configuration with a directly mapped input buffer with non-interleaved ADC data. After Range FFT, data is saved in radar cube * with format:@ref DPIF_RADARCUBE_FORMAT_2.\n * A conversion of data from non-interleaved format to interleaved format is done by PARAM_1 AND PARAM_3. * * DataIn EDMA is NOT required, DataOut EDMA should be configured with format @ref DPU_RangeProcHWA_EDMAOutputConfigFmt2.\n * * Input params | Setting * :------------|:-----------: * InterleaveMode | Non-Interleave * HWA input mode|Mapped * RadarCube format|DPIF_RADARCUBE_FORMAT_2 * numTxAnt| 1, 2, 3 * * @image html non-interleave_to_radarcubefmt2.png "Non-interleaved data input to DPIF_RADARCUBE_FORMAT_2" * * * * @subsection hwa_usecase3 Non-Interleaved RX channel data(1 or 2 TX Antenna) -> DPIF_RADARCUBE_FORMAT_1 * * This use case is for configuration with a directly mapped input buffer with non-interleaved ADC data. After RangeFFT, data is saved in radar cube * with format:@ref DPIF_RADARCUBE_FORMAT_1. * * DataIn EDMA is NOT required, DataOut EDMA should be configured with format @ref DPU_RangeProcHWA_EDMAOutputConfigFmt2.\n * The diagram shows radarCube in 2 TX Antenna format. The output of Ping will be saved in TX1 section and output of Pong will be saved in TX2 section of the radar cube. * For one TX antenna case, data from ping and pong data will be saved in TX1 radar cube in alternate order. * * Input params | Setting * :------------|:-----------: * InterleaveMode | Non-Interleave * HWA input mode|Mapped * RadarCube format|DPIF_RADARCUBE_FORMAT_1 * numTxAnt| 1, 2 * * @image html non-interleave_to_radarcubefmt1.png "Non-interleaved data input to DPIF_RADARCUBE_FORMAT_1" * * * * @subsection hwa_usecase4 Isolated Non-Interleaved RX channel data(1 or 2 TX Antenna) -> DPIF_RADARCUBE_FORMAT_1 * * This use case is for configuration with isolated input buffer with non-interleaved ADC data. After RangeFFT, data is saved in radar cube * with format:@ref DPIF_RADARCUBE_FORMAT_1. \n * * DataIn EDMA is required, DataOut EDMA should be configured with format @ref DPU_RangeProcHWA_EDMAOutputConfigFmt2 \n * The diagram shows radarCube in 2 TX Antenna format. The output of Ping will be saved in TX1 section and output of Pong will be saved in TX2 section of the radar cube. * For one TX antenna case, data from ping and pong will be saved in TX1 radar cube in alternate order. * * Input params | Setting * :------------|:-----------: * InterleaveMode | Non-Interleave * HWA input mode|Isolated * RadarCube format|DPIF_RADARCUBE_FORMAT_1 * numTxAnt| 1, 2 * * @image html isolated_non-interleave_to_radarcubefmt1.png "Isolated Non-interleaved data input to DPIF_RADARCUBE_FORMAT_1" * * * * @subsection hwa_usecase5 Isolated Non-Interleaved RX channel data(3 TX Antenna) -> DPIF_RADARCUBE_FORMAT_1 * * This use case is for configuration with isolated input buffer with non-interleaved ADC data. After RangeFFT, data is saved in radar cube * with format:@ref DPIF_RADARCUBE_FORMAT_1.\n * DataIn EDMA is required, DataOut EDMA should be configured with format @ref DPU_RangeProcHWA_EDMAOutputConfigFmt1.\n * * The output of Ping/Pong FFT results will be saved in radar cube as follows: * Ping 1 (first dataOut EDMA channel) data will goto odd number doppler chirps in TX1, as shown in dark grey arrow) * Ping 2 (second dataOut EDMA channel) data will goto odd number doppler chirps in TX3, as shown in light blue arrow) * Ping 3 (third dataOut EDMA channel) data will goto even number doppler chirps in TX2, as shown in peach arrow) * * Pong 1 (first dataOut EDMA channel) data will goto odd number doppler chirps in TX2, as shown in dark green arrow) * Pong 2 (second dataOut EDMA channel) data will goto even number doppler chirps in TX1, as shown in light green arrow) * Pong 3 (third dataOut EDMA channel) data will goto even number doppler chirps in TX3, as shown in blue arrow) * * Input params | Setting * :------------|:-----------: * InterleaveMode | Non-Interleave * HWA input mode|Isolated * RadarCube format|DPIF_RADARCUBE_FORMAT_1 * numTxAnt| 3 * * @image html isolated_non-interleave_to_radarcubefmt1_3tx.png "3 TX Isolated Non-interleaved data input to DPIF_RADARCUBE_FORMAT_1" * * * * */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /* mmWave SDK Driver/Common Include Files */ /* mmWave SDK Data Path Include Files */ /* \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file dpif_adcdata.h * * @brief * Defines RF ADCBuf interface. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* MMWAVE SDK Include Files */ /** * @file dpif_types.h * * @brief * Defines the common data types used in data path data interface. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* MMWAVE SDK Include Files */ /** * @brief * Data format for data Path interface buffers * * @details * The enumeration describes the data format used in data interface buffers between data processing unit */ typedef enum DPIF_DATAFORMAT_e { /*! @brief Complex 16bit for imaginary/real */ DPIF_DATAFORMAT_COMPLEX16_IMRE=0U, /*! @brief Complex 16bit for real/imaginary */ DPIF_DATAFORMAT_COMPLEX16_REIM, /*! @brief Complex 32bit for imaginary/real */ DPIF_DATAFORMAT_COMPLEX32_IMRE, /*! @brief Complex 32bit for real/imaginary */ DPIF_DATAFORMAT_COMPLEX32_REIM, /*! @brief Float data format */ DPIF_DATAFORMAT_FLOAT, /*! @brief Real 16bit data */ DPIF_DATAFORMAT_REAL16, /*! @brief Real 32bit data */ DPIF_DATAFORMAT_REAL32 }DPIF_DATAFORMAT; /** * @brief * RX channel ADC data interleave mode * * @details * The enumeration describes the data interleave mode across RF RX channels */ typedef enum DPIF_RXCHAN_INTERLEAVE_e { /*! @brief Non-Interleave mode */ DPIF_RXCHAN_NON_INTERLEAVE_MODE=0U, /*! @brief Interleave mode */ DPIF_RXCHAN_INTERLEAVE_MODE }DPIF_RXCHAN_INTERLEAVE; /** * @brief * ADC Data buffer property * * @details * The structure describes the properties for ADC data buffers */ typedef struct DPIF_ADCBufProperty_t { /*! @brief Data format in adcbuf */ DPIF_DATAFORMAT dataFmt; /*! @brief Data in interleave or non-interleave mode */ DPIF_RXCHAN_INTERLEAVE interleave; /*! @brief ADCBUF will generate chirp interrupt event every this many chirps - chirpthreshold */ uint8_t numChirpsPerChirpEvent; /*! @brief ADC out bits * 0(12 Bits), 1(14 Bits), 2(16 Bits) refer to rlAdcBitFormat_t for details */ uint8_t adcBits; /*! @brief Number of receive antennas */ uint8_t numRxAntennas; /*! @brief Number of ADC samples */ uint16_t numAdcSamples; /*! @brief rxChan offset in ADCBuf, it is required in non-interleave mode The offset array is set for numRxAntennas starting from index 0 contiguously The offset is in number of bytes */ uint16_t rxChanOffset[4U]; }DPIF_ADCBufProperty; /** * @brief * ADC Data buffer definition * * @details * The structure defines the ADC data buffer ,including data property, data size and data pointer */ typedef struct DPIF_ADCBufData_t { /*! @brief ADCBuf data property */ DPIF_ADCBufProperty dataProperty; /*! @brief ADCBuf buffer size in bytes */ uint32_t dataSize; /*! @brief ADCBuf data pointer */ void *data; }DPIF_ADCBufData; /** * @file dpif_radarcube.h * * @brief * Defines the data path radar cube data interface. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /** * @defgroup DPIF_RADARCUBE_FORMAT DPIF_RADARCUBE_FORMAT * @brief Combination of C structure declaration and Content that uniquely describes the radar cube * * * # |Declaration |Content *---| ---------------------------------------------------------------------|----------------------------- * 1 |cmplx16ImRe_t x[numTXPatterns][numDopplerChirps][numRX][numRangeBins] |1D Range FFT output * 2 |cmplx16ImRe_t x[numRangeBins][numDopplerChirps][numTXPatterns][numRX] |1D Range FFT output * 3 |cmplx16ImRe_t x[numRangeBins][numTXPatterns][numRX][numDopplerChirps] |1D Range FFT output * 4 |cmplx16ImRe_t x[numRangeBins][numDopplerBins][numTXPatterns][numRX] |2D (Range+Doppler) FFT output * 5 |cmplx16ImRe_t x[numRangeBins][numTXPatterns][numRX][numDopplerBins] |2D (Range+Doppler) FFT output * @{ */ /** @}*/ /*DPIF_RADARCUBE_FORMAT*/ /** * @brief * Radar Cube Buffer Interface * * @details * The structure defines the radar cube buffer interface, including * property, size and data pointer. */ typedef struct DPIF_RadarCube_t { /*! @brief Radar Cube data Format @ref DPIF_RADARCUBE_FORMAT */ uint32_t datafmt; /*! @brief Radar Cube buffer size in bytes */ uint32_t dataSize; /*! @brief Radar Cube data pointer User could remap this to specific typedef using information in @ref DPIF_RADARCUBE_FORMAT */ void *data; }DPIF_RadarCube; /** * @file dp_error.h * * @brief * Base error codes for the data path Modules. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** * Base Error Code for the mmWave data path DPUs **************************************************************************/ /************************************************************************** * Base Error Code for the mmWave data path DPCs **************************************************************************/ /** * @file dpedmahwa.h * * @brief * EDMA Configuration Utility API definitions for HWA. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Include Files */ /** * @file dpedma.h * * @brief * EDMA Configuration Utility API definitions. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Include Files */ /** @defgroup DPEDMA_EXTERNAL_FUNCTION DataPath EDMA External Functions @ingroup DP_EDMA @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the DataPath EDMA */ /** @defgroup DPEDMA_EXTERNAL_DATA_STRUCTURE DataPath EDMA External Data Structures @ingroup DP_EDMA @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DPEDMA_ERROR_CODE DataPath EDMA Error Codes @ingroup DP_EDMA @brief * The section has a list of all the error codes which are generated by the module */ /** @defgroup DPEDMA_INTERNAL_FUNCTION DataPath EDMA Internal Functions @ingroup DP_EDMA @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup DPEDMA_INTERNAL_DATA_STRUCTURE DataPath EDMA Internal Data Structures @ingroup DP_EDMA @brief * The section has a list of all internal data structures which are used internally * by the DataPath EDMA module. */ /** @defgroup DPEDMA_INTERNAL_DEFINITION DataPath EDMA Internal Definitions @ingroup DP_EDMA @brief * The section has a list of all internal definitions which are used internally * by the DataPath EDMA. */ /** @addtogroup DPEDMA_ERROR_CODE * Base error code for the dpedma is defined in the * \include ti/datapath/dpif/dp_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** @} */ /** * @brief * EDMA channel configuration * * @details * The structure is used to hold the EDMA channel configuration * * \ingroup DPEDMA_EXTERNAL_DATA_STRUCTURE */ typedef struct DPEDMA_ChanCfg_t { /*! @brief EDMA channel id */ uint8_t channel; /*! @brief EDMA channel shadow id */ uint16_t channelShadow; /*! @brief EDMA event Queue used for the transfer */ uint8_t eventQueue; }DPEDMA_ChanCfg; /** * @brief * EDMA channel configuration with 3 shadow channels. * * @details * The structure is used to hold the EDMA channel configuration for 1 EDMA channel * which is linked to 3 shadow channels. * * \ingroup DPEDMA_EXTERNAL_DATA_STRUCTURE */ typedef struct DPEDMA_3LinkChanCfg_t { /*! @brief EDMA channel id */ uint8_t channel; /*! @brief EDMA channel shadow id */ uint16_t channelShadow[3]; /*! @brief EDMA event Queue used for the transfer */ uint8_t eventQueue; }DPEDMA_3LinkChanCfg; /** * @brief * EDMA chaining configuration * * @details * The structure is used to hold the EDMA channel chaining configuration * * \ingroup DPEDMA_EXTERNAL_DATA_STRUCTURE */ typedef struct DPEDMA_ChainingCfg_t { /*! @brief EDMA chaining channel id */ uint8_t chainingChan; /*! @brief EDMA intermediate chaining flag */ _Bool isIntermediateChainingEnabled; /*! @brief EDMA final chaining flag */ _Bool isFinalChainingEnabled; }DPEDMA_ChainingCfg; /** * @brief * EDMA configuration for Sync A copy * * @details * The structure is used to hold the sync A configuration * * \ingroup DPEDMA_EXTERNAL_DATA_STRUCTURE */ typedef struct DPEDMA_syncACfg_t { /*! @brief Source Address */ uint32_t srcAddress; /*! @brief Destination Address */ uint32_t destAddress; /*! @brief a count */ uint16_t aCount; /*! @brief b count */ uint16_t bCount; /*! @brief source B index */ int16_t srcBIdx; /*! @brief destination B index */ int16_t dstBIdx; }DPEDMA_syncACfg; /** * @brief * EDMA configuration for Sync AB copy * * @details * The structure is used to hold the sync AB configuration * * \ingroup DPEDMA_EXTERNAL_DATA_STRUCTURE */ typedef struct DPEDMA_syncABCfg_t { /*! @brief Source Address */ uint32_t srcAddress; /*! @brief Destination Address */ uint32_t destAddress; /*! @brief a count */ uint16_t aCount; /*! @brief b count */ uint16_t bCount; /*! @brief c count */ uint16_t cCount; /*! @brief source B index */ int16_t srcBIdx; /*! @brief destination B index */ int16_t dstBIdx; /*! @brief source C index */ int16_t srcCIdx; /*! @brief destination C index */ int16_t dstCIdx; }DPEDMA_syncABCfg; extern int32_t DPEDMA_configSyncAB ( EDMA_Handle handle, DPEDMA_ChanCfg *chanCfg, DPEDMA_ChainingCfg *chainingCfg, DPEDMA_syncABCfg *syncABCfg, _Bool isEventTriggered, _Bool isIntermediateTransferCompletionEnabled, _Bool isTransferCompletionEnabled, EDMA_transferCompletionCallbackFxn_t transferCompletionCallbackFxn, uintptr_t transferCompletionCallbackFxnArg); extern int32_t DPEDMA_configSyncA_singleFrame ( EDMA_Handle handle, DPEDMA_ChanCfg *chanCfg, DPEDMA_ChainingCfg *chainingCfg, DPEDMA_syncACfg *syncACfg, _Bool isEventTriggered, _Bool isIntermediateTransferInterruptEnabled, _Bool isTransferCompletionEnabled, EDMA_transferCompletionCallbackFxn_t transferCompletionCallbackFxn, uintptr_t transferCompletionCallbackFxnArg ); extern int32_t DPEDMA_updateAddressAndTrigger ( EDMA_Handle handle, uint32_t srcAddress, uint32_t destAddress, uint8_t channel, uint8_t triggerEnabled ); int32_t DPEDMAHWA_configOneHotSignature ( EDMA_Handle edmaHandle, DPEDMA_ChanCfg *chanCfg, HWA_Handle hwaHandle, uint8_t dmaTriggerSource, _Bool isEventTriggered ); int32_t DPEDMAHWA_configTwoHotSignature ( EDMA_Handle edmaHandle, DPEDMA_ChanCfg *chanCfg, HWA_Handle hwaHandle, uint8_t dmaTriggerSource1, uint8_t dmaTriggerSource2, _Bool isEventTriggered ); /* * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file rangeproc_common.h * * @brief * Implements Common definition across rangeProc DPU. */ /** * @mainpage RangeProc DPU * [TOC] * This DPU implements range processing using hardware accelerator(HWA) and DSP. * * @section dpu_range_intro RangeProc DPU * * Description * ---------------- * * Range Processing Unit takes RF data in ADC buffer, computes 1D FFT and saves results in * radarCube in the requested format. * * Range Processing includes two DPU implementations: * * DPU | runs on cores * :------------|:---------------- * rangeProcHWA| R4F or DSP * rangeProcDSP| DSP * * * Data Interface * ---------------- * * Range processing only supports 16bits complex data in ImRe format (@ref DPIF_DATAFORMAT_COMPLEX16_IMRE).\n * Range processing data Input interface is defined by @ref DPIF_ADCBufData_t.\n * Range processing data Output interface is define by @ref DPIF_RadarCube_t.\n * The parameters for radarCube are defined in @ref DPU_RangeProcHWA_StaticConfig_t or @ref DPU_RangeProcDSP_StaticConfig_t. * * Both rangeProcHWA and rangeProcDSP has the same data interface as described above. However rangeProcHWA * supports more input and output formats. Refer to each DPU for more details. * * * Antenna Coupling Signature Removal * ---------------- * * Antenna coupling signature dominates the range bins close to the radar. * These are the bins in the range FFT output located around DC. * * This feature can be enabled/disabled through configuration @ref DPU_RangeProc_CalibDcRangeSigCfg_t at configure time or at run time. * * After the feature is enabled, it does calibration for * @ref DPU_RangeProc_CalibDcRangeSigCfg_t::numAvgChirps doppler chirps. * During calibration, each of the specified range bins * ([@ref DPU_RangeProc_CalibDcRangeSigCfg_t::negativeBinIdx, * @ref DPU_RangeProc_CalibDcRangeSigCfg_t::positiveBinIdx]) for each of the * virtual antennas are accumulated over the specified number of chirps ("numAvgChirps") * and at the end of the period, the average is computed for each range bin * and each virtual antenna combination. * * It is assumed that no objects are present in the vicinity of the radar during * this calibration period. After calibration is done, the removal starts for * all subsequent frames for each range bin and virtual antenna, average estimate is * subtracted from the corresponding received samples in real-time for subsequent processing. * * @note The number of chirps to average(numAvgChirps) must be power of 2. * * RangeProc DPUs * --------------------- * - RangeProc using HWA \ref dpu_rangehwa * - RangeProc using DSP \ref dpu_rangedsp * */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /** @defgroup DPU_RANGEPROC_EXTERNAL_FUNCTION rangeProc DPU External Functions @ingroup RANGE_PROC_DPU @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the rangeProc DPU */ /** @defgroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE rangeProc DPU External Data Structures @ingroup RANGE_PROC_DPU @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DPU_RANGEPROC_ERROR_CODE rangeProc DPU Error Codes @ingroup RANGE_PROC_DPU @brief * The section has a list of all the error codes which are generated by the sampleProc DPU */ /** @defgroup DPU_RANGEPROC_INTERNAL_FUNCTION rangeProc DPU Internal Functions @ingroup RANGE_PROC_DPU @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup DPU_RANGEPROC_INTERNAL_DATA_STRUCTURE rangeProc DPU Internal Data Structures @ingroup RANGE_PROC_DPU @brief * The section has a list of all internal data structures which are used internally * by the rangeProc DPU module. */ /** @defgroup DPU_RANGEPROC_INTERNAL_DEFINITION rangeProc DPU Internal Definitions @ingroup RANGE_PROC_DPU @brief * The section has a list of all internal definitions which are used internally * by the rangeProc DPU. */ /** @brief Maximum number of 1D FFT bins in DC range antenna signature compensation */ /** * @brief * Data Path DC range signature compensation * * @details * The structure contains the DC range antenna signature removeal configuration used in data path * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProc_CalibDcRangeSigCfg_t { /*! @brief enabled flag: 1-enabled 0-disabled */ uint16_t enabled; /*! @brief maximum negative range bin (1D FFT index) to be compensated */ int16_t negativeBinIdx; /*! @brief maximum positive range bin (1D FFT index) to be compensated */ int16_t positiveBinIdx; /*! @brief number of chirps in the averaging phase */ uint16_t numAvgChirps; } DPU_RangeProc_CalibDcRangeSigCfg; /** * @brief * Data processing Unit statistics * * @details * The structure is used to hold the statistics of the DPU * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProc_stats_t { /*! @brief total processing time during all chirps in a frame excluding EDMA waiting time*/ uint32_t processingTime; /*! @brief total wait time for EDMA data transfer during all chirps in a frame*/ uint32_t waitTime; }DPU_RangeProc_stats; /*! Number of HWA parameter sets */ /*! Alignment for DC range signal mean buffer - if DPU is running on DSP(C674) */ /*! Alignment for DC range signal mean buffer - if DPU is running on R4F */ /** @addtogroup DPU_RANGEPROC_ERROR_CODE * Base error code for the rangeProc DPU is defined in the * \include ti/datapath/dpif/dp_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Internal error */ /** * @brief Error Code: Not implemented */ /** * @brief Error Code: Not implemented */ /** * @brief Error Code: Invalid control command */ /** * @brief Error Code: Semaphore error */ /** * @brief Error Code: DC range signal removal configuration error */ /** * @brief Error Code: ADCBuf data interface configuration error */ /** * @brief Error Code: ADCBuf data interface configuration error */ /** * @brief Error Code: HWA windowing configuration error */ /** * @brief Error Code: Incorrect number of butterfly stages specified for scaling */ /** @} */ /** * @brief * RangeProc data input mode * * @details * This enum defines if the rangeProc input data is from RF front end or it is in M0 but * standalone from RF. * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef enum DPU_RangeProcHWA_InputMode_e { /*! @brief Range input is integrated with DFE input ADC buffer is mapped to HWA memory DMA data from ADC buffer to HWA is NOT required */ DPU_RangeProcHWA_InputMode_MAPPED, /*! @brief Range input is integrated with DFE input ADC buffer is not mapped to HWA memory, DMA data from ADCBuf to HWA memory is needed in range processing */ DPU_RangeProcHWA_InputMode_ISOLATED } DPU_RangeProcHWA_InputMode; /** * @brief * rangeProc control command * * @details * The enum defines the rangeProc supported run time command * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef enum DPU_RangeProcHWA_Cmd_e { /*! @brief Command to update DC Signature removal configuration */ DPU_RangeProcHWA_Cmd_dcRangeCfg, /*! @brief Command to trigger rangeProcHWA process */ DPU_RangeProcHWA_Cmd_triggerProc, }DPU_RangeProcHWA_Cmd; /** * @brief * rangeProc FFT tuning parameters for HWA based Range FFT * * @details * This structure allows users to tune the scaling factors for HWA based Range FFTs * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_FFTtuning_t{ /*! @brief Specify amount of right (divide) shift to apply to convert HWA internal 24-bit Range FFT output to 16-bit RadarCube. User should adjust this based on the setup where sensor is deployed and sensors setting for Tx O/P power/RX gain and their application needs */ uint16_t fftOutputDivShift; /*! @brief Specify number of Last butterfly stages to scale to avoid clipping within HWA FFT stages. Given the ADC data bit width of 16-bits and internal 24-bit width of HWA, user has around 8-bits to grow Range FFT output and should not need to use butterfly scaling for FFT sizes upto 256. Beyond that fft size, user should adjust this based on the setup where sensor is deployed and sensors setting for Tx O/P power/RX gain*/ uint16_t numLastButterflyStagesToScale; }DPU_RangeProcHWA_FFTtuning; /** * @brief * RangeProc HWA configuration * * @details * The structure is used to hold the HWA configuration needed for Range FFT * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_HwaConfig_t { /*! @brief HWA paramset Start index */ uint8_t paramSetStartIdx; /*! @brief Number of HWA param sets must be @ref DPU_RANGEPROCHWA_NUM_HWA_PARAM_SETS */ uint8_t numParamSet; /*! @brief Flag to indicate if HWA windowing is symmetric see HWA_WINDOW_SYMM definitions in HWA driver's doxygen documentation */ uint8_t hwaWinSym; /*! @brief HWA windowing RAM offset in number of samples */ uint16_t hwaWinRamOffset; /*! @brief Data Input Mode, */ DPU_RangeProcHWA_InputMode dataInputMode; }DPU_RangeProcHWA_HwaConfig; /** * @brief * RangeProc EDMA configuration * * @details * The structure is used to hold the EDMA configuration needed for Range FFT * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_EDMAInputConfig_t { /*! @brief EDMA configuration for rangeProc data Input This is needed only in @ref DPU_RangeProcHWA_InputMode_ISOLATED */ DPEDMA_ChanCfg dataIn; /*! @brief EDMA configuration for rangeProc data Input Signature */ DPEDMA_ChanCfg dataInSignature; }DPU_RangeProcHWA_EDMAInputConfig; /** * @brief * RangeProc EDMA configuration * * @details * The structure is used to hold the EDMA configuration needed for Range FFT * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_EDMAOutputConfigFmt1_t { /*! @brief EDMA configuration for rangeProc data Out- ping It must be a HWACC triggered EDMA channel. */ DPEDMA_ChanCfg dataOutPing; /*! @brief EDMA configuration for rangeProc data Out- pong It must be a HWACC triggered EDMA channel */ DPEDMA_ChanCfg dataOutPong; }DPU_RangeProcHWA_EDMAOutputConfigFmt1; /** * @brief * RangeProc EDMA configuration * * @details * The structure is used to hold the EDMA configuration needed for Range FFT * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_EDMAOutputConfigFmt2_t { /*! @brief EDMA configuration for rangeProc data Out- ping It must be a HWACC triggered EDMA channel */ DPEDMA_3LinkChanCfg dataOutPing; DPEDMA_ChanCfg dataOutPingData[3]; /*! @brief EDMA configuration for rangeProc data Out- pong It must be a HWACC triggered EDMA channel */ DPEDMA_3LinkChanCfg dataOutPong; DPEDMA_ChanCfg dataOutPongData[3]; }DPU_RangeProcHWA_EDMAOutputConfigFmt2; /** * @brief * RangeProc output EDMA configuration * * @details * The structure is used to hold the EDMA configuration needed for Range FFT * * Fmt1: Generic EDMA ping/pong output mode * - 1 ping/pong EDMA channel, * - 1 ping/pong HWA signature channel * * Fmt2: Specific EDMA ping/pong output mode used ONLY for 3 TX anntenna for radar cube * layout format: @ref DPIF_RADARCUBE_FORMAT_1, ADCbuf interleave mode * @ref DPIF_RXCHAN_NON_INTERLEAVE_MODE * - 1 ping/pong dummy EDMA channel with 3 shadow channels - 3 ping/pong dataOut channel * - 1 ping/pong HWA signature channel * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_EDMAOutputConfig_t { /*! @brief EDMA data output Signature */ DPEDMA_ChanCfg dataOutSignature; union { /*! @brief EDMA data output fmt1 @ref DPU_RangeProcHWA_EDMAOutputConfigFmt1 */ DPU_RangeProcHWA_EDMAOutputConfigFmt1 fmt1; /*! @brief EDMA data output fmt2 @ref DPU_RangeProcHWA_EDMAOutputConfigFmt2 */ DPU_RangeProcHWA_EDMAOutputConfigFmt2 fmt2; }u; }DPU_RangeProcHWA_EDMAOutputConfig; /** * @brief * RangeProcHWA hardware resources * * @details * The structure is used to hold the hardware resources needed for Range FFT * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_HW_Resources_t { /*! @brief EDMA Handle */ EDMA_Handle edmaHandle; /*! @brief HWA configuration */ DPU_RangeProcHWA_HwaConfig hwaCfg; /*! @brief EDMA configuration for rangeProc data Input */ DPU_RangeProcHWA_EDMAInputConfig edmaInCfg; /*! @brief EDMA configuration for rangeProc data Output */ DPU_RangeProcHWA_EDMAOutputConfig edmaOutCfg; /*! @brief Pointer to Calibrate DC Range signature buffer The size of the buffer = DPU_RANGEPROC_SIGNATURE_COMP_MAX_BIN_SIZE * numTxAntenna * numRxAntenna * sizeof(cmplx32ImRe_t) For R4F:\n Byte alignment Requirement = @ref DPU_RANGEPROCHWA_DCRANGESIGMEAN_BYTE_ALIGNMENT_R4F \n For DSP (C674X):\n Byte alignment Requirement = @ref DPU_RANGEPROCHWA_DCRANGESIGMEAN_BYTE_ALIGNMENT_DSP \n */ cmplx32ImRe_t *dcRangeSigMean; /*! @brief DC range calibration scratch buffer size */ uint32_t dcRangeSigMeanSize; /*! @brief Radar cube data interface */ DPIF_RadarCube radarCube; }DPU_RangeProcHWA_HW_Resources; /** * @brief * RangeProcHWA static configuration * * @details * The structure is used to hold the static configuraiton used by rangeProcHWA * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_StaticConfig_t { /*! @brief Number of transmit antennas */ uint8_t numTxAntennas; /*! @brief Number of virtual antennas */ uint8_t numVirtualAntennas; /*! @brief Number of range bins */ uint16_t numRangeBins; /*! @brief Number of chirps per frame */ uint16_t numChirpsPerFrame; /*! @brief Range FFT window coefficients, Appliation provided windows coefficients After @ref DPU_RangeProcHWA_config(), windowing buffer is not used by rangeProcHWA DPU, Hence memory can be released */ int32_t *window; /*! @brief Range FFT window coefficients size in bytes non-symmetric window, size = sizeof(uint32_t) * numADCSamples symmetric window, size = sizeof(uint32_t)*(numADCSamples round up to even number )/2 */ uint32_t windowSize; /*! @brief ADCBuf buffer interface */ DPIF_ADCBufData ADCBufData; /*! @brief Flag to reset dcRangeSigMean buffer 1 - to reset the dcRangeSigMean buffer and counter 0 - do not reset */ uint8_t resetDcRangeSigMeanBuffer; /*! @brief Range FFT Tuning Params */ DPU_RangeProcHWA_FFTtuning rangeFFTtuning; }DPU_RangeProcHWA_StaticConfig; /** * @brief * RangeProcHWA dynamic configuration * * @details * The structure is used to hold the dynamic configuraiton used by rangeProcHWA * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_DynamicConfig_t { /*! @brief Pointer to Calibrate DC Range signature configuration */ DPU_RangeProc_CalibDcRangeSigCfg *calibDcRangeSigCfg; }DPU_RangeProcHWA_DynamicConfig; /** * @brief * Range FFT configuration * * @details * The structure is used to hold the configuration needed for Range FFT * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_Config_t { /*! @brief rangeProc hardware resources */ DPU_RangeProcHWA_HW_Resources hwRes; /*! @brief rangeProc static configuration */ DPU_RangeProcHWA_StaticConfig staticCfg; /*! @brief rangeProc dynamic configuration */ DPU_RangeProcHWA_DynamicConfig dynCfg; }DPU_RangeProcHWA_Config; /** * @brief * rangeProcHWA output parameters populated during rangeProc Processing time * * @details * The structure is used to hold the output parameters for rangeProcHWA * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_InitParams_t { /*! @brief HWA Handle */ HWA_Handle hwaHandle; }DPU_RangeProcHWA_InitParams; /** * @brief * rangeProcHWA output parameters populated during rangeProc Processing time * * @details * The structure is used to hold the output parameters for rangeProcHWA * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_RangeProcHWA_OutParams_t { /*! @brief End of Chirp indication for rangeProcHWA */ _Bool endOfChirp; /*! @brief rangeProcHWA stats */ DPU_RangeProc_stats stats; }DPU_RangeProcHWA_OutParams; /** * @brief * rangeProc DPU Handle * * \ingroup DPU_RANGEPROC_EXTERNAL_DATA_STRUCTURE */ typedef void* DPU_RangeProcHWA_Handle ; /*================================================================ rangeProcHWA DPU exposed APIs ================================================================*/ DPU_RangeProcHWA_Handle DPU_RangeProcHWA_init ( DPU_RangeProcHWA_InitParams *initParams, int32_t* errCode ); int32_t DPU_RangeProcHWA_config ( DPU_RangeProcHWA_Handle handle, DPU_RangeProcHWA_Config* rangeHwaCfg ); int32_t DPU_RangeProcHWA_process ( DPU_RangeProcHWA_Handle handle, DPU_RangeProcHWA_OutParams* outParams ); int32_t DPU_RangeProcHWA_control ( DPU_RangeProcHWA_Handle handle, DPU_RangeProcHWA_Cmd cmd, void* arg, uint32_t argSize ); int32_t DPU_RangeProcHWA_deinit ( DPU_RangeProcHWA_Handle handle ); /** * @file staticclutterproc.h * * @brief * staticclutterproc DPU include file * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Data Path include files */ /** @defgroup STATICCLUTTER_PROC_DPU_EXTERNAL staticClutterProc DPU External */ /** @defgroup DPU_STATICCLUTTERPROC_EXTERNAL_FUNCTION staticclutterproc DPU External Functions @ingroup STATICCLUTTER_PROC_DPU_EXTERNAL @brief * The section has a list of all the exported APIs which the application needs to * invoke in order to use the DPU */ /** @defgroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE staticclutterproc DPU External Data Structures @ingroup STATICCLUTTER_PROC_DPU_EXTERNAL @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DPU_STATICCLUTTERPROC_ERROR_CODE staticclutterproc DPU Error Codes @ingroup STATICCLUTTER_PROC_DPU_EXTERNAL @brief * The section has a list of all the error codes which are generated by the staticclutterproc DPU */ /************************************************************** **** staticclutterproc DPU exposed definitions **** **************************************************************/ /** * @brief Error Code: Invalid argument * \ingroup DPU_STATICCLUTTERPROC_ERROR_CODE * Base error code for the static clutter proc is defined in the * \include ti/datapath/dpif/dp_error.h */ /** * @brief Error Code: No memory * \ingroup DPU_STATICCLUTTERPROC_ERROR_CODE */ /** * @brief Error Code: Scratch buffer has incorrect size or incorrect alignment * \ingroup DPU_STATICCLUTTERPROC_ERROR_CODE */ /** * @brief Required alignment for scratch buffer provided by application * (if DPU is running on DSP (C674X)) */ /** * @brief Required alignment for scratch buffer provided by application * (if DPU is running on R4F) */ /*! * @brief Handle for static clutter DPU. */ typedef void* DPU_StaticClutterProc_Handle; /** * @brief * staticclutterproc DPU EDMA configuration parameters * * @details * The structure is used to hold the EDMA configuration parameters * for the static clutter removal DPU * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_EdmaCfg_t { /*! @brief EDMA Ping channel. */ DPEDMA_ChanCfg ping; /*! @brief EDMA Pong channel. */ DPEDMA_ChanCfg pong; }DPU_StaticClutterProc_EdmaCfg; /** * @brief * Scratch buffer used by DPU * * @details * The structure defines the scratch buffer interface, including * size and data pointer. This buffer should be allocated from * internal memory (TCMB if running on R4F and L2/L1 SRAM on DSP) as the * clutter removal algorithm will be performed on data sitting * on this buffer. * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_ScratchBuf_t { /*! @brief Scratch buffer size in bytes.\n Size must be at least:\n Y*2*sizeof(cmplx16ImRe_t)\n Where:\n For R4F: Y is equal to numDopplerChirps\n For DSP (C674X): Y is the smallest multiple of 4 greater or equal to numDopplerChirps\n */ uint32_t bufSize; /*! @brief Scratch buffer data pointer.\n For R4F:\n Byte alignment Requirement = @ref DPU_STATICCLUTTERPROC_SCRATCHBUFFER_BYTE_ALIGNMENT_R4F \n For DSP (C674X):\n Byte alignment Requirement = @ref DPU_STATICCLUTTERPROC_SCRATCHBUFFER_BYTE_ALIGNMENT_DSP \n */ void *buf; }DPU_StaticClutterProc_ScratchBuf; /** * @brief * staticclutterproc DPU HW configuration parameters * * @details * The structure is used to hold the HW configuration parameters * for the static clutter removal DPU * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_HW_Resources_t { /*! @brief EDMA driver handle. */ EDMA_Handle edmaHandle; /*! @brief EDMA configuration for Input data (Radar cube -> Scratch buffer). */ DPU_StaticClutterProc_EdmaCfg edmaIn; /*! @brief EDMA configuration for Output data (Scratch buffer -> Radar cube). */ DPU_StaticClutterProc_EdmaCfg edmaOut; /*! @brief Radar Cube. This DPU supports only one cube format: @ref DPIF_RADARCUBE_FORMAT_1 */ DPIF_RadarCube radarCube; /*! @brief Scratch buffer */ DPU_StaticClutterProc_ScratchBuf scratchBuf; }DPU_StaticClutterProc_HW_Resources; /** * @brief * Doppler DPU static configuration parameters * * @details * The structure is used to hold the static configuration parameters * for the Doppler DPU * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_StaticConfig_t { /*! @brief Number of transmit antennas */ uint8_t numTxAntennas; /*! @brief Number of receive antennas */ uint8_t numRxAntennas; /*! @brief Number of virtual antennas */ uint8_t numVirtualAntennas; /*! @brief Number of range bins */ uint16_t numRangeBins; /*! @brief Number of Doppler chirps. */ uint16_t numDopplerChirps; }DPU_StaticClutterProc_StaticConfig; /** * @brief * staticclutterproc DPU configuration parameters * * @details * The structure is used to hold the configuration parameters * for the static clutter removal DPU * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_Config_t { /*! @brief HW resources. */ DPU_StaticClutterProc_HW_Resources hwRes; /*! @brief Static configuration. */ DPU_StaticClutterProc_StaticConfig staticCfg; }DPU_StaticClutterProc_Config; /** * @brief * Data processing unit statistics * * @details * The structure is used to hold the statistics of the DPU * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_Stats_t { /*! @brief total processing time for one execution of the DPU*/ uint32_t processingTime; }DPU_StaticClutterProc_Stats; /** * @brief * DPU processing output parameters * * @details * The structure is used to hold the output parameters DPU processing * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_StaticClutterProc_OutParams_t { /*! @brief DPU statistics */ DPU_StaticClutterProc_Stats stats; }DPU_StaticClutterProc_OutParams; /************************************************************** **** staticclutterproc DPU exposed APIs **** **************************************************************/ /** * @b Description * @n * staticclutterproc DPU init function. It allocates memory to store * DPU's internal data object and returns a handle if it executes successfully. * * @param[in] errCode Pointer to errCode generates from the API * @ref DPU_STATICCLUTTERPROC_ERROR_CODE * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_FUNCTION * * @retval * Success - valid handle * @retval * Error - NULL */ DPU_StaticClutterProc_Handle DPU_StaticClutterProc_init(int32_t* errCode); /** * @b Description * @n * staticclutterproc DPU deinit function. It release resources used for the DPU. * * @param[in] handle staticclutterproc handle. * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_FUNCTION * * @retval * Success =0 * @retval * Error !=0 @ref DPU_STATICCLUTTERPROC_ERROR_CODE */ int32_t DPU_StaticClutterProc_deinit(DPU_StaticClutterProc_Handle handle); /** * @b Description * @n * staticclutterproc DPU process function. * This function executes the static clutter removal algorithm on data sitting * on the scratch buffer in a ping/pong fashion.\n * The data is first brought from radarCube into scratch buffer by EDMA, * then static clutter removal is performed and data is moved back by EDMA * from scratch buffer to radarCube. All hardware resources (EDMA properties), * buffers and static configuration are provided by application through * @ref DPU_StaticClutterProc_config.\n * Note that the subtraction step of the static clutter removal * algorithm performs a saturated subtraction on every sample. * * @param[in] handle staticclutterproc handle. * @param[out] outParams Output parameters. * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_FUNCTION * * @retval * Success =0 * @retval * Error !=0 @ref DPU_STATICCLUTTERPROC_ERROR_CODE */ int32_t DPU_StaticClutterProc_process(DPU_StaticClutterProc_Handle handle, DPU_StaticClutterProc_OutParams *outParams); /** * @b Description * @n * staticclutterproc DPU config function. It stores the data path parameters * and configures relevant components that will be used in its process and. * * @param[in] handle staticclutterproc handle. * @param[in] cfg staticclutterproc configuration.0 * * \ingroup DPU_STATICCLUTTERPROC_EXTERNAL_FUNCTION * * @retval * Success =0 * @retval * Error !=0 @ref DPU_STATICCLUTTERPROC_ERROR_CODE */ int32_t DPU_StaticClutterProc_config(DPU_StaticClutterProc_Handle handle, DPU_StaticClutterProc_Config *cfg); /** * @file cfarcaprochwa.h * * @brief * Implements CFARCA DPU using HWA. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /* mmWave SDK Driver/Common Include Files */ /* Datapath files */ /** * @file dpif_detmatrix.h * * @brief * Defines the detection matrix buffer interface * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* @brief definition for detection matrix data QFormat */ /** * @defgroup DPIF_DETMATRIX_FORMAT DPIF_DETMATRIX_FORMAT * @brief Combination of C structure declaration and Content that uniquely describes the detection matrix * * * # |Declaration |Content *---| ----------------------------------------|------------------------------ * 1 |uint16_t x[numRangeBins][numDopplerBins] |Range-Doppler Detection Matrix * @{ */ /** @}*/ /*DPIF_DETMATRIX_FORMAT*/ /** * @brief * Detection matrix buffer interface * * @details * The structure defines the detection matrix buffer interface, including data property, * size and pointer */ typedef struct DPIF_DetMatrix_t { /*! @brief Detection Matrix data Format @ref DPIF_DETMATRIX_FORMAT */ uint32_t datafmt; /*! @brief Detection Matrix buffer size in bytes */ uint32_t dataSize; /*! @brief Detection Matrix data pointer User could remap this to specific typedef using information in @ref DPIF_DETMATRIX_FORMAT */ void *data; }DPIF_DetMatrix; /** * @file dpif_pointcloud.h * * @brief * Defines the point cloud interfaces used in data path processing. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* MMWAVE SDK Include Files */ /** * @brief * Point cloud definition in Cartesian coordinate system */ typedef struct DPIF_PointCloudCartesian_t { /*! @brief x - coordinate in meters. This axis is parallel to the sensor plane * and makes the azimuth plane with y-axis. Positive x-direction is rightward * in the azimuth plane when observed from the sensor towards the scene * and negative is the opposite direction. */ float x; /*! @brief y - coordinate in meters. This axis is perpendicular to the * sensor plane with positive direction from the sensor towards the scene */ float y; /*! @brief z - coordinate in meters. This axis is parallel to the sensor plane * and makes the elevation plane with the y-axis. Positive z direction * is above the sensor and negative below the sensor */ float z; /*! @brief Doppler velocity estimate in m/s. Positive velocity means target * is moving away from the sensor and negative velocity means target * is moving towards the sensor. */ float velocity; }DPIF_PointCloudCartesian; /** * @brief * Alignment for memory allocation purposes for structure @ref DPIF_PointCloudCartesian_t * when structure is accessed by the CPU. Alignment is the maximum sized field in the structure. */ /** * @brief * Point cloud side information such as SNR and noise level * * @details * The structure describes the field for a point cloud in XYZ format */ typedef struct DPIF_PointCloudSideInfo_t { /*! @brief snr - CFAR cell to side noise ratio in dB expressed in 0.1 steps of dB */ int16_t snr; /*! @brief y - CFAR noise level of the side of the detected cell in dB expressed in 0.1 steps of dB */ int16_t noise; }DPIF_PointCloudSideInfo; /** * @brief * Alignment for memory allocation purposes for structure @ref DPIF_PointCloudSideInfo_t * when structure is accessed by the CPU. Alignment is the maximum sized field in the structure. */ /** * @brief * Point cloud definition in spherical coordinate system */ typedef struct DPIF_PointCloudSpherical_t { /*! @brief Range in meters */ float range; /*! @brief Azimuth angle in degrees in the range [-90,90], * where positive angle represents the right hand side as viewed * from the sensor towards the scene and negative angle * represents left hand side */ float azimuthAngle; /*! @brief Elevation angle in degrees in the range [-90,90], where positive angle represents above the sensor and negative * below the sensor */ float elevAngle; /*! @brief Doppler velocity estimate in m/s. Positive velocity means target * is moving away from the sensor and negative velocity means target * is moving towards the sensor. */ float velocity; }DPIF_PointCloudSpherical; /** * @brief * Alignment for memory allocation purposes for structure @ref DPIF_PointCloudSpherical_t * when structure is accessed by the CPU. Alignment is the maximum sized field in the structure. */ /** * @brief * CFAR detection output * * @details * The holds CFAR detections with SNR * */ typedef volatile struct DPIF_CFARDetList_t { uint16_t rangeIdx; /*!< Range index */ uint16_t dopplerIdx; /*!< Doppler index */ int16_t snr; /*!< Signal to noise power ratio in steps of 0.1 dB */ int16_t noise; /*!< Noise level in steps of 0.1 dB */ } DPIF_CFARDetList; /** * @brief * Alignment for memory allocation purposes for structure @ref DPIF_CFARDetList * when structure is accessed by the CPU. Alignment is the maximum sized field in the structure. */ /** * @file cfarcaproccommon.h * * @brief * Implements Common definition across cfarcaProc DPU. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage CFARCA DPU * [TOC] * @section cfarca_intro_section CFAR-CA DPU * * This DPU implements CFAR object detection from the Range/Doppler detection * matrix. * * * CFARCA DPU includes two DPU implementations: * * DPU | runs on cores * :------------|:---------------- * cfarcaProcHWA| R4F or DSP * cfarcaProcDSP| DSP * * @section cfarca_hwa HWA-CFARCA DPU * * @subsection cfarcahwa_intro_section Introduction * This DPU implements CFAR object detection from the Range/Doppler detection * matrix using hardware accelerator (HWA). * CFAR detection is performed in both Range and Doppler domains. The DPU exports * the list of objects that are detected both in range and in Doppler domains. * A high level data flow is illustrated in figure below. * * @image html hwa_cfar_top_level.png "HWA-CFAR high level data flow" * * The following figure depicts the DPU implementation: * * @image html hwa_cfar.png "HWA-CFAR implementation" * * The input is detection matrix * as per the format @ref DPIF_DetMatrix @ref DPIF_DETMATRIX_FORMAT_1, the elements * of this matrix are sum of log2 magnitudes across received antennas of the 2D FFT. * This matrix must be no bigger than what can fit in M0+M1 memory (error checking * is done during @ref DPU_CFARCAProcHWA_config and violation will generate error code * @ref DPU_CFARCAPROCHWA_ENOMEM__DET_MATRIX_EXCEEDS_HWA_INP_MEM). * * The detection process is initiated by triggering input EDMA (@ref DPU_CFARCAProcHWA_HW_Resources::edmaHwaIn) * that copies detection matrix(@ref DPIF_DetMatrix) * from L3 memory to internal HWA memory (@ref DPU_CFARCAProcHWA_HW_Resources::hwaMemInp, typically * (M0+M1)). Signature EDMA (@ref DPU_CFARCAProcHWA_HW_Resources::edmaHwaInSignature) * then triggers HWA CFAR which is executed * with one param set that performs CFAR in Doppler domain. * The results are stored in HWA memory * (@ref DPU_CFARCAProcHWA_HW_Resources::hwaMemOutDoppler, typically M2) as a list with each element represented * as @ref DPU_CFARCAProcHWA_CfarDetOutput_t. * Upon completion, the CPU triggers the HWA CFAR in range domain with the results * directed to HWA memory (@ref DPU_CFARCAProcHWA_HW_Resources::hwaMemOutRange, typically in M3) * and then in parallel calculates * (@ref CFARHWA_convHwaCfarDetListToDetMask) the bit mask of detected points * and puts it in to the @ref DPU_CFARCAProcHWA_HW_Resources::cfarDopplerDetOutBitMask * that is allocated by the application (typically in core local memory). * The bit position in the array corresponding to element x[rangeIdx][dopplerIdx] * is calculated as shown in the figure above (expressions "word = , bit = "). * * After the HWA CFAR detection is completed, the CPU (@ref CFARHWA_cfarRange_AND_cfarDoppler) * takes detected objects from the range CFAR detection list (M3 memory) and * populates in the output list (@ref DPIF_CFARDetList_t) * if the following conditions are satisfied: * 1. The object is also detected in the Doppler domain (i.e. if the corresponding * bit is set in the Doppler detection bit mask). * 2. The range and doppler indices are within those determined from the * FOV configuration given by the application when issuing any of the following: * - @ref DPU_CFARCAProcHWA_config (@ref DPU_CFARCAProcHWA_DynamicConfig::fovRange, @ref DPU_CFARCAProcHWA_DynamicConfig::fovDoppler) * - @ref DPU_CFARCAProcHWA_control (@ref DPU_CFARCAProcHWA_Cmd_FovRangeCfg, @ref DPU_CFARCAProcHWA_Cmd_FovDopplerCfg). * * In this output list, side information of noise (from the range CFAR HWA processing) * and SNR is also populated for each of the generated points in this list. The * SNR is calculated using the noise (from range CFAR HWA) and the detection matrix * value corresponding to the detected range,doppler position. * * The HWA CFAR function can also perform peak grouping functionality. It (enable/disable) * is configured from the application when issuing @ref DPU_CFARCAProcHWA_config (@ref DPU_CFARCAProcHWA_DynamicConfig::cfarCfgRange, * @ref DPU_CFARCAProcHWA_DynamicConfig::cfarCfgDoppler) or when issuing @ref DPU_CFARCAProcHWA_control (@ref DPU_CFARCAProcHWA_Cmd_CfarRangeCfg, * @ref DPU_CFARCAProcHWA_Cmd_CfarDopplerCfg). These configurations also allow CFAR parameters * like threshold scale and window/guard lengths to be set. The CFAR detection processing in * the Doppler domain can be bypassed by setting doppler direction's detection threshold to zero. * In this case the peak grouping in the Doppler domain is unavailable. * @warning * For xWR18xx: The HWA's peak grouping functionality declares peak if the cell * under test is strictly greater than its most immediate neighboring cells. * This implies that if neighbors were exactly identical, then a CFAR detected peak group * corresponding to an object can result in no single peak being declared belonging * to this group i.e the object that otherwise was declared detected by CFAR would * be undetected due to peak grouping. The chance of neighbors being identical * depends on how the input to the CFAR algorithm is generated and also the * type of CFAR algorithm. For example, when the input to CFAR is * coming from sum across virtual antennas of the log * magnitude of 2D FFT, there is a chance of having identical * neighbor peaks because of the type of FFT windows used in range or * doppler FFTs (wider main lobes may increase the chance), * the nature of log function (more flattening at higher values), * the approximations in the implementation of log and magnitude calculations, * the degree of interpolation of FFTs (more interpolation may increase chance), etc. * Users are advised to disable peak grouping functionality if this inversion * in detectability is not acceptable for their application. * * * The HWA-CFAR timing diagram is illustrated in figure below. * * @image html hwa_cfar_timing.png "HWA-CFAR timing" * * @subsection cfarcahwa_apis CFARCA HWA APIs * * - @ref DPU_CFARCAProcHWA_init DPU initialization initialization function. * - @ref DPU_CFARCAProcHWA_config DPU configuration function. The configuration can only be done after * the DPU has been initialized using @ref DPU_CFARCAProcHWA_init. * * - @ref DPU_CFARCAProcHWA_process DPU processing function. This will execute the CFAR detection * algorithm using HWA. This processing can only be done after the DPU has been configured through. * - @ref DPU_CFARCAProcHWA_config. If the parameters used by this DPU do not * change from one frame to the next, @ref DPU_CFARCAProcHWA_config can be called only once for the first * frame and for every frame @ref DPU_CFARCAProcHWA_process can be executed without the need of reconfiguring the DPU. * - @ref DPU_CFARCAProcHWA_control DPU control function. It processes the following messages received from DPC: * - @ref DPU_CFARCAProcHWA_Cmd_CfarRangeCfg, * - @ref DPU_CFARCAProcHWA_Cmd_CfarDopplerCfg, * - @ref DPU_CFARCAProcHWA_Cmd_FovRangeCfg, * - @ref DPU_CFARCAProcHWA_Cmd_FovDopplerCfg * * Full API details can be seen at @ref CFARCA_PROC_DPU_EXTERNAL * * @section cfarca_dsp DSP-CFARCA DPU * * @subsection cfarcadsp_intro_section Introduction * This DPU implements CFAR object detection from the Range/Doppler detection * matrix using CFAR and Peak grouping algorithms running on DSP. * CFAR detection is performed in both Range and Doppler domains. The DPU exports * the list of objects that are detected both in range and in Doppler domains. * A high level data flow is illustrated in figure below. * * @image html dsp_cfar_top_level.png "DSP-CFAR high level data flow" * * The size of detection objects list is defined by DPU_CFARCAProcDSP_HW_Resources_t::cfarRngDopSnrListSize. * When there is only doppler domain or range domain processing, it is possible that the detected objects are truncated due to this size limitation. * When both doppler domain and range domain processing are enabled, the ouput from doppler domain will be put in doppler detection bit mask array only, * hence it is not limited by the size. After range domain processing, the detection list is then populated. If there are too many detected objects, * the list will be truncated to DPU_CFARCAProcDSP_HW_Resources_t::cfarRngDopSnrListSize. * * The following figure depicts the DPU implementation: * * @image html dsp_cfar.png "DSP-CFAR implementation" * * The input is range-doppler detection matrix * as per the format @ref DPIF_DetMatrix @ref DPIF_DETMATRIX_FORMAT_1, the elements * of this matrix are sum of log2 magnitudes across received antennas of the 2D FFT. * * The doppler domain detection process is initiated by triggering input EDMA (@ref DPU_CFARCAProcDSP_HW_Resources::edmaInPing and edmaInPong) * that copies detection matrix(@ref DPIF_DetMatrix) from L3 memory to local buffer (@ref DPU_CFARCAProcDSP_HW_Resources::localDetMatrixBuffer) * one range bin at a time in ping/pong manner. * It then executes CFARCA algorithm and generates cfarDopplerDetOutBitMask based on detection results. * * Upon completion of all range bins and whole cfarDopplerDetOutBitMask table is populated, the CPU starts CFAR in range domain for those doppler lines * that have detected objects as indicated by cfarDopplerDetOutBitMask. * * After the DSP CFAR detection is completed, if peak grouping is enabled, peak * grouping is performed and final detected objects list(@ref DPIF_CFARDetList_t) is populated. * @note Unlike the HWA CFAR case, the DSP implementation declares peak if peak under * evaluation is greater than *or equal to* the neighbors (CFAR qualified or not) so * the problem described earlier in HWA CFAR's peak grouping does not exist for this * DSP implementation. * * * Object is presented in the final list if the following conditions are satisfied: * 1. The object is detected in both Doppler and Range domain * 2. The range and doppler indices are within those determined from the * FOV configuration given by the application when issuing any of the following: * - @ref DPU_CFARCAProcDSP_config (@ref DPU_CFARCAProcDSP_DynamicConfig::fovRange, @ref DPU_CFARCAProcDSP_DynamicConfig::fovDoppler) * - @ref DPU_CFARCAProcDSP_control (@ref DPU_CFARCAProcDSP_Cmd_FovRangeCfg, @ref DPU_CFARCAProcDSP_Cmd_FovDopplerCfg). * * In this output list, side information of noise and SNR is also populated for each of the generated points. The * SNR is calculated using the noise and the detection matrix value corresponding to the detected range,doppler position. * * If both CFAR doopler and range domain processing are enabled, then noise is taken from range domain processing. * If only one processing domain is enabled, the noise is from the enabed processing domain. * * The CFAR processing and peak grouping can be enabled from dynamic configurations, such as: * - @ref DPU_CFARCAProcDSP_DynamicConfig::cfarCfgRange, * - @ref DPU_CFARCAProcDSP_DynamicConfig::cfarCfgDoppler. * * This can be done through: * - @ref DPU_CFARCAProcDSP_config * - @ref DPU_CFARCAProcDSP_control(@ref DPU_CFARCAProcDSP_Cmd_CfarRangeCfg, @ref DPU_CFARCAProcDSP_Cmd_CfarDopplerCfg). * * Additional parameters from the configuration also allow CFAR parameters * like threshold scale and window/guard lengths to be set. The CFAR detection processing in * the Doppler domain can be bypassed by setting doppler direction's detection threshold to zero. * * @subsection cfarcadsp_apis CFARCA DSP APIs * * - @ref DPU_CFARCAProcDSP_init DPU initialization function. * - @ref DPU_CFARCAProcDSP_config DPU configuration function. The configuration can only be done after * the DPU has been initialized using @ref DPU_CFARCAProcDSP_init. * * - @ref DPU_CFARCAProcDSP_process DPU processing function. This will execute the CFAR detection * algorithm using DSP. This processing can only be done after the DPU has been configured through * @ref DPU_CFARCAProcDSP_config. If the parameters used by this DPU do not * change from one frame to the next, @ref DPU_CFARCAProcDSP_config can be called only once for the first * frame and for every frame @ref DPU_CFARCAProcDSP_process can be executed without the need of reconfiguring the DPU. * * - @ref DPU_CFARCAProcDSP_control DPU control function. It processes the following messages received from DPC: * - @ref DPU_CFARCAProcDSP_Cmd_CfarRangeCfg, * - @ref DPU_CFARCAProcDSP_Cmd_CfarDopplerCfg, * - @ref DPU_CFARCAProcDSP_Cmd_FovRangeCfg, * - @ref DPU_CFARCAProcDSP_Cmd_FovDopplerCfg * * Full API details can be seen at @ref CFARCA_PROC_DPU_EXTERNAL */ /** @defgroup CFARCA_PROC_DPU_EXTERNAL cfarcaProc DPU External */ /** @defgroup DPU_CFARCAPROC_EXTERNAL_FUNCTION cfarcaProc DPU External Functions @ingroup CFARCA_PROC_DPU_EXTERNAL @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the cfarcaProc DPU */ /** @defgroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE cfarcaProc DPU External Data Structures @ingroup CFARCA_PROC_DPU_EXTERNAL @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DPU_CFARCAPROC_EXTERNAL_DEFINITIONS cfarcaProc DPU External Definitions @ingroup CFARCA_PROC_DPU_EXTERNAL @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DPU_CFARCAPROC_ERROR_CODE cfarcaProc DPU Error Codes @ingroup CFARCA_PROC_DPU_EXTERNAL @brief * The section has a list of all the error codes which are generated by the sampleProc DPU */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /*! @brief CFAR detection in range domain */ /*! * @brief CFAR detection in Doppler domain */ /*! @brief Peak grouping scheme of CFAR detected objects based on peaks of neighboring cells taken from detection matrix */ /*! @brief Peak grouping scheme of CFAR detected objects based only on peaks of neighboring cells that are already detected by CFAR */ /*! @brief Convert peak/noise value to log10 value in 0.1dB Since, val = log2(|.|)* 2^Qformat = log10(|.|) / log10(2) * 2^Qformat Equation: output = 1/0.1 * 10log10(|.|^2) = 10 * [ val * 20log10(2) / 2^Qformat ] = val * 6.0 / 2^Qformat * 10 */ /** * @brief * CFAR Configuration * * @details * The structure contains the cfar configuration used in data path */ typedef struct DPU_CFARCAProc_CfarCfg_t { /*! @brief CFAR threshold scale */ uint16_t thresholdScale; /*! @brief CFAR averagining mode 0-CFAR_CA, 1-CFAR_CAGO, 2-CFAR_CASO */ uint8_t averageMode; /*! @brief CFAR noise averaging one sided window length */ uint8_t winLen; /*! @brief CFAR one sided guard length*/ uint8_t guardLen; /*! @brief CFAR cumulative noise sum divisor CFAR_CA: noiseDivShift should account for both left and right noise window ex: noiseDivShift = ceil(log2(2 * winLen)) CFAR_CAGO/_CASO: noiseDivShift should account for only one sided noise window ex: noiseDivShift = ceil(log2(winLen)) */ uint8_t noiseDivShift; /*! @brief CFAR 0-cyclic mode disabled, 1-cyclic mode enabled */ uint8_t cyclicMode; /*! @brief Peak grouping scheme 1-based on neighboring peaks from detection matrix * 2-based on on neighboring CFAR detected peaks. * Scheme 2 is not supported on the HWA version (cfarcaprochwa.h) */ uint8_t peakGroupingScheme; /*! @brief Peak grouping, 0- disabled, 1-enabled */ uint8_t peakGroupingEn; } DPU_CFARCAProc_CfarCfg; /** * @brief * Data processing Unit statistics * * @details * The structure is used to hold the statistics of the DPU * * \ingroup INTERNAL_DATA_STRUCTURE */ typedef struct DPU_CFARCAProc_Stats_t { /*! @brief total number of calls of DPU processing */ uint32_t numProcess; /*! @brief total processing time during all chirps in a frame excluding EDMA waiting time*/ uint32_t processingTime; /*! @brief total wait time for EDMA data transfer during all chirps in a frame*/ uint32_t waitTime; }DPU_CFARCAProc_Stats; /*! * @brief Field of view indices * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_CFARCAProc_FovCfg_t { /*! @brief Minimum value in meters for range, or meters/sec for doppler */ float min; /*! @brief Maximum value in meters for range, or meters/sec for doppler */ float max; } DPU_CFARCAProc_FovCfg; /** @addtogroup DPU_CFARCAPROC_EXTERNAL_DEFINITIONS * @{ */ /*! @brief Number of HWA parameter sets */ /*! @brief Alignment for memory allocation purpose of detection matrix. * There is CPU access of detection matrix in the implementation. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. This is the maximum field size of the * @ref DPU_CFARCAProcHWA_CfarDetOutput structure. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of thi buffers * in the implementation. This is the maximum field size of the * @ref DPU_CFARCAProcHWA_CfarDetOutput structure. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /** @} */ /** @addtogroup DPU_CFARCAPROC_ERROR_CODE * Base error code for the cfarcaProc DPU is defined in the * \include ti/datapath/dpif/dp_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Invalid detection matrix format argument */ /** * @brief Error Code: Invalid number of param sets */ /** * @brief Error Code: Out of memory when allocating using MemoryP_osal */ /** * @brief Error Code: HWA input memory for detection matrix is not sufficient. */ /** * @brief Error Code: Memory not aligned for detection matrix (detMatrix.data) */ /** * @brief Error Code: Memory not aligned for @ref DPU_CFARCAProcHWA_HW_Resources::cfarRngDopSnrList */ /** * @brief Error Code: Memory not aligned for @ref DPU_CFARCAProcHWA_HW_Resources::hwaMemOutDoppler */ /** * @brief Error Code: Memory not aligned for @ref DPU_CFARCAProcHWA_HW_Resources::hwaMemOutRange */ /** * @brief Error Code: Insufficient memory allocated to @ref DPU_CFARCAProcHWA_HW_Resources::cfarDopplerDetOutBitMask. */ /** * @brief Error Code: Memory not aligned for @ref DPU_CFARCAProcHWA_HW_Resources::cfarDopplerDetOutBitMask */ /** * @brief Error Code: Internal error */ /** * @brief Error Code: Not implemented */ /** * @brief Error Code: Semaphore error */ /** @} */ /** * @brief * cfarcaProc control command * * @details * The enum defines the cfarcaProc supported run time command * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE */ typedef enum DPU_CFARCAProcHWA_Cmd_e { /*! @brief Command to update CFAR configuration in range domain */ DPU_CFARCAProcHWA_Cmd_CfarRangeCfg, /*! @brief Command to update CFAR configuration in Doppler domain */ DPU_CFARCAProcHWA_Cmd_CfarDopplerCfg, /*! @brief Command to update field of view in range domain, minimum and maximum range limits */ DPU_CFARCAProcHWA_Cmd_FovRangeCfg, /*! @brief Command to update field of view in Doppler domain, minimum and maximum Doppler limits */ DPU_CFARCAProcHWA_Cmd_FovDopplerCfg }DPU_CFARCAProcHWA_Cmd; /** * @brief * CFAR HWA configuration * * @details * The structure is used to hold the HWA configuration needed for CFAR * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_CFARCAProcHWA_HwaCfarConfig_t { /*! @brief HWA paramset Start index */ uint8_t paramSetStartIdx; /*! @brief number of HWA paramset */ uint8_t numParamSet; }DPU_CFARCAProcHWA_HwaCfarConfig; /*! * @brief Detected object parameters filled by HWA CFAR * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef volatile struct DPU_CFARCAProcHWA_CfarDetOutput_t { uint32_t noise; /*!< @brief Noise energy in CFAR cell */ uint32_t cellIdx : 12; /*!< @brief Sample index (i.e. cell under test index) */ uint32_t iterNum : 12; /*!< @brief Iteration number (i.e. REG_BCNT counter value) */ uint32_t reserved : 8; /*!< @brief Reserved */ } DPU_CFARCAProcHWA_CfarDetOutput; /** * @brief * CFARCAProcHWA DPU initial configuration parameters * * @details * The structure is used to hold the DPU initial configurations. * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_CFARCAProcHWA_InitParams_t { /*! @brief HWA Handle */ HWA_Handle hwaHandle; }DPU_CFARCAProcHWA_InitParams; /** * @brief * CFAR Hardware resources * * @details * CFAR Hardware resources * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * * */ typedef struct DPU_CFARCAProcHWA_Resources_t { /*! @brief EDMA Handle */ EDMA_Handle edmaHandle; /*! @brief EDMA configuration for CFAR data In */ DPEDMA_ChanCfg edmaHwaIn; /*! @brief EDMA configuration for EDMA In to trigger HWA*/ DPEDMA_ChanCfg edmaHwaInSignature; /*! @brief HWA Configuration */ DPU_CFARCAProcHWA_HwaCfarConfig hwaCfg; /*! @brief Pointer to range/Doppler log2 magnitude detection matrix. The data buffer * must be aligned to @ref DPU_CFARCAPROCHWA_DET_MATRIX_BYTE_ALIGNMENT */ DPIF_DetMatrix detMatrix; /*! @brief Pointer to CFAR output list, must be aligned to * @ref DPU_CFARCAPROCHWA_CFAR_DET_LIST_BYTE_ALIGNMENT */ DPIF_CFARDetList *cfarRngDopSnrList; /*! @brief Number of elements of type DPIF_cfarDetList of CFAR output list */ uint32_t cfarRngDopSnrListSize; /*! @brief HWA scratch memory to page-in detection matrix. Note two contiguous M * memory banks (of the 4 banks) could be allocated to this. */ uint16_t *hwaMemInp; /*! @brief Number of elements of type uint16_t of HWA memory to hold detection matrix * (associated with @ref hwaMemInp) */ uint32_t hwaMemInpSize; /*! @brief HWA scratch memory for producing intermediate cfar detection list in Doppler domain, * cannot be overlaid with other HWA scratch memory inputs specified in this * structure. Must be different memory bank than bank(s) of @ref hwaMemInpSize. * Must be aligned to @ref DPU_CFARCAPROCHWA_HWA_MEM_OUT_DOPPLER_BYTE_ALIGNMENT. * Note this need not be the start of a HWA memory bank but typically it is, * and is therefore naturally aligned to this alignment requirement. */ DPU_CFARCAProcHWA_CfarDetOutput *hwaMemOutDoppler; /*! @brief Number of elements of type @ref DPU_CFARCAProcHWA_CfarDetOutput of * HWA memory for cfar detection list in Doppler domain */ uint32_t hwaMemOutDopplerSize; /*! @brief HWA scratch memory for producing intermediate cfar detection list in Range domain, * cannot be overlaid with other HWA scratch memory inputs for this DPU. * Must be different memory bank than bank(s) of @ref hwaMemInp. * Must be aligned to @ref DPU_CFARCAPROCHWA_HWA_MEM_OUT_RANGE_BYTE_ALIGNMENT. * Note this need not be the start of a HWA memory bank but typically it is, * and is therefore naturally aligned to this alignment requirement */ DPU_CFARCAProcHWA_CfarDetOutput *hwaMemOutRange; /*! @brief Number of elements of type @ref DPU_CFARCAProcHWA_CfarDetOutput of * HWA memory for cfar detection list in Range domain */ uint32_t hwaMemOutRangeSize; /*! @brief Scratch memory for Doppler cfar detection bit mask. Must be aligned to * @ref DPU_CFARCAPROCHWA_DOPPLER_DET_OUT_BIT_MASK_BYTE_ALIGNMENT */ uint32_t *cfarDopplerDetOutBitMask; /*! @brief Number of elements of type uint32_t of scratch memory for bit mask * of Doppler cfar detections. * Must be >= (numRangeBins * numDoppplerBins) / 32 */ uint32_t cfarDopplerDetOutBitMaskSize; } DPU_CFARCAProcHWA_HW_Resources; /** * @brief * HWA CFAR dynamic configuration * * @details * The structure is used to hold the dynamic configuration used for CFAR * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * * */ typedef struct DPU_CFARCAProcHWA_DynamicConfig_t { /*! @brief CFAR configuration in range direction */ DPU_CFARCAProc_CfarCfg *cfarCfgRange; /*! @brief CFAR configuration in Doppler direction */ DPU_CFARCAProc_CfarCfg *cfarCfgDoppler; /*! @brief Field of view configuration in range domain */ DPU_CFARCAProc_FovCfg *fovRange; /*! @brief Field of view configuration in Doppler domain */ DPU_CFARCAProc_FovCfg *fovDoppler; } DPU_CFARCAProcHWA_DynamicConfig; /** * @brief * HWA CFAR static configuration * * @details * The structure is used to hold the static configuration used for CFAR. * The following condition must be satisfied: * * @verbatim numRangeBins * numDopplerBins * sizeof(uint16_t) <= 32 KB (two HWA memory banks) @endverbatim * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_CFARCAProcHWA_StaticConfig_t { /*! @brief Log2 of number of doppler bins */ uint8_t log2NumDopplerBins; /*! @brief Number of range bins */ uint16_t numRangeBins; /*! @brief Number of doppler bins */ uint16_t numDopplerBins; /*! @brief Range conversion factor for FFT range index to meters */ float rangeStep; /*! @brief Doppler conversion factor for Doppler FFT index to m/s */ float dopplerStep; } DPU_CFARCAProcHWA_StaticConfig; /** * @brief * HWA CFAR configuration * * @details * The structure is used to hold the HWA configuration used for CFAR * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * * */ typedef struct DPU_CFARCAProcHWA_Config_t { /*! @brief Hardware resources */ DPU_CFARCAProcHWA_HW_Resources res; /*! @brief Dynamic configuration */ DPU_CFARCAProcHWA_DynamicConfig dynCfg; /*! @brief Static configuration */ DPU_CFARCAProcHWA_StaticConfig staticCfg; }DPU_CFARCAProcHWA_Config; /** * @brief * Output parameters populated during Processing time * * @details * The structure is used to hold the output parameters * * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_CFARCAProcHWA_OutParams_t { /*! @brief CFARCAProc statistics */ DPU_CFARCAProc_Stats stats; /*! @brief Number of CFAR detected points*/ uint32_t numCfarDetectedPoints; }DPU_CFARCAProcHWA_OutParams; /** * @brief * CFARHwa DPU Handle * * * \ingroup DPU_CFARCAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef void* DPU_CFARCAProcHWA_Handle; /** * @b Description * @n * The function is CFARCAProcHWA DPU initialization function. It allocates memory to store * its internal data object and returns a handle if it executes successfully. * * @param[in] initCfg Pointer to initialization configuration * * @param[in] errCode Pointer to errCode generates from the API * * \ingroup DPU_CFARCAPROC_EXTERNAL_FUNCTION * * @retval * Success - valid CFARCAProcHWA handle * @retval * Error - NULL */ DPU_CFARCAProcHWA_Handle DPU_CFARCAProcHWA_init ( DPU_CFARCAProcHWA_InitParams *initCfg, int32_t* errCode ); /** * @b Description * @n * The function is CFARCAProcHWA DPU configuration function. It saves buffer pointer and configurations * including system resources and configures EDMA for runtime range processing. * * @pre DPU_CFARCAProcHWA_init() has been called * * @param[in] handle CFARCAProcHWA DPU handle * @param[in] cfarHwaCfg Pointer to CFARCAProcHWA configuration data structure * * \ingroup DPU_CFARCAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_CFARCAProcHWA_config ( DPU_CFARCAProcHWA_Handle handle, DPU_CFARCAProcHWA_Config *cfarHwaCfg ); /** * @b Description * @n * The function is CFARCAProcHWA DPU process function. It performs CFAR detection using HWA * * @pre DPU_CFARCAProcHWA_init() has been called * * @param[in] handle CFARCAProcHWA DPU handle * @param[in] outParams DPU output parameters * * \ingroup DPU_CFARCAPROC_EXTERNAL_FUNCTION * * @retval * Success = 0 * @retval * Error != 0 */ int32_t DPU_CFARCAProcHWA_process ( DPU_CFARCAProcHWA_Handle handle, DPU_CFARCAProcHWA_OutParams *outParams ); /** * @b Description * @n * The function is CFARCAProcHWA DPU control function. * * @pre DPU_CFARCAProcHWA_init() has been called * * @param[in] handle CFARCAProcHWA DPU handle * @param[in] cmd CFARCAProcHWA DPU control command * @param[in] arg CFARCAProcHWA DPU control argument pointer * @param[in] argSize CFARCAProcHWA DPU control argument size * * \ingroup DPU_CFARCAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_CFARCAProcHWA_control ( DPU_CFARCAProcHWA_Handle handle, DPU_CFARCAProcHWA_Cmd cmd, void *arg, uint32_t argSize ); /** * @b Description * @n * The function is CFARCAProcHWA DPU deinitialization function. It frees up the * resources allocated during initialization. * * @pre DPU_CFARCAProcHWA_init() has been called * * @param[in] handle CFARCAProcHWA DPU handle * * \ingroup DPU_CFARCAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_CFARCAProcHWA_deinit ( DPU_CFARCAProcHWA_Handle handle ); /** * @file aoaprochwa.h * * @brief * Implements Data path processing functionality. * * \par * NOTE: * (C) Copyright 2018-2019 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /* mmWave SDK Driver/Common Include Files */ /** * @file antenna_geometry.h * * @brief * * * \par * NOTE: * (C) Copyright 2019 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /* mmWave SDK drivers/common Include Files */ /** * @file antenna_geometry.h * * @brief * * * \par * NOTE: * (C) Copyright 2019 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @brief Antenna offset position in vertical and horizontal directions * */ typedef struct ANTDEF_AntOffset_t { /*! @brief antenna offset in horizontal direction (azimuth) expressed in Lambda/2 */ int16_t azimuthOffset; /*! @brief antenna offset in vertical direction (elevation) expressed in Lambda/2 */ int16_t elevationOffset; } ANTDEF_AntOffset; /** * @brief Antenna offset positions in vertical and horizontal directions * */ typedef struct ANTDEF_AntGeometry_t { /*! @brief Tx antenna positions */ ANTDEF_AntOffset txAnt[3U]; /*! @brief Rx antenna positions */ ANTDEF_AntOffset rxAnt[4U]; } ANTDEF_AntGeometry; extern float gAntennaSpacing; /* The value of Lambda/2 */ extern ANTDEF_AntGeometry gAntDef; /* Datapath files */ /** * @file aoaproc_common.h * * @brief * Implements Common definition across cfarcaProc DPU. * * \par * NOTE: * (C) Copyright 2018-2019 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage AOA DPU * * @section aoaprocdpu_intro_section AoA DPU * * Description * ---------------- * * This DPU implements angle of arrival (AoA) estimation. * It generates information about detected objects into two lists: 1) list with coordinates * defined by @ref DPIF_PointCloudCartesian_t and 2) side information list defined by @ref DPIF_PointCloudSideInfo_t. * The DPU receives 1D-FFT Radar Cube matrix calculated by range processing DPU * and the list of detected objects (@ref DPIF_CFARDetList_t) which is assumed to * be populated by previous CFAR algorithm processing.\n\n * * The AoA DPU is available in two distinct implementations: * * DPU Implementation | Runs on cores | Uses HWA * :---------------------|:----------------|:--------- * AoAProcHWA | R4F or DSP | Yes * AoAProcDSP | DSP | No *\n * * This document is organized as follows:\n * * Starting Section | Description * :--------------------------|:---------------- * @ref HWA-AOA-start | Start of the sections describing the AoAProcHWA DPU. It covers DPU implementation details. * @ref DSP-AOA-start | Start of the sections describing the AoAProcDSP DPU. It covers DPU implementation details. * @ref HWA-DSP-Common-start | Start of the sections that are common for AoAProcDSP and AoAProcHWA. It covers Doppler compensation, XYZ estimation/geometry and FoV configuration. * \n\n * * @anchor HWA-AOA-start * @section section_HWA-AOA HWA-AOA DPU (AoAProcHWA) * * @subsection section_AOA_Description Description * This DPU implements angle of arrival (AoA) estimation using HWA and CPU. * A high level data flow is illustrated in figure below. * * @image html hwa_aoa_top_level.png "HWA-AOA high level data flow" * * The following figure depicts detailed DPU implementation. DPU processes data * from the input CFAR detection list in a loop, two objects from the input list per loop. * The processing is done in ping/pong manner so that the HWA processing, the EDMA transfers and * the local core processing is done in parallel. Data processing is split in two paths, * ping and pong path, one detected object per path. * In each path processing is split between HWA and local core and it is divided in four stages: * 2D-FFT calculation by HWA, Doppler compensation by local core, 3D-FFT calculation by HWA and * XYZ estimation by local core. These four stages include: * 1. Calculation of the array of 2D-FFT Rx virtual antenna symbols as input to Azimuth FFT computation. * 1. Input EDMA pages from radarCube memory to HWA memory the 1D-FFT data corresponding to the range index * of the detected object. Note the input size limiting condition: * \f$N_{TxAnt}*N_{RxAnt}*N_{DopplerChirps}*sizeof(cmplx16ImRe\_t) \leq 16\;KB\f$ * 2. HWA calculates 2D FFT. Note the output size limiting condition: * \f$N_{TxAnt}*N_{RxAnt}*N_{DopplerBins}*sizeof(cmplx16ImRe\_t) \leq 16\;KB\f$ * 3. Output EDMA picks the data of the Doppler bin corresponding to the detected object's * Doppler index from the above FFT output and copies into core local memory. * 2. CPU performs * 1. Rx channel phase/gain compensation * 2. Doppler compensation * 3. Triggers EDMA to copy data back to HWA memory * 3. Azimuth FFT calculation: * 1. EDMA copies 2D-FFT antenna symbols from local memory to HWA memory, * 2. HWA calculates azimuth FFT (complex output) on azimuth Tx antennas, * 3. HWA calculates azimuth FFT (complex output) on elevation Tx antennas, * 4. HWA calculates Magnitude square of the FFT output of azimuth Tx antennas, * 5. EDMA copies magnitude squares from HWA memory to the local core memory * 4. Final azimuth and elevation estimation and x/y/z calculation performed by local core. * The calculated data of detected object is appended to the output lists. * * One HWA loop iteration processes 2 detected objects. (If the number of detected objects is odd, a * dummy one is appended at the end of the list of detected points.) * * @image html hwa_aoa.png "HWA-AOA implementation (for 3 Tx antennas)" * * The following figure shows the local core processing flow including two objects per loop. * The HWA runs in parallel, processing data within its loop in the following order: ping path 2D-FFT, pong path 2D-FFT, * ping path 3D-FFTs, pong path 3D-FFTs. This is illustrated in the timing diagram shown in figure below. * * @image html hwa_aoa_flow_chart.png "Local core processing flow" * * @image html hwa_aoa_timing_diagram.png "Timing diagram example: processing 5 detected objects" * * The scheme uses four EDMA physical channels, two EDMA channels to input data from the * local core memory to HWA, one channel per path, and two EDMA channels to output data from * HWA memory to the local core memory, one EDMA channel per path. The scheme also uses 12 EDMA param * sets programmed for data transfer and HWA triggering. HWA programming is done by up to 12 HWA Param sets. * The usage of EDMA and HWA param set is described in figure below. * Note that EDMA Input to HWA in the first stage is AB-Synchronized type transfer, * while all other EDMAs in the scheme are A-Synchronized type transfers. Since the * radar cube is aligned to 4 byte boundary, none of these transfers fall under the EDMA * 4K boundary problem. * @image html hwa_aoa_param_sets.png "EDMA and HWA param set usage" * * @subsection Azimuth_heat_map Azimuth heatmap preparation * In addition to AoA estimation, this DPU also generates data for computing * azimuth heat-map (e.g for visualization purposes), this data is 2D FFT of the * phase compensated Doppler bin 0 (static objects) output of each of the range bins. * The following figure depicts data generation for azimuth heat-map visualization. * Here, as well none of the trunfers fall under the EDMA 4K boundary problem. * * @image html hwa_aoa_azimuth_heatmap.png "Data processing for azimuth heat-map visualization" * * * @section api_section AoAProcHWA APIs * * - @ref DPU_AoAProcHWA_init - DPUs initialization function. * - @ref DPU_AoAProcHWA_config - DPUs configuration function. The configuration can only be done after * the DPU has been initialized using @ref DPU_AoAProcHWA_init. If the parameters used by this DPU do not * change from one frame to the next, this function can be called only once, for the first * frame, otherwise it has to be called before each @ref DPU_AoAProcHWA_process. * - @ref DPU_AoAProcHWA_process - DPUs processing function performs AoA estimation of * detected objects in the given frame. This processing can only be done after the * DPU has been configured. * - @ref DPU_AoAProcHWA_control - DPUs control function. It processes following messages from DPC: * - @ref DPU_AoAProcHWA_Cmd_FovAoACfg, * - @ref DPU_AoAProcHWA_Cmd_MultiObjBeamFormingCfg, * - @ref DPU_AoAProcHWA_Cmd_CompRxChannelBiasCfg, * - @ref DPU_AoAProcHWA_Cmd_PrepareRangeAzimuthHeatMap, * - @ref DPU_AoAProcHWA_Cmd_ExtMaxVelocityCfg * * Full API details can be seen at @ref DPU_AOAPROC_EXTERNAL * * * * *\n\n\n * @anchor DSP-AOA-start * @section section_DSP-AOA DSP-AOA DPU (AoAProcDSP) * * @subsection section_AOADSP_Description Description * This DPU implements angle of arrival (AoA) estimation using the DSP only(HWA is not used). * A high level data flow is illustrated in figure below. * * @image html dsp_aoa_top_level.png "DSP-AOA high level data flow" * * This DPU has the following restrictions regarding its input parameters:\n * The number of Doppler chirps (numDopplerChirps) must be a multiple of 4 and the number of Doppler bins (numDopplerBins) * must be a power of 2 greater or equal than numDopplerChirps. Also, due to restrictions on the FFT implementation by DSPLIB, * numDopplerBins must be at least 16. * * Parameter | Restriction * :------------------|:-------------- * numDopplerChirps | Must be a multiple of 4. * numDopplerBins | Must be at least 16. Must be a power of two, greater or equal than numDopplerChirps. * \n * * Below are details of the DPU implementation.\n\n * The AoA DSP DPU processes data from the input CFAR detection list in a loop. * For each object in the CFAR detection list the DPU performs the following operations: * * **Input data**\n * The CFAR detection list determines which range bin should be processed for the given object. * EDMA is used to move data from the radar cube into the DPU scratch buffers.\n * A ping/pong buffer scheme is used where in each iteration (ping/pong), data pertinent to one virtual antenna * (for the given range bin) is brought from the radar cube matrix for processing. * * **Static Clutter Removal**\n * When Static Clutter Removal is enabled, the mean value of the input samples to the * Doppler FFT is subtracted from the samples.\n\n * * **Windowing**\n * Before the 2D FFT operation, input samples are multiplied by a real symmetric window function. Window size and coefficients are * defined in @ref DPU_AoAProcDSP_HW_Resources. Window coefficients must be provided by application. The same window used for the * DSP Doppler DPU should be used here.\n * Note that the windowing function also executes IQ swap. Before windowing the samples are in the same format as in the radar cube, * which is cmplx16ImRe_t. After windowing the output is in cmplx32ReIm_t format.\n\n * * **2D FFT**\n * 2D FFT is computed, the output of the FFT has numDopplerBins samples of type cmplx32ReIm_t. * The CFAR detection list determines which Doppler bin should be stored, the other bins are discarded.\n\n * * **Repeat for all virtual antennas**\n * The above steps are repeated for all virtual antennas for the given range bin before moving to the next step.\n\n * * **Doppler Compensation**\n * Doppler correction is done on the symbols belonging to TX1 and TX2 antennas.\n\n * * **BPM decoding**\n * If BPM is enabled, BPM is decoded. \n\n * * **RX Channel Phase Compensation**\n * RX channel phase compensation is performed. \n\n * * **Angle of Arrival Estimation**\n * Azimuth FFT is computed, Elevation FFT is computed. These FFTs are input to @ref AoAProcDSP_angleEstimationAzimElev, * which calculates the x/y/z coordinates of the object. \n\n * * **Detailed block diagram for 3 TX 4 RX TDM-MIMO (no BPM)**\n * * The following figure depicts in detail the DPU implementation for the case of 3 TX and 4RX antennas (no BPM). * * @image html dsp_aoa_withMaxVelocity.png "DSP-AOA detailed implementation for 3 TX 4 RX TDM-MIMO (no BPM)" * * @subsection Azimuth_heat_mapDSP Azimuth heatmap preparation * In addition to AoA estimation, this DPU also generates data for computing * azimuth heat-map (e.g for visualization purposes), this data is 2D FFT of the * phase compensated Doppler bin 0 (static objects) output of each of the range bins. * * Below are details of the Azimuth heatmap preparation.\n\n * * **Input data**\n * EDMA is used to move data from the radar cube into the DPU scratch buffers.\n * A ping/pong buffer scheme is used where in each iteration (ping/pong), data pertinent to one virtual antenna * (for a given range bin) is brought from the radar cube matrix for processing. * * **Static Clutter Removal**\n * When Static Clutter Removal is enabled, the mean value of the input samples to the * Doppler FFT is subtracted from the samples.\n\n * * **BPM decoding**\n * If BPM is enabled, BPM is decoded. \n\n * * **Doppler bin zero**\n * Doppler bin zero is computed. Note that only bin zero is required.\n\n * * **RX Channel Phase Compensation**\n * RX channel phase compensation is performed. \n\n * * **Repeat for all Azimuth virtual antennas for all range bins**\n * The above steps are repeated for all Azimuth virtual antennas for all range bin. Note that data pertinent to the * elevation virtual antennas are not processed.\n\n * * The following figure depicts the heatmap computation for the case of 3TX and 4RX antennas. * * @image html dsp_aoa_azimuth.png "DSP-AOA Azimuth heatmap computation" * * @subsection aoa_bpmCfgNotes BPM Scheme * Similar to TDM-MIMO, in BPM scheme a frame consists of multiple blocks, each * block consisting of 2 chirp intervals. However, unlike in TDM-MIMO where only * one TX antenna active per chirp interval, two TX antennas are active in each * chirp interval. This DPU only supports a BPM scheme with two * TX antennas say A and B. In the even time slots (0, 2,...), both transmit antennas * should be configured to transmit with positive phase i.e * @verbatim (A,B) = (+,+) @endverbatim * In the odd time slots (1, 3,...), the transmit antennas should be configured to * transmit with phase\n * @verbatim (A,B) = (+,-) @endverbatim * The BPM scheme is shown in the figure below where TX0 is used as antenna A and TX1 as * antenna B. * * @image html bpm_antenna_cfg.png "BPM Scheme Antenna configuration" * * **BPM decoding**\n * Let S1 and S2 represent chirp signals from two TX antennas. In time slot zero * a combined signal Sa=S1+S2 is transmitted. Similarly in time slot one a * combined signal Sb=S1-S2 is transmitted. Using the corresponding received signals, * (S'a and S'b), at a specific received RX antenna, the components from the individual * transmitters are separated out using\n * @verbatim S'1=(S'a+S'b)/2 @endverbatim * and * @verbatim S'2=(S'a-S'b)/2 @endverbatim * With simultaneous transmission on both TX antennas the total transmitted power per * chirp interval is increased, and it can be shown that this translates to an SNR * improvement of 3dB.\n * * **Order of the TX antennas in the BPM scheme**\n * The BPM decoding will produce the virtual antenna * array in the order (A, B), not (B, A), which will be used for AoA processing. * Therefore, user must make sure that the (A, B) mapping to the physical transmit antennas * corresponds to the intended virtual antenna order. * For example, take the 6843 EVM antenna arrangement as shown in the figure below. * Note that the DPU indexes the TX antennas as (TX0, TX1, TX2) which corresponds * in the device to (TX1, TX2, TX3). \n * * @image html coordinate_geometry.png "6843 EVM antenna arrangement" * * Here two antennas TX1 and TX3 can create a virtual array of 8 antennas in the azimuth direction. * In order to ensure correct virtual antenna processing for AoA calculations, after BPM decoding, * the TX1 virtual antennas should precede the TX3 because the direction of spatial progression of * RX antennas matches the direction of spatial progression of TX antennas when TX1 is before TX3 * (post BPM decoding, the result should essentially be like TDM-MIMO). Therefore A=TX1 and B=TX3. * In other words, BPM must be configured to do\n * @verbatim (TX1,TX3) = (+,+) in even slots @endverbatim * and\n * @verbatim (TX1,TX3) = (+,-) in odd slots @endverbatim * The opposite arrangement i.e\n * @verbatim (TX3,TX1) = (+,+) in even slots @endverbatim * and\n * @verbatim (TX3,TX1) = (+,-) in odd slots @endverbatim * will not work.\n\n * * @subsection aoa_bpmNotes AoA DSP DPU changes when BPM is enabled * When BPM is enabled the following changes are done in the AoA DSP DPU processing:\n * For AoA estimation, BPM decoding is done after Doppler compensation. The following * figure depicts the DPU implementation when BPM is enabled. * * @image html dsp_aoa_BPM.png "BPM Scheme Antenna configuration" * * * @section api_sectionDSP AoAProcDSP APIs * * - @ref DPU_AoAProcDSP_init - DPUs initialization function. * - @ref DPU_AoAProcDSP_config - DPUs configuration function. The configuration can only be done after * the DPU has been initialized using @ref DPU_AoAProcDSP_init. * - @ref DPU_AoAProcDSP_process - DPUs processing function performs AoA estimation of * detected objects in the given frame. This processing can only be done after the * DPU has been configured. * - @ref DPU_AoAProcDSP_control - DPUs control function. It processes following messages from DPC: * - @ref DPU_AoAProcDSP_Cmd_FovAoACfg, * - @ref DPU_AoAProcDSP_Cmd_MultiObjBeamFormingCfg, * - @ref DPU_AoAProcDSP_Cmd_CompRxChannelBiasCfg, * - @ref DPU_AoAProcDSP_Cmd_PrepareRangeAzimuthHeatMap, * - @ref DPU_AoAProcDSP_Cmd_staticClutterCfg * - @ref DPU_AoAProcDSP_Cmd_ExtMaxVelocityCfg * * Full API details can be seen at @ref DPU_AOAPROC_EXTERNAL \n\n\n * * * * @anchor HWA-DSP-Common-start * @section common_HWA_DSP_DPUs Common Sections for AoAProcDSP and AoAProcHW * The following sections are common for AoAProcDSP and AoAProcHWA\n * * @subsection Sect_dopplerComp Doppler Compensation * Doppler compensation function (@ref aoaHwa_dopplerCompensation or @ref AoAProcDSP_dopplerCompensation) is done by CPU after * Rx channel phase/gain compensation. It performs compensation for the Doppler phase shift on * the symbols corresponding to the virtual Rx antennas. In case of 2Tx MIMO scheme, the second * set of Rx symbols is rotated by half of the estimated Doppler phase shift between subsequent * chirps corresponding to the same Tx antenna. In case of 3Tx MIMO elevation scheme, the second * set of Rx symbols is rotated by 1/3 of the estimated Doppler phase shift, while the third set * of Rx symbols is rotated by 2/3 of the estimated Doppler phase shift. Refer to the pictures below. * @anchor Figure_doppler * @image html angle_doppler_compensation.png "Figure_doppler: Doppler Compensation" * * @subsection Extended_max_velocity Extended maximum velocity feature * In TDM-MIMO scheme the angle resolution increases with the number of Tx antennas, as the length of * array of Rx virtual antennas increases, however the maximum unambiguous radial velocity Vmax decreases * proportionally to the number of Tx antennas, as illustrated in Figure below. * * @image html max_velocity_comparison.png "Maximum unambiguous velocities in TDM-MIMO for different number of Tx antennas, assuming the same profile configuration in each scheme" * * For the target velocities beyond Vmax, the Doppler measurements are aliased. This is illustrated in Figure below * for 3TxTDM-MIMO where several actual velocities can fold into the same aliased velocity. * * @image html max_velocity_aliasing.png "Examples of different actual velocities beyond Vmax folding into same aliased velocity" * * Maximum velocity extension method is based on the maximum peak in angular FFTs. It consists of the following steps: * * 1. Calculate phase change \f$\Delta\varphi_{dop}=2\pi\frac{l_d}{N_{DopFFT}}\f$ where \f$l_d\f$ is the Doppler detection index. * 2. Test \f$N_{Tx}\f$ hypotheses \f$H_n\f$, \f$ n=0,...N_{Tx}-1\f$. For each hypothesis calculate phase change \f$\Delta\varphi_n\f$. * - for even \f$N_{Tx}\f$ * \f[ * \Delta\varphi_n= \left\{ \begin{array}{lr} \Delta\varphi_{dop}+2\pi(n-\frac{N_{Tx}}{2}) & : \Delta\varphi_{dop} \ge 0\\ \Delta\varphi_{dop}+2\pi(n-\frac{N_{Tx}}{2}+1) & : \Delta\varphi_{dop} < 0 \end{array}\right. * \f] * - for odd \f$N_{Tx}\f$ * \f[ * \Delta\varphi_n= \Delta\varphi_{dop}+2\pi(n- \lfloor\frac{N_{Tx}}{2}\rfloor) * \f] * Figure below illustrates in 3Tx TDM-MIMO 3 hypothetical phase changes \f$\Delta\varphi_n\f$ based on measured \f$\Delta\varphi_{dop}\f$. * @image html max_velocity_unwrpped_phases.png "Doppler phase offsets under different Hypothesis based on measured phase offset" * 3. Apply Doppler correction on the \f$i^{th}\f$ set of virtual Rx antennas: * \f[ * \Delta\varphi_i= i \cdot \frac{\Delta\varphi_n}{N_{Tx}}, \;\; i=0,1,...,N_{Tx} - 1 * \f] * 4. Compute azimuth spectrum \f$S_n\f$ for each \f$H_n\f$ and find the peaks \f$P_n = max(Sn)\f$. * 5. Find m = argmax \f$P_n\f$, * 6. Complete the azimuth estimation using the data from \f$S_m\f$ * * Extended maximum velocity feature can be enabled/disabled by using the cli command: extendedMaxVelocity. * When the feature is enabled, local core performs Doppler compensation for all possible hypotheses, * 2 hypotheses for 2Tx, and 3 hypotheses for 3Tx antenna TDM MIMO scheme. HWA calculates FFTs for all hypotheses, and * in the local core one hypothesis is picked based on the maximum peak in the magnitude square outputs. * * @subsubsection LimitationExtMaxVel Limitation of extended maximum velocity algorithm * The algorithm works well when the single target occurs in range/Doppler bin. * However it can fail with multiple targets in the same range/Doppler bin. * It also fails with multiple targets at the same range and different velocities * wrapped to the same Doppler bin. * * @subsection dataXYZ Data Path - Direction of Arrival Estimation (x,y,z) * This processing is done on CPU in the function @ref AoAProcHWA_angleEstimationAzimElev or @ref AoAProcDSP_angleEstimationAzimElev. * The actual computation per detected object is performed by @ref AoAProcHWA_XYZestimation or @ref AoAProcDSP_XYZestimation. * \anchor Figure_geometry * @image html coordinate_geometry.png "Figure A: Coordinate Geometry" * \n * \anchor Figure_wz * @image html coordinate_geometry_wz.png "Figure wz" * \n * \anchor Figures_wx * @image html coordinate_geometry_wx.png "Figures wx" * \ref Figure_geometry shows orientation of x,y,z axes with respect to the sensor/antenna positions. The objective is to estimate * the (x,y,z) coordinates of each detected object. * \f$w_x\f$ is the phase difference between consecutive receive azimuth antennas of the 2D FFT and \f$w_z\f$ is the phase difference between * azimuth and corresponding elevation antenna above the azimuth antenna. The phases for each antenna are shown in the \ref Figure_doppler. * \ref Figure_wz shows that the distance AB which represents the relative distance between wavefronts intersecting consecutive elevation * antennas is \f$AB = \frac{\lambda}{2} \sin (\phi)\f$. Therefore \f$W_z = \frac{2\pi}{\lambda} \cdot AB\f$, therefore \f$W_z = \pi \sin (\phi)\f$. * Note that the phase of the lower antenna is advanced compared to the upper * antenna which is why picture X shows -Wz term in the upper antenna. * \ref Figures_wx show that distance CD which represents the relative distance between wavefronts intersecting consecutive azimuth * antennas is \f$CD = \frac{\lambda}{2} \sin (\theta) \cos (\phi)\f$ Therefore \f$w_x = \frac{2\pi}{\lambda} \cdot CD\f$, * therefore \f$w_x = \pi \sin (\theta) \cos (\phi)\f$. * For a single obstacle, the signal at the 8 azimuth antennas will be (\f$A_1\f$ and \f$\psi\f$ are the arbitrary starting * amplitude/phase at the first antenna): * \f[ * A_1 e^{j\psi} [ 1 \; e^{jw_x} \; e^{j2w_x} \; e^{j3w_x} \; e^{j4w_x} \; e^{j5w_x} \; e^{j6w_x} \; e^{j7w_x} ] * \f] * * An FFT of the above signal will yield a peak \f$P_1\f$ at \f$w_x\f$, with the phase of this peak being \f$\psi\f$ i.e * \f[ * P_1 = A_1 e^{j\psi} * \f] * If \f$k_{MAX}\f$ is the index of the peak in log magnitude FFT represented as * signed index in range \f$[-\frac{N}{2}, \frac{N}{2}-1]\f$, then \f$ w_x \f$ will be * \f[ * w_x = \frac{2\pi}{N}k_{MAX} * \f] * * The signal at the 4 elevation antennas will be: * \f[ * A_2 e^{j(\psi + 2 w_x - w_z)} [ 1 \; e^{jw_x} \; e^{j2w_x} \; e^{j3w_x}] * \f] * * An FFT of the above signal will yield a peak \f$P_2\f$ at \f$w_x\f$, with the phase of this peak being \f$\psi + 2w_x - w_z\f$. * \f[ * P_2 = A_2 e^{j(\psi+ 2 w_x - w_z)} * \f] * * From above, * \f[ * P_1 \cdot P_2^* = A_1 \cdot A_2 e^{j(\psi - (\psi+ 2 w_x - w_z))} * \f] * * Therefore, * \f[ * w_z=\angle (P_1 \cdot P_2^* \cdot e^{j2w_x}) * \f] * * * Calculate range (in meters) as: * \f[ * R=k_r\frac{c \cdot F_{SAMP}}{2 \cdot S \cdot N_{FFT}} * \f] * where, \f$c\f$ is the speed of light (m/sec), \f$k_r\f$ is range index, \f$F_{SAMP}\f$ is the sampling frequency (Hz), * \f$S\f$ is chirp slope (Hz/sec), \f$N_{FFT}\f$ is 1D FFT size. * Based on above calculations of \f$R\f$, \f$w_x\f$ and \f$w_z\f$, the \f$(x,y,z)\f$ position of the object * can be calculated as seen in the \ref Figure_geometry, * \f[ * x = R\cos(\phi)\sin(\theta) = R\frac{w_x}{\pi}, \;\;\;\;\; z = R\sin(\phi) = R\frac{w_z}{\pi},\;\;\;\;\; y = \sqrt{R^2-x^2-z^2} * \f] * The computed \f$(x,y,z)\f$ along with the Doppler value for each detected object are populated in the output * list, structured as @ref DPIF_PointCloudCartesian_t. * * If the multi object beam forming feature is enabled, (it can be dynamically controlled from CLI), the algorithm * searches for the second peak in the azimuth FFT output and compares its height relative to the first peak height, * and if detected, it creates new object in the output list with the same Doppler * value and calculated (x,y,z) coordinates. * * @subsection fovSubSection Elimination of detected objects based on FoV limits * * The AoA DPU filters out detected objects whose azimuth, \f$\theta\f$, and elevation, \f$\phi\f$, angles * are not within configured FoV limits. The DPU receives the following FoV parameters: * * \f$\phi_{min},\;\phi_{max},\f$ - elevation angle FoV limits * * \f$\theta_{min},\;\theta_{max}\f$ - azimuth angle FoV limits * * The DPU computes \f$W_z\f$ and \f$W_x\f$ directly from azimuth FFT output data, where * * \f$W_z = w_z/\pi\f$ * * \f$W_x = w_x/\pi\f$ * * From equations in previous section the following holds * * \f$W_z = \sin(\phi)\f$ * * \f$W_x = \cos(\phi) \sin(\theta)\f$ * * Because sine is a monotonic increasing function in the maximum possible range * of -90 deg, 90 deg, the elevation angle \f$\phi\f$ FoV limits can be checked on \f$W_z\f$ * as follows * * \f[ * \sin(\phi_{min}) \leq W_z \leq \sin(\phi_{max}) * \f] * * Since \f$W_x\f$ is not monotonic in \f$\phi\f$ but monotonic on \f$\theta\f$, * the azimuth angle \f$\theta\f$ limits can be checked by checking \f$W_x\f$ after computing * the \f$\cos(\phi)\f$ on the measured \f$\phi\f$. * * \f[ * \cos(\phi)\sin(\theta_{min}) \leq W_x \leq \cos(\phi) \sin(\theta_{max}) * \f] * * where \f$\cos(\phi) = \sqrt{1 - \sin(\phi)^2} = \sqrt{1 - W_z^2}\f$. * Note that the terms \f$\sin(\phi_{min})\f$, \f$\sin(\phi_{max})\f$, * \f$\sin(\theta_{min})\f$ and \f$\sin(\theta_{max})\f$ are precomputed during configuration time * and stored in the dpu's instance (@ref DPU_AoAProc_fovAoaLocalCfg_t) to be used * in the real-time limit checks above. * The brute-force method of checking limits on \f$\phi\f$ and \f$\theta\f$ directly * requires computing these, which involves two sin inverses, one cosine and one * division which are computationally more expensive than the above method. * * */ /** @defgroup DPU_AOAPROC_INTERNAL aoaProc DPU Internal * */ /** @defgroup DPU_AOAPROC_INTERNAL_FUNCTION aoaProc DPU Internal Functions @ingroup DPU_AOAPROC_INTERNAL @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup DPU_AOAPROC_INTERNAL_DATA_STRUCTURE aoaProc DPU Internal Data Structures @ingroup DPU_AOAPROC_INTERNAL @brief * The section has a list of all internal data structures which are used internally * by the aoaProc DPU module. */ /** @defgroup DPU_AOAPROC_INTERNAL_DEFINITION aoaProc DPU Internal Definitions @ingroup DPU_AOAPROC_INTERNAL @brief * The section has a list of all internal definitions which are used internally * by the aoaProc DPU. */ /** @defgroup DPU_AOAPROC_EXTERNAL aoaProc DPU External */ /** @defgroup DPU_AOAPROC_EXTERNAL_FUNCTION aoaProc DPU External Functions @ingroup DPU_AOAPROC_EXTERNAL @brief * The section has a list of all the exported API which the user need to * invoke in order to use the aoaProc DPU */ /** @defgroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE aoaProc DPU External Data Structures @ingroup DPU_AOAPROC_EXTERNAL @brief * The section has a list of all the data structures which are exposed to the user */ /** @defgroup DPU_AOAPROC_EXTERNAL_DEFINITIONS aoaProc DPU External Definitions @ingroup DPU_AOAPROC_EXTERNAL @brief * The section has a list of all the definitions which are exposed to the user */ /** @defgroup DPU_AOAPROC_ERROR_CODE aoaProc DPU Error Codes @ingroup DPU_AOAPROC_EXTERNAL @brief * The section has a list of all the error codes which are generated by the sampleProc DPU */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /*! @brief Converts Doppler index to signed variable. Value greater than or equal * half the Doppler FFT size will become negative. */ /** * @brief * Field of view - AoA Configuration * * @details * The structure contains the field of view - AoA configuration used in data path * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProc_FovAoaCfg_t { /*! @brief minimum azimuth angle (in degrees) exported to Host*/ float minAzimuthDeg; /*! @brief maximum azimuth angle (in degrees) exported to Host*/ float maxAzimuthDeg; /*! @brief minimum elevation angle (in degrees) exported to Host*/ float minElevationDeg; /*! @brief maximum elevation angle (in degrees) exported to Host*/ float maxElevationDeg; } DPU_AoAProc_FovAoaCfg; /** * @brief * Multi object beam forming Configuration * * @details * The structure contains the Peak grouping configuration used in data path * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProc_MultiObjBeamFormingCfg_t { /*! @brief enabled flag: 1-enabled 0-disabled */ uint8_t enabled; /*! @brief second peak detection threshold */ float multiPeakThrsScal; } DPU_AoAProc_MultiObjBeamFormingCfg; /** * @brief Range Bias and rx channel gain/phase compensation configuration. * * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProc_compRxChannelBiasCfg_t { /*! @brief Compensation for range estimation bias in meters */ float rangeBias; /*! @brief Compensation for Rx channel phase bias in Q15 format. * The order here is like x[tx][rx] where rx order is 0,1,....SYS_COMMON_NUM_RX_CHANNEL-1 * and tx order is 0, 1,...,SYS_COMMON_NUM_TX_ANTENNAS-1 */ cmplx16ImRe_t rxChPhaseComp[3U * 4U]; } DPU_AoAProc_compRxChannelBiasCfg; /** * @brief * Extended maximum velocity configuration * * @details * Extended maximum velocity configuration * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProc_ExtendedMaxVelocityCfg_t { /*! @brief enabled flag: 1-enabled 0-disabled */ uint8_t enabled; } DPU_AoAProc_ExtendedMaxVelocityCfg; /** * @brief * Static clutter removal configuration * * @details * The structure contains the configuration for static clutter removal. * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_AoAProc_StaticClutterRemovalCfg_t { /*! @brief Flag that indicates if static clutter removal is enabled.*/ _Bool isEnabled; }DPU_AoAProc_StaticClutterRemovalCfg; /** * @brief * AoAProc dynamic configuration * * @details * The structure is used to hold the dynamic configuration used for AoA * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProc_DynamicConfig_t { /** @brief Multiobject beam forming configuration */ DPU_AoAProc_MultiObjBeamFormingCfg *multiObjBeamFormingCfg; /** @brief Flag indicates to prepare data for azimuth heat-map */ _Bool prepareRangeAzimuthHeatMap; /** @brief Pointer to Rx channel compensation configuration */ DPU_AoAProc_compRxChannelBiasCfg *compRxChanCfg; /** @brief Field of view configuration for angle of arrival */ DPU_AoAProc_FovAoaCfg *fovAoaCfg; /** @brief Extended maximum velocity configuration */ DPU_AoAProc_ExtendedMaxVelocityCfg *extMaxVelCfg; /*! @brief Static clutter removal configuration. Valid only for DSP version of the AoA DPU.*/ DPU_AoAProc_StaticClutterRemovalCfg staticClutterCfg; } DPU_AoAProc_DynamicConfig; /** * @brief * Data processing Unit statistics * * @details * The structure is used to hold the statistics of the DPU * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_AoAProc_Stats_t { /** @brief total processing time during all chirps in a frame excluding EDMA waiting time*/ uint32_t processingTime; /** @brief total wait time for EDMA data transfer during all chirps in a frame*/ uint32_t waitTime; } DPU_AoAProc_Stats; /** @addtogroup DPU_AOAPROC_EXTERNAL_DEFINITIONS * @{ */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Log2 of the size of azimuth FFT */ /*! @brief Size of azimuth FFT */ /*! @brief Alignment for memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Radar cube alignment must be the same as the size of the complex sample Even though HWA processing does not need this alignment, the 4 KB boundary problem of the EDMA requires that we make sure the source address is aligned to the EDMA's Acount (= sample size = 4 bytes which divides 4 KB) */ /*! @brief Alignment for local scratch memory allocation purpose. There is CPU access of this buffer * in the implementation. */ /*! @brief Number of local scratch buffers */ /*! @brief Local scratch buffer size. The size maximum of the two buffers that are overlayed: * Buffer 1 (azimElevLocalBuf and azimElevLocalHypothesesBuf) size: * (NTxAnt + 1) * NTxAnt * NRxAnt * sizeof(uint32_t) * Buffer 2 (azimuthFftOutMagBuf) size: * NTxAnt * @ref DPU_AOAPROCHWA_NUM_ANGLE_BINS * sizeof(uint16_t) * The size of the second buffer is greater than the first one as long as * (NTxAnt + 1) * NRxAnt < 32, which is true, therefore the size of the * second buffer is defined below. Note: For nTx*nTx*nRx*sizeof(uint32_t) == 64, this is the case where only combination that is valid is nTx = 2, nRx = 4, we do the EDMA 4K speculative correction for some devices which advances the azimElevLocalHypothesesBuf by a maximum of 64. In this case, buffer1 size = 32 + (64 + 64) = 160 buffer2 size = 256, so condition above is still true */ /** @} */ /** @addtogroup DPU_AOAPROC_ERROR_CODE * Base error code for the aoaProc DPU is defined in the * \include ti/datapath/dpif/dp_error.h @{ */ /** * @brief Error Code: Invalid argument (general e.g NULL pointers) */ /** * @brief Error Code: Invalid argument - radar cube format */ /** * @brief Error Code: Out of memory when allocating using MemoryP_osal */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::cfarRngDopSnrList */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::detObjOut */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::detObjOutSideInfo */ /** * @brief Error Code: Insufficient memory allocated for azimuth static heat map */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::azimuthStaticHeatMap */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::detObjElevationAngle */ /** * @brief Error Code: azimuth heat-map flag enabled and single virtual antenna not valid combination */ /** * @brief Error Code: Configure parameters exceed HWA memory bank size */ /** * @brief Error Code: Detected object list size is not even number */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::localScratchBuffer */ /** * @brief Error Code: Insufficient memory allocated for @ref DPU_AoAProcHWA_HW_Resources::localScratchBuffer */ /** * @brief Error Code: Memory not aligned for @ref DPU_AoAProcHWA_HW_Resources::radarCube */ /** * @brief Error Code: Internal error */ /** * @brief Error Code: Not implemented */ /** * @brief Error Code: Semaphore error */ /** @} */ /** * @brief * AoAProcHWA DPU control command * * @details * The enum defines the AoAProcHWA supported run time command * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef enum DPU_AoAProcHWA_Cmd_e { /*! @brief Command to update field of view configuration, azimuth and elevation selected range*/ DPU_AoAProcHWA_Cmd_FovAoACfg, /*! @brief Command to update multiobject beam forming configuration */ DPU_AoAProcHWA_Cmd_MultiObjBeamFormingCfg, /*! @brief Command to update rx channel phase compensation */ DPU_AoAProcHWA_Cmd_CompRxChannelBiasCfg, /*! @brief Command to update Azimuth heat-map configuration */ DPU_AoAProcHWA_Cmd_PrepareRangeAzimuthHeatMap, /*! @brief Command to update field of extended maximum velocity */ DPU_AoAProcHWA_Cmd_ExtMaxVelocityCfg } DPU_AoAProcHWA_Cmd; /** * @brief * AoAProcHWA DPU configuration * * @details * The structure is used to hold the HWA configuration needed for AOA * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_AoAProcHWA_hwaAoAConfig_t { /** @brief HWA paramset Start index */ uint8_t paramSetStartIdx; /** @brief number of HWA paramsets */ uint8_t numParamSet; /*! @brief Flag to indicate if HWA windowing is symmetric see HWA_WINDOW_SYMM definitions in HWA driver's doxygen documentation */ uint8_t winSym; /*! @brief Doppler FFT window size in bytes. This is the number of coefficients to be programmed in the HWA for the windowing functionality. The size is a function of @ref DPU_AoAProcHWA_StaticConfig::numDopplerChirps as follows:\n If non-symmetric window is selected: windowSize = numDopplerChirps * sizeof(int32_t) \n If symmetric window is selected and numDopplerChirps is even: windowSize = numDopplerChirps * sizeof(int32_t) / 2 \n If symmetric window is selected and numDopplerChirps is odd: windowSize = (numDopplerChirps + 1) * sizeof(int32_t) / 2 */ uint32_t windowSize; /*! @brief Pointer to doppler FFT window coefficients. */ int32_t *window; /*! @brief Offset in HWA window RAM for singleBin doppler FFT * in number of samples */ uint32_t winRamOffset; }DPU_AoAProcHWA_hwaAoAConfig; /** * @brief * AoAProcHWA DPU initial configuration parameters * * @details * The structure is used to hold the DPU initial configurations parameters. * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_AoAProcHWA_InitParams_t { /*! @brief HWA Handle */ HWA_Handle hwaHandle; }DPU_AoAProcHWA_InitParams; /** * @brief * AoAProcHWA DPU EDMA configuration * * @details * EDMA configuration for input/output to HWA for calculation of zero-Doppler 2D-FFT used for azimuth heatmap * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProcHWA_EdmaHwaInOut_t { /*! @brief EDMA configuration for AOA data In */ DPEDMA_ChanCfg in; /*! @brief EDMA configuration for AOA data In signature */ DPEDMA_ChanCfg inSignature; /*! @brief EDMA configuration for AOA data Out */ DPEDMA_ChanCfg out; } DPU_AoAProcHWA_EdmaHwaInOut; /** * @brief * AoAProcHWA DPU EDMA channel configuration * * @details * DMA physical channel configuration * * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProcHWA_ChanCfg_t { /*! @brief EDMA channel id */ uint8_t channel; /*! @brief EDMA event Queue used for the transfer */ uint8_t eventQueue; } DPU_AoAProcHWA_ChanCfg; /** * @brief * AoAProcHWA DPU EDMA configuration for HWA input/output * * @details * EDMA Param sets used for data transfer to and from HWA * * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProcHWA_EdmaHwaInOutParamId_t { /*! @brief EDMA configuration for AOA data In */ uint16_t paramIn; /*! @brief EDMA configuration for AOA data In signaure */ uint16_t paramInSignature; /*! @brief EDMA configuration for AOA data Out */ uint16_t paramOut; /*! @brief EDMA to read CFAR peak counts. This is for future use. */ uint16_t paramPeakCnt; /*! @brief EDMA to trigger HWA to continue running. This is for future use. */ uint16_t paramHwaContinue; } DPU_AoAProcHWA_EdmaHwaInOutParamId; /** * @brief * AoAProcHWA DPU EDMA configuration * * @details * EDMA configuration for input/output to HWA for 2D-FFT and 3D-FFT stages * * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProcHWA_EdmaHwaDataInOut_t { /*! @brief EDMA physical channel In */ DPU_AoAProcHWA_ChanCfg chIn; /*! @brief EDMA physical channel Out */ DPU_AoAProcHWA_ChanCfg chOut; /*! @brief EDMA configuration in/out per stage: 0: 2D-FFT and 1: 3D-FFT */ DPU_AoAProcHWA_EdmaHwaInOutParamId stage[2]; /*! @brief EDMA event Queue used for the transfer */ uint8_t eventQueue; } DPU_AoAProcHWA_EdmaHwaDataInOut; /** * @brief * AoAProcHWA DPU Hardware resources * * @details * AoAProcHWA DPU Hardware resources * * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef struct DPU_AoAProcHWA_Resources_t { /*! @brief EDMA Handle */ EDMA_Handle edmaHandle; /*! @brief EDMA configuration for azimuth heatmap computation (zero-Doppler 2D-FFT calculation for all range bins), 0-ping, 1-pong */ DPU_AoAProcHWA_EdmaHwaInOut edmaHwa[2]; /*! @brief EDMA configuration, for point-cloud computation including 2D-FFT and 3D-FFT, 0-ping, 1-pong*/ DPU_AoAProcHWA_EdmaHwaDataInOut edmaHwaExt[2]; /*! @brief HWA Configuration */ DPU_AoAProcHWA_hwaAoAConfig hwaCfg; /*! @brief Radar Cube structure */ DPIF_RadarCube radarCube; /*! @brief List of CFAR detected objects of @ref cfarRngDopSnrListSize elements, * must be aligned to @ref DPU_AOAPROCHWA_CFAR_DET_LIST_BYTE_ALIGNMENT */ DPIF_CFARDetList *cfarRngDopSnrList; /*! @brief CFAR detected objects list size */ uint16_t cfarRngDopSnrListSize; /*! @brief Detected objects output list sized to @ref detObjOutMaxSize elements, * must be aligned to @ref DPU_AOAPROCHWA_POINT_CLOUD_CARTESIAN_BYTE_ALIGNMENT */ DPIF_PointCloudCartesian *detObjOut; /*! @brief Detected objects side information (snr + noise) output list, * sized to @ref detObjOutMaxSize elements, * must be aligned to @ref DPU_AOAPROCHWA_POINT_CLOUD_SIDE_INFO_BYTE_ALIGNMENT */ DPIF_PointCloudSideInfo *detObjOutSideInfo; /*! @brief This field dimensions several other fields in this structure as * referred in their descriptions. It is determined by the dpc/application based * on balancing between maximum number of objects expected to be * detected in the scene (this can depend on configuration like cfar thresholds, * static clutter removal etc) and memory and MIPS limitations. */ uint32_t detObjOutMaxSize; /*! @brief Pointer to range-azimuth static heat map, this is a 2D FFT * array in range direction (x[numRangeBins][numVirtualAntAzim]), * at doppler index 0, sized to @ref azimuthStaticHeatMapSize elements of * type cplx16ImRe_t. * Alignment should be @ref DPU_AOAPROCHWA_AZIMUTH_STATIC_HEAT_MAP_BYTE_ALIGNMENT */ cmplx16ImRe_t *azimuthStaticHeatMap; /*! @brief Number of elements of azimuthStaticHeatMap, this should be * numVirtualAntAzim * numRangeBins */ uint32_t azimuthStaticHeatMapSize; /*! @brief Detected objects azimuth index for debugging, * sized to @ref detObjOutMaxSize elements */ uint8_t *detObj2dAzimIdx; /*! @brief Detected object elevation angle for debugging, * sized to @ref detObjOutMaxSize elements, must be aligned to * @ref DPU_AOAPROCHWA_DET_OBJ_ELEVATION_ANGLE_BYTE_ALIGNMENT */ float *detObjElevationAngle; /*! @brief Local scratch buffer */ uint8_t *localScratchBuffer[(2)]; /*! @brief Local scratch buffer size = numTxAntennas * DPU_AOAPROCHWA_NUM_ANGLE_BINS * sizeof(uint16_t). A convenient macro @ref DPU_AOAPROCHWA_NUM_LOCAL_SCRATCH_BUFFER_SIZE_BYTES has been provided for calculating this size */ uint32_t localScratchBufferSizeBytes; } DPU_AoAProcHWA_HW_Resources; /** * @brief * AoAProcHWA DPU static configuration parameters * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * * @details * The following conditions must be satisfied: * @verbatim numTxAntennas * numRxAntennas * numDopplerChirps * sizeof(cmplx16ImRe_t) <= 16 KB (one HWA memory bank) numTxAntennas * numRxAntennas * numDopplerBins * sizeof(cmplx16ImRe_t) <= 32 KB (two HWA memory banks) @endverbatim * */ typedef struct DPU_AoAProcHWA_StaticConfig_t { /*! @brief Number of transmit antennas */ uint8_t numTxAntennas; /*! @brief Number of receive antennas */ uint8_t numRxAntennas; /*! @brief Number of virtual azimuth antennas */ uint8_t numVirtualAntAzim; /*! @brief Number of virtual elevation antennas */ uint8_t numVirtualAntElev; /*! @brief Number of range bins */ uint16_t numRangeBins; /*! @brief Number of chirps for Doppler computation purposes. For example, in TDM/BPM-MIMO scheme, this is the physical chirps in a frame per transmit antenna i.e numDopplerChirps = numChirpsPerFrame / numTxAntennas */ uint16_t numDopplerChirps; /*! @brief Number of doppler bins */ uint16_t numDopplerBins; /*! @brief Range conversion factor for range FFT index to meters */ float rangeStep; /*! @brief Doppler conversion factor for Doppler FFT index to m/s */ float dopplerStep; /*! @brief Pointer to antenna geometry definition. This is for future use */ ANTDEF_AntGeometry *antDef; /*! @brief Wavelength over antenna spacing factor */ float lambdaOverDist; } DPU_AoAProcHWA_StaticConfig; /** * @brief * AoAProcHWA DPU configuration * * @details * The structure is used to hold the AoAProcHWA configuration * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_AoAProcHWA_Config_t { /*! @brief Data path common parameters */ DPU_AoAProcHWA_StaticConfig staticCfg; /*! @brief Hardware resources */ DPU_AoAProcHWA_HW_Resources res; /*! @brief Dynamic configuration */ DPU_AoAProc_DynamicConfig dynCfg; }DPU_AoAProcHWA_Config; /** * @brief * Output parameters populated during Processing time * * @details * The structure is used to hold the output parameters * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_AoAProcHWA_OutParams_t { /*! @brief AoAProcHWA stats */ DPU_AoAProc_Stats stats; /*! @brief Number of AoA DPU detected points*/ uint32_t numAoADetectedPoints; }DPU_AoAProcHWA_OutParams; /** * @brief * AoAProcHWA DPU Handle * * * \ingroup DPU_AOAPROC_EXTERNAL_DATA_STRUCTURE * */ typedef void* DPU_AoAProcHWA_Handle ; /** * @b Description * @n * The function returns number of used HWA Param sets * * @param[in] numTxAnt Number of Tx antennas in TDM MIMO scheme * * @param[in] numRxVirtAntElevation Number of Rx vitual elevation antennas * * \ingroup DPU_AOAPROC_EXTERNAL_FUNCTION * * @retval * Number of used HWA Param sets */ uint16_t DPU_AoAProcHWA_getNumHwaParamSets ( uint16_t numTxAnt, uint16_t numRxVirtAntElevation ); /** * @b Description * @n * The function is AoAProcHWA DPU initialization function. It allocates memory to store * its internal data object and returns a handle if it executes successfully. * * @param[in] initParams Pointer to initialization parameters * * @param[in] errCode Pointer to errCode generates from the API * * \ingroup DPU_AOAPROC_EXTERNAL_FUNCTION * * @retval * Success - valid AoAProcHWA handle * @retval * Error - NULL */ DPU_AoAProcHWA_Handle DPU_AoAProcHWA_init ( DPU_AoAProcHWA_InitParams *initParams, int32_t* errCode ); /** * @b Description * @n * The function is AoAProcHWA DPU configuration function. It saves buffer pointer and configurations * including system resources and configures EDMA for runtime range processing. * * @pre DPU_AoAProcHWA_init() has been called * * @param[in] handle AoAProcHWA DPU handle * @param[in] aoaHwaCfg Pointer to AoAProcHWA configuration data structure * * \ingroup DPU_AOAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_AoAProcHWA_config ( DPU_AoAProcHWA_Handle handle, DPU_AoAProcHWA_Config *aoaHwaCfg ); /** * @b Description * @n * The function is AoAProcHWA DPU process function. It performs CFAR detection using HWA * * @pre DPU_AoAProcHWA_init() has been called * * @param[in] handle AoAProcHWA DPU handle * * @param[in] numObjsIn Number of detected objects by CFAR DPU * * @param[in] outParams DPU output parameters * * \ingroup DPU_AOAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_AoAProcHWA_process ( DPU_AoAProcHWA_Handle handle, uint32_t numObjsIn, DPU_AoAProcHWA_OutParams *outParams ); /** * @b Description * @n * The function is AoAProcHWA DPU control function. * * @pre DPU_AoAProcHWA_init() has been called * * @param[in] handle AoAProcHWA DPU handle * @param[in] cmd AoAProcHWA DPU control command * @param[in] arg AoAProcHWA DPU control argument pointer * @param[in] argSize AoAProcHWA DPU control argument size * * \ingroup DPU_AOAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_AoAProcHWA_control ( DPU_AoAProcHWA_Handle handle, DPU_AoAProcHWA_Cmd cmd, void *arg, uint32_t argSize ); /** * @b Description * @n * The function is AoAProcHWA DPU deinitialization function. It frees up the * resources allocated during initialization. * * @pre DPU_AoAProcHWA_init() has been called * * @param[in] handle AoAProcHWA DPU handle * * \ingroup DPU_AOAPROC_EXTERNAL_FUNCTION * * @retval * Success - 0 * @retval * Error - <0 */ int32_t DPU_AoAProcHWA_deinit ( DPU_AoAProcHWA_Handle handle ); /** @defgroup DPC_OBJDET_EXTERNAL Object Detection DPC (Data-path Processing Chain) External * * This DPC performs processes ADC samples and generates detected object list. */ /** @defgroup DPC_OBJDET__GLOBAL Object Detection DPC Globals @ingroup DPC_OBJDET_EXTERNAL @brief * This section has a list of all the globals exposed by the Object detection DPC. */ /** @defgroup DPC_OBJDET_IOCTL__DATA_STRUCTURES Object Detection DPC Data Structures @ingroup DPC_OBJDET_EXTERNAL @brief * This section has a list of all the data structures which are a part of the DPC module * and which are exposed to the application */ /** @defgroup DPC_OBJDET_IOCTL__DEFINITIONS Object Detection DPC Definitions @ingroup DPC_OBJDET_EXTERNAL @brief * This section has a list of all the definitions which are used by the Object Detection DPC. */ /** @defgroup DPC_OBJDET_IOCTL__COMMAND Object Detection DPC Configuration Commands @ingroup DPC_OBJDET_EXTERNAL @brief * This section has a list of all the commands which are supported by the DPC. * All commands of the type IOCTL__STATIC_<...> can only be issued either before the * first call to @ref DPM_start (DPC_ObjectDetection_start) or after the @ref DPM_stop (DPC_ObjectDetection_stop) * All commands of the type IOCTL__DYNAMIC_<...> can be issued between at * the inter-frame boundary i.e when the result is available from @ref DPM_execute (DPC_ObjectDetection_execute). * All commands of the type IOCTL__STATIC_<..> must be issued * before @ref DPM_start (DPC_ObjectDetection_start) because there are no defaults. */ /** @defgroup DPC_OBJECTDETECTION_ERROR_CODE Object Detection DPC Error Codes @ingroup DPC_OBJDET_EXTERNAL @brief * This section has a list of all the error codes returned when calling Object Detection DPC functions * during error conditions. */ /** @addtogroup DPC_OBJDET_IOCTL__DEFINITIONS @{ */ /* Currently nothing here */ /** @} */ /** @addtogroup DPC_OBJDET_IOCTL__DATA_STRUCTURES @{ */ /** * @brief * DC range signature compensation * * @details * The structure contains the DC range antenna signature removeal configuration used in data path */ typedef struct DPC_ObjectDetection_CalibDcRangeSigCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Calibration DC Range configuration */ DPU_RangeProc_CalibDcRangeSigCfg cfg; }DPC_ObjectDetection_CalibDcRangeSigCfg; /** * @brief * CFAR Configuration * * @details * The structure contains the cfar configuration used in data path */ typedef struct DPC_ObjectDetection_CfarCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief CFAR Configuration */ DPU_CFARCAProc_CfarCfg cfg; }DPC_ObjectDetection_CfarCfg; /*! @brief Field of view configuration in range domain */ typedef struct DPC_ObjectDetection_fovRangeCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Field of view configuration in range domain */ DPU_CFARCAProc_FovCfg cfg; } DPC_ObjectDetection_fovRangeCfg; /*! @brief Field of view configuration in Doppler domain */ typedef struct DPC_ObjectDetection_fovDopplerCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Field of view configuration in Doppler domain */ DPU_CFARCAProc_FovCfg cfg; } DPC_ObjectDetection_fovDopplerCfg; /** * @brief * Multi-object beam forming Configuration. */ typedef struct DPC_ObjectDetection_MultiObjBeamFormingCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Multi Object Beam Forming configuration */ DPU_AoAProc_MultiObjBeamFormingCfg cfg; }DPC_ObjectDetection_MultiObjBeamFormingCfg; /* * @brief Field of view configuration for AoA. * */ typedef struct DPC_ObjectDetection_fovAoaCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Field of view configuration for AoA */ DPU_AoAProc_FovAoaCfg cfg; } DPC_ObjectDetection_fovAoaCfg; /* * @brief Extended maximum velocity configuration * */ typedef struct DPC_ObjectDetection_extMaxVelCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Field of view configuration for AoA */ DPU_AoAProc_ExtendedMaxVelocityCfg cfg; } DPC_ObjectDetection_extMaxVelCfg; /* * @brief Range Bias and rx channel gain/phase compensation configuration. * */ typedef struct DPC_ObjectDetection_RangeAzimuthHeatMapCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Flag indicates to prepare data for azimuth heat-map */ _Bool prepareRangeAzimuthHeatMap; } DPC_ObjectDetection_RangeAzimuthHeatMapCfg; /** * @brief * Static clutter removal base (subframe agnostic) configuration * * @details * The structure contains Static clutter removal configuration */ typedef struct DPC_ObjectDetection_StaticClutterRemovalCfg_Base_t { /*! @brief enabled flag: 1-enabled 0-disabled */ uint8_t enabled; } DPC_ObjectDetection_StaticClutterRemovalCfg_Base; /** * @brief * Static clutter removal configuration * * @details * The structure contains static clutter removal configuration */ typedef struct DPC_ObjectDetection_StaticClutterRemovalCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! @brief Static clutter Removal Cfg */ DPC_ObjectDetection_StaticClutterRemovalCfg_Base cfg; } DPC_ObjectDetection_StaticClutterRemovalCfg; /** * @brief Range Bias and rx channel gain/phase measurement configuration. * */ typedef struct DPC_ObjectDetection_MeasureRxChannelBiasCfg_t { /*! @brief 1-enabled 0-disabled */ uint8_t enabled; /*! @brief Target distance during measurement (in meters) */ float targetDistance; /*! @brief Search window size (in meters), the search is done in range * [-searchWinSize/2 + targetDistance, targetDistance + searchWinSize/2] */ float searchWinSize; } DPC_ObjectDetection_MeasureRxChannelBiasCfg; /*! * @brief Call back function type for calling back during process * @param[out] subFrameIndx Sub-frame indx [0..(numSubFrames-1)] */ typedef void (*DPC_ObjectDetection_processCallBackFxn_t)(uint8_t subFrameIndx); /*! @brief Process call backs configuration */ typedef struct DPC_ObjectDetection_ProcessCallBackCfg_t { /*! @brief Call back function that will be called at the beginning of frame * processing (beginning of 1D) */ DPC_ObjectDetection_processCallBackFxn_t processFrameBeginCallBackFxn; /*! @brief Call back function that will be called at the beginning of inter-frame * processing (beginning of 2D) */ DPC_ObjectDetection_processCallBackFxn_t processInterFrameBeginCallBackFxn; } DPC_ObjectDetection_ProcessCallBackCfg; /* * @brief Memory Configuration used during init API */ typedef struct DPC_ObjectDetection_MemCfg_t { /*! @brief Start address of memory provided by the application * from which DPC will allocate. */ void *addr; /*! @brief Size limit of memory allowed to be consumed by the DPC */ uint32_t size; } DPC_ObjectDetection_MemCfg; /* * @brief Configuration for DPM's init API. * DPM_init's arg = pointer to this structure. * DPM_init's argLen = size of this structure. * */ typedef struct DPC_ObjectDetection_InitParams_t { /*! @brief Handle to the hardware accelerator */ HWA_Handle hwaHandle; /*! @brief Handles of the EDMA driver. */ EDMA_Handle edmaHandle[(2U)]; /*! @brief L3 RAM configuration. DPC will allocate memory from this * as needed and report the amount of memory consumed through * @ref DPC_ObjectDetection_PreStartCfg to application */ DPC_ObjectDetection_MemCfg L3ramCfg; /*! @brief Core Local RAM configuration (e.g data TCM for R4F). * DPC will allocate memory from this as needed and report the amount * of memory consumed through @ref DPC_ObjectDetection_PreStartCfg * to the application */ DPC_ObjectDetection_MemCfg CoreLocalRamCfg; /*! @brief Process call back function configuration */ DPC_ObjectDetection_ProcessCallBackCfg processCallBackCfg; } DPC_ObjectDetection_InitParams; /* * @brief Static Configuration that is part of the pre-start configuration. */ typedef struct DPC_ObjectDetection_StaticCfg_t { /*! @brief ADCBuf buffer interface */ DPIF_ADCBufData ADCBufData; /*! @brief Rx Antenna order */ uint8_t rxAntOrder[4U]; /*! @brief Tx Antenna order */ uint8_t txAntOrder[3U]; /*! @brief Number of transmit antennas */ uint8_t numTxAntennas; /*! @brief Number of virtual antennas */ uint8_t numVirtualAntennas; /*! @brief Number of virtual azimuth antennas */ uint8_t numVirtualAntAzim; /*! @brief Number of virtual elevation antennas */ uint8_t numVirtualAntElev; /*! @brief Number of range FFT bins, this is at a minimum the next power of 2 of @ref DPIF_ADCBufProperty_t::numAdcSamples. If range zoom is supported, this can be bigger than the minimum. */ uint16_t numRangeBins; /*! @brief Number of chirps per frame */ uint16_t numChirpsPerFrame; /*! @brief Number of chirps for Doppler computation purposes. For example, in TDM/BPM-MIMO scheme, this is the physical chirps in a frame per transmit antenna i.e numDopplerChirps = @ref numChirpsPerFrame / @ref numTxAntennas */ uint16_t numDopplerChirps; /*! @brief Number of Doppler FFT bins, this is at a minimum the next power of 2 of @ref numDopplerChirps. If Doppler zoom is supported, this can be bigger than the minimum. */ uint16_t numDopplerBins; /*! @brief Range conversion factor for FFT range index to meters */ float rangeStep; /*! @brief Doppler conversion factor for Doppler FFT index to m/s */ float dopplerStep; /*! @brief 1 if valid profile has one Tx per chirp else 0 */ uint8_t isValidProfileHasOneTxPerChirp; /*! @brief Antenna geometry definition */ ANTDEF_AntGeometry antDef; /*! @brief Range FFT Tuning Params */ DPU_RangeProcHWA_FFTtuning rangeFFTtuning; /*! @brief Center frequency of the chirp */ float centerFreq; } DPC_ObjectDetection_StaticCfg; /* * @brief Dynamic Configuration that is part of the pre-start configuration. */ typedef struct DPC_ObjectDetection_DynCfg_t { /*! @brief Calibration DC Range configuration */ DPU_RangeProc_CalibDcRangeSigCfg calibDcRangeSigCfg; /*! @brief CFAR configuration in range direction */ DPU_CFARCAProc_CfarCfg cfarCfgRange; /*! @brief CFAR configuration in Doppler direction */ DPU_CFARCAProc_CfarCfg cfarCfgDoppler; /*! @brief Field of view configuration in range domain */ DPU_CFARCAProc_FovCfg fovRange; /*! @brief Field of view configuration in Doppler domain */ DPU_CFARCAProc_FovCfg fovDoppler; /*! @brief Multi Object Beam Forming configuration */ DPU_AoAProc_MultiObjBeamFormingCfg multiObjBeamFormingCfg; /*! @brief Flag indicates to prepare data for azimuth heat-map */ _Bool prepareRangeAzimuthHeatMap; /*! @brief Field of view configuration for AoA */ DPU_AoAProc_FovAoaCfg fovAoaCfg; /*! @brief Extended maximum velocity configuration */ DPU_AoAProc_ExtendedMaxVelocityCfg extMaxVelCfg; /*! @brief Static Clutter Removal Cfg */ DPC_ObjectDetection_StaticClutterRemovalCfg_Base staticClutterRemovalCfg; } DPC_ObjectDetection_DynCfg; /* * @brief Configuration related to IOCTL API for command * @ref DPC_OBJDET_IOCTL__STATIC_PRE_START_COMMON_CFG. This is independent * of sub frame. */ typedef struct DPC_ObjectDetection_PreStartCommonCfg_t { /*! @brief Number of sub-frames */ uint8_t numSubFrames; /*! @brief Range Bias and rx channel gain/phase measurement configuration */ DPC_ObjectDetection_MeasureRxChannelBiasCfg measureRxChannelBiasCfg; /*! @brief Range Bias and rx channel gain/phase compensation configuration */ DPU_AoAProc_compRxChannelBiasCfg compRxChanCfg; /*! @brief Antenna geometry */ ANTDEF_AntGeometry antDef; } DPC_ObjectDetection_PreStartCommonCfg; /* * @brief Structure related to @ref DPC_OBJDET_IOCTL__STATIC_PRE_START_CFG * IOCTL command. When the pre-start IOCTL is processed, it will report * memory usage as part of @DPC_ObjectDetection_PreStartCfg. */ typedef struct DPC_ObjectDetection_DPC_IOCTL_preStartCfg_memUsage_t { /*! @brief Indicates number of bytes of L3 memory allocated to be used by DPC */ uint32_t L3RamTotal; /*! @brief Indicates number of bytes of L3 memory used by DPC from the allocated * amount indicated through @ref DPC_ObjectDetection_InitParams */ uint32_t L3RamUsage; /*! @brief Indicates number of bytes of Core Local memory allocated to be used by DPC */ uint32_t CoreLocalRamTotal; /*! @brief Indicates number of bytes of Core Local memory used by DPC from the allocated * amount indicated through @ref DPC_ObjectDetection_InitParams */ uint32_t CoreLocalRamUsage; /*! @brief Indicates number of bytes of system heap allocated */ uint32_t SystemHeapTotal; /*! @brief Indicates number of bytes of system heap used at the end of PreStartCfg */ uint32_t SystemHeapUsed; /*! @brief Indicates number of bytes of system heap used by DCP at the end of PreStartCfg */ uint32_t SystemHeapDPCUsed; } DPC_ObjectDetection_DPC_IOCTL_preStartCfg_memUsage; /* * @brief Configuration related to IOCTL API for command * @ref DPC_OBJDET_IOCTL__STATIC_PRE_START_CFG. * */ typedef struct DPC_ObjectDetection_PreStartCfg_t { /*! @brief Subframe number for which this message is applicable. When * advanced frame is not used, this should be set to * 0 (the 1st and only sub-frame) */ uint8_t subFrameNum; /*! Static configuration */ DPC_ObjectDetection_StaticCfg staticCfg; /*! Dynamic configuration */ DPC_ObjectDetection_DynCfg dynCfg; /*! Memory usage after the preStartCfg is applied */ DPC_ObjectDetection_DPC_IOCTL_preStartCfg_memUsage memUsage; } DPC_ObjectDetection_PreStartCfg; /* * @brief Stats structure to convey to Application timing and related information. */ typedef struct DPC_ObjectDetection_Stats_t { /*! @brief interChirpProcess margin in CPU cyctes */ uint32_t interChirpProcessingMargin; /*! @brief Counter which tracks the number of frame start interrupt */ uint32_t frameStartIntCounter; /*! @brief Frame start CPU time stamp */ uint32_t frameStartTimeStamp; /*! @brief Inter-frame start CPU time stamp */ uint32_t interFrameStartTimeStamp; /*! @brief Inter-frame end CPU time stamp */ uint32_t interFrameEndTimeStamp; /*! @brief Sub frame preparation cycles. Note when this is reported as part of * the process result reporting, then it indicates the cycles that took * place in the previous sub-frame/frame for preparing to switch to * the sub-frame that is being reported because switching happens * in the processing of DPC_OBJDET_IOCTL__DYNAMIC_EXECUTE_RESULT_EXPORTED, * which is after the DPC process. */ uint32_t subFramePreparationCycles; } DPC_ObjectDetection_Stats; /* * @brief This is the result structure reported from DPC's registered processing function * to the application through the DPM_Buffer structure. The DPM_Buffer's * first fields will be populated as follows: * pointer[0] = pointer to this structure. * size[0] = size of this structure i.e sizeof(DPC_ObjectDetection_Result) * * pointer[1..3] = NULL and size[1..3] = 0. */ typedef struct DPC_ObjectDetection_ExecuteResult_t { /*! @brief Sub-frame index, this is in the range [0..numSubFrames - 1] */ uint8_t subFrameIdx; /*! @brief Number of detected objects */ uint32_t numObjOut; /*! @brief Detected objects output list of @ref numObjOut elements */ DPIF_PointCloudCartesian *objOut; /*! @brief Radar Cube structure */ DPIF_RadarCube radarCube; /*! @brief Detection Matrix structure */ DPIF_DetMatrix detMatrix; /*! @brief Detected objects side information (snr + noise) output list, * of @ref numObjOut elements */ DPIF_PointCloudSideInfo *objOutSideInfo; /*! @brief Pointer to range-azimuth static heat map, this is a 2D FFT * array in range direction (cmplx16ImRe_t x[numRangeBins][numVirtualAntAzim]), * at doppler index 0 */ cmplx16ImRe_t *azimuthStaticHeatMap; /*! @brief Number of elements of @ref azimuthStaticHeatMap, this will be * @ref DPC_ObjectDetection_StaticCfg_t::numVirtualAntAzim * * @ref DPC_ObjectDetection_StaticCfg_t::numRangeBins */ uint32_t azimuthStaticHeatMapSize; /*! @brief Pointer to DPC stats structure */ DPC_ObjectDetection_Stats *stats; /*! @brief Pointer to Range Bias and rx channel gain/phase compensation measurement * result. Note the contents of this pointer are independent of sub-frame * i.e all sub-frames will report the same result although it is * expected that when measurement is enabled, * the number of sub-frames will be 1 (i.e advanced frame * feature will be disabled). If measurement * was not enabled, then this pointer will be NULL. */ DPU_AoAProc_compRxChannelBiasCfg *compRxChanBiasMeasurement; } DPC_ObjectDetection_ExecuteResult; /* * @brief This is the informational structure related to the IOCTL command * @ref DPC_OBJDET_IOCTL__DYNAMIC_EXECUTE_RESULT_EXPORTED. */ typedef struct DPC_ObjectDetection_ExecuteResultExportedInfo_t { /*! @brief Sub-frame index, this is in the range [0..numSubFrames - 1]. * This is the sub-frame whose results have been exported. * Although this DPC implementation knows what sub-frame to expect as the exports * are expected to be sequential in sub-frames, this field helps * in error checking when for example the application could miss * exporting/consuming a sub-frame in a timely manner or have out of order * export/consumption. */ uint8_t subFrameIdx; } DPC_ObjectDetection_ExecuteResultExportedInfo; /** @} */ /** @addtogroup DPC_OBJDET_IOCTL__COMMAND @{ */ /** * @brief Command associated with @ref DPC_ObjectDetection_PreStartCfg_t. In this IOCTL, the sub-frame's * configurations will be processed by configuring individual DPUs. * The @ref DPC_OBJDET_IOCTL__STATIC_PRE_START_COMMON_CFG must be issued * before issuing this IOCTL. */ /** * @brief Command associated with @ref DPC_ObjectDetection_PreStartCommonCfg_t. Must be issued before * issuing @ref DPC_OBJDET_IOCTL__STATIC_PRE_START_CFG */ /** * @brief Command associated with @ref DPC_ObjectDetection_CfarCfg_t for range dimension. */ /** * @brief Command associated with @ref DPC_ObjectDetection_CfarCfg_t for doppler dimension. */ /** * @brief Command associated with @ref DPC_ObjectDetection_MultiObjBeamFormingCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_CalibDcRangeSigCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_StaticClutterRemovalCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_MeasureRxChannelBiasCfg_t */ /** * @brief Command associated with @ref DPU_AoAProc_compRxChannelBiasCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_fovRangeCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_fovDopplerCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_fovAoaCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_RangeAzimuthHeatMapCfg_t */ /** * @brief Command associated with @ref DPC_ObjectDetection_extMaxVelCfg_t */ /** * @brief This commands indicates to the DPC that the results DPC provided to the application * through its execute API (which application will access through DPM_execute API) * have been exported/consumed. The purpose of this command is for DPC to * reclaim the memory resources associated with the results. The DPC may * also perform sub-frame switching, and do error-checking to see * if export was later than expected e.g the DPC design may be such that * the previous frame/sub-frame's export notification may need to come * after a new frame/sub-frame (this is the case currently with this * object detection DPC). The DPC will also consider this command as a * signal from the application that all its processing for the current frame/sub-frame * has been done and so if a new frame/sub-frame interrupt (DPC has registered * a frame interrupt with the DPM) comes before the last step in the * processing of this command (which could be sub-frame switching and * preparing for next sub-frame/frame), then the DPC will signal an assert * to the application from its frame interrupt. The expected sequence is * the following: * * 1. App consumes the process result of the DPC (e.g sending output on UART). * 2. App performs any dynamic configuration command processing by issuing DPC's * IOCTL APIs for the next frame/sub-frame. * 3. App issues this result-exported IOCTL. * 4. DPC does its processing related to this IOCTL in the following sequence: * a. May do error checking and preparing for next sub-frame/frame. * b. Do book-keeping related to marking this as end of sub-frame/frame processing * by the app. The DPC's registered frame start interrupt performs * check on this information to see if next frame/sub-frame came before * this end of processing in which case it will issue an assert to app. * * An informational structure @ref DPC_ObjectDetection_ExecuteResultExportedInfo_t * is associated with this command. */ /** * @brief This command is for non real-time (without RF) testing. When issued, it will simulate * the trigger of frame start. No configuration structure is associated with this command. * Must be issued between start and stop of DPC. */ /** @} */ /** @addtogroup DPC_OBJECTDETECTION_ERROR_CODE * Base error code for the objdethwa DPC is defined in the * \include ti/datapath/dpif/dp_error.h @{ */ /** * @brief Error Code: Invalid argument general (such as NULL argument pointer) */ /** * @brief Error Code: Invalid argSize in DPM_InitCfg provided to @ref DPC_ObjectDetection_init, * does not match the expected size of @ref DPC_ObjectDetection_InitParams_t */ /** * @brief Error Code: Invalid argument in configuration @ref DPC_ObjectDetection_MeasureRxChannelBiasCfg_t */ /** * @brief Error Code: Invalid argument bad command argument in DPM_ProcChainIoctlFxn for * Object detection DPC. */ /** * @brief Error Code: Out of general heap memory */ /** * @brief Error Code: Out of L3 RAM during radar cube allocation. */ /** * @brief Error Code: Out of L3 RAM during detection matrix allocation. */ /** * @brief Error Code: Out of HWA Window RAM */ /** * @brief Error Code: Out of Core Local RAM for generating window coefficients * for HWA when doing range DPU Config. */ /** * @brief Error Code: Out of Core Local RAM for generating window coefficients * for HWA when doing doppler DPU Config. */ /** * @brief Error Code: When doing CFAR configuration, Core Local RAM allocation for cfarDopplerDetOutBitMask * failed. */ /** * @brief Error Code: When doing Static clutter configuration, Core Local RAM allocation for * its scratch buffer failed. */ /** * @brief Error Code: Out of Core Local RAM allocation for cfarRngDopSnrList (DPIF_CFARDetList). */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's detObjOut. */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's detObjOutSideInfo. */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's detObj2dAzimIdx. */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's detObjElevationAngle. */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's azimuthStaticHeatMap. */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's angle FFT magnitude buffer. */ /** * @brief Error Code: Out of Core Local RAM allocation for AoA's scratch buffer. */ /** * @brief Error Code: Pre-start config was received before pre-start common config. */ /** * @brief Error Code: Internal error */ /** * @brief Error Code: Not implemented */ /** @} */ /** @addtogroup DPC_OBJDET__GLOBAL @{ */ /*! Application developers: Use this configuration to load the Object Detection DPC * within the DPM. */ extern DPM_ProcChainCfg gDPC_ObjectDetectionCfg; /** @} */ /** * @brief * Millimeter Wave Demo Gui Monitor Selection * * @details * The structure contains the selection for what information is placed to * the output packet, and sent out to GUI. Unless otherwise specified, * if the flag is set to 1, information * is sent out. If the flag is set to 0, information is not sent out. * */ typedef struct MmwDemo_GuiMonSel_t { /*! @brief if 1: Send list of detected objects (see @ref DPIF_PointCloudCartesian) and * side info (@ref DPIF_PointCloudSideInfo).\n * if 2: Send list of detected objects only (no side info)\n * if 0: Don't send anything */ uint8_t detectedObjects; /*! @brief Send log magnitude range array */ uint8_t logMagRange; /*! @brief Send noise floor profile */ uint8_t noiseProfile; /*! @brief Send complex range bins at zero doppler, all antenna symbols for range-azimuth heat map */ uint8_t rangeAzimuthHeatMap; /*! @brief Send complex range bins at zero doppler, (all antenna symbols), for range-azimuth heat map */ uint8_t rangeDopplerHeatMap; /*! @brief Send stats */ uint8_t statsInfo; } MmwDemo_GuiMonSel; /** * @brief * LVDS streaming configuration * * @details * The structure is used to hold all the relevant configuration * for the LVDS streaming. */ typedef struct MmwDemo_LvdsStreamCfg_t { /** * @brief HSI Header enabled/disabled flag. Only applicable for HW streaming. * Will be ignored for SW streaming which will always have HSI header. */ _Bool isHeaderEnabled; /*! HW STREAMING DISABLED */ /*! ADC */ /*! CP_ADC_CQ */ /*! HW streaming data format: 0-HW STREAMING DISABLED 1-ADC 2-Reserved 3-Reserved 4-CP_ADC_CQ */ uint8_t dataFmt; /** * @brief SW enabled/disabled flag */ _Bool isSwEnabled; }MmwDemo_LvdsStreamCfg; /** * @brief * Millimeter Wave Demo Data Path Information. * * @details * The structure is used to hold all the relevant information for * the data path. */ typedef struct MmwDemo_platformCfg_t { /*! @brief GPIO index for sensor status */ uint32_t SensorStatusGPIO; /*! @brief CPU Clock Frequency. */ uint32_t sysClockFrequency; /*! @brief UART Logging Baud Rate. */ uint32_t loggingBaudRate; /*! @brief UART Command Baud Rate. */ uint32_t commandBaudRate; } MmwDemo_platformCfg; /** * @brief * Millimeter Wave Demo configuration * * @details * The structure is used to hold all the relevant configuration * which is used to execute the Millimeter Wave Demo. */ typedef struct MmwDemo_Cfg_t { /*! @brief mmWave Control Configuration. */ MMWave_CtrlCfg ctrlCfg; /*! @brief mmWave Open Configuration. */ MMWave_OpenCfg openCfg; /*! @brief Platform specific configuration. */ MmwDemo_platformCfg platformCfg; /*! @brief Datapath output loggerSetting 0 (default): MSS UART logger 1: DSS UART logger */ uint8_t dataLogger; } MmwDemo_Cfg; typedef struct MmwDemo_DPC_ObjDet_CommonCfg_t { /*! @brief Flag indicating if new MeasureRxChannelBiasCfg configuration is * pending issuance to DPC */ uint8_t isMeasureRxChannelBiasCfgPending : 1; /*! @brief Flag indicating if new CompRxChannelBiasCfg configuration is * pending issuance to DPC */ uint8_t isCompRxChannelBiasCfgPending : 1; /*! @brief pre start common config */ DPC_ObjectDetection_PreStartCommonCfg preStartCommonCfg; } MmwDemo_DPC_ObjDet_CommonCfg; typedef struct MmwDemo_DPC_ObjDet_DynCfg_t { /*! @brief Flag indicating if new CalibDcRangeSigCfg configuration is * pending issuance to DPC */ uint16_t isCalibDcRangeSigCfg : 1; /*! @brief Flag indicating if new CfarCfgRange configuration is * pending issuance to DPC */ uint16_t isCfarCfgRangePending : 1; /*! @brief Flag indicating if new CfarCfgDoppler configuration is * pending issuance to DPC */ uint16_t isCfarCfgDopplerPending : 1; /*! @brief Flag indicating if new FovRange configuration is * pending issuance to DPC */ uint16_t isFovRangePending : 1; /*! @brief Flag indicating if new FovDoppler configuration is * pending issuance to DPC */ uint16_t isFovDopplerPending : 1; /*! @brief Flag indicating if new multiObjBeamFormingCfg configuration is * pending issuance to DPC */ uint16_t isMultiObjBeamFormingCfgPending : 1; /*! @brief Flag indicating if new PrepareRangeAzimuthHeatMap configuration is * pending issuance to DPC */ uint16_t isPrepareRangeAzimuthHeatMapPending : 1; /*! @brief Flag indicating if new fovAoaCfg configuration is * pending issuance to DPC */ uint16_t isFovAoaCfgPending : 1; /*! @brief Flag indicating if new StaticClutterRemovalCfg configuration is * pending issuance to DPC */ uint16_t isStaticClutterRemovalCfgPending : 1; /*! @brief Flag indicating if new extendedMaxVelocity configuration is * pending issuance to DPC */ uint16_t isExtMaxVelCfgPending : 1; /*! @brief dynamic config */ DPC_ObjectDetection_DynCfg dynCfg; } MmwDemo_DPC_ObjDet_DynCfg; /** * @file mmwdemo_rfparser.h * * @brief * Header file for RF configuration parser * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Copyright (c) 2016, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** =========================================================== * @file ADCBuf.h * * @brief ADCBuf driver interface * */ /** @mainpage ADCBuf Driver * * The ADCBuf header file should be included in an application as follows: * @code * #include * @endcode * * # Operation # * The ADCBuf driver in TI-RTOS samples an analogue waveform at a specified * frequency. The resulting samples are transferred to a buffer provided by * the application. The driver can either take n samples once, or continuously * sample by double-buffering and providing a callback to process each finished * buffer. * * The APIs in this driver serve as an interface to a typical TI-RTOS * application. The specific peripheral implementations are responsible to * create all the SYS/BIOS specific primitives to allow for thread-safe * operation. * * The platform specific ADCBUF file present in the ti/drivers/adcbuf/platform * directory. This file is built as a part of the ADCBUF Library for the specific * platform. * * ## Opening the driver # * * @code * ADCBuf_Handle adcBufHandle; * ADCBuf_Params adcBufParams; * * ADCBuf_Params_init(&adcBufParams); * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); * @endcode * * ## Making a conversion # * In this context, a conversion refers to taking multiple ADC samples and * transferring them to an application-provided buffer. * To start a conversion, the application must configure an ADCBuf_Conversion struct * and call ADCBuf_convert(). In blocking mode, ADCBuf_convert() will return * when the conversion is finished and the desired number of samples have been made. * In callback mode, ADCBuf_convert() will return immediately and the application will * get a callback when the conversion is done. * * @code * ADCBuf_Conversion blockingConversion; * * blockingConversion.arg = NULL; * blockingConversion.adcChannel = Board_ADCCHANNEL_A1; * blockingConversion.sampleBuffer = sampleBufferOnePtr; * blockingConversion.sampleBufferTwo = NULL; * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; * * if (!ADCBuf_convert(adcBuf, &continuousConversion, 1)) { * // handle error * } * @endcode * * ## Canceling a conversion # * ADCBuf_convertCancel() is used to cancel an ADCBuf conversion when the driver is * used in ADCBuf_RETURN_MODE_CALLBACK. * * Calling this API while no conversion is in progress has no effect. If a * conversion is in progress, it is canceled and the provided callback function * is called. * * In ADCBuf_RECURRENCE_MODE_CONTINUOUS, this function must be called to stop the * conversion. The driver will continue providing callbacks with fresh samples * until thie ADCBuf_convertCancel() function is called. The callback function is not * called after ADCBuf_convertCancel() while in ADCBuf_RECURRENCE_MODE_CONTINUOUS. * * # Implementation # * * This module serves as the main interface for TI-RTOS applications. Its * purpose is to redirect the module's APIs to specific peripheral * implementations which are specified using a pointer to an ADCBuf_FxnTable. * * The ADCBuf driver interface module is joined (at link time) to a * NULL-terminated array of ADCBuf_Config data structures named *ADCBuf_config*. * *ADCBuf_config* is implemented in the application with each entry being an * instance of an ADCBuf peripheral. Each entry in *ADCBuf_config* contains a: * - (ADCBuf_FxnTable *) to a set of functions that implement an ADCBuf peripheral * - (void *) data object that is associated with the ADCBuf_FxnTable * - (void *) hardware attributes that are associated to the ADCBuf_FxnTable * * # Instrumentation # * * The ADCBuf driver interface produces log statements if instrumentation is * enabled. * * Diagnostics Mask | Log details | * ---------------- | ---------------------------------| * Diags_USER1 | basic operations performed | * Diags_USER2 | detailed operations performed | * * ============================================================================ */ /** @defgroup ADCBUF_DRIVER_EXTERNAL_FUNCTION ADCBUF Driver External Functions @ingroup ADCBUF_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE ADCBUF Driver External Data Structures @ingroup ADCBUF_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup ADCBUF_DRIVER_ERROR_CODE ADCBUF Driver Error Codes @ingroup ADCBUF_DRIVER @brief * The section has a list of all the error codes which are generated by the CRC Driver * module */ /** @defgroup ADCBUF_DRIVER_INTERNAL_FUNCTION ADCBUF Driver Internal Functions @ingroup ADCBUF_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup ADCBUF_DRIVER_INTERNAL_DATA_STRUCTURE ADCBUF Driver Internal Data Structures @ingroup ADCBUF_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the ADCBUF module. */ /*! * Common ADCBuf_control command code reservation offset. * ADC driver implementations should offset command codes with ADCBuf_CMD_RESERVED * growing positively * * Example implementation specific command codes: * @code * #define ADCXYZ_COMMAND0 ADCBuf_CMD_RESERVED + 0 * #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1 * @endcode */ /*! * Common ADCBuf_control status code reservation offset. * ADC driver implementations should offset status codes with * ADCBuf_STATUS_RESERVED growing negatively. * * Example implementation specific status codes: * @code * #define ADCXYZ_STATUS_ERROR0 ADCBuf_STATUS_RESERVED - 0 * #define ADCXYZ_STATUS_ERROR1 ADCBuf_STATUS_RESERVED - 1 * #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2 * @endcode */ /*! * \brief Success status code returned by: * ADCBuf_control() * * Functions return ADCBuf_STATUS_SUCCESS if the call was executed * successfully. */ /*! * \brief Generic error status code returned by ADCBuf_control(). * * ADCBuf_control() returns ADCBuf_STATUS_ERROR if the control code was not executed * successfully. * * \ingroup ADCBUF_DRIVER_ERROR_CODE * */ /*! * \brief An error status code returned by ADCBuf_control() for undefined * command codes. * * ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is not * recognized by the driver implementation. * * \ingroup ADCBUF_DRIVER_ERROR_CODE * */ /*! * \brief An error status code returned by ADCBuf_control() for feature not implemented. * * ADCBuf_control() returns ADCBuf_STATUS_NOT_IMPLEMENTED if the control command * was not supported. * * \ingroup ADCBUF_DRIVER_ERROR_CODE * */ /*! * \brief An error status code returned by ADCBuf_control() for invalid input parameters. * * ADCBuf_control() returns ADCBuf_STATUS_INVALID_PARAMS if the control code gets * invalid parameters. * * \ingroup ADCBUF_DRIVER_ERROR_CODE * */ /*! * \brief An error status code returned by ADCBuf_control() for invalid * command codes. * * ADCBuf_control() returns ADCBuf_STATUS_INVALID_CMD if the control code is not * recognized by the driver implementation. * * \ingroup ADCBUF_DRIVER_ERROR_CODE * */ /*! * \brief An error status code returned by ADCBuf_open() for invalid * socHandle. * * * \ingroup ADCBUF_DRIVER_ERROR_CODE * */ /*! * @brief A handle that is returned from an ADCBuf_open() call. */ typedef struct ADCBuf_Config_t *ADCBuf_Handle; /*! * @brief * An ::ADCBuf_Conversion data structure is used with ADCBuf_convert(). It indicates * which channel to perform the ADC conversion on, how many conversions to make, and where to put them. * The arg variable is an user-definable argument which gets passed to the * ::ADCBuf_Callback when the ADC driver is in ADCBuf_RETURN_MODE_CALLBACK. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef struct ADCBuf_Conversion_t { uint16_t samplesRequestedCount; /*!< Number of samples to convert and return */ void *sampleBuffer; /*!< Buffer the results of the conversions are stored in */ void *sampleBufferTwo; /*!< A second buffer that is filled in ADCBuf_RECURRENCE_MODE_CONTINUOUS mode while the first buffer is processed by the application. The value is not used in ADCBuf_RECURRENCE_MODE_ONE_SHOT mode. */ void *arg; /*!< Argument to be passed to the callback function in ADCBuf_RETURN_MODE_CALLBACK */ uint32_t adcChannel; /*!< Channel to perform the ADC conversion on. Mapping of channel to pin or internal signal is device specific. */ } ADCBuf_Conversion; /*! * @brief The definition of a callback function used by the ADC driver * when used in ADCBuf_RETURN_MODE_CALLBACK. It is called in a HWI or SWI context depending on the device specific implementation. */ typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle, ADCBuf_Conversion *conversion, void *activeADCBuffer); /*! * @brief The definition of a callback function used by the ADCBUF interrupt handler */ typedef void (*ADCBuf_IntCallbackFxn) (ADCBuf_Handle handle); /** * @brief * ADCBUF Source selection * * @details * The structure is used to define ADCBUF driver commands. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef enum ADCBufSource_e { /** * @brief Select DFE as source. */ ADCBUF_SOURCE_DFE = 0, /** * @brief Select HIL as source. */ ADCBUF_SOURCE_HIL }ADCBufSource; /** * @brief * ADC Buffer data format Parameters * * @details * The structure is used to define ADC Buffer data format. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef struct ADCBuf_dataFormat_t { /* ADC out Format 0 - Complex Data mode 1 - Real data mode */ uint8_t adcOutFormat; /* Sample interleave - IQswap 0 - I is stored in LSB, Q is stored in MSB 1 - Q is stored in LSB, I is stored in MSB */ uint8_t sampleInterleave; /* channel interleave 0 - interleaved 1 - non-interleaved */ uint8_t channelInterleave; }ADCBuf_dataFormat; /** * @brief * ADC Buffer RX channel configuration Parameters * * @details * The structure is used to define ADC Buffer RX Channel configuration. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef struct ADCBuf_RxChanConf_t { /* RX channel id - 0~3 */ uint8_t channel; /* Address offset for the channel in Ping/Pong buffer Used only in non-interleaved mode, it must be 16 bytes aligned. */ uint16_t offset; }ADCBuf_RxChanConf; /** * @brief * ADC Buffer test pattern configuration Parameters * * @details * The structure is used to define ADC Buffer test pattern configuration. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef struct ADCBuf_rxTestPatternConf_t { /* I sample offset */ uint16_t rxIOffset; /* I sample incremental value */ uint16_t rxIInc; /* Q sample offset */ uint16_t rxQOffset; /* Q sample incremental value */ uint16_t rxQInc; }ADCBuf_rxTestPatternConf; /** * @brief * ADC Buffer test pattern configuration Parameters * * @details * The structure is used to define ADC Buffer test pattern configuration. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef struct ADCBuf_TestPatternConf_t { /* Test pattern configuration for 4 channels */ ADCBuf_rxTestPatternConf rxConfig[4U]; /* Periodicity of the pattern */ uint16_t period; /* Sample count to store in ADC buffer */ uint16_t numSamples; }ADCBuf_TestPatternConf; /** * @brief * Chirp Quality(CQ) configuration Parameters * * @details * The structure is used to define Chirp Quality configuration. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef struct ADCBuf_CQConf_t { /*! 0x0 or 0x1:Raw16, 0x2:Raw12, 0x3:Raw14 */ uint8_t cqDataWidth; /*! Set in case of 3 channel mode */ uint8_t cq96BitPackEn; /*! CQ0 Address offset : 16bytes aligned address for Storing CQ0 */ uint16_t cq0AddrOffset; /*! CQ1 Address offset : 16 bytes aligned address for Storing CQ1 */ uint16_t cq1AddrOffset; /*! CQ2 Address offset : 16 bytes aligned address for Storing CQ2 */ uint16_t cq2AddrOffset; }ADCBuf_CQConf; /*! * @brief ADC Parameters * * ADC Parameters are used to with the ADCBuf_open() call. Default values for * these parameters are set using ADCBuf_Params_init(). * * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * * @sa ADCBuf_Params_init() */ typedef struct ADCBuf_Params_t { /** * @brief ADC buffer source, DFE or HIL */ ADCBufSource source; /** * @brief Continuous mode selection */ uint8_t continousMode; /** * @brief xwr16xx/xwr18xx/xwr68xx: Ping buffer Chirp Threshold for non-continous operation */ uint8_t chirpThresholdPing; /** * @brief xwr16xx/xwr18xx/xwr68xx: Pong buffer Chirp Threshold for non-continous operation */ uint8_t chirpThresholdPong; /** * @brief Custom configuration, Pointer to a device specific extension of the ADCBuf_Params */ void *custom; /** * @brief SOC Handle */ SOC_Handle socHandle; } ADCBuf_Params; /** * @brief * ADCBUF Command * * @details * The structure is used to define ADCBUF driver commands. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef enum ADCBufMMWave_CMD_e { /** * @brief set ADCBUF source, it can be DFE or VIN. * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_SET_SRC = 0, /** * @brief Set number of Chirps to be stored in each Ping and Pong buffer. * It should be programmed one less the actual number needed . * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_SET_CHIRP_THRESHHOLD, /** * @brief Set number of Chirps to be stored in each Ping buffer. * It should be programmed one less the actual number needed . * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_SET_PING_CHIRP_THRESHHOLD, /** * @brief Set number of Chirps to be stored in each Pong buffer. * It should be programmed one less the actual number needed . * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_SET_PONG_CHIRP_THRESHHOLD, /** * @brief Enables/Disables Continuous mode for ADCBUF. * 1 to enable continuous mode. * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_SET_CONTINUOUS_MODE, /** * @brief Starts Continuous mode for ADCBUF. * Number of Samples to store in Ping/Pong buffer needs to be provided. * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_START_CONTINUOUS_MODE, /** * @brief Stops Continuous mode for ADCBUF. * The size of the argument size for this command is 0 bytes */ ADCBufMMWave_CMD_STOP_CONTINUOUS_MODE, /** * @brief Configures ADCBUF data format. * The size of the argument size for this command is size of \ref ADCBuf_dataFormat */ ADCBufMMWave_CMD_CONF_DATA_FORMAT, /** * @brief Enable RX channels and configures the address offset in ADCBUF for the channel. * The size of the argument size for this command is size of \ref ADCBuf_RxChanConf */ ADCBufMMWave_CMD_CHANNEL_ENABLE, /** * @brief Disable RX channels specified with RX channel bitmask * The size of the argument size for this command is 4 bytes */ ADCBufMMWave_CMD_CHANNEL_DISABLE, /** * @brief Test pattern configuration. * The size of the argument size for this command is size of \ref ADCBuf_TestPatternConf */ ADCBufMMWave_CMD_CONF_TEST_PATTERN, /** * @brief Starts Test pattern generation. Reboot is required when switching from Test pattern mode * to normal operation mode. * The size of the argument size for this command is 0 bytes */ ADCBufMMWave_CMD_START_TEST_PATTERN, /** * @brief Stops Test pattern generation. * The size of the argument size for this command is 0 bytes */ ADCBufMMWave_CMD_STOP_TEST_PATTERN, /** * @brief Chirp Quality configuration. * The size of the argument size for this command is size of \ref ADCBuf_CQConf */ ADCBufMMWave_CMD_CONF_CQ, /** * @brief Last command. */ ADCBufMMWave_CMD_LAST }ADCBufMMWave_CMD; /*! * @brief A function pointer to a driver specific implementation of * ADCBuf_close(). */ typedef void (*ADCBuf_CloseFxn) (ADCBuf_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * ADCBuf_open(). */ typedef ADCBuf_Handle (*ADCBuf_OpenFxn) (ADCBuf_Handle handle, const ADCBuf_Params *params); /*! * @brief A function pointer to a driver specific implementation of * ADCBuf_control(). */ typedef int_fast16_t (*ADCBuf_ControlFxn) (ADCBuf_Handle handle, uint_fast8_t cmd, void *arg); /*! * @brief A function pointer to a driver specific implementation of * ADCBuf_init(). */ typedef void (*ADCBuf_InitFxn) (ADCBuf_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * ADCBuf_getChanBufAddr(). */ typedef uint32_t (*ADCBuf_GetChanBufAddrFxn) (ADCBuf_Handle handle, uint8_t channel, int32_t *errCode); /*! * @brief The definition of an ADCBuf function table that contains the * required set of functions to control a specific ADC driver * implementation. */ typedef struct ADCBuf_FxnTable_t { /*! Function to close the specified peripheral */ ADCBuf_CloseFxn closeFxn; /*! Function to driver implementation specific control function */ ADCBuf_ControlFxn controlFxn; /*! Function to initialize the given data object */ ADCBuf_InitFxn initFxn; /*! Function to open the specified peripheral */ ADCBuf_OpenFxn openFxn; /*! Function to get ADC buffer address for a given channel */ ADCBuf_GetChanBufAddrFxn getChanBufAddr; } ADCBuf_FxnTable; /*! * @brief ADCBuf Global configuration * * The ADCBuf_Config structure contains a set of pointers used to characterise * the ADC driver implementation. * * This structure needs to be defined before calling ADCBuf_init() and it must * not be changed thereafter. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * * @sa ADCBuf_init() */ typedef struct ADCBuf_Config_t { /*! Pointer to a table of driver-specific implementations of ADC APIs */ const ADCBuf_FxnTable *fxnTablePtr; /*! Pointer to a driver specific data object */ void *object; /*! Pointer to a driver specific hardware attributes structure */ void const *hwAttrs; } ADCBuf_Config; /** * @brief * ADCBUF CQ monitoring type * * @details * The structure is used to define CQ monitoring types. * * \ingroup ADCBUF_DRIVER_EXTERNAL_DATA_STRUCTURE * */ typedef enum ADCBufMMWave_CQType_e { /** * @brief CQ type for CQ0. */ ADCBufMMWave_CQType_CQ0, /** * @brief CQ type for CQ1. */ ADCBufMMWave_CQType_CQ1, /** * @brief CQ type for CQ2. */ ADCBufMMWave_CQType_CQ2, /** * @brief Maximum number of CQ which can be supported. */ ADCBufMMWave_CQType_MAX_CQ }ADCBufMMWave_CQType; /*! * @brief Function to close an ADC peripheral specified by the ADC handle * * @pre ADCBuf_open() has to be called first. * * @pre In ADCBuf_RECURRENCE_MODE_CONTINUOUS, the application must call ADCBuf_convertCancel() first. * * @param handle An ADCBuf handle returned from ADCBuf_open() * * \ingroup ADCBUF_DRIVER_EXTERNAL_FUNCTION * * @sa ADCBuf_open() */ extern void ADCBuf_close(ADCBuf_Handle handle); /*! * @brief Function performs implementation specific features on a given * ADCBuf_Handle. * * @pre ADCBuf_open() has to be called first. * * @param handle An ADCBuf handle returned from ADCBuf_open() * * @param cmd A command value defined by the driver specific * implementation * * @param arg A pointer to an optional R/W (read/write) argument that * is accompanied with cmd. arg should be 4 bytes aligned. * * @return An ADCBuf_Status describing an error or success state. Negative values * indicates an error. * * \ingroup ADCBUF_DRIVER_EXTERNAL_FUNCTION * * @sa ADCBuf_open() */ extern int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast8_t cmd, void * arg); /*! * @brief This function gets the physical address of ADCBuf for a given receive channel * * @pre ADCBuf_open() has to be called first. * * @param handle An ADCBuf handle returned from ADCBuf_open() * * @param channel Receive channel number * * @param errCode Pointer to an error code populated by the driver * * @return An ADCBuf physical address for the given channel on success or 0 on an error * * \ingroup ADCBUF_DRIVER_EXTERNAL_FUNCTION * */ extern uint32_t ADCBuf_getChanBufAddr(ADCBuf_Handle handle, uint8_t channel, int32_t *errCode); /*! * @brief This function gets the physical address of chirp info(CQ) buffer for a given CQ type * * @pre ADCBuf_open() has to be called first. * * @param handle An ADCBuf handle returned from ADCBuf_open() * * @param cqType Type of CQ that request the address * * @param errCode Pointer to an error code populated by the driver * * @return An CQ buffer physical address for the given cqType on success or 0 on an error * * \ingroup ADCBUF_DRIVER_EXTERNAL_FUNCTION * */ extern uint32_t ADCBUF_MMWave_getCQBufAddr ( ADCBuf_Handle handle, ADCBufMMWave_CQType cqType, int32_t *errCode ); /*! * @brief This function initializes the ADC module. This function must be called * before any other functions are called. * * @pre The ADCBuf_Config structure must exist and be persistent before this * function can be called. * This function call does not modify any peripheral registers. * Function should only be called once. */ extern void ADCBuf_init(void); /*! * @brief This function sets all fields of a specified ADCBuf_Params structure to their * default values. * * @param params A pointer to ADCBuf_Params structure for initialization * * Default values are: * returnMode = ADCBuf_RETURN_MODE_BLOCKING, * blockingTimeout = 25000, * callbackFxn = NULL, * recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT, * samplingFrequency = 10000, * custom = NULL * * ADCBuf_Params::blockingTimeout should be set large enough to allow for the desired number of samples to be * collected with the specified frequency. * * \ingroup ADCBUF_DRIVER_EXTERNAL_FUNCTION * */ extern void ADCBuf_Params_init(ADCBuf_Params *params); /*! * @brief This function opens a given ADCBuf peripheral. * * @param index Logical peripheral number for the ADCBuf indexed into * the ADCBuf_config table * * @param params Pointer to an parameter block, if NULL it will use * default values. * * @return An ADCBuf_Handle on success or a NULL on an error or if it has been * opened already. If NULL is returned further ADC API calls will * result in undefined behaviour. * * \ingroup ADCBUF_DRIVER_EXTERNAL_FUNCTION * * @sa ADCBuf_close() */ extern ADCBuf_Handle ADCBuf_open(uint_fast8_t index, ADCBuf_Params *params); /** * @file mmwdemo_adcconfig.h * * @brief * API header for adc open/config functions * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @defgroup MMWDEMO_ADCCONFIG_EXTERNAL Mmwdemo ADC Config External */ /** @defgroup MMWDEMO_ADCCONFIG_EXTERNAL_FUNCTION ADC Config External Functions @ingroup MMWDEMO_ADCCONFIG_EXTERNAL @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup MMWDEMO_ADCCONFIG_EXTERNAL_DATA_STRUCTURE ADC Config External Data Structures @ingroup MMWDEMO_ADCCONFIG_EXTERNAL @brief * The section has a list of all external data structures which are used internally * by the ADC Config module. */ /** * @brief * ADCBUF configuration (meant for CLI configuration) * * @details * The structure is used to hold all the relevant configuration * which is used to configure ADCBUF. * * \ingroup MMWDEMO_ADCCONFIG_EXTERNAL_DATA_STRUCTURE */ typedef struct MmwDemo_ADCBufCfg_t { /*! ADCBUF out format: 0-Complex, 1-Real */ uint8_t adcFmt; /*! ADCBUF IQ swap selection: 0-I in LSB, Q in MSB, 1-Q in LSB, I in MSB */ uint8_t iqSwapSel; /*! ADCBUF channel interleave configuration: 0-interleaved(not supported on XWR16xx), 1- non-interleaved */ uint8_t chInterleave; /** * @brief Chirp Threshold configuration used for ADCBUF buffer */ uint8_t chirpThreshold; }MmwDemo_ADCBufCfg; extern ADCBuf_Handle MmwDemo_ADCBufOpen(SOC_Handle socHandle); extern int32_t MmwDemo_ADCBufConfig ( ADCBuf_Handle adcBufHandle, uint16_t rxChannelEn, uint8_t chirpThreshold, uint32_t chanDataSize, MmwDemo_ADCBufCfg *adcBufCfg, uint16_t *rxChanOffset ); /** * @file mmwdemo_error.h * * @brief * Error codes of modules from demo/utils that are used by mmwdemo * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @defgroup MMWDEMO_RFPARSER_EXTERNAL Mmwdemo RFparser External */ /** @defgroup MMWDEMO_RFPARSER_EXTERNAL_FUNCTION RF Parser External Functions @ingroup MMWDEMO_RFPARSER_EXTERNAL @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the RF Parser */ /** @defgroup MMWDEMO_RFPARSER_EXTERNAL_DATA_STRUCTURE RF Parser External Data Structures @ingroup MMWDEMO_RFPARSER_EXTERNAL @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup MMWDEMO_RFPARSER_ERROR_CODE RF Parser Error Codes @ingroup MMWDEMO_RFPARSER_EXTERNAL @brief * The section has a list of all the error codes which are generated by the RFParser DPU */ /** @addtogroup MMWDEMO_RFPARSER_ERROR_CODE @{ */ /** * @brief Error Code: Invalid computed output number of tx antennas. */ /** * @brief Error Code: Invalid computed output number of virtual antennas. */ /** * @brief Error Code: Invalid subFrameIndx argument to @ref MmwDemo_RFParser_parseConfig */ /** * @brief Error Code: Chirp threshold bigger than max allowed */ /** * @brief Error Code: Not implemented parsing of number of unique chirps * (determined by chirpEndIndx and chirpStartIndx) more than 32. */ /** * @brief Error Code: Not supported non complex ADC */ /** * @brief Error Code: Not supported non-16-bits ADC */ /** * @brief Error Code: Not supported non one numOfBurst in Advanced fram */ /** * @brief Error Code: Not supported negative frequency slope. */ /** * @brief Error Code: Not supported chirp threshold that is not divisible to number of chirps per frame. */ /** * @brief Error Code: Not supported non-complex ADC format. */ /** * @brief Error Code: Invalid input specified for num rx antennas. */ /** * @brief Error Code: Valid profileCfg not found for the given legacy frame or subframe */ /** @} */ /** * @brief RF parser's output parameters structure. * * \ingroup MMWDEMO_RFPARSER_EXTERNAL_DATA_STRUCTURE */ typedef struct MmwDemo_RFParserOutParams_t { /*! @brief valid Profile index */ uint8_t validProfileIdx; /*! @brief 1 if valid profile has one Tx per chirp else 0 */ uint8_t validProfileHasOneTxPerChirp; /*! @brief ADCBUF will generate chirp interrupt event every this many chirps - chirpthreshold */ uint8_t numChirpsPerChirpEvent; /*! @brief Number of ADC samples */ uint16_t numAdcSamples; /*! @brief Number of transmit antennas */ uint8_t numRxAntennas; /*! @brief Rx Antenna order */ uint8_t rxAntOrder[4U]; /*! @brief Tx Antenna order */ uint8_t txAntOrder[3U]; /*! @brief Number of transmit antennas */ uint8_t numTxAntennas; /*! @brief Number of virtual antennas */ uint8_t numVirtualAntennas; /*! @brief Number of virtual azimuth antennas */ uint8_t numVirtualAntAzim; /*! @brief Number of virtual elevation antennas */ uint8_t numVirtualAntElev; /*! @brief Number of range FFT bins, this is at a minimum the next power of 2 of @ref numAdcSamples. If range zoom is supported, this can be bigger than the minimum. */ uint16_t numRangeBins; /*! @brief Number of chirps per frame */ uint16_t numChirpsPerFrame; /*! @brief Number of bytes per RX channel, it is aligned to 16 bytes as required by ADCBuf driver */ uint32_t adcBufChanDataSize; /*! @brief Number of chirps for Doppler computation purposes. For example, in TDM/BPM-MIMO scheme, this is the physical chirps in a frame per transmit antenna i.e numDopplerChirps = @ref numChirpsPerFrame / @ref numTxAntennas */ uint16_t numDopplerChirps; /*! @brief Number of Doppler FFT bins, this is at a minimum the next power of 2 of @ref numDopplerChirps. If Doppler zoom is supported, this can be bigger than the minimum. */ uint16_t numDopplerBins; /*! @brief Range conversion factor for FFT range index to meters (based on @ref numRangeBins) */ float rangeStep; /*! @brief Doppler conversion factor for Doppler FFT index to m/s (based on @ref numDopplerBins) */ float dopplerStep; /*! @brief Range resolution in meters (based on @ref numAdcSamples) */ float rangeResolution; /*! @brief Doppler resolution in m/s (based on @ref numDopplerChirps) */ float dopplerResolution; /*! @brief Frame period in msec */ float framePeriod; /*! @brief Chirp interval (chirp ramp time + chirp idle time) in msec */ float chirpInterval; /*! @brief Center frequency of the chirp */ float centerFreq; } MmwDemo_RFParserOutParams; /*************************************************** * RFParserProc APIs ***************************************************/ extern int32_t MmwDemo_RFParser_parseConfig ( MmwDemo_RFParserOutParams *outParams, uint8_t subFrameIdx, MMWave_OpenCfg *openCfg, MMWave_CtrlCfg *ptrCtrlCfg, MmwDemo_ADCBufCfg *adcBufCfg, float rfFreqScaleFactor, _Bool bpmEnabled ); extern uint8_t MmwDemo_RFParser_getNumSubFrames(MMWave_CtrlCfg *ctrlCfg); /** * @file mmwdemo_monitor.h * * @brief * This is used to abstract the mmWave demo monitor definitions. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* mmWave SDK Include Files: */ /*********************************************************************************************** * Analog Monitor Defines ***********************************************************************************************/ /** * @brief * Millimeter Wave Demo analog monitor configuration * * @details * The structure contains the flags that select analog monitors * to be enabled. */ typedef struct MmwDemo_AnaMonitorCfg_t { /*! @brief Setting for Rx Saturation monitor */ uint8_t rxSatMonEn; /*! @brief Setting for signal & image band monitor */ uint8_t sigImgMonEn; } MmwDemo_AnaMonitorCfg; /** * @brief * Mmwave link analog monitor definition * * @details * Enumeration describes the mmwave supported analog monitors. */ typedef enum mmwDemo_AnaMonitor_e { MMWDEMO_ANALOG_MONITOR_TEMPERATURE = 0U, MMWDEMO_ANALOG_MONITOR_RX_GAIN_PHASE, MMWDEMO_ANALOG_MONITOR_RX_NOISE_FIGURE, MMWDEMO_ANALOG_MONITOR_IFSTAGE, MMWDEMO_ANALOG_MONITOR_TX0_POWER, MMWDEMO_ANALOG_MONITOR_TX1_POWER, MMWDEMO_ANALOG_MONITOR_TX2_POWER, MMWDEMO_ANALOG_MONITOR_TX0_BALLBREAK, MMWDEMO_ANALOG_MONITOR_TX1_BALLBREAK, MMWDEMO_ANALOG_MONITOR_TX2_BALLBREAK, MMWDEMO_ANALOG_MONITOR_TX_GAIN_PHASE_MISMATCH, MMWDEMO_ANALOG_MONITOR_TX0_BPM, MMWDEMO_ANALOG_MONITOR_TX1_BPM, MMWDEMO_ANALOG_MONITOR_TX2_BPM, MMWDEMO_ANALOG_MONITOR_SYNTH_FREQ, MMWDEMO_ANALOG_MONITOR_EXT_ANALOG_SIGNALS, MMWDEMO_ANALOG_MONITOR_INTERNAL_TX0_SIGNALS, MMWDEMO_ANALOG_MONITOR_INTERNAL_TX1_SIGNALS, MMWDEMO_ANALOG_MONITOR_INTERNAL_TX2_SIGNALS, MMWDEMO_ANALOG_MONITOR_INTERNAL_RX_SIGNALS, MMWDEMO_ANALOG_MONITOR_INTERNAL_PMCLKLO_SIGNALS, MMWDEMO_ANALOG_MONITOR_INTERNAL_GPADC_SIGNALS, MMWDEMO_ANALOG_MONITOR_PLL_CONTROL_VOLTAGE, MMWDEMO_ANALOG_MONITOR_DCC_CLOCK_FREQ, MMWDEMO_ANALOG_MONITOR_RX_SATURATION_DETECTOR, MMWDEMO_ANALOG_MONITOR_RX_SIG_IMG_BAND, MMWDEMO_ANALOG_MONITOR_RX_MIXER_INPUT_POWER, MMWDEMO_ANALOG_MONITOR_MAX }mmwDemo_AnaMonitor; /*********************************************************************************************** * Monitor API: Available in FULL configuration mode ***********************************************************************************************/ extern int32_t mmwDemo_cfgAnalogMonitor(MmwDemo_AnaMonitorCfg *ptrAnaMonCfg); extern int32_t mmwDemo_cfgRxSigImgMonitor( rlSigImgMonConf_t* ptrSigImgMonCfg); extern int32_t mmwDemo_cfgRxSaturationMonitor( rlRxSatMonConf_t* ptrRxSatMonCfg); /** * @file mmw_output.h * * @brief * This is the interface/message header file for the Millimeter Wave Demo * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @brief Output packet length is a multiple of this value, must be power of 2*/ /*! * @brief * Message types used in Millimeter Wave Demo for the communication between * target and host, and also for Mailbox communication * between MSS and DSS on the XWR18xx platform. Message types are used to indicate * different type detection information sent out from the target. * */ typedef enum MmwDemo_output_message_type_e { /*! @brief List of detected points */ MMWDEMO_OUTPUT_MSG_DETECTED_POINTS = 1, /*! @brief Range profile */ MMWDEMO_OUTPUT_MSG_RANGE_PROFILE, /*! @brief Noise floor profile */ MMWDEMO_OUTPUT_MSG_NOISE_PROFILE, /*! @brief Samples to calculate static azimuth heatmap */ MMWDEMO_OUTPUT_MSG_AZIMUT_STATIC_HEAT_MAP, /*! @brief Range/Doppler detection matrix */ MMWDEMO_OUTPUT_MSG_RANGE_DOPPLER_HEAT_MAP, /*! @brief Stats information */ MMWDEMO_OUTPUT_MSG_STATS, /*! @brief List of detected points */ MMWDEMO_OUTPUT_MSG_DETECTED_POINTS_SIDE_INFO, /*! @brief Samples to calculate static azimuth/elevation heatmap, (all virtual antennas exported) - unused in this demo */ MMWDEMO_OUTPUT_MSG_AZIMUT_ELEVATION_STATIC_HEAT_MAP, /*! @brief temperature stats from Radar front end */ MMWDEMO_OUTPUT_MSG_TEMPERATURE_STATS, MMWDEMO_OUTPUT_MSG_MAX } MmwDemo_output_message_type; /*! * @brief * Message header for reporting detection information from data path. * * @details * The structure defines the message header. */ typedef struct MmwDemo_output_message_header_t { /*! @brief Output buffer magic word (sync word). It is initialized to {0x0102,0x0304,0x0506,0x0708} */ uint16_t magicWord[4]; /*! brief Version: : MajorNum * 2^24 + MinorNum * 2^16 + BugfixNum * 2^8 + BuildNum */ uint32_t version; /*! @brief Total packet length including header in Bytes */ uint32_t totalPacketLen; /*! @brief platform type */ uint32_t platform; /*! @brief Frame number */ uint32_t frameNumber; /*! @brief Time in CPU cycles when the message was created. For XWR16xx/XWR18xx: DSP CPU cycles, for XWR14xx: R4F CPU cycles */ uint32_t timeCpuCycles; /*! @brief Number of detected objects */ uint32_t numDetectedObj; /*! @brief Number of TLVs */ uint32_t numTLVs; /*! @brief For Advanced Frame config, this is the sub-frame number in the range * 0 to (number of subframes - 1). For frame config (not advanced), this is always * set to 0. */ uint32_t subFrameNumber; } MmwDemo_output_message_header; /*! * @brief * Structure holds message stats information from data path. * * @details * The structure holds stats information. This is a payload of the TLV message item * that holds stats information. */ typedef struct MmwDemo_output_message_stats_t { /*! @brief Interframe processing time in usec */ uint32_t interFrameProcessingTime; /*! @brief Transmission time of output detection information in usec */ uint32_t transmitOutputTime; /*! @brief Interframe processing margin in usec */ uint32_t interFrameProcessingMargin; /*! @brief Interchirp processing margin in usec */ uint32_t interChirpProcessingMargin; /*! @brief CPU Load (%) during active frame duration */ uint32_t activeFrameCPULoad; /*! @brief CPU Load (%) during inter frame duration */ uint32_t interFrameCPULoad; } MmwDemo_output_message_stats; /** * @brief * Size of HSRAM Payload data array. */ /** * @brief * DSS stores demo output and stats in HSRAM. */ typedef struct MmwDemo_HSRAM_t { /*! @brief DPC execution result */ DPC_ObjectDetection_ExecuteResult result; /*! @brief Output message stats reported by DSS */ MmwDemo_output_message_stats outStats; /*! @brief Payload data of result */ uint8_t payload[(0x8000U - sizeof(DPC_ObjectDetection_ExecuteResult) - sizeof(MmwDemo_output_message_stats))]; } MmwDemo_HSRAM; /** * @brief * Message for reporting detected objects from data path. * * @details * The structure defines the message body for detected objects from from data path. */ typedef struct MmwDemo_output_message_tl_t { /*! @brief TLV type */ uint32_t type; /*! @brief Length in bytes */ uint32_t length; } MmwDemo_output_message_tl; /** * @file mmw_res.h * * @brief * Defines partitioning of hardware resources (HWA, EDMA etc) among the * DPCs and other components in the millimeter wave demo. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* DPUs */ /** * @file dopplerprochwa.h * * @brief * Implements Data path doppler processing functionality. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /* mmWave SDK Driver/Common Include Files */ /* DPIF Components Include Files */ /* mmWave SDK Data Path Include Files */ /** * @file dopplerproccommon.h * * @brief * Implements Common definition across dopplerProc DPU. * * \par * NOTE: * (C) Copyright 2018 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /************************************************************************** *************************** Include Files ******************************** **************************************************************************/ /* Standard Include Files. */ /*****************************************************************************/ /* stdlib.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.15\")") /* FreeBSD library requires code outside of the include guard */ _Pragma("CHECK_MISRA(\"-19.1\")") /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_stdlib.h if xlocale.h has already been included. This */ /* comes from FreeBSD's stdlib.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* The _TI_PROPRIETARY_PRAGMA macro exoands to a C99 _Pragma operator. */ /* The _Pragma statement is handled after the Pragma itself causing unexpected */ /* warnings due to the diagnostic state being popped. This is done to suppress */ /* unexpected 19.15 misra warnings. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /** @mainpage Doppler DPU * * This DPU implements the Doppler FFT (2D FFT). * * @section dopplerdpu_intro_section Doppler DPU * * Description * ---------------- * * This DPU expects as input the radar cube with 1D FFT data as described in @ref DPIF_RADARCUBE_FORMAT_1. * The output of this DPU is a detection matrix of format described in @ref DPIF_DETMATRIX_FORMAT_1. * These are the only formats supported by this DPU. * * The Doppler DPU is available in two distinct implementations: * * DPU Implementation | Runs on cores | Uses HWA * :---------------------|:----------------|:--------- * dopplerProcHWA | R4F or DSP | Yes * dopplerProcDSP | DSP | No *\n\n * @section doppler_hwa_dpu DopplerProcHWA * * Data from radar cube is moved into HWA memory using EDMA, * HWA performs the required computations and data is moved by EDMA from HWA internal memory to the detection matrix.\n\n * * The following figure shows a high level block diagram of the DPU implementation.\n * * @image html hwa_doppler_toplevel.png "HWA based Doppler DPU High Level block diagram" * * A list of resources required by this DPU is described in @ref DPU_DopplerProcHWA_HW_Resources_t. * In particular, the number of EDMA channels required is constant and does not depend on the DPU configuration. * On the other hand, the number of required HWA paramsets is a function of the number of TX antennas configured in * the data path as described in @ref DPU_DopplerProcHWA_HwaCfg_t.\n * * Besides the resources described above, other parameters required for the DPU configuration are listed * in @ref DPU_DopplerProcHWA_StaticConfig_t. * In particular, the DPU takes as input the number of Doppler chirps (numDopplerChirps), which does not * need to be a power of two. It produces a detection matrix of Doppler dimension equal to numDopplerBins * which must be a power of 2 greater or equal than numDopplerChirps. * Another DPU input is the number of range bins, which must be even but does not need to be a power of two.\n\n * * * Parameter | Restriction * :------------------|:-------------- * numDopplerChirps | None. * numDopplerBins | Must be power of two greater or equal than numDopplerChirps. * numRangeBins | Must be even. * * Below are details of the DPU implementation:\n * * EDMA is used to move data from the radar cube into the HWA internal memory and after processing is done * to move data from HWA internal memory to the detection matrix. * All 4 HWA memory banks are required by this DPU, regardless of the DPU configuration. In this document, the * HWA memory banks are called M0, M1, M2, M3.\n * * A ping/pong buffer scheme is used where:\n * * M0 and M2 are used for ping input/processing.\n * M1 and M3 are used for pong input/processing.\n * * In each iteration (ping/pong), a column of the radar cube matrix is brought into HWA for processing. * Such column consists of all samples for a fixed range, that is, all received virtual antennas for all * Doppler chirps for a fixed range bin.\n * * The steps below are executed by HWA on data (one column of the radar cube as described above) sitting * in its M memory. The description below is given for processing the ping buffer. * Pong buffer processing is identical to ping, except that M0 memory is replaced by M1 and M2 memory is replaced by M3.\n\n * * **Windowing**\n * Before FFT operation, input samples are multiplied by a window function. Window size and coefficients are * defined in @ref DPU_DopplerProcHWA_HwaCfg_t.\n * Window coefficients must be provided by application.\n\n * * **FFT and Log2|.|**\n * In this step 2D FFT and Log2 of the absolute value of each sample is computed. Input samples are in M0 * and output samples are in M2. Input sample is of type cmplx16ImRe_t and output is of type uint16_t. * This step also converts the number of input samples from N = numDopplerChirps * to a number of output samples K = numDopplerBins, which is the size of the Doppler FFT. * Both numDopplerBins and numDopplerChirps are input parameters for this DPU and numDopplerBins must be a power * of 2 greater or equal than numDopplerChirps. \n\n * * **Summation**\n * Summation of all virtual antennas is computed for each Doppler bin. \n * The output of the previous step (HWA Log2 magnitude) is in Q11 format. * The sum is done using FFT in HWA, the sum is obtained in the DC (0th) bin. * Input of the summation is on M2 and output is on M0. This FFT programming has srcScale of 3, meaning 3 * redundant bits (sign extension, in this case unsigned) are added to MSB and 5 LSBs are padded with 0, * so input before computation is in Q[11 + 5] format. The dstScale is set to 8, so summation output will * have 8-bits dropped, giving a result in Q[11 + 5 - 8] = Q8 format. The FFT size is the next power of 2 * of number of virtual antennas and the FFT is programmed to enable all butterfly scaling stages, hence the * FFT output will be 1/N' * sum(.), where N' = 2^Ceil(Log2(N)), where N = numVirtualAntennas. * The sum output which is input to CFAR is in Q8 format, so the CFAR threshold-scale * also needs to be in Q8 format. If CFAR threshold is originally intended to be expressed in dB * (say for user friendliness), then we need to do some translation before feeding to the CFAR * algorithm. This can be derived as follows: \n * Let N be the number of virtual antennas and N' = 2^ceil(log2(N)) * and user friendly CFAR threshold in dB is TdB (= 20*log10(|.|)). * CFAR needs to do in general: \n * CUT (Cell Under Test) = 1/N * sum(log10(|.|)) > TdB/20 + average of noise terms [similar looking to CUT on LHS] \n * Given log10(|.|) = log2(|.|)/log2(10), and further adjusting the terms to do computation similar to match what is the * sum output described above : \n * 2^8 * 1/ N' * sum(log2(|.|)) > TdB/20*log2(10)*2^8 * (N/N') + average of noise terms [similar looking to CUT on LHS] \n * So the CFAR threshold to be provided to the CFAR algorithm operating on this doppler DPU output is \n * T = 256 * TdB / 6 * N / N' * * Once the summation is computed for all Doppler bins, EDMA transfers the result from M0 to the detection matrix.\n\n * * **HWA memory bank size limitation**\n * The following 2 conditions must be satisfied for the parameters in this DPU configuration:\n * 4 x numRxAntennas x numTxAntennas x numDopplerChirps <= 16384\n * 2 x numRxAntennas x numTxAntennas x numDopplerBins <= 16384\n\n * * The reason for this limitation is as follows:\n * The size of the data that is brought in for processing in HWA (per ping/pong iteration) is a column of the radar cube. * The size of radar cube column is\n * 4 x numRxAntennas x numTxAntennas x numDopplerChirps (I),\n * where 4 bytes is sizeof(cmplx16ImRe_t), the sample size.\n * * After the 2D FFT and Log2|.| , we go from Doppler chirps to Doppler bins and from cmplx16ImRe_t to uint16_t. \n * * Therefore the size after 2D FFT and Log2|.| is\n * 2 x numRxAntennas x numTxAntennas x numDopplerBins (II),\n * where 2 bytes is sizeof(uint16_t).\n\n * * Both quantities above (I and II) should fit (independently) in one of the HWA M memory partitions * which has a size of 16KB.\n\n * * **Exported APIs**\n * DPU initialization is done through @ref DPU_DopplerProcHWA_init.\n\n * * DPU configuration is done by @ref DPU_DopplerProcHWA_config. The configuration can only be done after * the DPU has been initialized. The configuration parameters are described in @ref DPU_DopplerProcHWA_Config. \n\n * * The DPU is executed by calling @ref DPU_DopplerProcHWA_process. \n * This will trigger the first ping/pong EDMA transfers and from there on, the processing of the Doppler DPU for the * full radar cube is driven by hardware: EDMA will move data in and trigger HWA, which will process the data and * trigger EDMA to move data out (to detection matrix) and trigger next EDMA to move data in – and so on. All columns of the radar cube * matrix will be processed in this loop and no CPU intervention is needed. When HWA finishes processing all columns of the * radar cube it will generate an interrupt. When the last EDMA transfer to the detection matrix has landed, EDMA will generate * an interrupt. The DPU processing is done when both interrupts are received. * Both interrupts are depicted in green boxes in the figure below.\n\n * * * **Detailed block diagram for 3 TX 4 RX**\n * * The following figure depicts in detail the DPU implementation for the case of 3 TX and 4RX antennas. * The blue boxes connected by blue arrows represent different HWA paramsets.\n\n * * @image html hwa_doppler_fft.png "Doppler DPU implementation for 3 TX and 4 RX antennas" * * \n\n\n * @section dpu2 DopplerProcDSP * In this version of the Doppler DPU HWA is not used. All computation is done by the DSP.\n * Data from radar cube is moved into scratch memory using EDMA, * DSP performs the required computations and data is moved by EDMA from scratch memory to the detection matrix.\n\n * * The following figure shows a high level block diagram of the DPU implementation.\n * * @image html dsp_doppler_fft_toplevel.png "DSP Doppler DPU High Level block diagram" * * A list of resources required by this DPU is described in @ref DPU_DopplerProcDSP_HW_Resources_t. * In particular, the number of EDMA channels required is constant and does not depend on the DPU configuration. * * Besides the resources described above, other parameters required for the DPU configuration are listed * in @ref DPU_DopplerProcDSP_StaticConfig_t. * In particular, the DPU takes as input the number of Doppler chirps (numDopplerChirps), which does not * need to be a power of two but must be a multiple of 4. It produces a detection matrix of Doppler dimension equal to numDopplerBins * which must be a power of 2 greater or equal than numDopplerChirps. Also, due to restrictions on the FFT implementation by DSPLIB, * numDopplerBins must be at least 16. * * Parameter | Restriction * :------------------|:-------------- * numDopplerChirps | Must be a multiple of 4. * numDopplerBins | Must be at least 16. Must be power of two greater or equal than numDopplerChirps. * \n * Below are details of the DPU implementation:\n\n * * **Input data**\n * EDMA is used to move data from the radar cube into the DPU scratch buffers.\n * A ping/pong buffer scheme is used where in each iteration (ping/pong), data pertinent to one virtual antenna (for a fixed range bin) is brought * from the radar cube matrix for processing. \n * For a fixed range bin, the order in which the virtual antennas are processed must assure that BPM can be decoded * and all virtual antennas can be summed up. In order to achieve this goal with minimum temporary buffering of virtual * antennas data, the sequence of virtual antennas is processed in the following order:\n\n * 1) Next TX antennas for same range bin and same RX antenna. This assures that BPM can be decoded.\n * 2) Once 1 is exhausted for all TX antennas for a fixed range bin and fixed RX antenna, move to the next RX antenna * for the same range bin (to assure that the sum of all virtual antennas can be computed) and repeat 1.\n * 3) Once all virtual antennas for this range bin have been processed, move to the next range bin.\n\n * * Illustration of the ping/pong data pattern is shown in the next sections for the [3TX,4RX] and [2TX,4RX] cases.\n\n * * **Static Clutter Removal**\n * When Static Clutter Removal is enabled, the mean value of the input samples to the * Doppler FFT is subtracted from the samples.\n\n * * **Windowing**\n * Before FFT operation, input samples are multiplied by a real symmetric window function. Window size and coefficients are * defined in @ref DPU_DopplerProcDSP_HW_Resources_t. Window coefficients must be provided by application.\n * Note that the windowing function also executes IQ swap. Before windowing the samples are in the same format as in the radar cube, * which is cmplx16ImRe_t. After windowing the output is in cmplx32ReIm_t format.\n\n * * **FFT**\n * FFT is computed the output has numDopplerBins samples of type cmplx32ReIm_t.\n\n * * **BPM decoding**\n * If BPM is enabled, when the FFT output is available for the 2 TX antennas (for the same RX antenna and range bin), * BPM is decoded. More details on BPM implementation in the following section.\n\n * * **Log2|.|**\n * Log2 of the absolute value of each sample is computed and the output is a 16 bit number in Q8 format.\n\n * * **Summation and Output**\n * Accumulation is done for every Doppler bin for every virtual antenna. Note that before accumulating, each * factor in the sum is divided by 2^Ceil(Log2(numVirtualAntennas)). The purpose of doing this * is to have the same CFAR threshold scale interpretation between the HWA and DSP versions of the DPU, * this same interpretation allows for the convenience of configuring the same threshold scale * for a downstream CFAR algorithm whether operating on the HWA or the DSP version of the doppler DPU. * Refer to the description related to the conversion of CFAR threshold scale from user-friendly dB units * to what is required for CFAR algorithm under **Summation** section in @ref doppler_hwa_dpu \n * Once all virtual antennas are processed for a given range bin, the accumulated array is transferred by * EDMA to the detection matrix.\n\n * * **Detailed block diagram for 3 TX 4 RX TDM-MIMO (no BPM)**\n * * The following figure depicts in detail the DPU implementation for the case of 3 TX and 4RX antennas (no BPM). * * @image html dsp_doppler_fft_3TX_4RX.png "Doppler DPU implementation for 3 TX and 4 RX antennas" * * * The following picture illustrates the ping/pong pattern for the case of 3 TX and 4 RX antennas. * @image html dsp_doppler_fft_3TX_4RX_pingpong.png "Ping/pong pattern for the case of 3 TX and 4 RX antennas" * * * @subsection doppler_bpmCfgNotes BPM Scheme * Similar to TDM-MIMO, in BPM scheme a frame consists of multiple blocks, each * block consisting of 2 chirp intervals. However, unlike in TDM-MIMO where only * one TX antenna active per chirp interval, two TX antennas are active in each * chirp interval. This DPU only supports a BPM scheme with two * TX antennas say A and B. In the even time slots (0, 2,...), both transmit antennas * should be configured to transmit with positive phase i.e * @verbatim (A,B) = (+,+) @endverbatim * In the odd time slots (1, 3,...), the transmit antennas should be configured to * transmit with phase\n * @verbatim (A,B) = (+,-) @endverbatim * The BPM scheme is shown in the figure below where TX0 is used as antenna A and TX1 as * antenna B. * * @image html bpm_antenna_cfg.png "BPM Scheme Antenna configuration" * * **BPM decoding**\n * Let S1 and S2 represent chirp signals from two TX antennas. In time slot zero * a combined signal Sa=S1+S2 is transmitted. Similarly in time slot one a * combined signal Sb=S1-S2 is transmitted. Using the corresponding received signals, * (S'a and S'b), at a specific received RX antenna, the components from the individual * transmitters are separated out using\n * @verbatim S'1=(S'a+S'b)/2 @endverbatim * and * @verbatim S'2=(S'a-S'b)/2 @endverbatim * With simultaneous transmission on both TX antennas the total transmitted power per * chirp interval is increased, and it can be shown that this translates to an SNR * improvement of 3dB.\n * * **Order of the TX antennas in the BPM scheme**\n * The BPM decoding will produce the virtual antenna * array in the order (A, B), not (B, A), which will be used for AoA processing. * Therefore, user must make sure that the (A, B) mapping to the physical transmit antennas * corresponds to the intended virtual antenna order. * For example, take the 6843 EVM antenna arrangement as shown in the figure below. * Note that the DPU indexes the TX antennas as (TX0, TX1, TX2) which corresponds * in the device to (TX1, TX2, TX3). \n * * @image html coordinate_geometry_6843.png "6843 EVM antenna arrangement" * * Here two antennas TX1 and TX3 can create a virtual array of 8 antennas in the azimuth direction. * In order to ensure correct virtual antenna processing for AoA calculations, after BPM decoding, * the TX1 virtual antennas should precede the TX3 because the direction of spatial progression of * RX antennas matches the direction of spatial progression of TX antennas when TX1 is before TX3 * (post BPM decoding, the result should essentially be like TDM-MIMO). Therefore A=TX1 and B=TX3. * In other words, BPM must be configured to do\n * @verbatim (TX1,TX3) = (+,+) in even slots @endverbatim * and\n * @verbatim (TX1,TX3) = (+,-) in odd slots @endverbatim * The opposite arrangement i.e\n * @verbatim (TX3,TX1) = (+,+) in even slots @endverbatim * and\n * @verbatim (TX3,TX1) = (+,-) in odd slots @endverbatim * will not work.\n\n * * @subsection doppler_bpmNotes Doppler DPU changes when BPM is enabled * When BPM is enabled the following changes are done in the Doppler DPU processing:\n * Doppler compensation and BPM decoding are done after the Doppler FFT. * Note that the decoded data is not stored in the radar cube, therefore * BPM decoding needs to be done again (on a much smaller set of samples) * during the direction of arrival computation. * The following figure shows the required changes in the Doppler processing. * When BPM is enabled the fftOutBuf buffer is doubled in size to accommodate both Ping (TX0+TX1) * and Pong (TX0-TX1) so that BPM can be decoded. The decoded data is written back to the fftOutBuf. * * @image html dsp_doppler_fft_2TX_4RX_BPM.png "Doppler DPU implementation for 2 TX and 4 RX antennas and BPM enabled" * \n\n * The following picture shows the ping/pong pattern for the case of 2 TX and 4 RX antennas (regardless if BPM is enabled or not). * @image html dsp_doppler_fft_2TX_4RX_BPM_pingpong.png "Ping/pong pattern for the case of 2 TX and 4 RX antennas" * * **Exported APIs**\n * DPU initialization is done through @ref DPU_DopplerProcDSP_init.\n\n * * DPU configuration is done by @ref DPU_DopplerProcDSP_config. The configuration can only be done after * the DPU has been initialized. The configuration parameters are described in @ref DPU_DopplerProcDSP_Config. \n\n * * The DPU is executed by calling @ref DPU_DopplerProcDSP_process. \n * * */ /** @defgroup DPU_DOPPLERPROC_EXTERNAL_FUNCTION dopplerProc DPU External Functions @ingroup DOPPLER_PROC_DPU @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the dopplerProc DPU */ /** @defgroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE dopplerProc DPU External Data Structures @ingroup DOPPLER_PROC_DPU @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup DPU_DOPPLERPROC_ERROR_CODE dopplerProc DPU Error Codes @ingroup DOPPLER_PROC_DPU @brief * The section has a list of all the error codes which are generated by the dopplerProc DPU */ /** @defgroup DPU_DOPPLERPROC_INTERNAL_FUNCTION dopplerProc DPU Internal Functions @ingroup DOPPLER_PROC_DPU @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup DPU_DOPPLERPROC_INTERNAL_DATA_STRUCTURE dopplerProc DPU Internal Data Structures @ingroup DOPPLER_PROC_DPU @brief * The section has a list of all internal data structures which are used internally * by the dopplerProc DPU module. */ /** @defgroup DPU_DOPPLERPROC_INTERNAL_DEFINITION dopplerProc DPU Internal Definitions @ingroup DOPPLER_PROC_DPU @brief * The section has a list of all internal definitions which are used internally * by the dopplerProc DPU. */ /** * @brief * dopplerProc DPU EDMA configuration parameters * * @details * The structure is used to hold the EDMA configuration parameters * for the Doppler Processing DPU * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProc_Edma_t { /*! @brief EDMA Ping channel. */ DPEDMA_ChanCfg ping; /*! @brief EDMA Pong channel. */ DPEDMA_ChanCfg pong; }DPU_DopplerProc_Edma; /** * @brief * dopplerProc DPU statistics * * @details * The structure is used to hold the statistics of the DPU * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProc_Stats_t { /*! @brief total number of DPU processing */ uint32_t numProcess; /*! @brief For HWA version of the DPU: total processing time including EDMA transfers.\n For DSP version of the DPU: total processing time excluding EDMA transfers.*/ uint32_t processingTime; /*! @brief time spent waiting for EDMA transfers. Valid only for DSP version of DPU.*/ uint32_t waitTime; }DPU_DopplerProc_Stats; /** @addtogroup DPU_DOPPLERPROC_ERROR_CODE * Base error code for the dopplerProc DPU is defined in the * \include ti/datapath/dpif/dp_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: DPU is in progress */ /** * @brief Error Code: Out of HWA resources */ /** * @brief Error Code: Semaphore creation failed */ /** * @brief Error Code: Bad semaphore status */ /** * @brief Error Code: Configure parameters exceed HWA memory bank size */ /** * @brief Error Code: Unsupported radar cube format */ /** * @brief Error Code: Unsupported detection matrix format */ /** * @brief Error Code: Insufficient detection matrix size */ /** * @brief Error Code: Wrong window size */ /** @} */ /** * @brief Maximum number of HWA paramsets used by DPU. * Computed as follows:\n * (1 for each TX antenna + 1 for sum) * 2 (ping/pong) = 8 */ /** * @brief Number of HWA memory banks needed */ /** * @brief Disables first butterfly stage scaling */ /** * @brief Enables first butterfly stage scaling */ /*! * @brief Handle for Doppler Processing DPU. */ typedef void* DPU_DopplerProcHWA_Handle; /** * @brief * dopplerProc DPU initial configuration parameters * * @details * The structure is used to hold the DPU initial configurations. * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_InitCfg_t { /*! @brief HWA Handle */ HWA_Handle hwaHandle; }DPU_DopplerProcHWA_InitParams; /** * @brief * dopplerProc DPU HWA configuration parameters * * @details * The structure is used to hold the HWA configuration parameters * for the Doppler Processing DPU * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_HwaCfg_t { /*! @brief Indicates if HWA window is symmetric or non-symmetric. Use HWA macro definitions for symmetric/non-symmetric. */ uint8_t winSym; /*! @brief Doppler FFT window size in bytes. This is the number of coefficients to be programmed in the HWA for the windowing functionality. The size is a function of numDopplerChirps as follows:\n If non-symmetric window is selected: windowSize = numDopplerChirps * sizeof(int32_t) \n If symmetric window is selected and numDopplerChirps is even: windowSize = numDopplerChirps * sizeof(int32_t) / 2 \n If symmetric window is selected and numDopplerChirps is odd: windowSize = (numDopplerChirps + 1) * sizeof(int32_t) / 2 */ uint32_t windowSize; /*! @brief Pointer to Doppler FFT window coefficients. */ int32_t *window; /*! @brief HWA window RAM offset in number of samples. */ uint32_t winRamOffset; /*! @brief Indicates if HWA should enable butterfly scaling (divide by 2) of the first radix-2 stage. Depending on the window definition, user may want to skip the first stage scaling in order to avoid signal degradation.\n Options are:\n Disable first stage scaling: firstStageScaling = @ref DPU_DOPPLERPROCHWA_FIRST_SCALING_DISABLED \n Enable first stage scaling: firstStageScaling = @ref DPU_DOPPLERPROCHWA_FIRST_SCALING_ENABLED \n Note: All other butterfly stages have the scaling enabled. This option applies only for the first stage.\n */ uint8_t firstStageScaling; /*! @brief Number of HWA paramsets reserved for the Doppler DPU. The number of HWA paramsets required by this DPU is a function of the number of TX antennas used in the configuration:\n numParamSets = 2 x (Number of TX antennas) + 2\n The DPU will use numParamSets consecutively, starting from paramSetStartIdx.\n */ uint8_t numParamSets; /*! @brief HWA paramset Start index. Application has to ensure that paramSetStartIdx is such that \n [paramSetStartIdx, paramSetStartIdx + 1, ... (paramSetStartIdx + numParamSets - 1)] \n is a valid set of HWA paramsets.\n */ uint32_t paramSetStartIdx; }DPU_DopplerProcHWA_HwaCfg; /** * @brief * dopplerProc DPU EDMA configuration parameters * * @details * The structure is used to hold the EDMA configuration parameters * for the Doppler Processing DPU * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_EdmaCfg_t { /*! @brief EDMA driver handle. */ EDMA_Handle edmaHandle; /*! @brief EDMA configuration for Input data (Radar cube -> HWA memory). */ DPU_DopplerProc_Edma edmaIn; /*! @brief EDMA configuration for Output data (HWA memory -> detection matrix). */ DPU_DopplerProc_Edma edmaOut; /*! @brief EDMA configuration for hot signature. */ DPU_DopplerProc_Edma edmaHotSig; }DPU_DopplerProcHWA_EdmaCfg; /** * @brief * Doppler DPU HW configuration parameters * * @details * The structure is used to hold the HW configuration parameters * for the Doppler DPU * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_HW_Resources_t { /*! @brief EDMA configuration */ DPU_DopplerProcHWA_EdmaCfg edmaCfg; /*! @brief HWA configuration */ DPU_DopplerProcHWA_HwaCfg hwaCfg; /*! @brief Radar Cube */ DPIF_RadarCube radarCube; /*! @brief Detection matrix */ DPIF_DetMatrix detMatrix; }DPU_DopplerProcHWA_HW_Resources; /** * @brief * Doppler DPU static configuration parameters * * @details * The structure is used to hold the static configuration parameters * for the Doppler DPU. The following conditions must be satisfied: * * @verbatim numTxAntennas * numRxAntennas * numDopplerChirps * sizeof(cmplx16ImRe_t) <= 16 KB (one HWA memory bank) numTxAntennas * numRxAntennas * numDopplerBins * sizeof(uint16_t) <= 16 KB (one HWA memory bank) @endverbatim * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_StaticConfig_t { /*! @brief Number of transmit antennas */ uint8_t numTxAntennas; /*! @brief Number of receive antennas */ uint8_t numRxAntennas; /*! @brief Number of virtual antennas */ uint8_t numVirtualAntennas; /*! @brief Number of range bins */ uint16_t numRangeBins; /*! @brief Number of Doppler chirps. */ uint16_t numDopplerChirps; /*! @brief Number of Doppler bins */ uint16_t numDopplerBins; /*! @brief Log2 of number of Doppler bins */ uint8_t log2NumDopplerBins; }DPU_DopplerProcHWA_StaticConfig; /** * @brief * dopplerProc DPU configuration parameters * * @details * The structure is used to hold the configuration parameters * for the Doppler Processing removal DPU * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_Config_t { /*! @brief HW resources. */ DPU_DopplerProcHWA_HW_Resources hwRes; /*! @brief Static configuration. */ DPU_DopplerProcHWA_StaticConfig staticCfg; }DPU_DopplerProcHWA_Config; /** * @brief * DPU processing output parameters * * @details * The structure is used to hold the output parameters DPU processing * * \ingroup DPU_DOPPLERPROC_EXTERNAL_DATA_STRUCTURE */ typedef struct DPU_DopplerProcHWA_OutParams_t { /*! @brief DPU statistics */ DPU_DopplerProc_Stats stats; }DPU_DopplerProcHWA_OutParams; DPU_DopplerProcHWA_Handle DPU_DopplerProcHWA_init(DPU_DopplerProcHWA_InitParams *initCfg, int32_t* errCode); int32_t DPU_DopplerProcHWA_process(DPU_DopplerProcHWA_Handle handle, DPU_DopplerProcHWA_OutParams *outParams); int32_t DPU_DopplerProcHWA_deinit(DPU_DopplerProcHWA_Handle handle); int32_t DPU_DopplerProcHWA_config(DPU_DopplerProcHWA_Handle handle, DPU_DopplerProcHWA_Config *cfg); /******************************************************************************* * Resources for Object Detection DPC, currently the only DPC and hwa/edma * resource user in the demo. *******************************************************************************/ /* EDMA instance used*/ /* Range DPU */ /* Doppler DPU */ /* Static Clutter DPU */ /* CFARCA DPU */ /* AOA DPU */ /* INTR_15 to INTR_18 are among those not presently used in the system, * hence use it for general purpose, note an actual event coming on these * will not falsely trigger the EDMA. */ /* Event queues PING path */ /* Event queues PONG path */ /* EDMA physical channels tied to HWA output events */ /* EDMA general physical channels */ /* EDMA Param sets */ /*************************LVDS streaming EDMA resources*******************************/ /*EDMA instance used*/ /* CBUFF EDMA trigger channels */ /* HW Session*/ /* SW Session*/ /*shadow*/ /*shadow CBUFF trigger channels*/ /* HW Session*/ /* SW Session*/ /*************************LVDS streaming EDMA resources END*******************************/ /** * @file mmw_mss.h * * @brief * This is the main header file for the Millimeter Wave Demo * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /* * Do not modify this file; it is automatically * generated and any modifications will be overwritten. * * @(#) xdc-E00 */ /* * ======== GENERATED SECTIONS ======== * * PROLOGUE * INCLUDES * * CREATE ARGS * INTERNAL DEFINITIONS * MODULE-WIDE CONFIGS * PER-INSTANCE TYPES * FUNCTION DECLARATIONS * SYSTEM FUNCTIONS * * EPILOGUE * STATE STRUCTURES * PREFIX ALIASES */ /* * ======== PROLOGUE ======== */ /* * ======== STATE STRUCTURES ======== */ /* * ======== PREFIX ALIASES ======== */ /** * @file mmw_lvds_stream.h * * @brief * LVDS stream header file. * * \par * NOTE: * (C) Copyright 2019 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** * @file cbuff.h * * @brief * This is the header file for the CBUFF driver which exposes the * data structures and exported API which can be used by the * applications to use the CBUFF driver. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage CBUFF Driver * * The CBUFF (Common Buffer Controller) is responsible for the transfer * of data from multiple sources like ADCBUFF, Chirp Parameters (CP), * Chirp Quality (CQ) or any other source to the LVDS Tx or CSI2 Module. * * The CBUFF header file should be included in an application as follows: * @code #include @endcode * * ## Customizing the driver # * * The default driver library fully supports the following data modes:- * - Interleaved * - Non-Interleaved * * The default library may not include all formats that the code supports. * To see what formats are supported, refer to the following tables in * device platform file (platform/cbuff_\.c), entries marked NULL are not * supported. Users can modify these tables to support their choice of formats * and rebuild the library. These tables thus allow memory footprint * to scale based on desired set of formats. * - @sa gInterleavedTransferFxn * - @sa gNonInterleavedTransferFxn * - @sa gMultipleChirpNonInterleavedTransferFxn (on some devices) * * ## Sessions # * * The CBUFF driver introduces a concept called sessions. Sessions are created during * application startup. Sessions will allocate the required EDMA channels and will setup * a virtualized CBUFF linked list to support the data format which is being streamed out. * * Sessions can be executed by Hardware or Software triggers. The ADC data being available * is a hardware trigger which will kick start the transfers without any software * intervention. On the other hand software triggered sessions need to be triggered by * the CBUFF Driver API * * In order for the sessions to coexist only one of the sessions can be active at a time. * Applications can register a frame done callback function which is invoked once * the transfer associated with the session is complete. This can be used to switch from * one active session to another. It is the responsiblity of the application to guarantee * that the transfers in the sessions do not overlap. * * @sa CBUFF_activateSession @sa CBUFF_deactivateSession */ /** @defgroup CBUFF_DRIVER CBUFF Driver */ /** * @file csi.h * * @brief * This is the header file for the CSI driver which exposes the * data structures and exported API which can be used by the * applications to use the CSI driver. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage CSI Driver * * The CSI Driver provides support for a high speed interface which allows * the data to be transferred out of the XWR14xx to another device. The CSI * driver works in conjunction with the CBUFF Driver. * * The CSI header file should be included in an application as follows: * @code #include @endcode * * The CSI Driver exposes the following register definition files: * - CSI Phy Module : csi/include/reg_dsiphy.h * - CSI Protocol Engine: csi/include/reg_dsiproteng.h * * ## Initializing the PHY Parameters # * The CSI driver exposes an API CSI_phyParamsInit() which is used to setup and * initialize the PHY Parameters to the default values. However it is possible * that the applications would want to change these parameters from the default * values as per their use case. * * ## Initializing the driver # * The CSI driver can be initialized using the CSI_open() API. The CSI driver * is only used in conjunction with the CBUFF module. * * ## Closing the driver # * The CSI driver can be closed using the CSI_close() API. Please ensure that the * CBUFF driver is closed before closing down the CSI driver. */ /** @defgroup CSI_DRIVER CSI Driver */ /** @defgroup CSI_DRIVER_EXTERNAL_FUNCTION CSI Driver External Functions @ingroup CSI_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup CSI_DRIVER_EXTERNAL_DATA_STRUCTURE CSI Driver External Data Structures @ingroup CSI_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup CSI_DRIVER_ERROR_CODE CSI Driver Error Codes @ingroup CSI_DRIVER @brief * The section has a list of all the error codes which are generated by the CSI Driver * module */ /** @defgroup CSI_DRIVER_INTERNAL_FUNCTION CSI Driver Internal Functions @ingroup CSI_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup CSI_DRIVER_INTERNAL_DATA_STRUCTURE CSI Driver Internal Data Structures @ingroup CSI_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the CSI module. */ /** @addtogroup CSI_DRIVER_ERROR_CODE * Base error code for the CSI module is defined in the * \include ti/common/mmwave_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Operation cannot be implemented because the CSI driver * is in use */ /** @} */ /** @addtogroup CSI_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief * CSI Driver Handle */ typedef void* CSI_Handle; /** * @brief * FIFO Arbiteration Mode * * @details * Enumeration which describes the FIFO Arbiteration mode */ typedef enum CSI_FIFO_Arbiteration_e { /** * @brief Round Robin: This indicates that the FIFO is serviced starting * from the lowest enabled virtual channel identifier */ CSI_FIFO_Arbiteration_RR = 0x0, /** * @brief Sequential: This indicates that the all pending requests from * a virtual channel are processed before moving to the next channel. */ CSI_FIFO_Arbiteration_SEQ }CSI_FIFO_Arbiteration; /** * @brief * CSI virtual channel * * @details * Enumeration which describes the CSI virtual channels */ typedef enum CSI_VirtualCh_e { /** * @brief Virtual Channel 0 */ CSI_VirtualCh_CH0 = 0, /** * @brief Virtual Channel 1 */ CSI_VirtualCh_CH1 = 1, /** * @brief Virtual Channel 2 */ CSI_VirtualCh_CH2 = 2, /** * @brief Virtual Channel 3 */ CSI_VirtualCh_CH3 = 3, /** * @brief Maximum number of virtual channels supported */ CSI_VirtualCh_MAX_CHANNEL = 4, /** * @brief Invalid channel */ CSI_VirtualCh_INVALID = 0xFF, }CSI_VirtualCh; /** * @brief * Virtual Channel FIFO Size * * @details * Enumeration which describes the size of the FIFO used by * the virtual channels. */ typedef enum CSI_VC_FIFO_Size_e { /** * @brief FIFO Size is 0*33 bits. */ CSI_VC_FIFO_Size_0 = 0, /** * @brief FIFO Size is 32*33 bits. */ CSI_VC_FIFO_Size_32, /** * @brief FIFO Size is 64*33 bits. */ CSI_VC_FIFO_Size_64, /** * @brief FIFO Size is 96*33 bits. */ CSI_VC_FIFO_Size_96, /** * @brief FIFO Size is 128*33 bits. */ CSI_VC_FIFO_Size_128 }CSI_VC_FIFO_Size; /** * @brief * CSI Data Rates * * @details * Enumeration which describes the data rates supported by the CSI interface. * * Please note that the definitions have changed in SDK 2.1/newer releases. * Old definitions seemed to imply data rate when it was really the HSClk * rate which was twice the data rate * The mapping from old values to new values is given below * * Defines in SDK 2.0/older Equivalent defines in SDK 2.1/newer * (this was actually This is true datarate=[old_define]/2 * HSICLK_xxxMhz) * ------------------------ ------------------------------------ * CSI_DataRate_1200Mhz CSI_DataRate_600Mbps * CSI_DataRate_900Mhz CSI_DataRate_450Mbps * CSI_DataRate_600Mhz CSI_DataRate_300Mbps * CSI_DataRate_450Mhz CSI_DataRate_225Mbps * CSI_DataRate_400Mhz [invalid/not supported] * CSI_DataRate_300Mhz CSI_DataRate_150Mbps * CSI_DataRate_225Mhz [invalid/not supported] * [No definition] CSI_DataRate_400Mbps * * Old definitions in user code will result in compilation error * and user should use the above mapping table to find the new * definition corresponding to the old one and use that in their code */ typedef enum CSI_DataRate_e { /** * @brief Data rate is 600Mbps */ CSI_DataRate_600Mbps = 0x1, /** * @brief Data rate is 450Mbps */ CSI_DataRate_450Mbps, /** * @brief Data rate is 400Mbps */ CSI_DataRate_400Mbps, /** * @brief Data rate is 300Mbps */ CSI_DataRate_300Mbps, /** * @brief Data rate is 225Mbps */ CSI_DataRate_225Mbps, /** * @brief Data rate is 150Mbps */ CSI_DataRate_150Mbps }CSI_DataRate; /** * @brief * CSI Virtual Channel Configuration * * @details * The structure describes the configuration which needs to be specified * in order to create a virtual channel. */ typedef struct CSI_VirtualChannelCfg_t { /** * @brief Virtual channel id */ CSI_VirtualCh channelId; /** * @brief Receive FIFO Size */ CSI_VC_FIFO_Size rxFIFOSize; /** * @brief Transmit FIFO Size */ CSI_VC_FIFO_Size txFIFOSize; }CSI_VirtualChannelCfg; /** * @brief * CSI Phy Parameters * * @details * The structure describes the configuration for the PHY registers. This * is an advanced configuration feature which is available and can be used * by application developers to trim the CSI PHY. * * @sa CSI_phyParamsInit */ typedef struct CSI_PhyParams_t { /** * @brief CSI PHY Registers */ uint32_t phyRegister[16]; }CSI_PhyParams; /** * @brief * CSI Configuration * * @details * The structure describes the configuration information which is needed * to initialize and setup the CSI Driver. */ typedef struct CSI_Cfg_t { /** * @brief SOC Handle used to enable the CSI */ SOC_Handle socHandle; /** * @brief FIFO arbiteration mode */ CSI_FIFO_Arbiteration fifoArbiteration; /** * @brief Data Rate */ CSI_DataRate dataRate; /** * @brief CSI PHY Parameters which can be overwritten by application developers * to trim the PHY values. * * The PHY parameters can be set to the default values using the following API: * @sa CSI_phyParamsInit */ CSI_PhyParams phyParams; /** * @brief Virtual channel configuration: This is a table which specifies all the * virtual channels which need to be configured. If the channel id in the configuration * is set to an invalid value the configuration for the channel is skipped. */ CSI_VirtualChannelCfg virtualChannelCfg[CSI_VirtualCh_MAX_CHANNEL]; }CSI_Cfg; /** @} */ /******************************************************************************************************* * CSI Exported API: *******************************************************************************************************/ extern CSI_Handle CSI_open(CSI_Cfg* ptrCfg, int32_t* errCode); extern int32_t CSI_close (CSI_Handle csiHandle, int32_t* errCode); extern int32_t CSI_phyParamsInit (CSI_DataRate dataRate, CSI_PhyParams* ptrPhyParams); /** @defgroup CBUFF_DRIVER_EXTERNAL_FUNCTION CBUFF Driver External Functions @ingroup CBUFF_DRIVER @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the driver */ /** @defgroup CBUFF_DRIVER_EXTERNAL_DATA_STRUCTURE CBUFF Driver External Data Structures @ingroup CBUFF_DRIVER @brief * The section has a list of all the data structures which are exposed to the application */ /** @defgroup CBUFF_DRIVER_EXTERNAL_DEFINITION CBUFF Driver External Definition @ingroup CBUFF_DRIVER @brief * The section has a list of all the exported definitions */ /** @defgroup CBUFF_DRIVER_ERROR_CODE CBUFF Driver Error Codes @ingroup CBUFF_DRIVER @brief * The section has a list of all the error codes which are generated by the CBUFF Driver * module */ /** @defgroup CBUFF_DRIVER_INTERNAL_FUNCTION CBUFF Driver Internal Functions @ingroup CBUFF_DRIVER @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup CBUFF_DRIVER_INTERNAL_DATA_STRUCTURE CBUFF Driver Internal Data Structures @ingroup CBUFF_DRIVER @brief * The section has a list of all internal data structures which are used internally * by the CBUFF module. */ /** @addtogroup CBUFF_DRIVER_ERROR_CODE * Base error code for the CBUFF module is defined in the * \include ti/common/mmwave_error.h @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Out of memory */ /** * @brief Error Code: Operation cannot be implemented because the CBUFF driver * is in use */ /** * @brief Error Code: Operation cannot be implemented because the CBUFF driver * is not supporting this currently */ /** * @brief Error Code: The application failed to provide the EDMA resources * which are required by the CBUFF driver to support the application use case */ /** * @brief Error Code: Limit exceeded */ /** @} */ /** @addtogroup CBUFF_DRIVER_EXTERNAL_DEFINITION @{ */ /** * @brief Maximum number of user supplied data buffers which can be configured * and sent over the interface */ /** * @brief Maximum number of sessions which can be supported * by the CBUFF Driver. * * *NOTE*: This is limited to the number of DMA channels available * to the CBUFF IP. */ /** @} */ /** @addtogroup CBUFF_DRIVER_EXTERNAL_DATA_STRUCTURE @{ */ /** * @brief * Opaque handle to the CBUFF Driver */ typedef void* CBUFF_Handle; /** * @brief * Opaque handle to the CBUFF Session */ typedef void* CBUFF_SessionHandle; /** * @brief * High Speed Interface * * @details * The enumeration describes the high speed interface which is to be used * by the CBUFF to send out the data */ typedef enum CBUFF_Interface_e { /** * @brief The CBUFF driver will send out the packets using the CSI Interface */ CBUFF_Interface_CSI = 0x1, /** * @brief The CBUFF driver will send out the packets using the LVDS Interface */ CBUFF_Interface_LVDS }CBUFF_Interface; /** * @brief * CBUFF Command * * @details * The enumeration describes commands which are used to get/set information * from the CBUFF Driver * * @sa * CBUFF_control */ typedef enum CBUFF_Command_e { /** * @brief The command is used to get the statistics associated with the * CBUFF driver. While using this command in the CBUFF_control API; * please ensure the following:- * arg = &CBUFF_Stats * argLen = sizeof(CBUFF_Stats) * @sa CBUFF_Stats */ CBUFF_Command_GET_CBUFF_STATS = 0x1, /** * @brief The command is used to clear the statistics associated with the * CBUFF driver. While using this command in the CBUFF_control API; * please ensure the following:- * arg = NULL * argLen = 0 */ CBUFF_Command_CLEAR_CBUFF_STATS, /** * @brief The command is used to get the current active session in the CBUFF * Driver. While using this command in the CBUFF_control API; * please ensure the following:- * arg = &CBUFF_SessionHandle * argLen = sizeof(CBUFF_SessionHandle) * * If session handle is marked as NULL it implies that there was no active session * in the CBUFF driver. */ CBUFF_Command_GET_ACTIVE_SESSION }CBUFF_Command; /** * @brief * Output Data Format * * @details * The enumeration describes the LVDS/CSI2 output data format. */ typedef enum CBUFF_OutputDataFmt_e { /** * @brief 12bit output format */ CBUFF_OutputDataFmt_12bit = 0x0, /** * @brief 14bit output format */ CBUFF_OutputDataFmt_14bit, /** * @brief 16bit output format */ CBUFF_OutputDataFmt_16bit }CBUFF_OutputDataFmt; /** * @brief * Data Format * * @details * The enumeration describes the data format. */ typedef enum CBUFF_DataFmt_e { /** * @brief Only ADC Data is to sent out */ CBUFF_DataFmt_ADC_DATA = 0x0, /** * @brief Chirp Parameters + ADC Data */ CBUFF_DataFmt_CP_ADC, /** * @brief ADC Data + Chirp Parameters */ CBUFF_DataFmt_ADC_CP, /** * @brief Chirp Parameters + ADC Data + Chirp Quality */ CBUFF_DataFmt_CP_ADC_CQ, /** * @brief ADC + User Data */ CBUFF_DataFmt_ADC_USER, /** * @brief Chirp Parameters + ADC Data + Chirp Quality + User Data */ CBUFF_DataFmt_CP_ADC_CQ_USER, /** * @brief Maximum Data format value. */ CBUFF_DataFmt_MAX }CBUFF_DataFmt; /** * @brief * Data Type * * @details * The enumeration describes the data type */ typedef enum CBUFF_DataType_e { /** * @brief Real Data */ CBUFF_DataType_REAL = 0x0, /** * @brief Complex Data */ CBUFF_DataType_COMPLEX }CBUFF_DataType; /** * @brief * CBUFF Operational Mode * * @details * The enumeration describes the operational mode for the CBUFF */ typedef enum CBUFF_OperationalMode_e { /** * @brief The CBUFF sends out the data on the High speed interface * based on the number of chirps. */ CBUFF_OperationalMode_CHIRP = 0x1, /** * @brief The CBUFF sends out the data on the High speed interface * based on the threshold. This is only supported on LVDS. */ CBUFF_OperationalMode_CONTINUOUS }CBUFF_OperationalMode; /** * @brief * LVDS Lane Format Map * * @details * The enumeration describes the LVDS Lane Format maps which are available * and which need to be used. */ typedef enum CBUFF_LVDSLaneFmtMap_e { /** * @brief Use the LVDS Lane Format-0 */ CBUFF_LVDSLaneFmtMapLANEx_FMT_0_y = 0U, /** * @brief Use the LVDS Lane Format-1 */ CBUFF_LVDSLaneFmtMapLANEx_FMT_1_y }CBUFF_LVDSLaneFmtMap; /** * @brief * Data Storage Mode * * @details * The enumeration describes the storage mode in which the data is stored * in the ADC Buffer. */ typedef enum CBUFF_DataMode_e { /** * @brief Data is stored in interleaved mode. This implies that sample of * each receive channel is stored one after another. */ CBUFF_DataMode_INTERLEAVED = 0, /** * @brief Data is stored in non-interleaved mode. This implies that all the * samples of a receive channel are grouped together. */ CBUFF_DataMode_NON_INTERLEAVED }CBUFF_DataMode; /** * @brief * Header Mode * * @details * The enumeration describes the header mode. The CBUFF driver can add headers * to the data before it is sent out over the CSI/LVDS. */ typedef enum CBUFF_HeaderMode_e { /** * @brief No header is added */ CBUFF_HeaderMode_NONE = 0x1, /** * @brief Custom application specific headers. */ CBUFF_HeaderMode_CUSTOM }CBUFF_HeaderMode; /** * @brief * Session Execution Mode * * @details * The enumeration describes the execution mode for the sessions. * Sessions can be automatically triggered by the hardware *or* these * need to be triggered manually by the CBUFF Driver. */ typedef enum CBUFF_SessionExecuteMode_e { /** * @brief CBUFF Transfers are triggered by the hardware. */ CBUFF_SessionExecuteMode_HW = 0x0, /** * @brief CBUFF Transfers are triggered by the driver */ CBUFF_SessionExecuteMode_SW }CBUFF_SessionExecuteMode; /** * @brief * CBUFF LVDS Initialization configuration * * @details * The structure describes the configuration which is required to configure * the LVDS */ typedef struct CBUFF_LVDSCfg_t { /** * @brief Enable/Disable CRC on LVDS */ uint8_t crcEnable; /** * @brief LVDS Lane configuration: The bit mask here is used to indicate * the active LVDS lanes i.e. Bit 0 implies Lane-0, Bit 1 implies Lanel-1 etc * * The number of LVDS lanes is platform specific and is defined in the CBUFF * platform file. */ uint8_t lvdsLaneEnable; /** * @brief Set the flag to 1 to indicate that the MSB is sent first or LSB */ uint8_t msbFirst; /** * @brief Set the flag to 1 for DDR Clock Mode and 0 for SDR */ uint8_t ddrClockMode; /** * @brief Set the flag to 1 for DDR Mode Clock Mux and 0 for SDR Mode Clock Mux */ uint8_t ddrClockModeMux; /** * @brief LVDS Lane Format: */ CBUFF_LVDSLaneFmtMap laneFormat; }CBUFF_LVDSCfg; /** * @brief * CBUFF CSI configuration * * @details * The structure describes the configuration which is required to use * the CBUFF with the CSI as a high speed interface */ typedef struct CBUFF_CSICfg_t { /** * @brief Handle to the CSI Driver: */ CSI_Handle handle; }CBUFF_CSICfg; /** * @brief * CBUFF Buffer configuration * * @details * This is a generic data structure which is exposed to the application * to pass buffer configuration to the drivers. This is used to populate * the User Buffers and Headers which can be streamed out via CBUFF to * the selected High speed interface. */ typedef struct CBUFF_BufferCfg_t { /** * @brief Size of the Buffer: This can be set to 0 to indicate * that no buffer is specified. The size is specified in CBUFF units * i.e. 16 bits. */ uint16_t size; /** * @brief Address of the Buffer: * Please be aware that the address should be in a memory range * which is accessible by the EDMA. */ uint32_t address; }CBUFF_BufferCfg; /** * @brief * CBUFF Statistics * * @details * The structure describes the CBUFF statistics which can be used * to determine the behavior of the CBUFF module. */ typedef struct CBUFF_Stats_t { /** * @brief Number of frame start interrupts received: This is available * only if the driver is initialized in the debug mode. Else this is * always set to 0. * * @sa CBUFF_InitCfg_t::enableDebugMode */ uint32_t numFrameStart; /** * @brief Number of frame done interrupts received: This is available * only in the following cases: * (a) Enable debug mode * (b) Sessions with the Frame done callback * If either of the above cases is not met the value of this is always 0. * * @sa CBUFF_InitCfg_t::enableDebugMode * @sa CBUFF_SessionCfg_t::frameDoneCallbackFxn */ uint32_t numFrameDone; /** * @brief Number of chirp done interrupts received: This is available * only in the following cases: * (a) Enable debug mode * (b) Sessions with the Frame done callback * If either of the above cases is not met the value of this is always 0. * * @sa CBUFF_InitCfg_t::enableDebugMode * @sa CBUFF_SessionCfg_t::frameDoneCallbackFxn */ uint32_t numChirpDone; /** * @brief Number of error interrupts received. This is always available */ uint32_t numErrorInterrupts; /** * @brief Flag which indicated if a frame start error was detected. * This is always available */ uint8_t frameStartError; /** * @brief Flag which indicated if a chirp error was detected. * This is always available */ uint8_t chirpError; }CBUFF_Stats; /** * @brief * CBUFF EDMA channel resource configuration * * @details * The structure describes the EDMA channel resources which are needed by the * CBUFF driver in order to stream out the data over the high speed interface. */ typedef struct CBUFF_EDMAChannelCfg_t { /** * @brief EDMA Chain Channels Identifier */ uint8_t chainChannelsId; /** * @brief EDMA Shadow link channels Identifier */ uint16_t shadowLinkChannelsId; }CBUFF_EDMAChannelCfg; /** * @brief * CBUFF EDMA Information block * * @details * The structure describes the EDMA informational block which is passed * to the application. The information here requires to be used by the * application before performing an EDMA channel allocation. */ typedef struct CBUFF_EDMAInfo_t { /** * @brief EDMA Instance handle: This is the configuration which was passed * by the application. Ensure that the EDMA channels are allocated from the * the specified EDMA instance. */ EDMA_Handle edmaHandle; /** * @brief Flag which if set indicates that this is the first EDMA channel which * is being allocated. The first EDMA channel allocation is a special case explained * below. */ _Bool isFirstEDMAChannel; /** * @brief DMA Number: There are multiple DMA in the CBUFF driver. There exists * a mapping between the CBUFF DMA number and the corresponding hardwired EDMA channel. * * Please be aware that the CBUFF EDMA transfers are kicked in automatically by the * hardware. The XWR1xx has a special CBUFF EDMA Physical channel which has been allocated * for this purpose and which should not be used for any other reason. Each DMA Number is * associated with a corresponding EDMA channel. * * DMA Number | EDMA Physical Channel(s) * ------------|----------------------- * 0 | EDMA_TPCC0_REQ_CBUFF_0, EDMA_TPCC1_REQ_CBUFF_0 * 1 | EDMA_TPCC0_REQ_CBUFF_1, EDMA_TPCC1_REQ_CBUFF_1 * 2 | EDMA_TPCC0_REQ_CBUFF_2, EDMA_TPCC1_REQ_CBUFF_2 * 3 | EDMA_TPCC0_REQ_CBUFF_3, EDMA_TPCC1_REQ_CBUFF_3 * 4 | EDMA_TPCC0_REQ_CBUFF_4, EDMA_TPCC1_REQ_CBUFF_4 * 5 | EDMA_TPCC0_REQ_CBUFF_5, EDMA_TPCC1_REQ_CBUFF_5 * 6 | EDMA_TPCC0_REQ_CBUFF_6, EDMA_TPCC1_REQ_CBUFF_6 * * The XXX_TPCC0_YYY are for EDMA Instance 0 while the XXX_TPCC1_YYY are for the * EDMA Instance 1. * * Please ensure that the *first* EDMA channel for the specified DMA number has to be * from the table above. There is no restriction on subsequent EDMA channel allocations. * This table needs to be enforced if the 'isFirstEDMAChannel' is set to true. * * *NOTE*: The CBUFF driver will fail the session creation if the above table is not * enforced. */ uint8_t dmaNum; }CBUFF_EDMAInfo; /** * @b Description * @n * This is the function which is registered with the CBUFF driver and is invoked * by the driver whenever it needs to allocate and use an EDMA channel. * * @param[in] dmaNum * DMA Number to be used for EDMA channel allocation * @param[in] ptrEDMAInfo * Pointer to the EDMA informational block which needs to be used by * the application to perform the EDMA channel allocation * @param[out] ptrEDMAChannelCfg * Pointer to the EDMA Channel configuration which is to be populated * * @retval * Success - 0 * @retval * Error - <0 [Implies that the application is unable to allocate a channel] * * @b NOTE: * The EDMA transfer completion codes are identical to the CBUFF Physical & chain channel * resources therefore these transfer completion codes are considered to be reserved * for CBUFF Usage. */ typedef int32_t (*CBUFF_EDMAChannelAllocateFxn) (CBUFF_EDMAInfo* ptrEDMAInfo, CBUFF_EDMAChannelCfg* ptrEDMAChannelCfg); /** * @b Description * @n * This is the function which is registered with the CBUFF driver and is invoked * by the driver whenever it needs to free an allocated EDMA channel. * * @param[in] ptrEDMAChannelCfg * Pointer to the EDMA chnanel configuration which is to be released * * @retval * Not applicable */ typedef void (*CBUFF_EDMAChannelFreeFxn) (CBUFF_EDMAChannelCfg* ptrEDMAChannelCfg); /** * @b Description * @n * Sessions can register for Frame Done interrupts. This callback function * is invoked if the session is currently active and the CBUFF Driver receives * a frame done interrupt. Application should use this to activate another * session. Switching between active sessions while the frame is not done can * lead to unexpected results. * * @param[in] sessionHandle * Session Handle which was active for which the Frame done interrupt was * received * * @retval * Not applicable */ typedef void (*CBUFF_FrameDoneCallbackFxn) (CBUFF_SessionHandle sessionHandle); /** * @brief * CBUFF Hardware Triggered Session configuration * * @details * The structure describes the configuration required to be specified if * the session is created in hardware triggered mode. */ typedef struct CBUFF_HwSessionCfg_t { /** * @brief ADCBUF Driver Handle: Ensure that the ADC Channels are * enabled and configured. */ ADCBuf_Handle adcBufHandle; /** * @brief Data Format: This is used to describe the format of the data * which is being sent out via the HSI. */ CBUFF_DataFmt dataFormat; /** * @brief ADC Buffer data storage mode: Interleaved or Non-Interleaved * This is only used if the data format is configured to send out ADC Data */ CBUFF_DataMode dataMode; /** * @brief Operational mode for the driver: */ CBUFF_OperationalMode opMode; /** * @brief This field is described as follows:- * * - Chirp Mode : Number of chirps per frame * - Continuous Mode: This field is ignored */ uint32_t numChirpsPerFrame; /** * @brief This field is described as follows:- * - Single Chirp Mode : Set this to 1 * - Multi-Chirp Mode : Set this between 2 to 8 * - Continuous Mode : Set this to 0 * * *NOTE*: Multi-Chirp mode is possible only on the XWR16xx/XWR18xx/XWR68xx. * But default CBUFF library disables this on these devices. * In order to include support for multi-chirp mode, populate the multi-chirp table * as instructed in the platform/cbuff_\.c file. */ uint32_t chirpMode; /** * @brief This field is described as follows:- * * - Chirp Mode : This is the number of ADC samples per chirp per channel * - Continuous Mode : This is the number of samples per channel which is configured * in the ADC Buffer * * This is only used if the data format is configured to send out ADC data. */ uint16_t numADCSamples; /** * @brief Chirp Quality Size: The size is specified in CBUFF units * If the size is set to 0; CQx is ignored. */ uint16_t cqSize[ADCBufMMWave_CQType_MAX_CQ]; /** * @brief User supplied data buffers which can be transmitted over the interface */ CBUFF_BufferCfg userBufferInfo[3U]; }CBUFF_HwSessionCfg; /** * @brief * CBUFF Software Triggered Session configuration * * @details * The structure describes the configuration required to be specified if * the session is created in software triggered mode. */ typedef struct CBUFF_SwSessionCfg_t { /** * @brief User supplied data buffers which can be transmitted over the interface */ CBUFF_BufferCfg userBufferInfo[3U]; }CBUFF_SwSessionCfg; /** * @brief * CBUFF configuration * * @details * The structure describes the configuration which is required to configure * the CBUFF Driver. */ typedef struct CBUFF_SessionCfg_t { /** * @brief Session execution mode: Hardware or Software triggered */ CBUFF_SessionExecuteMode executionMode; /** * @brief This is the callback function which is triggered once the frame has * been sent over the HSI. This can be set to NULL if the application only uses * a single session. But if multiple sessions are being used application should * register this callback function in order to switch from one session to another * * *NOTE*: Applications are responsible for ensuring that the switch between the * sessions is done between the inter-frame boundaries. Failure to enforce this * will result in unpredictable behavior. */ CBUFF_FrameDoneCallbackFxn frameDoneCallbackFxn; /** * @brief EDMA Instance Handle: The session will allocate EDMA channels */ EDMA_Handle edmaHandle; /** * @brief Application provided EDMA Channel allocation function. */ CBUFF_EDMAChannelAllocateFxn allocateEDMAChannelFxn; /** * @brief Application provided EDMA Channel free function. */ CBUFF_EDMAChannelFreeFxn freeEDMAChannelFxn; /** * @brief Type of Data: Real or Complex which is going to be streamed out * via the CBUFF High speed interface */ CBUFF_DataType dataType; /** * @brief This is the header which needs to be added to the stream. If the * size in the header is set to 0 then no header will be appended. */ CBUFF_BufferCfg header; union { /** * @brief Configuration used if the session is executing in hardware * trigerred mode */ CBUFF_HwSessionCfg hwCfg; /** * @brief Configuration used if the session is executing in software * trigerred mode */ CBUFF_SwSessionCfg swCfg; }u; }CBUFF_SessionCfg; /** * @brief * CBUFF Initialization Configuration * * @details * The structure describes the configuration which is required to initialize * the CBUFF Driver. */ typedef struct CBUFF_InitCfg_t { /** * @brief SOC Handle */ SOC_Handle socHandle; /** * @brief This is used to specify the LVDS/CSI2 output format. */ CBUFF_OutputDataFmt outputDataFmt; /** * @brief Enable/Disable the ECC in the CBUFF module */ uint8_t enableECC; /** * @brief In order to ensure data integrity of data transfer from ADC buffer to CBUFF * there is a CRC computed and this checked for integrity in the hardware at both the * source (ADC Buffer) and destination (CBUFF) */ uint8_t crcEnable; /** * @brief This is the maximum number of sessions which can be supported * for the CBUFF Instance. This value needs to be >= 1 and < CBUFF_MAX_NUM_SESSION. * Any other value will result in an invalid argument error. */ uint8_t maxSessions; /** * @brief This is a flag which if set to true will register the ISR to track * Frame Start/Done and Chirp done. * * *NOTE*: Enable the debug mode will allow the statistics to increment and can * be useful to ensure that the streaming is working. But this can overwhelm the * system with a large number of interrupts. * * Certain interrupt such as the Frame Done interrupts are required to be registered * if multiple sessions are created. Switching from one session to another can * only be done with the intra-frame boundary. */ _Bool enableDebugMode; /** * @brief The interface over which the CBUFF module will send out the data */ CBUFF_Interface interface; /** * @brief Interface specific configuration: */ union { /** * @brief LVDS Initializaton configuration: This needs to be specified * if the interface is configured to be LVDS. */ CBUFF_LVDSCfg lvdsCfg; /** * @brief CSI Initializaton configuration: This needs to be specified * if the interface is configured to be CSI. */ CBUFF_CSICfg csiCfg; }u; }CBUFF_InitCfg; /** @} */ /******************************************************************************************************* * CBUFF Exported API: *******************************************************************************************************/ extern CBUFF_Handle CBUFF_init (CBUFF_InitCfg* ptrInitCfg, int32_t* errCode); extern int32_t CBUFF_deinit (CBUFF_Handle cBuffHandle, int32_t* errCode); extern int32_t CBUFF_control(CBUFF_Handle cBuffHandle, CBUFF_Command cmd, void* arg, uint32_t argLen, int32_t* errCode); /* Session Management API: */ extern CBUFF_SessionHandle CBUFF_createSession (CBUFF_Handle cbuffHandle, CBUFF_SessionCfg* ptrSessionCfg, int32_t* errCode); extern int32_t CBUFF_activateSession (CBUFF_SessionHandle sessionHandle, int32_t* errCode); extern int32_t CBUFF_deactivateSession (CBUFF_SessionHandle sessionHandle, int32_t* errCode); extern int32_t CBUFF_deleteSession (CBUFF_SessionHandle sessionHandle, int32_t* errCode); /* data capabilities query API */ extern _Bool CBUFF_isInterleavedDataFormatSupported(CBUFF_DataFmt dataFmt); extern _Bool CBUFF_isNonInterleavedDataFormatSupported(CBUFF_DataFmt dataFmt); extern _Bool CBUFF_isMultipleChirpNonInterleavedDataFormatSupported(CBUFF_DataFmt dataFmt); /** * @file hsiheader.h * * @brief * This is the main header file which is exported to the application * developers. This can be used in conjunction with the mmWave SDK * CBUFF driver to create a header which can then be attached to * a data stream. * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @mainpage HSI Header * * The HSI Header is a utility library which can be used in conjunction with * the CBUFF Driver to create a header which can be attached to any data stream * which is being transmitted via the High speed interface (HSI). * * The HSI Header Utility provides the following features:- * - Management of Header and creating CBUFF Sessions * Application developers use this feature while developing code on the * XWR1xx device using the mmWave SDK. Developers will use this module * to create a header for a specific CBUFF Driver session. * * In order to use this feature application developers would need to include * the following headers:- * @code #include #include @endcode * * - Decoding the Header * Once the data has been streamed out then on the remote peer the header would * need to be decoded to get access to the actual data which has been streamed * out. * * In order to use this feature application developers would need to include * the following headers:- * @code #include @endcode * This header file is defined to be a standalone header file with *no* dependency * on any other mmWave SDK component. This will ensure that the file can be compiled * into any application on the remote peer for header decoding. */ /** @defgroup HSI_HEADER_UTIL HSI Header Utility */ /* mmWave SDK Include Files: */ /** * @file hsiprotocol.h * * @brief * The header file exposes the HSI header and associated definitions. * HSI headers are created and attached to an LVDS stream which is * being transmitted. The headers can be decoded on the peer where * the stream is received to get access to the actual data. * * This file can be used independently and does not have any * dependencies on the mmWave SDK. * * \par * NOTE: * (C) Copyright 2017 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @addtogroup HSI_HEADER_PROTOCOL @{ */ /********************************************************************************** * Standard Endianess Macros: * - The HSI Header Protocol works natively over Little Endian. Use the following * macros to ensure portability. **********************************************************************************/ /** * @brief Macro which converts 16 bit data from host to network order. */ /** * @brief Macro which converts 32 bit data from host to network order. */ /** * @brief Macro which converts 64 bit data from host to network order. */ /** * @brief Macro which converts 32 bit data from network to host order. */ /** * @brief Macro which converts 16 bit data from network to host order. */ /** * @brief Macro which converts 64 bit data from network to host order. */ /** * @brief * HSI Header Identifier1: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier2: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier3: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier4: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier5: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier6: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier7: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * HSI Header Identifier8: These are unique identifiers which * are attached at the beginning of each header. * * @sa HSIHeader::id */ /** * @brief * Platform is XWR14xx * * @sa HSIHeader::platform */ /** * @brief * Platform is XWR16xx * * @sa HSIHeader::platform */ /** * @brief * Platform is XWR18xx * * @sa HSIHeader::platform */ /** * @brief * Platform is XWR68xx * * @sa HSIHeader::platform */ /** * @brief * ADC Data is interleaved * * @sa HSIHeader::interleavedMode */ /** * @brief * Data is non-interleaved. This is applicable for ADC while * operating in non-interleaved mode and for all user data. * * @sa HSIHeader::interleavedMode */ /** * @brief * Size of the data (16bit) being transferred streamed over the LVDS * * @sa HSIHeader::dataSize */ /** * @brief * Size of the data (14bit) being transferred streamed over the LVDS * * @sa HSIHeader::dataSize */ /** * @brief * Size of the data (12bit) being transferred streamed over the LVDS * * @sa HSIHeader::dataSize */ /** * @brief * Real data being streamed out * * @sa HSIHeader::dataType */ /** * @brief * Complex data being streamed out * * @sa HSIHeader::dataType */ /** * @brief * Data Format: Only ADC data is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * Data Format: Chirp Profile + ADC data is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * Data Format: ADC data + Chirp Profile is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * Data Format: Chirp Profile + ADC data + Chirp Quality is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * Data Format: User Data is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * Data Format: ADC + User Data is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * Data Format: Chirp Profile + ADC data + Chirp Quality + User Data is being streamed over the LVDS * * @sa HSIHeader::dataFmt */ /** * @brief * This is the maximum number of user buffers which can be supported in the HSI Header. This * should be the same as the MAX number of user buffers supported in the CBUFF Driver. However * we cannot use the same macro here because it will make the file dependent on the mmWave * SDK. So instead we redefine the macro and verify the sanity during the * HSI Header initialization */ /** * @brief * This is the maximum number of chirp quality which can be supported in the HSI Header. This * should be the same as the definition supported in the ADCBUF Driver. However we cannot * use the same macro here because it will make the file dependent on the mmWave SDK. * So instead we redefine the macro and verify the sanity during the HSI Header * initialization */ /** * @brief * The DCA1000EVM FPGA needs a minimum delay of 12ms between Bit clock starts and * actual LVDS Data start to lock the LVDS PLL IP. This is documented in the DCA UG */ /** * @brief * The HSI Header Size is the maximum size of the HSI Header. The DCA1000EVM FPGA * requires the data to be aligned on 256 bytes. While creating a header applications * can specify the alignment requirements. */ /** * @brief * The HSI header allows an application to add an application defined extension * header. This is the maximum size of the header. */ /** * @brief * HSI Data Card Header * * @details * The HSI Data Card Header is used by the TI Data card while configured to * operate in Multi-Mode */ typedef struct HSIDataCardHeader_t { /** * @brief Unique HSI Identifier associated with the header. */ uint64_t id; /** * @brief Total length (in BYTES) of all the data which is being streamed. * This is the lower 12 bits. */ uint16_t totalLengthLSW; /** * @brief Total length (in BYTES) of all the data which is being streamed. * This is the higher 12 bits. Application developers can use the helper * function to get the total length of the packet. The size excludes the * data card header. * * @sa HSIHeader_getTotalLength */ uint16_t totalLengthMSW; /** * @brief Reserved: */ uint32_t reserved; }HSIDataCardHeader; /** * @brief * HSI SDK Header * * @details * The HSI SDK Header is a header which provides meta-information to the * receiver of the HSI stream. This information can be used to parse the * stream and access the data */ typedef struct HSISDKHeader_t { /** * @brief Version of the mmWave SDK associated with the HSI Header. Refer to * the following file mmwave_sdk_version.h for more information. The field is * encoded as follows:- * * @code 11 9 6 3 0 ----------------------------------- | Major | Minor | Bug Fix | Build | ----------------------------------- @endcode * * Application developers can use the helper function to extract this information * @sa HSIHeader_getVersion */ uint16_t version; /** * @brief In order to ensure that the entire data is streamed out there are * certain size alignments which need to be enforced. This is explained in more * detail in the TRM. The size of the header is thus not *fixed* and could be * padded to ensure alignment. The size is specified in CBUFF Units. * * In order to get the padding size refer to the following helper function:- * @sa HSIHeader_getPaddingSize * * Application developers can use the helper function to skip the header to get to * the payload * @sa HSIHeader_getPayload */ uint16_t headerSize; /** * @brief Platform on which the HSI Header was generated * * @sa * HSI_PLATFORM_XWR14XX * @sa * HSI_PLATFORM_XWR16XX * @sa * HSI_PLATFORM_XWR18XX * @sa * HSI_PLATFORM_XWR68XX */ uint8_t platform; /** * @brief Mode in which the data is being transferred. * - ADC Data can be Interleaved or Non-Interleaved * - User data is always Non-interleaved * * @sa * HSI_HEADER_MODE_INTERLEAVED * @sa * HSI_HEADER_MODE_NON_INTERLEAVED */ uint8_t interleavedMode; /** * @brief This is the number of bits being transferred * @sa * HSI_HEADER_SIZE_16BIT * @sa * HSI_HEADER_SIZE_14BIT * @sa * HSI_HEADER_SIZE_12BIT */ uint8_t dataSize; /** * @brief This is the type of data being streamed * @sa * HSI_HEADER_TYPE_REAL * @sa * HSI_HEADER_TYPE_COMPLEX */ uint8_t dataType; /** * @brief Bit Flag which will indicate the receive channel status on * whether it is enabled or disabled * Bit Number | Channel Number * -----------|--------------- * Bit 0 | Channel 0 * Bit 1 | Channel 1 * Bit 2 | Channel 2 * Bit 3 | Channel 3 */ uint8_t rxChannelStatus; /** * @brief This is the format of the data which is being streamed out. */ uint8_t dataFmt; /** * @brief This is used to indicate the number of chirps. Set to 1 for * single chirp mode and between 2 to 8 for multiple chirp mode. * * *NOTE*: Multiple Chirp Mode is applicable only for XWR16xx/XWR18xx/XWR68xx */ uint16_t chirpMode; /** * @brief Size in CBUFF Units of the ADC Data for each channel */ uint16_t adcDataSize; /** * @brief Size in CBUFF Units of the Chirp Profile for each channel */ uint16_t cpDataSize; /** * @brief Size in CBUFF Units of the Chirp Quality (CQx). If the * size is set to 0 then there is no CQx data present. */ uint16_t cqDataSize[3U]; /** * @brief Size in CBUFF Units of the User Buffer */ uint16_t userBufSize[3U]; /** * @brief Application defined extension header: This is available to the * application to add an application specific *static* header. Once the * headers are configured and the sessions are executing this data should not * be changed. */ uint8_t appExtensionHeader[8U]; }HSISDKHeader; /** * @brief * HSI Header * * @details * This is the header which is created by the HSI Module. The header * should be configured as a part of the CBUFF session. The header allows * the ability to specify meta-information which can be used on the * remote end to help decode the received data. * * *NOTE*: The data which gets streamed out could be 12bit/14bit/16bit * But in order to make the header generic each field is defined to be * at most 12bits */ typedef struct HSIHeader_t { /** * @brief Data Card Header: The data card header is required and is * interpreted the TI Data Card in Multi-Mode */ HSIDataCardHeader dataCardHeader; /** * @brief SDK Header: */ HSISDKHeader sdkHeader; /** * @brief Padding Buffer: */ uint8_t paddingBuffer[256U - sizeof(HSIDataCardHeader) - sizeof(HSISDKHeader)]; }HSIHeader; /*********************************************************************************** * Exported Protocol Inline Functions: ***********************************************************************************/ /** * @b Description * @n * This is an exported function which is provided to convert * CBUFF Units into bytes * * @param[in] cbuffUnits * CBUFF Units to convert * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Number of bytes */ static inline uint16_t HSIHeader_toBytes (uint16_t cbuffUnits) { return (cbuffUnits << 1U); } /** * @b Description * @n * This is an exported function which is provided to convert * bytes into CBUFF Units * * @param[in] bytes * Bytes to convert * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Number of CBUFF Units */ static inline uint16_t HSIHeader_toCBUFFUnits (uint16_t bytes) { return (bytes >> 1U); } /** * @b Description * @n * This is an exported function which is used to skip the HSI header * and return a pointer to the actual payload. * * @param[in] ptrHeader * Pointer to the Header * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Pointer to the data stream */ static inline uint8_t* HSIHeader_getPayload (HSIHeader* ptrHeader) { /* Convert the header size into bytes. Skip the header to get the payload */ return (uint8_t*)ptrHeader + HSIHeader_toBytes(ptrHeader->sdkHeader.headerSize); } /** * @b Description * @n * This is an exported function which is used to get the size of the HSI Header * The size of the HSI Header is typically passed to the CBUFF Sessions and * is the amount of data actually streamed out. The header size will include * any padding * * @param[in] ptrHeader * Pointer to the Header * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Size of the HSI Header to be streamed out in CBUFF Units */ static inline uint16_t HSIHeader_getHeaderSize (HSIHeader* ptrHeader) { return ptrHeader->sdkHeader.headerSize; } /** * @b Description * @n * This is an exported function which is used to get the padding size * * @param[in] ptrHeader * Pointer to the Header * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Padding Size in CBUFF Units */ static inline uint16_t HSIHeader_getPaddingSize (HSIHeader* ptrHeader) { uint16_t minHeaderSize; /* Mandatory Size of the Header: Size of the header without any padding. */ minHeaderSize = sizeof (HSIDataCardHeader) + sizeof(HSISDKHeader); minHeaderSize = HSIHeader_toCBUFFUnits (minHeaderSize); /* What ever is left after the mandatory header is the padding */ return (ptrHeader->sdkHeader.headerSize - minHeaderSize); } /** * @b Description * @n * This is an exported function which is used to extract the version * information from the HSI header * * @param[in] ptrHeader * Pointer to the Header * @param[out] major * mmWave SDK Major Version Number * @param[out] minor * mmWave SDK Minor Version Number * @param[out] bugFix * mmWave SDK Bug Fix Number * @param[out] build * mmWave SDK Build Number * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Not applicable */ static inline void HSIHeader_getVersion ( HSIHeader* ptrHeader, uint8_t* major, uint8_t* minor, uint8_t* bugFix, uint8_t* build ) { uint16_t version = (ptrHeader->sdkHeader . version); *major = (version & 0xE00) >> 9; *minor = (version & 0x1C0) >> 6; *bugFix = (version & 0x031) >> 3; *build = (version & 0x7); } /** * @b Description * @n * This is an exported function which is provided to get the * total length of the entire stream. This is specified in * bytes and includes the HSI header & actual data * * @param[in] ptrHeader * Pointer to the Header * * \ingroup HSI_HEADER_PROTOCOL * * @retval * Total Length of the packet in bytes */ static inline uint32_t HSIHeader_getTotalLength (HSIHeader* ptrHeader) { uint32_t totalLength; totalLength = sizeof(HSIDataCardHeader); totalLength += ((((ptrHeader->dataCardHeader . totalLengthMSW) & 0xFFF) << 12U) | ((ptrHeader->dataCardHeader . totalLengthLSW) & 0xFFF)); return totalLength; } /** @} */ /** @defgroup HSI_HEADER_UTIL_EXTERNAL_FUNCTION HSI Header Utility External Functions @ingroup HSI_HEADER_UTIL @brief * The section has a list of all the exported API which the applications need to * invoke in order to use the module */ /** @defgroup HSI_HEADER_PROTOCOL HSI Header Protocol @ingroup HSI_HEADER_UTIL @brief * The section has information pertinent to the definition of the HSI Header. */ /** @defgroup HSI_HEADER_UTIL_INTERNAL_FUNCTION HSI Header Utility Internal Functions @ingroup HSI_HEADER_UTIL @brief * The section has a list of all internal API which are not exposed to the external * applications. */ /** @defgroup HSI_HEADER_UTIL_INTERNAL_DATA_STRUCTURE HSI Header Utility Internal Data Structures @ingroup HSI_HEADER_UTIL @brief * The section has a list of all internal data structures which are used internally * by the module. */ /** @defgroup HSI_HEADER_UTIL_INTERNAL_DEFINITION HSI Header Utility Internal Definition @ingroup HSI_HEADER_UTIL @brief * The section has a list of all internal definitions which are used internally * by the module. */ /** @defgroup HSI_HEADER_UTIL_ERROR_CODE HSI Header Utility Error Codes @ingroup HSI_HEADER_UTIL @brief * The section has a list of all the error codes which are generated by the module */ /** @addtogroup HSI_HEADER_UTIL_ERROR_CODE @{ */ /** * @brief Error Code: Invalid argument */ /** * @brief Error Code: Limit Exceeded */ /** @} */ /************************************************************************** *************************** Extern Definitions *************************** **************************************************************************/ extern int32_t HSIHeader_init (CBUFF_InitCfg* ptrInitCfg, int32_t* errCode); extern int32_t HSIHeader_createHeader (CBUFF_SessionCfg* ptrSessionCfg, _Bool bAlignDataCard, HSIHeader* ptrHeader, int32_t* errCode); extern int32_t HSIHeader_deleteHeader(HSIHeader* ptrHeader, int32_t* errCode); extern int32_t HSIHeader_deinit (int32_t* errCode); /** * @brief This is the maximum number of EDMA Channels which is used by * the HW Session */ /** * @brief This is the maximum number of EDMA Channels which is used by * the SW Session */ /** * @brief * LVDS streaming user data header * * @details * The LVDS SW streaming user data header. */ typedef struct MmwDemo_LVDSUserDataHeader { /** * @brief Frame number. */ uint32_t frameNum; /** * @brief Sub-Frame number. Always 0 when advanced frame is not enabled. * Note although the subFrameNum does not need to be 16-bits (it needs to be * only 8-bits), we keep it 16-bit for parsing convenience as compiler * does not insert holes in this case */ uint16_t subFrameNum; /** * @brief Number of detected objects. */ uint16_t detObjNum; } MmwDemo_LVDSUserDataHeader_t; /** * @brief * LVDS streaming MCB * * @details * The LVDS streaming MCB. */ typedef struct MmwDemo_LVDSStream_MCB { /** * @brief Handle to the CBUFF Driver */ CBUFF_Handle cbuffHandle; /** * @brief EDMA Channel Allocator Index for the HW Session */ uint8_t hwSessionEDMAChannelAllocatorIndex; /** * @brief EDMA Channel Resource Table: This is used for creating the CBUFF Session. */ CBUFF_EDMAChannelCfg hwSessionEDMAChannelTable[11U]; /** * @brief EDMA Channel Allocator Index for the SW Session */ uint8_t swSessionEDMAChannelAllocatorIndex; /** * @brief EDMA Channel Resource Table: This is used for creating the CBUFF Session. */ CBUFF_EDMAChannelCfg swSessionEDMAChannelTable[3U]; /** * @brief HW session HSI header. */ HSIHeader hwSessionHSIHeader; /** * @brief True if hw session HSI header is allocated, false otherwise */ _Bool isHwSessionHSIHeaderAllocated; /** * @brief SW session HSI header. */ HSIHeader swSessionHSIHeader; /** * @brief Handle to the HW CBUFF Session Handle. */ CBUFF_SessionHandle hwSessionHandle; /** * @brief Handle to the SW CBUFF Session Handle. */ CBUFF_SessionHandle swSessionHandle; /** * @brief Number of HW frame done interrupt received. */ uint16_t hwFrameDoneCount; /** * @brief Number of SW frame done interrupt received. */ uint16_t swFrameDoneCount; /** * @brief Semaphore handle to signal hw session done. */ ti_sysbios_knl_Semaphore_Handle hwFrameDoneSemHandle; /** * @brief Semaphore handle to signal sw session done. */ ti_sysbios_knl_Semaphore_Handle swFrameDoneSemHandle; /** * @brief Pointer to user data header. */ MmwDemo_LVDSUserDataHeader_t *userDataHeader; } MmwDemo_LVDSStream_MCB_t; int32_t MmwDemo_LVDSStreamInit (void); int32_t MmwDemo_LVDSStreamHwConfig (uint8_t subFrameIndx); int32_t MmwDemo_LVDSStreamSwConfig (uint32_t numObjOut, DPIF_PointCloudCartesian *objOut, DPIF_PointCloudSideInfo *objOutSideInfo); void MmwDemo_configLVDSHwData(uint8_t subFrameIndx); void MmwDemo_LVDSStreamDeleteHwSession (void); void MmwDemo_LVDSStreamDeleteSwSession (void); /*! @brief For advanced frame config, below define means the configuration given is * global at frame level and therefore it is broadcast to all sub-frames. */ /*! @brief CFAR threshold encoding factor */ /** * @defgroup configStoreOffsets Offsets for storing CLI configuration * @brief Offsets of config fields within the parent structures, note these offsets will be * unique and hence can be used to differentiate the commands for processing purposes. * @{ */ /** @}*/ /* configStoreOffsets */ /** * @brief * Millimeter Wave Demo Sensor State * * @details * The enumeration is used to define the sensor states used in mmwDemo */ typedef enum MmwDemo_SensorState_e { /*! @brief Inital state after sensor is initialized. */ MmwDemo_SensorState_INIT = 0, /*! @brief Inital state after sensor is post RF init. */ MmwDemo_SensorState_OPENED, /*! @brief Indicates sensor is started */ MmwDemo_SensorState_STARTED, /*! @brief State after sensor has completely stopped */ MmwDemo_SensorState_STOPPED }MmwDemo_SensorState; /** * @brief * Millimeter Wave Demo statistics * * @details * The structure is used to hold the statistics information for the * Millimeter Wave demo */ typedef struct MmwDemo_MSS_Stats_t { /*! @brief Counter which tracks the number of frame trigger events from BSS */ uint64_t frameTriggerReady; /*! @brief Counter which tracks the number of failed calibration reports * The event is triggered by an asynchronous event from the BSS */ uint32_t failedTimingReports; /*! @brief Counter which tracks the number of calibration reports received * The event is triggered by an asynchronous event from the BSS */ uint32_t calibrationReports; /*! @brief Counter which tracks the number of sensor stop events received * The event is triggered by an asynchronous event from the BSS */ uint32_t sensorStopped; }MmwDemo_MSS_Stats; /** * @brief * Millimeter Wave Demo Data Path Information. * * @details * The structure is used to hold all the relevant information for * the data path. */ typedef struct MmwDemo_SubFrameCfg_t { /*! @brief ADC buffer configuration storage */ MmwDemo_ADCBufCfg adcBufCfg; /*! @brief Flag indicating if @ref adcBufCfg is pending processing. */ uint8_t isAdcBufCfgPending : 1; /*! @brief LVDS stream configuration */ MmwDemo_LvdsStreamCfg lvdsStreamCfg; /*! @brief Flag indicating if @ref lvdsStreamCfg is pending processing. */ uint8_t isLvdsStreamCfgPending : 1; /*! @brief GUI Monitor selection configuration storage from CLI */ MmwDemo_GuiMonSel guiMonSel; /*! @brief Dynamic configuration storage for object detection DPC */ MmwDemo_DPC_ObjDet_DynCfg objDetDynCfg; /*! @brief Number of range FFT bins, this is at a minimum the next power of 2 of numAdcSamples. If range zoom is supported, this can be bigger than the minimum. */ uint16_t numRangeBins; /*! @brief Number of Doppler FFT bins, this is at a minimum the next power of 2 of numDopplerChirps. If Doppler zoom is supported, this can be bigger than the minimum. */ uint16_t numDopplerBins; /*! @brief ADCBUF will generate chirp interrupt event every this many chirps - chirpthreshold */ uint8_t numChirpsPerChirpEvent; /*! @brief Number of bytes per RX channel, it is aligned to 16 bytes as required by ADCBuf driver */ uint32_t adcBufChanDataSize; /*! @brief CQ signal & image band monitor buffer size */ uint32_t sigImgMonTotalSize; /*! @brief CQ RX Saturation monitor buffer size */ uint32_t satMonTotalSize; /*! @brief Number of ADC samples */ uint16_t numAdcSamples; /*! @brief Number of chirps per sub-frame */ uint16_t numChirpsPerSubFrame; /*! @brief Number of virtual antennas */ uint8_t numVirtualAntennas; } MmwDemo_SubFrameCfg; /*! * @brief * Structure holds message stats information from data path. * * @details * The structure holds stats information. This is a payload of the TLV message item * that holds stats information. */ typedef struct MmwDemo_SubFrameStats_t { /*! @brief Frame processing stats */ MmwDemo_output_message_stats outputStats; /*! @brief Dynamic CLI configuration time in usec */ uint32_t pendingConfigProcTime; /*! @brief SubFrame Preparation time on MSS in usec */ uint32_t subFramePreparationTime; } MmwDemo_SubFrameStats; /** * @brief Task handles storage structure */ typedef struct MmwDemo_TaskHandles_t { /*! @brief MMWAVE Control Task Handle */ ti_sysbios_knl_Task_Handle mmwaveCtrl; /*! @brief ObjectDetection DPC related dpmTask */ ti_sysbios_knl_Task_Handle objDetDpmTask; /*! @brief Demo init task */ ti_sysbios_knl_Task_Handle initTask; } MmwDemo_taskHandles; /*! * @brief * Structure holds temperature information from Radar front end. * * @details * The structure holds temperature stats information. */ typedef struct MmwDemo_temperatureStats_t { /*! @brief retVal from API rlRfTempData_t - can be used to know if values in temperatureReport are valid */ int32_t tempReportValid; /*! @brief detailed temperature report - snapshot taken just before shipping data over UART */ rlRfTempData_t temperatureReport; } MmwDemo_temperatureStats; /*! * @brief * Structure holds calibration save configuration used during sensor open. * * @details * The structure holds calibration save configuration. */ typedef struct MmwDemo_calibDataHeader_t { /*! @brief Magic word for calibration data header */ uint32_t magic; /*! @brief Header length */ uint32_t hdrLen; /*! @brief mmwLink version */ rlSwVersionParam_t linkVer; /*! @brief RadarSS version */ rlFwVersionParam_t radarSSVer; /*! @brief Data length */ uint32_t dataLen; /*! @brief data padding to make sure calib data is 8 bytes aligned */ uint32_t padding; } MmwDemo_calibDataHeader; /*! * @brief * Structure holds calibration save configuration used during sensor open. * * @details * The structure holds calibration save configuration. */ typedef struct MmwDemo_calibCfg_t { /*! @brief Calibration data header for validation read from flash */ MmwDemo_calibDataHeader calibDataHdr; /*! @brief Size of Calibraton data size includng header */ uint32_t sizeOfCalibDataStorage; /*! @brief Enable/Disable calibration save process */ uint32_t saveEnable; /*! @brief Enable/Disable calibration restore process */ uint32_t restoreEnable; /*! @brief Flash Offset to restore the data from */ uint32_t flashOffset; } MmwDemo_calibCfg; /*! * @brief * Structure holds calibration restore configuration used during sensor open. * * @details * The structure holds calibration restore configuration. */ typedef struct MmwDemo_calibData_t { /*! @brief Calibration data header for validation read from flash */ MmwDemo_calibDataHeader calibDataHdr; /*! @brief Calibration data */ rlCalibrationData_t calibData; /*! @brief Phase shift Calibration data */ rlPhShiftCalibrationData_t phaseShiftCalibData; /* Future: If more fields are added to this structure or RL definitions are changed, please add dummy padding bytes here if size of MmwDemo_calibData is not multiple of 8 bytes. */ } MmwDemo_calibData; /** * @brief * Millimeter Wave Demo MCB * * @details * The structure is used to hold all the relevant information for the * Millimeter Wave demo. */ typedef struct MmwDemo_MSS_MCB_t { /*! @brief Configuration which is used to execute the demo */ MmwDemo_Cfg cfg; /*! * @brief Handle to the SOC Module */ SOC_Handle socHandle; /*! @brief UART Logging Handle */ UART_Handle loggingUartHandle; /*! @brief UART Command Rx/Tx Handle */ UART_Handle commandUartHandle; /*! @brief This is the mmWave control handle which is used * to configure the BSS. */ MMWave_Handle ctrlHandle; /*! @brief ADCBuf driver handle */ ADCBuf_Handle adcBufHandle; /*! @brief Handle of the EDMA driver, used for CBUFF */ EDMA_Handle edmaHandle; /*! @brief Number of EDMA event Queues (tc) */ uint8_t numEdmaEventQueues; /*! @brief True if need to poll for edma error (because error interrupt is not * connected to the CPU on the device */ _Bool isPollEdmaError; /*! @brief True if need to poll for edma transfer controller error * because at least one of the transfer controller error interrupts * are not connected to the CPU on the device */ _Bool isPollEdmaTransferControllerError; /*! @brief EDMA error Information when there are errors like missing events */ EDMA_errorInfo_t EDMA_errorInfo; /*! @brief EDMA transfer controller error information. */ EDMA_transferControllerErrorInfo_t EDMA_transferControllerErrorInfo; /*! @brief DPM Handle */ DPM_Handle objDetDpmHandle; /*! @brief Object Detection DPC common configuration */ MmwDemo_DPC_ObjDet_CommonCfg objDetCommonCfg; /*! @brief Object Detection DPC subFrame configuration */ MmwDemo_SubFrameCfg subFrameCfg[(4U)]; /*! @brief sub-frame stats */ MmwDemo_SubFrameStats subFrameStats[(4U)]; /*! @brief Demo Stats */ MmwDemo_MSS_Stats stats; /*! @brief Task handle storage */ MmwDemo_taskHandles taskHandles; /*! @brief Rf frequency scale factor, = 2.7 for 60GHz device, = 3.6 for 76GHz device */ double rfFreqScaleFactor; /*! @brief Semaphore handle to signal DPM started from DPM report function */ ti_sysbios_knl_Semaphore_Handle DPMstartSemHandle; /*! @brief Semaphore handle to signal DPM stopped from DPM report function. */ ti_sysbios_knl_Semaphore_Handle DPMstopSemHandle; /*! @brief Semaphore handle to signal DPM ioctl from DPM report function. */ ti_sysbios_knl_Semaphore_Handle DPMioctlSemHandle; /*! @brief Sensor state */ MmwDemo_SensorState sensorState; /*! @brief Tracks the number of sensor start */ uint32_t sensorStartCount; /*! @brief Tracks the number of sensor sop */ uint32_t sensorStopCount; /*! @brief CQ monitor configuration - Signal Image band data */ rlSigImgMonConf_t cqSigImgMonCfg[(4U)]; /*! @brief CQ monitor configuration - Saturation data */ rlRxSatMonConf_t cqSatMonCfg[(4U)]; /*! @brief Analog monitor bit mask */ MmwDemo_AnaMonitorCfg anaMonCfg; /*! @brief this structure is used to hold all the relevant information for the mmw demo LVDS stream*/ MmwDemo_LVDSStream_MCB_t lvdsStream; /*! @brief this structure is used to hold all the relevant information for the temperature report*/ MmwDemo_temperatureStats temperatureStats; /*! @brief Calibration cofiguration for save/restore */ MmwDemo_calibCfg calibCfg; /*! @brief Flag indicating if @ref anaMonCfg is pending processing. */ uint8_t isAnaMonCfgPending : 1; /*! @brief Flag indicating if @ref calibCfg is pending processing. */ uint8_t isCalibCfgPending : 1; } MmwDemo_MSS_MCB; /************************************************************************** *************************** Extern Definitions *************************** **************************************************************************/ /* Functions to handle the actions need to move the sensor state */ extern int32_t MmwDemo_openSensor(_Bool isFirstTimeOpen); extern int32_t MmwDemo_configSensor(void); extern int32_t MmwDemo_startSensor(void); extern void MmwDemo_stopSensor(void); /* functions to manage the dynamic configuration */ extern uint8_t MmwDemo_isAllCfgInPendingState(void); extern uint8_t MmwDemo_isAllCfgInNonPendingState(void); extern void MmwDemo_resetStaticCfgPendingState(void); extern void MmwDemo_CfgUpdate(void *srcPtr, uint32_t offset, uint32_t size, int8_t subFrameNum); /* Debug Functions */ extern void _MmwDemo_debugAssert(int32_t expression, const char *file, int32_t line); /** * @file mmwdemo_flash.h * * @brief * This is used to abstract the mmWave demo QSPI flash API definitions. * * \par * NOTE: * (C) Copyright 2020 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*********************************************************************************************** * mmwDemo Flash module error ***********************************************************************************************/ /** * @brief Error Code: Invalid variable */ /** * @brief Error Code: receive error when accessing QSPI interface */ /** * @brief Error Code: receive error when accessing QSPI Flash */ /*********************************************************************************************** * Flash API: to access QSPI Flash from mmw Demo ***********************************************************************************************/ extern int32_t mmwDemo_flashInit(void); extern int32_t mmwDemo_flashRead(uint32_t flashAddr, uint32_t *readBuf, uint32_t size); extern int32_t mmwDemo_flashWrite(uint32_t flashAddr, uint32_t *writeBuf, uint32_t size); extern int32_t mmwDemo_flashEraseOneSector(uint32_t flashAddr); extern int32_t mmwDemo_flashSetReadMode(void); /* Profiler Include Files */ /** * @file cycle_profiler.h * * @brief * Portable CPU Cycle profiling APIs. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** ============================================================================ * @defgroup CYCLEPROFILERP_OSAL CycleprofilerP OSAL Porting Layer * * @brief Cycle profiler module to measure CPU cycles * * Cycle profiler module gives APIs that allows a segment of code to be profiled * with the APIs to measure CPU cycles. * ============================================================================ */ /** @defgroup CYCLEPROFILERP_OSAL_EXTERNAL_FUNCTION CycleprofilerP OSAL External Functions @ingroup CYCLEPROFILERP_OSAL @brief * The section documents the external API exposed by the OSAL Porting layer. */ /*! * @brief Function to initialize cycle profiler * * \ingroup CYCLEPROFILERP_OSAL_EXTERNAL_FUNCTION */ extern void CycleprofilerP_init(void); /*! * @brief Function to delete a semaphore. * * @return Get CPU cycle count time stamp * * \ingroup CYCLEPROFILERP_OSAL_EXTERNAL_FUNCTION */ extern uint32_t CycleprofilerP_getTimeStamp(void); static inline void Cycleprofiler_init(void) { CycleprofilerP_init(); } /** * @file rtrimutils.h * * @brief * This is the header file for the APIs which allow applications * to set and retrieve the RTRIM_REP_APLL(27:31) field in the * CLK_CTRL_REG2_APLL register. * * \par * NOTE: * (C) Copyright 2016 Texas Instruments, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Analog Functions */ /** * @b Description * @n * Pass Trim Value to APLL * Swing voltage is updated by writing to RTRM_REP_APLL field in CLK_CTRL_REG2_APLL register * Set and reset MSS memory region accordingly * * @param[in] uint8_t trimValue * Trim Value * * @retval * Success - 0 * @retval * Error - <0 */ int32_t rtrim_set(uint8_t); /** * @b Description * @n * Read Trim Value from APLL * Value should be 0x12 at reset. * Set and reset MSS memory region accordingly * * @param[in] * * @retval * uint8_t trimValue * @retval * Error - <0 */ int32_t rtrim_get(); typedef uint8_t data_u8[1]; void functionname( uint8_t *aaaa); void functionname( data_u8 *aaaa) { } void main() { }