/*!
 * File generated by platform wizard. DO NOT MODIFY
 *
 */

metaonly module Platform inherits xdc.platform.IPlatform {

    config ti.platforms.generic.Platform.Instance CPU =
        ti.platforms.generic.Platform.create("CPU", {
            clockRate:      1000,                                       
            catalogName:    "ti.catalog.c6000",
            deviceName:     "TMS320C6678",
            customMemoryMap:
           [          
                ["MSMCSRAM", 
                     {
                        name: "MSMCSRAM",
                        base: 0x0c000000,                    
                        len: 0x00400000,                    
                        space: "code/data",
                        access: "RWX",
                     }
                ],
                ["L1DSRAM", 
                     {
                        name: "L1DSRAM",
                        base: 0x00F00000,                    
                        len: 0x00008000,                    
                        space: "data",
                        access: "RW",
                     }
                ],
                ["L1PSRAM", 
                     {
                        name: "L1PSRAM",
                        base: 0x00E00000,                    
                        len: 0x00008000,                    
                        space: "code",
                        access: "RWX",
                     }
                ],
                ["L2SRAM", 
                     {
                        name: "L2SRAM",
                        base: 0x00800000,                    
                        len: 0x19F00,                    
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["L2HEAP", 
                     {
                        name: "L2HEAP",
                        base: 0x00819F00,                    
                        len: 0x46100,                    
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["DDR", 
                     {
                        name: "DDR",
                        base: 0x81000000,                    
                        len: 0x0F3C0000,                    
                        space: "code/data",
                        access: "RWX",
                     }
                ],
                ["DDRUNCACHED", 
                     {
                        name: "DDRUNCACHED",
                        base: 0x80000000,                    
                        len: 0x00fffe00,                    
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["DDRCINE", 
                     {
                        name: "DDRCINE",
                        base: 0x903C0000,                    
                        len: 0x0FC40000,                    
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["IBL_VERSIONS", 
                     {
                        name: "IBL_VERSIONS",
                        base: 0x80fffe00,                    
                        len: 0x100,                    
                        space: "data",
                        access: "RW",
                     }
                ],
           ],
          l2Mode: "128k",
          l1PMode: "32k",
          l1DMode: "32k",

    });
    
instance :
    
    override config string codeMemory  = "MSMCSRAM";   
    override config string dataMemory  = "L2SRAM";                                
    override config string stackMemory = "L2SRAM";

    config String l2Mode = "128k";
    config String l1PMode = "32k";
    config String l1DMode = "32k";
}
