
`$args[1]`

/*
 */
    .heapll2:                       load >> L2HEAP       align = 0x8
    .text:                          load >> MSMCSRAM     align = 0x8
    .vecs:                          load >> MSMCSRAM     align = 0x8
    .sect_SL2:                      load >  MSMCSRAM     align = 0x8
    .sect_SL2_EDMA:                 load >> MSMCSRAM     align = 0x8
    .cinit:                         load >  DDR          align = 0x8
    .const:                         load >  DDR          align = 0x8
    .sect_DDR2:                     load >  DDR          align = 0x8
    .sect_DDR2_code:                load >  DDR          align = 0x8
    .sect_colorflow_ddr:            load >> DDR          align = 0x80
    .sect_doppler_output:           load >> DDR          align = 0x8
    .sect_doppler_data:             load >> DDR          align = 0x8
    .sect_cine_data:                load >> DDRCINE      align = 0x8      
    .sect_mem_ext                   load >> DDR          align = 0x8

    GROUP: load = L2SRAM
    {
        .far                            {} align = 0x8
        .cio:                           {} align = 0x8
        .sysmem:                        {} align = 0x8
        .bss:                           {} align = 0x8
        .pinit:                         {} align = 0x8
        .switch:                        {} align = 0x8
        .data:                          {} align = 0x8
        .stack:                         {} align = 0x8
        .sect_LL2:                      {} align = 0x8
        .sect_doppler_data_LL2:         {} align = 0x8
        .args:							{} align = 0x8
    }
    GROUP: load = DDRUNCACHED
    {
        .sect_host_interface_struct:    {} align = 0x8
        .sect_params:                   {} align = 0x8
        .sect_params_misc:              {} align = 0x8
        .sect_error:                    {} align = 0x8
        .sect_noncached_DDR2            {} align = 0x8
        .sect_diagnostics               {} align = 0x8
        .sect_dup_vers_struct           {} align = 0x8
    }
    GROUP: load = IBL_VERSIONS
    {
        .sect_ibl_version               {} align = 0x8
        
        // .sect_top_of_DDR_vars MUST be the last section in IBL_VERSIONS
        //    That section is used to calculate the bottom of the DDR heap
        .sect_top_of_DDR_vars:          {} align = 0x8
    }
    /*Placing _c_int00 on 10-bit aligned address to support DSP warm reset through PSC registers.*/
    boot palign(0x400)
    {
        -l boot.ae66<boot.oe66>(.text:_c_int00)
    } > DDR

    /* overlap Bootloader with the uninitialized section */
    UNION: run = L2SRAM 
    {
        .boot_entry {}
        .far {}
    }

    UNION: run = L2SRAM 
    {
        .sect_Core0_LL2 {}
        .sect_RSC_LL2 {}
        .sect_Doppler_LL2 {}
    }


/* -----------------------------------------------
 *        Revision History
 * -----------------------------------------------
 * 10-Jun-2014 wrz: Modified further for M2HF/6678, taking into account the standard memory segment names for that 
 *                  platform (as created), and modifying the custom ones accordingly.
 *                  NOTE: I've mapped the existing M2 memory sections onto the 
 *                        memory segments I defined as the M2HF platform in CCS. Note that several
 *                        of the memory sections are now misnomers. That is, .sect_DDR2 doesn't really
 *                        point to DDR2, because this system has DDR3. We could change that if the 
 *                        misnomers bother anyone. I recommend that, if we do go through the entire 
 *                        code base to remove references to _DDR2 (there's a couple hundred of them), 
 *                        we simplify them to _DDR rather than renaming them to _DDR3, or we'll have 
 *                        to do the entire exercise over again when DDR4 becomes the standard.
 *       NOTE: Note new .sect_extended code/data section. In the new 
 *           M2HF platform, that memory is defined as the top 1GB of DDR3, and should be
 *           considered to be reserve memory. That means it should be unused until the DSP
 *           group as a whole decides on the best way to use it. Don't just use it.
 * 06-Jun-2014 wrz: Modified for M2HF/6678
 * 23-Oct-2012 wrz: removed .sect_color_LL2. Now Color Wall Filter and MP_FIR can co-exist in one core with 
 *                  any other cluster without fear of overlapping memory sections causing trouble.
 * 19-Sep-2012  ll: Added new memory section: .sect_DDR2_code
 * 24-Aug-2012 dwu: Added 256 MB to the DDR2 Cine memory 
 * 20-Jul-2012 dwu: Updated IPC, XDC and SYS/BIOS to ipc_1_24_03_32, xdctools_3_23_02_47 and bios_6_33_05_46
 * 30-Jan-2012 wrz: Added .sect_top_of_DDR_vars. This is to make sure that the STATIC value in
 *                  M2_EVM6472.cfg that controls the base of DDR2 heap memory, namely Program.global.CFG_DDR2_BASE,
 *                  is AFTER the statically-allocate memory of the program. I define a variable in the
 *                  new section, and compare its address to the base of the newly created DDR2 heap
 *                  in HeapMemMgr_create(). A better solution would be one which adjusts this value at
 *                  compile time (i.e., linker-generated), but that does not appear to be easy to do. The
 *                  next best thing, which I've done in that function, is to fatal assert if there's an
 *                  overlap. 
 * 27-Oct-2011 wrz: In the light of core-overlapping DDR access issue, set .sect_colorflow_ddr to
 *                  128-byte alignment, which is one full cache line. This will make all accesses
 *                  within that section cache-independent of all other cores. This should be done 
 *                  for all DDR sections that are accessed by subordinate cores.
 * 26-Oct-2011 dwu: Increase SL2 heap size by 64KB. 
 * 19-Sep-2011 dwu: Updated CGT, IPC and SYS/BIOS to cgt_7_2_6, ipc_1_22_03_23 and bios_6_31_04_27 
 * 25-Aug-2011 ejp: Increased DDR2HOST section to accomodate new CW resampling filter coeffs.
 * 17-Aug-2011 dwu: Removed unused/duplicated memory sections 
 * 18-Mar-2011 dwu: Added DDR2CINE sections (128MB) and reduce the size of DDR2 heap to 100MB 
 * 25-mar-2011 ejp: - added boot section to memory, but could not get .text:boot_entry to work
 *                  (the syntax somehow destroys the following sections).
 *                  - added host section for spDspInterface.
 * 03-Mar-2011 dwu: created
 */






