//############################################################################# // // FILE: stl_can.c // // TITLE: // //############################################################################# // $TI Release: $ // $Release Date: $ // $Copyright: $ //############################################################################# // // Includes // //############################################################################# // // FILE: stl_crc.h // // TITLE: // //############################################################################# // $TI Release: $ // $Release Date: $ // $Copyright: $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** // // Included Files // /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /*****************************************************************************/ /* STDINT.H v15.12.3 */ /* */ /* Copyright (c) 2002-2016 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /* 7.18.1.1 Exact-width integer types */ typedef int int16_t; typedef unsigned int uint16_t; typedef long int32_t; typedef unsigned long uint32_t; typedef long long int64_t; typedef unsigned long long uint64_t; /* 7.18.1.2 Minimum-width integer types */ typedef int16_t int_least8_t; typedef uint16_t uint_least8_t; typedef int16_t int_least16_t; typedef uint16_t uint_least16_t; typedef int32_t int_least32_t; typedef uint32_t uint_least32_t; typedef int64_t int_least64_t; typedef uint64_t uint_least64_t; /* 7.18.1.3 Fastest minimum-width integer types */ typedef int16_t int_fast8_t; typedef uint16_t uint_fast8_t; typedef int16_t int_fast16_t; typedef uint16_t uint_fast16_t; typedef int32_t int_fast32_t; typedef uint32_t uint_fast32_t; typedef int64_t int_fast64_t; typedef uint64_t uint_fast64_t; /* 7.18.1.4 Integer types capable of holding object pointers */ typedef long intptr_t; typedef unsigned long uintptr_t; /* 7.18.1.5 Greatest-width integer types */ typedef long long intmax_t; typedef unsigned long long uintmax_t; /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ /* 7.18.2 Limits of specified width integer types */ /* 7.18.3 Limits of other integer types */ /* 7.18.4.1 Macros for minimum-width integer constants */ /* There is a defect report filed against the C99 standard concerning how the (U)INTN_C macros should be implemented. Please refer to -- http://wwwold.dkuug.dk/JTC1/SC22/WG14/www/docs/dr_209.htm for more information. These macros are implemented according to the suggestion given at this web site. */ /* 7.18.4.2 Macros for greatest-width integer constants */ //########################################################################### // // FILE: hw_types.h // // TITLE: Type definitions used in driverlib functions. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // Macros for hardware access // //***************************************************************************** //***************************************************************************** // // SUCCESS and FAILURE for API return value // //***************************************************************************** //***************************************************************************** // // Extern compiler intrinsic prototypes. See compiler User's Guide for details. // These are provided to satisfy static analysis tools. The #ifndef is required // because the '&' is for a C++-style reference, and although it is the correct // prototype, it will not build in C code. // //***************************************************************************** //############################################################################# // // FILE: stl_util.h // // TITLE: // //############################################################################# // $TI Release: $ // $Release Date: $ // $Copyright: $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** // // Includes // //########################################################################### // // FILE: sysctl.h // // TITLE: C28x system control driver. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup sysctl_api SysCtl //! \brief The System Control module is used for miscellaneous system //! configurations. //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_memmap.h // // TITLE: Macros defining the memory map of the C28x. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the base address of the memories and // peripherals. // //***************************************************************************** //########################################################################### // // FILE: hw_nmi.h // // TITLE: Definitions for the NMI registers. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the NMI register offsets // //***************************************************************************** // Clear) //***************************************************************************** // // The following are defines for the bit fields in the NMICFG register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the NMIFLG register // //***************************************************************************** // Flag // Flag // Flag // Indication Flag //***************************************************************************** // // The following are defines for the bit fields in the NMIFLGCLR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the NMIFLGFRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the NMISHDFLG register // //***************************************************************************** //########################################################################### // // FILE: hw_sysctl.h // // TITLE: Definitions for the SYSCTL registers. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the SYSCTL register offsets // //***************************************************************************** // registers // Identification Number // Identification Number // Information // Block Customization // Customization // Customization // Customization // Customization // Customization // Customization // Customization // Customization // Customization // Customization // Customization // Customization // Modules Customization // Modules Customization // Modules Customization // SRAM Customization // SRAM Customization // Customization // register // Reset register // register // register // register // register // register // register // register // register // register // register // register // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // common peripherals // secondary C28x CPUs // secondary C28x CPUs // Register // register-1 // register-2 // register-3 // register // Select register // Selet register // register // Prescalar // Register // Register // Address register // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // Registers // register for common peripherals: // Selects between CLA & DMA // registers // registers // functionality control register // Register // Register // Select Lock Register // Select Lock Register // Select Register-1 // Select Register-2 // Select Register-1 // Select Register-2 // Register // Select Register // Lock register //***************************************************************************** // // The following are defines for the bit fields in the DEVCFGLOCK1 register // //***************************************************************************** // register // register // register // register // register //***************************************************************************** // // The following are defines for the bit fields in the PARTIDL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PARTIDH register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC5 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC10 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC11 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC12 register // //***************************************************************************** // USB_A Module //***************************************************************************** // // The following are defines for the bit fields in the DC13 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC14 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC15 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC17 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC18 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC19 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the DC20 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PERCNF1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the FUSEERR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES11 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES13 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES14 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SOFTPRES16 register // //***************************************************************************** // bit // bit // bit //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL5 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL11 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL12 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSEL14 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPU2RESCTL register // //***************************************************************************** // this register //***************************************************************************** // // The following are defines for the bit fields in the RSTSTAT register // //***************************************************************************** // CPU2.NMIWD reset was issued to CPU2 // reset was issued to CPU2 // reset was issued to CPU2 //***************************************************************************** // // The following are defines for the bit fields in the LPMSTAT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CLKSEM register // //***************************************************************************** // Ownership by CPU1 or CPU2 // this register //***************************************************************************** // // The following are defines for the bit fields in the CLKCFGLOCK1 register // //***************************************************************************** // register // register // register // register // register // register // register // register // register // register // register // register //***************************************************************************** // // The following are defines for the bit fields in the CLKSRCCTL1 register // //***************************************************************************** // Off Bit //***************************************************************************** // // The following are defines for the bit fields in the CLKSRCCTL2 register // //***************************************************************************** // Bit // Bit //***************************************************************************** // // The following are defines for the bit fields in the CLKSRCCTL3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SYSPLLCTL1 register // //***************************************************************************** // in the PLLSYSCLK path //***************************************************************************** // // The following are defines for the bit fields in the SYSPLLMULT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SYSPLLSTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the AUXPLLCTL1 register // //***************************************************************************** // in the AUXPLLCLK path //***************************************************************************** // // The following are defines for the bit fields in the AUXPLLMULT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the AUXPLLSTS register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the SYSCLKDIVSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the AUXCLKDIVSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PERCLKDIVSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the XCLKOUTDIVSEL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the LOSPCP register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the MCDCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the X1CNT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CPUSYSLOCK1 register // //***************************************************************************** // register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the IORESTOREADDR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PIEVERRADDR register // //***************************************************************************** // Handler Routine Address //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR0 register // //***************************************************************************** // sync //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR2 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR3 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR4 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR6 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR7 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR8 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR9 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR10 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR11 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR12 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR13 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR14 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the PCLKCR16 register // //***************************************************************************** // Bit // Bit // Bit //***************************************************************************** // // The following are defines for the bit fields in the SECMSEL register // //***************************************************************************** // VBUS32_1 Bridge // VBUS32_2 Bridge //***************************************************************************** // // The following are defines for the bit fields in the LPMCR register // //***************************************************************************** // Qualification Setting // STANDBY // mode during HIB //***************************************************************************** // // The following are defines for the bit fields in the GPIOLPMSEL0 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the GPIOLPMSEL1 register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the TMR2CLKCTL register // //***************************************************************************** // Select Bit // Value //***************************************************************************** // // The following are defines for the bit fields in the RESC register // //***************************************************************************** // Bit // Bit // Bit // Indication Bit // Indication Bit // Indication Bit // Indication Bit //***************************************************************************** // // The following are defines for the bit fields in the SCSR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDCNTR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDKEY register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDCR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the WDWCR register // //***************************************************************************** // Windowed Watchdog // functionality //***************************************************************************** // // The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register // //***************************************************************************** // bit // bit //***************************************************************************** // // The following are defines for the bit fields in the DMACHSRCSELLOCK register // //***************************************************************************** // bit // bit //***************************************************************************** // // The following are defines for the bit fields in the CLA1TASKSRCSEL1 register // //***************************************************************************** // for TASK1 of CLA1 // for TASK2 of CLA1 // for TASK3 of CLA1 // for TASK4 of CLA1 //***************************************************************************** // // The following are defines for the bit fields in the CLA1TASKSRCSEL2 register // //***************************************************************************** // for TASK5 of CLA1 // for TASK6 of CLA1 // for TASK7 of CLA1 // for TASK8 of CLA1 //***************************************************************************** // // The following are defines for the bit fields in the DMACHSRCSEL1 register // //***************************************************************************** // Source CH1 of DMA // Source CH2 of DMA // Source CH3 of DMA // Source CH4 of DMA //***************************************************************************** // // The following are defines for the bit fields in the DMACHSRCSEL2 register // //***************************************************************************** // Source CH5 of DMA // Source CH6 of DMA //***************************************************************************** // // The following are defines for the bit fields in the SYNCSELECT register // //***************************************************************************** // EPWM4 // EPWM7 // EPWM10 // ECAP1 // ECAP4 //***************************************************************************** // // The following are defines for the bit fields in the ADCSOCOUTSELECT register // //***************************************************************************** // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCAO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO // ADCSOCBO //***************************************************************************** // // The following are defines for the bit fields in the SYNCSOCLOCK register // //***************************************************************************** // bit //########################################################################### // // FILE: cpu.h // // TITLE: Useful C28x CPU defines. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** // // External reference to the interrupt flag register (IFR) register // extern __cregister volatile uint16_t IFR; // // External reference to the interrupt enable register (IER) register // extern __cregister volatile uint16_t IER; // // Define to enable interrupts // // // Define to disable interrupts // // // Define to enable debug events // // // Define to disable debug events // // // Define to allow writes to protected registers // // // Define to disable writes to protected registers // // // Define for emulation stop // // // Define for emulation stop // // // Define for no operation // // // Define for putting processor into a low-power mode // //***************************************************************************** // // Extern compiler intrinsic prototypes. See compiler User's Guide for details. // //***************************************************************************** extern void __eallow(void); extern void __edis(void); //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //########################################################################### // // FILE: debug.h // // TITLE: Assert definition macro for debug. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // Prototype for the function that is called when an invalid argument is passed // to an API. This is only used when doing a DEBUG build. It is the // application's responsibility to define the __error__ function. // //***************************************************************************** extern void __error__(char *filename, uint32_t line); //***************************************************************************** // // The ASSERT macro, which does the actual assertion checking. Typically, this // will be for procedure arguments. // //***************************************************************************** //***************************************************************************** // // Defines for system control functions. Not intended for use by application // code. // //***************************************************************************** // Shifted pattern for WDCR register's WDCHK field. // Keys for WDKEY field. The first enables resets and the second resets. // Values to help decode peripheral parameter // LPM defines for LPMCR.LPM //! Bit shift for DAC to configure the CPUSEL register // Default internal oscillator frequency, 10 MHz // Mask for SYNCSELECT.SYNCIN //***************************************************************************** // // The following are values that can be passed to the SysCtl_setClock() API as // the config parameter. // //***************************************************************************** // System clock divider (SYSDIV) //! Macro to format system clock divider value. x must be 1 or even values up //! to 126. // Integer multiplier (IMULT) //! Macro to format integer multiplier value. x is a number from 1 to 127. //! // Fractional multiplier (FMULT) // Oscillator source // Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(), // and SysCtl_turnOffOsc() functions as the oscSource parameter. //! Internal oscillator INTOSC2 //! External oscillator (XTAL) in crystal mode //! Internal oscillator INTOSC1 //! AUXCLKIN from GPIO // Enable/disable PLL //! INTOSC2 as auxiliary clock input //! External Oscillator (XTAL) as auxiliary clock input //! AUXCLKIN (from GPIO) as auxiliary clock input //! auxiliary PLL fractional multiplier of 0 //! auxiliary PLL fractional multiplier of 0.25 //! auxiliary PLL fractional multiplier of 0.5 //! auxiliary PLL fractional multiplier of 0.75 //! auxiliary PLL divide by 1 //! auxiliary PLL divide by 2 //! auxiliary PLL divide by 4 //! auxiliary PLL divide by 8 //! x shall be assigned with one of the above values //! Configure CLA as the secondary master //! Configure DMA as the secondary master //***************************************************************************** // // Values that can be passed to SysCtl_clearNMIStatus(), // SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and // SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by // SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus(). // //***************************************************************************** //***************************************************************************** // // The following are values that can be passed to the SysCtl_clearResetCause() // API as rstCauses or returned by the SysCtl_getResetCause() API. // //***************************************************************************** //***************************************************************************** // // The following values define the adcsocSrc parameter for // SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource(). // //***************************************************************************** // ADCSOCAO // ADCSOCBO //***************************************************************************** // //! The following are values that can be passed to SysCtl_enablePeripheral() //! and SysCtl_disablePeripheral() as the \e peripheral parameter. // //***************************************************************************** typedef enum { // PCLKCR0 SYSCTL_PERIPH_CLK_CLA1 = 0x0000, //!< CLA1 clock SYSCTL_PERIPH_CLK_DMA = 0x0200, //!< DMA clock SYSCTL_PERIPH_CLK_TIMER0 = 0x0300, //!< CPUTIMER0 clock SYSCTL_PERIPH_CLK_TIMER1 = 0x0400, //!< CPUTIMER1 clock SYSCTL_PERIPH_CLK_TIMER2 = 0x0500, //!< CPUTIMER2 clock SYSCTL_PERIPH_CLK_HRPWM = 0x1000, //!< HRPWM clock SYSCTL_PERIPH_CLK_TBCLKSYNC = 0x1200, //!< ePWM time base clock sync SYSCTL_PERIPH_CLK_GTBCLKSYNC = 0x1300, //!< ePWM global time base sync // PCLKCR1 SYSCTL_PERIPH_CLK_EMIF1 = 0x0001, //!< EMIF1 clock SYSCTL_PERIPH_CLK_EMIF2 = 0x0101, //!< EMIF2 clock // PCLKCR2 SYSCTL_PERIPH_CLK_EPWM1 = 0x0002, //!< ePWM1 clock SYSCTL_PERIPH_CLK_EPWM2 = 0x0102, //!< ePWM2 clock SYSCTL_PERIPH_CLK_EPWM3 = 0x0202, //!< ePWM3 clock SYSCTL_PERIPH_CLK_EPWM4 = 0x0302, //!< ePWM4 clock SYSCTL_PERIPH_CLK_EPWM5 = 0x0402, //!< ePWM5 clock SYSCTL_PERIPH_CLK_EPWM6 = 0x0502, //!< ePWM6 clock SYSCTL_PERIPH_CLK_EPWM7 = 0x0602, //!< ePWM7 clock SYSCTL_PERIPH_CLK_EPWM8 = 0x0702, //!< ePWM8 clock SYSCTL_PERIPH_CLK_EPWM9 = 0x0802, //!< ePWM9 clock SYSCTL_PERIPH_CLK_EPWM10 = 0x0902, //!< ePWM10 clock SYSCTL_PERIPH_CLK_EPWM11 = 0x0A02, //!< ePWM11 clock SYSCTL_PERIPH_CLK_EPWM12 = 0x0B02, //!< ePWM12 clock // PCLKCR3 SYSCTL_PERIPH_CLK_ECAP1 = 0x0003, //!< eCAP1 clock SYSCTL_PERIPH_CLK_ECAP2 = 0x0103, //!< eCAP2 clock SYSCTL_PERIPH_CLK_ECAP3 = 0x0203, //!< eCAP3 clock SYSCTL_PERIPH_CLK_ECAP4 = 0x0303, //!< eCAP4 clock SYSCTL_PERIPH_CLK_ECAP5 = 0x0403, //!< eCAP5 clock SYSCTL_PERIPH_CLK_ECAP6 = 0x0503, //!< eCAP6 clock // PCLKCR4 SYSCTL_PERIPH_CLK_EQEP1 = 0x0004, //!< eQEP1 clock SYSCTL_PERIPH_CLK_EQEP2 = 0x0104, //!< eQEP2 clock SYSCTL_PERIPH_CLK_EQEP3 = 0x0204, //!< eQEP3 clock // PCLKCR5 // Reserved // PCLKCR6 SYSCTL_PERIPH_CLK_SD1 = 0x0006, //!< SDFM1 clock SYSCTL_PERIPH_CLK_SD2 = 0x0106, //!< SDFM2 clock // PCLKCR7 SYSCTL_PERIPH_CLK_SCIA = 0x0007, //!< SCIA clock SYSCTL_PERIPH_CLK_SCIB = 0x0107, //!< SCIB clock SYSCTL_PERIPH_CLK_SCIC = 0x0207, //!< SCIC clock SYSCTL_PERIPH_CLK_SCID = 0x0307, //!< SCID clock // PCLKCR8 SYSCTL_PERIPH_CLK_SPIA = 0x0008, //!< SPIA clock SYSCTL_PERIPH_CLK_SPIB = 0x0108, //!< SPIB clock SYSCTL_PERIPH_CLK_SPIC = 0x0208, //!< SPIC clock // PCLKCR9 SYSCTL_PERIPH_CLK_I2CA = 0x0009, //!< I2CA clock SYSCTL_PERIPH_CLK_I2CB = 0x0109, //!< I2CB clock // PCLKCR10 SYSCTL_PERIPH_CLK_CANA = 0x000A, //!< CANA clock SYSCTL_PERIPH_CLK_CANB = 0x010A, //!< CANB clock // PCLKCR11 SYSCTL_PERIPH_CLK_MCBSPA = 0x000B, //!< McBSPA clock SYSCTL_PERIPH_CLK_MCBSPB = 0x010B, //!< McBSPB clock SYSCTL_PERIPH_CLK_USBA = 0x100B, //!< USBA clock // PCLKCR12 SYSCTL_PERIPH_CLK_UPPA = 0x000C, //!< uPPA clock // PCLKCR13 SYSCTL_PERIPH_CLK_ADCA = 0x000D, //!< ADCA clock SYSCTL_PERIPH_CLK_ADCB = 0x010D, //!< ADCB clock SYSCTL_PERIPH_CLK_ADCC = 0x020D, //!< ADCC clock SYSCTL_PERIPH_CLK_ADCD = 0x030D, //!< ADCD clock // PCLKCR14 SYSCTL_PERIPH_CLK_CMPSS1 = 0x000E, //!< CMPSS1 clock SYSCTL_PERIPH_CLK_CMPSS2 = 0x010E, //!< CMPSS2 clock SYSCTL_PERIPH_CLK_CMPSS3 = 0x020E, //!< CMPSS3 clock SYSCTL_PERIPH_CLK_CMPSS4 = 0x030E, //!< CMPSS4 clock SYSCTL_PERIPH_CLK_CMPSS5 = 0x040E, //!< CMPSS5 clock SYSCTL_PERIPH_CLK_CMPSS6 = 0x050E, //!< CMPSS6 clock SYSCTL_PERIPH_CLK_CMPSS7 = 0x060E, //!< CMPSS7 clock SYSCTL_PERIPH_CLK_CMPSS8 = 0x070E, //!< CMPSS8 clock // PCLKCR15 // Reserved // PCLKCR16 SYSCTL_PERIPH_CLK_DACA = 0x1010, //!< DACA clock SYSCTL_PERIPH_CLK_DACB = 0x1110, //!< DACB clock SYSCTL_PERIPH_CLK_DACC = 0x1210, //!< DACC clock } SysCtl_PeripheralPCLOCKCR; //***************************************************************************** // //! The following are values that can be passed to SysCtl_resetPeripheral() as //! the \e peripheral parameter. // //***************************************************************************** typedef enum { // SOFTPRES0 SYSCTL_PERIPH_RES_CPU1_CLA1 = 0x0000, //!< Reset CPU1 CLA1 SYSCTL_PERIPH_RES_CPU2_CLA1 = 0x0200, //!< Reset CPU2 CLA1 // SOFTPRES1 SYSCTL_PERIPH_RES_EMIF1 = 0x0001, //!< Reset EMIF1 SYSCTL_PERIPH_RES_EMIF2 = 0x0101, //!< Reset EMIF2 // SOFTPRES2 SYSCTL_PERIPH_RES_EPWM1 = 0x0002, //!< Reset ePWM1 SYSCTL_PERIPH_RES_EPWM2 = 0x0102, //!< Reset ePWM2 SYSCTL_PERIPH_RES_EPWM3 = 0x0202, //!< Reset ePWM3 SYSCTL_PERIPH_RES_EPWM4 = 0x0302, //!< Reset ePWM4 SYSCTL_PERIPH_RES_EPWM5 = 0x0402, //!< Reset ePWM5 SYSCTL_PERIPH_RES_EPWM6 = 0x0502, //!< Reset ePWM6 SYSCTL_PERIPH_RES_EPWM7 = 0x0602, //!< Reset ePWM7 SYSCTL_PERIPH_RES_EPWM8 = 0x0702, //!< Reset ePWM8 SYSCTL_PERIPH_RES_EPWM9 = 0x0802, //!< Reset ePWM9 SYSCTL_PERIPH_RES_EPWM10 = 0x0902, //!< Reset ePWM10 SYSCTL_PERIPH_RES_EPWM11 = 0x0A02, //!< Reset ePWM11 SYSCTL_PERIPH_RES_EPWM12 = 0x0B02, //!< Reset ePWM12 // SOFTPRES3 SYSCTL_PERIPH_RES_ECAP1 = 0x0003, //!< Reset eCAP1 SYSCTL_PERIPH_RES_ECAP2 = 0x0103, //!< Reset eCAP2 SYSCTL_PERIPH_RES_ECAP3 = 0x0203, //!< Reset eCAP3 SYSCTL_PERIPH_RES_ECAP4 = 0x0303, //!< Reset eCAP4 SYSCTL_PERIPH_RES_ECAP5 = 0x0403, //!< Reset eCAP5 SYSCTL_PERIPH_RES_ECAP6 = 0x0503, //!< Reset eCAP6 // SOFTPRES4 SYSCTL_PERIPH_RES_EQEP1 = 0x0004, //!< Reset eQEP1 SYSCTL_PERIPH_RES_EQEP2 = 0x0104, //!< Reset eQEP2 SYSCTL_PERIPH_RES_EQEP3 = 0x0204, //!< Reset eQEP3 // SOFTPRES5 // Reserved // SOFTPRES6 SYSCTL_PERIPH_RES_SD1 = 0x0006, //!< Reset SDFM1 SYSCTL_PERIPH_RES_SD2 = 0x0106, //!< Reset SDFM2 // SOFTPRES7 SYSCTL_PERIPH_RES_SCIA = 0x0007, //!< Reset SCIA SYSCTL_PERIPH_RES_SCIB = 0x0107, //!< Reset SCIB SYSCTL_PERIPH_RES_SCIC = 0x0207, //!< Reset SCIC SYSCTL_PERIPH_RES_SCID = 0x0307, //!< Reset SCID // SOFTPRES8 SYSCTL_PERIPH_RES_SPIA = 0x0008, //!< Reset SPIA SYSCTL_PERIPH_RES_SPIB = 0x0108, //!< Reset SPIB SYSCTL_PERIPH_RES_SPIC = 0x0208, //!< Reset SPIC // SOFTPRES9 SYSCTL_PERIPH_RES_I2CA = 0x0009, //!< Reset I2CA SYSCTL_PERIPH_RES_I2CB = 0x0109, //!< Reset I2CB // SOFTPRES10 // Reserved // SOFTPRES11 SYSCTL_PERIPH_RES_MCBSPA = 0x000B, //!< Reset McBSPA SYSCTL_PERIPH_RES_MCBSPB = 0x010B, //!< Reset McBSPB SYSCTL_PERIPH_RES_USBA = 0x100B, //!< Reset USBA // SOFTPRES12 // Reserved // SOFTPRES13 SYSCTL_PERIPH_RES_ADCA = 0x000D, //!< Reset ADCA SYSCTL_PERIPH_RES_ADCB = 0x010D, //!< Reset ADCB SYSCTL_PERIPH_RES_ADCC = 0x020D, //!< Reset ADCC SYSCTL_PERIPH_RES_ADCD = 0x030D, //!< Reset ADCD // SOFTPRES14 SYSCTL_PERIPH_RES_CMPSS1 = 0x000E, //!< Reset CMPSS1 SYSCTL_PERIPH_RES_CMPSS2 = 0x010E, //!< Reset CMPSS2 SYSCTL_PERIPH_RES_CMPSS3 = 0x020E, //!< Reset CMPSS3 SYSCTL_PERIPH_RES_CMPSS4 = 0x030E, //!< Reset CMPSS4 SYSCTL_PERIPH_RES_CMPSS5 = 0x040E, //!< Reset CMPSS5 SYSCTL_PERIPH_RES_CMPSS6 = 0x050E, //!< Reset CMPSS6 SYSCTL_PERIPH_RES_CMPSS7 = 0x060E, //!< Reset CMPSS7 SYSCTL_PERIPH_RES_CMPSS8 = 0x070E, //!< Reset CMPSS8 // SOFTPRES15 // Reserved // SOFTPRES16 SYSCTL_PERIPH_RES_DACA = 0x1010, //!< Reset DACA SYSCTL_PERIPH_RES_DACB = 0x1110, //!< Reset DACB SYSCTL_PERIPH_RES_DACC = 0x1210 //!< Reset DACC } SysCtl_PeripheralSOFTPRES; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_selectCPUForPeripheral() as the \e peripheral parameter. // //***************************************************************************** typedef enum { //! Configure CPU Select for EPWM SYSCTL_CPUSEL0_EPWM = 0x0U, //! Configure CPU Select for ECAP SYSCTL_CPUSEL1_ECAP = 0x1U, //! Configure CPU Select for EQEP SYSCTL_CPUSEL2_EQEP = 0x2U, //! Configure CPU Select for SD SYSCTL_CPUSEL4_SD = 0x4U, //! Configure CPU Select for SCI SYSCTL_CPUSEL5_SCI = 0x5U, //! Configure CPU Select for SPI SYSCTL_CPUSEL6_SPI = 0x6U, //! Configure CPU Select for I2C SYSCTL_CPUSEL7_I2C = 0x7U, //! Configure CPU Select for CAN SYSCTL_CPUSEL8_CAN = 0x8U, //! Configure CPU Select for MCBSP SYSCTL_CPUSEL9_MCBSP = 0x9U, //! Configure CPU Select for ADC SYSCTL_CPUSEL11_ADC = 0xBU, //! Configure CPU Select for CMPSS SYSCTL_CPUSEL12_CMPSS = 0xCU, //! Configure CPU Select for DAC SYSCTL_CPUSEL14_DAC = 0xEU } SysCtl_CPUSelPeripheral; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_selectCPUForPeripheral() as \e cpuInst parameter. // //***************************************************************************** typedef enum { //! Connect the peripheral (indicated by SysCtl_CPUSelPeripheral) to CPU1 SYSCTL_CPUSEL_CPU1 = 0x0U, //! Connect the peripheral (indicated by SysCtl_CPUSelPeripheral) to CPU2 SYSCTL_CPUSEL_CPU2 = 0x1U } SysCtl_CPUSel; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setWatchdogPrescaler() as the \e prescaler parameter. // //***************************************************************************** typedef enum { SYSCTL_WD_PRESCALE_1 = 1, //!< WDCLK = PREDIVCLK / 1 SYSCTL_WD_PRESCALE_2 = 2, //!< WDCLK = PREDIVCLK / 2 SYSCTL_WD_PRESCALE_4 = 3, //!< WDCLK = PREDIVCLK / 4 SYSCTL_WD_PRESCALE_8 = 4, //!< WDCLK = PREDIVCLK / 8 SYSCTL_WD_PRESCALE_16 = 5, //!< WDCLK = PREDIVCLK / 16 SYSCTL_WD_PRESCALE_32 = 6, //!< WDCLK = PREDIVCLK / 32 SYSCTL_WD_PRESCALE_64 = 7 //!< WDCLK = PREDIVCLK / 64 } SysCtl_WDPrescaler; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setWatchdogMode() as the \e prescaler parameter. // //***************************************************************************** typedef enum { //! Watchdog can generate a reset signal SYSCTL_WD_MODE_RESET, //! Watchdog can generate an interrupt signal; reset signal is disabled SYSCTL_WD_MODE_INTERRUPT } SysCtl_WDMode; //***************************************************************************** // //! The following are values that can be passed to SysCtl_setLowSpeedClock() as //! the \e prescaler parameter. // //***************************************************************************** typedef enum { SYSCTL_LSPCLK_PRESCALE_1 = 0, //!< LSPCLK = SYSCLK / 1 SYSCTL_LSPCLK_PRESCALE_2 = 1, //!< LSPCLK = SYSCLK / 2 SYSCTL_LSPCLK_PRESCALE_4 = 2, //!< LSPCLK = SYSCLK / 4 (default) SYSCTL_LSPCLK_PRESCALE_6 = 3, //!< LSPCLK = SYSCLK / 6 SYSCTL_LSPCLK_PRESCALE_8 = 4, //!< LSPCLK = SYSCLK / 8 SYSCTL_LSPCLK_PRESCALE_10 = 5, //!< LSPCLK = SYSCLK / 10 SYSCTL_LSPCLK_PRESCALE_12 = 6, //!< LSPCLK = SYSCLK / 12 SYSCTL_LSPCLK_PRESCALE_14 = 7 //!< LSPCLK = SYSCLK / 14 } SysCtl_LSPCLKPrescaler; //***************************************************************************** // //! The following are values that can be passed to SysCtl_setEPWMClockDivider() //! as the \e divider parameter. // //***************************************************************************** typedef enum { SYSCTL_EPWMCLK_DIV_1, //!< EPWMCLK = PLLSYSCLK / 1 SYSCTL_EPWMCLK_DIV_2 //!< EPWMCLK = PLLSYSCLK / 2 } SysCtl_EPWMCLKDivider; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setEMIF1ClockDivider() as the \e divider parameter. // //***************************************************************************** typedef enum { SYSCTL_EMIF1CLK_DIV_1, //!< EMIF1CLK = PLLSYSCLK / 1 SYSCTL_EMIF1CLK_DIV_2 //!< EMIF1CLK = PLLSYSCLK / 2 } SysCtl_EMIF1CLKDivider; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_setEMIF2ClockDivider() as the \e divider parameter. // //***************************************************************************** typedef enum { SYSCTL_EMIF2CLK_DIV_1, //!< EMIF2CLK = PLLSYSCLK / 1 SYSCTL_EMIF2CLK_DIV_2 //!< EMIF2CLK = PLLSYSCLK / 2 } SysCtl_EMIF2CLKDivider; //***************************************************************************** // //! The following are values that can be passed to //! SysCtl_selectClockOutSource() as the \e source parameter. // //***************************************************************************** typedef enum { SYSCTL_CLOCKOUT_PLLSYS = 0U, //!< PLL System Clock SYSCTL_CLOCKOUT_PLLRAW = 1U, //!< PLL Raw Clock SYSCTL_CLOCKOUT_SYSCLK = 2U, //!< CPU System Clock SYSCTL_CLOCKOUT_INTOSC1 = 5U, //!< Internal Oscillator 1 SYSCTL_CLOCKOUT_INTOSC2 = 6U, //!< Internal Oscillator 2 SYSCTL_CLOCKOUT_XTALOSC = 7U //!< External Oscillator } SysCtl_ClockOut; //***************************************************************************** // //! The following values define the \e syncInput parameter for //! SysCtl_setSyncInputConfig(). // //***************************************************************************** typedef enum { SYSCTL_SYNC_IN_EPWM4 = 0, //!< Sync input to ePWM 4 SYSCTL_SYNC_IN_EPWM7 = 3, //!< Sync input to ePWM 7 SYSCTL_SYNC_IN_EPWM10 = 6, //!< Sync input to ePWM 10 SYSCTL_SYNC_IN_ECAP1 = 9, //!< Sync input to eCAP 1 SYSCTL_SYNC_IN_ECAP4 = 12 //!< Sync input to eCAP 4 } SysCtl_SyncInput; //***************************************************************************** // //! The following values define the \e syncSrc parameter for //! SysCtl_setSyncInputConfig(). Note that some of these are only valid for //! certain values of \e syncInput. See device technical reference manual for //! info on time-base counter synchronization for details. // //***************************************************************************** typedef enum { //! EPWM1SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT = 0, //! EPWM4SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM4SYNCOUT = 1, //! EPWM7SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM7SYNCOUT = 2, //! EPWM10SYNCOUT SYSCTL_SYNC_IN_SRC_EPWM10SYNCOUT = 3, //! ECAP1SYNCOUT SYSCTL_SYNC_IN_SRC_ECAP1SYNCOUT = 4, //! EXTSYNCIN1--Valid for all values of syncInput SYSCTL_SYNC_IN_SRC_EXTSYNCIN1 = 5, //! EXTSYNCIN2--Valid for all values of syncInput SYSCTL_SYNC_IN_SRC_EXTSYNCIN2 = 6 } SysCtl_SyncInputSource; //***************************************************************************** // //! The following values define the \e syncSrc parameter for //! SysCtl_setSyncOutputConfig(). // //***************************************************************************** typedef enum { SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT, //!< EPWM1SYNCOUT --> EXTSYNCOUT SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT, //!< EPWM4SYNCOUT --> EXTSYNCOUT SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT, //!< EPWM7SYNCOUT --> EXTSYNCOUT SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT //!< EPWM10SYNCOUT --> EXTSYNCOUT } SysCtl_SyncOutputSource; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! Resets a peripheral //! //! \param peripheral is the peripheral to reset. //! //! This function uses the SOFTPRESx registers to reset a specified peripheral. //! Module registers will be returned to their reset states. //! //! \note This includes registers containing trim values. //! //! \return None. // //***************************************************************************** static inline void SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral) { uint16_t regIndex; uint16_t bitIndex; // // Decode the peripheral variable. // regIndex = (uint16_t)2U * ((uint16_t)peripheral & (uint16_t)0x001FU); bitIndex = ((uint16_t)peripheral & 0x1F00U) >> 0x0008U; __eallow(); // // Sets the appropriate reset bit and then clears it. // (*((volatile uint32_t *)(0x0005D000U + 0x82U + regIndex))) |= ((uint32_t)1U << bitIndex); (*((volatile uint32_t *)(0x0005D000U + 0x82U + regIndex))) &= ~((uint32_t)1U << bitIndex); __edis(); } //***************************************************************************** // //! Enables a peripheral. //! //! \param peripheral is the peripheral to enable. //! //! Peripherals are enabled with this function. At power-up, all peripherals //! are disabled; they must be enabled in order to operate or respond to //! register reads/writes. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) { uint16_t regIndex; uint16_t bitIndex; // // Decode the peripheral variable. // regIndex = (uint16_t)2U * ((uint16_t)peripheral & (uint16_t)0x001FU); bitIndex = ((uint16_t)peripheral & 0x1F00U) >> 0x0008U; __eallow(); // // Turn on the module clock. // (*((volatile uint32_t *)(0x0005D300U + 0x22U + regIndex))) |= ((uint32_t)1U << bitIndex); __edis(); } //***************************************************************************** // //! Disables a peripheral. //! //! \param peripheral is the peripheral to disable. //! //! Peripherals are disabled with this function. Once disabled, they will not //! operate or respond to register reads/writes. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) { uint16_t regIndex; uint16_t bitIndex; // // Decode the peripheral variable. // regIndex = (uint16_t)2U * ((uint16_t)peripheral & (uint16_t)0x001FU); bitIndex = ((uint16_t)peripheral & 0x1F00U) >> 0x0008U; __eallow(); // // Turn off the module clock. // (*((volatile uint32_t *)(0x0005D300U + 0x22U + regIndex))) &= ~((uint32_t)1U << bitIndex); __edis(); } //***************************************************************************** // //! Resets the device. //! //! This function performs a watchdog reset of the device. //! //! \return This function does not return. // //***************************************************************************** static inline void SysCtl_resetDevice(void) { // // Write an incorrect check value to the watchdog control register // This will cause a device reset // __eallow(); // Enable the watchdog (*((volatile uint16_t *)(0x00007000U + 0x29U))) = 0x0028U; // Write a bad check value (*((volatile uint16_t *)(0x00007000U + 0x29U))) = 0U; __edis(); // // The device should have reset, so this should never be reached. Just in // case, loop forever. // while(1) { } } //***************************************************************************** // //! Gets the reason for a reset. //! //! This function will return the reason(s) for a reset. Since the reset //! reasons are sticky until either cleared by software or an external reset, //! multiple reset reasons may be returned if multiple resets have occurred. //! The reset reason will be a logical OR of //! - \b SYSCTL_CAUSE_POR - Power-on reset //! - \b SYSCTL_CAUSE_XRS - External reset pin //! - \b SYSCTL_CAUSE_WDRS - Watchdog reset //! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset //! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM //! //! \note Some reset causes are cleared by the boot ROM. //! //! \return Returns the reason(s) for a reset. // //***************************************************************************** static inline uint32_t SysCtl_getResetCause(void) { // // Return the reset reasons. // return((*((volatile uint32_t *)(0x0005D300U + 0x80U))) & ((uint32_t)0x1U | (uint32_t)0x2U | (uint32_t)0x4U | (uint32_t)0x8U | (uint32_t)0x100U)); } //***************************************************************************** // //! Clears reset reasons. //! //! \param rstCauses are the reset causes to be cleared; must be a logical //! OR of \b SYSCTL_CAUSE_POR, \b SYSCTL_CAUSE_XRS, \b SYSCTL_CAUSE_WDRS, //! \b SYSCTL_CAUSE_NMIWDRS, and/or \b SYSCTL_CAUSE_SCCRESET. //! //! This function clears the specified sticky reset reasons. Once cleared, //! another reset for the same reason can be detected, and a reset for a //! different reason can be distinguished (instead of having two reset causes //! set). If the reset reason is used by an application, all reset causes //! should be cleared after they are retrieved with SysCtl_getResetCause(). //! //! \note Some reset causes are cleared by the boot ROM. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearResetCause(uint32_t rstCauses) { // // Clear the given reset reasons. // (*((volatile uint32_t *)(0x0005D300U + 0x80U))) = rstCauses; } //***************************************************************************** // //! Sets the low speed peripheral clock rate prescaler. //! //! \param prescaler is the LSPCLK rate relative to SYSCLK //! //! This function configures the clock rate of the low speed peripherals. The //! \e prescaler parameter is the value by which the SYSCLK rate is divided to //! get the LSPCLK rate. For example, a \e prescaler of //! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter //! of the SYSCLK rate. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler) { // // Write the divider selection to the appropriate register. // __eallow(); (*((volatile uint32_t *)(0x0005D200U + 0x2CU))) = ((*((volatile uint32_t *)(0x0005D200U + 0x2CU))) & ~0x7U) | (uint32_t)prescaler; __edis(); } //***************************************************************************** // //! Sets the ePWM clock divider. //! //! \param divider is the value by which PLLSYSCLK is divided //! //! This function configures the clock rate of the EPWMCLK. The //! \e divider parameter is the value by which the SYSCLK rate is divided to //! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an //! EPWMCLK rate that is half the PLLSYSCLK rate. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider) { // // Write the divider selection to the appropriate register. // __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x26U))) = ((*((volatile uint16_t *)(0x0005D200U + 0x26U))) & ~0x3U) | divider; __edis(); } //***************************************************************************** // //! Sets the EMIF1 clock divider. //! //! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual //! core device) is divided //! //! This function configures the clock rate of the EMIF1CLK. The //! \e divider parameter is the value by which the SYSCLK rate is divided to //! get the EMIF1CLK rate. For example, \b SYSCTL_EMIF1CLK_DIV_2 will select an //! EMIF1CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual //! core device) rate. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setEMIF1ClockDivider(SysCtl_EMIF1CLKDivider divider) { // // Write the divider selection to the appropriate register. // __eallow(); if(divider == SYSCTL_EMIF1CLK_DIV_2) { (*((volatile uint16_t *)(0x0005D200U + 0x26U))) |= 0x10U; } else { (*((volatile uint16_t *)(0x0005D200U + 0x26U))) &= ~0x10U; } __edis(); } //***************************************************************************** // //! Sets the EMIF2 clock divider. //! //! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual //! core device) is divided //! //! This function configures the clock rate of the EMIF2CLK. The //! \e divider parameter is the value by which the SYSCLK rate is divided to //! get the EMIF2CLK rate. For example, \b SYSCTL_EMIF2CLK_DIV_2 will select an //! EMIF2CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual //! core device) rate. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setEMIF2ClockDivider(SysCtl_EMIF2CLKDivider divider) { // // Write the divider selection to the appropriate register. // __eallow(); if(divider == SYSCTL_EMIF2CLK_DIV_2) { (*((volatile uint16_t *)(0x0005D200U + 0x26U))) |= 0x40U; } else { (*((volatile uint16_t *)(0x0005D200U + 0x26U))) &= ~0x40U; } __edis(); } //***************************************************************************** // //! Selects a clock source to mux to an external GPIO pin (XCLKOUT). //! //! \param source is the internal clock source to be configured. //! //! This function configures the specified clock source to be muxed to an //! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a //! value of one of the following values: //! - \b SYSCTL_CLOCKOUT_PLLSYS //! - \b SYSCTL_CLOCKOUT_PLLRAW //! - \b SYSCTL_CLOCKOUT_SYSCLK //! - \b SYSCTL_CLOCKOUT_INTOSC1 //! - \b SYSCTL_CLOCKOUT_INTOSC2 //! - \b SYSCTL_CLOCKOUT_XTALOSC //! //! \return None. // //***************************************************************************** static inline void SysCtl_selectClockOutSource(SysCtl_ClockOut source) { __eallow(); // // Clear clock out source // (*((volatile uint16_t *)(0x0005D200U + 0xCU))) &= ~0x7U; // // Set clock out source // (*((volatile uint16_t *)(0x0005D200U + 0xCU))) |= (uint16_t)source; __edis(); } //***************************************************************************** // //! Gets the external oscillator counter value. //! //! This function returns the X1 clock counter value. When the return value //! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external //! oscillator (XTAL), an application should call this function to make sure the //! counter is saturated. //! //! \return Returns the value of the 10-bit X1 clock counter. // //***************************************************************************** static inline uint16_t SysCtl_getExternalOscCounterValue(void) { return((*((volatile uint16_t *)(0x0005D200U + 0x30U))) & 0x3FFU); } //***************************************************************************** // //! Turns on the specified oscillator sources. //! //! \param oscSource is the oscillator source to be configured. //! //! This function turns on the oscillator specified by the \e oscSource //! parameter which may take a value of \b SYSCTL_OSCSRC_OSC2 or //! \b SYSCTL_OSCSRC_XTAL. //! //! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. //! //! \return None. // //***************************************************************************** static inline void SysCtl_turnOnOsc(uint32_t oscSource) { do { if(!((oscSource == 0x00000000U) | (oscSource == 0x00010000U))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1082); } } while(0); __eallow(); switch(oscSource) { case 0x00000000U: // Turn on INTOSC2 (*((volatile uint16_t *)(0x0005D200U + 0x8U))) &= ~0x8U; break; case 0x00010000U: // Turn on XTALOSC (*((volatile uint16_t *)(0x0005D200U + 0x8U))) &= ~0x10U; break; default: // Do nothing. Not a valid oscSource value. break; } __edis(); } //***************************************************************************** // //! Turns off the specified oscillator sources. //! //! \param oscSource is the oscillator source to be configured. //! //! This function turns off the oscillator specified by the \e oscSource //! parameter which may take a value of \b SYSCTL_OSCSRC_OSC2 or //! \b SYSCTL_OSCSRC_XTAL. //! //! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. //! //! \return None. // //***************************************************************************** static inline void SysCtl_turnOffOsc(uint32_t oscSource) { do { if(!((oscSource == 0x00000000U) | (oscSource == 0x00010000U))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1127); } } while(0); __eallow(); switch(oscSource) { case 0x00000000U: // Turn off INTOSC2 (*((volatile uint16_t *)(0x0005D200U + 0x8U))) |= 0x8U; break; case 0x00010000U: // Turn off XTALOSC (*((volatile uint16_t *)(0x0005D200U + 0x8U))) |= 0x10U; break; default: // Do nothing. Not a valid oscSource value. break; } __edis(); } //***************************************************************************** // //! Enters IDLE mode. //! //! This function puts the device into IDLE mode. The CPU clock is gated while //! all peripheral clocks are left running. Any enabled interrupt will wake the //! CPU up from IDLE mode. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enterIdleMode(void) { __eallow(); // // Configure the device to go into IDLE mode when IDLE is executed. // (*((volatile uint32_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint32_t *)(0x0005D300U + 0x76U))) & ~0x3U) | 0x0000U; __edis(); __asm(" IDLE"); } //***************************************************************************** // //! Enters STANDBY mode. //! //! This function puts the device into STANDBY mode. This will gate both the //! CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is //! left active, and an NMI or an optional watchdog interrupt will wake the //! CPU subsystem from STANDBY mode. //! //! GPIOs may be configured to wake the CPU subsystem. See //! SysCtl_enableLPMWakeupPin(). //! //! The CPU will receive an interrupt (WAKEINT) on wakeup. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enterStandbyMode(void) { __eallow(); // // Configure the device to go into STANDBY mode when IDLE is executed. // (*((volatile uint32_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint32_t *)(0x0005D300U + 0x76U))) & ~0x3U) | 0x0001U; __edis(); __asm(" IDLE"); } //***************************************************************************** // //! Enters HALT mode. //! //! This function puts the device into HALT mode. This will gate almost all //! systems and clocks and allows for the power-down of oscillators and analog //! blocks. The watchdog may be left clocked to produce a reset. See //! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be //! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin(). //! //! Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. //! //! The CPU will receive an interrupt (WAKEINT) on wakeup. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enterHaltMode(void) { __eallow(); // // Configure the device to go into HALT mode when IDLE is executed. // (*((volatile uint32_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint32_t *)(0x0005D300U + 0x76U))) & ~0x3U) | 0x0002U; (*((volatile uint16_t *)(0x0005D200U + 0xEU))) &= ~(0x2U | 0x1U); __edis(); __asm(" IDLE"); } //***************************************************************************** // //! Enters Hibernate mode. //! //! This function puts the device into Hibernate mode. Hibernate (HIB) is a //! global low-power mode that gates the supply voltages to most of the system. //! This mode affects both CPU subsystems. HIB is essentially a controlled //! power-down with remote wakeup capability, and can be used to save power //! during long periods of inactivity. //! //! To wake the device from HIB mode: //! 1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the //! power-up of the device clock sources. //! 2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the //! rest of the device. //! //! To enter Hibernate mode in dual CPU put CPU2 in STANDBY mode first. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enterHibernateMode(void) { __eallow(); // // Configure the device to go into Hibernate mode when IDLE is executed // (*((volatile uint32_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint32_t *)(0x0005D300U + 0x76U))) & ~0x3U) | 0x0003U; (*((volatile uint16_t *)(0x0005D200U + 0xEU))) &= ~(0x2U | 0x1U); __edis(); __asm(" IDLE"); } //***************************************************************************** // //! Enables a pin to wake up the device from STANDBY or HALT. //! //! \param pin is the identifying number of the pin. //! //! This function connects a pin to the LPM circuit, allowing an event on the //! pin to wake up the device when when it is in STANDBY or HALT mode. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of //! being connected to the LPM circuit. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableLPMWakeupPin(uint32_t pin) { uint32_t pinMask; // // Check the arguments. // do { if(!(pin <= 63U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1345); } } while(0); pinMask = (uint32_t)1U << (uint32_t)(pin % 32U); __eallow(); if(pin < 32U) { (*((volatile uint32_t *)(0x0005D300U + 0x78U))) |= pinMask; } else { (*((volatile uint32_t *)(0x0005D300U + 0x7AU))) |= pinMask; } __edis(); } //***************************************************************************** // //! Disables a pin to wake up the device from STANDBY or HALT. //! //! \param pin is the identifying number of the pin. //! //! This function disconnects a pin to the LPM circuit, disallowing an event on //! the pin to wake up the device when when it is in STANDBY or HALT mode. //! //! The pin is specified by its numerical value. For example, GPIO34 is //! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableLPMWakeupPin(uint32_t pin) { uint32_t pinMask; // // Check the arguments. // do { if(!(pin <= 63U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1386); } } while(0); pinMask = (uint32_t)1U << (uint32_t)(pin % 32U); __eallow(); if(pin < 32U) { (*((volatile uint32_t *)(0x0005D300U + 0x78U))) &= ~pinMask; } else { (*((volatile uint32_t *)(0x0005D300U + 0x7AU))) &= ~pinMask; } __edis(); } //***************************************************************************** // //! Sets the number of cycles to qualify an input on waking from STANDBY mode. //! //! \param cycles is the number of OSCCLK cycles. //! //! This function sets the number of OSCCLK clock cycles used to qualify the //! selected inputs when waking from STANDBY mode. The \e cycles parameter //! should be passed a cycle count between 2 and 65 cycles inclusive. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setStandbyQualificationPeriod(uint16_t cycles) { // // Check the arguments. // do { if(!((cycles >= 2U) && (cycles <= 65U))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1423); } } while(0); __eallow(); (*((volatile uint16_t *)(0x0005D300U + 0x76U))) = ((*((volatile uint16_t *)(0x0005D300U + 0x76U))) & ~(uint16_t)0xFCU) | ((cycles - (uint16_t)2U) << 2U); __edis(); } //***************************************************************************** // //! Enable the device to wake from STANDBY mode upon a watchdog interrupt. //! //! \note In order to use this option, you must configure the watchdog to //! generate an interrupt using SysCtl_setWatchdogMode(). //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableWatchdogStandbyWakeup(void) { __eallow(); // // Set the bit enables the watchdog to wake up the device from STANDBY. // (*((volatile uint16_t *)(0x0005D300U + 0x76U))) |= 0x8000U; __edis(); } //***************************************************************************** // //! Disable the device from waking from STANDBY mode upon a watchdog interrupt. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableWatchdogStandbyWakeup(void) { __eallow(); // // Clear the bit enables the watchdog to wake up the device from STANDBY. // (*((volatile uint16_t *)(0x0005D300U + 0x76U))) &= ~0x8000U; __edis(); } //***************************************************************************** // //! Enable the watchdog to run while in HALT mode. //! //! This function configures the watchdog to continue to run while in HALT //! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the //! system enters HALT mode. By default the watchdog is gated when the system //! enters HALT. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableWatchdogInHalt(void) { __eallow(); // // Set the watchdog HALT mode ignore bit. // (*((volatile uint16_t *)(0x0005D200U + 0x8U))) |= 0x20U; __edis(); } //***************************************************************************** // //! Disable the watchdog from running while in HALT mode. //! //! This function gates the watchdog when the system enters HALT mode. INTOSC1 //! and INTOSC2 will be powered down. This is the default behavior of the //! device. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableWatchdogInHalt(void) { __eallow(); // // Clear the watchdog HALT mode ignore bit. // (*((volatile uint16_t *)(0x0005D200U + 0x8U))) &= ~0x20U; __edis(); } //***************************************************************************** // //! Configures whether the watchdog generates a reset or an interrupt signal. //! //! \param mode is a flag to select the watchdog mode. //! //! This function configures the action taken when the watchdog counter reaches //! its maximum value. When the \e mode parameter is //! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog //! interrupt signal and disables the generation of a reset signal. This will //! allow the watchdog module to wake up the device from IDLE or STANDBY if //! desired (see SysCtl_enableWatchdogStandbyWakeup()). //! //! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will //! be put into reset mode and generation of a watchdog interrupt signal will //! be disabled. This is how the watchdog is configured by default. //! //! \note Check the status of the watchdog interrupt using //! SysCtl_isWatchdogInterruptActive() before calling this function. If the //! interrupt is still active, switching from interrupt mode to reset mode will //! immediately reset the device. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogMode(SysCtl_WDMode mode) { __eallow(); // // Either set or clear the WDENINT bit to that will determine whether the // watchdog will generate a reset signal or an interrupt signal. Take care // not to write a 1 to WDOVERRIDE. // if(mode == SYSCTL_WD_MODE_INTERRUPT) { (*((volatile uint16_t *)(0x00007000U + 0x22U))) = ((*((volatile uint16_t *)(0x00007000U + 0x22U))) & ~0x1U) | 0x2U; } else { (*((volatile uint16_t *)(0x00007000U + 0x22U))) &= ~(0x2U | 0x1U); } __edis(); } //***************************************************************************** // //! Gets the status of the watchdog interrupt signal. //! //! This function returns the status of the watchdog interrupt signal. If the //! interrupt is active, this function will return \b true. If \b false, the //! interrupt is NOT active. //! //! \note Make sure to call this function to ensure that the interrupt is not //! active before making any changes to the configuration of the watchdog to //! prevent any unexpected behavior. For instance, switching from interrupt //! mode to reset mode while the interrupt is active will immediately reset the //! device. //! //! \return \b true if the interrupt is active and \b false if it is not. // //***************************************************************************** static inline _Bool SysCtl_isWatchdogInterruptActive(void) { // // If the status bit is cleared, the WDINTn signal is active. // return(((*((volatile uint16_t *)(0x00007000U + 0x22U))) & 0x4U) == 0U); } //***************************************************************************** // //! Disables the watchdog. //! //! This function disables the watchdog timer. Note that the watchdog timer is //! enabled on reset. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableWatchdog(void) { __eallow(); // // Set the disable bit. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) |= 0x0028U | 0x40U; __edis(); } //***************************************************************************** // //! Enables the watchdog. //! //! This function enables the watchdog timer. Note that the watchdog timer is //! enabled on reset. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableWatchdog(void) { __eallow(); // // Clear the disable bit. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) = ((*((volatile uint16_t *)(0x00007000U + 0x29U))) & ~0x40U) | 0x0028U; __edis(); } //***************************************************************************** // //! Services the watchdog. //! //! This function resets the watchdog. //! //! \return None. // //***************************************************************************** static inline void SysCtl_serviceWatchdog(void) { __eallow(); // // Enable the counter to be reset and then reset it. // (*((volatile uint16_t *)(0x00007000U + 0x25U))) = 0x0055U; (*((volatile uint16_t *)(0x00007000U + 0x25U))) = 0x00AAU; __edis(); } //***************************************************************************** // //! Sets up watchdog clock (WDCLK) prescaler. //! //! \param prescaler is the value that configures the watchdog clock relative //! to the value from the pre-divider. //! //! This function sets up the watchdog clock (WDCLK) prescaler. The //! \e prescaler parameter divides INTOSC1 down to WDCLK. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler) { uint16_t regVal; regVal = (uint16_t)prescaler | (uint16_t)0x0028U; __eallow(); // // Write the prescaler to the appropriate register. // (*((volatile uint16_t *)(0x00007000U + 0x29U))) = ((*((volatile uint16_t *)(0x00007000U + 0x29U))) & ~(0x7U)) | regVal; __edis(); } //***************************************************************************** // //! Gets the watchdog counter value. //! //! \return Returns the current value of the 8-bit watchdog counter. If this //! count value overflows, a watchdog output pulse is generated. // //***************************************************************************** static inline uint16_t SysCtl_getWatchdogCounterValue(void) { // // Read and return the value of the watchdog counter. // return((*((volatile uint16_t *)(0x00007000U + 0x23U)))); } //***************************************************************************** // //! Gets the watchdog reset status. //! //! This function returns the watchdog reset status. If this function returns //! \b true, that indicates that a watchdog reset generated the last reset //! condition. Otherwise, it was an external device or power-up reset //! condition. //! //! \return Returns \b true if the watchdog generated the last reset condition. // //***************************************************************************** static inline _Bool SysCtl_getWatchdogResetStatus(void) { // // Read and return the status of the watchdog reset status flag. // return(((*((volatile uint16_t *)(0x0005D300U + 0x80U))) & 0x4U) != 0U); } //***************************************************************************** // //! Clears the watchdog reset status. //! //! This function clears the watchdog reset status. To check if it was set //! first, see SysCtl_getWatchdogResetStatus(). //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearWatchdogResetStatus(void) { __eallow(); // // Read and return the status of the watchdog reset status flag. // (*((volatile uint16_t *)(0x0005D300U + 0x80U))) = 0x4U; __edis(); } //***************************************************************************** // //! Set the minimum threshold value for windowed watchdog //! //! \param value is the value to set the window threshold //! //! This function sets the minimum threshold value used to define the lower //! limit of the windowed watchdog functionality. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setWatchdogWindowValue(uint16_t value) { __eallow(); // // Clear the windowed value // (*((volatile uint16_t *)(0x00007000U + 0x2AU))) &= ~0xFFU; // // Set the windowed value // (*((volatile uint16_t *)(0x00007000U + 0x2AU))) |= (value & 0xFFU); __edis(); } //***************************************************************************** // //! Read NMI interrupts. //! //! Read the current state of NMI interrupt. //! //! \return \b true if NMI interrupt is triggered, \b false if not. // //***************************************************************************** static inline _Bool SysCtl_getNMIStatus(void) { // // Read and return the current value of the NMI flag register, masking out // all but the NMI bit. // return(((*((volatile uint16_t *)(0x00007060U + 0x1U))) & 0x1U) != 0U); } //***************************************************************************** // //! Read NMI Flags. //! //! Read the current state of individual NMI interrupts //! //! \return Value of NMIFLG register. These defines are provided to decode //! the value: //! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt //! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure //! - \b SYSCTL_NMI_RAMUNCERR - Uncorrectable RAM error //! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error //! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error //! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset //! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset // //***************************************************************************** static inline uint32_t SysCtl_getNMIFlagStatus(void) { // // Read and return the current value of the NMI flag register. // return((*((volatile uint16_t *)(0x00007060U + 0x1U)))); } //***************************************************************************** // //! Check if the individual NMI interrupts are set. //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt //! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure //! - \b SYSCTL_NMI_RAMUNCERR - Uncorrectable RAM error //! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error //! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error //! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset //! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset //! //! Check if interrupt flags corresponding to the passed in bit mask are //! asserted. //! //! \return \b true if any of the NMI asked for in the parameter bit mask //! is set. \b false if none of the NMI requested in the parameter bit mask are //! set. // //***************************************************************************** static inline _Bool SysCtl_isNMIFlagSet(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // do { if(!((nmiFlags & ~(0x0001U | 0x0002U | 0x0004U | 0x0008U | 0x0040U | 0x0200U | 0x0400U)) == 0)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1873); } } while(0); // // Read the flag register and return true if any of them are set. // return(((*((volatile uint16_t *)(0x00007060U + 0x1U))) & nmiFlags) != 0U); } //***************************************************************************** // //! Function to clear individual NMI interrupts. //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_CLOCKFAIL //! - \b SYSCTL_NMI_RAMUNCERR //! - \b SYSCTL_NMI_FLUNCERR //! - \b SYSCTL_NMI_PIEVECTERR //! - \b SYSCTL_NMI_CPU2WDRSN //! - \b SYSCTL_NMI_CPU2NMIWDRSN //! //! Clear NMI interrupt flags that correspond with the passed in bit mask. //! //! \b Note: The NMI Interrupt flag is always cleared by default and //! therefore doesn't have to be included in the bit mask. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearNMIStatus(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // do { if(!((nmiFlags & ~(0x0001U | 0x0002U | 0x0004U | 0x0008U | 0x0040U | 0x0200U | 0x0400U)) == 0)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1913); } } while(0); __eallow(); // // Clear the individual flags as well as NMI Interrupt flag // (*((volatile uint16_t *)(0x00007060U + 0x2U))) = nmiFlags; (*((volatile uint16_t *)(0x00007060U + 0x2U))) = 0x1U; __edis(); } //***************************************************************************** // //! Clear all the NMI Flags that are currently set. //! //! \return None. // //***************************************************************************** static inline void SysCtl_clearAllNMIFlags(void) { uint32_t nmiFlags; // // Read the flag status register and then write to the clear register, // clearing all the flags that were returned plus the NMI flag. // __eallow(); nmiFlags = SysCtl_getNMIFlagStatus(); (*((volatile uint16_t *)(0x00007060U + 0x2U))) = nmiFlags; (*((volatile uint16_t *)(0x00007060U + 0x2U))) = 0x1U; __edis(); } //***************************************************************************** // //! Function to force individual NMI interrupt fail flags //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_CLOCKFAIL //! - \b SYSCTL_NMI_RAMUNCERR //! - \b SYSCTL_NMI_FLUNCERR //! - \b SYSCTL_NMI_PIEVECTERR //! - \b SYSCTL_NMI_CPU2WDRSN //! - \b SYSCTL_NMI_CPU2NMIWDRSN //! //! \return None. // //***************************************************************************** static inline void SysCtl_forceNMIFlags(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // do { if(!((nmiFlags & ~(0x0001U | 0x0002U | 0x0004U | 0x0008U | 0x0040U | 0x0200U | 0x0400U)) == 0)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 1978); } } while(0); __eallow(); // // Set the Flags for the individual interrupts in the NMI flag // force register // (*((volatile uint16_t *)(0x00007060U + 0x3U))) |= nmiFlags; __edis(); } //***************************************************************************** // //! Gets the NMI watchdog counter value. //! //! \b Note: The counter is clocked at the SYSCLKOUT rate. //! //! \return Returns the NMI watchdog counter register's current value. // //***************************************************************************** static inline uint16_t SysCtl_getNMIWatchdogCounter(void) { // // Read and return the NMI watchdog counter register's value. // return((*((volatile uint16_t *)(0x00007060U + 0x4U)))); } //***************************************************************************** // //! Sets the NMI watchdog period value. //! //! \param wdPeriod is the 16-bit value at which a reset is generated. //! //! This function writes to the NMI watchdog period register that holds the //! value to which the NMI watchdog counter is compared. When the two registers //! match, a reset is generated. By default, the period is 0xFFFF. //! //! \note If a value smaller than the current counter value is passed into the //! \e wdPeriod parameter, a NMIRSn will be forced. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod) { __eallow(); // // Write to the period register. // (*((volatile uint16_t *)(0x00007060U + 0x5U))) = wdPeriod; __edis(); } //***************************************************************************** // //! Gets the NMI watchdog period value. //! //! \return Returns the NMI watchdog period register's current value. // //***************************************************************************** static inline uint16_t SysCtl_getNMIWatchdogPeriod(void) { // // Read and return the NMI watchdog period register's value. // return((*((volatile uint16_t *)(0x00007060U + 0x5U)))); } //***************************************************************************** // //! Read NMI Shadow Flags. //! //! Read the current state of individual NMI interrupts //! //! \return Value of NMISHDFLG register. These defines are provided to decode //! the value: //! - \b SYSCTL_NMI_NMIINT - Non-maskable interrupt //! - \b SYSCTL_NMI_CLOCKFAIL - Clock Failure //! - \b SYSCTL_NMI_RAMUNCERR - Uncorrectable RAM error //! - \b SYSCTL_NMI_FLUNCERR - Uncorrectable Flash error //! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error //! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset //! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset // //***************************************************************************** static inline uint32_t SysCtl_getNMIShadowFlagStatus(void) { // // Read and return the current value of the NMI shadow flag register. // return((*((volatile uint16_t *)(0x00007060U + 0x6U)))); } //***************************************************************************** // //! Check if the individual NMI shadow flags are set. //! //! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. //! The bit format of this parameter is same as of the NMIFLG register. These //! defines are provided: //! - \b SYSCTL_NMI_NMIINT //! - \b SYSCTL_NMI_CLOCKFAIL //! - \b SYSCTL_NMI_RAMUNCERR //! - \b SYSCTL_NMI_FLUNCERR //! - \b SYSCTL_NMI_PIEVECTERR //! - \b SYSCTL_NMI_CPU2WDRSN //! - \b SYSCTL_NMI_CPU2NMIWDRSN //! //! Check if interrupt flags corresponding to the passed in bit mask are //! asserted. //! //! \return \b true if any of the NMI asked for in the parameter bit mask //! is set. \b false if none of the NMI requested in the parameter bit mask are //! set. // //***************************************************************************** static inline _Bool SysCtl_isNMIShadowFlagSet(uint32_t nmiFlags) { // // Check the arguments. // Make sure if reserved bits are not set in nmiFlags. // do { if(!((nmiFlags & ~(0x0001U | 0x0002U | 0x0004U | 0x0008U | 0x0040U | 0x0200U | 0x0400U)) == 0)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/sysctl.h", 2113); } } while(0); // // Read the flag register and return true if any of them are set. // return(((*((volatile uint16_t *)(0x00007060U + 0x6U))) & nmiFlags) != 0U); } //***************************************************************************** // //! Enable the missing clock detection (MCD) Logic //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableMCD(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) &= ~(0x4U); __edis(); } //***************************************************************************** // //! Disable the missing clock detection (MCD) Logic //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableMCD(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) |= 0x4U; __edis(); } //***************************************************************************** // //! Get the missing clock detection Failure Status //! //! \note A failure means the oscillator clock is missing //! //! \return Returns \b true if a failure is detected or \b false if a //! failure isn't detected // //***************************************************************************** static inline _Bool SysCtl_isMCDClockFailureDetected(void) { // // Check the status bit to determine failure // return(((*((volatile uint16_t *)(0x0005D200U + 0x2EU))) & 0x1U) != 0U); } //***************************************************************************** // //! Reset the missing clock detection logic after clock failure //! //! \return None. // //***************************************************************************** static inline void SysCtl_resetMCD(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) |= 0x2U; __edis(); } //***************************************************************************** // //! Re-connect missing clock detection clock source to stop simulating clock //! failure //! //! \return None. // //***************************************************************************** static inline void SysCtl_connectMCDClockSource(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) &= ~(0x8U); __edis(); } //***************************************************************************** // //! Disconnect missing clock detection clock source to simulate clock failure. //! This is for testing the MCD functionality. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disconnectMCDClockSource(void) { __eallow(); (*((volatile uint16_t *)(0x0005D200U + 0x2EU))) |= 0x8U; __edis(); } //***************************************************************************** // //! Configures the sync input source for the ePWM and eCAP signals. //! //! \param syncInput is the sync input being configured //! \param syncSrc is sync input source selection. //! //! This function configures the sync input source for the ePWM and eCAP //! modules. The \e syncInput parameter is the sync input being configured. It //! should be passed a value of \b SYSCTL_SYNC_IN_XXXX, where XXXX is the ePWM //! or eCAP instance the sync signal is entering. //! //! The \e syncSrc parameter is the sync signal selected as the source of the //! sync input. It should be passed a value of \b SYSCTL_SYNC_IN_SRC_XXXX, //! XXXX is a sync signal coming from an ePWM, eCAP or external sync output. //! where For example, a \e syncInput value of \b SYSCTL_SYNC_IN_ECAP1 and a //! \e syncSrc value of \b SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT will make the //! EPWM1SYNCOUT signal drive eCAP1's SYNCIN signal. //! //! Note that some \e syncSrc values are only valid for certain values of //! \e syncInput. See device technical reference manual for details on //! time-base counter synchronization. //! //! \return None. // //***************************************************************************** static inline void SysCtl_setSyncInputConfig(SysCtl_SyncInput syncInput, SysCtl_SyncInputSource syncSrc) { uint32_t clearMask; // // Write the input sync source selection to the appropriate register. // __eallow(); clearMask = (uint32_t)0x7U << (uint32_t)syncInput; (*((volatile uint32_t *)(0x00007940U + 0x0U))) = ((*((volatile uint32_t *)(0x00007940U + 0x0U))) & ~clearMask) | ((uint32_t)syncSrc << (uint32_t)syncInput); __edis(); } //***************************************************************************** // //! Configures the sync output source. //! //! \param syncSrc is sync output source selection. //! //! This function configures the sync output source from the ePWM modules. The //! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is //! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT //! //! \return None. // //***************************************************************************** static inline void SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc) { // // Write the sync output source selection to the appropriate register. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x0U))) = ((*((volatile uint32_t *)(0x00007940U + 0x0U))) & ~((uint32_t)0x18000000U)) | ((uint32_t)syncSrc << 27U); __edis(); } //***************************************************************************** // //! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal. //! //! \param adcsocSrc is a bit field of the selected signals to be enabled //! //! This function configures which ePWM SOC signals are enabled as a source for //! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR //! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different //! signals. //! //! \return None. // //***************************************************************************** static inline void SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc) { // // Set the bits that correspond to signal to be enabled. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x2U))) |= adcsocSrc; __edis(); } //***************************************************************************** // //! Disables ePWM SOC signals from driving an external ADCSOC signal. //! //! \param adcsocSrc is a bit field of the selected signals to be disabled //! //! This function configures which ePWM SOC signals are disabled as a source //! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical //! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different //! signals. //! //! \return None. // //***************************************************************************** static inline void SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc) { // // Clear the bits that correspond to signal to be disabled. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x2U))) &= ~adcsocSrc; __edis(); } //***************************************************************************** // //! Locks the SOC Select of the Trig X-BAR. //! //! This function locks the external ADC SOC select of the Trig X-BAR. //! //! \return None. // //***************************************************************************** static inline void SysCtl_lockExtADCSOCSelect(void) { // // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x4U))) = 0x2U; __edis(); } //***************************************************************************** // //! Configures whether a peripheral is connected to CPU1 or CPU2. //! //! \param peripheral is the peripheral for which CPU needs to be configured. //! \param peripheralInst is the instance for which CPU needs to be configured. //! \param cpuInst is the CPU to which the peripheral instance need to be //! connected. //! //! The \e peripheral parameter can have one enumerated value from //! SysCtl_CPUSelPeripheral //! //! The \e peripheralInst parameter is the instance number for e.g. //! 1 for EPWM1, 2 for EPWM2 etc...For instances which are named with alphabets //! (instead of numbers) the following convention needs to be followed. //! 1 for A (SPI_A), 2 for B (SPI_B), 3 for C (SPI_C) etc... //! //! The \e cpuInst parameter can have one the following values: //! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 //! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 //! //! \return Returns the low-speed peripheral clock frequency. // //***************************************************************************** static inline void SysCtl_selectCPUForPeripheral(SysCtl_CPUSelPeripheral peripheral, uint16_t peripheralInst, uint16_t cpuInst) { uint16_t tempValue = 0U; if(SYSCTL_CPUSEL14_DAC == peripheral) { peripheralInst = peripheralInst + 0x10U; } tempValue = (*((volatile uint32_t *)(0x0005D000U + 0xD6U + peripheral))) & (~(1 << (peripheralInst-1))); __eallow(); (*((volatile uint32_t *)(0x0005D000U + 0xD6U + peripheral))) = tempValue | ((uint32_t)cpuInst << (peripheralInst-1)); __edis(); } //***************************************************************************** // //! Configures whether whether the dual ported bridge is connected with DMA or //! CLA as the secondary master. //! //! \param periFrame1Config indicates whether CLA or DMA is configured as //! secondary master on peripheral frame 1. //! \param periFrame2Config indicates whether CLA or DMA is configured as //! secondary master on peripheral frame 2. //! //! One of the following values can be passed as parameter. //! \b SYSCTL_SEC_MASTER_CLA //! \b SYSCTL_SEC_MASTER_DMA //! //! \return None. // //***************************************************************************** static inline void SysCtl_selectSecMaster(uint16_t periFrame1Config, uint16_t periFrame2Config) { __eallow(); (*((volatile uint32_t *)(0x0005D300U + 0x74U))) = (((periFrame1Config << 0U) & 0x3U) | ((periFrame2Config << 2U) & 0xCU)); __edis(); } //***************************************************************************** // //! Locks the Sync Select of the Trig X-BAR. //! //! This function locks Sync Input and Output Select of the Trig X-BAR. //! //! \return None. // //***************************************************************************** static inline void SysCtl_lockSyncSelect(void) { // // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. // __eallow(); (*((volatile uint32_t *)(0x00007940U + 0x4U))) = 0x1U; __edis(); } //***************************************************************************** // //! Delays for a fixed number of cycles. //! //! \param count is the number of delay loop iterations to perform. //! //! This function generates a constant length delay using assembly code. The //! loop takes 5 cycles per iteration plus 9 cycles of overhead. //! //! \note If count is equal to zero, the loop will underflow and run for a //! very long time. //! //! \return None. // //***************************************************************************** extern void SysCtl_delay(uint32_t count); //***************************************************************************** // //! Calculates the system clock frequency (SYSCLK). //! //! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). //! //! This function determines the frequency of the system clock based on the //! frequency of the oscillator clock source (from \e clockInHz) and the PLL //! and clock divider configuration registers. //! //! \return Returns the system clock frequency. If a missing clock is detected, //! the function will return the INTOSC1 frequency. This needs to be //! corrected and cleared (see SysCtl_resetMCD()) before trying to call this //! function again. // //***************************************************************************** extern uint32_t SysCtl_getClock(uint32_t clockInHz); //***************************************************************************** // //! Calculates the system auxiliary clock frequency (AUXPLLCLK). //! //! \param clockInHz is the frequency of the oscillator clock source (AUXOSCCLK). //! //! This function determines the frequency of the auxiliary clock based on the //! frequency of the oscillator clock source (from \e clockInHz) and the AUXPLL //! and clock divider configuration registers. //! //! \return Returns the auzillary clock frequency. // //***************************************************************************** extern uint32_t SysCtl_getAuxClock(uint32_t clockInHz); //***************************************************************************** // //! Configures the clocking of the device. //! //! \param config is the required configuration of the device clocking. //! //! This function configures the clocking of the device. The input crystal //! frequency, oscillator to be used, use of the PLL, and the system clock //! divider are all configured with this function. //! //! The \e config parameter is the OR of several different values, many of //! which are grouped into sets where only one can be chosen. //! //! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x) //! where x is either 1 or an even value up to 126. //! //! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or //! \b SYSCTL_PLL_DISABLE. //! //! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value //! from 1 to 127. //! //! - The fractional multiplier is chosen with either \b SYSCTL_FMULT_0, //! \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or \b SYSCTL_FMULT_3_4. //! //! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2, //! \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. //! //! \return Returns \b false if a missing clock error is detected. This needs //! to be cleared (see SysCtl_resetMCD()) before trying to call this function //! again. Otherwise, returns \b true. // //***************************************************************************** extern _Bool SysCtl_setClock(uint32_t config); //***************************************************************************** // //! Selects the oscillator to be used for the clocking of the device. //! //! \param oscSource is the oscillator source to be configured. //! //! This function configures the oscillator to be used in the clocking of the //! device. The \e oscSource parameter may take a value of //! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. //! //! \sa SysCtl_turnOnOsc() //! //! \return None. // //***************************************************************************** extern void SysCtl_selectOscSource(uint32_t oscSource); //***************************************************************************** // //! Calculates the low-speed peripheral clock frequency (LSPCLK). //! //! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). //! //! This function determines the frequency of the low-speed peripheral clock //! based on the frequency of the oscillator clock source (from \e clockInHz) //! and the PLL and clock divider configuration registers. //! //! \return Returns the low-speed peripheral clock frequency. // //***************************************************************************** extern uint32_t SysCtl_getLowSpeedClock(uint32_t clockInHz); //***************************************************************************** // //! Configures the auxiliary PLL for clocking USB. //! //! \param config is the required configuration of the device clocking. //! //! This function configures the clock source for aux PLL, configures the //! multiplier, fractional multiplier and divider for aux PLL. And Also ensures //! the PLL is locked. //! //! The \e config parameter is the OR of several different values, many of //! which are grouped into sets where only one can be chosen. //! //! - The system clock divider is chosen with the macro one of the following macros //! \b SYSCTL_AUXPLL_DIVIDER_1 //! \b SYSCTL_AUXPLL_DIVIDER_2 //! \b SYSCTL_AUXPLL_DIVIDER_4 //! \b SYSCTL_AUXPLL_DIVIDER_8 //! passed through the macro SYSCTL_AUX_PLL_DIV(x) //! //! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or //! \b SYSCTL_PLL_DISABLE. //! //! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value //! from 1 to 127. //! //! - The fractional multiplier is chosen with either \b SYSCTL_AUXPLL_FMULT_0, //! \b SYSCTL_AUXPLL_FMULT_1_4, \b SYSCTL_AUXPLL_FMULT_1_2, or //! \b SYSCTL_AUXPLL_FMULT_3_4. //! //! - The oscillator source chosen with one of, //! \b SYSCTL_AUXOSC_CLKSRCSEL_INTOSC2 //! \b SYSCTL_AUXOSC_CLKSRCSEL_XTAL //! \b SYSCTL_AUXOSC_CLKSRCSEL_AUXCLKIN //! //! \return None. // //***************************************************************************** extern void SysCtl_setAuxClock(uint32_t config); //***************************************************************************** // // Close the Doxygen group. //! @} // //**************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //***************************************************************************** // //! //! \addtogroup stl_util Utilities API Functions //! @{ // //***************************************************************************** // // Defines // //#define STL_UTIL_CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT) //#define STL_UTIL_CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) // // Defines to specify the device for which to build the library. // Make sure only one of the three #defines below is uncommented for the build. // //#define STL_UTIL_BUILD_F2837XS //#define STL_UTIL_BUILD_F2807X // // Typedefs // // // 32-bit float type // typedef float float32_t; // // 64-bit float type // typedef long double float64_t; //! Values to be passed to STL_Util_setErrorFlag() and //! STL_Util_clearErrorFlag(). These correspond to different errors in the STL. // typedef enum { STL_UTIL_SCI_TX_TO = 0x0000000000000001ULL,//!< SCI transmit STL_UTIL_SCI_RX_TO = 0x0000000000000002ULL,//!< SCI receive STL_UTIL_SCI_RX_CRC = 0x0000000000000004ULL,//!< SCI CRC STL_UTIL_I2C_TX_TO = 0x0000000000000008ULL,//!< I2C transmit STL_UTIL_I2C_RX_TO = 0x0000000000000010ULL,//!< I2C receive STL_UTIL_I2C_RX_CRC = 0x0000000000000020ULL,//!< I2C CRC STL_UTIL_SPI_TX_TO = 0x0000000000000040ULL,//!< SPI transmit STL_UTIL_SPI_RX_TO = 0x0000000000000080ULL,//!< SPI receive STL_UTIL_SPI_RX_CRC = 0x0000000000000100ULL,//!< SPI CRC STL_UTIL_MCBSP_TX_TO = 0x0000000000000200ULL,//!< MCBSP transmit STL_UTIL_MCBSP_RX_TO = 0x0000000000000400ULL,//!< MCBSP receive STL_UTIL_MCBSP_RX_CRC = 0x0000000000000800ULL,//!< MCBSP CRC STL_UTIL_CAN_TX_TO = 0x0000000000001000ULL,//!< CAN transmit STL_UTIL_CAN_RX_TO = 0x0000000000002000ULL,//!< CAN receive STL_UTIL_CAN_RX_CRC = 0x0000000000004000ULL,//!< CAN CRC STL_UTIL_PIE_RAM_MISMATCH = 0x0000000000008000ULL,//!< PIE RAM STL_UTIL_PIE_RAM_INT = 0x0000000000010000ULL,//!< PIE RAM handler was executed STL_UTIL_FLASH_LOGIC = 0x0000000000020000ULL,//!< Flash ECC logic test failure STL_UTIL_FLASH_LOGIC_SINT = 0x0000000000040000ULL,//!< Flash ECC single bit error interrupt occurred in ECC logic test STL_UTIL_FLASH_LOGIC_UINT = 0x0000000000080000ULL,//!< Flash ECC uncorrectable error interrupt occurred in ECC logic test STL_UTIL_FLASH_DETECT = 0x0000000000100000ULL,//!< Flash ECC detect STL_UTIL_CRC = 0x0000000000200000ULL,//!< CRC Check STL_UTIL_OSC_TIMER2 = 0x0000000000400000ULL,//!< OSC timer 2 STL_UTIL_GPIO_INPUT = 0x0000000000800000ULL,//!< GPIO input STL_UTIL_GPIO_OUTPUT = 0x0000000001000000ULL,//!< GPIO output STL_UTIL_PIE = 0x0000000002000000ULL,//!< Interrupt STL_UTIL_CPUTIMER = 0x0000000004000000ULL,//!< CPU timer STL_UTIL_MCD = 0x0000000008000000ULL,//!< Missing clock STL_UTIL_NMIWD = 0x0000000010000000ULL,//!< NMI watchdog STL_UTIL_ADC_DAC = 0x0000000020000000ULL,//!< ADC/DAC Mismatch STL_UTIL_ADC_DAC_TO = 0x0000000040000000ULL,//!< ADC/DAC Time out STL_UTIL_WD = 0x0000000080000000ULL,//!< Watchdog STL_UTIL_PWM_TRIP_DUTY_CYCLE = 0x0000000100000000ULL,//!< PWM duty cycle mismatch STL_UTIL_PWM_TRIP_MISSING_EDGES = 0x0000000200000000ULL,//!< PWM edges not captured STL_UTIL_HWBIST_NMI_TEST = 0x0000000400000000ULL,//!< HWBIST NMI test STL_UTIL_HWBIST_FAIL = 0x0000000800000000ULL,//!< HWBIST fail STL_UTIL_HWBIST_NMI_INT = 0x0000001000000000ULL,//!< HWBIST NMI interrupt STL_UTIL_HWBIST_OVERRUN = 0x0000002000000000ULL,//!< HWBIST over-run STL_UTIL_DEVCFG = 0x0000004000000000ULL,//!< Device configuration STL_UTIL_RAM_LOGIC = 0x0000008000000000ULL,//!< RAM error logic test failure STL_UTIL_RAM_LOGIC_SINT = 0x0000010000000000ULL,//!< RAM single bit error interrupt occurred in ECC logic test STL_UTIL_RAM_LOGIC_UINT = 0x0000020000000000ULL,//!< RAM error uncorrectable error interrupt occurred in ECC/parity logic test STL_UTIL_RAM_DETECT = 0x0000040000000000ULL,//!< RAM error detect STL_UTIL_PER_REG = 0x0000080000000000ULL,//!< Register test STL_UTIL_SP_CORRUPT = 0x0000100000000000ULL,//!< SP in watchpoint monitored range STL_UTIL_SP = 0x0000200000000000ULL,//!< Stack pointer interrupt not generated STL_UTIL_ERRORSTS = 0x0000400000000000ULL,//!< Error status pin STL_UTIL_BROM = 0x0000800000000000ULL,//!< Boot ROM status STL_UTIL_MARCH = 0x0001000000000000ULL,//!< March RAM test STL_UTIL_INT_MON = 0x0002000000000000ULL,//!< Interrupt timing test STL_UTIL_SDFM = 0x0004000000000000ULL,//!< SDFM test STL_UTIL_SCI_MON = 0x0008000000000000ULL,//!< SCI monitor test STL_UTIL_OSC_HR_MEP_RANGE = 0x0010000000000000ULL,//!< MEP out of range STL_UTIL_OSC_HR_SFO = 0x0020000000000000ULL,//!< SFO calibration error STL_UTIL_OSC_HR_DELAY = 0x0040000000000000ULL,//!< SFO delay error STL_UTIL_EQEP = 0x0080000000000000ULL,//!< EQEP test STL_UTIL_IPC_MASTER = 0x0100000000000000ULL,//!< IPC Master STL_UTIL_IPC_SLAVE = 0x0200000000000000ULL //!< IPC Slave } STL_Util_ErrorFlag; //***************************************************************************** // //! Delay for a specified number of microseconds //! //! \param microseconds is the number of microseconds to delay. //! //! This function calls SysCtl_delay() to achieve a delay in microseconds. The //! function will convert the desired delay in microseconds to the count value //! expected by the function. \e microseconds is the number of microseconds to //! delay. //! //! \note If this function does not get inlined (for instance, if the optimizer //! is turned off) the delay will be made less accurate by the overhead of the //! additional function call. //! //! \return None. // //***************************************************************************** #pragma CODE_SECTION(STL_Util_delayUS, "ramfuncs") static inline void STL_Util_delayUS(uint32_t microseconds) { uint32_t delay = ((((float64_t)microseconds * 1000.0L) / (float64_t)5.00L) - 9.0L) / 5.0L; SysCtl_delay(delay); } //***************************************************************************** // //! Sets a global error flag. //! //! \param errorFlag is a STL_Util_ErrorFlag that will be set in //! globalErrorFlags. //! //! This function sets an error flag in the global globalErrorFlags. //! //! //! \return None. // //***************************************************************************** extern void STL_Util_setErrorFlag(const STL_Util_ErrorFlag errorFlag); //***************************************************************************** // //! Gets the error flag status of globalErrorFlags. //! //! This function returns the global globalErrorFlags. //! //! \return Returns the global globalErrorFlags. // //***************************************************************************** extern uint64_t STL_Util_getErrorFlag(void); //***************************************************************************** // //! Clears a flag of globalErrorFlags.. //! //! \param errorFlag is a STL_Util_ErrorFlag that will be cleared in //! globalErrorFlags. //! //! This function clears a flag of global globalErroFlags. //! //! \return None. // //***************************************************************************** extern void STL_Util_clearErrorFlag(const STL_Util_ErrorFlag errorFlag); //***************************************************************************** // //! Returns the contents of ST1 register. //! //! \return Returns the contents of ST1 register. // //***************************************************************************** extern uint32_t STL_Util_getST1(void); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** // // End of File // //***************************************************************************** // //! \addtogroup stl_crc CRC API Functions //! @{ // //***************************************************************************** // // Defines // // // Typedefs // //! \brief Parity enumeration //! //! The parity is used by the CRC algorithm to determine whether to begin //! calculations from the low byte (EVEN) or from the high byte (ODD) of the //! first word (16-bit) in the message. \n //! For example, if your message had 10 bytes and started at the address 0x8000 //! but the first byte was at the high byte position of the first 16-bit word, //! the user would call the CRC function with odd parity i.e. //! STL_CRC_PARITY_ODD \n //! Address: HI LO \n //! 0x8000 : B0 XX \n //! 0x8001 : B2 B1 \n //! 0x8002 : B4 B3 \n //! 0x8003 : B6 B5 \n //! 0x8004 : B8 B7 \n //! 0x8005 : XX B9 \n //! However, if the first byte was at the low byte position of the first 16-bit //! word, the user would call the CRC function with even parity i.e. //! STL_CRC_PARITY_EVEN \n //! Address: HI LO \n //! 0x8000 : B1 B0 \n //! 0x8001 : B3 B2 \n //! 0x8002 : B5 B4 \n //! 0x8003 : B7 B6 \n //! 0x8004 : B9 B8 \n // typedef enum { STL_CRC_PARITY_EVEN = 0, //!< Even parity, CRC starts at the low byte of //!< the first word (16-bit) STL_CRC_PARITY_ODD = 1 //!< Odd parity, CRC starts at the high byte of //!< the first word (16-bit) } STL_CRC_Parity; //! \brief CRC structure //! typedef struct { uint32_t seedValue; //!< Initial value of the CRC calculation uint16_t nMsgBytes; //!< Number of bytes in the message buffer STL_CRC_Parity parity; //!< Start the CRC from the low byte //!< or high byte uint32_t crcResult; //!< The calculated CRC void *pMsgBuffer; //!< Pointer to the message buffer } STL_CRC_Obj; //! \brief Handle to the CRC structure //! typedef STL_CRC_Obj *STL_CRC_Handle; // // Prototypes // //***************************************************************************** // //! \brief Workaround to the silicon issue of first VCU calculation on power up //! being erroneous //! //! Due to the internal power-up state of the VCU module, it is possible that //! the first CRC result will be incorrect. This condition applies to the //! first result from each of the eight CRC instructions. This rare condition //! can only occur after a power-on reset, but will not necessarily occur on //! every power on. A warm reset will not cause this condition to reappear. //! //! Workaround(s): The application can reset the internal VCU CRC logic by //! performing a CRC calculation of a single byte in the initialization //! routine. This routine only needs to perform one CRC calculation and can use //! any of the CRC instructions. //! //! \return None. // //***************************************************************************** extern void STL_CRC_reset(void); //***************************************************************************** // //! \brief Initializes the CRC object //! //! \param[in] hndCRC handle to the CRC object //! //! Clears the CRCMSGFLIP bit, ensuring the input is interpreted in normal //! bit-order. //! //! \return None. // //***************************************************************************** extern void STL_CRC_init32Bit(STL_CRC_Handle hndCRC); //***************************************************************************** // //! \brief Runs the 32-bit CRC routine using polynomial 0x04c11db7 //! //! \param[in] hndCRC handle to the CRC object //! //! Calculates the 32-bit CRC using polynomial 0x04c11db7 on the VCU. //! Depending on the parity chosen the CRC begins at either //! the low byte (STL_CRC_PARITY_EVEN) or the high byte (STL_CRC_PARITY_ODD) //! of the first word (16-bit). //! //! \note The size of the message (bytes) is limited to 65535 bytes. //! //! \return None. // //***************************************************************************** extern void STL_CRC_run32BitPoly1(STL_CRC_Handle hndCRC); //***************************************************************************** // //! \brief Runs the 32-bit CRC routine using polynomial 0x04c11db7 //! //! \param[in] hndCRC handle to the CRC object //! //! Calculates the 32-bit CRC using polynomial 0x04c11db7 on the VCU. //! Depending on the parity chosen the CRC begins at either //! the low byte (STL_CRC_PARITY_EVEN) or the high byte (STL_CRC_PARITY_ODD) //! of the first word (16-bit). //! //! \note The size of the message (bytes) is limited to 65535 bytes. //! //! This function works on unpacked data. //! //! \return None. // //***************************************************************************** extern void STL_CRC_run32BitPoly1_LowBytes(STL_CRC_Handle hndCRC); //***************************************************************************** // //! \brief Calculates a CRC-32 value for specific memory range and compares it //! with the goldenCRC value. //! //! \param startAddress - start address of CRC calculation. //! \param endAddress - end address of CRC calculation, inclusive. //! \param goldenCRC - golden CRC value. //! //! This functions performs a test of the memory range by calculating the //! CRC-32 value for the input memory range and comparing it with the golden //! CRC value. //! //! \note This function could be used with many memory types including //! Flash and Boot ROM. //! //! \return If the calculated CRC matches the golden CRC, then the function //! returns \b STL_CRC_PASS. Otherwise, it returns \b STL_CRC_FAIL. // //***************************************************************************** extern uint16_t STL_CRC_checkCRC(const uint32_t startAddress, const uint32_t endAddress, const uint32_t goldenCRC); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** // // End of File // //############################################################################# // // FILE: stl_can.h // // TITLE: // // //############################################################################# // $TI Release: $ // $Release Date: $ // $Copyright: $ //############################################################################# //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** // // Includes // //########################################################################### // // FILE: can.h // // TITLE: C28x CAN driver. // //########################################################################### // $TI Release: $ // $Release Date: $ // $Copyright: $ //########################################################################### //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** //***************************************************************************** // //! \addtogroup can_api CAN //! \brief This module configures and interacts with the device's controller //! area network bus //! @{ // //***************************************************************************** //########################################################################### // // FILE: hw_can.h // // TITLE: Definitions for the CAN registers. // //########################################################################### // $TI Release: F2837xD Support Library v2.00.00.00 $ // $Release Date: Thu Jun 30 15:51:34 CDT 2016 $ // $Copyright: // Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //***************************************************************************** // // The following are defines for the CAN register offsets // //***************************************************************************** // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register // Register //***************************************************************************** // // The following are defines for the bit fields in the CAN_CTL register // //***************************************************************************** // Disabled // Enable Disabled // Disabled // Retransmission // Enable // Disabled //***************************************************************************** // // The following are defines for the bit fields in the CAN_ES register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_ERRC register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_BTR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_INT register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_TEST register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_PERR register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_REL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_RAM_INIT register // //***************************************************************************** // complete //***************************************************************************** // // The following are defines for the bit fields in the CAN_GLB_INT_EN register // //***************************************************************************** // CAN INT0 // CAN INT1 //***************************************************************************** // // The following are defines for the bit fields in the CAN_GLB_INT_FLG register // //***************************************************************************** // INT0 // INT1 //***************************************************************************** // // The following are defines for the bit fields in the CAN_GLB_INT_CLR register // //***************************************************************************** // for CAN INT0 // for CAN INT1 //***************************************************************************** // // The following are defines for the bit fields in the CAN_TXRQ_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_NDAT_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IPEN_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_MVAL_X register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1CMD register // //***************************************************************************** // Bit //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1MSK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1ARB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF1DATB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2CMD register // //***************************************************************************** // Bit //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2MSK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2ARB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF2DATB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3OBS register // //***************************************************************************** // observation // access // data read access // read access // access // access //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3MSK register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3ARB register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3MCTL register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3DATA register // //***************************************************************************** //***************************************************************************** // // The following are defines for the bit fields in the CAN_IF3DATB register // //***************************************************************************** // // The key value for RAM initialization // // // The Parity disable key value // // // This is the maximum number that can be stored as an 11bit Message // identifier. // // // The maximum CAN bit timing divisor is 13. // // // The minimum CAN bit timing divisor is 5. // // // The maximum CAN pre-divisor is 1024. // // // The minimum CAN pre-divisor is 1. // //***************************************************************************** // // Miscellaneous defines for Message ID Types // //***************************************************************************** //***************************************************************************** // // These are the flags used by the flags parameter when calling // the CAN_setupMessageObject() function. // //***************************************************************************** //! This indicates that transmit interrupts should be enabled, or are enabled. //! This indicates that receive interrupts should be enabled, or are //! enabled. //! This indicates that a message object will use or is using filtering //! based on the object's message identifier. //! This indicates that a message object will use or is using filtering //! based on the direction of the transfer. //! This indicates that a message object will use or is using message //! identifier filtering based on the extended identifier. //! This indicates that this message object is part of a FIFO structure and //! not the final message object in a FIFO. //! This indicates that a message object has no flags set. //***************************************************************************** // // These definitions are used to specify interrupt sources to // CAN_enableInterrupt() and CAN_disableInterrupt(). // //***************************************************************************** //! This flag is used to allow a CAN controller to generate error //! interrupts. //! This flag is used to allow a CAN controller to generate status //! interrupts. //! This flag is used to allow a CAN controller to generate interrupts //! on interrupt line 0 //! This flag is used to allow a CAN controller to generate interrupts //! on interrupt line 1 //***************************************************************************** // // The following definitions contain all error or status indicators that can // be returned when calling the CAN_getStatus() function. // //***************************************************************************** //! CAN controller is in local power down mode. //! CAN controller has initiated a system wakeup. //! CAN controller has detected a parity error. //! CAN controller has entered a Bus Off state. //! CAN controller error level has reached warning level. //! CAN controller error level has reached error passive level. //! A message was received successfully since the last read of this status. //! A message was transmitted successfully since the last read of this //! status. //! This is the mask for the last error code field. //! There was no error. //! A bit stuffing error has occurred. //! A formatting error has occurred. //! An acknowledge error has occurred. //! The bus remained a bit level of 1 for longer than is allowed. //! The bus remained a bit level of 0 for longer than is allowed. //! A CRC error has occurred. //***************************************************************************** // // The following macros are added for the Global Interrupt EN/FLG/CLR // register // //***************************************************************************** //! CANINT0 global interrupt bit //! CANINT1 global interrupt bit //***************************************************************************** // // The following macros are added for accessing the interrupt register and // the standard arbitration ID in the interface registers. // //***************************************************************************** //! Status of INT0ID //! IF1 Arbitration Standard ID Shift Offset //! IF1 Arbitration Standard ID Mask //! IF2 Arbitration Standard ID Shift Offset //! IF2 Arbitration Standard ID Mask //***************************************************************************** // //! This data type is used to identify the interrupt status register. This is //! used when calling the CAN_setupMessageObject() function. // //***************************************************************************** typedef enum { //! Set the message ID frame to standard. CAN_MSG_FRAME_STD, //! Set the message ID frame to extended. CAN_MSG_FRAME_EXT } CAN_MsgFrameType; //***************************************************************************** // //! This definition is used to determine the type of message object that will //! be set up via a call to the CAN_setupMessageObject() API. // //***************************************************************************** typedef enum { //! Transmit message object. CAN_MSG_OBJ_TYPE_TX, //! Transmit remote request message object CAN_MSG_OBJ_TYPE_TX_REMOTE, //! Receive message object. CAN_MSG_OBJ_TYPE_RX, //! Remote frame receive remote, with auto-transmit message object. CAN_MSG_OBJ_TYPE_RXTX_REMOTE } CAN_MsgObjType; //***************************************************************************** // //! This definition is used to determine the clock source that will //! be set up via a call to the CAN_selectClockSource() API. // //***************************************************************************** typedef enum { //! Peripheral System Clock Source CAN_CLOCK_SOURCE_SYS = 0x0, //! External Oscillator Clock Source CAN_CLOCK_SOURCE_XTAL = 0x1, //! Auxiliary Clock Input Source CAN_CLOCK_SOURCE_AUX = 0x2 } CAN_ClockSource; //***************************************************************************** // // Prototypes for the APIs. // //***************************************************************************** //***************************************************************************** // //! \internal //! //! Checks a CAN base address. //! //! \param base is the base address of the CAN controller. //! //! This function determines if a CAN controller base address is valid. //! //! \return Returns \b true if the base address is valid and \b false //! otherwise. // //***************************************************************************** static _Bool CAN_isBaseValid(uint32_t base) { return((base == 0x00048000U)||(base == 0x0004A000U)); } //***************************************************************************** // //! \internal //! //! Copies data from a buffer to the CAN Data registers. //! //! \param data is a pointer to the data to be written out to the CAN //! controller's data registers. //! \param address is an int16_t pointer to the first register of the //! CAN controller's data registers. For example, in order to use the IF1 //! CAN controller's data registers. For example, in order to use the IF1 //! register set on CAN controller 0, the value would be: \b CANA_BASE \b + //! \b CAN_O_IF1DATA. //! \param size is the number of bytes to copy into the CAN controller. //! //! This function takes the steps necessary to copy data from a contiguous //! buffer in memory into the non-contiguous data registers used by the CAN //! controller. //! //! \return None. // //***************************************************************************** static void CAN_writeDataReg(const uint16_t *const data, int16_t *address, uint32_t size) { uint32_t idx; int16_t *dataReg = address; // // Loop always copies 1 byte per iteration. // for(idx = 0U; idx < size; idx++) { // // Write out the data 8 bits at a time. // if(dataReg != 0U) { __byte((int16_t *)(dataReg),0) = data[idx]; dataReg++; } } } //***************************************************************************** // //! \internal //! //! Copies data from a buffer to the CAN Data registers. //! //! \param data is a pointer to the location to store the data read from the //! CAN controller's data registers. //! \param address is an int16_t pointer to the first register of the //! CAN controller's data registers. For example, in order to use the IF1 //! register set on CAN controller 1, the value would be: \b CANA_BASE \b + //! \b CAN_O_IF1DATA. //! \param size is the number of bytes to copy from the CAN controller. //! //! This function takes the steps necessary to copy data to a contiguous buffer //! in memory from the non-contiguous data registers used by the CAN //! controller. //! //! \return None. // //***************************************************************************** static void CAN_readDataReg(uint16_t *data, int16_t *address, uint32_t size) { uint32_t idx; int16_t *dataReg = address; // // Loop always copies 1 byte per iteration. // for(idx = 0U; idx < size; idx++) { // // Read out the data // data[idx] = __byte((int16_t *)(dataReg),0); dataReg++; } } //***************************************************************************** // //! Initializes the CAN controller's RAM. //! //! \param base is the base address of the CAN controller. //! //! Performs the initialization of the RAM used for the CAN message objects. //! //! \return None. // //***************************************************************************** static inline void CAN_initRAM(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 418); } } while(0); (*((volatile uint16_t *)(base + 0x40U))) = 0x10U | (0xAU); while(!(((*((volatile uint16_t *)(base + 0x40U))) & 0x20U) == 0x20U)) { // // Wait until RAM Init is complete // } } //***************************************************************************** // //! Select CAN Clock Source //! //! \param base is the base address of the CAN controller. //! \param source is the clock source to use for the CAN controller. //! //! This function selects the specified clock source for the CAN controller. //! //! The \e source parameter can be any one of the following: //! - \b CAN_CLOCK_SOURCE_SYS - Peripheral System Clock //! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator //! - \b CAN_CLOCK_SOURCE_AUX - Auxiliary Clock Input from GPIO //! //! \return None. // //***************************************************************************** static inline void CAN_selectClockSource(uint32_t base, CAN_ClockSource source) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 455); } } while(0); // // Determine the CAN controller and set specified clock source // __eallow(); switch(base) { case 0x00048000U: (*((volatile uint16_t *)(0x0005D200U + 0xAU))) &= ~0xCU; (*((volatile uint16_t *)(0x0005D200U + 0xAU))) |= ((uint16_t)source << 2U); break; case 0x0004A000U: (*((volatile uint16_t *)(0x0005D200U + 0xAU))) &= ~0x30U; (*((volatile uint16_t *)(0x0005D200U + 0xAU))) |= ((uint16_t)source << 4U); break; default: // Do nothing. Not a valid mode value. break; } __edis(); } //***************************************************************************** // //! Starts the CAN Module's Operations //! //! \param base is the base address of the CAN controller. //! //! This function starts the CAN module's operations after initialization, //! which includes the CAN protocol controller state machine of the CAN core //! and the message handler state machine to begin controlling the CAN's //! internal data flow. //! //! \return None. // //***************************************************************************** static inline void CAN_startModule(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 508); } } while(0); // // Clear Init and CCE bits // (*((volatile uint16_t *)(base + 0x0U))) &= ~(0x1U | 0x40U); } //***************************************************************************** // //! Enables the CAN controller. //! //! \param base is the base address of the CAN controller to enable. //! //! Enables the CAN controller for message processing. Once enabled, the //! controller will automatically transmit any pending frames, and process any //! received frames. The controller can be stopped by calling //! CAN_disableController(). //! //! \return None. // //***************************************************************************** static inline void CAN_enableController(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 536); } } while(0); // // Clear the init bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x1U; } //***************************************************************************** // //! Disables the CAN controller. //! //! \param base is the base address of the CAN controller to disable. //! //! Disables the CAN controller for message processing. When disabled, the //! controller will no longer automatically process data on the CAN bus. The //! controller can be restarted by calling CAN_enableController(). The state //! of the CAN controller and the message objects in the controller are left as //! they were before this call was made. //! //! \return None. // //***************************************************************************** static inline void CAN_disableController(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 565); } } while(0); // // Set the init bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x1U; } //***************************************************************************** // //! Enables the test modes of the CAN controller. //! //! \param base is the base address of the CAN controller. //! \param mode are the the test modes to enable. //! //! Enables test modes within the controller. The following valid options for //! \e mode can be OR'ed together: //! - \b CAN_TEST_SILENT - Silent Mode //! - \b CAN_TEST_LBACK - Loopback Mode //! - \b CAN_TEST_EXL - External Loopback Mode //! //! \note Loopback mode and external loopback mode \b can \b not be //! enabled at the same time. //! //! \return None. // //***************************************************************************** static inline void CAN_enableTestMode(uint32_t base, uint16_t mode) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 598); } } while(0); do { if(!((mode & (0x10U | 0x100U)) != (0x10U | 0x100U))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 600); } } while(0); // // Clear the bits in the test register. // (*((volatile uint16_t *)(base + 0x14U))) &= ~((uint16_t)0x8U | (uint16_t)0x10U | (uint16_t)0x100U); // // Enable test mode and set the bits in the test register. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x80U; (*((volatile uint16_t *)(base + 0x14U))) |= mode; } //***************************************************************************** // //! Disables the test modes of the CAN controller. //! //! \param base is the base address of the CAN controller. //! //! Disables test modes within the controller and clears the test bits. //! //! \return None. // //***************************************************************************** static inline void CAN_disableTestMode(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 633); } } while(0); // // Clear the bits in the test register. // (*((volatile uint16_t *)(base + 0x14U))) &= ~((uint16_t)0x8U | (uint16_t)0x10U | (uint16_t)0x100U); // // Clear the test mode enable bit // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x80U; } //***************************************************************************** // //! Get the current settings for the CAN controller bit timing. //! //! \param base is the base address of the CAN controller. //! //! This function reads the current configuration of the CAN controller bit //! clock timing. //! //! \return Returns the value of the bit timing register. // //***************************************************************************** static inline uint32_t CAN_getBitTiming(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 666); } } while(0); // // Read and return BTR register // return(__byte_peripheral_32((uint32_t *)(base + 0xCU))); } //***************************************************************************** // //! Enables direct access to the RAM. //! //! \param base is the base address of the CAN controller. //! //! Enables direct access to the RAM while in Test mode. //! //! \note Test Mode must first be enabled to use this function. //! //! \return None. // //***************************************************************************** static inline void CAN_enableMemoryAccessMode(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 693); } } while(0); // // Set the RAM direct access bit // (*((volatile uint16_t *)(base + 0x14U))) |= 0x200U; } //***************************************************************************** // //! Disables direct access to the RAM. //! //! \param base is the base address of the CAN controller. //! //! Disables direct access to the RAM while in Test mode. //! //! \return None. // //***************************************************************************** static inline void CAN_disableMemoryAccessMode(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 718); } } while(0); // // Clear the RAM direct access bit // (*((volatile uint16_t *)(base + 0x14U))) &= ~0x200U; } //***************************************************************************** // //! Sets the interruption debug mode of the CAN controller. //! //! \param base is the base address of the CAN controller. //! \param enable is a flag to enable or disable the interruption debug mode. //! //! This function sets the interruption debug mode of the CAN controller. When //! the \e enable parameter is \b true, CAN will be configured to interrupt any //! transmission or reception and enter debug mode immediately after it is //! requested. When \b false, CAN will wait for a started transmission or //! reception to be completed before entering debug mode. //! //! \return None. // //***************************************************************************** static inline void CAN_setInterruptionDebugMode(uint32_t base, _Bool enable) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 748); } } while(0); if(enable) { // // Enable interrupt debug support // (*((volatile uint16_t *)(base + 0x0U))) |= 0x100U; } else { // // Disable interrupt debug support // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x100U; } } //***************************************************************************** // //! Disables Auto-Bus-On. //! //! \param base is the base address of the CAN controller. //! //! Disables the Auto-Bus-On feature of the CAN controller. //! //! \return None. // //***************************************************************************** static inline void CAN_disableAutoBusOn(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 784); } } while(0); // // Clear the ABO bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x200U; } //***************************************************************************** // //! Enables Auto-Bus-On. //! //! \param base is the base address of the CAN controller. //! //! Enables the Auto-Bus-On feature of the CAN controller. Be sure to also //! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function. //! //! \return None. // //***************************************************************************** static inline void CAN_enableAutoBusOn(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 810); } } while(0); // // Set the ABO bit in the control register. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x200U; } //***************************************************************************** // //! Sets the time before a Bus-Off recovery sequence is started. //! //! \param base is the base address of the CAN controller. //! \param time is number of clock cycles before a Bus-Off recovery sequence //! is started. //! //! This function sets the number of clock cycles before a Bus-Off recovery //! sequence is started by clearing the Init bit. //! //! \note To enable this functionality, use CAN_enableAutoBusOn(). //! //! \return None. // //***************************************************************************** static inline void CAN_setAutoBusOnTime(uint32_t base, uint32_t time) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 840); } } while(0); // // Set bus-off timer value // __byte_peripheral_32((uint32_t *)(base + 0x80U)) = time; } //***************************************************************************** // //! Enables individual CAN controller interrupt sources. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Enables specific interrupt sources of the CAN controller. Only enabled //! sources will cause a processor interrupt. //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_INT_ERROR - a controller error condition has occurred //! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has //! been detected //! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt //! line 0 //! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt //! line 1 //! //! \return None. // //***************************************************************************** static inline void CAN_enableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 876); } } while(0); do { if(!((intFlags & ~((0x00000008U) | (0x00000004U) | (0x00000002U) | (0x00020000U))) == 0U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 878); } } while(0); // // Enable the specified interrupts. // __byte_peripheral_32((uint32_t *)(base + 0x0U)) |= intFlags; } //***************************************************************************** // //! Disables individual CAN controller interrupt sources. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! Disables the specified CAN controller interrupt sources. Only enabled //! interrupt sources can cause a processor interrupt. //! //! The \e intFlags parameter has the same definition as in the //! CAN_enableInterrupt() function. //! //! \return None. // //***************************************************************************** static inline void CAN_disableInterrupt(uint32_t base, uint32_t intFlags) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 908); } } while(0); do { if(!((intFlags & ~((0x00000008U) | (0x00000004U) | (0x00000002U) | (0x00020000U))) == 0U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 910); } } while(0); // // Disable the specified interrupts. // __byte_peripheral_32((uint32_t *)(base + 0x0U)) &= ~(intFlags); } //***************************************************************************** // //! Get the CAN controller Interrupt Line set for each mailbox //! //! \param base is the base address of the CAN controller. //! //! Gets which interrupt line each message object should assert when an //! interrupt occurs. Bit 0 corresponds to message object 32 and then bits //! 1 to 31 correspond to message object 1 through 31 respectively. Bits that //! are asserted indicate the message object should generate an interrupt on //! interrupt line 1, while bits that are not asserted indicate the message //! object should generate an interrupt on line 0. //! //! \return Returns the value of the interrupt muxing register. // //***************************************************************************** static inline uint32_t CAN_getInterruptMux(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 940); } } while(0); // // Get the interrupt muxing for the CAN peripheral // return(__byte_peripheral_32((uint32_t *)(base + 0xD8U))); } //***************************************************************************** // //! Set the CAN controller Interrupt Line for each mailbox //! //! \param base is the base address of the CAN controller. //! \param mux bit packed representation of which message objects should //! generate an interrupt on a given interrupt line. //! //! Selects which interrupt line each message object should assert when an //! interrupt occurs. Bit 0 corresponds to message object 32 and then bits //! 1 to 31 correspond to message object 1 through 31 respectively. Bits that //! are asserted indicate the message object should generate an interrupt on //! interrupt line 1, while bits that are not asserted indicate the message //! object should generate an interrupt on line 0. //! //! \return None. // //***************************************************************************** static inline void CAN_setInterruptMux(uint32_t base, uint32_t mux) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 972); } } while(0); // // Set the interrupt muxing for the CAN peripheral // __byte_peripheral_32((uint32_t *)(base + 0xD8U)) = mux; } //***************************************************************************** // //! Enables the CAN controller automatic retransmission behavior. //! //! \param base is the base address of the CAN controller. //! //! Enables the automatic retransmission of messages with detected errors. //! //! \return None. // //***************************************************************************** static inline void CAN_enableRetry(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 997); } } while(0); // // Clearing the DAR bit tells the controller to not disable the // auto-retry of messages which were not transmitted or received // correctly. // (*((volatile uint16_t *)(base + 0x0U))) &= ~0x20U; } //***************************************************************************** // //! Disables the CAN controller automatic retransmission behavior. //! //! \param base is the base address of the CAN controller. //! //! Disables the automatic retransmission of messages with detected errors. //! //! \return None. // //***************************************************************************** static inline void CAN_disableRetry(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1024); } } while(0); // // Setting the DAR bit tells the controller to disable the auto-retry // of messages which were not transmitted or received correctly. // (*((volatile uint16_t *)(base + 0x0U))) |= 0x20U; } //***************************************************************************** // //! Returns the current setting for automatic retransmission. //! //! \param base is the base address of the CAN controller. //! //! Reads the current setting for the automatic retransmission in the CAN //! controller and returns it to the caller. //! //! \return Returns \b true if automatic retransmission is enabled, \b false //! otherwise. // //***************************************************************************** static inline _Bool CAN_isRetryEnabled(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1052); } } while(0); // // Read the disable automatic retry setting from the CAN controller. // return((_Bool)(((*((volatile uint16_t *)(base + 0x0U))) & 0x20U) != 0x20U)); } //***************************************************************************** // //! Reads the CAN controller error counter register. //! //! \param base is the base address of the CAN controller. //! \param rxCount is a pointer to storage for the receive error counter. //! \param txCount is a pointer to storage for the transmit error counter. //! //! Reads the error counter register and returns the transmit and receive error //! counts to the caller along with a flag indicating if the controller receive //! counter has reached the error passive limit. The values of the receive and //! transmit error counters are returned through the pointers provided as //! parameters. //! //! After this call, \e rxCount will hold the current receive error count //! and \e txCount will hold the current transmit error count. //! //! \return Returns \b true if the receive error count has reached the error //! passive limit, and \b false if the error count is below the error passive //! limit. // //***************************************************************************** static inline _Bool CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount) { uint32_t canError = 0U; // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1090); } } while(0); // // Read the current count of transmit/receive errors. // canError = __byte_peripheral_32((uint32_t *)(base + 0x8U)); // // Extract the error numbers from the register value. // *rxCount = (canError & 0x7F00U) >> 8U; *txCount = (canError & 0xFFU) >> 0U; return((_Bool)((canError & 0x8000U) != 0U)); } //***************************************************************************** // //! Reads the CAN controller error and status register. //! //! \param base is the base address of the CAN controller. //! //! Reads the error and status register of the CAN controller. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint16_t CAN_getStatus(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1123); } } while(0); // // Return error and status register value // return((*((volatile uint16_t *)(base + 0x4U)))); } //***************************************************************************** // //! Reads the CAN controller TX request register. //! //! \param base is the base address of the CAN controller. //! //! Reads the TX request register of the CAN controller. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint32_t CAN_getTxRequests(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1148); } } while(0); // // Return Tx requests register value // return(__byte_peripheral_32((uint32_t *)(base + 0x88U))); } //***************************************************************************** // //! Reads the CAN controller new data status register. //! //! \param base is the base address of the CAN controller. //! //! Reads the new data status register of the CAN controller for all message //! objects. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint32_t CAN_getNewDataFlags(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1174); } } while(0); // // Return new data register value // return(__byte_peripheral_32((uint32_t *)(base + 0x9CU))); } //***************************************************************************** // //! Reads the CAN controller valid message object register. //! //! \param base is the base address of the CAN controller. //! //! Reads the valid message object register of the CAN controller. //! //! \return Returns the value of the register. // //***************************************************************************** static inline uint32_t CAN_getValidMessageObjects(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1199); } } while(0); // // Return the valid message register value // return(__byte_peripheral_32((uint32_t *)(base + 0xC4U))); } //***************************************************************************** // //! Get the CAN controller interrupt cause. //! //! \param base is the base address of the CAN controller. //! //! This function returns the value of the interrupt register that indicates //! the cause of the interrupt. //! //! \return Returns the value of the interrupt register. // //***************************************************************************** static inline uint32_t CAN_getInterruptCause(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1225); } } while(0); // // Read interrupt identifier status // return(__byte_peripheral_32((uint32_t *)(base + 0x10U))); } //***************************************************************************** // //! Get the CAN controller pending interrupt message source. //! //! \param base is the base address of the CAN controller. //! //! Returns the value of the pending interrupts register that indicates //! which messages are the source of pending interrupts. //! //! \return Returns the value of the pending interrupts register. // //***************************************************************************** static inline uint32_t CAN_getInterruptMessageSource(uint32_t base) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1251); } } while(0); // // Read message object interrupt status // return(__byte_peripheral_32((uint32_t *)(base + 0xB0U))); } //***************************************************************************** // //! CAN Global interrupt Enable function. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Enables specific CAN interrupt in the global interrupt enable register //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt Enable bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt Enable bit for CAN INT1 //! //! \return None. // //***************************************************************************** static inline void CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1281); } } while(0); do { if(!((intFlags & ~((0x00000001U) | (0x00000002U))) == 0U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1283); } } while(0); // // Enable the requested interrupts // (*((volatile uint16_t *)(base + 0x50U))) |= intFlags; } //***************************************************************************** // //! CAN Global interrupt Disable function. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be disabled. //! //! Disables the specific CAN interrupt in the global interrupt enable register //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 //! //! \return None. // //***************************************************************************** static inline void CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1313); } } while(0); do { if(!((intFlags & ~((0x00000001U) | (0x00000002U))) == 0U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1315); } } while(0); // // Disable the requested interrupts // (*((volatile uint16_t *)(base + 0x50U))) &= ~intFlags; } //***************************************************************************** // //! CAN Global interrupt Clear function. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be cleared. //! //! Clear the specific CAN interrupt bit in the global interrupt flag register. //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 //! //! \return None. // //***************************************************************************** static inline void CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1345); } } while(0); do { if(!((intFlags & ~((0x00000001U) | (0x00000002U))) == 0U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1347); } } while(0); // // Clear the requested interrupts // (*((volatile uint16_t *)(base + 0x58U))) |= intFlags; } //***************************************************************************** // //! Get the CAN Global Interrupt status. //! //! \param base is the base address of the CAN controller. //! \param intFlags is the bit mask of the interrupt sources to be enabled. //! //! Check if any interrupt bit is set in the global interrupt flag register. //! //! The \e intFlags parameter is the logical OR of any of the following: //! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 //! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 //! //! \return True if any of the requested interrupt bits are set. False, if //! none of the requested bits are set. // //***************************************************************************** static inline _Bool CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags) { // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1378); } } while(0); do { if(!((intFlags & ~((0x00000001U) | (0x00000002U))) == 0U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/driverlib/f2837xd/driverlib/can.h", 1380); } } while(0); // // Read and return the global interrupt flag register // return((_Bool)(((*((volatile uint16_t *)(base + 0x54U))) & intFlags) != 0U)); } //***************************************************************************** // //! Initializes the CAN controller //! //! \param base is the base address of the CAN controller. //! //! This function initializes the message RAM, which also clears all the //! message objects, and places the CAN controller in an init state. Write //! access to the configuration registers is available as a result, allowing //! the bit timing and message objects to be setup. //! //! \note To exit the initialization mode and start the CAN module, use the //! CAN_startModule() function. //! //! \return None. // //***************************************************************************** extern void CAN_initModule(uint32_t base); //***************************************************************************** // //! Sets the CAN Bit Timing based on requested Bit Rate. //! //! \param base is the base address of the CAN controller. //! \param clock is the CAN module clock frequency before the bit rate //! prescaler (Hertz) //! \param bitRate is the desired bit rate (bits/sec) //! \param bitTime is the number of time quanta per bit required for desired //! bit time (Tq) and must be in the range from 8 to 25 //! //! This function sets the CAN bit timing values for the bit rate passed in the //! \e bitRate and \e bitTime parameters based on the \e clock parameter. The //! CAN bit clock is calculated to be an average timing value that should work //! for most systems. If tighter timing requirements are needed, then the //! CAN_setBitTiming() function is available for full customization of all of //! the CAN bit timing values. //! //! \return None. // //***************************************************************************** extern void CAN_setBitRate(uint32_t base, uint32_t clock, uint32_t bitRate, uint16_t bitTime); //***************************************************************************** // //! Manually set the CAN controller bit timing. //! //! \param base is the base address of the CAN controller. //! \param prescaler is the baud rate prescaler //! \param prescalerExtension is the baud rate prescaler extension //! \param tSeg1 is the time segment 1 //! \param tSeg2 is the time segment 2 //! \param sjw is the synchronization jump width //! //! This function sets the various timing parameters for the CAN bus bit //! timing: baud rate prescaler, prescaler extension, time segment 1, //! time segment 2, and the Synchronization Jump Width. //! //! \return None. // //***************************************************************************** extern void CAN_setBitTiming(uint32_t base, uint16_t prescaler, uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, uint16_t sjw); //***************************************************************************** // //! Clears a CAN interrupt source. //! //! \param base is the base address of the CAN controller. //! \param intClr is a value indicating which interrupt source to clear. //! //! This function can be used to clear a specific interrupt source. The //! \e intClr parameter should be either a number from 1 to 32 to clear a //! specific message object interrupt or can be the following: //! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt. //! //! It is not necessary to use this function to clear an interrupt. This //! should only be used if the application wants to clear an interrupt source //! without taking the normal interrupt action. //! //! \return None. // //***************************************************************************** extern void CAN_clearInterruptStatus(uint32_t base, uint32_t intClr); //***************************************************************************** // //! Setup a Message Object //! //! \param base is the base address of the CAN controller. //! \param objID is the message object number to configure (1-32). //! \param msgID is the CAN message identifier used for the 11 or 29 bit //! identifiers //! \param frame is the CAN ID frame type //! \param msgType is the message object type //! \param msgIDMask is the CAN message identifier mask used when identifier //! filtering is enabled //! \param flags is the various flags and settings to be set for the message //! object //! \param msgLen is the number of bytes of data in the message object (0-15) //! //! This function sets the various values required for a message object. //! //! The \e frame parameter can be one of the following values: //! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier //! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier //! //! The \e msgType parameter can be one of the following values: //! - \b CAN_MSG_OBJ_TYPE_TX - Transmit Message //! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE - Transmit Remote Message //! - \b CAN_MSG_OBJ_TYPE_RX - Receive Message //! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with //! auto-transmit //! //! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags //! are required or the parameter can be a logical OR of any of the following //! values: //! - \b CAN_MSG_OBJ_TX_INT_ENABLE - Enable Transmit Interrupts //! - \b CAN_MSG_OBJ_RX_INT_ENABLE - Enable Receive Interrupts //! - \b CAN_MSG_OBJ_USE_ID_FILTER - Use filtering based on the Message ID //! - \b CAN_MSG_OBJ_USE_EXT_FILTER - Use filtering based on the Extended //! Message ID //! - \b CAN_MSG_OBJ_USE_DIR_FILTER - Use filtering based on the direction of //! the transfer //! - \b CAN_MSG_OBJ_FIFO - Message object is part of a FIFO //! structure and isn't the final message //! object in FIFO //! //! \return None. // //***************************************************************************** extern void CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, CAN_MsgFrameType frame, CAN_MsgObjType msgType, uint32_t msgIDMask, uint32_t flags, uint16_t msgLen); //***************************************************************************** // //! Sends a Message Object //! //! \param base is the base address of the CAN controller. //! \param objID is the object number to configure (1-32). //! \param msgLen is the number of bytes of data in the message object (0-15) //! \param msgData is a pointer to the message object's data //! //! This function is used to transmit a message object and the message data, //! if applicable. //! //! \note The message object requested by the \e objID must first be setup //! using the CAN_setupMessageObject() function. //! //! \return None. // //***************************************************************************** extern void CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, const uint16_t *msgData); //***************************************************************************** // //! Reads the data in a Message Object //! //! \param base is the base address of the CAN controller. //! \param objID is the object number to read (1-32). //! \param msgData is a pointer to the array to store the message data //! //! This function is used to read the data contents of the specified message //! object in the CAN controller. The data returned is stored in the //! \e msgData parameter. //! //! \note The message object requested by the \e objID must first be setup //! using the CAN_setupMessageObject() function. //! //! \note If the DLC of the received message is larger than the \e msgData //! buffer provided, then it is possible for a buffer overflow to occur. //! //! \return Returns \b true if new data was retrieved, else returns //! \b false to indicate no new data was retrieved. // //***************************************************************************** extern _Bool CAN_readMessage(uint32_t base, uint32_t objID, uint16_t *msgData); //***************************************************************************** // //! Clears a message object so that it is no longer used. //! //! \param base is the base address of the CAN controller. //! \param objID is the message object number to disable (1-32). //! //! This function frees the specified message object from use. Once a message //! object has been cleared, it will no longer automatically send or //! receive messages, or generate interrupts. //! //! \return None. // //***************************************************************************** extern void CAN_clearMessage(uint32_t base, uint32_t objID); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** //***************************************************************************** // //! \addtogroup stl_can_test //! @{ // //***************************************************************************** // // Defines // // // Typedefs // //! \brief Defines CAN Loopback Modes //! typedef enum { LOOPBACK_NONE, //!< No CAN Loopback LOOPBACK_INTERNAL, //!< CAN Loopback Internal LOOPBACK_EXTERNAL //!< CAN Loopback External } STL_CAN_Loopback; //! \brief Defines the CAN master configuration object //! typedef struct { uint32_t canBase; //!< CAN port base address uint32_t clockFrequency; //!< CAN and SYSCLK frequency in Hz uint32_t canBitRate; //!< CAN bit rate in Hz STL_CAN_Loopback loopback; //!< Loopback enable or disable } STL_CAN_ConfigObj; //! \brief Defines the CAN configuration handle //! typedef STL_CAN_ConfigObj * STL_CAN_ConfigHandle; //! \brief Defines the CAN transmit object //! typedef struct { uint32_t canBase; //!< CAN port base address uint32_t delayCount; //!< Delay for the loopback mode uint64_t *pTestData; //!< Pointer to 64-bit data array uint16_t testDataSize; //!< Test data size uint16_t msgIDOffset; //!< Offset for TX Message ID (Always initialize to zero) uint32_t crc32; //!< CRC } STL_CAN_TxObj; //! \brief Defines the CAN transmit handle //! typedef STL_CAN_TxObj * STL_CAN_TxHandle; //! \brief Defines the CAN receive object //! typedef struct { uint32_t canBase; //!< CAN port base address uint32_t delayCount; //!< Delay for the loopback mode uint64_t *pTestData; //!< Pointer to 64-bit data array uint16_t testDataSize; //!< Test data size } STL_CAN_RxObj; //! \brief Defines the CAN receive handle //! typedef STL_CAN_RxObj * STL_CAN_RxHandle; //***************************************************************************** // // STL_CAN_setupMessageObject(uint32_t base, uint32_t objID, // uint32_t msgID, CAN_MsgFrameType frame, // CAN_MsgObjType msgType, uint32_t msgIDMask, // uint32_t flags, uint16_t msgLen, // uint32_t delayCount) // //***************************************************************************** extern void STL_CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, CAN_MsgFrameType frame, CAN_MsgObjType msgType, uint32_t msgIDMask, uint32_t flags, uint16_t msgLen, uint32_t delayCount); //***************************************************************************** // //! \brief Configures the CAN in master mode. //! //! \param canMasterConfigHandle is a pointer to the CAN master configuration //! object. //! //! This functions configures the CAN port under test as a master which will //! send data. //! The function takes a handle to \b STL_CAN_MasterConfigHandle object as //! its parameter. The \b canBase parameter determines the CAN port to be //! configured. The values of \b canBitRateDivider correspond to the value of //! CANBRR. The object member \b loopback allows the internal digital loopback //! to be enabled if desired. //! The function uses the following settings for the CAN. //! - 16 data bits //! - master mode //! //! The user must preserve and restore the registers modified by this function. //! The following registers are modified by the function. //! - CANFFTX //! - CANFFRX //! - CANFFCT //! - CANBRR //! - CANPRI //! - CANCTL //! - CANCCR //! //! \return None. // //***************************************************************************** extern void STL_CAN_config(STL_CAN_ConfigHandle canConfigHandle); //***************************************************************************** // //! \brief Configures the CAN in slave mode. //! //! \param canBase is a valid CAN module base address. //! //! This functions configures the CAN port under test as a slave which will //! receive data. //! The function takes a handle to \b canBase as its parameter. The \b canBase //! parameter determines the CAN port to be configured. //! The function uses the following settings for the CAN. //! - 16 data bits //! - slave mode //! //! The user must preserve and restore the registers modified by this function. //! The following registers are modified by the function. //! - CANFFTX //! - CANFFRX //! - CANFFCT //! - CANBRR //! - CANPRI //! - CANCTL //! - CANCCR //! //! \return None. // //***************************************************************************** extern void STL_CAN_configTxMsgObj(STL_CAN_TxHandle handle); extern void STL_CAN_configRxMsgObj(STL_CAN_RxHandle handle); //***************************************************************************** // //! \brief Tests functionality of CAN tranmit. //! //! \param canTxHandle is a pointer to the CAN transmit test object. //! //! This functions should be called after configuring the CAN port under //! test with STL_CAN_configMaster(). //! //! This function will transmit data via the transmit FIFO and then transmit a //! CRC32 of that data. This function could be used with STL_CAN_rx() to //! test the functionality of the transmitter and receiver of the CAN port. //! //! The function takes a \b STL_CAN_TxHandle as its parameter. The \b canBase //! member determines the CAN port to be tested. The \b delayCount member is //! a value to be used to invoke a time-out of a blocking write to the //! transmit FIFO. The \b pTestData is a pointer to 16-bit data and //! \b testDataSize is the number of elements to transmit. Upon completion of //! transmitting the input data, this function will send the \b crc32. //! //! The user must preserve and restore the registers modified by this function. //! The following registers are modified by the function. //! - CANFFTX //! - CANTXBUF //! //! \return If the transmittion did not time out then the function returns //! \b STL_CAN_PASS. Otherwise, it returns \b STL_CAN_FAIL_TX_TO. // //***************************************************************************** extern uint32_t STL_CAN_Tx(STL_CAN_TxHandle canTxhandle); //***************************************************************************** // //! \brief Tests functionality of CAN receive. //! //! \param canRxHandle is a pointer to the CAN receive test object. //! //! This functions should be called after configuring the CAN port under //! test with either STL_CAN_configMaster() or STL_CAN_configSlave(). //! //! This function will receive data via the receive FIFO, calculate a CRC32 on //! the data, and then receive a CRC32. This function could be used with //! STL_CAN_tx() to test the functionality of the transmitter and receiver //! of the CAN port. //! //! The function takes a STL_CAN_RxHandle as its parameter. The \b sciBase //! member determines the CAN port to be tested. The \b delayCount member is //! a value to be used to invoke a time-out of a blocking read of the receive //! FIFO. The \b pTestData is a pointer to buffer of \b testDataSize length. //! This function will write to that buffer in order to store the received data //! and calculate a CRC32 on that data. Upon completion of receiving the input //! data and the CRC32, this function will compare the calculated CRC32 with //! the received CRC32 and return. //! //! The user must preserve and restore the registers modified by this function. //! The following registers are modified by the function. //! - CANFFRX //! - CANRXBUF //! //! \return If the receive did nt time out and the CRC32 of the received data //! matcehs the received CRC32 the function returns \b STL_CAN_PASS. //! Otherwise, it returns \b STL_CAN_FAIL_RX_TO on a time out and //! \b STL_CAN_FAIL_RX_CRC on a CRC mismatch.. // //***************************************************************************** extern uint16_t STL_CAN_Rx(STL_CAN_RxHandle canRxhandle); //***************************************************************************** // //! \brief Resets the CAN. //! //! \param canBase is a valid CAN module base address. //! //! This functions resets the CAN port under test. //! The \b canBase parameter determines the CAN port to be reset. //! //! The user must preserve and restore the registers modified by this function. //! The following registers are modified by the function. //! - CANFFTX //! - CANFFRX //! - CANFFCT //! - CANBRR //! - CANPRI //! - CANCTL //! - CANCCR //! //! \return None. // //***************************************************************************** extern void STL_CAN_reset(const uint32_t canBase); //***************************************************************************** // // Close the Doxygen group. //! @} // //***************************************************************************** //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** // // End of File // //***************************************************************************** // // STL_CAN_setupMessageObject(uint32_t base, uint32_t objID, // uint32_t msgID, CAN_MsgFrameType frame, // CAN_MsgObjType msgType, uint32_t msgIDMask, // uint32_t flags, uint16_t msgLen, // uint32_t delayCount) // //***************************************************************************** void STL_CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, CAN_MsgFrameType frame, CAN_MsgObjType msgType, uint32_t msgIDMask, uint32_t flags, uint16_t msgLen, uint32_t delayCount) { /*LDRA_INSPECTED 8 D 0 MR:R.2.2 Comment_8D*/ uint32_t cmdMaskReg = 0U; uint32_t maskReg = 0U; uint32_t arbReg = 0U; uint32_t msgCtrl = 0U; // // Check the arguments. // do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 43); } } while(0); do { if(!((objID <= 32U) && (objID > 0U))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 44); } } while(0); do { if(!(msgLen <= 8U)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 45); } } while(0); // // Wait for busy bit to clear // /*LDRA_INSPECTED 87 S MR:R.18.4 "LDRA Tool Issue, no actual pointer arithmetic in code"*/ while((((*((volatile uint16_t *)(base + 0x100U))) & 0x8000U) == 0x8000U) && (delayCount != 0U)) { delayCount = delayCount - 1; } switch(msgType) { // // Transmit message object. // case CAN_MSG_OBJ_TYPE_TX: { // // Set message direction to transmit. // arbReg = 0x20000000U; break; } // // Remote frame receive remote, with auto-transmit message object. // case CAN_MSG_OBJ_TYPE_RXTX_REMOTE: { // // Set message direction to Tx for remote receivers. // arbReg = 0x20000000U; // // Set this object to auto answer if a matching identifier is seen. // msgCtrl = (uint32_t)((uint32_t)0x200U | (uint32_t)0x1000U); break; } // // Transmit remote request message object (CAN_MSG_OBJ_TYPE_TX_REMOTE) // or Receive message object (CAN_MSG_OBJ_TYPE_RX). // default: { // // Set message direction to read. // arbReg = 0U; break; } } // // Set values based on Extended Frame or Standard Frame // if(frame == CAN_MSG_FRAME_EXT) { // // Configure the Mask Registers for 29 bit Identifier mask. // if((flags & (0x00000001U)) == (0x00000001U)) { maskReg = msgIDMask & 0x1FFFFFFFU; } // // Set the 29 bit version of the Identifier for this message // object. Mark the message as valid and set the extended ID bit. // arbReg |= (msgID & 0x1FFFFFFFU) | 0x80000000U | 0x40000000U; } else { // // Configure the Mask Registers for 11 bit Identifier mask. // if((flags & (0x00000001U)) == (0x00000001U)) { maskReg = ((msgIDMask << (18U)) & (0x1FFC0000U)); } // // Set the 11 bit version of the Identifier for this message // object. The lower 18 bits are set to zero. Mark the message as // valid. // arbReg |= ((msgID << (18U)) & (0x1FFC0000U)) | 0x80000000U; } // // If the caller wants to filter on the extended ID bit then set it. // maskReg |= (flags & 0x80000000U); // // The caller wants to filter on the message direction field. // maskReg |= (flags & 0x40000000U); // // If any filtering is requested, set the UMASK bit to use mask register // if(((flags & (0x00000001U)) | (flags & 0x40000000U) | (flags & 0x80000000U)) != 0U) { msgCtrl |= 0x1000U; } // // Set the data length since this is set for all transfers. This is // also a single transfer and not a FIFO transfer so set EOB bit. // msgCtrl |= ((uint32_t)msgLen & 0xFU); // // Mark this as the last entry if this is not the last entry in a FIFO. // if((flags & (0x00000002U)) == 0U) { msgCtrl |= 0x80U; } // // Enable transmit interrupts if they should be enabled. // msgCtrl |= (flags & 0x800U); // // Enable receive interrupts if they should be enabled. // msgCtrl |= (flags & 0x400U); // // Set the Control, Arb, and Mask bit so that they get transferred to the // Message object. // cmdMaskReg |= 0x200000U; cmdMaskReg |= 0x100000U; cmdMaskReg |= 0x400000U; cmdMaskReg |= 0x800000U; // // Clear and Write out the registers to program the message object. // __byte_peripheral_32((uint32_t *)(base + 0x100U)) = 0U; __byte_peripheral_32((uint32_t *)(base + 0x104U)) = 0U; __byte_peripheral_32((uint32_t *)(base + 0x108U)) = 0U; __byte_peripheral_32((uint32_t *)(base + 0x10CU)) = 0U; __byte_peripheral_32((uint32_t *)(base + 0x100U)) = cmdMaskReg; __byte_peripheral_32((uint32_t *)(base + 0x104U)) = maskReg; __byte_peripheral_32((uint32_t *)(base + 0x108U)) = arbReg; __byte_peripheral_32((uint32_t *)(base + 0x10CU)) = msgCtrl; // // Transfer data to message object RAM // (*((volatile uint16_t *)(base + 0x100U))) = objID & 0xFFU; } //***************************************************************************** // // STL_CAN_config(STL_CAN_ConfigHandle canConfigHandle) // //***************************************************************************** void STL_CAN_config(STL_CAN_ConfigHandle canConfigHandle) { uint32_t base = canConfigHandle->canBase; do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 225); } } while(0); // // Disable module. // CAN_disableController(base); // // Disable all interrupts. // CAN_disableInterrupt(base, (0x00000008U) | (0x00000004U) | (0x00000002U) | (0x00020000U)); // // Configure the CAN module. // //Can_clearMessage(); CAN_initModule(base); CAN_setBitRate(base, canConfigHandle->clockFrequency, canConfigHandle->canBitRate, 16); if(canConfigHandle->loopback == LOOPBACK_INTERNAL) { // // Enable internal loopback // CAN_enableTestMode(base, 0x10U); } if(canConfigHandle->loopback == LOOPBACK_EXTERNAL) { // // Enable external loopback // CAN_enableTestMode(base, 0x100U); } // // Enable the CAN module. // CAN_startModule(base); } //***************************************************************************** // // STL_CAN_configTxMsgObj(STL_CAN_TxHandle canTxhandle) // //***************************************************************************** void STL_CAN_configTxMsgObj(STL_CAN_TxHandle canTxhandle) { do { if(!(CAN_isBaseValid(canTxhandle ->canBase))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 274); } } while(0); // // Initialize the transmit message object used for sending CAN messages. // Message Object Parameters: // Message Object ID Number: 1 // Message Identifier: 0x100 + requested offset // Message Frame: Standard // Message Type: Transmit // Message ID Mask: 0x0 // Message Object Flags: None // Message Data Length: 8 Bytes // STL_CAN_setupMessageObject(canTxhandle->canBase, 1, (0x100 + canTxhandle->msgIDOffset), CAN_MSG_FRAME_STD, CAN_MSG_OBJ_TYPE_TX, 0, (0x00000000U), 8, canTxhandle->delayCount); } //***************************************************************************** // // STL_CAN_configRxMsgObj(STL_CAN_RxHandle canRxhandle) // //***************************************************************************** void STL_CAN_configRxMsgObj(STL_CAN_RxHandle canRxhandle) { do { if(!(CAN_isBaseValid(canRxhandle ->canBase))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 301); } } while(0); do { if(!(canRxhandle ->testDataSize <= 30)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 303); } } while(0); // // Setup extra message object for CRC. // // // Initialize the receive message object used for receiving CAN messages. // Message Object Parameters: // Message Object ID Number: 32 // Message Identifier: 0x200 + testDataSize // Message Frame: Standard // Message Type: Receive // Message ID Mask: 0x0 // Message Object Flags: None // Message Data Length: 2 Bytes // STL_CAN_setupMessageObject(canRxhandle->canBase, 32, (0x200 + canRxhandle->testDataSize), CAN_MSG_FRAME_STD, CAN_MSG_OBJ_TYPE_RX, 0, (0x00000000U), 4, canRxhandle->delayCount); // // Set up message objects for data. // uint16_t i; for(i = 0; i < canRxhandle->testDataSize; i++) { // // Initialize the receive message object used for receiving CAN messages. // Message Object Parameters: // Message Object ID Number: 2 to 31 // Message Identifier: 0x100 + testDataSize offset // Message Frame: Standard // Message Type: Receive // Message ID Mask: 0x0 // Message Object Flags: None // Message Data Length: 8 Bytes // STL_CAN_setupMessageObject(canRxhandle->canBase, i + 2, (0x100 + i), CAN_MSG_FRAME_STD, CAN_MSG_OBJ_TYPE_RX, 0, (0x00000000U), 8, canRxhandle->delayCount); } } //***************************************************************************** // // STL_CAN_Tx(STL_CAN_TxHandle canTxhandle) // //***************************************************************************** uint32_t STL_CAN_Tx(STL_CAN_TxHandle canTxhandle) { /*LDRA_INSPECTED 7 C MR:R.15.5 Comment_7C*/ uint16_t i; uint64_t dataValue; uint32_t delay; uint32_t base = canTxhandle->canBase; do { if(!(CAN_isBaseValid(base))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 365); } } while(0); do { if(!(canTxhandle ->testDataSize <= 30)) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 366); } } while(0); for(i = 0U; i < canTxhandle->testDataSize; i++) { delay = canTxhandle->delayCount; // // Setup Destination Msg ID // canTxhandle->msgIDOffset = i; STL_CAN_configTxMsgObj(canTxhandle); // // Get the data value at the index. // dataValue = canTxhandle->pTestData[i]; // // Set up the request for data from the message object. // __byte_peripheral_32((uint32_t *)(base + 0x100U)) = 0x100000U; // // Transfer the TX message object to the IF register. // (*((volatile uint16_t *)(base + 0x100U))) = 1; // // Wait for busy bit to clear // while((((*((volatile uint16_t *)(base + 0x100U))) & 0x8000U) == 0x8000U) && (delay != 0U)) { delay = delay - 1; } // // If CAN Tx timed out, then return. // if(delay == 0U) { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_TX_TO); return(1U); } // // Write the data out to the CAN Data registers. // __byte_peripheral_32((uint32_t *)(base + 0x110U)) = (uint32_t)dataValue; __byte_peripheral_32((uint32_t *)(base + 0x114U)) = (uint32_t)(dataValue >> 32UL); // // Set Direction to write // __byte_peripheral_32((uint32_t *)(base + 0x100U)) = 0x800000U | 0x10000U | 0x20000U; // // Set Tx Request Bit // __byte_peripheral_32((uint32_t *)(base + 0x100U)) |= 0x40000U; // // Transfer the TX message object to the message object // (*((volatile uint16_t *)(base + 0x100U))) = 1; // // Wait for message to be sent // delay = canTxhandle->delayCount; while(((CAN_getTxRequests(base) & 0x1) == 0x1) && (delay != 0U)) { delay = delay - 1; } } // // Send 32-bit CRC // delay = canTxhandle->delayCount; // // Setup TX Msg for CRC // STL_CAN_setupMessageObject(base, 1, (0x200 + canTxhandle->testDataSize), CAN_MSG_FRAME_STD, CAN_MSG_OBJ_TYPE_TX, 0, (0x00000000U), 4, canTxhandle->delayCount); // // Set up the request for data from the message object. // __byte_peripheral_32((uint32_t *)(base + 0x100U)) = 0x100000U; // // Transfer the message object to the IF register. // (*((volatile uint16_t *)(base + 0x100U))) = 1; // // Wait for busy bit to clear // while((((*((volatile uint16_t *)(base + 0x100U))) & 0x8000U) == 0x8000U) && (delay != 0U)) { delay = delay - 1; } // // If CAN Tx timed out, then return. // if(delay == 0U) { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_TX_TO); return(1U); } // // Write the data out to the CAN Data registers. // __byte_peripheral_32((uint32_t *)(base + 0x110U)) = canTxhandle->crc32; // // Set Direction to write // __byte_peripheral_32((uint32_t *)(base + 0x100U)) = 0x800000U | 0x20000U; // // Set Tx Request Bit // __byte_peripheral_32((uint32_t *)(base + 0x100U)) |= 0x40000U; // // Transfer the message object to the message object // (*((volatile uint16_t *)(base + 0x100U))) = 1; // // Wait for message to be sent // delay = canTxhandle->delayCount; while(((CAN_getTxRequests(base) & 0x1) == 0x1) && (delay != 0U)) { delay = delay - 1; } return(0U); } //***************************************************************************** // // STL_CAN_rx(STL_CAN_RxHandle canRxHandle) // //***************************************************************************** uint16_t STL_CAN_Rx(STL_CAN_RxHandle canRxhandle) { uint32_t rxCRC = 0U; uint32_t msgCtrl = 0U; uint32_t delay = 0U; STL_CRC_Obj crcObj; uint32_t base = canRxhandle->canBase; uint16_t testStatus; // // Receive the Data from the RXFIFO // uint16_t i; for(i = 0U; i < canRxhandle->testDataSize; i++) { delay = canRxhandle->delayCount; // // Set the Message Data A, Data B, and control values to be read // on request for data from the message object. // __byte_peripheral_32((uint32_t *)(base + 0x120U)) = (0x20000U | 0x10000U | 0x100000U); // // Transfer the message object to the message object IF register. // (*((volatile uint16_t *)(base + 0x120U))) = (i + 2) & 0xFFU; // // Wait for busy bit to clear // while((((*((volatile uint16_t *)(base + 0x120U))) & 0x8000U) == 0x8000U) && (delay != 0)) { delay = delay - 1; } if(delay == 0U) { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_RX_TO); return(2U); } // // Read out the IF control Register. // msgCtrl = (*((volatile uint16_t *)(base + 0x12CU))); // // See if there is new data available. // if((msgCtrl & 0x8000U) == 0x8000U) { // // Read out the data from the CAN registers. // (canRxhandle->pTestData)[i] = ((uint64_t)__byte_peripheral_32((uint32_t *)(base + 0x134U)) << 32) | (uint64_t)__byte_peripheral_32((uint32_t *)(base + 0x130U)); } else { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_RX_TO); return(2U); } } // // Receive CRC // delay = canRxhandle->delayCount; // // Set the Message Data A and control values to be read // on request for data from the message object. // __byte_peripheral_32((uint32_t *)(base + 0x120U)) = (0x20000U | 0x100000U); // // Transfer the message object to the message object IF register. // (*((volatile uint16_t *)(base + 0x120U))) = 32; // // Wait for busy bit to clear // while((((*((volatile uint16_t *)(base + 0x120U))) & 0x8000U) == 0x8000U) && (delay != 0)) { delay = delay - 1; } if(delay == 0U) { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_RX_TO); return(2U); } // // Read out the IF control Register. // msgCtrl = (*((volatile uint16_t *)(base + 0x12CU))); // // See if there is new data available. // if((msgCtrl & 0x8000U) == 0x8000U) { // // Read out the data from the CAN registers. // rxCRC = (*((volatile uint16_t *)(base + 0x130U))); } else { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_RX_TO); return(2U); } // // Calculate the CRC of the received data using the VCU. // // // Step 1: Initialize the CRC object. // CRC number of bytes is twice the testDataSize because it is 16-bit // transfers. // /*LDRA_INSPECTED 105 D MR:R.2.2 Comment_105D*/ crcObj.seedValue = 0x0UL; /*LDRA_INSPECTED 105 D MR:R.2.2 Comment_105D*/ crcObj.nMsgBytes = canRxhandle->testDataSize * 8U; /*LDRA_INSPECTED 105 D MR:R.2.2 Comment_105D*/ crcObj.parity = STL_CRC_PARITY_EVEN; crcObj.crcResult = 0U; /*LDRA_INSPECTED 105 D MR:R.2.2 Comment_105D*/ crcObj.pMsgBuffer = canRxhandle->pTestData; // // Step 2: Run the 32-bit CRC on the received data. // STL_CRC_reset(); STL_CRC_init32Bit(&crcObj); STL_CRC_run32BitPoly1(&crcObj); // // Compare received CRC and computed CRC. // if( rxCRC != crcObj.crcResult ) { // // Report global error. // STL_Util_setErrorFlag(STL_UTIL_CAN_RX_CRC); testStatus = 3U; } else { testStatus = 0U; } testStatus = 0U; return(testStatus); } //***************************************************************************** // // STL_CAN_reset(const uint32_t canBase) // //***************************************************************************** void STL_CAN_reset(const uint32_t canBase) { do { if(!(CAN_isBaseValid(canBase))) { __error__("C:/ti/c2000/C2000Ware_0_04_00_06/libraries/soprano_60730_class_c/f2837xd/source/stl_can.c", 704); } } while(0); // // Disable loopback. // //CAN_disableLoopback(canBase); // // Reset the CAN // //CAN_disableModule(canBase); } // // End of File //