/** @file sys_startup.c * @brief Startup Source File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Include Files * - Type Definitions * - External Functions * - VIM RAM Setup * - Startup Routine * . * which are relevant for the Startup. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Include Files */ /** @file sys_common.h * @brief Common Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - General Definitions * . * which are relevant for all drivers. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file hal_stdtypes.h * @brief HALCoGen standard types header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Type and Global definitions which are relevant for all drivers. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /*****************************************************************************/ /* STDINT.H */ /* */ /* Copyright (c) 2002 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* _STDINT40.H */ /* */ /* Copyright (c) 2018 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1991, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Berkeley Software Design, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 * $FreeBSD$ */ #pragma diag_push #pragma CHECK_MISRA("none") /* * Testing against Clang-specific extensions. */ /* * This code has been put in place to help reduce the addition of * compiler specific defines in FreeBSD code. It helps to aid in * having a compiler-agnostic source tree. */ /* * Macro to test if we're using a specific version of gcc or later. */ /* * The __CONCAT macro is used to concatenate parts of symbol names, e.g. * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI * mode -- there must be no spaces between its arguments, and for nested * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also * concatenate double-quoted strings produced by the __STRING macro, but * this only works with ANSI C. * * __XSTRING is like __STRING, but it expands any macros in its argument * first. It is only available with ANSI C. */ /* * Compiler-dependent macros to help declare dead (non-returning) and * pure (no side effects) functions, and unused variables. They are * null except for versions of gcc that are known to support the features * properly (old versions of gcc-2 supported the dead and pure features * in a different (wrong) way). If we do not provide an implementation * for a given compiler, let the compile fail if it is told to use * a feature that we cannot live without. */ /* * TI ADD - check that __GNUC__ is defined before referencing it to avoid * generating an error when __GNUC__ treated as zero warning is * promoted to an error via -pdse195 option. */ /* * Keywords added in C11. */ /* * Emulation of C11 _Generic(). Unlike the previously defined C11 * keywords, it is not possible to implement this using exactly the same * syntax. Therefore implement something similar under the name * __generic(). Unlike _Generic(), this macro can only distinguish * between a single type, so it requires nested invocations to * distinguish multiple cases. */ /* * C99 Static array indices in function parameter declarations. Syntax such as: * void bar(int myArray[static 10]); * is allowed in C99 but not in C++. Define __min_size appropriately so * headers using it can be compiled in either language. Use like this: * void bar(int myArray[__min_size(10)]); */ /* XXX: should use `#if __STDC_VERSION__ < 199901'. */ /* C++11 exposes a load of C99 stuff */ /* * GCC 2.95 provides `__restrict' as an extension to C90 to support the * C99-specific `restrict' type qualifier. We happen to use `__restrict' as * a way to define the `restrict' type qualifier without disturbing older * software that is unaware of C99 keywords. * The TI compiler supports __restrict in all compilation modes. */ /* * GNU C version 2.96 adds explicit branch prediction so that * the CPU back-end can hint the processor and also so that * code blocks can be reordered such that the predicted path * sees a more linear flow, thus improving cache behavior, etc. * * The following two macros provide us with a way to utilize this * compiler feature. Use __predict_true() if you expect the expression * to evaluate to true, and __predict_false() if you expect the * expression to evaluate to false. * * A few notes about usage: * * * Generally, __predict_false() error condition checks (unless * you have some _strong_ reason to do otherwise, in which case * document it), and/or __predict_true() `no-error' condition * checks, assuming you want to optimize for the no-error case. * * * Other than that, if you don't know the likelihood of a test * succeeding from empirical or other `hard' evidence, don't * make predictions. * * * These are meant to be used in places that are run `a lot'. * It is wasteful to make predictions in code that is run * seldomly (e.g. at subsystem initialization time) as the * basic block reordering that this affects can often generate * larger code. */ /* * We define this here since , , and * require it. */ /* * Given the pointer x to the member m of the struct s, return * a pointer to the containing structure. When using GCC, we first * assign pointer x to a local variable, to check that its type is * compatible with member m. */ /* * Compiler-dependent macros to declare that functions take printf-like * or scanf-like arguments. They are null except for versions of gcc * that are known to support the features properly (old versions of gcc-2 * didn't permit keeping the keywords out of the application namespace). */ /* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ /* * The following definition might not work well if used in header files, * but it should be better than nothing. If you want a "do nothing" * version, then it should generate some harmless declaration, such as: * #define __IDSTRING(name,string) struct __hack */ /* * Embed the rcs id of a source file in the resulting library. Note that in * more recent ELF binutils, we use .ident allowing the ID to be stripped. * Usage: * __FBSDID("$FreeBSD$"); */ /*- * The following definitions are an extension of the behavior originally * implemented in , but with a different level of granularity. * POSIX.1 requires that the macros we test be defined before any standard * header file is included. * * Here's a quick run-down of the versions: * defined(_POSIX_SOURCE) 1003.1-1988 * _POSIX_C_SOURCE == 1 1003.1-1990 * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option * _POSIX_C_SOURCE == 199309 1003.1b-1993 * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, * and the omnibus ISO/IEC 9945-1: 1996 * _POSIX_C_SOURCE == 200112 1003.1-2001 * _POSIX_C_SOURCE == 200809 1003.1-2008 * * In addition, the X/Open Portability Guide, which is now the Single UNIX * Specification, defines a feature-test macro which indicates the version of * that specification, and which subsumes _POSIX_C_SOURCE. * * Our macros begin with two underscores to avoid namespace screwage. */ /* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ /* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ /* Deal with various X/Open Portability Guides and Single UNIX Spec. */ /* * Deal with all versions of POSIX. The ordering relative to the tests above is * important. */ /*- * Deal with _ANSI_SOURCE: * If it is defined, and no other compilation environment is explicitly * requested, then define our internal feature-test macros to zero. This * makes no difference to the preprocessor (undefined symbols in preprocessing * expressions are defined to have value zero), but makes it more convenient for * a test program to print out the values. * * If a program mistakenly defines _ANSI_SOURCE and some other macro such as * _POSIX_C_SOURCE, we will assume that it wants the broader compilation * environment (and in fact we will never get here). */ /* User override __EXT1_VISIBLE */ /* * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h * translates them to __ARM_ARCH and the modern feature symbols defined by ARM. */ /* * Nullability qualifiers: currently only supported by Clang. */ /* * Type Safety Checking * * Clang provides additional attributes to enable checking type safety * properties that cannot be enforced by the C type system. */ /* * Lock annotations. * * Clang provides support for doing basic thread-safety tests at * compile-time, by marking which locks will/should be held when * entering/leaving a functions. * * Furthermore, it is also possible to annotate variables and structure * members to enforce that they are only accessed when certain locks are * held. */ /* Structure implements a lock. */ /* Function acquires an exclusive or shared lock. */ /* Function attempts to acquire an exclusive or shared lock. */ /* Function releases a lock. */ /* Function asserts that an exclusive or shared lock is held. */ /* Function requires that an exclusive or shared lock is or is not held. */ /* Function should not be analyzed. */ /* Guard variables and structure members by lock. */ #pragma diag_pop /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2002 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 2002 Mike Barcroft * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 * From: @(#)types.h 8.3 (Berkeley) 1/5/94 * $FreeBSD$ */ #pragma diag_push /* This file is required to use base types */ #pragma CHECK_MISRA("-6.3") /* * Basic types upon which most other types are built. */ typedef signed char __int8_t; typedef unsigned char __uint8_t; typedef short __int16_t; typedef unsigned short __uint16_t; typedef int __int32_t; typedef unsigned int __uint32_t; /* LONGLONG */ typedef long long __int64_t; /* LONGLONG */ typedef unsigned long long __uint64_t; /* * Standard type definitions. */ typedef __uint32_t __clock_t; /* clock()... */ typedef __int32_t __critical_t; typedef double __double_t; typedef float __float_t; typedef __int32_t __intfptr_t; typedef __int64_t __intmax_t; typedef __int32_t __intptr_t; typedef __int32_t __int_fast8_t; typedef __int32_t __int_fast16_t; typedef __int32_t __int_fast32_t; typedef __int64_t __int_fast64_t; typedef __int8_t __int_least8_t; typedef __int16_t __int_least16_t; typedef __int32_t __int_least32_t; typedef __int64_t __int_least64_t; typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ typedef __int32_t __register_t; typedef __int32_t __segsz_t; /* segment size (in pages) */ typedef __uint32_t __size_t; /* sizeof() */ typedef __int32_t __ssize_t; /* byte count or error */ typedef __uint32_t __time_t; typedef __uint32_t __uintfptr_t; typedef __uint64_t __uintmax_t; typedef __uint32_t __uintptr_t; typedef __uint32_t __uint_fast8_t; typedef __uint32_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; typedef __uint64_t __uint_fast64_t; typedef __uint8_t __uint_least8_t; typedef __uint16_t __uint_least16_t; typedef __uint32_t __uint_least32_t; typedef __uint64_t __uint_least64_t; typedef __uint32_t __u_register_t; typedef __uint32_t __vm_offset_t; typedef __uint32_t __vm_paddr_t; typedef __uint32_t __vm_size_t; typedef unsigned short ___wchar_t; /* * Unusual type definitions. */ typedef struct __va_list_t { void * __ap; } __va_list; #pragma diag_pop #pragma diag_push /* This file is required to use types without size and signedness */ #pragma CHECK_MISRA("-6.3") /* * Standard type definitions. */ typedef __int32_t __blksize_t; /* file block size */ typedef __int64_t __blkcnt_t; /* file block count */ typedef __int32_t __clockid_t; /* clock_gettime()... */ typedef __uint32_t __fflags_t; /* file flags */ typedef __uint64_t __fsblkcnt_t; typedef __uint64_t __fsfilcnt_t; typedef __uint32_t __gid_t; typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ typedef __uint64_t __ino_t; /* inode number */ typedef long __key_t; /* IPC key (for Sys V IPC) */ typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ typedef __uint16_t __mode_t; /* permissions */ typedef int __accmode_t; /* access permissions */ typedef int __nl_item; typedef __uint64_t __nlink_t; /* link count */ typedef __int64_t __off_t; /* file offset */ typedef __int64_t __off64_t; /* file offset (alias) */ typedef __int32_t __pid_t; /* process [group] */ typedef __int64_t __rlim_t; /* resource limit - intentionally */ /* signed, because of legacy code */ /* that uses -1 for RLIM_INFINITY */ typedef __uint8_t __sa_family_t; typedef __uint32_t __socklen_t; typedef long __suseconds_t; /* microseconds (signed) */ typedef struct __timer *__timer_t; /* timer_gettime()... */ typedef struct __mq *__mqd_t; /* mq_open()... */ typedef __uint32_t __uid_t; typedef unsigned int __useconds_t; /* microseconds (unsigned) */ typedef int __cpuwhich_t; /* which parameter for cpuset. */ typedef int __cpulevel_t; /* level parameter for cpuset. */ typedef int __cpusetid_t; /* cpuset identifier. */ /* * Unusual type definitions. */ /* * rune_t is declared to be an ``int'' instead of the more natural * ``unsigned long'' or ``long''. Two things are happening here. It is not * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, * it looks like 10646 will be a 31 bit standard. This means that if your * ints cannot hold 32 bits, you will be in trouble. The reason an int was * chosen over a long is that the is*() and to*() routines take ints (says * ANSI C), but they use __ct_rune_t instead of int. * * NOTE: rune_t is not covered by ANSI nor other standards, and should not * be instantiated outside of lib/libc/locale. Use wchar_t. wint_t and * rune_t must be the same type. Also, wint_t should be able to hold all * members of the largest character set plus one extra value (WEOF), and * must be at least 16 bits. */ typedef int __ct_rune_t; /* arg type for ctype funcs */ typedef __ct_rune_t __rune_t; /* rune_t (see above) */ typedef __ct_rune_t __wint_t; /* wint_t (see above) */ /* Clang already provides these types as built-ins, but only in C++ mode. */ typedef __uint_least16_t __char16_t; typedef __uint_least32_t __char32_t; /* In C++11, char16_t and char32_t are built-in types. */ typedef struct { long long __max_align1 __attribute__((aligned(_Alignof(long long)))); long double __max_align2 __attribute__((aligned(_Alignof(long double)))); } __max_align_t; typedef __uint64_t __dev_t; /* device number */ typedef __uint32_t __fixpt_t; /* fixed point number */ /* * mbstate_t is an opaque object to keep conversion state during multibyte * stream conversions. */ typedef int _Mbstatet; typedef _Mbstatet __mbstate_t; typedef __uintmax_t __rman_res_t; /* * When the following macro is defined, the system uses 64-bit inode numbers. * Programs can use this to avoid including , with its associated * namespace pollution. */ #pragma diag_pop /*- * SPDX-License-Identifier: BSD-2-Clause-NetBSD * * Copyright (c) 2001, 2002 Mike Barcroft * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #pragma diag_push /* 19.4 is issued for macros that are defined in terms of other macros. */ #pragma CHECK_MISRA("-19.4") /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types */ /* Minimum values of exact-width signed integer types. */ /* Maximum values of exact-width signed integer types. */ /* Maximum values of exact-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.2 Limits of minimum-width integer types */ /* Minimum values of minimum-width signed integer types. */ /* Maximum values of minimum-width signed integer types. */ /* Maximum values of minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.3 Limits of fastest minimum-width integer types */ /* Minimum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.4 Limits of integer types capable of holding object pointers */ /* * ISO/IEC 9899:1999 * 7.18.2.5 Limits of greatest-width integer types */ /* * ISO/IEC 9899:1999 * 7.18.3 Limits of other integer types */ /* Limits of ptrdiff_t. */ /* Limits of sig_atomic_t. */ /* Limit of size_t. */ /* Limits of wint_t. */ #pragma diag_pop /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 David E. O'Brien * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ typedef __int8_t int8_t; typedef __int16_t int16_t; typedef __int32_t int32_t; typedef __int64_t int64_t; typedef __uint8_t uint8_t; typedef __uint16_t uint16_t; typedef __uint32_t uint32_t; typedef __uint64_t uint64_t; typedef __intptr_t intptr_t; typedef __uintptr_t uintptr_t; typedef __intmax_t intmax_t; typedef __uintmax_t uintmax_t; typedef __int_least8_t int_least8_t; typedef __int_least16_t int_least16_t; typedef __int_least32_t int_least32_t; typedef __int_least64_t int_least64_t; typedef __uint_least8_t uint_least8_t; typedef __uint_least16_t uint_least16_t; typedef __uint_least32_t uint_least32_t; typedef __uint_least64_t uint_least64_t; typedef __int_fast8_t int_fast8_t; typedef __int_fast16_t int_fast16_t; typedef __int_fast32_t int_fast32_t; typedef __int_fast64_t int_fast64_t; typedef __uint_fast8_t uint_fast8_t; typedef __uint_fast16_t uint_fast16_t; typedef __uint_fast32_t uint_fast32_t; typedef __uint_fast64_t uint_fast64_t; /* GNU and Darwin define this and people seem to think it's portable */ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* Limits of wchar_t. */ #pragma diag_pop /* ISO/IEC 9899:2011 K.3.4.4 */ /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /************************************************************/ /* Type Definitions */ /************************************************************/ typedef uint64_t uint64; typedef uint32_t uint32; typedef uint16_t uint16; typedef uint8_t uint8; typedef _Bool boolean; typedef int64_t sint64; typedef int32_t sint32; typedef int16_t sint16; typedef int8_t sint8; typedef float float32; typedef double float64; typedef uint8 Std_ReturnType; typedef struct { uint16 vendorID; uint16 moduleID; uint8 instanceID; uint8 sw_major_version; uint8 sw_minor_version; uint8 sw_patch_version; } Std_VersionInfoType; /*****************************************************************************/ /* SYMBOL DEFINITIONS */ /*****************************************************************************/ typedef unsigned char StatusType; /************************************************************/ /* Global Definitions */ /************************************************************/ /** @def NULL * @brief NULL definition */ /*SAFETYMCUSW 218 S MR:20.2 "Custom Type Definition." */ /*****************************************************************************/ /* Define: NULL_PTR */ /* Description: Void pointer to 0 */ /*****************************************************************************/ /** @def TRUE * @brief definition for TRUE */ /** @def FALSE * @brief BOOLEAN definition for FALSE */ /*****************************************************************************/ /* Define: NULL_PTR */ /* Description: Void pointer to 0 */ /*****************************************************************************/ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /************************************************************/ /* Type Definitions */ /************************************************************/ typedef boolean tBoolean; /** @enum loopBackType * @brief Loopback type definition */ /** @typedef loopBackType_t * @brief Loopback type Type Definition * * This type is used to select the module Loopback type Digital or Analog loopback. */ typedef enum loopBackType { Digital_Lbk = 0U, Analog_Lbk = 1U }loopBackType_t; /** @enum config_value_type * @brief config type definition */ /** @typedef config_value_type_t * @brief config type Type Definition * * This type is used to specify the Initial and Current value. */ typedef enum config_value_type { InitialValue, CurrentValue }config_value_type_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /********************************************************************************/ /* The ASSERT macro, which does the actual assertion checking. Typically, this */ /* will be for procedure arguments. */ /********************************************************************************/ /* USER CODE BEGIN (2) */ /* USER CODE END */ /* USER CODE BEGIN (3) */ /* USER CODE END */ /** @file system.h * @brief System Driver Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_system.h * @brief System Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_gio.h * @brief GIO Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the GIO driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Gio Register Frame Definition */ /** @struct gioBase * @brief GIO Base Register Definition * * This structure is used to access the GIO module registers. */ /** @typedef gioBASE_t * @brief GIO Register Frame Type Definition * * This type is used to access the GIO Registers. */ typedef volatile struct gioBase { uint32 GCR0; /**< 0x0000: Global Control Register */ uint32 rsvd; /**< 0x0004: Reserved*/ uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/ uint32 POL; /**< 0x000C: Interrupt Polarity Register */ uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */ uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */ uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */ uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */ uint32 FLG; /**< 0x0020: Interrupt Flag Register */ uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */ uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */ uint32 EMU1; /**< 0x002C: Emulation 1 Register */ uint32 EMU2; /**< 0x0030: Emulation 2 Register */ } gioBASE_t; /** @struct gioPort * @brief GIO Port Register Definition */ /** @typedef gioPORT_t * @brief GIO Port Register Type Definition * * This type is used to access the GIO Port Registers. */ typedef volatile struct gioPort { uint32 DIR; /**< 0x0000: Data Direction Register */ uint32 DIN; /**< 0x0004: Data Input Register */ uint32 DOUT; /**< 0x0008: Data Output Register */ uint32 DSET; /**< 0x000C: Data Output Set Register */ uint32 DCLR; /**< 0x0010: Data Output Clear Register */ uint32 PDR; /**< 0x0014: Open Drain Register */ uint32 PULDIS; /**< 0x0018: Pullup Disable Register */ uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */ } gioPORT_t; /** @def gioREG * @brief GIO Register Frame Pointer * * This pointer is used by the GIO driver to access the gio module registers. */ /** @def gioPORTA * @brief GIO Port (A) Register Pointer * * Pointer used by the GIO driver to access PORTA */ /** @def gioPORTB * @brief GIO Port (B) Register Pointer * * Pointer used by the GIO driver to access PORTB */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* System Register Frame 1 Definition */ /** @struct systemBase1 * @brief System Register Frame 1 Definition * * This type is used to access the System 1 Registers. */ /** @typedef systemBASE1_t * @brief System Register Frame 1 Type Definition * * This type is used to access the System 1 Registers. */ typedef volatile struct systemBase1 { uint32 SYSPC1; /* 0x0000 */ uint32 SYSPC2; /* 0x0004 */ uint32 SYSPC3; /* 0x0008 */ uint32 SYSPC4; /* 0x000C */ uint32 SYSPC5; /* 0x0010 */ uint32 SYSPC6; /* 0x0014 */ uint32 SYSPC7; /* 0x0018 */ uint32 SYSPC8; /* 0x001C */ uint32 SYSPC9; /* 0x0020 */ uint32 SSWPLL1; /* 0x0024 */ uint32 SSWPLL2; /* 0x0028 */ uint32 SSWPLL3; /* 0x002C */ uint32 CSDIS; /* 0x0030 */ uint32 CSDISSET; /* 0x0034 */ uint32 CSDISCLR; /* 0x0038 */ uint32 CDDIS; /* 0x003C */ uint32 CDDISSET; /* 0x0040 */ uint32 CDDISCLR; /* 0x0044 */ uint32 GHVSRC; /* 0x0048 */ uint32 VCLKASRC; /* 0x004C */ uint32 RCLKSRC; /* 0x0050 */ uint32 CSVSTAT; /* 0x0054 */ uint32 MSTGCR; /* 0x0058 */ uint32 MINITGCR; /* 0x005C */ uint32 MSINENA; /* 0x0060 */ uint32 MSTFAIL; /* 0x0064 */ uint32 MSTCGSTAT; /* 0x0068 */ uint32 MINISTAT; /* 0x006C */ uint32 PLLCTL1; /* 0x0070 */ uint32 PLLCTL2; /* 0x0074 */ uint32 SYSPC10; /* 0x0078 */ uint32 DIEIDL; /* 0x007C */ uint32 DIEIDH; /* 0x0080 */ uint32 VRCTL; /* 0x0084 */ uint32 LPOMONCTL; /* 0x0088 */ uint32 CLKTEST; /* 0x008C */ uint32 DFTCTRLREG1; /* 0x0090 */ uint32 DFTCTRLREG2; /* 0x0094 */ uint32 rsvd1; /* 0x0098 */ uint32 rsvd2; /* 0x009C */ uint32 GPREG1; /* 0x00A0 */ uint32 BTRMSEL; /* 0x00A4 */ uint32 IMPFASTS; /* 0x00A8 */ uint32 IMPFTADD; /* 0x00AC */ uint32 SSISR1; /* 0x00B0 */ uint32 SSISR2; /* 0x00B4 */ uint32 SSISR3; /* 0x00B8 */ uint32 SSISR4; /* 0x00BC */ uint32 RAMGCR; /* 0x00C0 */ uint32 BMMCR1; /* 0x00C4 */ uint32 BMMCR2; /* 0x00C8 */ uint32 CPURSTCR; /* 0x00CC */ uint32 CLKCNTL; /* 0x00D0 */ uint32 ECPCNTL; /* 0x00D4 */ uint32 DSPGCR; /* 0x00D8 */ uint32 DEVCR1; /* 0x00DC */ uint32 SYSECR; /* 0x00E0 */ uint32 SYSESR; /* 0x00E4 */ uint32 SYSTASR; /* 0x00E8 */ uint32 GBLSTAT; /* 0x00EC */ uint32 DEV; /* 0x00F0 */ uint32 SSIVEC; /* 0x00F4 */ uint32 SSIF; /* 0x00F8 */ } systemBASE1_t; /** @def systemREG1 * @brief System Register Frame 1 Pointer * * This pointer is used by the system driver to access the system frame 1 registers. */ /** @def systemPORT * @brief ECLK GIO Port Register Pointer * * Pointer used by the GIO driver to access I/O PORT of System/Eclk * (use the GIO drivers to access the port pins). */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* System Register Frame 2 Definition */ /** @struct systemBase2 * @brief System Register Frame 2 Definition * * This type is used to access the System 2 Registers. */ /** @typedef systemBASE2_t * @brief System Register Frame 2 Type Definition * * This type is used to access the System 2 Registers. */ typedef volatile struct systemBase2 { uint32 PLLCTL3; /* 0x0000 */ uint32 rsvd1; /* 0x0004 */ uint32 STCCLKDIV; /* 0x0008 */ uint32 rsvd2[6U]; /* 0x000C */ uint32 ECPCNTRL0; /* 0x0024 */ uint32 rsvd3[5U]; /* 0x0028 */ uint32 CLK2CNTL; /* 0x003C */ uint32 VCLKACON1; /* 0x0040 */ uint32 rsvd4[11U]; /* 0x0044 */ uint32 CLKSLIP; /* 0x0070 */ uint32 rsvd5[30U]; /* 0x0074 */ uint32 EFC_CTLEN; /* 0x00EC */ uint32 DIEIDL_REG0; /* 0x00F0 */ uint32 DIEIDH_REG1; /* 0x00F4 */ uint32 DIEIDL_REG2; /* 0x00F8 */ uint32 DIEIDH_REG3; /* 0x00FC */ } systemBASE2_t; /** @def systemREG2 * @brief System Register Frame 2 Pointer * * This pointer is used by the system driver to access the system frame 2 registers. */ /** @file reg_flash.h * @brief Flash Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* Flash Register Frame Definition */ /** @struct flashWBase * @brief Flash Wrapper Register Frame Definition * * This type is used to access the Flash Wrapper Registers. */ /** @typedef flashWBASE_t * @brief Flash Wrapper Register Frame Type Definition * * This type is used to access the Flash Wrapper Registers. */ typedef volatile struct flashWBase { uint32 FRDCNTL; /* 0x0000 */ uint32 rsvd1; /* 0x0004 */ uint32 FEDACCTRL1; /* 0x0008 */ uint32 FEDACCTRL2; /* 0x000C */ uint32 FCORERRCNT; /* 0x0010 */ uint32 FCORERRADD; /* 0x0014 */ uint32 FCORERRPOS; /* 0x0018 */ uint32 FEDACSTATUS; /* 0x001C */ uint32 FUNCERRADD; /* 0x0020 */ uint32 FEDACSDIS; /* 0x0024 */ uint32 FPRIMADDTAG; /* 0x0028 */ uint32 FREDUADDTAG; /* 0x002C */ uint32 FBPROT; /* 0x0030 */ uint32 FBSE; /* 0x0034 */ uint32 FBBUSY; /* 0x0038 */ uint32 FBAC; /* 0x003C */ uint32 FBFALLBACK; /* 0x0040 */ uint32 FBPRDY; /* 0x0044 */ uint32 FPAC1; /* 0x0048 */ uint32 FPAC2; /* 0x004C */ uint32 FMAC; /* 0x0050 */ uint32 FMSTAT; /* 0x0054 */ uint32 FEMUDMSW; /* 0x0058 */ uint32 FEMUDLSW; /* 0x005C */ uint32 FEMUECC; /* 0x0060 */ uint32 FLOCK; /* 0x0064 */ uint32 FEMUADDR; /* 0x0068 */ uint32 FDIAGCTRL; /* 0x006C */ uint32 FRAWDATAH; /* 0x0070 */ uint32 FRAWDATAL; /* 0x0074 */ uint32 FRAWECC; /* 0x0078 */ uint32 FPAROVR; /* 0x007C */ uint32 rsvd2[16U]; /* 0x009C */ uint32 FEDACSDIS2; /* 0x00C0 */ uint32 rsvd3[15U]; /* 0x00C4 */ uint32 rsvd4[13U]; /* 0x0100 */ uint32 rsvd5[85U]; /* 0x0134 */ uint32 FSMWRENA; /* 0x0288 */ uint32 rsvd6[6U]; /* 0x028C */ uint32 FSMSECTOR; /* 0x02A4 */ uint32 rsvd7[4U]; /* 0x02A8 */ uint32 EEPROMCONFIG; /* 0x02B8 */ uint32 rsvd8[19U]; /* 0x02BC */ uint32 EECTRL1; /* 0x0308 */ uint32 EECTRL2; /* 0x030C */ uint32 EECORRERRCNT; /* 0x0310 */ uint32 EECORRERRADD; /* 0x0314 */ uint32 EECORRERRPOS; /* 0x0318 */ uint32 EESTATUS; /* 0x031C */ uint32 EEUNCERRADD; /* 0x0320 */ } flashWBASE_t; /** @def flashWREG * @brief Flash Wrapper Register Frame Pointer * * This pointer is used by the system driver to access the flash wrapper registers. */ /* USER CODE BEGIN (2) */ /* USER CODE END */ /** @file reg_tcram.h * @brief TCRAM Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* Tcram Register Frame Definition */ /** @struct tcramBase * @brief TCRAM Wrapper Register Frame Definition * * This type is used to access the TCRAM Wrapper Registers. */ /** @typedef tcramBASE_t * @brief TCRAM Wrapper Register Frame Type Definition * * This type is used to access the TCRAM Wrapper Registers. */ typedef volatile struct tcramBase { uint32 RAMCTRL; /* 0x0000 */ uint32 RAMTHRESHOLD; /* 0x0004 */ uint32 RAMOCCUR; /* 0x0008 */ uint32 RAMINTCTRL; /* 0x000C */ uint32 RAMERRSTATUS; /* 0x0010 */ uint32 RAMSERRADDR; /* 0x0014 */ uint32 rsvd1; /* 0x0018 */ uint32 RAMUERRADDR; /* 0x001C */ uint32 rsvd2[4U]; /* 0x0020 */ uint32 RAMTEST; /* 0x0030 */ uint32 rsvd3; /* 0x0034 */ uint32 RAMADDRDECVECT; /* 0x0038 */ uint32 RAMPERADDR; /* 0x003C */ } tcramBASE_t; /* USER CODE BEGIN (2) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* System General Definitions */ /** @enum systemClockSource * @brief Alias names for clock sources * * This enumeration is used to provide alias names for the clock sources: * - Oscillator * - Pll1 * - External1 * - Low Power Oscillator Low * - Low Power Oscillator High * - PLL2 * - External2 * - Synchronous VCLK1 */ enum systemClockSource { SYS_OSC = 0U, /**< Alias for oscillator clock Source */ SYS_PLL1 = 1U, /**< Alias for Pll1 clock Source */ SYS_EXTERNAL1 = 3U, /**< Alias for external clock Source */ SYS_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ SYS_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ SYS_PLL2 = 6U, /**< Alias for Pll2 clock Source */ SYS_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ SYS_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ }; /** @def OSC_FREQ * @brief Oscillator clock source exported from HALCoGen GUI * * Oscillator clock source exported from HALCoGen GUI */ /** @def PLL1_FREQ * @brief PLL 1 clock source exported from HALCoGen GUI * * PLL 1 clock source exported from HALCoGen GUI */ /** @def LPO_LF_FREQ * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI * * LPO Low Freq Oscillator source exported from HALCoGen GUI */ /** @def LPO_HF_FREQ * @brief LPO High Freq Oscillator source exported from HALCoGen GUI * * LPO High Freq Oscillator source exported from HALCoGen GUI */ /** @def PLL1_FREQ * @brief PLL 2 clock source exported from HALCoGen GUI * * PLL 2 clock source exported from HALCoGen GUI */ /** @def GCLK_FREQ * @brief GCLK domain frequency exported from HALCoGen GUI * * GCLK domain frequency exported from HALCoGen GUI */ /** @def HCLK_FREQ * @brief HCLK domain frequency exported from HALCoGen GUI * * HCLK domain frequency exported from HALCoGen GUI */ /** @def RTI_FREQ * @brief RTI Clock frequency exported from HALCoGen GUI * * RTI Clock frequency exported from HALCoGen GUI */ /** @def AVCLK1_FREQ * @brief AVCLK1 Domain frequency exported from HALCoGen GUI * * AVCLK Domain frequency exported from HALCoGen GUI */ /** @def AVCLK2_FREQ * @brief AVCLK2 Domain frequency exported from HALCoGen GUI * * AVCLK2 Domain frequency exported from HALCoGen GUI */ /** @def AVCLK3_FREQ * @brief AVCLK3 Domain frequency exported from HALCoGen GUI * * AVCLK3 Domain frequency exported from HALCoGen GUI */ /** @def AVCLK4_FREQ * @brief AVCLK4 Domain frequency exported from HALCoGen GUI * * AVCLK4 Domain frequency exported from HALCoGen GUI */ /** @def VCLK1_FREQ * @brief VCLK1 Domain frequency exported from HALCoGen GUI * * VCLK1 Domain frequency exported from HALCoGen GUI */ /** @def VCLK2_FREQ * @brief VCLK2 Domain frequency exported from HALCoGen GUI * * VCLK2 Domain frequency exported from HALCoGen GUI */ /** @def VCLK3_FREQ * @brief VCLK3 Domain frequency exported from HALCoGen GUI * * VCLK3 Domain frequency exported from HALCoGen GUI */ /** @def VCLK4_FREQ * @brief VCLK4 Domain frequency exported from HALCoGen GUI * * VCLK4 Domain frequency exported from HALCoGen GUI */ /** @def SYS_PRE1 * @brief Alias name for RTI1CLK PRE clock source * * This is an alias name for the RTI1CLK pre clock source. * This can be either: * - Oscillator * - Pll * - 32 kHz Oscillator * - External * - Low Power Oscillator Low * - Low Power Oscillator High * - Flexray Pll */ /*SAFETYMCUSW 79 S MR:19.4 " Value comes from GUI drop down option " */ /** @def SYS_PRE2 * @brief Alias name for RTI2CLK pre clock source * * This is an alias name for the RTI2CLK pre clock source. * This can be either: * - Oscillator * - Pll * - 32 kHz Oscillator * - External * - Low Power Oscillator Low * - Low Power Oscillator High * - Flexray Pll */ /*SAFETYMCUSW 79 S MR:19.4 " Value comes from GUI drop down option " */ /* Configuration registers */ typedef struct system_config_reg { uint32 CONFIG_SYSPC1; uint32 CONFIG_SYSPC2; uint32 CONFIG_SYSPC7; uint32 CONFIG_SYSPC8; uint32 CONFIG_SYSPC9; uint32 CONFIG_CSDIS; uint32 CONFIG_CDDIS; uint32 CONFIG_GHVSRC; uint32 CONFIG_VCLKASRC; uint32 CONFIG_RCLKSRC; uint32 CONFIG_MSTGCR; uint32 CONFIG_MINITGCR; uint32 CONFIG_MSINENA; uint32 CONFIG_PLLCTL1; uint32 CONFIG_PLLCTL2; uint32 CONFIG_UERFLAG; uint32 CONFIG_LPOMONCTL; uint32 CONFIG_CLKTEST; uint32 CONFIG_DFTCTRLREG1; uint32 CONFIG_DFTCTRLREG2; uint32 CONFIG_GPREG1; uint32 CONFIG_RAMGCR; uint32 CONFIG_BMMCR1; uint32 CONFIG_MMUGCR; uint32 CONFIG_CLKCNTL; uint32 CONFIG_ECPCNTL; uint32 CONFIG_DEVCR1; uint32 CONFIG_SYSECR; uint32 CONFIG_PLLCTL3; uint32 CONFIG_STCCLKDIV; uint32 CONFIG_CLK2CNTL; uint32 CONFIG_VCLKACON1; uint32 CONFIG_CLKSLIP; uint32 CONFIG_EFC_CTLEN; } system_config_reg_t; /* Configuration registers initial value */ void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type); /* USER CODE BEGIN (1) */ /* USER CODE END */ /* FlashW General Definitions */ /** @enum flashWPowerModes * @brief Alias names for flash bank power modes * * This enumeration is used to provide alias names for the flash bank power modes: * - sleep * - standby * - active */ enum flashWPowerModes { SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ }; /* USER CODE BEGIN (2) */ /* USER CODE END */ /* Configuration registers */ typedef struct tcmflash_config_reg { uint32 CONFIG_FRDCNTL; uint32 CONFIG_FEDACCTRL1; uint32 CONFIG_FEDACCTRL2; uint32 CONFIG_FEDACSDIS; uint32 CONFIG_FBPROT; uint32 CONFIG_FBSE; uint32 CONFIG_FBAC; uint32 CONFIG_FBFALLBACK; uint32 CONFIG_FPAC1; uint32 CONFIG_FPAC2; uint32 CONFIG_FMAC; uint32 CONFIG_FLOCK; uint32 CONFIG_FDIAGCTRL; uint32 CONFIG_FEDACSDIS2; } tcmflash_config_reg_t; /* Configuration registers initial value */ void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type); /* USER CODE BEGIN (3) */ /* USER CODE END */ /* System Interface Functions */ void setupPLL(void); void trimLPO(void); void customTrimLPO(void); void setupFlash(void); void periphInit(void); void mapClocks(void); void systemInit(void); void systemPowerDown(uint32 mode); /*Configuration registers * index 0: Even RAM * index 1: Odd RAM */ typedef struct sram_config_reg { uint32 CONFIG_RAMCTRL[2U]; uint32 CONFIG_RAMTHRESHOLD[2U]; uint32 CONFIG_RAMINTCTRL[2U]; uint32 CONFIG_RAMTEST[2U]; uint32 CONFIG_RAMADDRDECVECT[2U]; } sram_config_reg_t; /* Configuration registers initial value */ void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type); /** @file sys_vim.h * @brief Vectored Interrupt Module Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - VIM Type Definitions * - VIM General Definitions * . * which are relevant for Vectored Interrupt Controller. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_vim.h * @brief VIM Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Vim Register Frame Definition */ /** @struct vimBase * @brief Vim Register Frame Definition * * This type is used to access the Vim Registers. */ /** @typedef vimBASE_t * @brief VIM Register Frame Type Definition * * This type is used to access the VIM Registers. */ typedef volatile struct vimBase { uint32 IRQINDEX; /* 0x0000 */ uint32 FIQINDEX; /* 0x0004 */ uint32 rsvd1; /* 0x0008 */ uint32 rsvd2; /* 0x000C */ uint32 FIRQPR0; /* 0x0010 */ uint32 FIRQPR1; /* 0x0014 */ uint32 FIRQPR2; /* 0x0018 */ uint32 FIRQPR3; /* 0x001C */ uint32 INTREQ0; /* 0x0020 */ uint32 INTREQ1; /* 0x0024 */ uint32 INTREQ2; /* 0x0028 */ uint32 INTREQ3; /* 0x002C */ uint32 REQMASKSET0; /* 0x0030 */ uint32 REQMASKSET1; /* 0x0034 */ uint32 REQMASKSET2; /* 0x0038 */ uint32 REQMASKSET3; /* 0x003C */ uint32 REQMASKCLR0; /* 0x0040 */ uint32 REQMASKCLR1; /* 0x0044 */ uint32 REQMASKCLR2; /* 0x0048 */ uint32 REQMASKCLR3; /* 0x004C */ uint32 WAKEMASKSET0; /* 0x0050 */ uint32 WAKEMASKSET1; /* 0x0054 */ uint32 WAKEMASKSET2; /* 0x0058 */ uint32 WAKEMASKSET3; /* 0x005C */ uint32 WAKEMASKCLR0; /* 0x0060 */ uint32 WAKEMASKCLR1; /* 0x0064 */ uint32 WAKEMASKCLR2; /* 0x0068 */ uint32 WAKEMASKCLR3; /* 0x006C */ uint32 IRQVECREG; /* 0x0070 */ uint32 FIQVECREG; /* 0x0074 */ uint32 CAPEVT; /* 0x0078 */ uint32 rsvd3; /* 0x007C */ uint32 CHANCTRL[24U]; /* 0x0080-0x0DC */ } vimBASE_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* VIM Type Definitions */ /** @typedef t_isrFuncPTR * @brief ISR Function Pointer Type Definition * * This type is used to access the ISR handler. */ typedef void (*t_isrFuncPTR)(void); /** @enum systemInterrupt * @brief Alias names for clock sources * * This enumeration is used to provide alias names for the clock sources: * - IRQ * - FIQ */ typedef enum systemInterrupt { SYS_IRQ = 0U, /**< Alias for IRQ interrupt */ SYS_FIQ = 1U /**< Alias for FIQ interrupt */ }systemInterrupt_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /* VIM General Configuration */ /* USER CODE BEGIN (2) */ /* USER CODE END */ /* Interrupt Handlers */ extern void esmHighInterrupt(void); extern void phantomInterrupt(void); /* USER CODE BEGIN (3) */ /* USER CODE END */ /* Configuration registers */ typedef struct vim_config_reg { uint32 CONFIG_FIRQPR0; uint32 CONFIG_FIRQPR1; uint32 CONFIG_FIRQPR2; uint32 CONFIG_FIRQPR3; uint32 CONFIG_REQMASKSET0; uint32 CONFIG_REQMASKSET1; uint32 CONFIG_REQMASKSET2; uint32 CONFIG_REQMASKSET3; uint32 CONFIG_WAKEMASKSET0; uint32 CONFIG_WAKEMASKSET1; uint32 CONFIG_WAKEMASKSET2; uint32 CONFIG_WAKEMASKSET3; uint32 CONFIG_CAPEVT; uint32 CONFIG_CHANCTRL[24U]; } vim_config_reg_t; /* Configuration registers initial value */ /** * @defgroup VIM VIM * @brief Vectored Interrupt Manager * * The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the * many interrupt sources present on a device. Interrupts are caused by events outside of the normal flow of * program execution. * * Related files: * - reg_vim.h * - sys_vim.h * - sys_vim.c * * @addtogroup VIM * @{ */ /*VIM Interface functions*/ void vimInit(void); void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler); void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype); void vimDisableInterrupt(uint32 channel); void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type); /*@}*/ /** @file sys_core.h * @brief System Core Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Core Interface Functions * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /** @def USER_STACK_LENGTH * @brief USER Mode Stack length (in bytes) * * Alias for USER Mode Stack length (in bytes) * * @note: Use this macro for USER Mode Stack length (in bytes) */ /** @def SVC_STACK_LENGTH * @brief SVC Mode Stack length (in bytes) * * Alias for SVC Mode Stack length (in bytes) * * @note: Use this macro for SVC Mode Stack length (in bytes) */ /** @def FIQ_STACK_LENGTH * @brief FIQ Mode Stack length (in bytes) * * Alias for FIQ Mode Stack length (in bytes) * * @note: Use this macro for FIQ Mode Stack length (in bytes) */ /** @def IRQ_STACK_LENGTH * @brief IRQ Mode Stack length (in bytes) * * Alias for IRQ Mode Stack length (in bytes) * * @note: Use this macro for IRQ Mode Stack length (in bytes) */ /** @def ABORT_STACK_LENGTH * @brief ABORT Mode Stack length (in bytes) * * Alias for ABORT Mode Stack length (in bytes) * * @note: Use this macro for ABORT Mode Stack length (in bytes) */ /** @def UNDEF_STACK_LENGTH * @brief UNDEF Mode Stack length (in bytes) * * Alias for UNDEF Mode Stack length (in bytes) * * @note: Use this macro for UNDEF Mode Stack length (in bytes) */ /* System Core Interface Functions */ /** @fn void _coreInitRegisters_(void) * @brief Initialize Core register */ void _coreInitRegisters_(void); /** @fn void _coreInitStackPointer_(void) * @brief Initialize Core stack pointer */ void _coreInitStackPointer_(void); /** @fn void _getCPSRValue_(void) * @brief Get CPSR Value */ uint32 _getCPSRValue_(void); /** @fn void _gotoCPUIdle_(void) * @brief Take CPU to Idle state */ void _gotoCPUIdle_(void); /** @fn void _coreEnableIrqVicOffset_(void) * @brief Enable Irq offset propagation via Vic controller */ void _coreEnableIrqVicOffset_(void); /** @fn void _coreEnableVfp_(void) * @brief Enable vector floating point unit */ void _coreEnableVfp_(void); /** @fn void _coreEnableEventBusExport_(void) * @brief Enable event bus export for external monitoring modules * @note It is required to enable event bus export to process ecc issues. * * This function enables event bus exports to external monitoring modules * like tightly coupled RAM wrapper, Flash wrapper and error signaling module. */ void _coreEnableEventBusExport_(void); /** @fn void _coreDisableEventBusExport_(void) * @brief Disable event bus export for external monitoring modules * * This function disables event bus exports to external monitoring modules * like tightly coupled RAM wrapper, Flash wrapper and error signaling module. */ void _coreDisableEventBusExport_(void); /** @fn void _coreEnableRamEcc_(void) * @brief Enable external ecc error for RAM odd and even bank * @note It is required to enable event bus export to process ecc issues. */ void _coreEnableRamEcc_(void); /** @fn void _coreDisableRamEcc_(void) * @brief Disable external ecc error for RAM odd and even bank */ void _coreDisableRamEcc_(void); /** @fn void _coreEnableFlashEcc_(void) * @brief Enable external ecc error for the Flash * @note It is required to enable event bus export to process ecc issues. */ void _coreEnableFlashEcc_(void); /** @fn void _coreDisableFlashEcc_(void) * @brief Disable external ecc error for the Flash */ void _coreDisableFlashEcc_(void); /** @fn uint32 _coreGetDataFault_(void) * @brief Get core data fault status register * @return The function will return the data fault status register value: * - bit [10,3..0]: * - 0b00001: Alignment -> address is valid * - 0b00000: Background -> address is valid * - 0b01101: Permission -> address is valid * - 0b01000: Precise External Abort -> address is valid * - 0b10110: Imprecise External Abort -> address is unpredictable * - 0b11001: Precise ECC Error -> address is valid * - 0b11000: Imprecise ECC Error -> address is unpredictable * - 0b00010: Debug -> address is unchanged * - bit [11]: * - 0: Read * - 1: Write * - bit [12]: * - 0: AXI Decode Error (DECERR) * - 1: AXI Slave Error (SLVERR) */ uint32 _coreGetDataFault_(void); /** @fn void _coreClearDataFault_(void) * @brief Clear core data fault status register */ void _coreClearDataFault_(void); /** @fn uint32 _coreGetInstructionFault_(void) * @brief Get core instruction fault status register * @return The function will return the instruction fault status register value: * - bit [10,3..0]: * - 0b00001: Alignment -> address is valid * - 0b00000: Background -> address is valid * - 0b01101: Permission -> address is valid * - 0b01000: Precise External Abort -> address is valid * - 0b10110: Imprecise External Abort -> address is unpredictable * - 0b11001: Precise ECC Error -> address is valid * - 0b11000: Imprecise ECC Error -> address is unpredictable * - 0b00010: Debug -> address is unchanged * - bit [12]: * - 0: AXI Decode Error (DECERR) * - 1: AXI Slave Error (SLVERR) */ uint32 _coreGetInstructionFault_(void); /** @fn void _coreClearInstructionFault_(void) * @brief Clear core instruction fault status register */ void _coreClearInstructionFault_(void); /** @fn uint32 _coreGetDataFaultAddress_(void) * @brief Get core data fault address register * @return The function will return the data fault address: */ uint32 _coreGetDataFaultAddress_(void); /** @fn void _coreClearDataFaultAddress_(void) * @brief Clear core data fault address register */ void _coreClearDataFaultAddress_(void); /** @fn uint32 _coreGetInstructionFaultAddress_(void) * @brief Get core instruction fault address register * @return The function will return the instruction fault address: */ uint32 _coreGetInstructionFaultAddress_(void); /** @fn void _coreClearInstructionFaultAddress_(void) * @brief Clear core instruction fault address register */ void _coreClearInstructionFaultAddress_(void); /** @fn uint32 _coreGetAuxiliaryDataFault_(void) * @brief Get core auxiliary data fault status register * @return The function will return the auxiliary data fault status register value: * - bit [13..5]: * - Index value for access giving error * - bit [21]: * - 0: Unrecoverable error * - 1: Recoverable error * - bit [23..22]: * - 0: Side cache * - 1: Side ATCM (Flash) * - 2: Side BTCM (RAM) * - 3: Reserved * - bit [27..24]: * - Cache way or way in which error occurred */ uint32 _coreGetAuxiliaryDataFault_(void); /** @fn void _coreClearAuxiliaryDataFault_(void) * @brief Clear core auxiliary data fault status register */ void _coreClearAuxiliaryDataFault_(void); /** @fn uint32 _coreGetAuxiliaryInstructionFault_(void) * @brief Get core auxiliary instruction fault status register * @return The function will return the auxiliary instruction fault status register value: * - bit [13..5]: * - Index value for access giving error * - bit [21]: * - 0: Unrecoverable error * - 1: Recoverable error * - bit [23..22]: * - 0: Side cache * - 1: Side ATCM (Flash) * - 2: Side BTCM (RAM) * - 3: Reserved * - bit [27..24]: * - Cache way or way in which error occurred */ uint32 _coreGetAuxiliaryInstructionFault_(void); /** @fn void _coreClearAuxiliaryInstructionFault_(void) * @brief Clear core auxiliary instruction fault status register */ void _coreClearAuxiliaryInstructionFault_(void); /** @fn void _disable_interrupt_(void) * @brief Disable IRQ and FIQ Interrupt mode in CPSR register * * This function disables IRQ and FIQ Interrupt mode in CPSR register. */ void _disable_interrupt_(void); /** @fn void _disable_IRQ_interrupt_(void) * @brief Disable IRQ Interrupt mode in CPSR register * * This function disables IRQ Interrupt mode in CPSR register. */ void _disable_IRQ_interrupt_(void); /** @fn void _disable_FIQ_interrupt_(void) * @brief Disable FIQ Interrupt mode in CPSR register * * This function disables IRQ Interrupt mode in CPSR register. */ void _disable_FIQ_interrupt_(void); /** @fn void _enable_interrupt_(void) * @brief Enable IRQ and FIQ Interrupt mode in CPSR register * * This function Enables IRQ and FIQ Interrupt mode in CPSR register. * User must call this function to enable Interrupts in non-OS environments. */ void _enable_interrupt_(void); /** @fn void _esmCcmErrorsClear_(void) * @brief Clears ESM Error caused due to CCM Errata in RevA Silicon * * This function Clears ESM Error caused due to CCM Errata * in RevA Silicon immediately after powerup. */ void _esmCcmErrorsClear_(void); /** @fn void _errata_CORTEXR4_66_(void) * @brief Work Around for Errata CORTEX-R4#66 * * This function Disable out-of-order completion for divide * instructions in Auxiliary Control register. */ void _errata_CORTEXR4_66_(void); /** @fn void _errata_CORTEXR4_57_(void) * @brief Work Around for Errata CORTEX-R4#57 * * Disable out-of-order single-precision floating point * multiply-accumulate instruction completion. */ void _errata_CORTEXR4_57_(void); /** @file sys_selftest.h * @brief System Memory Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Efuse Self Test Functions * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_pbist.h * @brief PBIST Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* PBIST Register Frame Definition */ /** @struct pbistBase * @brief PBIST Base Register Definition * * This structure is used to access the PBIST module registers. */ /** @typedef pbistBASE_t * @brief PBIST Register Frame Type Definition * * This type is used to access the PBIST Registers. */ typedef volatile struct pbistBase { uint32 RAMT; /* 0x0160: RAM Configuration Register */ uint32 DLR; /* 0x0164: Datalogger Register */ uint32 rsvd1[6U]; /* 0x0168 */ uint32 PACT; /* 0x0180: PBIST Activate Register */ uint32 PBISTID; /* 0x0184: PBIST ID Register */ uint32 OVER; /* 0x0188: Override Register */ uint32 rsvd2; /* 0x018C */ uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */ uint32 rsvd5; /* 0x0194 */ uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */ uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */ uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */ uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */ uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */ uint32 rsvd3; /* 0x01AC */ uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */ uint32 rsvd4[3U]; /* 0x01B4 */ uint32 ROM; /* 0x01C0: ROM Mask Register */ uint32 ALGO; /* 0x01C4: Algorithm Mask Register */ uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */ uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */ } pbistBASE_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @file reg_stc.h * @brief STC Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Stc Register Frame Definition */ /** @struct stcBase * @brief STC Base Register Definition * * This structure is used to access the STC module registers. */ /** @typedef stcBASE_t * @brief STC Register Frame Type Definition * * This type is used to access the STC Registers. */ typedef volatile struct stcBase { uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */ uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */ uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */ uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */ uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */ uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */ uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */ uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */ uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */ uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */ uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */ uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */ uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */ uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */ uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */ uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */ } stcBASE_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @file reg_efc.h * @brief EFC Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the System driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Efc Register Frame Definition */ /** @struct efcBase * @brief Efc Register Frame Definition * * This type is used to access the Efc Registers. */ /** @typedef efcBASE_t * @brief Efc Register Frame Type Definition * * This type is used to access the Efc Registers. */ typedef volatile struct efcBase { uint32 INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */ uint32 ADDRESS; /* 0x4 ADDRESS REGISTER */ uint32 DATA_UPPER; /* 0x8 DATA UPPER REGISTER */ uint32 DATA_LOWER; /* 0xc DATA LOWER REGISTER */ uint32 SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */ uint32 SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */ uint32 ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */ uint32 BOUNDARY; /* 0x1C BOUNDARY REGISTER */ uint32 KEY_FLAG; /* 0x20 KEY FLAG REGISTER */ uint32 KEY; /* 0x24 KEY REGISTER */ uint32 rsvd1; /* 0x28 RESERVED */ uint32 PINS; /* 0x2C PINS REGISTER */ uint32 CRA; /* 0x30 CRA */ uint32 READ; /* 0x34 READ REGISTER */ uint32 PROGRAMME; /* 0x38 PROGRAMME REGISTER */ uint32 ERROR; /* 0x3C ERROR STATUS REGISTER */ uint32 SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */ uint32 TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */ uint32 SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */ uint32 SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */ } efcBASE_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @file adc.h * @brief ADC Driver Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the ADC driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_adc.h * @brief ADC Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the ADC driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Adc Register Frame Definition */ /** @struct adcBase * @brief ADC Register Frame Definition * * This type is used to access the ADC Registers. */ /** @typedef adcBASE_t * @brief ADC Register Frame Type Definition * * This type is used to access the ADC Registers. */ typedef volatile struct adcBase { uint32 RSTCR; /**< 0x0000: Reset control register */ uint32 OPMODECR; /**< 0x0004: Operating mode control register */ uint32 CLOCKCR; /**< 0x0008: Clock control register */ uint32 CALCR; /**< 0x000C: Calibration control register */ uint32 GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */ uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */ uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */ uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */ uint32 GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */ uint32 GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */ uint32 GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */ uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */ uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */ uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */ uint32 BNDCR; /**< 0x0058: Buffer boundary control register */ uint32 BNDEND; /**< 0x005C: Buffer boundary end register */ uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */ uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */ uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */ uint32 EVSR; /**< 0x006C: Group 0 status register */ uint32 G1SR; /**< 0x0070: Group 1 status register */ uint32 G2SR; /**< 0x0074: Group 2 status register */ uint32 GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */ uint32 CALR; /**< 0x0084: Calibration register */ uint32 SMSTATE; /**< 0x0088: State machine state register */ uint32 LASTCONV; /**< 0x008C: Last conversion register */ struct { uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */ uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */ uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */ uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */ uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */ uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */ uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */ uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */ } GxBUF[3U]; uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */ uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */ uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */ uint32 EVTDIR; /**< 0x00FC: Event pin direction register */ uint32 EVTOUT; /**< 0x0100: Event pin digital output register */ uint32 EVTIN; /**< 0x0104: Event pin digital input register */ uint32 EVTSET; /**< 0x0108: Event pin set register */ uint32 EVTCLR; /**< 0x010C: Event pin clear register */ uint32 EVTPDR; /**< 0x0110: Event pin open drain register */ uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */ uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */ uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */ uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */ uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */ uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */ uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */ uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */ uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */ uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */ uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */ uint32 rsvd1; /**< 0x0140: Reserved */ uint32 rsvd2; /**< 0x0144: Reserved */ uint32 rsvd3; /**< 0x0148: Reserved */ uint32 rsvd4; /**< 0x014C: Reserved */ uint32 rsvd5; /**< 0x0150: Reserved */ uint32 rsvd6; /**< 0x0154: Reserved */ uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */ uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */ uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */ uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */ uint32 GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */ uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */ uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */ uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */ uint32 PARCR; /**< 0x0180: Parity control register */ uint32 PARADDR; /**< 0x0184: Parity error address register */ uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */ } adcBASE_t; /** @def adcREG1 * @brief ADC1 Register Frame Pointer * * This pointer is used by the ADC driver to access the ADC1 registers. */ /** @def adcREG2 * @brief ADC2 Register Frame Pointer * * This pointer is used by the ADC driver to access the ADC2 registers. */ /** @def adcRAM1 * @brief ADC1 RAM Pointer * * This pointer is used by the ADC driver to access the ADC1 RAM. */ /** @def adcRAM2 * @brief ADC2 RAM Pointer * * This pointer is used by the ADC driver to access the ADC2 RAM. */ /** @def adcPARRAM1 * @brief ADC1 Parity RAM Pointer * * This pointer is used by the ADC driver to access the ADC1 Parity RAM. */ /** @def adcPARRAM2 * @brief ADC2 Parity RAM Pointer * * This pointer is used by the ADC driver to access the ADC2 Parity RAM. */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* ADC General Definitions */ /** @def adcGROUP0 * @brief Alias name for ADC event group * * @note This value should be used for API argument @a group */ /** @def adcGROUP1 * @brief Alias name for ADC group 1 * * @note This value should be used for API argument @a group */ /** @def adcGROUP2 * @brief Alias name for ADC group 2 * * @note This value should be used for API argument @a group */ /** @def ADC_12_BIT_MODE * @brief Alias name for ADC 12-bit mode of operation */ /** @enum adcResolution * @brief Alias names for data resolution * This enumeration is used to provide alias names for the data resolution: * - 12 bit resolution * - 10 bit resolution * - 8 bit resolution */ enum adcResolution { ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */ ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */ ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */ }; /** @enum adcFiFoStatus * @brief Alias names for FiFo status * This enumeration is used to provide alias names for the current FiFo states: * - FiFo is not full * - FiFo is full * - FiFo overflow occurred */ enum adcFiFoStatus { ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */ ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */ ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */ }; /** @enum adcConversionStatus * @brief Alias names for conversion status * This enumeration is used to provide alias names for the current conversion states: * - Conversion is not finished * - Conversion is finished */ enum adcConversionStatus { ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished */ ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */ }; /** @enum adc1HwTriggerSource * @brief Alias names for hardware trigger source * This enumeration is used to provide alias names for the hardware trigger sources: */ enum adc1HwTriggerSource { ADC1_EVENT = 0U, /**< Alias for event pin */ ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */ ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ }; /** @enum adc2HwTriggerSource * @brief Alias names for hardware trigger source * This enumeration is used to provide alias names for the hardware trigger sources: */ enum adc2HwTriggerSource { ADC2_EVENT = 0U, /**< Alias for event pin */ ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */ ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ }; /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @struct adcData * @brief ADC Conversion data structure * * This type is used to pass adc conversion data. */ /** @typedef adcData_t * @brief ADC Data Type Definition */ typedef struct adcData { uint32 id; /**< Channel/Pin Id */ uint16 value; /**< Conversion data value */ } adcData_t; /* USER CODE BEGIN (2) */ /* USER CODE END */ typedef struct adc_config_reg { uint32 CONFIG_OPMODECR; uint32 CONFIG_CLOCKCR; uint32 CONFIG_GxMODECR[3U]; uint32 CONFIG_G0SRC; uint32 CONFIG_G1SRC; uint32 CONFIG_G2SRC; uint32 CONFIG_BNDCR; uint32 CONFIG_BNDEND; uint32 CONFIG_G0SAMP; uint32 CONFIG_G1SAMP; uint32 CONFIG_G2SAMP; uint32 CONFIG_G0SAMPDISEN; uint32 CONFIG_G1SAMPDISEN; uint32 CONFIG_G2SAMPDISEN; uint32 CONFIG_PARCR; }adc_config_reg_t; /** * @defgroup ADC ADC * @brief Analog To Digital Converter Module. * * The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit resolution * * Related Files * - reg_adc.h * - adc.h * - adc.c * @addtogroup ADC * @{ */ /* ADC Interface Functions */ void adcInit(void); void adcStartConversion(adcBASE_t *adc, uint32 group); void adcStopConversion(adcBASE_t *adc, uint32 group); void adcResetFiFo(adcBASE_t *adc, uint32 group); uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t *data); uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group); uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group); void adcEnableNotification(adcBASE_t *adc, uint32 group); void adcDisableNotification(adcBASE_t *adc, uint32 group); void adcCalibration(adcBASE_t *adc); uint32 adcMidPointCalibration(adcBASE_t *adc); void adcSetEVTPin(adcBASE_t *adc, uint32 value); uint32 adcGetEVTPin(adcBASE_t *adc); /** @fn void adcNotification(adcBASE_t *adc, uint32 group) * @brief Group notification * @param[in] adc Pointer to ADC node: * - adcREG1: ADC1 module pointer * - adcREG2: ADC2 module pointer * @param[in] group number of ADC node: * - adcGROUP0: ADC event group * - adcGROUP1: ADC group 1 * - adcGROUP2: ADC group 2 * * @note This function has to be provide by the user. */ void adcNotification(adcBASE_t *adc, uint32 group); /* USER CODE BEGIN (3) */ /* USER CODE END */ /**@}*/ /** @file can.h * @brief CAN Driver Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the CAN driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_can.h * @brief CAN Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the CAN driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Can Register Frame Definition */ /** @struct canBase * @brief CAN Register Frame Definition * * This type is used to access the CAN Registers. */ /** @typedef canBASE_t * @brief CAN Register Frame Type Definition * * This type is used to access the CAN Registers. */ typedef volatile struct canBase { uint32 CTL; /**< 0x0000: Control Register */ uint32 ES; /**< 0x0004: Error and Status Register */ uint32 EERC; /**< 0x0008: Error Counter Register */ uint32 BTR; /**< 0x000C: Bit Timing Register */ uint32 INT; /**< 0x0010: Interrupt Register */ uint32 TEST; /**< 0x0014: Test Register */ uint32 rsvd1; /**< 0x0018: Reserved */ uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */ uint32 rsvd2[24]; /**< 0x002C - 0x7C: Reserved */ uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */ uint32 TXRQX; /**< 0x0084: Transmission Request X Register */ uint32 TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */ uint32 NWDATX; /**< 0x0098: New Data X Register */ uint32 NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */ uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */ uint32 INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */ uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */ uint32 MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */ uint32 rsvd3; /**< 0x00D4: Reserved */ uint32 INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */ uint32 rsvd4[6]; /**< 0x00E8: Reserved */ uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */ uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */ uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */ uint8 IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */ uint32 rsvd5[2]; /**< 0x0118: Reserved */ uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */ uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */ uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */ uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */ uint8 IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */ uint32 rsvd6[2]; /**< 0x0138: Reserved */ uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */ uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */ uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */ uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */ uint8 IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */ uint32 rsvd7[2]; /**< 0x0158: Reserved */ uint32 IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */ uint32 rsvd8[28]; /**< 0x0170: Reserved */ uint32 TIOC; /**< 0x01E0: TX IO Control Register */ uint32 RIOC; /**< 0x01E4: RX IO Control Register */ } canBASE_t; /** @def canREG1 * @brief CAN1 Register Frame Pointer * * This pointer is used by the CAN driver to access the CAN1 registers. */ /** @def canREG2 * @brief CAN2 Register Frame Pointer * * This pointer is used by the CAN driver to access the CAN2 registers. */ /** @def canREG3 * @brief CAN3 Register Frame Pointer * * This pointer is used by the CAN driver to access the CAN3 registers. */ /** @def canRAM1 * @brief CAN1 Mailbox RAM Pointer * * This pointer is used by the CAN driver to access the CAN1 RAM. */ /** @def canRAM2 * @brief CAN2 Mailbox RAM Pointer * * This pointer is used by the CAN driver to access the CAN2 RAM. */ /** @def canRAM3 * @brief CAN3 Mailbox RAM Pointer * * This pointer is used by the CAN driver to access the CAN3 RAM. */ /** @def canPARRAM1 * @brief CAN1 Mailbox Parity RAM Pointer * * This pointer is used by the CAN driver to access the CAN1 Parity RAM * for testing RAM parity error detect logic. */ /** @def canPARRAM2 * @brief CAN2 Mailbox Parity RAM Pointer * * This pointer is used by the CAN driver to access the CAN2 Parity RAM * for testing RAM parity error detect logic. */ /** @def canPARRAM3 * @brief CAN3 Mailbox Parity RAM Pointer * * This pointer is used by the CAN driver to access the CAN3 Parity RAM * for testing RAM parity error detect logic. */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* CAN General Definitions */ /** @def canLEVEL_ACTIVE * @brief Alias name for CAN error operation level active (Error counter 0-31) */ /** @def canLEVEL_PASSIVE * @brief Alias name for CAN error operation level passive (Error counter 32-63) */ /** @def canLEVEL_WARNING * @brief Alias name for CAN error operation level warning (Error counter 64-127) */ /** @def canLEVEL_BUS_OFF * @brief Alias name for CAN error operation level bus off (Error counter 128-255) */ /** @def canLEVEL_PARITY_ERR * @brief Alias name for CAN Parity error (Error counter 256-511) */ /** @def canLEVEL_TxOK * @brief Alias name for CAN Sucessful Transmission */ /** @def canLEVEL_RxOK * @brief Alias name for CAN Sucessful Reception */ /** @def canLEVEL_WakeUpPnd * @brief Alias name for CAN Initiated a WakeUp to system */ /** @def canLEVEL_PDA * @brief Alias name for CAN entered low power mode successfully. */ /** @def canERROR_NO * @brief Alias name for no CAN error occurred */ /** @def canERROR_STUFF * @brief Alias name for CAN stuff error an RX message */ /** @def canERROR_FORMAT * @brief Alias name for CAN form/format error an RX message */ /** @def canERROR_ACKNOWLEDGE * @brief Alias name for CAN TX message wasn't acknowledged */ /** @def canERROR_BIT1 * @brief Alias name for CAN TX message sending recessive level but monitoring dominant */ /** @def canERROR_BIT0 * @brief Alias name for CAN TX message sending dominant level but monitoring recessive */ /** @def canERROR_CRC * @brief Alias name for CAN RX message received wrong CRC */ /** @def canERROR_NO * @brief Alias name for CAN no message has send or received since last call of CANGetLastError */ /** @def canMESSAGE_BOX1 * @brief Alias name for CAN message box 1 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX2 * @brief Alias name for CAN message box 2 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX3 * @brief Alias name for CAN message box 3 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX4 * @brief Alias name for CAN message box 4 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX5 * @brief Alias name for CAN message box 5 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX6 * @brief Alias name for CAN message box 6 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX7 * @brief Alias name for CAN message box 7 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX8 * @brief Alias name for CAN message box 8 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX9 * @brief Alias name for CAN message box 9 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX10 * @brief Alias name for CAN message box 10 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX11 * @brief Alias name for CAN message box 11 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX12 * @brief Alias name for CAN message box 12 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX13 * @brief Alias name for CAN message box 13 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX14 * @brief Alias name for CAN message box 14 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX15 * @brief Alias name for CAN message box 15 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX16 * @brief Alias name for CAN message box 16 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX17 * @brief Alias name for CAN message box 17 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX18 * @brief Alias name for CAN message box 18 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX19 * @brief Alias name for CAN message box 19 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX20 * @brief Alias name for CAN message box 20 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX21 * @brief Alias name for CAN message box 21 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX22 * @brief Alias name for CAN message box 22 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX23 * @brief Alias name for CAN message box 23 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX24 * @brief Alias name for CAN message box 24 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX25 * @brief Alias name for CAN message box 25 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX26 * @brief Alias name for CAN message box 26 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX27 * @brief Alias name for CAN message box 27 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX28 * @brief Alias name for CAN message box 28 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX29 * @brief Alias name for CAN message box 29 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX30 * @brief Alias name for CAN message box 30 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX31 * @brief Alias name for CAN message box 31 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX32 * @brief Alias name for CAN message box 32 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX33 * @brief Alias name for CAN message box 33 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX34 * @brief Alias name for CAN message box 34 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX35 * @brief Alias name for CAN message box 35 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX36 * @brief Alias name for CAN message box 36 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX37 * @brief Alias name for CAN message box 37 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX38 * @brief Alias name for CAN message box 38 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX39 * @brief Alias name for CAN message box 39 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX40 * @brief Alias name for CAN message box 40 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX41 * @brief Alias name for CAN message box 41 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX42 * @brief Alias name for CAN message box 42 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX43 * @brief Alias name for CAN message box 43 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX44 * @brief Alias name for CAN message box 44 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX45 * @brief Alias name for CAN message box 45 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX46 * @brief Alias name for CAN message box 46 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX47 * @brief Alias name for CAN message box 47 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX48 * @brief Alias name for CAN message box 48 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX49 * @brief Alias name for CAN message box 49 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX50 * @brief Alias name for CAN message box 50 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX51 * @brief Alias name for CAN message box 51 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX52 * @brief Alias name for CAN message box 52 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX53 * @brief Alias name for CAN message box 53 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX54 * @brief Alias name for CAN message box 54 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX55 * @brief Alias name for CAN message box 55 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX56 * @brief Alias name for CAN message box 56 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX57 * @brief Alias name for CAN message box 57 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX58 * @brief Alias name for CAN message box 58 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX59 * @brief Alias name for CAN message box 59 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX60 * @brief Alias name for CAN message box 60 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX61 * @brief Alias name for CAN message box 61 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX62 * @brief Alias name for CAN message box 62 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX63 * @brief Alias name for CAN message box 63 * * @note This value should be used for API argument @a messageBox */ /** @def canMESSAGE_BOX64 * @brief Alias name for CAN message box 64 * * @note This value should be used for API argument @a messageBox */ /** @enum canloopBackType * @brief canLoopback type definition */ /** @typedef canloopBackType_t * @brief canLoopback type Type Definition * * This type is used to select the can module Loopback type Digital or Analog loopback. */ typedef enum canloopBackType { Internal_Lbk = 0x00000010U, External_Lbk = 0x00000100U, Internal_Silent_Lbk = 0x00000018U }canloopBackType_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /* Configuration registers */ typedef struct can_config_reg { uint32 CONFIG_CTL; uint32 CONFIG_ES; uint32 CONFIG_BTR; uint32 CONFIG_TEST; uint32 CONFIG_ABOTR; uint32 CONFIG_INTMUX0; uint32 CONFIG_INTMUX1; uint32 CONFIG_INTMUX2; uint32 CONFIG_INTMUX3; uint32 CONFIG_TIOC; uint32 CONFIG_RIOC; } can_config_reg_t; /* Configuration registers initial value for CAN1*/ /* Configuration registers initial value for CAN2*/ /** * @defgroup CAN CAN * @brief Controller Area Network Module. * * The Controller Area Network is a high-integrity, serial, multi-master communication protocol for distributed * real-time applications. This CAN module is implemented according to ISO 11898-1 and is suitable for * industrial, automotive and general embedded communications * * Related Files * - reg_can.h * - can.h * - can.c * @addtogroup CAN * @{ */ /* CAN Interface Functions */ void canInit(void); uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data); uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data); uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox); uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data); uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox); uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox); uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox); uint32 canGetLastError(canBASE_t *node); uint32 canGetErrorLevel(canBASE_t *node); void canEnableErrorNotification(canBASE_t *node); void canDisableErrorNotification(canBASE_t *node); void canEnableStatusChangeNotification(canBASE_t *node); void canDisableStatusChangeNotification(canBASE_t *node); void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype); void canDisableloopback(canBASE_t *node); void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir); void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue); uint32 canIoTxGetBit(canBASE_t *node); uint32 canIoRxGetBit(canBASE_t *node); uint32 canGetID(canBASE_t *node, uint32 messageBox); void canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal); void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type); void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type); /** @fn void canErrorNotification(canBASE_t *node, uint32 notification) * @brief Error notification * @param[in] node Pointer to CAN node: * - canREG1: CAN1 node pointer * - canREG2: CAN2 node pointer * - canREG3: CAN3 node pointer * @param[in] notification Error notification code: * - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 and 63 * - canLEVEL_WARNING (0x40) : When RX- or TX error counter are between 64 and 127 * - canLEVEL_BUS_OFF (0x80) : When RX- or TX error counter are between 128 and 255 * - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256 * * @note This function has to be provide by the user. */ void canErrorNotification(canBASE_t *node, uint32 notification); /** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification) * @brief Status Change notification * @param[in] node Pointer to CAN node: * - canREG1: CAN1 node pointer * - canREG2: CAN2 node pointer * - canREG3: CAN3 node pointer * @param[in] notification Status change notification code: * - canLEVEL_TxOK (0x08) : When successful transmission * - canLEVEL_RxOK (0x10) : When successful reception * - canLEVEL_WakeUpPnd (0x200): When successful WakeUp to system initiated * - canLEVEL_PDA (0x400): When successful low power mode entrance * * @note This function has to be provide by the user. */ void canStatusChangeNotification(canBASE_t *node, uint32 notification); /** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox) * @brief Message notification * @param[in] node Pointer to CAN node: * - canREG1: CAN1 node pointer * - canREG2: CAN2 node pointer * - canREG3: CAN3 node pointer * @param[in] messageBox Message box number of CAN node: * - canMESSAGE_BOX1: CAN message box 1 * - canMESSAGE_BOXn: CAN message box n [n: 1-64] * - canMESSAGE_BOX64: CAN message box 64 * * @note This function has to be provide by the user. */ void canMessageNotification(canBASE_t *node, uint32 messageBox); /* USER CODE BEGIN (2) */ /* USER CODE END */ /**@}*/ /** @file mibspi.h * @brief MIBSPI Driver Definition File * @date 11-Dec-2018 * @version 04.07.01 * */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_mibspi.h * @brief MIBSPI Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the MIBSPI driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Mibspi Register Frame Definition */ /** @struct mibspiBase * @brief MIBSPI Register Definition * * This structure is used to access the MIBSPI module registers. */ /** @typedef mibspiBASE_t * @brief MIBSPI Register Frame Type Definition * * This type is used to access the MIBSPI Registers. */ typedef volatile struct mibspiBase { uint32 GCR0; /**< 0x0000: Global Control 0 */ uint32 GCR1; /**< 0x0004: Global Control 1 */ uint32 INT0; /**< 0x0008: Interrupt Register */ uint32 LVL; /**< 0x000C: Interrupt Level */ uint32 FLG; /**< 0x0010: Interrupt flags */ uint32 PC0; /**< 0x0014: Function Pin Enable */ uint32 PC1; /**< 0x0018: Pin Direction */ uint32 PC2; /**< 0x001C: Pin Input Latch */ uint32 PC3; /**< 0x0020: Pin Output Latch */ uint32 PC4; /**< 0x0024: Output Pin Set */ uint32 PC5; /**< 0x0028: Output Pin Clr */ uint32 PC6; /**< 0x002C: Open Drain Output Enable */ uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */ uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */ uint32 DAT0; /**< 0x0038: Transmit Data */ uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ uint32 BUF; /**< 0x0040: Receive Buffer */ uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ uint32 DELAY; /**< 0x0048: Delays */ uint32 DEF; /**< 0x004C: Default Chip Select */ uint32 FMT0; /**< 0x0050: Data Format 0 */ uint32 FMT1; /**< 0x0054: Data Format 1 */ uint32 FMT2; /**< 0x0058: Data Format 2 */ uint32 FMT3; /**< 0x005C: Data Format 3 */ uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ uint32 SRSEL; /**< 0x0068: Slew Rate Select */ uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */ uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */ uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */ uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */ uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */ uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */ uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */ uint32 rsvd1[2U]; /**< 0x0088: Reserved */ uint32 TICKCNT; /**< 0x0090: Tick Counter */ uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */ uint32 TGCTRL[16U]; /**< 0x0098 - 0x00D4: Transfer Group Control */ uint32 DMACTRL[8U]; /**< 0x00D8 - 0x00F4: DMA Control */ uint32 DMACOUNT[8U]; /**< 0x00F8 - 0x0114: DMA Count */ uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */ uint32 rsvd2; /**< 0x011C: Reserved */ uint32 UERRCTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */ uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */ uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */ uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */ uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */ uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ uint32 EXT_PRESCALE1; /**< 0x0138: */ uint32 EXT_PRESCALE2; /**< 0x013C: */ } mibspiBASE_t; /** @def mibspiREG1 * @brief MIBSPI1 Register Frame Pointer * * This pointer is used by the MIBSPI driver to access the mibspi module registers. */ /** @def mibspiPORT1 * @brief MIBSPI1 GIO Port Register Pointer * * Pointer used by the GIO driver to access I/O PORT of MIBSPI1 * (use the GIO drivers to access the port pins). */ /** @def mibspiREG3 * @brief MIBSPI3 Register Frame Pointer * * This pointer is used by the MIBSPI driver to access the mibspi module registers. */ /** @def mibspiPORT3 * @brief MIBSPI3 GIO Port Register Pointer * * Pointer used by the GIO driver to access I/O PORT of MIBSPI3 * (use the GIO drivers to access the port pins). */ /** @def mibspiREG5 * @brief MIBSPI5 Register Frame Pointer * * This pointer is used by the MIBSPI driver to access the mibspi module registers. */ /** @def mibspiPORT5 * @brief MIBSPI5 GIO Port Register Pointer * * Pointer used by the GIO driver to access I/O PORT of MIBSPI5 * (use the GIO drivers to access the port pins). */ /** @struct mibspiRamBase * @brief MIBSPI Buffer RAM Definition * * This structure is used to access the MIBSPI buffer memory. */ /** @typedef mibspiRAM_t * @brief MIBSPI RAM Type Definition * * This type is used to access the MIBSPI RAM. */ typedef volatile struct mibspiRamBase { struct { uint16 control; /**< tx buffer control */ uint16 data; /**< tx buffer data */ } tx[128]; struct { uint16 flags; /**< rx buffer flags */ uint16 data; /**< rx buffer data */ } rx[128]; } mibspiRAM_t; /** @def mibspiRAM1 * @brief MIBSPI1 Buffer RAM Pointer * * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. */ /** @def mibspiRAM3 * @brief MIBSPI3 Buffer RAM Pointer * * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. */ /** @def mibspiRAM5 * @brief MIBSPI5 Buffer RAM Pointer * * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. */ /** @def mibspiPARRAM1 * @brief MIBSPI1 Buffer RAM PARITY Pointer * * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. */ /** @def mibspiPARRAM3 * @brief MIBSPI3 Buffer RAM PARITY Pointer * * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. */ /** @def mibspiPARRAM5 * @brief MIBSPI5 Buffer RAM PARITY Pointer * * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /** @enum triggerEvent * @brief Transfer Group Trigger Event */ enum triggerEvent { TRG_NEVER = 0U, TRG_RISING = 1U, TRG_FALLING = 2U, TRG_BOTH = 3U, TRG_HIGH = 5U, TRG_LOW = 6U, TRG_ALWAYS = 7U }; /** @enum triggerSource * @brief Transfer Group Trigger Source */ enum triggerSource { TRG_DISABLED, TRG_GIOA0, TRG_GIOA1, TRG_GIOA2, TRG_GIOA3, TRG_GIOA4, TRG_GIOA5, TRG_GIOA6, TRG_GIOA7, TRG_HET1_8, TRG_HET1_10, TRG_HET1_12, TRG_HET1_14, TRG_HET1_16, TRG_HET1_18, TRG_TICK }; /** @enum mibspiPinSelect * @brief mibspi Pin Select */ enum mibspiPinSelect { PIN_CS0 = 0U, PIN_CS1 = 1U, PIN_CS2 = 2U, PIN_CS3 = 3U, PIN_CS4 = 4U, PIN_CS5 = 5U, PIN_CS6 = 6U, PIN_CS7 = 7U, PIN_ENA = 8U, PIN_CLK = 9U, PIN_SIMO = 10U, PIN_SOMI = 11U, PIN_SIMO_1 = 17U, PIN_SIMO_2 = 18U, PIN_SIMO_3 = 19U, PIN_SIMO_4 = 20U, PIN_SIMO_5 = 21U, PIN_SIMO_6 = 22U, PIN_SIMO_7 = 23U, PIN_SOMI_1 = 25U, PIN_SOMI_2 = 26U, PIN_SOMI_3 = 27U, PIN_SOMI_4 = 28U, PIN_SOMI_5 = 29U, PIN_SOMI_6 = 30U, PIN_SOMI_7 = 31U }; /** @enum chipSelect * @brief Transfer Group Chip Select */ enum chipSelect { CS_NONE = 0xFFU, CS_0 = 0xFEU, CS_1 = 0xFDU, CS_2 = 0xFBU, CS_3 = 0xF7U, CS_4 = 0xEFU, CS_5 = 0xDFU, CS_6 = 0xBFU, CS_7 = 0x7FU }; /** @typedef mibspiPmode_t * @brief Mibspi Parellel mode Type Definition * * This type is used to represent Mibspi Parellel mode. */ typedef enum mibspiPmode { PMODE_NORMAL = 0x0U, PMODE_2_DATALINE = 0x1U, PMODE_4_DATALINE = 0x2U, PMODE_8_DATALINE = 0x3U }mibspiPmode_t; /** @typedef mibspiDFMT_t * @brief Mibspi Data format selection Type Definition * * This type is used to represent Mibspi Data format selection. */ typedef enum mibspiDFMT { DATA_FORMAT0 = 0x0U, DATA_FORMAT1 = 0x1U, DATA_FORMAT2 = 0x2U, DATA_FORMAT3 = 0x3U }mibspiDFMT_t; typedef struct mibspi_config_reg { uint32 CONFIG_GCR1; uint32 CONFIG_INT0; uint32 CONFIG_LVL; uint32 CONFIG_PCFUN; uint32 CONFIG_PCDIR; uint32 CONFIG_PCPDR; uint32 CONFIG_PCDIS; uint32 CONFIG_PCPSL; uint32 CONFIG_DELAY; uint32 CONFIG_FMT0; uint32 CONFIG_FMT1; uint32 CONFIG_FMT2; uint32 CONFIG_FMT3; uint32 CONFIG_MIBSPIE; uint32 CONFIG_LTGPEND; uint32 CONFIG_TGCTRL[8U]; uint32 CONFIG_UERRCTRL; }mibspi_config_reg_t; /** * @defgroup MIBSPI MIBSPI * @brief Multi-Buffered Serial Peripheral Interface Module. * * The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a serial bit stream of * programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. * The MibSPI has a programmable buffer memory that enables programmed transmission to be completed * without CPU intervention * * Related Files * - reg_mibspi.h * - mibspi.h * - mibspi.c * @addtogroup MIBSPI * @{ */ /* MIBSPI Interface Functions */ void mibspiInit(void); void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port); void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data); uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data); void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group); boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group); void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level); void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group); void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype); void mibspiDisableLoopback(mibspiBASE_t *mibspi); void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT); void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type); void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type); /** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) * @brief Error interrupt callback * @param[in] mibspi - mibSpi module base address * @param[in] flags - Copy of error interrupt flags * * This is a error callback that is provided by the application and is call upon * an error interrupt. The paramer passed to the callback is a copy of the error * interrupt flag register. */ void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags); /** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group) * @brief Transfer complete notification callback * @param[in] mibspi - mibSpi module base address * @param[in] group - Transfer group * * This is a callback function provided by the application. It is call when * a transfer is complete. The parameter is the transfer group that triggered * the interrupt. */ void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group); /* USER CODE BEGIN (1) */ /* USER CODE END */ /**@}*/ /** @file het.h * @brief HET Driver Definition File * @date 11-Dec-2018 * @version 04.07.01 * */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_het.h * @brief HET Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the HET driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Het Register Frame Definition */ /** @struct hetBase * @brief HET Base Register Definition * * This structure is used to access the HET module registers. */ /** @typedef hetBASE_t * @brief HET Register Frame Type Definition * * This type is used to access the HET Registers. */ typedef volatile struct hetBase { uint32 GCR; /**< 0x0000: Global control register */ uint32 PFR; /**< 0x0004: Prescale factor register */ uint32 ADDR; /**< 0x0008: Current address register */ uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */ uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */ uint32 INTENAS; /**< 0x0014: Interrupt enable set register */ uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */ uint32 EXC1; /**< 0x001C: Exception control register 1 */ uint32 EXC2; /**< 0x0020: Exception control register 2 */ uint32 PRY; /**< 0x0024: Interrupt priority register */ uint32 FLG; /**< 0x0028: Interrupt flag register */ uint32 AND; /**< 0x002C: AND share control register */ uint32 rsvd1; /**< 0x0030: Reserved */ uint32 HRSH; /**< 0x0034: High resolution share register */ uint32 XOR; /**< 0x0038: XOR share register */ uint32 REQENS; /**< 0x003C: Request enable set register */ uint32 REQENC; /**< 0x0040: Request enable clear register */ uint32 REQDS; /**< 0x0044: Request destination select register */ uint32 rsvd2; /**< 0x0048: Reserved */ uint32 DIR; /**< 0x004C: Direction register */ uint32 DIN; /**< 0x0050: Data input register */ uint32 DOUT; /**< 0x0054: Data output register */ uint32 DSET; /**< 0x0058: Data output set register */ uint32 DCLR; /**< 0x005C: Data output clear register */ uint32 PDR; /**< 0x0060: Open drain register */ uint32 PULDIS; /**< 0x0064: Pull disable register */ uint32 PSL; /**< 0x0068: Pull select register */ uint32 rsvd3; /**< 0x006C: Reserved */ uint32 rsvd4; /**< 0x0070: Reserved */ uint32 PCR; /**< 0x0074: Parity control register */ uint32 PAR; /**< 0x0078: Parity address register */ uint32 PPR; /**< 0x007C: Parity pin select register */ uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */ uint32 SFENA; /**< 0x0084: Suppression filter enable register */ uint32 rsvd5; /**< 0x0088: Reserved */ uint32 LBPSEL; /**< 0x008C: Loop back pair select register */ uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */ uint32 PINDIS; /**< 0x0094: Pin disable register */ } hetBASE_t; /** @struct hetInstructionBase * @brief HET Instruction Definition * * This structure is used to access the HET RAM. */ /** @typedef hetINSTRUCTION_t * @brief HET Instruction Type Definition * * This type is used to access a HET Instruction. */ typedef volatile struct hetInstructionBase { uint32 Program; uint32 Control; uint32 Data; uint32 rsvd1; } hetINSTRUCTION_t; /** @struct hetRamBase * @brief HET RAM Definition * * This structure is used to access the HET RAM. */ /** @typedef hetRAMBASE_t * @brief HET RAM Type Definition * * This type is used to access the HET RAM. */ typedef volatile struct het1RamBase { hetINSTRUCTION_t Instruction[160U]; } hetRAMBASE_t; /** @def hetREG1 * @brief HET Register Frame Pointer * * This pointer is used by the HET driver to access the het module registers. */ /** @def hetPORT1 * @brief HET GIO Port Register Pointer * * Pointer used by the GIO driver to access I/O PORT of HET1 * (use the GIO drivers to access the port pins). */ /** @def hetRAM1 * @brief NHET1 RAM Pointer * * This pointer is used by the HET driver to access the NHET1 memory. */ /** @def hetREG2 * @brief HET2 Register Frame Pointer * * This pointer is used by the HET driver to access the het module registers. */ /** @def hetPORT2 * @brief HET2 GIO Port Register Pointer * * Pointer used by the GIO driver to access I/O PORT of HET2 * (use the GIO drivers to access the port pins). */ /** @def hetRAM2 * @brief NHET1 RAM Pointer * * This pointer is used by the HET driver to access the NHET2 memory. */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /*****************************************************************************/ /* string.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-6.3") /* standard types required for standard headers */ #pragma CHECK_MISRA("-19.1") /* #includes required for implementation */ #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ typedef unsigned size_t; /*****************************************************************************/ /* _ti_config.h */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") #pragma CHECK_MISRA("-19.1") /* Common definitions */ /* C */ /* C11 */ /* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It is intended to be used for functions like abort and atexit that are supposed to be declared noexcept only in C++14 mode. */ /* Target-specific definitions */ /*****************************************************************************/ /* linkage.h */ /* */ /* Copyright (c) 1998 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ /* No modifiers are needed to access code or data */ /*--------------------------------------------------------------------------*/ /* Define _IDECL ==> how inline functions are declared */ /*--------------------------------------------------------------------------*/ #pragma diag_pop #pragma diag_pop #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ #pragma diag_pop size_t strlen(const char *string); char *strcpy(char * __restrict dest, const char * __restrict src); char *strncpy(char * __restrict dest, const char * __restrict src, size_t n); char *strcat(char * __restrict string1, const char * __restrict string2); char *strncat(char * __restrict dest, const char * __restrict src, size_t n); char *strchr(const char *string, int c); char *strrchr(const char *string, int c); int strcmp(const char *string1, const char *string2); int strncmp(const char *string1, const char *string2, size_t n); int strcoll(const char *string1, const char *_string2); size_t strxfrm(char * __restrict to, const char * __restrict from, size_t n); char *strpbrk(const char *string, const char *chs); size_t strspn(const char *string, const char *chs); size_t strcspn(const char *string, const char *chs); char *strstr(const char *string1, const char *string2); char *strtok(char * __restrict str1, const char * __restrict str2); char *strerror(int _errno); char *strdup(const char *string); void *memmove(void *s1, const void *s2, size_t n); #pragma diag_push #pragma CHECK_MISRA("-16.4") /* false positives due to builtin declarations */ void *memcpy(void * __restrict s1, const void * __restrict s2, size_t n); #pragma diag_pop int memcmp(const void *cs, const void *ct, size_t n); void *memchr(const void *cs, int c, size_t n); void *memset(void *mem, int ch, size_t length); /*----------------------------------------------------------------------------*/ /* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ /* this file will have already included sys/cdefs.h. */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* Include xlocale/_string.h> if POSIX is enabled. This will expose the */ /* xlocale string interface. */ /*----------------------------------------------------------------------------*/ #pragma diag_pop /* USER CODE BEGIN (0) */ /* USER CODE END */ /** @def pwm0 * @brief Pwm signal 0 * * Alias for pwm signal 0 */ /** @def pwm1 * @brief Pwm signal 1 * * Alias for pwm signal 1 */ /** @def pwm2 * @brief Pwm signal 2 * * Alias for pwm signal 2 */ /** @def pwm3 * @brief Pwm signal 3 * * Alias for pwm signal 3 */ /** @def pwm4 * @brief Pwm signal 4 * * Alias for pwm signal 4 */ /** @def pwm5 * @brief Pwm signal 5 * * Alias for pwm signal 5 */ /** @def pwm6 * @brief Pwm signal 6 * * Alias for pwm signal 6 */ /** @def pwm7 * @brief Pwm signal 7 * * Alias for pwm signal 7 */ /** @def edge0 * @brief Edge signal 0 * * Alias for edge signal 0 */ /** @def edge1 * @brief Edge signal 1 * * Alias for edge signal 1 */ /** @def edge2 * @brief Edge signal 2 * * Alias for edge signal 2 */ /** @def edge3 * @brief Edge signal 3 * * Alias for edge signal 3 */ /** @def edge4 * @brief Edge signal 4 * * Alias for edge signal 4 */ /** @def edge5 * @brief Edge signal 5 * * Alias for edge signal 5 */ /** @def edge6 * @brief Edge signal 6 * * Alias for edge signal 6 */ /** @def edge7 * @brief Edge signal 7 * * Alias for edge signal 7 */ /** @def cap0 * @brief Capture signal 0 * * Alias for capture signal 0 */ /** @def cap1 * @brief Capture signal 1 * * Alias for capture signal 1 */ /** @def cap2 * @brief Capture signal 2 * * Alias for capture signal 2 */ /** @def cap3 * @brief Capture signal 3 * * Alias for capture signal 3 */ /** @def cap4 * @brief Capture signal 4 * * Alias for capture signal 4 */ /** @def cap5 * @brief Capture signal 5 * * Alias for capture signal 5 */ /** @def cap6 * @brief Capture signal 6 * * Alias for capture signal 6 */ /** @def cap7 * @brief Capture signal 7 * * Alias for capture signal 7 */ /** @def pwmEND_OF_DUTY * @brief Pwm end of duty * * Alias for pwm end of duty notification */ /** @def pwmEND_OF_PERIOD * @brief Pwm end of period * * Alias for pwm end of period notification */ /** @def pwmEND_OF_BOTH * @brief Pwm end of duty and period * * Alias for pwm end of duty and period notification */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @struct hetBase * @brief HET Register Definition * * This structure is used to access the HET module registers. */ /** @typedef hetBASE_t * @brief HET Register Frame Type Definition * * This type is used to access the HET Registers. */ enum hetPinSelect { PIN_HET_0 = 0U, PIN_HET_1 = 1U, PIN_HET_2 = 2U, PIN_HET_3 = 3U, PIN_HET_4 = 4U, PIN_HET_5 = 5U, PIN_HET_6 = 6U, PIN_HET_7 = 7U, PIN_HET_8 = 8U, PIN_HET_9 = 9U, PIN_HET_10 = 10U, PIN_HET_11 = 11U, PIN_HET_12 = 12U, PIN_HET_13 = 13U, PIN_HET_14 = 14U, PIN_HET_15 = 15U, PIN_HET_16 = 16U, PIN_HET_17 = 17U, PIN_HET_18 = 18U, PIN_HET_19 = 19U, PIN_HET_20 = 20U, PIN_HET_21 = 21U, PIN_HET_22 = 22U, PIN_HET_23 = 23U, PIN_HET_24 = 24U, PIN_HET_25 = 25U, PIN_HET_26 = 26U, PIN_HET_27 = 27U, PIN_HET_28 = 28U, PIN_HET_29 = 29U, PIN_HET_30 = 30U, PIN_HET_31 = 31U }; /** @struct hetSignal * @brief HET Signal Definition * * This structure is used to define a pwm signal. */ /** @typedef hetSIGNAL_t * @brief HET Signal Type Definition * * This type is used to access HET Signal Information. */ typedef struct hetSignal { uint32 duty; /**< Duty cycle in % of the period */ float64 period; /**< Period in us */ } hetSIGNAL_t; /* Configuration registers */ typedef struct het_config_reg { uint32 CONFIG_GCR; uint32 CONFIG_PFR; uint32 CONFIG_INTENAS; uint32 CONFIG_INTENAC; uint32 CONFIG_PRY; uint32 CONFIG_AND; uint32 CONFIG_HRSH; uint32 CONFIG_XOR; uint32 CONFIG_DIR; uint32 CONFIG_PDR; uint32 CONFIG_PULDIS; uint32 CONFIG_PSL; uint32 CONFIG_PCR; } het_config_reg_t; /* Configuration registers initial value for HET1*/ /** * @defgroup HET HET * @brief HighEnd Timer Module. * * The HET is a software-controlled timer with a dedicated specialized timer micromachine and a set of 30 instructions. * The HET micromachine is connected to a port of up to 32 input/output (I/O) pins. * * Related Files * - reg_het.h * - het.h * - het.c * - reg_htu.h * - htu.h * - std_nhet.h * @addtogroup HET * @{ */ /* HET Interface Functions */ void hetInit(void); /* PWM Interface Functions */ void pwmStart(hetRAMBASE_t * hetRAM,uint32 pwm); void pwmStop(hetRAMBASE_t * hetRAM,uint32 pwm); void pwmSetDuty(hetRAMBASE_t * hetRAM,uint32 pwm, uint32 pwmDuty); void pwmSetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t signal); void pwmGetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t *signal); void pwmEnableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification); void pwmDisableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification); void pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification); /* Edge Interface Functions */ void edgeResetCounter(hetRAMBASE_t * hetRAM,uint32 edge); uint32 edgeGetCounter(hetRAMBASE_t * hetRAM,uint32 edge); void edgeEnableNotification(hetBASE_t * hetREG,uint32 edge); void edgeDisableNotification(hetBASE_t * hetREG,uint32 edge); void edgeNotification(hetBASE_t * hetREG,uint32 edge); /* Captured Signal Interface Functions */ void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t *signal); /* Timestamp Interface Functions */ void hetResetTimestamp(hetRAMBASE_t * hetRAM); uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM); void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type); /** @fn void hetNotification(hetBASE_t *het, uint32 offset) * @brief het interrupt callback * @param[in] het - Het module base address * - hetREG1: HET1 module base address pointer * - hetREG2: HET2 module base address pointer * @param[in] offset - het interrupt offset / Source number * * @note This function has to be provide by the user. * * This is a interrupt callback that is provided by the application and is call upon * an het interrupt. The parameter passed to the callback is a copy of the interrupt * offset register which is used to decode the interrupt source. */ void hetNotification(hetBASE_t *het, uint32 offset); /* USER CODE BEGIN (2) */ /* USER CODE END */ /**@}*/ /** @file htu.h * @brief HTU Driver Definition File * @date 11-Dec-2018 * @version 04.07.01 * */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_htu.h * @brief HTU Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the HTU driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* htu Register Frame Definition */ /** @struct htuBase * @brief HTU Base Register Definition * * This structure is used to access the HTU module registers. */ /** @typedef htuBASE_t * @brief HTU Register Frame Type Definition * * This type is used to access the HTU Registers. */ typedef volatile struct htuBase { uint32 GC; /** 0x00 */ uint32 CPENA; /** 0x04 */ uint32 BUSY0; /** 0x08 */ uint32 BUSY1; /** 0x0C */ uint32 BUSY2; /** 0x10 */ uint32 BUSY3; /** 0x14 */ uint32 ACPE; /** 0x18 */ uint32 rsvd1; /** 0x1C */ uint32 RLBECTRL; /** 0x20 */ uint32 BFINTS; /** 0x24 */ uint32 BFINTC; /** 0x28 */ uint32 INTMAP; /** 0x2C */ uint32 rsvd2; /** 0x30 */ uint32 INTOFF0; /** 0x34 */ uint32 INTOFF1; /** 0x38 */ uint32 BIM; /** 0x3C */ uint32 RLOSTFL; /** 0x40 */ uint32 BFINTFL; /** 0x44 */ uint32 BERINTFL; /** 0x48 */ uint32 MP1S; /** 0x4C */ uint32 MP1E; /** 0x50 */ uint32 DCTRL; /** 0x54 */ uint32 WPR; /** 0x58 */ uint32 WMR; /** 0x5C */ uint32 ID; /** 0x60 */ uint32 PCR; /** 0x64 */ uint32 PAR; /** 0x68 */ uint32 rsvd3; /** 0x6C */ uint32 MPCS; /** 0x70 */ uint32 MP0S; /** 0x74 */ uint32 MP0E; /** 0x78 */ } htuBASE_t; typedef volatile struct { struct /* 0x00-0x7C */ { uint32 IFADDRA; uint32 IFADDRB; uint32 IHADDRCT; uint32 ITCOUNT; }DCP[8U]; struct /* 0x80-0xFC */ { uint32 res[32U]; } RESERVED; struct /* 0x100-0x17C */ { uint32 CFADDRA; uint32 CFADDRB; uint32 CFCOUNT; uint32 rsvd4; }CDCP[8U]; } htuRAMBASE_t; /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* HTU General Definitions */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /** @file esm.h * @brief Error Signaling Module Driver Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * . * which are relevant for the Esm driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** @file reg_esm.h * @brief ESM Register Layer Header File * @date 11-Dec-2018 * @version 04.07.01 * * This file contains: * - Definitions * - Types * - Interface Prototypes * . * which are relevant for the ESM driver. */ /* * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Esm Register Frame Definition */ /** @struct esmBase * @brief Esm Register Frame Definition * * This type is used to access the Esm Registers. */ /** @typedef esmBASE_t * @brief Esm Register Frame Type Definition * * This type is used to access the Esm Registers. */ typedef volatile struct esmBase { uint32 EEPAPR1; /* 0x0000 */ uint32 DEPAPR1; /* 0x0004 */ uint32 IESR1; /* 0x0008 */ uint32 IECR1; /* 0x000C */ uint32 ILSR1; /* 0x0010 */ uint32 ILCR1; /* 0x0014 */ uint32 SR1[3U]; /* 0x0018, 0x001C, 0x0020 */ uint32 EPSR; /* 0x0024 */ uint32 IOFFHR; /* 0x0028 */ uint32 IOFFLR; /* 0x002C */ uint32 LTCR; /* 0x0030 */ uint32 LTCPR; /* 0x0034 */ uint32 EKR; /* 0x0038 */ uint32 SSR2; /* 0x003C */ uint32 IEPSR4; /* 0x0040 */ uint32 IEPCR4; /* 0x0044 */ uint32 IESR4; /* 0x0048 */ uint32 IECR4; /* 0x004C */ uint32 ILSR4; /* 0x0050 */ uint32 ILCR4; /* 0x0054 */ uint32 SR4[3U]; /* 0x0058, 0x005C, 0x0060 */ } esmBASE_t; /** @def esmREG * @brief Esm Register Frame Pointer * * This pointer is used by the Esm driver to access the Esm registers. */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* ESM General Definitions */ /** @def esmGROUP1 * @brief Alias name for ESM group 1 * * This is an alias name for the ESM group 1. * * @note This value should be used for API argument @a group */ /** @def esmGROUP2 * @brief Alias name for ESM group 2 * * This is an alias name for the ESM group 2. * * @note This value should be used for API argument @a group */ /** @def esmGROUP3 * @brief Alias name for ESM group 3 * * This is an alias name for the ESM group 3. * * @note This value should be used for API argument @a group */ /** @def esmCHANNEL0 * @brief Alias name for ESM group x channel 0 * * This is an alias name for the ESM group x channel 0. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL1 * @brief Alias name for ESM group x channel 1 * * This is an alias name for the ESM group x channel 1. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL2 * @brief Alias name for ESM group x channel 2 * * This is an alias name for the ESM group x channel 2. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL3 * @brief Alias name for ESM group x channel 3 * * This is an alias name for the ESM group x channel 3. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL4 * @brief Alias name for ESM group x channel 4 * * This is an alias name for the ESM group x channel 4. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL5 * @brief Alias name for ESM group x channel 5 * * This is an alias name for the ESM group x channel 5. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL6 * @brief Alias name for ESM group x channel 6 * * This is an alias name for the ESM group x channel 6. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL7 * @brief Alias name for ESM group x channel 7 * * This is an alias name for the ESM group x channel 7. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL8 * @brief Alias name for ESM group x channel 8 * * This is an alias name for the ESM group x channel 8. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL9 * @brief Alias name for ESM group x channel 9 * * This is an alias name for the ESM group x channel 9. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL10 * @brief Alias name for ESM group x channel 10 * * This is an alias name for the ESM group x channel 10. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL11 * @brief Alias name for ESM group x channel 11 * * This is an alias name for the ESM group x channel 11. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL12 * @brief Alias name for ESM group x channel 12 * * This is an alias name for the ESM group x channel 12. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL13 * @brief Alias name for ESM group x channel 13 * * This is an alias name for the ESM group x channel 13. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL14 * @brief Alias name for ESM group x channel 14 * * This is an alias name for the ESM group x channel 14. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL15 * @brief Alias name for ESM group x channel 15 * * This is an alias name for the ESM group x channel 15. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL16 * @brief Alias name for ESM group x channel 16 * * This is an alias name for the ESM group x channel 16. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL17 * @brief Alias name for ESM group x channel 17 * * This is an alias name for the ESM group x channel 17. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL18 * @brief Alias name for ESM group x channel 18 * * This is an alias name for the ESM group x channel 18. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL19 * @brief Alias name for ESM group x channel 19 * * This is an alias name for the ESM group x channel 19. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL20 * @brief Alias name for ESM group x channel 20 * * This is an alias name for the ESM group x channel 20. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL21 * @brief Alias name for ESM group x channel 21 * * This is an alias name for the ESM group x channel 21. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL22 * @brief Alias name for ESM group x channel 22 * * This is an alias name for the ESM group x channel 22. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL23 * @brief Alias name for ESM group x channel 23 * * This is an alias name for the ESM group x channel 23. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL24 * @brief Alias name for ESM group x channel 24 * * This is an alias name for the ESM group x channel 24. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL25 * @brief Alias name for ESM group x channel 25 * * This is an alias name for the ESM group x channel 25. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL26 * @brief Alias name for ESM group x channel 26 * * This is an alias name for the ESM group x channel 26. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL27 * @brief Alias name for ESM group x channel 27 * * This is an alias name for the ESM group x channel 27. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL28 * @brief Alias name for ESM group x channel 28 * * This is an alias name for the ESM group x channel 28. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL29 * @brief Alias name for ESM group x channel 29 * * This is an alias name for the ESM group x channel 29. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL30 * @brief Alias name for ESM group x channel 30 * * This is an alias name for the ESM group x channel 30. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL31 * @brief Alias name for ESM group x channel 31 * * This is an alias name for the ESM group x channel 31. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL32 * @brief Alias name for ESM group x channel 32 * * This is an alias name for the ESM group x channel 32. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL33 * @brief Alias name for ESM group x channel 33 * * This is an alias name for the ESM group x channel 33. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL34 * @brief Alias name for ESM group x channel 34 * * This is an alias name for the ESM group x channel 34. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL35 * @brief Alias name for ESM group x channel 35 * * This is an alias name for the ESM group x channel 35. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL36 * @brief Alias name for ESM group x channel 36 * * This is an alias name for the ESM group x channel 36. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL37 * @brief Alias name for ESM group x channel 37 * * This is an alias name for the ESM group x channel 37. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL38 * @brief Alias name for ESM group x channel 38 * * This is an alias name for the ESM group x channel 38. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL39 * @brief Alias name for ESM group x channel 39 * * This is an alias name for the ESM group x channel 39. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL40 * @brief Alias name for ESM group x channel 40 * * This is an alias name for the ESM group x channel 40. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL41 * @brief Alias name for ESM group x channel 41 * * This is an alias name for the ESM group x channel 41. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL42 * @brief Alias name for ESM group x channel 42 * * This is an alias name for the ESM group x channel 42. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL43 * @brief Alias name for ESM group x channel 43 * * This is an alias name for the ESM group x channel 43. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL44 * @brief Alias name for ESM group x channel 44 * * This is an alias name for the ESM group x channel 44. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL45 * @brief Alias name for ESM group x channel 45 * * This is an alias name for the ESM group x channel 45. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL46 * @brief Alias name for ESM group x channel 46 * * This is an alias name for the ESM group x channel 46. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL47 * @brief Alias name for ESM group x channel 47 * * This is an alias name for the ESM group x channel 47. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL48 * @brief Alias name for ESM group x channel 48 * * This is an alias name for the ESM group x channel 48. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL49 * @brief Alias name for ESM group x channel 49 * * This is an alias name for the ESM group x channel 49. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL50 * @brief Alias name for ESM group x channel 50 * * This is an alias name for the ESM group x channel 50. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL51 * @brief Alias name for ESM group x channel 51 * * This is an alias name for the ESM group x channel 51. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL52 * @brief Alias name for ESM group x channel 52 * * This is an alias name for the ESM group x channel 52. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL53 * @brief Alias name for ESM group x channel 53 * * This is an alias name for the ESM group x channel 53. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL54 * @brief Alias name for ESM group x channel 54 * * This is an alias name for the ESM group x channel 54. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL55 * @brief Alias name for ESM group x channel 55 * * This is an alias name for the ESM group x channel 55. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL56 * @brief Alias name for ESM group x channel 56 * * This is an alias name for the ESM group x channel 56. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL57 * @brief Alias name for ESM group x channel 57 * * This is an alias name for the ESM group x channel 57. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL58 * @brief Alias name for ESM group x channel 58 * * This is an alias name for the ESM group x channel 58. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL59 * @brief Alias name for ESM group x channel 59 * * This is an alias name for the ESM group x channel 59. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL60 * @brief Alias name for ESM group x channel 60 * * This is an alias name for the ESM group x channel 60. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL61 * @brief Alias name for ESM group x channel 61 * * This is an alias name for the ESM group x channel 61. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL62 * @brief Alias name for ESM group x channel 62 * * This is an alias name for the ESM group x channel 62. * * @note This value should be used for API argument @a channel */ /** @def esmCHANNEL63 * @brief Alias name for ESM group x channel 63 * * This is an alias name for the ESM group x channel 63. * * @note This value should be used for API argument @a channel */ /** @typedef esmSelfTestFlag_t * @brief ESM Self-Test Status Type Definition * * This type is used to represent ESM Self-Test Status. */ typedef enum esmSelfTestFlag { esmSelfTest_Passed = 0U, esmSelfTest_Active = 1U, esmSelfTest_NotStarted = 2U, esmSelfTest_Failed = 3U }esmSelfTestFlag_t; /* Configuration registers */ typedef struct esm_config_reg { uint32 CONFIG_EEPAPR1; uint32 CONFIG_IESR1; uint32 CONFIG_ILSR1; uint32 CONFIG_LTCPR; uint32 CONFIG_EKR; uint32 CONFIG_IEPSR4; uint32 CONFIG_IESR4; uint32 CONFIG_ILSR4; } esm_config_reg_t; /* Configuration registers initial value */ /* USER CODE BEGIN (1) */ /* USER CODE END */ /** * @defgroup ESM ESM * @brief Error Signaling Module. * * The ESM module aggregates device errors and provides internal and external error response based on error severity. * * Related Files * - reg_esm.h * - esm.h * - esm.c * @addtogroup ESM * @{ */ /* Esm Interface Functions */ void esmInit(void); uint32 esmError(void); void esmEnableError(uint64 channels); void esmDisableError(uint64 channels); void esmTriggerErrorPinReset(void); void esmActivateNormalOperation(void); void esmEnableInterrupt(uint64 channels); void esmDisableInterrupt(uint64 channels); void esmSetInterruptLevel(uint64 channels, uint64 flags); void esmClearStatus(uint32 group, uint64 channels); void esmClearStatusBuffer(uint64 channels); void esmSetCounterPreloadValue(uint32 value); uint64 esmGetStatus(uint32 group, uint64 channels); uint64 esmGetStatusBuffer(uint64 channels); esmSelfTestFlag_t esmEnterSelfTest(void); esmSelfTestFlag_t esmSelfTestStatus(void); void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type); /** @fn void esmGroup1Notification(uint32 channel) * @brief Interrupt callback * @param[in] channel - Group 1 channel * * This is a callback that is provided by the application and is called upon * an interrupt. The parameter passed to the callback is group 1 channel caused the interrupt. * @note Callback parameter channel is not a masked value. Do not use the macros esmCHANNELx for comparison. */ void esmGroup1Notification(uint32 channel); /** @fn void esmGroup2Notification(uint32 channel) * @brief Interrupt callback * @param[in] channel - Group 2 channel * * This is a callback that is provided by the application and is called upon * an interrupt. The parameter passed to the callback is group 2 channel caused the interrupt. * @note Callback parameter channel is not a masked value. Do not use the macros esmCHANNELx for comparison. */ void esmGroup2Notification(uint32 channel); /**@}*/ /* USER CODE BEGIN (2) */ /* USER CODE END */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /** @enum pbistPort * @brief Alias names for pbist Port number * * This enumeration is used to provide alias names for the pbist Port number * - PBIST_PORT0 * - PBIST_PORT1 * * @note Check the datasheet for the port avaiability */ enum pbistPort { PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */ PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */ }; /** @enum pbistAlgo * @brief Alias names for pbist Algorithm * * This enumeration is used to provide alias names for the pbist Algorithm */ enum pbistAlgo { PBIST_TripleReadSlow = 0x00000001U, /** "Functions from library" */ extern void __TI_auto_init(void); /*SAFETYMCUSW 354 S MR:NA " Startup code(main should be declared by the user)" */ extern int main(void); /*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be present)" */ /*SAFETYMCUSW 354 S MR:NA " Startup code(Extern declaration present in the library)" */ extern void exit(int _status); /* USER CODE BEGIN (3) */ asm ( " REQUIRE update1" " DC32 g_ulUpdateStatusAddr" " DC32 0x8001500" " DC32 0x5c1e4ba3" " DC32 0x801fffc" ); /* USER CODE END */ void handlePLLLockFail(void); /* Startup Routine */ void _c_int00(void); /* USER CODE BEGIN (4) */ /* USER CODE END */ #pragma CODE_STATE(_c_int00, 32) #pragma INTERRUPT(_c_int00, RESET) #pragma WEAK(_c_int00) /* SourceId : STARTUP_SourceId_001 */ /* DesignId : STARTUP_DesignId_001 */ /* Requirements : HL_SR508 */ void _c_int00(void) { /* USER CODE BEGIN (5) */ register uint32_t update1_save; register uint32_t update2_save; /* USER CODE END */ /* Initialize Core Registers to avoid CCM Error */ _coreInitRegisters_(); /* USER CODE BEGIN (6) */ /* USER CODE END */ /* Initialize Stack Pointers */ _coreInitStackPointer_(); /* USER CODE BEGIN (7) */ /* USER CODE END */ /* Work Around for Errata DEVICE#140: ( Only on Rev A silicon) * * Errata Description: * The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on * Workaround: * Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */ if ((*(volatile uint32 *)0xFFFFFFF0U) == 0x802AAD05U) { _esmCcmErrorsClear_(); } /* USER CODE BEGIN (8) */ /* USER CODE END */ /* Enable CPU Event Export */ /* This allows the CPU to signal any single-bit or double-bit errors detected * by its ECC logic for accesses to program flash or data RAM. */ _coreEnableEventBusExport_(); /* USER CODE BEGIN (11) */ /* USER CODE END */ /* Workaround for Errata CORTEXR4 66 */ _errata_CORTEXR4_66_(); /* Workaround for Errata CORTEXR4 57 */ _errata_CORTEXR4_57_(); /* Reset handler: the following instructions read from the system exception status register * to identify the cause of the CPU reset. */ /* check for power-on reset condition */ /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ if (((*(volatile uint32 *)0xFFFFFFE4U) & 0x8000U) != 0U) { /* USER CODE BEGIN (12) */ /* USER CODE END */ /* Add condition to check whether PLL can be started successfully */ if (_errata_SSWF021_45_both_plls(5U) != 0U) { /* Put system in a safe state */ handlePLLLockFail(); } /* clear all reset status flags */ (*(volatile uint32 *)0xFFFFFFE4U) = 0xFFFFU; /* USER CODE BEGIN (13) */ /* USER CODE END */ /* USER CODE BEGIN (14) */ /* USER CODE END */ /* USER CODE BEGIN (15) */ /* USER CODE END */ /* continue with normal start-up sequence */ } /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ else if (((*(volatile uint32 *)0xFFFFFFE4U) & 0x4000U) != 0U) { /* Reset caused due to oscillator failure. Add user code here to handle oscillator failure */ /* USER CODE BEGIN (16) */ /* USER CODE END */ } /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ else if (((*(volatile uint32 *)0xFFFFFFE4U) & 0x2000U) !=0U) { /* Reset caused due * 1) windowed watchdog violation - Add user code here to handle watchdog violation. * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS */ /* Check the WatchDog Status register */ if((*(volatile uint32 *)0xFFFFFC98U) != 0U) { /* Add user code here to handle watchdog violation. */ /* USER CODE BEGIN (17) */ /* USER CODE END */ /* Clear the Watchdog reset flag in Exception Status register */ (*(volatile uint32 *)0xFFFFFFE4U) = 0x2000U; /* USER CODE BEGIN (18) */ /* USER CODE END */ } else { /* Clear the ICEPICK reset flag in Exception Status register */ (*(volatile uint32 *)0xFFFFFFE4U) = 0x2000U; /* USER CODE BEGIN (19) */ /* USER CODE END */ } } /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ else if (((*(volatile uint32 *)0xFFFFFFE4U) & 0x0020U) !=0U) { /* Reset caused due to CPU reset. CPU reset can be caused by CPU self-test completion, or by toggling the "CPU RESET" bit of the CPU Reset Control Register. */ /* USER CODE BEGIN (20) */ /* USER CODE END */ /* clear all reset status flags */ (*(volatile uint32 *)0xFFFFFFE4U) = 0x0020U; /* USER CODE BEGIN (21) */ /* USER CODE END */ } /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ else if (((*(volatile uint32 *)0xFFFFFFE4U) & 0x0010U) != 0U) { /* Reset caused due to software reset. Add user code to handle software reset. */ /* USER CODE BEGIN (22) */ /* USER CODE END */ } else { /* Reset caused by nRST being driven low externally. Add user code to handle external reset. */ /* USER CODE BEGIN (23) */ /* USER CODE END */ } /* Check if there were ESM group3 errors during power-up. * These could occur during eFuse auto-load or during reads from flash OTP * during power-up. Device operation is not reliable and not recommended * in this case. * An ESM group3 error only drives the nERROR pin low. An external circuit * that monitors the nERROR pin must take the appropriate action to ensure that * the system is placed in a safe state, as determined by the application. */ if ((((esmBASE_t *)0xFFFFF500U)->SR1[2]) != 0U) { /* USER CODE BEGIN (24) */ /* USER CODE END */ /*SAFETYMCUSW 5 C MR:NA "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 26 S MR:NA "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 28 D MR:NA "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ for(;;) { }/* Wait */ /* USER CODE BEGIN (25) */ /* USER CODE END */ } /* USER CODE BEGIN (26) */ /* USER CODE END */ /* Initialize System - Clock, Flash settings with Efuse self check */ systemInit(); /* Workaround for Errata PBIST#4 */ errata_PBIST_4(); /* Run PBIST on STC ROM */ pbistRun((uint32)2U, ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast)); /* Wait for PBIST for STC ROM to be completed */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while(pbistIsTestCompleted() != 1) { }/* Wait */ /* Check if PBIST on STC ROM passed the self-test */ if( pbistIsTestPassed() != 1) { /* PBIST and STC ROM failed the self-test. * Need custom handler to check the memory failure * and to take the appropriate next step. */ pbistFail(); } /* Disable PBIST clocks and disable memory self-test mode */ pbistStop(); /* Run PBIST on PBIST ROM */ pbistRun((uint32)1U, ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast)); /* Wait for PBIST for PBIST ROM to be completed */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while(pbistIsTestCompleted() != 1) { }/* Wait */ /* Check if PBIST ROM passed the self-test */ if( pbistIsTestPassed() != 1) { /* PBIST and STC ROM failed the self-test. * Need custom handler to check the memory failure * and to take the appropriate next step. */ pbistFail(); } /* Disable PBIST clocks and disable memory self-test mode */ pbistStop(); /* USER CODE BEGIN (29) */ /* USER CODE END */ /* USER CODE BEGIN (31) */ /* USER CODE END */ /* USER CODE BEGIN (37) */ update1_save = update1; update2_save = update2; // asm ( "LDR R3,ref_table+0x00" ); // asm ( "LDR R4, [R3, #0]" ); // asm ( "LDR R3,ref_table+0x04" ); // asm ( "LDR R5, [R3, #0]" ); /* USER CODE END */ /* Initialize CPU RAM. * This function uses the system module's hardware for auto-initialization of memories and their * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. * Hence the value 0x1 passed to the function. * This function will initialize the entire CPU RAM and the corresponding ECC locations. */ memoryInit(0x1U); /* USER CODE BEGIN (38) */ update1 = update1_save; update2 = update2_save; // asm ( "STR R5,[R3, #0]" ); // asm ( "LDR R3,ref_table+0x00" ); // asm ( "STR R4,[R3, #0]" ); /* USER CODE END */ /* Enable ECC checking for TCRAM accesses. * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. */ _coreEnableRamEcc_(); /* USER CODE BEGIN (39) */ /* USER CODE END */ /* USER CODE BEGIN (55) */ /* USER CODE END */ /* USER CODE BEGIN (68) */ /* USER CODE END */ /* USER CODE BEGIN (72) */ /* USER CODE END */ /* Enable IRQ offset via Vic controller */ _coreEnableIrqVicOffset_(); /* USER CODE BEGIN (73) */ /* USER CODE END */ /* Initialize VIM table */ vimInit(); /* USER CODE BEGIN (74) */ /* USER CODE END */ /* Configure system response to error conditions signaled to the ESM group1 */ /* This function can be configured from the ESM tab of HALCoGen */ esmInit(); /* initialize copy table */ __TI_auto_init(); /* USER CODE BEGIN (75) */ /* USER CODE END */ /* call the application */ /*SAFETYMCUSW 296 S MR:8.6 "Startup code(library functions at block scope)" */ /*SAFETYMCUSW 326 S MR:8.2 "Startup code(Declaration for main in library)" */ /*SAFETYMCUSW 60 D MR:8.8 "Startup code(Declaration for main in library;Only doing an extern for the same)" */ main(); /* USER CODE BEGIN (76) */ /* USER CODE END */ /*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be present)" */ exit(0); /* USER CODE BEGIN (77) */ /* USER CODE END */ } /* USER CODE BEGIN (78) */ const uint32 ref_table[2] = { (uint32)&update1, (uint32)&update2 }; /* USER CODE END */ /** @fn void handlePLLLockFail(void) * @brief This function handles PLL lock fail. */ void handlePLLLockFail(void) { /* USER CODE BEGIN (79) */ /* USER CODE END */ while(1) { } /* USER CODE BEGIN (80) */ /* USER CODE END */ } /* USER CODE BEGIN (81) */ /* USER CODE END */