TI ARM Assembler PC v5.2.4 Tue Oct 15 10:23:08 2024

Tools Copyright (c) 1996-2015 Texas Instruments Incorporated
C:/Users/a0500955/TI Drive/HVC_MP_Projects/HPCS Firmware/firmware_training/ucd_min-pmbus/Device/UCD3138128/Source/load_UCD3138_128.asm PAGE    1

       1                    ;
       2                    ;  Copyright 2001 by Texas Instruments Incorporated.
       3                    ;  All rights reserved. Property of Texas Instruments Incorporated.
       4                    ;  Restricted rights to use, duplicate or disclose this code are
       5                    ;  granted through contract.
       6                    ;  U.S. Patent Nos. 5,283,900  5,392,448
       7                    ;
       8                    ;  ======== load.asm ========
       9                    ;
      10                    ;  C-callable interface to assembly language utility functions for the
      11                    ;  volume example.
      12                    
      13          0006BFFC  SUP_STACK_TOP   .equ    0x6bffc ;Supervisor mode (SWI stack) starts at top of memory
      14          0006BE00  FIQ_STACK_TOP   .equ    0x6be00 ;allocate 256 bytes to supervisor stack, then do FIQ stack
      15          0006BD00  IRQ_STACK_TOP   .equ    0x6bd00 ;allocate 256 bytes to fiq stack, then start irq stack
      16          0006BB00  USER_STACK_TOP  .equ    0x6bb00 ;Allocate 512 bytes to irq stack, regular stack gets rest, down to var
      17                                    .global _c_int00
      18                                    .global $c_int00
      19                                    .global $main
      20                                    .global _undefined_instruction_exception
      21                                    .global _software_interrupt
      22                                    .global _abort_prefetch_exception
      23                                    .global _abort_data_fetch_exception
      24                                    .global _reserved_exception
      25                                    .global _standard_interrupt
      26                                    .global _fast_interrupt
      27                                    .global cinit
      28                                    .global rom_main
      29          FFFFA4DC  rom_main .equ 0xffffa4dc
      30 00000000                           .sect ".vectors"
      31 00000000                           .state32
      32 00000000 EAFFFFFE!                 B       c_int00 
      33 00000004 EAFFFFFD!                 B       _undefined_instruction_exception
      34 00000008 EAFFFFFC!                 B       _software_interrupt
      35 0000000c EAFFFFFB!                 B       _abort_prefetch_exception
      36 00000010 EAFFFFFA!                 B       _abort_data_fetch_exception
      37 00000014 EAFFFFF9!                 B       _abort_prefetch_exception
      38 00000018 EAFFFFF8!                 B       _standard_interrupt
      39 0000001c EAFFFFF7!                 B       _fast_interrupt
      40                                    .align  4
      41 00000000                           .sect ".text"
      42 00000000                           .state32
      43 00000000           c_int00
      44                    ;               B       c_int00 
      45 00000000 E59FD0AC                  LDR             r13, c_sup_stack_top ; initialize supervisor stack pointer
      46                    ;               LDR             r4,c_mfbalr1_half0 ;point r4 at program flash base address register
      47                    ;               MOV             r0,#0x62 ;make block size 32K, address 0, read only
      48                    ;               STRH    r0,[r4]; store it there
      49                    ;               LDR             r0,c_mfbalr2_half0_load ;set up data flash for write only
      50                    ;               STRH    r0,[r4,#8] ;put it into mfbalr2
      51                                    
      52                    ;*------------------------------------------------------
      53                    ;* SET TO FIQ MODE, init FIQ stack
      54                    ;*------------------------------------------------------
      55 00000004 E10F0000          MRS     r0, cpsr
TI ARM Assembler PC v5.2.4 Tue Oct 15 10:23:08 2024

Tools Copyright (c) 1996-2015 Texas Instruments Incorporated
C:/Users/a0500955/TI Drive/HVC_MP_Projects/HPCS Firmware/firmware_training/ucd_min-pmbus/Device/UCD3138128/Source/load_UCD3138_128.asm PAGE    2

      56 00000008 E3C0001F          BIC     r0, r0, #0x1F  ; CLEAR MODES
      57 0000000c E3800011          ORR     r0, r0, #0x11  ; SET FIQ MODE
      58 00000010 E129F000          MSR     cpsr_cf, r0;
      59                    
      60 00000014 E59FD090                  LDR             R13, c_fiq_stack_top ; initialize stack pointer
      61                    
      62                    ;*------------------------------------------------------
      63                    ;* SET TO IRQ MODE, init IRQ stack
      64                    ;*------------------------------------------------------
      65 00000018 E10F0000          MRS     r0, cpsr
      66 0000001c E3C0001F          BIC     r0, r0, #0x1F  ; CLEAR MODES
      67 00000020 E3800012          ORR     r0, r0, #0x12  ; SET IRQ MODE
      68 00000024 E129F000          MSR     cpsr_cf, r0
      69                    
      70 00000028 E59FD080                  LDR             R13, c_irq_stack_top ; initialize stack pointer
      71                    
      72                    ;*------------------------------------------------------
      73                    ;* SET TO USER MODE, init user stack
      74                    ;*------------------------------------------------------
      75 0000002c E10F0000          MRS     r0, cpsr
      76 00000030 E3C0001F          BIC     r0, r0, #0x1F  ; CLEAR MODES
      77 00000034 E3800010          ORR     r0, r0, #0x10  ; SET USER MODE
      78 00000038 E129F000          MSR     cpsr_cf, r0
      79                    
      80 0000003c E59FD074                  ldr     R13, c_user_stack_top ; initialize stack pointer
      81 00000040           LOOPY
      82                    ;               B       LOOPY
      83                    ;               B       _c_int00
      84                    
      85                    ;*------------------------------------------------------
      86                    ;* CHANGE TO 16 BIT STATE
      87                    ;*------------------------------------------------------
      88 00000040 E28F0001                  ADD     r0, pc, #1
      89 00000044 E12FFF10                  BX      r0
      90                    
      91 00000048                   .state16
      92                    
      93                    ;*----------------
      94                    ;Clear RAM
      95                    ;-------------------------              
      96 00000048 2200              MOV       A3, #0     ;zero to store in RAM
      97                    ;
      98 0000004a 2001             MOV       A1, #1 ;loop counter
      99 0000004c 02C0              LSL       A1, A1, #11  ;set to 2** 11 = 2048 words = 8192 bytes - all of RAM
     100                    ;
     101 0000004e 216A              MOV       A2, #106      ;point at 0x6a000 - start of RAM
     102 00000050 0309              LSL       A2, A2, #12
     103 00000052           RAM_CLEAR_LOOP:    
     104 00000052 600A              STR       A3, [A2, #0]          ; clear location 
     105 00000054 3104              ADD       A2, #4                ; point to next word 
     106 00000056 3801              SUB       A1, #1                ; decrement loop counter 
     107 00000058 D1FB              BQNE      RAM_CLEAR_LOOP        ; loop until counter is zero 
     108                    ;*------------------------------------------------------
     109                    ;* PERFORM AUTO-INITIALIZATION.  IF CINIT IS -1, THEN
     110                    ;* THERE IS NONE.
TI ARM Assembler PC v5.2.4 Tue Oct 15 10:23:08 2024

Tools Copyright (c) 1996-2015 Texas Instruments Incorporated
C:/Users/a0500955/TI Drive/HVC_MP_Projects/HPCS Firmware/firmware_training/ucd_min-pmbus/Device/UCD3138128/Source/load_UCD3138_128.asm PAGE    3

     111                    ;*------------------------------------------------------
     112                    ;               BL      $c_int00
     113                    ;               BL      $c_int00
     114 0000005a 4813              LDR     r0, c_cinit
     115 0000005c 2701              MOV     r7, #1 
     116 0000005e 42F8              CMN     r0, r7
     117 00000060 D020              BEQ     _c1_
     118                    ;
     119                    ;initialize variables
     120                    ;
     121                    ;***************************************************************************
     122                    ;*  PROCESS INITIALIZATION TABLE.
     123                    ;*
     124                    ;*  THE TABLE CONSISTS OF A SEQUENCE OF RECORDS OF THE FOLLOWING FORMAT:
     125                    ;*                                                                          
     126                    ;*       .word  <length of data (bytes)>
     127                    ;*       .word  <address of variable to initialize>                         
     128                    ;*       .word  <data>
     129                    ;*                                                                          
     130                    ;*  THE INITIALIZATION TABLE IS TERMINATED WITH A ZERO LENGTH RECORD.
     131                    ;*                                                                          
     132                    ;***************************************************************************
     133                    
     134          00000000  tbl_addr  .set    r0
     135          00000001  var_addr  .set    r1
     136          00000002  tmp       .set    r2
     137          00000003  length:   .set    r3
     138          00000004  data:     .set    r4
     139          00000005  three:    .set    r5
     140                    
     141 00000062 2503              MOV     three, #3                  ;
     142 00000064 E01B              B       rec_chk                    ;
     143                    
     144                            ;*------------------------------------------------------
     145                            ;* PROCESS AN INITIALIZATION RECORD
     146                            ;*------------------------------------------------------
     147 00000066 6841      record: LDR     var_addr, [tbl_addr, #4]   ;
     148 00000068 3008              ADD     tbl_addr, #8               ;
     149                    
     150                            ;*------------------------------------------------------
     151                            ;* COPY THE INITIALIZATION DATA
     152                            ;*------------------------------------------------------
     153 0000006a 1C0A              MOV     tmp, var_addr              ; DETERMINE ALIGNMENT
     154 0000006c 402A              AND     tmp, three                 ; AND COPY BYTE BY BYTE
     155 0000006e D10B              BNE     _bcopy                     ; IF NOT WORD ALIGNED
     156                    
     157 00000070 1C1A              MOV     tmp, length                ; FOR WORD COPY, STRIP
     158 00000072 402A              AND     tmp, three                 ; OUT THE NONWORD PART
     159 00000074 43AB              BIC     length, three              ; OF THE LENGTH
     160 00000076 D005              BEQ     _wcont                     ;            
     161                    
     162 00000078 6804      _wcopy: LDR     data, [tbl_addr]           ;
     163 0000007a 3004              ADD     tbl_addr, #4               ;
     164 0000007c 600C              STR     data, [var_addr]           ; COPY A WORD OF DATA
     165 0000007e 3104              ADD     var_addr, #4               ;
TI ARM Assembler PC v5.2.4 Tue Oct 15 10:23:08 2024

Tools Copyright (c) 1996-2015 Texas Instruments Incorporated
C:/Users/a0500955/TI Drive/HVC_MP_Projects/HPCS Firmware/firmware_training/ucd_min-pmbus/Device/UCD3138128/Source/load_UCD3138_128.asm PAGE    4

     166 00000080 3B04              SUB     length, #4                 ;
     167 00000082 D1F9              BNE     _wcopy                     ;
     168 00000084 1C13      _wcont: MOV     length, tmp                ;
     169 00000086 D005              BEQ     _cont                      ;
     170                    
     171 00000088 7804      _bcopy: LDRB    data, [tbl_addr]           ;
     172 0000008a 3001              ADD     tbl_addr, #1               ;
     173 0000008c 700C              STRB    data, [var_addr]           ; COPY A BYTE OF DATA
     174 0000008e 3101              ADD     var_addr, #1               ;
     175 00000090 3B01              SUB     length, #1                 ;
     176 00000092 D1F9              BNE     _bcopy                     ;
     177                    
     178 00000094 1C02      _cont:  MOV     tmp, tbl_addr              ;
     179 00000096 402A              AND     tmp, three                 ; MAKE SURE THE ADDRESS
     180 00000098 D001              BEQ     rec_chk                    ; IS WORD ALIGNED
     181 0000009a 43A8              BIC     tbl_addr, three            ;
     182 0000009c 3004              ADD     tbl_addr, #0x4             ;
     183                    
     184 0000009e 6803      rec_chk:LDR     length, [tbl_addr]         ; PROCESS NEXT
     185 000000a0 2B00              CMP     length, #0                 ; RECORD IF LENGTH IS
     186 000000a2 D1E0              BNE     record                     ; NONZERO 
     187                    
     188                    
     189                            ;*------------------------------------------------------
     190                            ;* CALL INITIALIZATION ROUTINES FOR CONSTRUCTORS. IF
     191                            ;* PINIT IS -1, THEN THERE ARE NONE.
     192                            ;* NOTE THAT r7 IS PRESERVED ACROSS AUTO-INITIALIZATION.
     193                            ;*------------------------------------------------------
     194 000000a4           _c1_:   
     195 000000a4 F7FF!                     BL      _c_int00
         000000a6 FFAC     
     196                                    .align 4                                        
     197 000000a8 00000000! c_cinit .long    cinit
     198 000000ac 0006BE00  c_fiq_stack_top .long FIQ_STACK_TOP
     199 000000b0 0006BD00  c_irq_stack_top .long IRQ_STACK_TOP
     200 000000b4 0006BFFC  c_sup_stack_top .long SUP_STACK_TOP
     201 000000b8 0006BB00  c_user_stack_top .long USER_STACK_TOP
     202 000000bc FFFFFE0E  c_mfbalr1_half0 .long 0xFFFFFE0E ;low 16 bits of memory fine bank address low
     203                    ;c_mfbalr2_half0_load .long     0x9822 ;data flash base address 8800, block size 2K, read only
     204 00000000                           .sect ".dflash"
     205                                    .end

No Assembly Errors, No Assembly Warnings
