diff --git a/examples/drivers/boot/sbl_ospi/am261x-som/r5fss0-0_nortos/main.c b/examples/drivers/boot/sbl_ospi/am261x-som/r5fss0-0_nortos/main.c
index 0c86ab6..dc22ced 100644
--- a/examples/drivers/boot/sbl_ospi/am261x-som/r5fss0-0_nortos/main.c
+++ b/examples/drivers/boot/sbl_ospi/am261x-som/r5fss0-0_nortos/main.c
@@ -79,9 +79,12 @@ __attribute__((weak)) int32_t Keyring_init(HsmClient_t *gHSMClient)
     return SystemP_SUCCESS;
 }
 
+extern uint32_t gR5ClockFrequency;
+
 int main(void)
 {
     int32_t status;
+    gR5ClockFrequency = SOC_RCM_R5_FREQ_200MHZ;
     Bootloader_profileReset();
     Bootloader_socConfigurePll();
     Bootloader_socSetAutoClock();
diff --git a/source/drivers/bootloader/soc/am261x/bootloader_soc.c b/source/drivers/bootloader/soc/am261x/bootloader_soc.c
index 49f04da..ef161c2 100644
--- a/source/drivers/bootloader/soc/am261x/bootloader_soc.c
+++ b/source/drivers/bootloader/soc/am261x/bootloader_soc.c
@@ -60,6 +60,19 @@ Bootloader_resMemSections gResMemSection =
     .memSection[0].memEnd     = 0x70040000,
 };
 
+Bootloader_CoreBootInfo gCoreBootInfo200Mhz[]                                                                             =
+{
+    {
+        .defaultClockHz = (uint32_t)(200*1000000),
+        .coreName       = "r5f0-0",
+    },
+
+    {
+        .defaultClockHz = (uint32_t)(200*1000000),
+        .coreName       = "r5f0-1",
+    },
+};
+
 Bootloader_CoreBootInfo gCoreBootInfo400Mhz[]                                                                             =
 {
     {
@@ -167,6 +180,10 @@ uint32_t Bootloader_socCpuGetClkDefault(uint32_t cpuId)
         {
             defClock = gCoreBootInfo400Mhz[cpuId].defaultClockHz;
         }
+        else if(gR5ClockFrequency == SOC_RCM_R5_FREQ_200MHZ)
+        {
+            defClock = gCoreBootInfo200Mhz[cpuId].defaultClockHz;
+        }
         else
         {
             defClock = gCoreBootInfo500Mhz[cpuId].defaultClockHz;
@@ -231,7 +248,14 @@ int32_t Bootloader_socCpuSetClock(uint32_t cpuId, uint32_t cpuHz)
     {
         case CSL_CORE_ID_R5FSS0_0:
         case CSL_CORE_ID_R5FSS0_1:
-            status = SOC_rcmSetR5Clock(cpuHz, cpuHz/2, cpuId);
+            if(gR5ClockFrequency == SOC_RCM_R5_FREQ_200MHZ)
+            {
+                status = SOC_rcmSetR5Clock(cpuHz, cpuHz, cpuId);
+            }
+            else
+            {
+                status = SOC_rcmSetR5Clock(cpuHz, cpuHz/2, cpuId);
+            }
             break;
     }
     return status;
@@ -398,6 +422,29 @@ void Bootloader_socConfigurePll(void)
         hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(120U);
         SOC_rcmPerApllConfig(RCM_PLL_FOUT_FREQID_CLK_960MHZ, &hsDivCfg);
     }
+    else if (gR5ClockFrequency == SOC_RCM_R5_FREQ_200MHZ)
+    {
+        hsDivCfg.hsdivOutEnMask = RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL;
+        hsDivCfg.hsDivOutFreqHz[0] = SOC_RCM_FREQ_MHZ2HZ(200U);
+        hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(500U);
+        hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(400U);
+        hsDivCfg.hsDivOutFreqHz[3] = SOC_RCM_FREQ_MHZ2HZ(166U);
+        SOC_rcmCoreApllConfig(RCM_PLL_FOUT_FREQID_CLK_2000MHZ, &hsDivCfg);
+
+        hsDivCfg.hsdivOutEnMask = RCM_PLL_HSDIV_OUTPUT_ENABLE_0 |
+                                 RCM_PLL_HSDIV_OUTPUT_ENABLE_2;
+        hsDivCfg.hsDivOutFreqHz[0] = SOC_RCM_FREQ_MHZ2HZ(450U);
+        hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(150U);
+        SOC_rcmEthApllConfig(RCM_PLL_FOUT_FREQID_CLK_900MHZ, &hsDivCfg);
+
+        hsDivCfg.hsdivOutEnMask = (RCM_PLL_HSDIV_OUTPUT_ENABLE_0 |
+                                RCM_PLL_HSDIV_OUTPUT_ENABLE_2 |
+                                RCM_PLL_HSDIV_OUTPUT_ENABLE_3);
+        hsDivCfg.hsDivOutFreqHz[0] = SOC_RCM_FREQ_MHZ2HZ(192U);
+        hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(160U);
+        hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(120U);
+        SOC_rcmPerApllConfig(RCM_PLL_FOUT_FREQID_CLK_960MHZ, &hsDivCfg);
+    }
     else
     {
         hsDivCfg.hsdivOutEnMask = RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL;
@@ -487,6 +534,10 @@ void Bootloader_socSetAutoClock()
         {
             Bootloader_socCpuSetClock(CSL_CORE_ID_R5FSS0_0, (uint32_t)(400*1000000));
         }
+        else if(gR5ClockFrequency == SOC_RCM_R5_FREQ_200MHZ)
+        {
+            Bootloader_socCpuSetClock(CSL_CORE_ID_R5FSS0_0, (uint32_t)(200*1000000));
+        }
         else
         {
             Bootloader_socCpuSetClock(CSL_CORE_ID_R5FSS0_0, (uint32_t)(500*1000000));
diff --git a/source/drivers/soc/am261x/soc_rcm.c b/source/drivers/soc/am261x/soc_rcm.c
index 3c5c611..01956af 100644
--- a/source/drivers/soc/am261x/soc_rcm.c
+++ b/source/drivers/soc/am261x/soc_rcm.c
@@ -194,7 +194,7 @@ const SOC_RcmClkSrcInfo gPeripheralClkSrcInfoMap[] =
 const SOC_RcmClkSrcInfo gCR5ClkSrcInfoMap =
 {
     .pllId = RCM_PLLID_CORE,
-    .hsDivOut = RCM_PLLHSDIV_OUT_2,
+    .hsDivOut = RCM_PLLHSDIV_OUT_0,
 };
 
 const SOC_RcmClkSrcInfo gTraceClkSrcInfoMap =
diff --git a/source/drivers/soc/am261x/soc_rcm.h b/source/drivers/soc/am261x/soc_rcm.h
index 018b8f9..af134b7 100644
--- a/source/drivers/soc/am261x/soc_rcm.h
+++ b/source/drivers/soc/am261x/soc_rcm.h
@@ -56,6 +56,7 @@ extern "C"
 
 #define SOC_RCM_R5_FREQ_400MHZ          (0x0U)
 #define SOC_RCM_R5_FREQ_500MHZ          (0x1U)
+#define SOC_RCM_R5_FREQ_200MHZ          (0x2U)
 
 /**
  *  \anchor SOC_WarmResetCause_t