/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM62Px" --part "Default" --package "AMH" --product "Processor_DDR_Config@0.10.32"
 * @v2CliArgs --device "AM62P" --package "FCBGA (AMH)" --variant "AM62P54-M" --product "Processor_DDR_Config@0.10.32"
 * @versions {"tool":"1.23.0+4000"}
 */

/**
 * Import the modules used in this configuration.
 */
const DDRSS = scripting.addModule("/DDRSS");

/**
 * Write custom configuration values to the imported modules.
 */
DDRSS.lpddr4.$name                   = "sitara_lpddr4_DDRSS_LPDDR40";
DDRSS.lpddr4.system_cfg_dram_density = 4;
DDRSS.lpddr4.config_dram_tRFCab_ns   = 180;
DDRSS.lpddr4.config_dram_tRFCpb_ns   = 90;
DDRSS.lpddr4.system_cfg_temp_range   = "-40C to 105C";
DDRSS.lpddr4.system_cfg_dram_ranks   = 1;
DDRSS.lpddr4.config_dram_tCKE_tCK    = 3;
DDRSS.lpddr4.config_dram_tREFIpb_ns  = 488;
DDRSS.lpddr4.config_dram_tREFIab_ns  = 3904;
DDRSS.lpddr4.config_dram_DQ16        = "Memory DQ19";
DDRSS.lpddr4.config_dram_DQ0         = "Memory DQ6";
DDRSS.lpddr4.config_dram_DQ1         = "Memory DMI0";
DDRSS.lpddr4.config_dram_DQ2         = "Memory DQ1";
DDRSS.lpddr4.config_dram_DQ3         = "Memory DQ0";
DDRSS.lpddr4.config_dram_DQ4         = "Memory DQ7";
DDRSS.lpddr4.config_dram_DQ6         = "Memory DQ2";
DDRSS.lpddr4.config_dram_DQ7         = "Memory DQ3";
DDRSS.lpddr4.config_dram_DM0         = "Memory DQ4";
DDRSS.lpddr4.config_dram_DQ8         = "Memory DQ12";
DDRSS.lpddr4.config_dram_DQ9         = "Memory DMI1";
DDRSS.lpddr4.config_dram_DQ10        = "Memory DQ14";
DDRSS.lpddr4.config_dram_DQ11        = "Memory DQ8";
DDRSS.lpddr4.config_dram_DQ12        = "Memory DQ10";
DDRSS.lpddr4.config_dram_DQ14        = "Memory DQ15";
DDRSS.lpddr4.config_dram_DQ15        = "Memory DQ9";
DDRSS.lpddr4.config_dram_DM1         = "Memory DQ11";
DDRSS.lpddr4.config_dram_DQ17        = "Memory DQ18";
DDRSS.lpddr4.config_dram_DQ18        = "Memory DQ21";
DDRSS.lpddr4.config_dram_DQ19        = "Memory DQ20";
DDRSS.lpddr4.config_dram_DQ20        = "Memory DMI2";
DDRSS.lpddr4.config_dram_DQ21        = "Memory DQ22";
DDRSS.lpddr4.config_dram_DQ22        = "Memory DQ23";
DDRSS.lpddr4.config_dram_DQ23        = "Memory DQ16";
DDRSS.lpddr4.config_dram_DM2         = "Memory DQ17";
DDRSS.lpddr4.config_dram_DQ24        = "Memory DQ28";
DDRSS.lpddr4.config_dram_DQ25        = "Memory DQ27";
DDRSS.lpddr4.config_dram_DQ27        = "Memory DMI3";
DDRSS.lpddr4.config_dram_DQ28        = "Memory DQ29";
DDRSS.lpddr4.config_dram_DQ29        = "Memory DQ25";
DDRSS.lpddr4.config_dram_odtlon_FS2  = 6;
DDRSS.lpddr4.config_dram_odtloff_FS2 = 24;
DDRSS.lpddr4.config_dram_mr2_rl_FS2  = 14;