MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Starting ...

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Flash Manufacturer ID : 0x34

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Flash Device ID       : 0x2A1A

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Executing Flash Erase on first block...

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Erase Failed !!!

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Performing Write-Read Test...

MAIN_Cortex_R5_0_0: [OSPI Flash Diagnostic Test] Write-Read Test Passed!

MAIN_Cortex_R5_0_0: [QSPI Flash Diagnostic Test] SFDP Information : 

MAIN_Cortex_R5_0_0: ================================================

MAIN_Cortex_R5_0_0:                       SFDP                      

MAIN_Cortex_R5_0_0: ================================================

MAIN_Cortex_R5_0_0: SFDP Major Revision                       : 0x1

MAIN_Cortex_R5_0_0: SFDP Minor Revision                       : 0x8

MAIN_Cortex_R5_0_0: Number of Parameter Headers in this Table : 4

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0: Types of Additional Parameter Tables in this flash

MAIN_Cortex_R5_0_0: ---------------------------------------------------

MAIN_Cortex_R5_0_0: 4 BYTE ADDRESSING MODE INSTRUCTIONS TABLE

MAIN_Cortex_R5_0_0: SECTOR MAP TABLE

MAIN_Cortex_R5_0_0: STATUS CONTROL AND CONFIGURATION REGISTER MAP TABLE

MAIN_Cortex_R5_0_0: JSON Data for the flash :

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0: {

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0:     "flashSize": 67108864,

MAIN_Cortex_R5_0_0:     "flashPageSize": 256,

MAIN_Cortex_R5_0_0:     "flashManfId": "0x34",

MAIN_Cortex_R5_0_0:     "flashDeviceId": "0x2A1A",

MAIN_Cortex_R5_0_0:     "flashBlockSize": 262144,

MAIN_Cortex_R5_0_0:     "flashSectorSize": 4096,

MAIN_Cortex_R5_0_0:     "cmdBlockErase3B": "0xD8",

MAIN_Cortex_R5_0_0:     "cmdBlockErase4B": "0xDC",

MAIN_Cortex_R5_0_0:     "cmdSectorErase3B": "0x20",

MAIN_Cortex_R5_0_0:     "cmdSectorErase4B": "0x21",

MAIN_Cortex_R5_0_0:     "protos": {

MAIN_Cortex_R5_0_0:             "p111": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0x03",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 0,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p112": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0xFF",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 0,

MAIN_Cortex_R5_0_0:                     "enableType": "0",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p114": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0x6C",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 8,

MAIN_Cortex_R5_0_0:                     "enableType": "5",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x00",

MAIN_Cortex_R5_0_0:                     "dummyCfg": null,

MAIN_Cortex_R5_0_0:                     "protoCfg": null,

MAIN_Cortex_R5_0_0:                     "strDtrCfg": null

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p118": null,

MAIN_Cortex_R5_0_0:             "p444s": {

MAIN_Cortex_R5_0_0:                     "isDtr": false,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0xEB",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 2,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 8,

MAIN_Cortex_R5_0_0:                     "enableType": "5",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x08",

MAIN_Cortex_R5_0_0:                     "dummyCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": true,

MAIN_Cortex_R5_0_0:                             "cmdRegRd":"0x65",

MAIN_Cortex_R5_0_0:                             "cmdRegWr":"0x71",

MAIN_Cortex_R5_0_0:                             "cfgReg":"0x00800003",

MAIN_Cortex_R5_0_0:                             "shift":0,

MAIN_Cortex_R5_0_0:                             "mask":"0x03",

MAIN_Cortex_R5_0_0:                             "bitP":8

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "protoCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": true,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x65",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x71",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00800003",

MAIN_Cortex_R5_0_0:                             "shift": 6,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 6

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "strDtrCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00000000",

MAIN_Cortex_R5_0_0:                             "shift": 0,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 0

MAIN_Cortex_R5_0_0:                     }

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p444d": {

MAIN_Cortex_R5_0_0:                     "isDtr": true,

MAIN_Cortex_R5_0_0:                     "cmdRd": "0xEB",

MAIN_Cortex_R5_0_0:                     "cmdWr": "0x02",

MAIN_Cortex_R5_0_0:                     "modeClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "modeClksRd": 2,

MAIN_Cortex_R5_0_0:                     "dummyClksCmd": 0,

MAIN_Cortex_R5_0_0:                     "dummyClksRd": 8,

MAIN_Cortex_R5_0_0:                     "enableType": "5",

MAIN_Cortex_R5_0_0:                     "enableSeq": "0x08",

MAIN_Cortex_R5_0_0:                     "dummyCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": true,

MAIN_Cortex_R5_0_0:                             "cmdRegRd":"0x65",

MAIN_Cortex_R5_0_0:                             "cmdRegWr":"0x71",

MAIN_Cortex_R5_0_0:                             "cfgReg":"0x00800003",

MAIN_Cortex_R5_0_0:                             "shift":0,

MAIN_Cortex_R5_0_0:                             "mask":"0x03",

MAIN_Cortex_R5_0_0:                             "bitP":8

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "protoCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": true,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x65",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x71",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00800003",

MAIN_Cortex_R5_0_0:                             "shift": 6,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 6

MAIN_Cortex_R5_0_0:                     },

MAIN_Cortex_R5_0_0:                     "strDtrCfg": {

MAIN_Cortex_R5_0_0:                             "isAddrReg": false,

MAIN_Cortex_R5_0_0:                             "cmdRegRd": "0x00",

MAIN_Cortex_R5_0_0:                             "cmdRegWr": "0x00",

MAIN_Cortex_R5_0_0:                             "cfgReg": "0x00000000",

MAIN_Cortex_R5_0_0:                             "shift": 0,

MAIN_Cortex_R5_0_0:                             "mask": "0x00",

MAIN_Cortex_R5_0_0:                             "bitP": 0

MAIN_Cortex_R5_0_0:                     }

MAIN_Cortex_R5_0_0:             },

MAIN_Cortex_R5_0_0:             "p888s": null,

MAIN_Cortex_R5_0_0:             "p888d": null,

MAIN_Cortex_R5_0_0:             "pCustom": { 

MAIN_Cortex_R5_0_0:                     "fxn": null

MAIN_Cortex_R5_0_0:             }

MAIN_Cortex_R5_0_0:     },

MAIN_Cortex_R5_0_0:     "addrByteSupport": "1",

MAIN_Cortex_R5_0_0:     "fourByteAddrEnSeq": "0xA1",

MAIN_Cortex_R5_0_0:     "cmdExtType": "REPEAT",

MAIN_Cortex_R5_0_0:     "resetType": "0x38",

MAIN_Cortex_R5_0_0:     "deviceBusyType": "1",

MAIN_Cortex_R5_0_0:     "cmdWren": "0x06",

MAIN_Cortex_R5_0_0:     "cmdRdsr": "0x05",

MAIN_Cortex_R5_0_0:     "srWip":  0,

MAIN_Cortex_R5_0_0:     "srWel":  1,

MAIN_Cortex_R5_0_0:     "cmdChipErase": "0xC7",

MAIN_Cortex_R5_0_0:     "rdIdSettings": {

MAIN_Cortex_R5_0_0:             "cmd": "0x9F",

MAIN_Cortex_R5_0_0:             "numBytes": 5,

MAIN_Cortex_R5_0_0:             "dummy4": 0,

MAIN_Cortex_R5_0_0:             "dummy8": 0

MAIN_Cortex_R5_0_0:     },

MAIN_Cortex_R5_0_0:     "xspiWipRdCmd": "0x65",

MAIN_Cortex_R5_0_0:     "xspiWipReg": "0x00800000",

MAIN_Cortex_R5_0_0:     "xspiWipBit": 0,

MAIN_Cortex_R5_0_0:     "flashDeviceBusyTimeout": 256000000,

MAIN_Cortex_R5_0_0:     "flashPageProgTimeout": 512

MAIN_Cortex_R5_0_0: }

MAIN_Cortex_R5_0_0: 

MAIN_Cortex_R5_0_0: All tests have passed!!