/* * Copyright (C) 2021 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Auto generated file */ #include "ti_drivers_open_close.h" #include void Drivers_open(void) { // this may be used in the application by an definition. gEpwmTbClkSyncDisableMask = ((1U << 1U) | (1U << 3U)); /* Disabling the TBCLK SYNC for the EPWM configurations */ SOC_setMultipleEpwmTbClk(gEpwmTbClkSyncDisableMask, FALSE); /* Halt Controls for EPWM */ /* Halt Enabled for EPWM instance 1*/ Soc_enableEPWMHalt(1); /* Halt Enabled for EPWM instance 3*/ Soc_enableEPWMHalt(3); Drivers_epwmOpen(); Drivers_inputXbarOpen(); Drivers_uartOpen(); } void Drivers_close(void) { Drivers_uartClose(); } uint32_t gEpwmTbClkSyncEnableMask; uint32_t gEpwmTbClkSyncDisableMask; void Drivers_epwmOpen(void) { /* CONFIG_EPWM3 initialization */ /* Time Base */ EPWM_setEmulationMode(CONFIG_EPWM3_BASE_ADDR, EPWM_EMULATION_FREE_RUN); EPWM_setClockPrescaler(CONFIG_EPWM3_BASE_ADDR, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_TBPRD_TBPRDHR); EPWM_setPeriodLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_PERIOD_DIRECT_LOAD); EPWM_selectPeriodLoadEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO); EPWM_setTimeBasePeriod(CONFIG_EPWM3_BASE_ADDR, 5000); EPWM_setTimeBaseCounter(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setTimeBaseCounterMode(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_MODE_UP_DOWN); EPWM_setCountModeAfterSync(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNT_MODE_UP_AFTER_SYNC); EPWM_enablePhaseShiftLoad(CONFIG_EPWM3_BASE_ADDR); EPWM_setPhaseShift(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_enableSyncOutPulseSource(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setSyncInPulseSource(CONFIG_EPWM3_BASE_ADDR, EPWM_SYNC_IN_PULSE_SRC_DISABLE); EPWM_setOneShotSyncOutTrigger(CONFIG_EPWM3_BASE_ADDR, EPWM_OSHT_SYNC_OUT_TRIG_SYNC); HRPWM_setSyncPulseSource(CONFIG_EPWM3_BASE_ADDR, HRPWM_PWMSYNC_SOURCE_PERIOD); /* Counter Compare */ EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_CMPA_CMPAHR); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_PERIOD); EPWM_setCounterCompareValue(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_A, 2500); EPWM_setupEPWMLinks(CONFIG_EPWM3_BASE_ADDR, EPWM_LINK_WITH_EPWM_3, EPWM_LINK_COMP_A); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_CMPB_CMPBHR); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_B, 1500); EPWM_setCounterCompareValue(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_C, 0); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_CMPC); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_C, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_D, 0); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_CMPD); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_COUNTER_COMPARE_D, EPWM_COMP_LOAD_ON_CNTR_ZERO); /* Action Qualifier */ EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_AQCSFRC); EPWM_setActionQualifierContSWForceShadowMode(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_SW_IMMEDIATE_LOAD); EPWM_enableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_AQCTLA_AQCTLA2); EPWM_disableActionQualifierShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_ACTION_QUALIFIER_A); EPWM_setActionQualifierShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierT1TriggerSource(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1); EPWM_setActionQualifierT2TriggerSource(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1); EPWM_setActionQualifierSWAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE); EPWM_setActionQualifierContSWForceAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_SW_DISABLED); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_AQCTLB_AQCTLB2); EPWM_disableActionQualifierShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_ACTION_QUALIFIER_B); EPWM_setActionQualifierShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierSWAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE); EPWM_setActionQualifierContSWForceAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_SW_DISABLED); /* Events */ EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN); /* Trip Zone */ EPWM_setTripZoneAction(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_HIGH_Z); EPWM_disableTripZoneAdvAction(CONFIG_EPWM3_BASE_ADDR); EPWM_enableTripZoneSignals(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_enableTripZoneSignals(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_selectCycleByCycleTripZoneClearEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO); EPWM_enableTripZone2Signals(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_enableTripZone2Signals(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_enableTripZoneInterrupt(CONFIG_EPWM3_BASE_ADDR, 0); /* Digital Compare */ EPWM_setDigitalCompareFilterInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_WINDOW_SOURCE_DCAEVT1); EPWM_disableDigitalCompareBlankingWindow(CONFIG_EPWM3_BASE_ADDR); EPWM_setDigitalCompareBlankingEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_WINDOW_START_TBCTR_PERIOD, 0); EPWM_setDigitalCompareWindowOffset(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setDigitalCompareWindowLength(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_disableDigitalCompareWindowInverseMode(CONFIG_EPWM3_BASE_ADDR); EPWM_disableDigitalCompareCounterCapture(CONFIG_EPWM3_BASE_ADDR); EPWM_setDigitalCompareCounterShadowMode(CONFIG_EPWM3_BASE_ADDR, false); EPWM_disableDigitalCompareEdgeFilter(CONFIG_EPWM3_BASE_ADDR); EPWM_setDigitalCompareEdgeFilterMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_EDGEFILT_MODE_RISING); EPWM_setDigitalCompareEdgeFilterEdgeCount(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_EDGEFILT_EDGECNT_0); EPWM_disableValleyCapture(CONFIG_EPWM3_BASE_ADDR); EPWM_setValleyTriggerSource(CONFIG_EPWM3_BASE_ADDR, EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE); EPWM_setValleyTriggerEdgeCounts(CONFIG_EPWM3_BASE_ADDR, 0, 0); EPWM_disableValleyHWDelay(CONFIG_EPWM3_BASE_ADDR); EPWM_setValleySWDelayValue(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setValleyDelayDivider(CONFIG_EPWM3_BASE_ADDR, EPWM_VALLEY_DELAY_MODE_SW_DELAY); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM3_BASE_ADDR, 0, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAH); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM3_BASE_ADDR, 0, EPWM_DC_TYPE_DCAL); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAL); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareADCTrigger(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM3_BASE_ADDR, 0, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBH); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM3_BASE_ADDR, 0, EPWM_DC_TYPE_DCBL); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBL); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM3_BASE_ADDR, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareADCTrigger(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); /* DCCAP Edge Detection */ EPWM_disableCaptureInEvent(CONFIG_EPWM3_BASE_ADDR); EPWM_selectCaptureTripInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_CAPTURE_GATE); EPWM_configCaptureGateInputPolarity(CONFIG_EPWM3_BASE_ADDR, EPWM_CAPGATE_INPUT_ALWAYS_ON); EPWM_selectCaptureTripInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_CAPTURE_INPUT); EPWM_invertCaptureInputPolarity(CONFIG_EPWM3_BASE_ADDR, EPWM_CAPTURE_INPUT_CAPIN_SYNC); EPWM_disableIndependentPulseLogic(CONFIG_EPWM3_BASE_ADDR); /* Deadband */ EPWM_disableDeadBandControlShadowLoadMode(CONFIG_EPWM3_BASE_ADDR); EPWM_setDeadBandControlShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_LOAD_ON_CNTR_ZERO); EPWM_setRisingEdgeDeadBandDelayInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_INPUT_EPWMA); EPWM_setFallingEdgeDeadBandDelayInput(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_INPUT_EPWMA); EPWM_setDeadBandDelayPolarity(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); EPWM_setDeadBandDelayPolarity(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); EPWM_setDeadBandDelayMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_RED, true); EPWM_setDeadBandDelayMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_FED, true); EPWM_setDeadBandOutputSwapMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_OUTPUT_A, false); EPWM_setDeadBandOutputSwapMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_OUTPUT_B, false); EPWM_enableGlobalLoadRegisters(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_REGISTER_DBCTL); EPWM_disableRisingEdgeDelayCountShadowLoadMode(CONFIG_EPWM3_BASE_ADDR); EPWM_setRisingEdgeDelayCountShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_RED_LOAD_ON_CNTR_ZERO); EPWM_setRisingEdgeDelayCount(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_disableFallingEdgeDelayCountShadowLoadMode(CONFIG_EPWM3_BASE_ADDR); EPWM_setFallingEdgeDelayCountShadowLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_FED_LOAD_ON_CNTR_ZERO); EPWM_setFallingEdgeDelayCount(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setDeadBandCounterClock(CONFIG_EPWM3_BASE_ADDR, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE); /* Chopper */ EPWM_disableChopper(CONFIG_EPWM3_BASE_ADDR); EPWM_setChopperDutyCycle(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setChopperFreq(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setChopperFirstPulseWidth(CONFIG_EPWM3_BASE_ADDR, 0); /* Event Trigger */ EPWM_disableInterrupt(CONFIG_EPWM3_BASE_ADDR); EPWM_setInterruptSource(CONFIG_EPWM3_BASE_ADDR, EPWM_INT_TBCTR_ZERO, 0); EPWM_setInterruptEventCount(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_disableInterruptEventCountInit(CONFIG_EPWM3_BASE_ADDR); EPWM_setInterruptEventCountInitValue(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_disableADCTrigger(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_A); EPWM_setADCTriggerSource(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_A, EPWM_SOC_DCxEVT1, 0); EPWM_setADCTriggerEventPrescale(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_A, 0); EPWM_disableADCTriggerEventCountInit(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_A); EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_A, 0); EPWM_disableADCTrigger(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_B); EPWM_setADCTriggerSource(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_B, EPWM_SOC_DCxEVT1, 0); EPWM_setADCTriggerEventPrescale(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_B, 0); EPWM_disableADCTriggerEventCountInit(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_B); EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM3_BASE_ADDR, EPWM_SOC_B, 0); /* XCMP Mode */ EPWM_disableXCMPMode(CONFIG_EPWM3_BASE_ADDR); EPWM_disableSplitXCMP(CONFIG_EPWM3_BASE_ADDR); EPWM_allocAXCMP(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_NONE_CMPA); EPWM_setXCMPLoadMode(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE); EPWM_setXCMPShadowLevel(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_XLOADCTL_SHDWLEVEL_0); EPWM_setXCMPShadowBufPtrLoadOnce(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL); EPWM_setXCMPShadowRepeatBufxCount(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, 0); EPWM_setXCMPShadowRepeatBufxCount(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, 0); /* Write values to Reg */ EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP1_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP2_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP3_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP4_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP5_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP6_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP7_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP8_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP1_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP2_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP3_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP4_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP5_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP6_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP7_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP8_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP1_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP2_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP3_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP4_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP5_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP6_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP7_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP8_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP1_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP2_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP3_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP4_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP5_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP6_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP7_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP8_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XTBPRD_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XTBPRD_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XTBPRD_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XTBPRD_SHADOW3, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMIN_ACTIVE, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMAX_ACTIVE, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMIN_SHADOW1, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMAX_SHADOW1, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMIN_SHADOW2, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMAX_SHADOW2, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMIN_SHADOW3, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM3_BASE_ADDR, EPWM_XMAX_SHADOW3, 0); /* Events */ EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM3_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); /* Diode Emulation */ EPWM_disableDiodeEmulationMode(CONFIG_EPWM3_BASE_ADDR); EPWM_setDiodeEmulationMode(CONFIG_EPWM3_BASE_ADDR, EPWM_DIODE_EMULATION_CBC); EPWM_setDiodeEmulationReentryDelay(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_configureDiodeEmulationTripSources(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0, EPWM_DE_TRIPL); EPWM_configureDiodeEmulationTripSources(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0, EPWM_DE_TRIPH); EPWM_selectDiodeEmulationPWMsignal(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_CHANNEL_A, EPWM_DE_SYNC_TRIPHorL); EPWM_selectDiodeEmulationTripSignal(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_CHANNEL_A, EPWM_DE_TRIPL); EPWM_selectDiodeEmulationPWMsignal(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_CHANNEL_B, EPWM_DE_SYNC_TRIPHorL); EPWM_selectDiodeEmulationTripSignal(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_CHANNEL_B, EPWM_DE_TRIPL); EPWM_nobypassDiodeEmulationLogic(CONFIG_EPWM3_BASE_ADDR); EPWM_disableDiodeEmulationMonitorModeControl(CONFIG_EPWM3_BASE_ADDR); EPWM_setDiodeEmulationMonitorCounterThreshold(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_setDiodeEmulationMonitorModeStep(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_COUNT_DOWN, 0); EPWM_setDiodeEmulationMonitorModeStep(CONFIG_EPWM3_BASE_ADDR, EPWM_DE_COUNT_UP, 0); /* HRPWM */ HRPWM_disableAutoConversion(CONFIG_EPWM3_BASE_ADDR); HRPWM_setMEPControlMode(CONFIG_EPWM3_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setMEPControlMode(CONFIG_EPWM3_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setHiResPhaseShift(CONFIG_EPWM3_BASE_ADDR, 0); HRPWM_disablePhaseShiftLoad(CONFIG_EPWM3_BASE_ADDR); HRPWM_setMEPEdgeSelect(CONFIG_EPWM3_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_DISABLE); HRPWM_setMEPEdgeSelect(CONFIG_EPWM3_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_DISABLE); HRPWM_setHiResCounterCompareValue(CONFIG_EPWM3_BASE_ADDR, HRPWM_COUNTER_COMPARE_A, 1); HRPWM_setHiResCounterCompareValue(CONFIG_EPWM3_BASE_ADDR, HRPWM_COUNTER_COMPARE_B, 1); HRPWM_setCounterCompareShadowLoadEvent(CONFIG_EPWM3_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setCounterCompareShadowLoadEvent(CONFIG_EPWM3_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_disablePeriodControl(CONFIG_EPWM3_BASE_ADDR); HRPWM_setHiResTimeBasePeriod(CONFIG_EPWM3_BASE_ADDR, 0); HRPWM_setDeadbandMEPEdgeSelect(CONFIG_EPWM3_BASE_ADDR, HRPWM_DB_MEP_CTRL_DISABLE); HRPWM_setHiResRisingEdgeDelay(CONFIG_EPWM3_BASE_ADDR, 0); HRPWM_setRisingEdgeDelayLoadMode(CONFIG_EPWM3_BASE_ADDR, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setHiResFallingEdgeDelayOnly(CONFIG_EPWM3_BASE_ADDR, 0); HRPWM_setFallingEdgeDelayLoadMode(CONFIG_EPWM3_BASE_ADDR, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setOutputSwapMode(CONFIG_EPWM3_BASE_ADDR, false); HRPWM_setChannelBOutputPath(CONFIG_EPWM3_BASE_ADDR, HRPWM_OUTPUT_ON_B_NORMAL); /* ICL */ EPWM_disableIllegalComboLogic(CONFIG_EPWM3_BASE_ADDR, EPWM_MINDB_BLOCK_A); EPWM_disableIllegalComboLogic(CONFIG_EPWM3_BASE_ADDR, EPWM_MINDB_BLOCK_B); /* MDL */ EPWM_disableMinimumDeadBand(CONFIG_EPWM3_BASE_ADDR, EPWM_MINDB_BLOCK_A); EPWM_disableMinimumDeadBand(CONFIG_EPWM3_BASE_ADDR, EPWM_MINDB_BLOCK_B); /* Global Load */ EPWM_disableGlobalLoad(CONFIG_EPWM3_BASE_ADDR); EPWM_setGlobalLoadTrigger(CONFIG_EPWM3_BASE_ADDR, EPWM_GL_LOAD_PULSE_CNTR_ZERO); EPWM_setGlobalLoadEventPrescale(CONFIG_EPWM3_BASE_ADDR, 0); EPWM_disableGlobalLoadOneShotMode(CONFIG_EPWM3_BASE_ADDR); /* EPWM Module */ EPWM_lockRegisters(CONFIG_EPWM3_BASE_ADDR, 0); /* CONFIG_EPWM1 initialization */ /* Time Base */ EPWM_setEmulationMode(CONFIG_EPWM1_BASE_ADDR, EPWM_EMULATION_STOP_AFTER_NEXT_TB); EPWM_setClockPrescaler(CONFIG_EPWM1_BASE_ADDR, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_TBPRD_TBPRDHR); EPWM_setPeriodLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_PERIOD_DIRECT_LOAD); EPWM_selectPeriodLoadEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO); EPWM_setTimeBasePeriod(CONFIG_EPWM1_BASE_ADDR, 5000); EPWM_setTimeBaseCounter(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setTimeBaseCounterMode(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_MODE_UP_DOWN); EPWM_setCountModeAfterSync(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNT_MODE_UP_AFTER_SYNC); EPWM_enablePhaseShiftLoad(CONFIG_EPWM1_BASE_ADDR); EPWM_setPhaseShift(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_enableSyncOutPulseSource(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setSyncInPulseSource(CONFIG_EPWM1_BASE_ADDR, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3); EPWM_setOneShotSyncOutTrigger(CONFIG_EPWM1_BASE_ADDR, EPWM_OSHT_SYNC_OUT_TRIG_SYNC); HRPWM_setSyncPulseSource(CONFIG_EPWM1_BASE_ADDR, HRPWM_PWMSYNC_SOURCE_PERIOD); /* Counter Compare */ EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_CMPA_CMPAHR); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_A, 2500); EPWM_setupEPWMLinks(CONFIG_EPWM1_BASE_ADDR, EPWM_LINK_WITH_EPWM_3, EPWM_LINK_COMP_A); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_CMPB_CMPBHR); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_B, 15); EPWM_setCounterCompareValue(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_C, 0); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_CMPC); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_C, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_D, 0); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_CMPD); EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_COUNTER_COMPARE_D, EPWM_COMP_LOAD_ON_CNTR_ZERO); /* Action Qualifier */ EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_AQCSFRC); EPWM_setActionQualifierContSWForceShadowMode(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_AQCTLA_AQCTLA2); EPWM_disableActionQualifierShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_ACTION_QUALIFIER_A); EPWM_setActionQualifierShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierT1TriggerSource(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1); EPWM_setActionQualifierT2TriggerSource(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1); EPWM_setActionQualifierSWAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE); EPWM_setActionQualifierContSWForceAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_SW_DISABLED); EPWM_disableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_AQCTLB_AQCTLB2); EPWM_disableActionQualifierShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_ACTION_QUALIFIER_B); EPWM_setActionQualifierShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierSWAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE); EPWM_setActionQualifierContSWForceAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_SW_DISABLED); /* Events */ EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP); EPWM_setActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN); /* Trip Zone */ EPWM_setTripZoneAction(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_HIGH_Z); EPWM_setTripZoneAction(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_HIGH_Z); EPWM_disableTripZoneAdvAction(CONFIG_EPWM1_BASE_ADDR); EPWM_enableTripZoneSignals(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_enableTripZoneSignals(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_selectCycleByCycleTripZoneClearEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO); EPWM_enableTripZone2Signals(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_enableTripZone2Signals(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_enableTripZoneInterrupt(CONFIG_EPWM1_BASE_ADDR, 0); /* Digital Compare */ EPWM_setDigitalCompareFilterInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_WINDOW_SOURCE_DCAEVT1); EPWM_disableDigitalCompareBlankingWindow(CONFIG_EPWM1_BASE_ADDR); EPWM_setDigitalCompareBlankingEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_WINDOW_START_TBCTR_PERIOD, 0); EPWM_setDigitalCompareWindowOffset(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setDigitalCompareWindowLength(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_disableDigitalCompareWindowInverseMode(CONFIG_EPWM1_BASE_ADDR); EPWM_disableDigitalCompareCounterCapture(CONFIG_EPWM1_BASE_ADDR); EPWM_setDigitalCompareCounterShadowMode(CONFIG_EPWM1_BASE_ADDR, false); EPWM_disableDigitalCompareEdgeFilter(CONFIG_EPWM1_BASE_ADDR); EPWM_setDigitalCompareEdgeFilterMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_EDGEFILT_MODE_RISING); EPWM_setDigitalCompareEdgeFilterEdgeCount(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_EDGEFILT_EDGECNT_0); EPWM_disableValleyCapture(CONFIG_EPWM1_BASE_ADDR); EPWM_setValleyTriggerSource(CONFIG_EPWM1_BASE_ADDR, EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE); EPWM_setValleyTriggerEdgeCounts(CONFIG_EPWM1_BASE_ADDR, 0, 0); EPWM_disableValleyHWDelay(CONFIG_EPWM1_BASE_ADDR); EPWM_setValleySWDelayValue(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setValleyDelayDivider(CONFIG_EPWM1_BASE_ADDR, EPWM_VALLEY_DELAY_MODE_SW_DELAY); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM1_BASE_ADDR, 0, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAH); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM1_BASE_ADDR, 0, EPWM_DC_TYPE_DCAL); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAL); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareADCTrigger(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM1_BASE_ADDR, 0, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBH); EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM1_BASE_ADDR, 0, EPWM_DC_TYPE_DCBL); EPWM_selectDigitalCompareTripInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBL); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DC_DISABLED); EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM1_BASE_ADDR, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DC_DISABLED); EPWM_disableDigitalCompareADCTrigger(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED); EPWM_setDigitalCompareEventSource(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_DISABLED); EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO); /* DCCAP Edge Detection */ EPWM_disableCaptureInEvent(CONFIG_EPWM1_BASE_ADDR); EPWM_selectCaptureTripInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_CAPTURE_GATE); EPWM_configCaptureGateInputPolarity(CONFIG_EPWM1_BASE_ADDR, EPWM_CAPGATE_INPUT_ALWAYS_ON); EPWM_selectCaptureTripInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_CAPTURE_INPUT); EPWM_invertCaptureInputPolarity(CONFIG_EPWM1_BASE_ADDR, EPWM_CAPTURE_INPUT_CAPIN_SYNC); EPWM_disableIndependentPulseLogic(CONFIG_EPWM1_BASE_ADDR); /* Deadband */ EPWM_disableDeadBandControlShadowLoadMode(CONFIG_EPWM1_BASE_ADDR); EPWM_setDeadBandControlShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_LOAD_ON_CNTR_ZERO); EPWM_setRisingEdgeDeadBandDelayInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_INPUT_EPWMA); EPWM_setFallingEdgeDeadBandDelayInput(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_INPUT_EPWMA); EPWM_setDeadBandDelayPolarity(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); EPWM_setDeadBandDelayPolarity(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); EPWM_setDeadBandDelayMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_RED, true); EPWM_setDeadBandDelayMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_FED, true); EPWM_setDeadBandOutputSwapMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_OUTPUT_A, false); EPWM_setDeadBandOutputSwapMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_OUTPUT_B, false); EPWM_enableGlobalLoadRegisters(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_REGISTER_DBCTL); EPWM_disableRisingEdgeDelayCountShadowLoadMode(CONFIG_EPWM1_BASE_ADDR); EPWM_setRisingEdgeDelayCountShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_RED_LOAD_ON_CNTR_ZERO); EPWM_setRisingEdgeDelayCount(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_disableFallingEdgeDelayCountShadowLoadMode(CONFIG_EPWM1_BASE_ADDR); EPWM_setFallingEdgeDelayCountShadowLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_FED_LOAD_ON_CNTR_ZERO); EPWM_setFallingEdgeDelayCount(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setDeadBandCounterClock(CONFIG_EPWM1_BASE_ADDR, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE); /* Chopper */ EPWM_disableChopper(CONFIG_EPWM1_BASE_ADDR); EPWM_setChopperDutyCycle(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setChopperFreq(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setChopperFirstPulseWidth(CONFIG_EPWM1_BASE_ADDR, 0); /* Event Trigger */ EPWM_disableInterrupt(CONFIG_EPWM1_BASE_ADDR); EPWM_setInterruptSource(CONFIG_EPWM1_BASE_ADDR, EPWM_INT_TBCTR_ZERO, 0); EPWM_setInterruptEventCount(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_disableInterruptEventCountInit(CONFIG_EPWM1_BASE_ADDR); EPWM_setInterruptEventCountInitValue(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_disableADCTrigger(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_A); EPWM_setADCTriggerSource(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_A, EPWM_SOC_DCxEVT1, 0); EPWM_setADCTriggerEventPrescale(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_A, 0); EPWM_disableADCTriggerEventCountInit(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_A); EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_A, 0); EPWM_disableADCTrigger(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_B); EPWM_setADCTriggerSource(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_B, EPWM_SOC_DCxEVT1, 0); EPWM_setADCTriggerEventPrescale(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_B, 0); EPWM_disableADCTriggerEventCountInit(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_B); EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM1_BASE_ADDR, EPWM_SOC_B, 0); /* XCMP Mode */ EPWM_disableXCMPMode(CONFIG_EPWM1_BASE_ADDR); EPWM_disableSplitXCMP(CONFIG_EPWM1_BASE_ADDR); EPWM_allocAXCMP(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_NONE_CMPA); EPWM_setXCMPLoadMode(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE); EPWM_setXCMPShadowLevel(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_XLOADCTL_SHDWLEVEL_0); EPWM_setXCMPShadowBufPtrLoadOnce(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL); EPWM_setXCMPShadowRepeatBufxCount(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, 0); EPWM_setXCMPShadowRepeatBufxCount(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, 0); /* Write values to Reg */ EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP1_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP2_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP3_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP4_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP5_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP6_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP7_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP8_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP1_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP2_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP3_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP4_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP5_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP6_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP7_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP8_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP1_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP2_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP3_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP4_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP5_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP6_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP7_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP8_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP1_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP2_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP3_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP4_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP5_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP6_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP7_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP8_SHADOW3, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XTBPRD_ACTIVE, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XTBPRD_SHADOW1, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XTBPRD_SHADOW2, 0); EPWM_setXCMPRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XTBPRD_SHADOW3, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMIN_ACTIVE, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMAX_ACTIVE, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMIN_SHADOW1, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMAX_SHADOW1, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMIN_SHADOW2, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMAX_SHADOW2, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMIN_SHADOW3, 0); EPWM_setXMINMAXRegValue(CONFIG_EPWM1_BASE_ADDR, EPWM_XMAX_SHADOW3, 0); /* Events */ EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7); EPWM_setXCMPActionQualifierAction(CONFIG_EPWM1_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8); /* Diode Emulation */ EPWM_disableDiodeEmulationMode(CONFIG_EPWM1_BASE_ADDR); EPWM_setDiodeEmulationMode(CONFIG_EPWM1_BASE_ADDR, EPWM_DIODE_EMULATION_CBC); EPWM_setDiodeEmulationReentryDelay(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_configureDiodeEmulationTripSources(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0, EPWM_DE_TRIPL); EPWM_configureDiodeEmulationTripSources(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0, EPWM_DE_TRIPH); EPWM_selectDiodeEmulationPWMsignal(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_CHANNEL_A, EPWM_DE_SYNC_TRIPHorL); EPWM_selectDiodeEmulationTripSignal(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_CHANNEL_A, EPWM_DE_TRIPL); EPWM_selectDiodeEmulationPWMsignal(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_CHANNEL_B, EPWM_DE_SYNC_TRIPHorL); EPWM_selectDiodeEmulationTripSignal(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_CHANNEL_B, EPWM_DE_TRIPL); EPWM_nobypassDiodeEmulationLogic(CONFIG_EPWM1_BASE_ADDR); EPWM_disableDiodeEmulationMonitorModeControl(CONFIG_EPWM1_BASE_ADDR); EPWM_setDiodeEmulationMonitorCounterThreshold(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_setDiodeEmulationMonitorModeStep(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_COUNT_DOWN, 0); EPWM_setDiodeEmulationMonitorModeStep(CONFIG_EPWM1_BASE_ADDR, EPWM_DE_COUNT_UP, 0); /* HRPWM */ HRPWM_disableAutoConversion(CONFIG_EPWM1_BASE_ADDR); HRPWM_setMEPControlMode(CONFIG_EPWM1_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setMEPControlMode(CONFIG_EPWM1_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setHiResPhaseShift(CONFIG_EPWM1_BASE_ADDR, 0); HRPWM_disablePhaseShiftLoad(CONFIG_EPWM1_BASE_ADDR); HRPWM_setMEPEdgeSelect(CONFIG_EPWM1_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_DISABLE); HRPWM_setMEPEdgeSelect(CONFIG_EPWM1_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_DISABLE); HRPWM_setHiResCounterCompareValue(CONFIG_EPWM1_BASE_ADDR, HRPWM_COUNTER_COMPARE_A, 1); HRPWM_setHiResCounterCompareValue(CONFIG_EPWM1_BASE_ADDR, HRPWM_COUNTER_COMPARE_B, 1); HRPWM_setCounterCompareShadowLoadEvent(CONFIG_EPWM1_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setCounterCompareShadowLoadEvent(CONFIG_EPWM1_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_disablePeriodControl(CONFIG_EPWM1_BASE_ADDR); HRPWM_setHiResTimeBasePeriod(CONFIG_EPWM1_BASE_ADDR, 0); HRPWM_setDeadbandMEPEdgeSelect(CONFIG_EPWM1_BASE_ADDR, HRPWM_DB_MEP_CTRL_DISABLE); HRPWM_setHiResRisingEdgeDelay(CONFIG_EPWM1_BASE_ADDR, 0); HRPWM_setRisingEdgeDelayLoadMode(CONFIG_EPWM1_BASE_ADDR, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setHiResFallingEdgeDelayOnly(CONFIG_EPWM1_BASE_ADDR, 0); HRPWM_setFallingEdgeDelayLoadMode(CONFIG_EPWM1_BASE_ADDR, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setOutputSwapMode(CONFIG_EPWM1_BASE_ADDR, false); HRPWM_setChannelBOutputPath(CONFIG_EPWM1_BASE_ADDR, HRPWM_OUTPUT_ON_B_NORMAL); /* ICL */ EPWM_disableIllegalComboLogic(CONFIG_EPWM1_BASE_ADDR, EPWM_MINDB_BLOCK_A); EPWM_disableIllegalComboLogic(CONFIG_EPWM1_BASE_ADDR, EPWM_MINDB_BLOCK_B); /* MDL */ EPWM_disableMinimumDeadBand(CONFIG_EPWM1_BASE_ADDR, EPWM_MINDB_BLOCK_A); EPWM_disableMinimumDeadBand(CONFIG_EPWM1_BASE_ADDR, EPWM_MINDB_BLOCK_B); /* Global Load */ EPWM_disableGlobalLoad(CONFIG_EPWM1_BASE_ADDR); EPWM_setGlobalLoadTrigger(CONFIG_EPWM1_BASE_ADDR, EPWM_GL_LOAD_PULSE_CNTR_ZERO); EPWM_setGlobalLoadEventPrescale(CONFIG_EPWM1_BASE_ADDR, 0); EPWM_disableGlobalLoadOneShotMode(CONFIG_EPWM1_BASE_ADDR); /* EPWM Module */ EPWM_lockRegisters(CONFIG_EPWM1_BASE_ADDR, 0); } void Drivers_inputXbarOpen() { /* INPUT XBAR */ SOC_xbarSelectInputXBarInputSource_ext(CSL_CONTROLSS_INPUTXBAR_U_BASE, 0, 0, INPUT_XBAR_GPIO43, 0, 0); SOC_xbarSelectInputXBarInputSource_ext(CSL_CONTROLSS_INPUTXBAR_U_BASE, 1, 0, INPUT_XBAR_GPIO45, 0, 0); SOC_xbarSelectInputXBarInputSource_ext(CSL_CONTROLSS_INPUTXBAR_U_BASE, 2, 0, INPUT_XBAR_GPIO46, 0, 0); } /* * UART */ /* UART Driver handles */ UART_Handle gUartHandle[CONFIG_UART_NUM_INSTANCES]; #include #include #include /* EDMA driver confiurations */ EDMA_Config gEdmaConfig[] = { }; uint32_t gEdmaConfigNum = 0; UART_DmaChConfig gUartDmaChConfig[CONFIG_UART_NUM_INSTANCES] = { NULL, }; /* UART Driver Parameters */ UART_Params gUartParams[CONFIG_UART_NUM_INSTANCES] = { { .baudRate = 115200, .dataLength = UART_LEN_8, .stopBits = UART_STOPBITS_1, .parityType = UART_PARITY_NONE, .readMode = UART_TRANSFER_MODE_BLOCKING, .readReturnMode = UART_READ_RETURN_MODE_FULL, .writeMode = UART_TRANSFER_MODE_BLOCKING, .readCallbackFxn = NULL, .writeCallbackFxn = NULL, .hwFlowControl = FALSE, .hwFlowControlThr = UART_RXTRIGLVL_16, .transferMode = UART_CONFIG_MODE_INTERRUPT, .skipIntrReg = FALSE, .uartDmaIndex = -1, .intrNum = 38U, .intrPriority = 4U, .operMode = UART_OPER_MODE_16X, .rxTrigLvl = 8U, .txTrigLvl = 32U, .rxEvtNum = 0U, .txEvtNum = 0U, }, }; void Drivers_uartOpen(void) { uint32_t instCnt; int32_t status = SystemP_SUCCESS; for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++) { gUartHandle[instCnt] = NULL; /* Init to NULL so that we can exit gracefully */ } /* Open all instances */ for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++) { gUartHandle[instCnt] = UART_open(instCnt, &gUartParams[instCnt]); if(NULL == gUartHandle[instCnt]) { DebugP_logError("UART open failed for instance %d !!!\r\n", instCnt); status = SystemP_FAILURE; break; } } if(SystemP_FAILURE == status) { Drivers_uartClose(); /* Exit gracefully */ } return; } void Drivers_uartClose(void) { uint32_t instCnt; /* Close all instances that are open */ for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++) { if(gUartHandle[instCnt] != NULL) { UART_close(gUartHandle[instCnt]); gUartHandle[instCnt] = NULL; } } return; }