
/* This is the stack that is used by code running within main()
 * In case of NORTOS,
 * - This means all the code outside of ISR uses this stack
 * In case of FreeRTOS
 * - This means all the code until vTaskStartScheduler() is called in main()
 *   uses this stack.
 * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
 */
 ///*20250625, Null point memory accesss issuse 02*/
//--stack_size=128//131072//128//163840
//--heap_size=512
--stack_size=32768
--heap_size=40960
-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */

/* This is the size of stack when R5 is in IRQ mode
 * In NORTOS,
 * - Here interrupt nesting is disabled as of now
 * - This is the stack used by ISRs registered as type IRQ
 * In FreeRTOS,
 * - Here interrupt nesting is enabled
 * - This is stack that is used initally when a IRQ is received
 * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
 * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
 */
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
 * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
 */
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */

SECTIONS
{
    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
    .vectors:{} palign(8) > R5F_VECS

    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
     * i.e this cannot be placed in DDR
     */
    GROUP {
        .text.hwi: palign(8)
        .text.cache: palign(8)
        .text.mpu: palign(8)
        .text.boot: palign(8)
        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
    } > MSRAM

    GROUP {
     	.tcma_sect : {
     		tasks.o (.text*)
     		timers.o (.text*)
     		queue.o (.text*)
     		event_groups.o (.text*)
     		port.o (.text*)
     		portASM.o (.text*)
     		HwiP_armv7r_handlers_freertos.o (.text*)
     		list.o (.text*)
     		tlsf.o (.text*)
    		mpsc_pbuf.o (.text*)
     		log_core.o (.text*)
    		log_msg.o (.text*)
     		log_msg2.o (.text*)
     		mem_slab.o (.text*)
		
			
     	}
    } > R5F_TCMA

    GROUP {
     	.tcmb0_sect : {
     		port.o (.bss.uxTimerTaskStack)
     		port.o (.bss.uxIdleTaskStack)
     		rrp_dl_thread.o (.bss.RrpThreadStack)
     		rrp_dl_thread.o (.bss.RrpUserThreadStack)
     		enet_layer2_icssg.o (.bss.gEnetMpTaskStackRx)
     		//enet_layer2_icssg.o (.bss.gEnetMp)	/*250114, add gEnetMp to tcmb0_sect*/
     		enet_osal_dflt.o (.bss.gOsalSemPEnetOsalPool)
     		eips_userobj.o (.bss.g_stEipDataOfInst)
     		rapi_os_down.o (.bss.flash_write_buf)
     	}
    } > R5F_TCMB0

    /* 64KB M4F DATA RAM */
    GROUP (NOLOAD) {
     	.m4f_dram : {
     		xg_system.o (*g_stSysInstance)
     		expnet_manager.o (.bss.stPara)
			expdrv_manager.o (.bss.g_astObjSemaphore)
			expnet_manager.o (.bss.g_auObjList)
     		xg_exc.o (.bss.g_stExcInstance)
     		xg_slave.o (.bss.g_stSlaveInstance)
     		expnet_pm.o (.bss.g_astRAPIEnetDirectPara)
     		expnet_pm.o (.bss.g_astRAPIEnetPara)
     		expnet_pm.o (.bss.g_astEipPara)
            expnet_pm.o (.bss.g_astModbusPara)
            rapi_diag.o (.bss.g_stRapiDiagInstance)
            ti_drivers_config.o (.bss.gPruIcssObjects)
            eips_cnxn.o (.bss.eips_CnxnStruct)
            eips_userobj.o (.bss.local_t2o_asm_struct)
            eips_userobj.o (.bss.local_o2t_asm_struct)
            eips_iomsg.o (.bss.eips_stc_iocnxns)
     	}
    } > M4F_DRAM

	// 2024.01.09 Song.C : g100_dev.c 뷮 Ŀ MSRAM Ҵ ȵȴ.
	//					   log_core.c buf32 (32kB) MCANx_RAM ű.
	//					   MCANx_RAM    ̽ (packet dropped) ߻Ѵ. MSRAM  ӵ ʴ  .
    GROUP (NOLOAD) {
     	.mcan1_msgram : {
     		log_core.o (.bss.buf32)
     	}
    } > MCAN1_RAM	/* G100 uses MCAN1_RAM */
	//ICSSG0_RAM0 ///*20250627, Null point memory accesss issuse 03*/
	//MCAN1_RAM	/* G100 uses MCAN1_RAM */

    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .text:   {} palign(8)   /* This is where code resides */

        rodata_start: { _image_rodata_start = .;}
        .rodata: {} palign(8)   /* This is where const's go */
        /* zephyr log facilities */
		._log_backends : {
			__log_backends_start = .;
			*(._log_backend.*)
			__log_backends_end = .;
		} palign(8)

		.log_const_log : {
			__log_const_start = .;
			*(.log_const_*)
			__log_const_end = .;
		} palign(8)
		rodata_end:   { _image_rodata_end = .;}
    } > MSRAM

    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .data:   {} palign(8)   /* This is where initialized globals and static go */
    } > MSRAM

    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
        .stack:  {} palign(8)   /* This is where the main() stack goes */
    } > MSRAM

    GROUP {
        .bss:    {} palign(8)   /* This is where uninitialized globals go */
        RUN_START(__BSS_START)
        RUN_END(__BSS_END)
    } > MSRAM

    	/* For SDK packet memory */
	.bss:ENET_DMA_DESC_MEMPOOL (NOLOAD) {} ALIGN (128) > MSRAM
	.bss:ENET_DMA_RING_MEMPOOL (NOLOAD) {} ALIGN (128) > MSRAM
	.bss:ENET_DMA_PKT_MEMPOOL  (NOLOAD) {} ALIGN (128) > MSRAM
    .bss:ENET_DMA_OBJ_MEM (NOLOAD) {} ALIGN (128) > MSRAM
    .bss:ENET_DMA_PKT_INFO_MEMPOOL (NOLOAD) {} ALIGN (128) > MSRAM
    .bss:ENET_ICSSG_OCMC_MEM (NOLOAD) {} ALIGN (128) > MSRAM

	GROUP {
        .noinit: {} palign(8) /* zephyr logging buffer */
    } > MSRAM

    UNION
    {
        .icssfw: palign(128)

        .icss_mem: type = NOLOAD , palign(128) {
        	*(*gEnetSoc_icssg1PortPoolMem_0)
        	*(*gEnetSoc_icssg1PortPoolMem_1)
        	*(*gEnetSoc_icssg1HostPoolMem_0)
        	*(*gEnetSoc_icssg1HostPoolMem_1)
        	*(*gEnetSoc_icssg1HostQueueMem_0)
        	*(*gEnetSoc_icssg1HostQueueMem_1)
        	*(*gEnetSoc_icssg1ScratchMem_0)
        	*(*gEnetSoc_icssg1ScratchMem_1)
        }
    } > MSRAM

    /* This is where the stacks for different R5F modes go */
    GROUP {
        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
        RUN_START(__IRQ_STACK_START)
        RUN_END(__IRQ_STACK_END)
        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
        RUN_START(__FIQ_STACK_START)
        RUN_END(__FIQ_STACK_END)
        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
        RUN_START(__SVC_STACK_START)
        RUN_END(__SVC_STACK_END)
        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
        RUN_START(__ABORT_STACK_START)
        RUN_END(__ABORT_STACK_END)
        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
        RUN_START(__UNDEFINED_STACK_START)
        RUN_END(__UNDEFINED_STACK_END)

        .end_msram: {__end_msram__ = .;} align(32)
    } > MSRAM

    GROUP {
        .sbl_msram: {__sbl_msram__ = .;} align(8)
    } > MSRAM_SBL

    .tlsf_pool (NOLOAD) {
        *(*tlsf_lwip_mempool)
    } > MSRAM_BOOT

    .bsp_mempool (NOLOAD) {
    	*(*tlsf_bsp_mempool)
    } > M4F_IRAM

    .gunzip_mempool (NOLOAD) {
    	 *(*gunzip_dictbuf*)
    } > ICSSG0_RAM1

//    .enet_dma_mem {
//        *(*ENET_DMA_DESC_MEMPOOL)
//        *(*ENET_DMA_RING_MEMPOOL)
//        *(*ENET_DMA_PKT_MEMPOOL)
//    } (NOLOAD) {} ALIGN (128) > MSRAM
}

/*
NOTE: Below memory is reserved for DMSC usage
 - During Boot till security handoff is complete
   0x701E0000 - 0x701FFFFF (128KB)
 - After "Security Handoff" is complete (i.e at run time)
   0x701FC000 - 0x701FFFFF (16KB)

 Security handoff is complete when this message is sent to the DMSC,
   TISCI_MSG_SEC_HANDOVER

 This should be sent once all cores are loaded and all application
 specific firewall calls are setup.
*/

MEMORY
{
    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
    /* selected object's text */
    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
    /* selected object's bss */
    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000

    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
     * this memory does not overlap with other R5F's
     * last 16KB is reserved DMSC
     * MSRAM_BOOT is used by SBL, when SBL handover done (application start)
     * it's free to use. Use this area for SYSTEM malloc area (TLSF, Two-Level Segregated Fit memory).
     */
    /* after boot stage, tlsf_lwip_mempool */
    MSRAM_BOOT : ORIGIN = 0x70000000 , LENGTH = 0x080000
    /*
	NOTE: Below memory is reserved for DMSC usage
 	- During Boot till security handoff is complete
   	0x701E0000 - 0x701FFFFF (128KB)
   	ýÿ  ޸𸮰 Ǳ   ڸ code    .
   	Ŀ unused_ram_size = __sbl_msram__ - __end_msram__; ٽ 밡   ȴ.
   	text, bss, stack, ro_data, data, noinit_data
   	TaekSeung Lee 2023. 6. 19. : SR2.0      þ.
   	*/
    MSRAM      : ORIGIN = 0x70080000 , LENGTH = 0x180000 - 0x020000
/*    MSRAM_SBL  : ORIGIN = 0x701FC000 , LENGTH = 0x004000 */
    MSRAM_SBL  : ORIGIN = 0x701F4000 , LENGTH = 0x00C000
    /*
     * kwonsk@kmd.co.kr
     * Found hidden SRAM, M4F IRAM(192KB) and DRAM(64KB) also accessible from R5F
     * Tested with networking memalloc pool, performace difference is ignorable.
     * We don't use M4F cpu.
     */
    /* bsp_mempool */
    M4F_IRAM  : ORIGIN = 0x05000000 , LENGTH = 0x00030000
    /* selected object's bss */
    M4F_DRAM  : ORIGIN = 0x05040000 , LENGTH = 0x00010000

    /* selected object's bss */
    MCAN0_RAM  : ORIGIN = 0x20708000 , LENGTH = 0x00008000 /* 32KB */
    MCAN1_RAM  : ORIGIN = 0x20718000 , LENGTH = 0x00008000 /* 32KB */

    ICSSG0_RAM0  : ORIGIN = 0x30000000 , LENGTH = 0x00008000 /* 32KB */
    /* gunzip_dictbuf */
    ICSSG0_RAM1  : ORIGIN = 0x30010000 , LENGTH = 0x00010000 /* 64KB */

    ICSSG1_RAM0  : ORIGIN = 0x30080000 , LENGTH = 0x00008000 /* 32KB */
    ICSSG1_RAM1  : ORIGIN = 0x30090000 , LENGTH = 0x00010000 /* 64KB */
}
