/******************************************************************************/
/* Williams Advanced Engineering Limited                     Copyright(C) 2021*/
/* Grove                                                  All rights reserved */
/*                                                                            */
/******************************************************************************/


#ifndef MAINSOURCES_INCLUDE_IOS_DIGITAL_H_
#define MAINSOURCES_INCLUDE_IOS_DIGITAL_H_

#include "hal_stdtypes.h"
#include "dmm.h"
#include "het.h"
#include "gio.h"
#include "spi.h"


/*----------------------------------------------------------------------------*/
/* CONSTANT DEFINITIONS                                                       */
/*----------------------------------------------------------------------------*/
// Digital pins assignment

/* GPIO ID for status LEDs */

#define PIO_SYS_PWR_RELEASE        11u          // NHET1[11]

#define PIO_LED_1_ID               1u           // DMM_CLK
#define PIO_LED_2_ID               3u           // DMM_DATA[1]
#define PIO_LED_3_ID               2u           // DMM_DATA[0]
#define PIO_EXT_WDG_ID             18u          // DMM_ENA

/* GPIO ID for high side driver enable pin */

#define PIO_GP_HSD_00_ID           27u          // N2HET1[27]
#define PIO_GP_HSD_01_ID           26u          // N2HET1[26]
#define PIO_GP_HSD_02_ID           25u          // N2HET1[25]
#define PIO_GP_HSD_03_ID           23u          // N2HET1[23]
#define PIO_GP_HSD_04_ID           22u          // N2HET1[22]
#define PIO_GP_HSD_05_ID           21u          // N2HET1[21]
#define PIO_GP_HSD_06_ID           20u          // N2HET1[20]
#define PIO_GP_HSD_07_ID           19u          // N2HET1[19]

/* GPIO ID for low side driver enable pin */

#define PIO_GP_LSD_00_ID           31u          // N2HET1[31]
#define PIO_GP_LSD_01_ID           30u          // N2HET1[30]
#define PIO_GP_LSD_02_ID           29u          // N2HET1[29]
#define PIO_GP_LSD_03_ID           28u          // N2HET1[28]

/* GPIO ID for CTCR high side driver enable pin */

#define PIO_CTCR_HSD_00_ID         14u          // N2HET1[14]
#define PIO_CTCR_HSD_01_ID         12u          // N2HET1[12]
#define PIO_CTCR_HSD_02_ID         10u          // N2HET1[10]

/* GPIO ID for CTCR low side driver enable pin */

#define PIO_CTCR_LSD_00_ID         18u          // N2HET1[18]
#define PIO_CTCR_LSD_01_ID         17u          // N2HET1[17]
#define PIO_CTCR_LSD_02_ID         16u          // N2HET1[16]

/* GPIO ID for CTCR status and fault pins */

#define PIO_CTCR_INT_DET_ID        0u           // N2HET1[0]
#define PIO_CTCR_INT_RST_ID        2u           // N2HET1[2]

#define PIO_CTCR_FLT_HS_RST_ID     4u           // GIOA[4]
#define PIO_CTCR_FLT_LS_RST_ID     5u           // GIOA[5]

#define PIO_CTCR_FLT_HS_00_ID      0u           // GIOB[0]
#define PIO_CTCR_FLT_HS_01_ID      7u           // GIOA[7]
#define PIO_CTCR_FLT_HS_02_ID      6u           // GIOA[6]
#define PIO_CTCR_FLT_LS_00_ID      3u           // GIOB[3]
#define PIO_CTCR_FLT_LS_01_ID      2u           // GIOB[2]
#define PIO_CTCR_FLT_LS_02_ID      1u           // GIOB[1]

/* GPIO ID for digital inputs */

#define PIO_DIG_IN_00_ID           9u           // N2HET1[9]
#define PIO_DIG_IN_01_ID           8u           // N2HET1[8]
#define PIO_DIG_IN_02_ID           7u           // N2HET1[7]
#define PIO_DIG_IN_03_ID           4u           // N2HET1[4]
#define PIO_DIG_IN_04_ID           1u           // N2HET1[1]

#define PIO_DIG_IN_05_ID           8u           // MIBSPI1NENA
#define PIO_DIG_IN_06_ID           5u           // MIBSPI1NCS[5]
#define PIO_DIG_IN_07_ID           4u           // MIBSPI1NCS[4]
#define PIO_DIG_IN_08_ID           3u           // MIBSPI1NCS[3]
#define PIO_DIG_IN_09_ID           2u           // MIBSPI1NCS[2]

#define NUM_DIG_CHANNELS_TOT 41

/*----------------------------------------------------------------------------*/
/* TYPE DEFINITIONS                                                           */
/*----------------------------------------------------------------------------*/
typedef enum
{
    SysPwrRelease = 0,
    BoardLed1,
    BoardLed2,
    BoardLed3,
    ExternalWDG,
    HighSideDrv00,
    HighSideDrv01,
    HighSideDrv02,
    HighSideDrv03,
    HighSideDrv04,
    HighSideDrv05,
    HighSideDrv06,
    HighSideDrv07,
    LowSideDrv00,
    LowSideDrv01,
    LowSideDrv02,
    LowSideDrv03,
    CTCRHighSideDrv00,
    CTCRHighSideDrv01,
    CTCRHighSideDrv02,
    CTCRLowSideDrv00,
    CTCRLowSideDrv01,
    CTCRLowSideDrv02,
    CTCRPwrSupplyInterruptDetected,
    CTRPwrSupplyInterruptReset,
    FaultCTCRHighSideDrv00,
    FaultCTCRHighSideDrv01,
    FaultCTCRHighSideDrv02,
    FaultCTCRLowSideDrv00,
    FaultCTCRLowSideDrv01,
    FaultCTCRLowSideDrv02,
    DigitalInput00,
    DigitalInput01,
    DigitalInput02,
    DigitalInput03,
    DigitalInput04,
    DigitalInput05,
    DigitalInput06,
    DigitalInput07,
    DigitalInput08,
    DigitalInput09,

} DigitalChannelID_Type;

typedef enum
{
    DirInput = 0,
    DirOutput
} PinDirectionType;

typedef struct
{
    gioPORT_t* McuPort;
    PinDirectionType tPinDir;
    uint8 PortPinID;

} DigitalChannelConfigType;

/*----------------------------------------------------------------------------*/
/* FUNCTION PROTOTYPES                                                        */
/*----------------------------------------------------------------------------*/
extern void  fnIosInitDigitalIOs(void);
extern void  fnIosSetDigitalChannel(DigitalChannelID_Type tChannelId, uint8 Value);
extern uint8 fnIosGetDigitalChannel(DigitalChannelID_Type tChannelId);

/* Private */
void fnIosInitDigitalIOsDirection(void);
void fnIosInitDigitalOutputs(void);



#endif /* MAINSOURCES_INCLUDE_IOS_DIGITAL_H_ */
