/******************************************************************************/
/* Williams Advanced Engineering Limited                     Copyright(C) 2021*/
/* Grove                                                  All rights reserved */
/*                                                                            */
/******************************************************************************/
/*
 * Fls_Spi.h
 *
 *  Created on: 22 Jun 2022
 *      Author: Sebastien.Chapeau
 */

#ifndef MCAL_FLS_INCLUDE_FLS_SPI_H_
#define MCAL_FLS_INCLUDE_FLS_SPI_H_

#include "Os.h"
#include "Fls_Private.h"

// Removing of compiler warnings and errors because of type re-declaration between hal_stdtypes.h and Std_Types.h
#define _BOOLEAN_DECLARED
#define _UINT8_DECLARED
#define _UINT16_DECLARED
#define _UINT32_DECLARED
#define _UINT64_DECLARED
#define _SINT8_DECLARED
#define _SINT16_DECLARED
#define _SINT32_DECLARED
#define _SINT64_DECLARED
#define _FLOAT32_DECLARED
#define _FLOAT64_DECLARED
#define _STD_RETURN_TYPE_DECLARED
#define _STDVERSION_DECLARED

#include "hal_stdtypes.h"
#include "sys_common.h"
#include "reg_spi.h"
#include "spi.h"




/*******************************************************************************
**                      EXPORTED CONSTANTS and MACROS                         **
*******************************************************************************/
//WAE modified code starting from Xilinx MCAL
//#define FLS_VENDOR_ID_QSPI_H         39u
//#define FLS_MODULE_ID_QSPI_H         92u
//#define FLS_INSTANCE_ID_QSPI_H       1u

#define FLS_AR_RELEASE_MAJOR_VERSION_QSPI_H          4u
#define FLS_AR_RELEASE_MINOR_VERSION_QSPI_H          2u
#define FLS_AR_RELEASE_REVISION_VERSION_QSPI_H       2u

#define FLS_SW_MAJOR_VERSION_QSPI_H       1u
#define FLS_SW_MINOR_VERSION_QSPI_H       0u
#define FLS_SW_PATCH_VERSION_QSPI_H       3u
/*******************************************************************************
**                      EXPORTED STRUCTURES, ENUMS, TYPEDEFS                  **
*******************************************************************************/

/**
 * QSPI - Hardware ID type
 */
typedef uint32 QSPI_HwIDType;

typedef uint32  FLS_QSPIModeType;
typedef uint32  FLS_QSPISpeedType ;
typedef uint32  FLS_QSPIReadLaneType;
/**
 * QSPI command type
 */
typedef uint32 QSPI_CmdType;
#define QSPI_CMD_NONE           (0x0UL)   /**< No command */
#define QSPI_CMD_INIT           (0x1UL)   /**< QSPI initialisation command */
#define QSPI_CMD_READ           (0x2UL)   /**< QSPI read command */
#define QSPI_CMD_XFER           (0x3UL)   /**< QSPI transfer command */
#define QSPI_CMD_STOP           (0x4UL)   /**< QSPI stop command */

/**
 * QSPI command state type
 */
typedef uint32 QSPI_CmdStateType;
/** QSPI Read command state read start */
#define QSPI_CMD_READ_STATE_READ_START      (0x0UL)
/** QSPI Read command state read data */
#define QSPI_CMD_READ_STATE_READ_DATA       (0x1UL)
/** QSPI Read command state read stop */
#define QSPI_CMD_READ_STATE_READ_STOP       (0x2UL)
/** QSPI Read command state exit */
#define QSPI_CMD_READ_STATE_EXIT            (0x3UL)
/** QSPI Xfer command state transfer start */
#define QSPI_CMD_XFER_STATE_XFER_START      (0xAUL)
/** QSPI Xfer command state read data */
#define QSPI_CMD_XFER_STATE_READ_DATA       (0xBUL)
/** QSPI Xfer command state transfer stop */
#define QSPI_CMD_XFER_STATE_XFER_STOP       (0xCUL)
/** QSPI Xfer command state exit */
#define QSPI_CMD_XFER_STATE_EXIT            (0xDUL)

/* QSPI */
#define QSPI_MAX_HW_ID      (FLS_NUM_OF_QSPI_CONFIG)
#define QSPI0_BASE          (0xFF0F0000UL) /* QSPI */
#define QSPI1_BASE          (0xFF0F0800UL) /* DMA */
#define QSPI0_INT_NUM       (0x2AUL)
#define QSPI1_INT_NUM       (0x4BUL)
#define QSPI_INT_NUM(aID)   ((aID == 0UL) ? QSPI0_INT_NUM : QSPI1_INT_NUM)

/**
 * Flag for transfer continuation
 */
typedef uint32 QSPI_XferFlagType;
#define QSPI_XFER_STOP          (0x0UL)   /**< Transfer stop flag */
#define QSPI_XFER_CONTINUE      (0x1UL)   /**< Transfer continue flag */
#define QSPI_XFER_NOT_STOP      (0x2UL)   /**< Don't call stop flag */

/* Macros */
#define MSPI_FIFO_LEN           (0x100UL) // Try matching page size @256bytes //(0x40UL) /**< MSPI FIFO length in bytes*/
#define RAF_FIFO_LEN            (0x100UL) /**< RAF FIFO length in bytes */


#define QSPI_GCR1_DEVICE_ENABLE 0x01000000

/*
 * Identification of Flash
 * Micron:
 * Byte 0 is Manufacturer ID;
 * Byte 1 is first byte of Device ID - 0xBB or 0xBA
 * Byte 2 is second byte of Device ID describes flash size:
 * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
 * Spansion:
 * Byte 0 is Manufacturer ID;
 * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
 * Byte 2 is second byte of Device ID describes flash size:
 * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
 */

#define MICRON_ID       (0x20U)
#define SPANSION_ID     (0x01U)
#define WINBOND_ID      (0xEFU)
#define MACRONIX_ID     (0xC2U)


/* Macronix size constants are different for 512M and 1G */
#define MACRONIX_FLASH_SIZE_ID_512M    (0x1AU)
#define MACRONIX_FLASH_SIZE_ID_1G    (0x1BU)

/*
 * Size in bytes
 */
#define FLS_SIZE_64M         (0x0800000U)
#define FLS_SIZE_128M        (0x1000000U)
#define FLS_SIZE_256M        (0x2000000U)
#define FLS_SIZE_512M        (0x4000000U)
#define FLS_SIZE_1G          (0x8000000U)

#define WRITE_ENABLE_CMD      (0x06U)
#define BANK_REG_RD_CMD       (0x16U)
#define BANK_REG_WR_CMD       (0x17U)
/* Bank register is called Extended Address Reg in Micron */
#define EXTADD_REG_RD_CMD     (0xC8U)
#define EXTADD_REG_WR_CMD     (0xC5U)

/* FLASH instruction */
#define FLS_COMMAND_OFFSET    (0x0U)
/* MSB byte of address to read or write */
#define FLS_ADDRESS_1_OFFSET  (0x1U)
/* Middle byte of address to read or write */
#define FLS_ADDRESS_2_OFFSET  (0x2U)
/* Middle byte of address to read or write */
#define FLS_ADDRESS_3_OFFSET  (0x3U)
/* LSB byte of address to read or write */
#define FLS_ADDRESS_4_OFFSET  (0x4U)


/*
 * Common flash commands followed by many flash manufacturer.
 * NOTE: Apart for these commands, there are extended commands
 * which differs among manufacturers.
 */
#define FLS_CMD_READ              (0x03)  /**< Read */
#define FLS_CMD_FAST_READ         (0x0B)  /**< Fast read */
#define FLS_CMD_4FAST_READ        (0x0C)  /**< 4 Bytes Fast read */
#define FLS_CMD_RDID              (0x9F)  /**< Read ID */
#define FLS_CMD_WRR               (0x01)  /**< Write register  - used to write register SR1 - Config Reg 1,2,3 */
#define FLS_CMD_WREN              (0x06)  /**< Write enable */
#define FLS_CMD_WRENV             (0x50)  /**< Write Enable for Volatile Status and Configuration Registers - Device specific*/
#define FLS_CMD_WRDI              (0x04)  /**< Write disable */
#define FLS_CMD_RDSR              (0x05)  /**< Read status */
#define FLS_CMD_RCFR              (0x35)  /**< Read configuration */
#define FLS_CMD_WRSR              (0x01)  /**< Write status */
#define FLS_CMD_PP                (0x02)  /**< Page program */
#define FLS_CMD_SSE               (0x20)  /**< Sub-sector erase */
#define FLS_CMD_SE                (0xD8)  /**< Sector erase */
#define FLS_CMD_BE                (0xC7)  /**< Bulk erase */
#define FLS_CMD_RES               (0xAB)  /**< Read electronic signature */
#define FLS_CMD_DOFR              (0x3B)  /**< Dual output fast read */
#define FLS_CMD_DIOFR             (0xBB)  /**< Dual input/ouput fast read */
#define FLS_CMD_QOFR              (0x6B)  /**< Quad output fast read */
#define FLS_CMD_QIOFR             (0xEB)  /**< Quad input/output fast read*/
#define FLS_CMD_4BEN              (0xB7)  /**< Enter 4 bytes address mode */
#define FLS_CMD_4BEX              (0xE9)  /**< Exit 4 bytes address mode */

/**< write ENHANCED VOLATILECONFIGURATION register*/
#define FLS_CMD_WEVCR             (0x61)
/**< Read ENHANCED VOLATILECONFIGURATION register*/
#define FLS_CMD_REVCR             (0x65)

/* Common statuses */
#define FLS_XST_SUCCESS                     0x0L
#define FLS_XST_FAILURE                     0x1L
#define FLS_XST_DEVICE_NOT_FOUND            0x2L
#define FLS_XST_DEVICE_BLOCK_NOT_FOUND      0x3L
#define FLS_XST_INVALID_VERSION             0x4L
#define FLS_XST_DEVICE_IS_STARTED           0x5L
#define FLS_XST_DEVICE_IS_STOPPED           0x6L
#define FLS_XST_FIFO_ERROR                  0x7L
#define FLS_XST_DEVICE_BUSY                 21L  /* device is busy */



/**
 * QSPI config data
 *
 */
#define FLS_XQSPI_TXD_RXD_DEPTH                0x120U //256 bytes to write a page at a time + 6  (1byte cmd / 4 bytes address / 1 byte dummy
                                                     //+ margin for fast read command with dummy cycles
                                                     // Used for both Tx and Rx
#define FLS_XQSPI_CONNECTION_MODE_SINGLE      0x0U
#define FLS_XQSPI_CONNECTION_MODE_STACKED     0x1U
#define FLS_XQSPI_CONNECTION_MODE_PARALLEL    0x2U

/**
 * QSPI config structure
 */

typedef struct {
  /**< SPI mode */
  FLS_QSPIModeType      ulFlsQspiHwMode;
  /**< SPI speed */
  uint32                ulFlsQspiBaudRateDiv;
   /**< Read lane config */
  FLS_QSPIReadLaneType  ulFlsQspiBusWidth;
  /**<Input clock to QSPI block in MHz */
  uint8                 ucFlsQspiConnectionMode;
} QSPI_ConfigType;

/**
 * QSPI command information structure
 */
typedef struct {
  /** Pointer to transmit data buffer passed during QSPI command call */
  const uint8 *     pCmdTxData;
  /** Pointer to receive data buffer passed during QSPI command call */
  uint8 *           pCmdRxData;
  /** Flash address passed during QSPI command call */
  uint32            ulCmdAddr;
  /** Length passed during QSPI command call */
  uint32            ulCmdLen;
  /** Xfer flag passed during QSPI command call */
  QSPI_XferFlagType  ulCmdFlag;
  /** Pointer to transmit data buffer during command processing */
  const uint8 *     pTmpTxData;
  /** Pointer to receive data buffer during command processing */
  uint8 *           pTmpRxData;
  /** Flash address during command processing */
  uint32            ulTmpAddr;
  /** Transmit length during command processing */
  uint32            ulTmpTxLen;
  /** Transmit length remaining during command processing */
  uint32            ulTmpTxLenRem;
  /** Transmit read index during command processing */
  uint32            ulTmpTxRdIdx;
  /** Transmit write index during command processing */
  uint32            ulTmpTxWdIdx;
  /** Transmit length during command processing */
  uint32            ulTmpRxLen;
  /** Transmit length remaining during command processing */
  uint32            ulTmpRxLenRem;
  /** Transmit read index during command processing */
  uint32            ulTmpRxRdIdx;
  /** Transmit write index during command processing */
  uint32            ulTmpRxWrIdx;
  /** Xfer flag passed during command processing */
  QSPI_XferFlagType   ulTmpFlag;
} QSPI_CmdInfoType;

/**
 * QSPI read-write device type
 */
typedef struct {
/**< command being processed */
  QSPI_CmdType        ulCurrCmd;
  /**< Current state of current command */
  QSPI_CmdStateType   ulCurrCmdState;
  /**< current command information */
  QSPI_CmdInfoType    cmdInfo;
} QSPI_RWDevType;

/**
 * This typedef contains configuration information for a flash message.
 */
typedef struct {
  P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxBfrPtr;
  P2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pRxBfrPtr;
  volatile uint32 ulByteCount;
  volatile uint32 ulBusWidth;
  uint32 ulFlags;
  uint8 ucPollData;
  uint32 ulPollTimeout;
  uint8 ucPollStatusCmd;
  uint8 ucPollBusMask;
} Fls_QspiMsgType;

/**
 * This typedef contains configuration information for the device.
 */
typedef struct {
  uint32 ulInputClockHz;  /**< Input clock frequency */
  uint8  ucConnectionMode; /**< Single, Stacked and Parallel mode */
  volatile uint8  ucBusWidth;   /**< Bus width available on board */
} Fls_QspiConfig;


typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, uint32 StatusEvent, uint32 ByteCount);


/**
 * The XQspiPsu driver instance data. The user is required to allocate a
 * variable of this type for every QSPIPSU device in the system. A pointer
 * to a variable of this type is then passed to the driver API functions.
 */
typedef struct {
  Fls_QspiConfig Config;   /**< Configuration structure */
  uint32 IsReady;     /**< Device is initialized and ready */
  /**< Buffer to send (state) */
  P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pSendBufferPtr;
  /**< Buffer to receive (state) */
  P2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pRecvBufferPtr;
  /**< Gen FIFO entries */
  P2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pGenFifoBufferPtr;
  /**< Number of bytes to transfer (state) */
  uint32 ulTxBytes;
  /**< Number of bytes left to transfer(state) */
  uint32 ulRxBytes;
  /**< Number of Gen FIFO entries remaining */
  uint32 ulGenFifoEntries;
  /**< A transfer is in progress (state) */
  uint32 ulIsBusy;
  /**< DMA or IO mode */
  uint32 ulReadMode;
  uint32 ulGenFifoCS;
  uint32 ulGenFifoBus;
  uint32 ulBusConnectionMode;
  uint32 ulNumMsg;
  uint32 ulMsgCnt;
  uint32 ulIsUnaligned;
  uint8 ucIsManualstart;
  P2VAR(Fls_QspiMsgType, AUTOMATIC, FLS_APPL_DATA) pMsg;
  XQspiPsu_StatusHandler pfStatusHandler;
  void *StatusRef;
} XQspiConfigType;

/********** Private Functions ****************/
//#define FLS_START_SEC_CODE_SLOW_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(void, FLS_CODE_SLOW) Fls_QspiHwInit(P2CONST(QSPI_ConfigType, AUTOMATIC, FLS_APPL_DATA) pConfig);
//#define FLS_STOP_SEC_CODE_SLOW_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_SLOW_ASIL_C
//#include "Fls_MemMap.h"
//#if (FLS_4BYTE_ADDRESS_MODE == STD_ON)
//static FUNC(void, FLS_CODE_SLOW) Fls_Enable4ByteAddressing(void);
//#endif
//#define FLS_STOP_SEC_CODE_SLOW_ASIL_C
//#include "Fls_MemMap.h"
//
#define FLS_START_SEC_CODE_SLOW_ASIL_C
#include "Fls_MemMap.h"
static FUNC(void, FLS_CODE_SLOW) Fls_setFlashModeGeneric(void);
#define FLS_STOP_SEC_CODE_SLOW_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
extern FUNC(uint32, FLS_CODE_FAST) Fls_DMA_IsBusy(void);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_ReadStateHandler(CONSTP2VAR(uint32, AUTOMATIC, FLS_APPL_DATA) pIsTrigAgain);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_XferStateHandler(CONSTP2VAR(uint32, AUTOMATIC, FLS_APPL_DATA) pIsTrigAgain);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(void, FLS_CODE_FAST) Fls_QSPI_XferStart(void);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(void, FLS_CODE_FAST) Fls_QSPI_XferStop(void);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_ReadStart(void);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_ReadStop(void);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//
//#define FLS_START_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"
//static FUNC(uint32, FLS_CODE_FAST) Fls_Qspi_PolledTransfer( P2VAR(XQspiConfigType, AUTOMATIC, FLS_APPL_DATA) pInstancePtr,
//        P2VAR(Fls_QspiMsgType, AUTOMATIC, FLS_APPL_DATA) pMsg, VAR(uint32, AUTOMATIC) ulNumMsg);
//#define FLS_STOP_SEC_CODE_FAST_ASIL_C
//#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
FUNC(uint32, FLS_CODE_FAST) spiTransmitDataByByte(P2VAR(spiBASE_t,AUTOMATIC,FLS_APPL_DATA) spi,
                                                  P2VAR(spiDAT1_t,AUTOMATIC,FLS_APPL_DATA) dataconfig_t,
                                                  VAR(uint32,FLS_APPL_DATA) blocksize,
                                                  P2VAR(uint8,AUTOMATIC,FLS_APPL_DATA) srcbuff);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
FUNC(uint32, FLS_CODE_FAST) spiSendDummyDataByByte(P2VAR(spiBASE_t,AUTOMATIC,FLS_APPL_DATA) spi,
                                                 P2VAR(spiDAT1_t,AUTOMATIC,FLS_APPL_DATA) dataconfig_t,
                                                 VAR(uint32,FLS_APPL_DATA) blocksize);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
FUNC(uint32, FLS_CODE_FAST) spiReceiveDataByByte(P2VAR(spiBASE_t,AUTOMATIC,FLS_APPL_DATA) spi,
                                                 P2VAR(spiDAT1_t,AUTOMATIC,FLS_APPL_DATA) dataconfig_t,
                                                 VAR(uint32,FLS_APPL_DATA) blocksize,
                                                 P2VAR(uint8,AUTOMATIC,FLS_APPL_DATA) destbuff);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
FUNC(uint32, FLS_CODE_FAST )spiTransmitAndReceiveDataByByte(P2VAR(spiBASE_t,AUTOMATIC,FLS_APPL_DATA) spi,
                                                            P2VAR(spiDAT1_t,AUTOMATIC,FLS_APPL_DATA) dataconfig_t,
                                                            VAR(uint32,FLS_APPL_DATA) blocksize,
                                                            P2VAR(uint8,AUTOMATIC,FLS_APPL_DATA) srcbuff,
                                                            P2VAR(uint8,AUTOMATIC,FLS_APPL_DATA) destbuff,
                                                            VAR(uint32,FLS_APPL_DATA) numRxBytesToDiscardBeforeRealRxData);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
//#define FLS_START_SEC_CODE_SLOW_ASIL_C
//#include "Fls_MemMap.h"
//
//static FUNC(uint32, FLS_CODE_SLOW) Fls_Qspi_PolledTransferWithOutIntr(
//               P2VAR(XQspiConfigType, AUTOMATIC, FLS_APPL_DATA) pInstancePtr,
//               P2VAR(Fls_QspiMsgType, AUTOMATIC, FLS_APPL_DATA) pMsg,
//               VAR(uint32, AUTOMATIC) ulNumMsg);
//
//#define FLS_STOP_SEC_CODE_SLOW_ASIL_C
//#include "Fls_MemMap.h"


/********** Public Functions ****************/
#define FLS_START_SEC_CODE_SLOW_ASIL_C
#include "Fls_MemMap.h"
/** @brief QSPI initialisation
 *
 * This API initialises QSPI controller. Initialise controller and verify the
 * presence of Flash(in case of external flash)
 *
 * @param[in]   aID             Controller index
 * @param[in]   config          Pointer to QSPI configurations
 *
 * @return      void
 */
extern FUNC(Std_ReturnType, FLS_CODE_SLOW) Fls_QSPI_Init(P2CONST(QSPI_ConfigType, AUTOMATIC, FLS_APPL_DATA) pConfig);

#define FLS_STOP_SEC_CODE_SLOW_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
/** @brief QSPI Busy
 *
 * This API to check QSPI is busy or not in processing any command.
 *
 * @param[in]   aID             Controller index
 *
 * @retVal      TRUE            QSPI busy processing command
 * @retVal      FALSE           QSPI not processing any command
 */
extern FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_IsBusy(void);

#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
/** @brief QSPI command handler
 *
 * This API to trigger QSPI command state machine. State machine shall take
 * appropriate action based on the command in process.
 *
 * @param[in]   aID             Controller index
 * @param[in]   aIsErr          Error flag
 *ulIsErr
 * @return      void
 */
extern FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_CmdHandler(VAR(uint32, AUTOMATIC) ulIsErr);

#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

extern FUNC(uint32, FLS_CODE_FAST) Fls_SPI_ReadFlsDeviceReg(P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxData,
                                                           P2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pRxData,
                                                           VAR(uint32, AUTOMATIC) ulLen);

#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

extern FUNC(uint32, FLS_CODE_FAST) Fls_SPI_SendCmdFlsDevice(P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxData,
                                                           VAR(uint32, AUTOMATIC) ulLen);

#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
extern FUNC(uint32, FLS_CODE_FAST)FLS_SPI_ProcessFastReadCmd(P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxData,
                                                             P2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pRxData,
                                                             VAR(uint32, AUTOMATIC) ulLen);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"
extern FUNC(uint32, FLS_CODE_FAST)FLS_SPI_ProcessWriteCmd(P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxCmdBuff,
                                                          P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxData,
                                                          VAR(uint32, AUTOMATIC) ulLenDataToWrite);
#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

/** @brief QSPI Read
 *
 * This API for read operation using QSPI controller.
 *
 * @param[in]   aID             Controller index
 * @param[in]   aData           Pointer to receive data buffer
 * @param[in]   aLen            Length of data buffer
 *
 * @retval      ERR_INVAL_STATE Interface called in wrong state
 * @retval      ERR_TIME_OUT    Timeout happened during start
 * @retval      ERR_UNKNOWN     Unknown error
 */
extern FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_Read(VAR(uint32, AUTOMATIC) ulAddr,
                                                 P2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pData,
                                                 VAR(uint32, AUTOMATIC) ulLen);

#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#define FLS_START_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"


/** @brief QSPI transfer
 *
 * This API is to transfer data using QSPI controller.
 *
 * @param[in]   aID             Controller index
 * @param[in]   aTxData         Pointer to transmit data buffer
 * @param[in]   aRxData         Pointer to receive data buffer
 * @param[in]   aLen            Length of data buffer
 * @param[in]   aFlag           Transfer flag
 *
 * @retval      ERR_INVAL_STATE Interface called in wrong state
 * @retval      ERR_UNKNOWN     Unknown error
 */
extern FUNC(uint32, FLS_CODE_FAST) Fls_QSPI_Xfer(P2CONST(uint8, AUTOMATIC, FLS_APPL_DATA) pTxData,
                                                 CONSTP2VAR(uint8, AUTOMATIC, FLS_APPL_DATA) pRxData,
                                                 VAR(uint32, AUTOMATIC)  ulLen,
                                                 VAR(QSPI_XferFlagType, AUTOMATIC) ulFlag,
                                                 VAR(uint8, AUTOMATIC) isCmd);

#define FLS_STOP_SEC_CODE_FAST_ASIL_C
#include "Fls_MemMap.h"

#endif /* MCAL_FLS_INCLUDE_FLS_SPI_H_ */


