Readme

Example Summary

This example configures MCLK frequency to 80 MHz by using the SYSPLL to convert SYSOSC from 32 MHz to 80 MHz. SYSPLLCLK2X is passed to MCLK and configured as its source. Since MCLK isn’t mapped to CLK_OUT pin, SYSPLLCLK1 will be routed to CLK_OUT instead and is configured to be half the speed of SYSPLLCLK2X. Thus, CLK_OUT will have a 40MHz signal that can be measured.

Not valid on all devices that do not support up to 80MHz.

Peripherals & Pin Assignments

• CLK_OUT

  • PA14

    BoosterPacks, Board Resources & Jumper Settings

    // TODO UPDATE README FILE THIS SECTION IS TO BE UPDATED. Please refer to Launchpad User’s Guide for additional details on how to enable/access pins

Example Usage

Run the example and connect the pin used for CLK_OUT to a oscilloscope or a logic analyzer to measure the clock frequency.