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-uinterruptVectors
--stack_size=64

MEMORY
{
    INT_VECS		(RX)  : origin = 0x00001800, length = 0x000000C0
    FLASH           (RX)  : origin = 0x000018C0, length = 0x00002C00
    SRAM            (RWX) : origin = 0x20000000, length = 0x00000400
    BCR_CONFIG      (R)   : origin = 0x41C00000, length = 0x00000080
}

SECTIONS
{
    .intvecs:   > INT_VECS
    .text   : palign(8) {} > FLASH
    .const  : palign(8) {} > FLASH
    .cinit  : palign(8) {} > FLASH
    .pinit  : palign(8) {} > FLASH
    .rodata : palign(8) {} > FLASH
    .ARM.exidx    : palign(8) {} > FLASH
    .init_array   : palign(8) {} > FLASH
    .binit        : palign(8) {} > FLASH
    .TI.ramfunc   : load = FLASH, palign(8), run=SRAM, table(BINIT)

    .vtable :   > SRAM
    .args   :   > SRAM
    .data   :   > SRAM
    .bss    :   > SRAM
    .sysmem :   > SRAM
    .stack  :   > SRAM (HIGH)

    .BCRConfig  : {} > BCR_CONFIG
}
