[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x Initialization Scripts Launched. Please Wait...
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: ***AM261x Checks sequence Launched...
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x_Cryst_Clock_Loss_Status() Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x_SOP_Mode() Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000002
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: QSPI - 1S Functional boot mode
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x_Read_Device_Type() Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x_dual_or_lockstep_mode() Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000100
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 is in Lockstep mode ***
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: *** Note:Please call this function for Dual Core switch: Dual_core_switch()
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: Control_MMR_Register_Unlock() Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS_CTRL Control Registers Unlocked
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: Configure_R5F0() Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: ZFG - 13.25 mm x 13.25 mm Package
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: ***PLL lock sequence Launched
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete for 500MHZ
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: PER PLL Configuration Completed
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: ETH PLL Configuration Completed
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: **Clocks Programmed** R5F=500MHz and SYS_CLK=250MHz
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x R5F running at 500Mhz
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: Switch to dual core mode
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x Dual core switch
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: AM261x TCM MEM init Done
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 is in Dual core mode ***
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (250MHz)
[4/22/2026, 11:24:51 AM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (192MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (166.67MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: OSPI1 Clock Enabled (166.67MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling ICSSM0/1 Core Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: ICSSM0_CORE Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: ICSSM1_CORE Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling ICSSM0/1 UART0 Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: ICSSM0_UART0 Clock Enabled (160MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: ICSSM1_UART0 Clock Enabled (160MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:1] Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling GPMC Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: GPMC Clock Enabled (100MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling ELM Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: ELM Clock Enabled (50MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (50MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (50MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (50MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (50MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (500MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled for 500MHz PLL Configuration***
[4/22/2026, 11:24:52 AM] [INFO] Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL on program load.
[4/22/2026, 11:24:55 AM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x0
[4/22/2026, 11:24:58 AM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x81000
[4/22/2026, 11:25:04 AM] [INFO] Cortex_R5_0: Writing 1 chunk at offset 0x100000
[4/22/2026, 11:25:09 AM] [SUCCESS] Program Load completed successfully.