// Core Registers (Cortex-M0+) // System Control PER.Set.simple ESD:0xE000E010 %Long 0x0 // STCSR PER.Set.simple ESD:0xE000E014 %Long 0xFFFFFF // STRVR PER.Set.simple ESD:0xE000E018 %Long 0xFFFFFF // STCVR // PER.Set.simple ESD:0xE000E01C %Long 0x0 // STCR; reason=read-only // PER.Set.simple ESD:0xE000ED00 %Long 0x410CC601 // CPUID; reason=read-only PER.Set.simple ESD:0xE000ED04 %Long 0x425003 // ICSR PER.Set.simple ESD:0xE000ED08 %Long 0x20200000 // VTOR PER.Set.simple ESD:0xE000ED0C %Long 0xFA050000 // AIRCR PER.Set.simple ESD:0xE000ED10 %Long 0x0 // SCR // PER.Set.simple ESD:0xE000ED14 %Long 0x208 // CCR; reason=read-only PER.Set.simple ESD:0xE000ED1C %Long 0x0 // SHPR2 PER.Set.simple ESD:0xE000ED20 %Long 0x0 // SHPR3 PER.Set.simple ESD:0xE000ED24 %Long 0x0 // SHCSR // Memory Protection Unit (MPU) // PER.Set.simple ESD:0xE000ED90 %Long 0x800 // MPU_TYPE; reason=read-only PER.Set.simple ESD:0xE000ED94 %Long 0x0 // MPU_CTRL PER.Set.simple ESD:0xE000ED98 %Long 0x7 // MPU_RNR // MPU regions PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x0 ESD:0xE000ED9C %Long 0xFFFFFF00 // MPU_RBAR0 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x0 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR0 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x1 ESD:0xE000ED9C %Long 0xFFFFFF01 // MPU_RBAR1 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x1 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR1 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x2 ESD:0xE000ED9C %Long 0xFFFFFF02 // MPU_RBAR2 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x2 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR2 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x3 ESD:0xE000ED9C %Long 0xFFFFFF03 // MPU_RBAR3 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x3 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR3 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x4 ESD:0xE000ED9C %Long 0xFFFFFF04 // MPU_RBAR4 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x4 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR4 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x5 ESD:0xE000ED9C %Long 0xFFFFFF05 // MPU_RBAR5 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x5 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR5 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x6 ESD:0xE000ED9C %Long 0xFFFFFF06 // MPU_RBAR6 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x6 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR6 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x7 ESD:0xE000ED9C %Long 0xFFFFFF07 // MPU_RBAR7 PER.Set.SaveIndex ESD:0xE000ED98 %Long 0x7 ESD:0xE000EDA0 %Long 0x1707FF3E // MPU_RASR7 // Nested Vectored Interrupt Controller (NVIC) // Interrupt Enable Registers PER.Set.simple ESD:0xE000E100 %Long 0x200000 // SET/CLREN // Interrupt Pending Registers PER.Set.simple ESD:0xE000E200 %Long 0x200000 // SET/CLRPEN // Interrupt Priority Registers PER.Set.simple ESD:0xE000E400 %Long 0x0 // INT0 PER.Set.simple ESD:0xE000E404 %Long 0x0 // INT1 PER.Set.simple ESD:0xE000E408 %Long 0x0 // INT2 PER.Set.simple ESD:0xE000E40C %Long 0x0 // INT3 PER.Set.simple ESD:0xE000E410 %Long 0x0 // INT4 PER.Set.simple ESD:0xE000E414 %Long 0x8000 // INT5 PER.Set.simple ESD:0xE000E418 %Long 0x0 // INT6 PER.Set.simple ESD:0xE000E41C %Long 0x0 // INT7 // Debug // Core Debug PER.Set.simple ESD:0xE000ED30 %Long 0x9 // DFSR PER.Set.simple ESD:0xE000EDF0 %Long 0x30003 // DHCSR PER.Set.simple ESD:0xE000EDF8 %Long 0x0 // DCRDR PER.Set.simple ESD:0xE000EDFC %Long 0x1000401 // DEMCR // Breakpoint Unit (BPU) PER.Set.simple ESD:0xE0002000 %Long 0x40 // BP_CTRL PER.Set.simple ESD:0xE0002008 %Long 0x0 // B_COMP0 PER.Set.simple ESD:0xE000200C %Long 0x0 // B_COMP1 PER.Set.simple ESD:0xE0002010 %Long 0x0 // B_COMP2 PER.Set.simple ESD:0xE0002014 %Long 0x0 // B_COMP3 // Data Watchpoint and Trace Unit (DWT) // PER.Set.simple ESD:0xE0001000 %Long 0x20000000 // DW_CTRL; reason=read-only // PER.Set.simple ESD:0xE000101C %Long 0xFFFFFFFF // DW_PCSR; reason=read-only PER.Set.simple ESD:0xE0001020 %Long 0x0 // DW_COMP0 PER.Set.simple ESD:0xE0001024 %Long 0x0 // DW_MASK0 PER.Set.simple ESD:0xE0001028 %Long 0x0 // DW_FUNCTION0 PER.Set.simple ESD:0xE0001030 %Long 0x0 // DW_COMP1 PER.Set.simple ESD:0xE0001034 %Long 0x0 // DW_MASK1 PER.Set.simple ESD:0xE0001038 %Long 0x0 // DW_FUNCTION1 // ADC (Analog-to-Digital Converter) // ADC // ADC0 (PERIPHERALREGION) PER.Set.simple ASD:0x40000400 %Long 0x0 // ADC0_FSUB_0 PER.Set.simple ASD:0x40000444 %Long 0x0 // ADC0_FPUB_1 // ADC0_CPU_INT[%s] // PER.Set.simple ASD:0x40001020 %Long 0x0 // ADC0_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40001028 %Long 0x0 // ADC0_CPU_INT_IMASK // PER.Set.simple ASD:0x40001030 %Long 0x0 // ADC0_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40001038 %Long 0x0 // ADC0_CPU_INT_MIS; reason=read-only // ADC0_DMA_TRIG[%s] // PER.Set.simple ASD:0x40001080 %Long 0x0 // ADC0_DMA_TRIG_IIDX; reason=read-only PER.Set.simple ASD:0x40001088 %Long 0x0 // ADC0_DMA_TRIG_IMASK // PER.Set.simple ASD:0x40001090 %Long 0x0 // ADC0_DMA_TRIG_RIS; reason=read-only // PER.Set.simple ASD:0x40001098 %Long 0x0 // ADC0_DMA_TRIG_MIS; reason=read-only // ADC0_GEN_EVENT[%s] // PER.Set.simple ASD:0x40001050 %Long 0x0 // ADC0_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x40001058 %Long 0x0 // ADC0_GEN_EVENT_IMASK // PER.Set.simple ASD:0x40001060 %Long 0x0 // ADC0_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x40001068 %Long 0x0 // ADC0_GEN_EVENT_MIS; reason=read-only // ADC0_GPRCM[%s] PER.Set.simple ASD:0x40000800 %Long 0x0 // ADC0_PWREN PER.Set.simple ASD:0x40000808 %Long 0x0 // ADC0_CLKCFG // PER.Set.simple ASD:0x40000814 %Long 0x10000 // ADC0_STAT; reason=read-only // PER.Set.simple ASD:0x400010E0 %Long 0x0 // ADC0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400010FC %Long 0x0 // ADC0_DESC; reason=read-only PER.Set.simple ASD:0x40001100 %Long 0x0 // ADC0_CTL0 PER.Set.simple ASD:0x40001104 %Long 0x0 // ADC0_CTL1 PER.Set.simple ASD:0x40001108 %Long 0x0 // ADC0_CTL2 PER.Set.simple ASD:0x40001110 %Long 0x0 // ADC0_CLKFREQ PER.Set.simple ASD:0x40001114 %Long 0x0 // ADC0_SCOMP0 PER.Set.simple ASD:0x40001118 %Long 0x0 // ADC0_SCOMP1 PER.Set.simple ASD:0x40001148 %Long 0x0 // ADC0_WCLOW PER.Set.simple ASD:0x40001150 %Long 0x0 // ADC0_WCHIGH PER.Set.simple ASD:0x40001180 %Long 0x0 // ADC0_MEMCTL[0] PER.Set.simple ASD:0x40001184 %Long 0x0 // ADC0_MEMCTL[1] PER.Set.simple ASD:0x40001188 %Long 0x0 // ADC0_MEMCTL[2] PER.Set.simple ASD:0x4000118C %Long 0x0 // ADC0_MEMCTL[3] PER.Set.simple ASD:0x40001190 %Long 0x0 // ADC0_MEMCTL[4] PER.Set.simple ASD:0x40001194 %Long 0x0 // ADC0_MEMCTL[5] PER.Set.simple ASD:0x40001198 %Long 0x0 // ADC0_MEMCTL[6] PER.Set.simple ASD:0x4000119C %Long 0x0 // ADC0_MEMCTL[7] PER.Set.simple ASD:0x400011A0 %Long 0x0 // ADC0_MEMCTL[8] PER.Set.simple ASD:0x400011A4 %Long 0x0 // ADC0_MEMCTL[9] PER.Set.simple ASD:0x400011A8 %Long 0x0 // ADC0_MEMCTL[10] PER.Set.simple ASD:0x400011AC %Long 0x0 // ADC0_MEMCTL[11] PER.Set.simple ASD:0x400011B0 %Long 0x0 // ADC0_MEMCTL[12] PER.Set.simple ASD:0x400011B4 %Long 0x0 // ADC0_MEMCTL[13] PER.Set.simple ASD:0x400011B8 %Long 0x0 // ADC0_MEMCTL[14] PER.Set.simple ASD:0x400011BC %Long 0x0 // ADC0_MEMCTL[15] PER.Set.simple ASD:0x400011C0 %Long 0x0 // ADC0_MEMCTL[16] PER.Set.simple ASD:0x400011C4 %Long 0x0 // ADC0_MEMCTL[17] PER.Set.simple ASD:0x400011C8 %Long 0x0 // ADC0_MEMCTL[18] PER.Set.simple ASD:0x400011CC %Long 0x0 // ADC0_MEMCTL[19] PER.Set.simple ASD:0x400011D0 %Long 0x0 // ADC0_MEMCTL[20] PER.Set.simple ASD:0x400011D4 %Long 0x0 // ADC0_MEMCTL[21] PER.Set.simple ASD:0x400011D8 %Long 0x0 // ADC0_MEMCTL[22] PER.Set.simple ASD:0x400011DC %Long 0x0 // ADC0_MEMCTL[23] // PER.Set.simple ASD:0x40001340 %Long 0x0 // ADC0_STATUS; reason=read-only // ADC0_SVT (PERIPHERALREGIONSVT) // PER.Set.simple ASD:0x40AAC160 %Long 0x0 // ADC0_SVT_FIFODATA; reason=read-only // PER.Set.simple ASD:0x40AAC280 %Long 0x0 // ADC0_SVT_MEMRES[0]; reason=read-only // PER.Set.simple ASD:0x40AAC284 %Long 0x0 // ADC0_SVT_MEMRES[1]; reason=read-only // PER.Set.simple ASD:0x40AAC288 %Long 0x0 // ADC0_SVT_MEMRES[2]; reason=read-only // PER.Set.simple ASD:0x40AAC28C %Long 0x0 // ADC0_SVT_MEMRES[3]; reason=read-only // PER.Set.simple ASD:0x40AAC290 %Long 0x0 // ADC0_SVT_MEMRES[4]; reason=read-only // PER.Set.simple ASD:0x40AAC294 %Long 0x0 // ADC0_SVT_MEMRES[5]; reason=read-only // PER.Set.simple ASD:0x40AAC298 %Long 0x0 // ADC0_SVT_MEMRES[6]; reason=read-only // PER.Set.simple ASD:0x40AAC29C %Long 0x0 // ADC0_SVT_MEMRES[7]; reason=read-only // PER.Set.simple ASD:0x40AAC2A0 %Long 0x0 // ADC0_SVT_MEMRES[8]; reason=read-only // PER.Set.simple ASD:0x40AAC2A4 %Long 0x0 // ADC0_SVT_MEMRES[9]; reason=read-only // PER.Set.simple ASD:0x40AAC2A8 %Long 0x0 // ADC0_SVT_MEMRES[10]; reason=read-only // PER.Set.simple ASD:0x40AAC2AC %Long 0x0 // ADC0_SVT_MEMRES[11]; reason=read-only // PER.Set.simple ASD:0x40AAC2B0 %Long 0x0 // ADC0_SVT_MEMRES[12]; reason=read-only // PER.Set.simple ASD:0x40AAC2B4 %Long 0x0 // ADC0_SVT_MEMRES[13]; reason=read-only // PER.Set.simple ASD:0x40AAC2B8 %Long 0x0 // ADC0_SVT_MEMRES[14]; reason=read-only // PER.Set.simple ASD:0x40AAC2BC %Long 0x0 // ADC0_SVT_MEMRES[15]; reason=read-only // PER.Set.simple ASD:0x40AAC2C0 %Long 0x0 // ADC0_SVT_MEMRES[16]; reason=read-only // PER.Set.simple ASD:0x40AAC2C4 %Long 0x0 // ADC0_SVT_MEMRES[17]; reason=read-only // PER.Set.simple ASD:0x40AAC2C8 %Long 0x0 // ADC0_SVT_MEMRES[18]; reason=read-only // PER.Set.simple ASD:0x40AAC2CC %Long 0x0 // ADC0_SVT_MEMRES[19]; reason=read-only // PER.Set.simple ASD:0x40AAC2D0 %Long 0x0 // ADC0_SVT_MEMRES[20]; reason=read-only // PER.Set.simple ASD:0x40AAC2D4 %Long 0x0 // ADC0_SVT_MEMRES[21]; reason=read-only // PER.Set.simple ASD:0x40AAC2D8 %Long 0x0 // ADC0_SVT_MEMRES[22]; reason=read-only // PER.Set.simple ASD:0x40AAC2DC %Long 0x0 // ADC0_SVT_MEMRES[23]; reason=read-only // ADC1 (PERIPHERALREGION) PER.Set.simple ASD:0x40002400 %Long 0x0 // ADC1_FSUB_0 PER.Set.simple ASD:0x40002444 %Long 0x0 // ADC1_FPUB_1 // ADC1_CPU_INT[%s] // PER.Set.simple ASD:0x40003020 %Long 0x0 // ADC1_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40003028 %Long 0x0 // ADC1_CPU_INT_IMASK // PER.Set.simple ASD:0x40003030 %Long 0x0 // ADC1_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40003038 %Long 0x0 // ADC1_CPU_INT_MIS; reason=read-only // ADC1_DMA_TRIG[%s] // PER.Set.simple ASD:0x40003080 %Long 0x0 // ADC1_DMA_TRIG_IIDX; reason=read-only PER.Set.simple ASD:0x40003088 %Long 0x0 // ADC1_DMA_TRIG_IMASK // PER.Set.simple ASD:0x40003090 %Long 0x0 // ADC1_DMA_TRIG_RIS; reason=read-only // PER.Set.simple ASD:0x40003098 %Long 0x0 // ADC1_DMA_TRIG_MIS; reason=read-only // ADC1_GEN_EVENT[%s] // PER.Set.simple ASD:0x40003050 %Long 0x0 // ADC1_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x40003058 %Long 0x0 // ADC1_GEN_EVENT_IMASK // PER.Set.simple ASD:0x40003060 %Long 0x0 // ADC1_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x40003068 %Long 0x0 // ADC1_GEN_EVENT_MIS; reason=read-only // ADC1_GPRCM[%s] PER.Set.simple ASD:0x40002800 %Long 0x0 // ADC1_PWREN PER.Set.simple ASD:0x40002808 %Long 0x0 // ADC1_CLKCFG // PER.Set.simple ASD:0x40002814 %Long 0x10000 // ADC1_STAT; reason=read-only // PER.Set.simple ASD:0x400030E0 %Long 0x0 // ADC1_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400030FC %Long 0x0 // ADC1_DESC; reason=read-only PER.Set.simple ASD:0x40003100 %Long 0x0 // ADC1_CTL0 PER.Set.simple ASD:0x40003104 %Long 0x0 // ADC1_CTL1 PER.Set.simple ASD:0x40003108 %Long 0x0 // ADC1_CTL2 PER.Set.simple ASD:0x40003110 %Long 0x0 // ADC1_CLKFREQ PER.Set.simple ASD:0x40003114 %Long 0x0 // ADC1_SCOMP0 PER.Set.simple ASD:0x40003118 %Long 0x0 // ADC1_SCOMP1 PER.Set.simple ASD:0x40003148 %Long 0x0 // ADC1_WCLOW PER.Set.simple ASD:0x40003150 %Long 0x0 // ADC1_WCHIGH PER.Set.simple ASD:0x40003180 %Long 0x0 // ADC1_MEMCTL[0] PER.Set.simple ASD:0x40003184 %Long 0x0 // ADC1_MEMCTL[1] PER.Set.simple ASD:0x40003188 %Long 0x0 // ADC1_MEMCTL[2] PER.Set.simple ASD:0x4000318C %Long 0x0 // ADC1_MEMCTL[3] PER.Set.simple ASD:0x40003190 %Long 0x0 // ADC1_MEMCTL[4] PER.Set.simple ASD:0x40003194 %Long 0x0 // ADC1_MEMCTL[5] PER.Set.simple ASD:0x40003198 %Long 0x0 // ADC1_MEMCTL[6] PER.Set.simple ASD:0x4000319C %Long 0x0 // ADC1_MEMCTL[7] PER.Set.simple ASD:0x400031A0 %Long 0x0 // ADC1_MEMCTL[8] PER.Set.simple ASD:0x400031A4 %Long 0x0 // ADC1_MEMCTL[9] PER.Set.simple ASD:0x400031A8 %Long 0x0 // ADC1_MEMCTL[10] PER.Set.simple ASD:0x400031AC %Long 0x0 // ADC1_MEMCTL[11] PER.Set.simple ASD:0x400031B0 %Long 0x0 // ADC1_MEMCTL[12] PER.Set.simple ASD:0x400031B4 %Long 0x0 // ADC1_MEMCTL[13] PER.Set.simple ASD:0x400031B8 %Long 0x0 // ADC1_MEMCTL[14] PER.Set.simple ASD:0x400031BC %Long 0x0 // ADC1_MEMCTL[15] PER.Set.simple ASD:0x400031C0 %Long 0x0 // ADC1_MEMCTL[16] PER.Set.simple ASD:0x400031C4 %Long 0x0 // ADC1_MEMCTL[17] PER.Set.simple ASD:0x400031C8 %Long 0x0 // ADC1_MEMCTL[18] PER.Set.simple ASD:0x400031CC %Long 0x0 // ADC1_MEMCTL[19] PER.Set.simple ASD:0x400031D0 %Long 0x0 // ADC1_MEMCTL[20] PER.Set.simple ASD:0x400031D4 %Long 0x0 // ADC1_MEMCTL[21] PER.Set.simple ASD:0x400031D8 %Long 0x0 // ADC1_MEMCTL[22] PER.Set.simple ASD:0x400031DC %Long 0x0 // ADC1_MEMCTL[23] // PER.Set.simple ASD:0x40003340 %Long 0x0 // ADC1_STATUS; reason=read-only // ADC1_SVT (PERIPHERALREGIONSVT) // PER.Set.simple ASD:0x40AAE160 %Long 0x0 // ADC1_SVT_FIFODATA; reason=read-only // PER.Set.simple ASD:0x40AAE280 %Long 0x0 // ADC1_SVT_MEMRES[0]; reason=read-only // PER.Set.simple ASD:0x40AAE284 %Long 0x0 // ADC1_SVT_MEMRES[1]; reason=read-only // PER.Set.simple ASD:0x40AAE288 %Long 0x0 // ADC1_SVT_MEMRES[2]; reason=read-only // PER.Set.simple ASD:0x40AAE28C %Long 0x0 // ADC1_SVT_MEMRES[3]; reason=read-only // PER.Set.simple ASD:0x40AAE290 %Long 0x0 // ADC1_SVT_MEMRES[4]; reason=read-only // PER.Set.simple ASD:0x40AAE294 %Long 0x0 // ADC1_SVT_MEMRES[5]; reason=read-only // PER.Set.simple ASD:0x40AAE298 %Long 0x0 // ADC1_SVT_MEMRES[6]; reason=read-only // PER.Set.simple ASD:0x40AAE29C %Long 0x0 // ADC1_SVT_MEMRES[7]; reason=read-only // PER.Set.simple ASD:0x40AAE2A0 %Long 0x0 // ADC1_SVT_MEMRES[8]; reason=read-only // PER.Set.simple ASD:0x40AAE2A4 %Long 0x0 // ADC1_SVT_MEMRES[9]; reason=read-only // PER.Set.simple ASD:0x40AAE2A8 %Long 0x0 // ADC1_SVT_MEMRES[10]; reason=read-only // PER.Set.simple ASD:0x40AAE2AC %Long 0x0 // ADC1_SVT_MEMRES[11]; reason=read-only // PER.Set.simple ASD:0x40AAE2B0 %Long 0x0 // ADC1_SVT_MEMRES[12]; reason=read-only // PER.Set.simple ASD:0x40AAE2B4 %Long 0x0 // ADC1_SVT_MEMRES[13]; reason=read-only // PER.Set.simple ASD:0x40AAE2B8 %Long 0x0 // ADC1_SVT_MEMRES[14]; reason=read-only // PER.Set.simple ASD:0x40AAE2BC %Long 0x0 // ADC1_SVT_MEMRES[15]; reason=read-only // PER.Set.simple ASD:0x40AAE2C0 %Long 0x0 // ADC1_SVT_MEMRES[16]; reason=read-only // PER.Set.simple ASD:0x40AAE2C4 %Long 0x0 // ADC1_SVT_MEMRES[17]; reason=read-only // PER.Set.simple ASD:0x40AAE2C8 %Long 0x0 // ADC1_SVT_MEMRES[18]; reason=read-only // PER.Set.simple ASD:0x40AAE2CC %Long 0x0 // ADC1_SVT_MEMRES[19]; reason=read-only // PER.Set.simple ASD:0x40AAE2D0 %Long 0x0 // ADC1_SVT_MEMRES[20]; reason=read-only // PER.Set.simple ASD:0x40AAE2D4 %Long 0x0 // ADC1_SVT_MEMRES[21]; reason=read-only // PER.Set.simple ASD:0x40AAE2D8 %Long 0x0 // ADC1_SVT_MEMRES[22]; reason=read-only // PER.Set.simple ASD:0x40AAE2DC %Long 0x0 // ADC1_SVT_MEMRES[23]; reason=read-only // AESADV // AESADV (PERIPHERALREGION) // AESADV_GPRCM[%s] PER.Set.simple ASD:0x40442800 %Long 0x0 // AESADV_PWREN // PER.Set.simple ASD:0x40442814 %Long 0x10000 // AESADV_STAT; reason=read-only // PER.Set.simple ASD:0x40443018 %Long 0x0 // AESADV_PDBGCTL; reason=read-only // AESADV_INT_EVENT0[%s] // PER.Set.simple ASD:0x40443020 %Long 0x0 // AESADV_INT_EVENT0_IIDX; reason=read-only PER.Set.simple ASD:0x40443028 %Long 0x0 // AESADV_INT_EVENT0_IMASK // PER.Set.simple ASD:0x40443030 %Long 0x0 // AESADV_INT_EVENT0_RIS; reason=read-only // PER.Set.simple ASD:0x40443038 %Long 0x0 // AESADV_INT_EVENT0_MIS; reason=read-only // AESADV_INT_EVENT1[%s] // PER.Set.simple ASD:0x40443050 %Long 0x0 // AESADV_INT_EVENT1_IIDX; reason=read-only PER.Set.simple ASD:0x40443058 %Long 0x0 // AESADV_INT_EVENT1_IMASK // PER.Set.simple ASD:0x40443060 %Long 0x0 // AESADV_INT_EVENT1_RIS; reason=read-only // PER.Set.simple ASD:0x40443068 %Long 0x0 // AESADV_INT_EVENT1_MIS; reason=read-only // AESADV_INT_EVENT2[%s] // PER.Set.simple ASD:0x40443080 %Long 0x0 // AESADV_INT_EVENT2_IIDX; reason=read-only PER.Set.simple ASD:0x40443088 %Long 0x0 // AESADV_INT_EVENT2_IMASK // PER.Set.simple ASD:0x40443090 %Long 0x0 // AESADV_INT_EVENT2_RIS; reason=read-only // PER.Set.simple ASD:0x40443098 %Long 0x0 // AESADV_INT_EVENT2_MIS; reason=read-only // PER.Set.simple ASD:0x404430E0 %Long 0x0 // AESADV_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40443140 %Long 0x0 // AESADV_IV0 PER.Set.simple ASD:0x40443144 %Long 0x0 // AESADV_IV1 PER.Set.simple ASD:0x40443148 %Long 0x0 // AESADV_IV2 PER.Set.simple ASD:0x4044314C %Long 0x0 // AESADV_IV3 PER.Set.simple ASD:0x40443150 %Long 0x0 // AESADV_CTRL PER.Set.simple ASD:0x40443160 %Long 0x0 // AESADV_DATA0 PER.Set.simple ASD:0x40443164 %Long 0x0 // AESADV_DATA1 PER.Set.simple ASD:0x40443168 %Long 0x0 // AESADV_DATA2 PER.Set.simple ASD:0x4044316C %Long 0x0 // AESADV_DATA3 // PER.Set.simple ASD:0x40443170 %Long 0x0 // AESADV_TAG0; reason=read-only // PER.Set.simple ASD:0x40443174 %Long 0x0 // AESADV_TAG1; reason=read-only // PER.Set.simple ASD:0x40443178 %Long 0x0 // AESADV_TAG2; reason=read-only // PER.Set.simple ASD:0x4044317C %Long 0x0 // AESADV_TAG3; reason=read-only // PER.Set.simple ASD:0x40443180 %Long 0x0 // AESADV_STATUS; reason=read-only // PER.Set.simple ASD:0x40443188 %Long 0x0 // AESADV_DATA_OUT; reason=read-only PER.Set.simple ASD:0x404431D4 %Long 0x0 // AESADV_CCM_ALN_WRD PER.Set.simple ASD:0x404431D8 %Long 0x0 // AESADV_BLK_CNT0 PER.Set.simple ASD:0x404431DC %Long 0x0 // AESADV_BLK_CNT1 PER.Set.simple ASD:0x404431F4 %Long 0x0 // AESADV_DMA_HS // CANFD (FD Controler Area Network) // CANFD0 (PERIPHERALREGION) PER.Set.simple ASD:0x4050E800 %Long 0x0 // CANFD0_PWREN // PER.Set.simple ASD:0x4050E814 %Long 0x10000 // CANFD0_STAT; reason=read-only // CANFD0_MCAN[%s] // PER.Set.simple ASD:0x4050F000 %Long 0x0 // CANFD0_MCAN_CREL; reason=read-only // PER.Set.simple ASD:0x4050F004 %Long 0x0 // CANFD0_MCAN_ENDN; reason=read-only PER.Set.simple ASD:0x4050F00C %Long 0x0 // CANFD0_MCAN_DBTP PER.Set.simple ASD:0x4050F010 %Long 0x0 // CANFD0_MCAN_TEST PER.Set.simple ASD:0x4050F014 %Long 0x0 // CANFD0_MCAN_RWD PER.Set.simple ASD:0x4050F018 %Long 0x0 // CANFD0_MCAN_CCCR PER.Set.simple ASD:0x4050F01C %Long 0x0 // CANFD0_MCAN_NBTP PER.Set.simple ASD:0x4050F020 %Long 0x0 // CANFD0_MCAN_TSCC PER.Set.simple ASD:0x4050F024 %Long 0x0 // CANFD0_MCAN_TSCV PER.Set.simple ASD:0x4050F028 %Long 0x0 // CANFD0_MCAN_TOCC PER.Set.simple ASD:0x4050F02C %Long 0x0 // CANFD0_MCAN_TOCV // PER.Set.simple ASD:0x4050F040 %Long 0x0 // CANFD0_MCAN_ECR; reason=read-only // PER.Set.simple ASD:0x4050F044 %Long 0x0 // CANFD0_MCAN_PSR; reason=read-only PER.Set.simple ASD:0x4050F048 %Long 0x0 // CANFD0_MCAN_TDCR PER.Set.simple ASD:0x4050F050 %Long 0x0 // CANFD0_MCAN_IR PER.Set.simple ASD:0x4050F054 %Long 0x0 // CANFD0_MCAN_IE PER.Set.simple ASD:0x4050F058 %Long 0x0 // CANFD0_MCAN_ILS PER.Set.simple ASD:0x4050F05C %Long 0x0 // CANFD0_MCAN_ILE PER.Set.simple ASD:0x4050F080 %Long 0x0 // CANFD0_MCAN_GFC PER.Set.simple ASD:0x4050F084 %Long 0x0 // CANFD0_MCAN_SIDFC PER.Set.simple ASD:0x4050F088 %Long 0x0 // CANFD0_MCAN_XIDFC PER.Set.simple ASD:0x4050F090 %Long 0x0 // CANFD0_MCAN_XIDAM // PER.Set.simple ASD:0x4050F094 %Long 0x0 // CANFD0_MCAN_HPMS; reason=read-only PER.Set.simple ASD:0x4050F098 %Long 0x0 // CANFD0_MCAN_NDAT1 PER.Set.simple ASD:0x4050F09C %Long 0x0 // CANFD0_MCAN_NDAT2 PER.Set.simple ASD:0x4050F0A0 %Long 0x0 // CANFD0_MCAN_RXF0C // PER.Set.simple ASD:0x4050F0A4 %Long 0x0 // CANFD0_MCAN_RXF0S; reason=read-only PER.Set.simple ASD:0x4050F0A8 %Long 0x0 // CANFD0_MCAN_RXF0A PER.Set.simple ASD:0x4050F0AC %Long 0x0 // CANFD0_MCAN_RXBC PER.Set.simple ASD:0x4050F0B0 %Long 0x0 // CANFD0_MCAN_RXF1C // PER.Set.simple ASD:0x4050F0B4 %Long 0x0 // CANFD0_MCAN_RXF1S; reason=read-only PER.Set.simple ASD:0x4050F0B8 %Long 0x0 // CANFD0_MCAN_RXF1A PER.Set.simple ASD:0x4050F0BC %Long 0x0 // CANFD0_MCAN_RXESC PER.Set.simple ASD:0x4050F0C0 %Long 0x0 // CANFD0_MCAN_TXBC // PER.Set.simple ASD:0x4050F0C4 %Long 0x0 // CANFD0_MCAN_TXFQS; reason=read-only PER.Set.simple ASD:0x4050F0C8 %Long 0x0 // CANFD0_MCAN_TXESC // PER.Set.simple ASD:0x4050F0CC %Long 0x0 // CANFD0_MCAN_TXBRP; reason=read-only PER.Set.simple ASD:0x4050F0D0 %Long 0x0 // CANFD0_MCAN_TXBAR PER.Set.simple ASD:0x4050F0D4 %Long 0x0 // CANFD0_MCAN_TXBCR // PER.Set.simple ASD:0x4050F0D8 %Long 0x0 // CANFD0_MCAN_TXBTO; reason=read-only // PER.Set.simple ASD:0x4050F0DC %Long 0x0 // CANFD0_MCAN_TXBCF; reason=read-only PER.Set.simple ASD:0x4050F0E0 %Long 0x0 // CANFD0_MCAN_TXBTIE PER.Set.simple ASD:0x4050F0E4 %Long 0x0 // CANFD0_MCAN_TXBCIE PER.Set.simple ASD:0x4050F0F0 %Long 0x0 // CANFD0_MCAN_TXEFC // PER.Set.simple ASD:0x4050F0F4 %Long 0x0 // CANFD0_MCAN_TXEFS; reason=read-only PER.Set.simple ASD:0x4050F0F8 %Long 0x0 // CANFD0_MCAN_TXEFA // CANFD0_TI_WRAPPER[%s] // CANFD0_MSP[%s] // CANFD0_CPU_INT[%s] // PER.Set.simple ASD:0x4050F820 %Long 0x0 // CANFD0_IIDX; reason=read-only PER.Set.simple ASD:0x4050F828 %Long 0x0 // CANFD0_IMASK // PER.Set.simple ASD:0x4050F830 %Long 0x0 // CANFD0_RIS; reason=read-only // PER.Set.simple ASD:0x4050F838 %Long 0x0 // CANFD0_MIS; reason=read-only // PER.Set.simple ASD:0x4050F8E0 %Long 0x0 // CANFD0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x4050F8FC %Long 0x0 // CANFD0_DESC; reason=read-only PER.Set.simple ASD:0x4050F900 %Long 0x0 // CANFD0_MCANSS_CLKEN PER.Set.simple ASD:0x4050F904 %Long 0x0 // CANFD0_MCANSS_CLKDIV PER.Set.simple ASD:0x4050F908 %Long 0x0 // CANFD0_MCANSS_CLKCTL // PER.Set.simple ASD:0x4050F90C %Long 0x0 // CANFD0_MCANSS_CLKSTS; reason=read-only // CANFD0_PROCESSORS[%s] // CANFD0_MCAN_ECC_REGS[%s] // PER.Set.simple ASD:0x4050F400 %Long 0x0 // CANFD0_MCANERR_REV; reason=read-only PER.Set.simple ASD:0x4050F408 %Long 0x0 // CANFD0_MCANERR_VECTOR // PER.Set.simple ASD:0x4050F40C %Long 0x0 // CANFD0_MCANERR_STAT; reason=read-only // PER.Set.simple ASD:0x4050F410 %Long 0x0 // CANFD0_MCANERR_WRAP_REV; reason=read-only PER.Set.simple ASD:0x4050F414 %Long 0x0 // CANFD0_MCANERR_CTRL PER.Set.simple ASD:0x4050F418 %Long 0x0 // CANFD0_MCANERR_ERR_CTRL1 PER.Set.simple ASD:0x4050F41C %Long 0x0 // CANFD0_MCANERR_ERR_CTRL2 PER.Set.simple ASD:0x4050F420 %Long 0x0 // CANFD0_MCANERR_ERR_STAT1 // PER.Set.simple ASD:0x4050F424 %Long 0x0 // CANFD0_MCANERR_ERR_STAT2; reason=read-only PER.Set.simple ASD:0x4050F428 %Long 0x0 // CANFD0_MCANERR_ERR_STAT3 PER.Set.simple ASD:0x4050F43C %Long 0x0 // CANFD0_MCANERR_SEC_EOI // PER.Set.simple ASD:0x4050F440 %Long 0x0 // CANFD0_MCANERR_SEC_STATUS; reason=read-only PER.Set.simple ASD:0x4050F480 %Long 0x0 // CANFD0_MCANERR_SEC_ENABLE_SET PER.Set.simple ASD:0x4050F4C0 %Long 0x0 // CANFD0_MCANERR_SEC_ENABLE_CLR PER.Set.simple ASD:0x4050F53C %Long 0x0 // CANFD0_MCANERR_DED_EOI // PER.Set.simple ASD:0x4050F540 %Long 0x0 // CANFD0_MCANERR_DED_STATUS; reason=read-only PER.Set.simple ASD:0x4050F580 %Long 0x0 // CANFD0_MCANERR_DED_ENABLE_SET PER.Set.simple ASD:0x4050F5C0 %Long 0x0 // CANFD0_MCANERR_DED_ENABLE_CLR PER.Set.simple ASD:0x4050F600 %Long 0x0 // CANFD0_MCANERR_AGGR_ENABLE_SET PER.Set.simple ASD:0x4050F604 %Long 0x0 // CANFD0_MCANERR_AGGR_ENABLE_CLR PER.Set.simple ASD:0x4050F608 %Long 0x0 // CANFD0_MCANERR_AGGR_STATUS_SET PER.Set.simple ASD:0x4050F60C %Long 0x0 // CANFD0_MCANERR_AGGR_STATUS_CLR // CANFD0_MCANSS_REGS[%s] // PER.Set.simple ASD:0x4050F200 %Long 0x0 // CANFD0_MCANSS_PID; reason=read-only PER.Set.simple ASD:0x4050F204 %Long 0x0 // CANFD0_MCANSS_CTRL // PER.Set.simple ASD:0x4050F208 %Long 0x0 // CANFD0_MCANSS_STAT; reason=read-only PER.Set.simple ASD:0x4050F20C %Long 0x0 // CANFD0_MCANSS_ICS PER.Set.simple ASD:0x4050F210 %Long 0x0 // CANFD0_MCANSS_IRS PER.Set.simple ASD:0x4050F214 %Long 0x0 // CANFD0_MCANSS_IECS PER.Set.simple ASD:0x4050F218 %Long 0x0 // CANFD0_MCANSS_IE // PER.Set.simple ASD:0x4050F21C %Long 0x0 // CANFD0_MCANSS_IES; reason=read-only PER.Set.simple ASD:0x4050F220 %Long 0x0 // CANFD0_MCANSS_EOI PER.Set.simple ASD:0x4050F224 %Long 0x0 // CANFD0_MCANSS_EXT_TS_PRESCALER // PER.Set.simple ASD:0x4050F228 %Long 0x0 // CANFD0_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR; reason=read-only // CANFD1 (PERIPHERALREGION) PER.Set.simple ASD:0x40516800 %Long 0x0 // CANFD1_PWREN // PER.Set.simple ASD:0x40516814 %Long 0x10000 // CANFD1_STAT; reason=read-only // CANFD1_MCAN[%s] // PER.Set.simple ASD:0x40517000 %Long 0x0 // CANFD1_MCAN_CREL; reason=read-only // PER.Set.simple ASD:0x40517004 %Long 0x0 // CANFD1_MCAN_ENDN; reason=read-only PER.Set.simple ASD:0x4051700C %Long 0x0 // CANFD1_MCAN_DBTP PER.Set.simple ASD:0x40517010 %Long 0x0 // CANFD1_MCAN_TEST PER.Set.simple ASD:0x40517014 %Long 0x0 // CANFD1_MCAN_RWD PER.Set.simple ASD:0x40517018 %Long 0x0 // CANFD1_MCAN_CCCR PER.Set.simple ASD:0x4051701C %Long 0x0 // CANFD1_MCAN_NBTP PER.Set.simple ASD:0x40517020 %Long 0x0 // CANFD1_MCAN_TSCC PER.Set.simple ASD:0x40517024 %Long 0x0 // CANFD1_MCAN_TSCV PER.Set.simple ASD:0x40517028 %Long 0x0 // CANFD1_MCAN_TOCC PER.Set.simple ASD:0x4051702C %Long 0x0 // CANFD1_MCAN_TOCV // PER.Set.simple ASD:0x40517040 %Long 0x0 // CANFD1_MCAN_ECR; reason=read-only // PER.Set.simple ASD:0x40517044 %Long 0x0 // CANFD1_MCAN_PSR; reason=read-only PER.Set.simple ASD:0x40517048 %Long 0x0 // CANFD1_MCAN_TDCR PER.Set.simple ASD:0x40517050 %Long 0x0 // CANFD1_MCAN_IR PER.Set.simple ASD:0x40517054 %Long 0x0 // CANFD1_MCAN_IE PER.Set.simple ASD:0x40517058 %Long 0x0 // CANFD1_MCAN_ILS PER.Set.simple ASD:0x4051705C %Long 0x0 // CANFD1_MCAN_ILE PER.Set.simple ASD:0x40517080 %Long 0x0 // CANFD1_MCAN_GFC PER.Set.simple ASD:0x40517084 %Long 0x0 // CANFD1_MCAN_SIDFC PER.Set.simple ASD:0x40517088 %Long 0x0 // CANFD1_MCAN_XIDFC PER.Set.simple ASD:0x40517090 %Long 0x0 // CANFD1_MCAN_XIDAM // PER.Set.simple ASD:0x40517094 %Long 0x0 // CANFD1_MCAN_HPMS; reason=read-only PER.Set.simple ASD:0x40517098 %Long 0x0 // CANFD1_MCAN_NDAT1 PER.Set.simple ASD:0x4051709C %Long 0x0 // CANFD1_MCAN_NDAT2 PER.Set.simple ASD:0x405170A0 %Long 0x0 // CANFD1_MCAN_RXF0C // PER.Set.simple ASD:0x405170A4 %Long 0x0 // CANFD1_MCAN_RXF0S; reason=read-only PER.Set.simple ASD:0x405170A8 %Long 0x0 // CANFD1_MCAN_RXF0A PER.Set.simple ASD:0x405170AC %Long 0x0 // CANFD1_MCAN_RXBC PER.Set.simple ASD:0x405170B0 %Long 0x0 // CANFD1_MCAN_RXF1C // PER.Set.simple ASD:0x405170B4 %Long 0x0 // CANFD1_MCAN_RXF1S; reason=read-only PER.Set.simple ASD:0x405170B8 %Long 0x0 // CANFD1_MCAN_RXF1A PER.Set.simple ASD:0x405170BC %Long 0x0 // CANFD1_MCAN_RXESC PER.Set.simple ASD:0x405170C0 %Long 0x0 // CANFD1_MCAN_TXBC // PER.Set.simple ASD:0x405170C4 %Long 0x0 // CANFD1_MCAN_TXFQS; reason=read-only PER.Set.simple ASD:0x405170C8 %Long 0x0 // CANFD1_MCAN_TXESC // PER.Set.simple ASD:0x405170CC %Long 0x0 // CANFD1_MCAN_TXBRP; reason=read-only PER.Set.simple ASD:0x405170D0 %Long 0x0 // CANFD1_MCAN_TXBAR PER.Set.simple ASD:0x405170D4 %Long 0x0 // CANFD1_MCAN_TXBCR // PER.Set.simple ASD:0x405170D8 %Long 0x0 // CANFD1_MCAN_TXBTO; reason=read-only // PER.Set.simple ASD:0x405170DC %Long 0x0 // CANFD1_MCAN_TXBCF; reason=read-only PER.Set.simple ASD:0x405170E0 %Long 0x0 // CANFD1_MCAN_TXBTIE PER.Set.simple ASD:0x405170E4 %Long 0x0 // CANFD1_MCAN_TXBCIE PER.Set.simple ASD:0x405170F0 %Long 0x0 // CANFD1_MCAN_TXEFC // PER.Set.simple ASD:0x405170F4 %Long 0x0 // CANFD1_MCAN_TXEFS; reason=read-only PER.Set.simple ASD:0x405170F8 %Long 0x0 // CANFD1_MCAN_TXEFA // CANFD1_TI_WRAPPER[%s] // CANFD1_MSP[%s] // CANFD1_CPU_INT[%s] // PER.Set.simple ASD:0x40517820 %Long 0x0 // CANFD1_IIDX; reason=read-only PER.Set.simple ASD:0x40517828 %Long 0x0 // CANFD1_IMASK // PER.Set.simple ASD:0x40517830 %Long 0x0 // CANFD1_RIS; reason=read-only // PER.Set.simple ASD:0x40517838 %Long 0x0 // CANFD1_MIS; reason=read-only // PER.Set.simple ASD:0x405178E0 %Long 0x0 // CANFD1_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x405178FC %Long 0x0 // CANFD1_DESC; reason=read-only PER.Set.simple ASD:0x40517900 %Long 0x0 // CANFD1_MCANSS_CLKEN PER.Set.simple ASD:0x40517904 %Long 0x0 // CANFD1_MCANSS_CLKDIV PER.Set.simple ASD:0x40517908 %Long 0x0 // CANFD1_MCANSS_CLKCTL // PER.Set.simple ASD:0x4051790C %Long 0x0 // CANFD1_MCANSS_CLKSTS; reason=read-only // CANFD1_PROCESSORS[%s] // CANFD1_MCAN_ECC_REGS[%s] // PER.Set.simple ASD:0x40517400 %Long 0x0 // CANFD1_MCANERR_REV; reason=read-only PER.Set.simple ASD:0x40517408 %Long 0x0 // CANFD1_MCANERR_VECTOR // PER.Set.simple ASD:0x4051740C %Long 0x0 // CANFD1_MCANERR_STAT; reason=read-only // PER.Set.simple ASD:0x40517410 %Long 0x0 // CANFD1_MCANERR_WRAP_REV; reason=read-only PER.Set.simple ASD:0x40517414 %Long 0x0 // CANFD1_MCANERR_CTRL PER.Set.simple ASD:0x40517418 %Long 0x0 // CANFD1_MCANERR_ERR_CTRL1 PER.Set.simple ASD:0x4051741C %Long 0x0 // CANFD1_MCANERR_ERR_CTRL2 PER.Set.simple ASD:0x40517420 %Long 0x0 // CANFD1_MCANERR_ERR_STAT1 // PER.Set.simple ASD:0x40517424 %Long 0x0 // CANFD1_MCANERR_ERR_STAT2; reason=read-only PER.Set.simple ASD:0x40517428 %Long 0x0 // CANFD1_MCANERR_ERR_STAT3 PER.Set.simple ASD:0x4051743C %Long 0x0 // CANFD1_MCANERR_SEC_EOI // PER.Set.simple ASD:0x40517440 %Long 0x0 // CANFD1_MCANERR_SEC_STATUS; reason=read-only PER.Set.simple ASD:0x40517480 %Long 0x0 // CANFD1_MCANERR_SEC_ENABLE_SET PER.Set.simple ASD:0x405174C0 %Long 0x0 // CANFD1_MCANERR_SEC_ENABLE_CLR PER.Set.simple ASD:0x4051753C %Long 0x0 // CANFD1_MCANERR_DED_EOI // PER.Set.simple ASD:0x40517540 %Long 0x0 // CANFD1_MCANERR_DED_STATUS; reason=read-only PER.Set.simple ASD:0x40517580 %Long 0x0 // CANFD1_MCANERR_DED_ENABLE_SET PER.Set.simple ASD:0x405175C0 %Long 0x0 // CANFD1_MCANERR_DED_ENABLE_CLR PER.Set.simple ASD:0x40517600 %Long 0x0 // CANFD1_MCANERR_AGGR_ENABLE_SET PER.Set.simple ASD:0x40517604 %Long 0x0 // CANFD1_MCANERR_AGGR_ENABLE_CLR PER.Set.simple ASD:0x40517608 %Long 0x0 // CANFD1_MCANERR_AGGR_STATUS_SET PER.Set.simple ASD:0x4051760C %Long 0x0 // CANFD1_MCANERR_AGGR_STATUS_CLR // CANFD1_MCANSS_REGS[%s] // PER.Set.simple ASD:0x40517200 %Long 0x0 // CANFD1_MCANSS_PID; reason=read-only PER.Set.simple ASD:0x40517204 %Long 0x0 // CANFD1_MCANSS_CTRL // PER.Set.simple ASD:0x40517208 %Long 0x0 // CANFD1_MCANSS_STAT; reason=read-only PER.Set.simple ASD:0x4051720C %Long 0x0 // CANFD1_MCANSS_ICS PER.Set.simple ASD:0x40517210 %Long 0x0 // CANFD1_MCANSS_IRS PER.Set.simple ASD:0x40517214 %Long 0x0 // CANFD1_MCANSS_IECS PER.Set.simple ASD:0x40517218 %Long 0x0 // CANFD1_MCANSS_IE // PER.Set.simple ASD:0x4051721C %Long 0x0 // CANFD1_MCANSS_IES; reason=read-only PER.Set.simple ASD:0x40517220 %Long 0x0 // CANFD1_MCANSS_EOI PER.Set.simple ASD:0x40517224 %Long 0x0 // CANFD1_MCANSS_EXT_TS_PRESCALER // PER.Set.simple ASD:0x40517228 %Long 0x0 // CANFD1_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR; reason=read-only // COMP (Comparator) // COMP2 PER.Set.simple ASD:0x4000C400 %Long 0x0 // COMP2_FSUB_0 PER.Set.simple ASD:0x4000C404 %Long 0x0 // COMP2_FSUB_1 PER.Set.simple ASD:0x4000C444 %Long 0x0 // COMP2_FPUB_1 // COMP2_CPU_INT[%s] // PER.Set.simple ASD:0x4000D020 %Long 0x0 // COMP2_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x4000D028 %Long 0x0 // COMP2_CPU_INT_IMASK // PER.Set.simple ASD:0x4000D030 %Long 0x0 // COMP2_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x4000D038 %Long 0x0 // COMP2_CPU_INT_MIS; reason=read-only // COMP2_GEN_EVENT[%s] // PER.Set.simple ASD:0x4000D050 %Long 0x0 // COMP2_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x4000D058 %Long 0x0 // COMP2_GEN_EVENT_IMASK // PER.Set.simple ASD:0x4000D060 %Long 0x0 // COMP2_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x4000D068 %Long 0x0 // COMP2_GEN_EVENT_MIS; reason=read-only // COMP2_GPRCM[%s] PER.Set.simple ASD:0x4000C800 %Long 0x0 // COMP2_PWREN PER.Set.simple ASD:0x4000C808 %Long 0x0 // COMP2_CLKCFG // PER.Set.simple ASD:0x4000C814 %Long 0x10000 // COMP2_GPRCM_STAT; reason=read-only // PER.Set.simple ASD:0x4000D0E0 %Long 0x0 // COMP2_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x4000D0FC %Long 0x0 // COMP2_DESC; reason=read-only PER.Set.simple ASD:0x4000D100 %Long 0x0 // COMP2_CTL0 PER.Set.simple ASD:0x4000D104 %Long 0x0 // COMP2_CTL1 PER.Set.simple ASD:0x4000D108 %Long 0x0 // COMP2_CTL2 PER.Set.simple ASD:0x4000D10C %Long 0x0 // COMP2_CTL3 // PER.Set.simple ASD:0x4000D120 %Long 0x0 // COMP2_STAT; reason=read-only // COMP1 PER.Set.simple ASD:0x4000A400 %Long 0x0 // COMP1_FSUB_0 PER.Set.simple ASD:0x4000A404 %Long 0x0 // COMP1_FSUB_1 PER.Set.simple ASD:0x4000A444 %Long 0x0 // COMP1_FPUB_1 // COMP1_CPU_INT[%s] // PER.Set.simple ASD:0x4000B020 %Long 0x0 // COMP1_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x4000B028 %Long 0x0 // COMP1_CPU_INT_IMASK // PER.Set.simple ASD:0x4000B030 %Long 0x0 // COMP1_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x4000B038 %Long 0x0 // COMP1_CPU_INT_MIS; reason=read-only // COMP1_GEN_EVENT[%s] // PER.Set.simple ASD:0x4000B050 %Long 0x0 // COMP1_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x4000B058 %Long 0x0 // COMP1_GEN_EVENT_IMASK // PER.Set.simple ASD:0x4000B060 %Long 0x0 // COMP1_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x4000B068 %Long 0x0 // COMP1_GEN_EVENT_MIS; reason=read-only // COMP1_GPRCM[%s] PER.Set.simple ASD:0x4000A800 %Long 0x0 // COMP1_PWREN PER.Set.simple ASD:0x4000A808 %Long 0x0 // COMP1_CLKCFG // PER.Set.simple ASD:0x4000A814 %Long 0x10000 // COMP1_GPRCM_STAT; reason=read-only // PER.Set.simple ASD:0x4000B0E0 %Long 0x0 // COMP1_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x4000B0FC %Long 0x0 // COMP1_DESC; reason=read-only PER.Set.simple ASD:0x4000B100 %Long 0x0 // COMP1_CTL0 PER.Set.simple ASD:0x4000B104 %Long 0x0 // COMP1_CTL1 PER.Set.simple ASD:0x4000B108 %Long 0x0 // COMP1_CTL2 PER.Set.simple ASD:0x4000B10C %Long 0x0 // COMP1_CTL3 // PER.Set.simple ASD:0x4000B120 %Long 0x0 // COMP1_STAT; reason=read-only // COMP0 PER.Set.simple ASD:0x40008400 %Long 0x0 // COMP0_FSUB_0 PER.Set.simple ASD:0x40008404 %Long 0x0 // COMP0_FSUB_1 PER.Set.simple ASD:0x40008444 %Long 0x0 // COMP0_FPUB_1 // COMP0_CPU_INT[%s] // PER.Set.simple ASD:0x40009020 %Long 0x0 // COMP0_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40009028 %Long 0x0 // COMP0_CPU_INT_IMASK // PER.Set.simple ASD:0x40009030 %Long 0x0 // COMP0_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40009038 %Long 0x0 // COMP0_CPU_INT_MIS; reason=read-only // COMP0_GEN_EVENT[%s] // PER.Set.simple ASD:0x40009050 %Long 0x0 // COMP0_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x40009058 %Long 0x0 // COMP0_GEN_EVENT_IMASK // PER.Set.simple ASD:0x40009060 %Long 0x0 // COMP0_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x40009068 %Long 0x0 // COMP0_GEN_EVENT_MIS; reason=read-only // COMP0_GPRCM[%s] PER.Set.simple ASD:0x40008800 %Long 0x0 // COMP0_PWREN PER.Set.simple ASD:0x40008808 %Long 0x0 // COMP0_CLKCFG // PER.Set.simple ASD:0x40008814 %Long 0x10000 // COMP0_GPRCM_STAT; reason=read-only // PER.Set.simple ASD:0x400090E0 %Long 0x0 // COMP0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400090FC %Long 0x0 // COMP0_DESC; reason=read-only PER.Set.simple ASD:0x40009100 %Long 0x0 // COMP0_CTL0 PER.Set.simple ASD:0x40009104 %Long 0x0 // COMP0_CTL1 PER.Set.simple ASD:0x40009108 %Long 0x0 // COMP0_CTL2 PER.Set.simple ASD:0x4000910C %Long 0x0 // COMP0_CTL3 // PER.Set.simple ASD:0x40009120 %Long 0x0 // COMP0_STAT; reason=read-only // CPUSS (CPU Subsystem) // CPUSS (CPUSSMMR) // PER.Set.simple ASD:0x404010E0 %Long 0x1 // CPUSS_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x404010FC %Long 0x27110000 // CPUSS_DESC; reason=read-only // CPUSS_CPU_INT_GROUP0[%s] // PER.Set.simple ASD:0x40401100 %Long 0x0 // CPUSS_CPU_INT_GROUP0_IIDX; reason=read-only // PER.Set.simple ASD:0x40401108 %Long 0xFF // CPUSS_CPU_INT_GROUP0_IMASK; reason=read-only // PER.Set.simple ASD:0x40401110 %Long 0x0 // CPUSS_CPU_INT_GROUP0_RIS; reason=read-only // PER.Set.simple ASD:0x40401118 %Long 0x0 // CPUSS_CPU_INT_GROUP0_MIS; reason=read-only // CPUSS_CPU_INT_GROUP1[%s] // PER.Set.simple ASD:0x40401130 %Long 0x0 // CPUSS_CPU_INT_GROUP1_IIDX; reason=read-only // PER.Set.simple ASD:0x40401138 %Long 0xFF // CPUSS_CPU_INT_GROUP1_IMASK; reason=read-only // PER.Set.simple ASD:0x40401140 %Long 0x0 // CPUSS_CPU_INT_GROUP1_RIS; reason=read-only // PER.Set.simple ASD:0x40401148 %Long 0x0 // CPUSS_CPU_INT_GROUP1_MIS; reason=read-only PER.Set.simple ASD:0x40401300 %Long 0x7 // CPUSS_CTL // CRCP // CRCP0_GPRCM[%s] PER.Set.simple ASD:0x40440800 %Long 0x0 // CRCP0_PWREN // PER.Set.simple ASD:0x40440814 %Long 0x10000 // CRCP0_STAT; reason=read-only // PER.Set.simple ASD:0x404418FC %Long 0x0 // CRCP0_DESC; reason=read-only PER.Set.simple ASD:0x40441900 %Long 0x0 // CRCP0_CRCCTRL // PER.Set.simple ASD:0x4044190C %Long 0x0 // CRCP0_CRCOUT; reason=read-only PER.Set.simple ASD:0x40441910 %Long 0x0 // CRCP0_CRCPOLY // DAC (Digital-to-Analog Converter) // DAC PER.Set.simple ASD:0x40018400 %Long 0x0 // DAC0_FSUB_0 PER.Set.simple ASD:0x40018444 %Long 0x0 // DAC0_FPUB_1 // DAC0_CPU_INT[%s] // PER.Set.simple ASD:0x40019020 %Long 0x0 // DAC0_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40019028 %Long 0x0 // DAC0_CPU_INT_IMASK // PER.Set.simple ASD:0x40019030 %Long 0x0 // DAC0_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40019038 %Long 0x0 // DAC0_CPU_INT_MIS; reason=read-only // DAC0_GEN_EVENT[%s] // PER.Set.simple ASD:0x40019050 %Long 0x0 // DAC0_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x40019058 %Long 0x0 // DAC0_GEN_EVENT_IMASK // PER.Set.simple ASD:0x40019060 %Long 0x0 // DAC0_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x40019068 %Long 0x0 // DAC0_GEN_EVENT_MIS; reason=read-only // DAC0_GPRCM[%s] PER.Set.simple ASD:0x40018800 %Long 0x0 // DAC0_PWREN // PER.Set.simple ASD:0x40018814 %Long 0x10000 // DAC0_STAT; reason=read-only // PER.Set.simple ASD:0x400190E0 %Long 0x0 // DAC0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400190FC %Long 0x0 // DAC0_DESC; reason=read-only PER.Set.simple ASD:0x40019100 %Long 0x0 // DAC0_CTL0 PER.Set.simple ASD:0x40019110 %Long 0x0 // DAC0_CTL1 PER.Set.simple ASD:0x40019120 %Long 0x0 // DAC0_CTL2 PER.Set.simple ASD:0x40019130 %Long 0x0 // DAC0_CTL3 PER.Set.simple ASD:0x40019140 %Long 0x0 // DAC0_CALCTL // PER.Set.simple ASD:0x40019160 %Long 0x0 // DAC0_CALDATA; reason=read-only PER.Set.simple ASD:0x40019200 %Long 0x0 // DAC0_DATA0 // DEBUGSS (Debug Subsystem) // DEBUGSS (DSSM) // PER.Set.simple ASD:0x400C8020 %Long 0x0 // DEBUGSS_IIDX; reason=read-only PER.Set.simple ASD:0x400C8028 %Long 0x0 // DEBUGSS_IMASK // PER.Set.simple ASD:0x400C8030 %Long 0x4 // DEBUGSS_RIS; reason=read-only // PER.Set.simple ASD:0x400C8038 %Long 0x0 // DEBUGSS_MIS; reason=read-only // PER.Set.simple ASD:0x400C80E0 %Long 0x1 // DEBUGSS_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400C80FC %Long 0x3400000 // DEBUGSS_DESC; reason=read-only // PER.Set.simple ASD:0x400C8100 %Long 0x0 // DEBUGSS_TXD; reason=read-only // PER.Set.simple ASD:0x400C8104 %Long 0x0 // DEBUGSS_TXCTL; reason=read-only PER.Set.simple ASD:0x400C8108 %Long 0x0 // DEBUGSS_RXD PER.Set.simple ASD:0x400C810C %Long 0x0 // DEBUGSS_RXCTL // PER.Set.simple ASD:0x400C8200 %Long 0x7B // DEBUGSS_SPECIAL_AUTH; reason=read-only // PER.Set.simple ASD:0x400C8210 %Long 0x7 // DEBUGSS_APP_AUTH; reason=read-only // DMA (Direct Memory Access) // DMA (PERIPHERALREGION) PER.Set.simple ASD:0x4042A400 %Long 0x0 // DMA_FSUB_0 PER.Set.simple ASD:0x4042A404 %Long 0x0 // DMA_FSUB_1 PER.Set.simple ASD:0x4042A444 %Long 0x0 // DMA_FPUB_1 PER.Set.simple ASD:0x4042B018 %Long 0x3 // DMA_PDBGCTL // DMA_CPU_INT[%s] // PER.Set.simple ASD:0x4042B020 %Long 0x0 // DMA_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x4042B028 %Long 0x0 // DMA_CPU_INT_IMASK // PER.Set.simple ASD:0x4042B030 %Long 0x0 // DMA_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x4042B038 %Long 0x0 // DMA_CPU_INT_MIS; reason=read-only // DMA_GEN_EVENT[%s] // PER.Set.simple ASD:0x4042B050 %Long 0x0 // DMA_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x4042B058 %Long 0x0 // DMA_GEN_EVENT_IMASK // PER.Set.simple ASD:0x4042B060 %Long 0x0 // DMA_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x4042B068 %Long 0x0 // DMA_GEN_EVENT_MIS; reason=read-only // PER.Set.simple ASD:0x4042B0E0 %Long 0x9 // DMA_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x4042B0FC %Long 0x2511B000 // DMA_DESC; reason=read-only PER.Set.simple ASD:0x4042B100 %Long 0x0 // DMA_DMAPRIO // DMA_DMATRIG[0] PER.Set.simple ASD:0x4042B110 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[1] PER.Set.simple ASD:0x4042B114 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[2] PER.Set.simple ASD:0x4042B118 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[3] PER.Set.simple ASD:0x4042B11C %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[4] PER.Set.simple ASD:0x4042B120 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[5] PER.Set.simple ASD:0x4042B124 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[6] PER.Set.simple ASD:0x4042B128 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[7] PER.Set.simple ASD:0x4042B12C %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[8] PER.Set.simple ASD:0x4042B130 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[9] PER.Set.simple ASD:0x4042B134 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[10] PER.Set.simple ASD:0x4042B138 %Long 0x0 // DMA_DMATCTL // DMA_DMATRIG[11] PER.Set.simple ASD:0x4042B13C %Long 0x0 // DMA_DMATCTL // DMA_DMACHAN[0] PER.Set.simple ASD:0x4042B200 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B204 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B208 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B20C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[1] PER.Set.simple ASD:0x4042B210 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B214 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B218 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B21C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[2] PER.Set.simple ASD:0x4042B220 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B224 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B228 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B22C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[3] PER.Set.simple ASD:0x4042B230 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B234 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B238 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B23C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[4] PER.Set.simple ASD:0x4042B240 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B244 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B248 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B24C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[5] PER.Set.simple ASD:0x4042B250 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B254 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B258 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B25C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[6] PER.Set.simple ASD:0x4042B260 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B264 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B268 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B26C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[7] PER.Set.simple ASD:0x4042B270 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B274 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B278 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B27C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[8] PER.Set.simple ASD:0x4042B280 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B284 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B288 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B28C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[9] PER.Set.simple ASD:0x4042B290 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B294 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B298 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B29C %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[10] PER.Set.simple ASD:0x4042B2A0 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B2A4 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B2A8 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B2AC %Long 0x0 // DMA_DMASZ // DMA_DMACHAN[11] PER.Set.simple ASD:0x4042B2B0 %Long 0x0 // DMA_DMACTL PER.Set.simple ASD:0x4042B2B4 %Long 0x0 // DMA_DMASA PER.Set.simple ASD:0x4042B2B8 %Long 0x0 // DMA_DMADA PER.Set.simple ASD:0x4042B2BC %Long 0x0 // DMA_DMASZ // EVENTLP // EVENTLP (PERIPHERALREGION) // PER.Set.simple ASD:0x400C90F8 %Long 0x40B // EVENTLP_PUBCFG_DESC_EX; reason=read-only // PER.Set.simple ASD:0x400C90FC %Long 0x640F000 // EVENTLP_PUBCFG_DESC; reason=read-only // EVENTLP_IMPEXPCFG_EXPORT[%s] PER.Set.simple ASD:0x400CB000 %Long 0x0 // EVENTLP_IMPEXPCFG_EXPORT_PORT // EVENTLP_IMPEXPCFG_IMPORT[%s] PER.Set.simple ASD:0x400CB200 %Long 0x0 // EVENTLP_IMPEXPCFG_IMPORT_PORT // EVENTLP_LMGMT_SFTYDIAG[%s] // PER.Set.simple ASD:0x400CAFF8 %Long 0x0 // EVENTLP_DIAGPARFV; reason=read-only // PER.Set.simple ASD:0x400CAFFC %Long 0x0 // EVENTLP_DIAGSTAT; reason=read-only // EVENTLP_PUBCFG_CPU_CONNECT[%s] PER.Set.simple ASD:0x400C9900 %Long 0x0 // EVENTLP_PUBCFG_CPU_NUM // EVENTLP_PUBCFG_EXPORT[%s] PER.Set.simple ASD:0x400C9500 %Long 0x0 // EVENTLP_PUBCFG_EXPORT_PORT // EVENTLP_PUBCFG_FPUB[%s] PER.Set.simple ASD:0x400C9300 %Long 0x0 // EVENTLP_PUBCFG_FPUB_PORT // EVENTLP_PUBCFG_FSUB[%s] PER.Set.simple ASD:0x400C9100 %Long 0x0 // EVENTLP_PUBCFG_FSUB_PORT // EVENTLP_PUBCFG_IMPORT[%s] PER.Set.simple ASD:0x400C9700 %Long 0x0 // EVENTLP_PUBCFG_IMPORT_PORT // PER.Set.simple ASD:0x400CA0F8 %Long 0x40B // EVENTLP_SECCFG_DESC_EX; reason=read-only // PER.Set.simple ASD:0x400CA0FC %Long 0x640F000 // EVENTLP_SECCFG_DESC; reason=read-only // EVENTLP_SECCFG_CPU_CONNECT[%s] PER.Set.simple ASD:0x400CA300 %Byte 0x0 // EVENTLP_SECCFG_CPU_NUM // EVENTLP_SECCFG_EXPORT[%s] PER.Set.simple ASD:0x400CA200 %Byte 0x0 // EVENTLP_SECCFG_EXPORT_PORT // EVENTLP_SECCFG_FPUB[%s] PER.Set.simple ASD:0x400CA180 %Byte 0x0 // EVENTLP_SECCFG_FPUB_PORT // EVENTLP_SECCFG_FSUB[%s] PER.Set.simple ASD:0x400CA100 %Byte 0x0 // EVENTLP_SECCFG_FSUB_PORT // EVENTLP_SECCFG_IMPORT[%s] PER.Set.simple ASD:0x400CA280 %Byte 0x0 // EVENTLP_SECCFG_IMPORT_PORT PER.Set.simple ASD:0x400CA400 %Byte 0x0 // EVENTLP_CTL // FLASHCTL (Flash Controller) // FLASHCTL (NVMNW_A2512) // PER.Set.simple ASD:0x400CE020 %Long 0x0 // FLASHCTL_IIDX; reason=read-only PER.Set.simple ASD:0x400CE028 %Long 0x0 // FLASHCTL_IMASK // PER.Set.simple ASD:0x400CE030 %Long 0x1 // FLASHCTL_RIS; reason=read-only // PER.Set.simple ASD:0x400CE038 %Long 0x0 // FLASHCTL_MIS; reason=read-only // PER.Set.simple ASD:0x400CE0E0 %Long 0x1 // FLASHCTL_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400CE0FC %Long 0x2811A010 // FLASHCTL_DESC; reason=read-only PER.Set.simple ASD:0x400CE100 %Long 0x0 // FLASHCTL_CMDEXEC PER.Set.simple ASD:0x400CE104 %Long 0x5 // FLASHCTL_CMDTYPE PER.Set.simple ASD:0x400CE108 %Long 0x0 // FLASHCTL_CMDCTL PER.Set.simple ASD:0x400CE120 %Long 0x4 // FLASHCTL_CMDADDR PER.Set.simple ASD:0x400CE124 %Long 0x0 // FLASHCTL_CMDBYTEN PER.Set.simple ASD:0x400CE12C %Long 0x0 // FLASHCTL_CMDDATAINDEX PER.Set.simple ASD:0x400CE130 %Long 0xFFFFFFFF // FLASHCTL_CMDDATA0 PER.Set.simple ASD:0x400CE134 %Long 0xFFFFFFFF // FLASHCTL_CMDDATA1 PER.Set.simple ASD:0x400CE138 %Long 0x0 // FLASHCTL_CMDDATA2 PER.Set.simple ASD:0x400CE13C %Long 0x0 // FLASHCTL_CMDDATA3 PER.Set.simple ASD:0x400CE140 %Long 0x0 // FLASHCTL_CMDDATA4 PER.Set.simple ASD:0x400CE144 %Long 0x0 // FLASHCTL_CMDDATA5 PER.Set.simple ASD:0x400CE148 %Long 0x0 // FLASHCTL_CMDDATA6 PER.Set.simple ASD:0x400CE14C %Long 0x0 // FLASHCTL_CMDDATA7 PER.Set.simple ASD:0x400CE150 %Long 0x0 // FLASHCTL_CMDDATA8 PER.Set.simple ASD:0x400CE154 %Long 0x0 // FLASHCTL_CMDDATA9 PER.Set.simple ASD:0x400CE158 %Long 0x0 // FLASHCTL_CMDDATA10 PER.Set.simple ASD:0x400CE15C %Long 0x0 // FLASHCTL_CMDDATA11 PER.Set.simple ASD:0x400CE160 %Long 0x0 // FLASHCTL_CMDDATA12 PER.Set.simple ASD:0x400CE164 %Long 0x0 // FLASHCTL_CMDDATA13 PER.Set.simple ASD:0x400CE168 %Long 0x0 // FLASHCTL_CMDDATA14 PER.Set.simple ASD:0x400CE16C %Long 0x0 // FLASHCTL_CMDDATA15 PER.Set.simple ASD:0x400CE170 %Long 0x0 // FLASHCTL_CMDDATA16 PER.Set.simple ASD:0x400CE174 %Long 0x0 // FLASHCTL_CMDDATA17 PER.Set.simple ASD:0x400CE178 %Long 0x0 // FLASHCTL_CMDDATA18 PER.Set.simple ASD:0x400CE17C %Long 0x0 // FLASHCTL_CMDDATA19 PER.Set.simple ASD:0x400CE180 %Long 0x0 // FLASHCTL_CMDDATA20 PER.Set.simple ASD:0x400CE184 %Long 0x0 // FLASHCTL_CMDDATA21 PER.Set.simple ASD:0x400CE188 %Long 0x0 // FLASHCTL_CMDDATA22 PER.Set.simple ASD:0x400CE18C %Long 0x0 // FLASHCTL_CMDDATA23 PER.Set.simple ASD:0x400CE190 %Long 0x0 // FLASHCTL_CMDDATA24 PER.Set.simple ASD:0x400CE194 %Long 0x0 // FLASHCTL_CMDDATA25 PER.Set.simple ASD:0x400CE198 %Long 0x0 // FLASHCTL_CMDDATA26 PER.Set.simple ASD:0x400CE19C %Long 0x0 // FLASHCTL_CMDDATA27 PER.Set.simple ASD:0x400CE1A0 %Long 0x0 // FLASHCTL_CMDDATA28 PER.Set.simple ASD:0x400CE1A4 %Long 0x0 // FLASHCTL_CMDDATA29 PER.Set.simple ASD:0x400CE1A8 %Long 0x0 // FLASHCTL_CMDDATA30 PER.Set.simple ASD:0x400CE1AC %Long 0x0 // FLASHCTL_CMDDATA31 PER.Set.simple ASD:0x400CE1B0 %Long 0xFF // FLASHCTL_CMDDATAECC0 PER.Set.simple ASD:0x400CE1B4 %Long 0x0 // FLASHCTL_CMDDATAECC1 PER.Set.simple ASD:0x400CE1B8 %Long 0x0 // FLASHCTL_CMDDATAECC2 PER.Set.simple ASD:0x400CE1BC %Long 0x0 // FLASHCTL_CMDDATAECC3 PER.Set.simple ASD:0x400CE1C0 %Long 0x0 // FLASHCTL_CMDDATAECC4 PER.Set.simple ASD:0x400CE1C4 %Long 0x0 // FLASHCTL_CMDDATAECC5 PER.Set.simple ASD:0x400CE1C8 %Long 0x0 // FLASHCTL_CMDDATAECC6 PER.Set.simple ASD:0x400CE1CC %Long 0x0 // FLASHCTL_CMDDATAECC7 PER.Set.simple ASD:0x400CE1D0 %Long 0x0 // FLASHCTL_CMDWEPROTA PER.Set.simple ASD:0x400CE1D4 %Long 0xFFFFFFFF // FLASHCTL_CMDWEPROTB PER.Set.simple ASD:0x400CE1D8 %Long 0x0 // FLASHCTL_CMDWEPROTC PER.Set.simple ASD:0x400CE210 %Long 0x3 // FLASHCTL_CMDWEPROTNM PER.Set.simple ASD:0x400CE214 %Long 0x1 // FLASHCTL_CMDWEPROTTR PER.Set.simple ASD:0x400CE218 %Long 0x0 // FLASHCTL_CMDWEPROTEN PER.Set.simple ASD:0x400CE3B0 %Long 0x2 // FLASHCTL_CFGCMD PER.Set.simple ASD:0x400CE3B4 %Long 0x0 // FLASHCTL_CFGPCNT // PER.Set.simple ASD:0x400CE3D0 %Long 0x0 // FLASHCTL_STATCMD; reason=read-only // PER.Set.simple ASD:0x400CE3D4 %Long 0x210000 // FLASHCTL_STATADDR; reason=read-only // PER.Set.simple ASD:0x400CE3D8 %Long 0x0 // FLASHCTL_STATPCNT; reason=read-only // PER.Set.simple ASD:0x400CE3DC %Long 0x30000 // FLASHCTL_STATMODE; reason=read-only // PER.Set.simple ASD:0x400CE3F0 %Long 0x30400 // FLASHCTL_GBLINFO0; reason=read-only // PER.Set.simple ASD:0x400CE3F4 %Long 0x20840 // FLASHCTL_GBLINFO1; reason=read-only // PER.Set.simple ASD:0x400CE3F8 %Long 0x1 // FLASHCTL_GBLINFO2; reason=read-only // PER.Set.simple ASD:0x400CE400 %Long 0x100 // FLASHCTL_BANK0INFO0; reason=read-only // PER.Set.simple ASD:0x400CE404 %Long 0x102 // FLASHCTL_BANK0INFO1; reason=read-only // PER.Set.simple ASD:0x400CE410 %Long 0x100 // FLASHCTL_BANK1INFO0; reason=read-only // PER.Set.simple ASD:0x400CE414 %Long 0x0 // FLASHCTL_BANK1INFO1; reason=read-only // PER.Set.simple ASD:0x400CE420 %Long 0x10 // FLASHCTL_BANK2INFO0; reason=read-only // PER.Set.simple ASD:0x400CE424 %Long 0x0 // FLASHCTL_BANK2INFO1; reason=read-only // PER.Set.simple ASD:0x400CE430 %Long 0x0 // FLASHCTL_BANK3INFO0; reason=read-only // PER.Set.simple ASD:0x400CE434 %Long 0x0 // FLASHCTL_BANK3INFO1; reason=read-only // PER.Set.simple ASD:0x400CE440 %Long 0x0 // FLASHCTL_BANK4INFO0; reason=read-only // PER.Set.simple ASD:0x400CE444 %Long 0x0 // FLASHCTL_BANK4INFO1; reason=read-only // GPIO (General Purpose Input/Output) // GPIOA // GPIOA (PERIPHERALREGION) PER.Set.simple ASD:0x400A0400 %Long 0x0 // GPIOA_FSUB_0 PER.Set.simple ASD:0x400A0404 %Long 0x0 // GPIOA_FSUB_1 PER.Set.simple ASD:0x400A0444 %Long 0x0 // GPIOA_FPUB_0 PER.Set.simple ASD:0x400A0448 %Long 0x0 // GPIOA_FPUB_1 // GPIOA_GPRCM[%s] PER.Set.simple ASD:0x400A0800 %Long 0x1 // GPIOA_PWREN // PER.Set.simple ASD:0x400A0814 %Long 0x10000 // GPIOA_STAT; reason=read-only PER.Set.simple ASD:0x400A1010 %Long 0x0 // GPIOA_CLKOVR PER.Set.simple ASD:0x400A1018 %Long 0x1 // GPIOA_PDBGCTL // GPIOA_CPU_INT[%s] // PER.Set.simple ASD:0x400A1020 %Long 0x0 // GPIOA_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x400A1028 %Long 0x40000 // GPIOA_CPU_INT_IMASK // PER.Set.simple ASD:0x400A1030 %Long 0x0 // GPIOA_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x400A1038 %Long 0x0 // GPIOA_CPU_INT_MIS; reason=read-only // GPIOA_GEN_EVENT0[%s] // PER.Set.simple ASD:0x400A1050 %Long 0x0 // GPIOA_GEN_EVENT0_IIDX; reason=read-only PER.Set.simple ASD:0x400A1058 %Long 0x0 // GPIOA_GEN_EVENT0_IMASK // PER.Set.simple ASD:0x400A1060 %Long 0x0 // GPIOA_GEN_EVENT0_RIS; reason=read-only // PER.Set.simple ASD:0x400A1068 %Long 0x0 // GPIOA_GEN_EVENT0_MIS; reason=read-only // GPIOA_GEN_EVENT1[%s] // PER.Set.simple ASD:0x400A1080 %Long 0x0 // GPIOA_GEN_EVENT1_IIDX; reason=read-only PER.Set.simple ASD:0x400A1088 %Long 0x0 // GPIOA_GEN_EVENT1_IMASK // PER.Set.simple ASD:0x400A1090 %Long 0x0 // GPIOA_GEN_EVENT1_RIS; reason=read-only // PER.Set.simple ASD:0x400A1098 %Long 0x0 // GPIOA_GEN_EVENT1_MIS; reason=read-only // PER.Set.simple ASD:0x400A10E0 %Long 0x29 // GPIOA_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400A10FC %Long 0x16110000 // GPIOA_DESC; reason=read-only PER.Set.simple ASD:0x400A1280 %Long 0x1 // GPIOA_DOUT31_0 PER.Set.simple ASD:0x400A12C0 %Long 0x1 // GPIOA_DOE31_0 // PER.Set.simple ASD:0x400A1300 %Long 0x0 // GPIOA_DIN3_0; reason=read-only // PER.Set.simple ASD:0x400A1304 %Long 0x0 // GPIOA_DIN7_4; reason=read-only // PER.Set.simple ASD:0x400A1308 %Long 0x1000000 // GPIOA_DIN11_8; reason=read-only // PER.Set.simple ASD:0x400A130C %Long 0x0 // GPIOA_DIN15_12; reason=read-only // PER.Set.simple ASD:0x400A1310 %Long 0x0 // GPIOA_DIN19_16; reason=read-only // PER.Set.simple ASD:0x400A1314 %Long 0x0 // GPIOA_DIN23_20; reason=read-only // PER.Set.simple ASD:0x400A1318 %Long 0x0 // GPIOA_DIN27_24; reason=read-only // PER.Set.simple ASD:0x400A131C %Long 0x0 // GPIOA_DIN31_28; reason=read-only // PER.Set.simple ASD:0x400A1380 %Long 0x800 // GPIOA_DIN31_0; reason=read-only PER.Set.simple ASD:0x400A1390 %Long 0x0 // GPIOA_POLARITY15_0 PER.Set.simple ASD:0x400A13A0 %Long 0x10 // GPIOA_POLARITY31_16 PER.Set.simple ASD:0x400A1400 %Long 0x0 // GPIOA_CTL PER.Set.simple ASD:0x400A1404 %Long 0x0 // GPIOA_FASTWAKE PER.Set.simple ASD:0x400A1500 %Long 0x0 // GPIOA_SUB0CFG PER.Set.simple ASD:0x400A1508 %Long 0x0 // GPIOA_FILTEREN15_0 PER.Set.simple ASD:0x400A150C %Long 0x0 // GPIOA_FILTEREN31_16 PER.Set.simple ASD:0x400A1510 %Long 0x0 // GPIOA_DMAMASK PER.Set.simple ASD:0x400A1520 %Long 0x0 // GPIOA_SUB1CFG // GPIOB // GPIOB (PERIPHERALREGION) PER.Set.simple ASD:0x400A2400 %Long 0x0 // GPIOB_FSUB_0 PER.Set.simple ASD:0x400A2404 %Long 0x0 // GPIOB_FSUB_1 PER.Set.simple ASD:0x400A2444 %Long 0x0 // GPIOB_FPUB_0 PER.Set.simple ASD:0x400A2448 %Long 0x0 // GPIOB_FPUB_1 // GPIOB_GPRCM[%s] PER.Set.simple ASD:0x400A2800 %Long 0x1 // GPIOB_PWREN // PER.Set.simple ASD:0x400A2814 %Long 0x10000 // GPIOB_STAT; reason=read-only PER.Set.simple ASD:0x400A3010 %Long 0x0 // GPIOB_CLKOVR PER.Set.simple ASD:0x400A3018 %Long 0x1 // GPIOB_PDBGCTL // GPIOB_CPU_INT[%s] // PER.Set.simple ASD:0x400A3020 %Long 0x0 // GPIOB_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x400A3028 %Long 0x8 // GPIOB_CPU_INT_IMASK // PER.Set.simple ASD:0x400A3030 %Long 0x0 // GPIOB_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x400A3038 %Long 0x0 // GPIOB_CPU_INT_MIS; reason=read-only // GPIOB_GEN_EVENT0[%s] // PER.Set.simple ASD:0x400A3050 %Long 0x0 // GPIOB_GEN_EVENT0_IIDX; reason=read-only PER.Set.simple ASD:0x400A3058 %Long 0x0 // GPIOB_GEN_EVENT0_IMASK // PER.Set.simple ASD:0x400A3060 %Long 0x0 // GPIOB_GEN_EVENT0_RIS; reason=read-only // PER.Set.simple ASD:0x400A3068 %Long 0x0 // GPIOB_GEN_EVENT0_MIS; reason=read-only // GPIOB_GEN_EVENT1[%s] // PER.Set.simple ASD:0x400A3080 %Long 0x0 // GPIOB_GEN_EVENT1_IIDX; reason=read-only PER.Set.simple ASD:0x400A3088 %Long 0x0 // GPIOB_GEN_EVENT1_IMASK // PER.Set.simple ASD:0x400A3090 %Long 0x0 // GPIOB_GEN_EVENT1_RIS; reason=read-only // PER.Set.simple ASD:0x400A3098 %Long 0x0 // GPIOB_GEN_EVENT1_MIS; reason=read-only // PER.Set.simple ASD:0x400A30E0 %Long 0x29 // GPIOB_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400A30FC %Long 0x16110000 // GPIOB_DESC; reason=read-only PER.Set.simple ASD:0x400A3280 %Long 0x0 // GPIOB_DOUT31_0 PER.Set.simple ASD:0x400A32C0 %Long 0x0 // GPIOB_DOE31_0 // PER.Set.simple ASD:0x400A3300 %Long 0x1000000 // GPIOB_DIN3_0; reason=read-only // PER.Set.simple ASD:0x400A3304 %Long 0x0 // GPIOB_DIN7_4; reason=read-only // PER.Set.simple ASD:0x400A3308 %Long 0x0 // GPIOB_DIN11_8; reason=read-only // PER.Set.simple ASD:0x400A330C %Long 0x0 // GPIOB_DIN15_12; reason=read-only // PER.Set.simple ASD:0x400A3310 %Long 0x0 // GPIOB_DIN19_16; reason=read-only // PER.Set.simple ASD:0x400A3314 %Long 0x0 // GPIOB_DIN23_20; reason=read-only // PER.Set.simple ASD:0x400A3318 %Long 0x0 // GPIOB_DIN27_24; reason=read-only // PER.Set.simple ASD:0x400A331C %Long 0x0 // GPIOB_DIN31_28; reason=read-only // PER.Set.simple ASD:0x400A3380 %Long 0x8 // GPIOB_DIN31_0; reason=read-only PER.Set.simple ASD:0x400A3390 %Long 0x80 // GPIOB_POLARITY15_0 PER.Set.simple ASD:0x400A33A0 %Long 0x0 // GPIOB_POLARITY31_16 PER.Set.simple ASD:0x400A3400 %Long 0x0 // GPIOB_CTL PER.Set.simple ASD:0x400A3404 %Long 0x0 // GPIOB_FASTWAKE PER.Set.simple ASD:0x400A3500 %Long 0x0 // GPIOB_SUB0CFG PER.Set.simple ASD:0x400A3508 %Long 0x0 // GPIOB_FILTEREN15_0 PER.Set.simple ASD:0x400A350C %Long 0x0 // GPIOB_FILTEREN31_16 PER.Set.simple ASD:0x400A3510 %Long 0x0 // GPIOB_DMAMASK PER.Set.simple ASD:0x400A3520 %Long 0x0 // GPIOB_SUB1CFG // GPIOC // GPIOC (PERIPHERALREGION) PER.Set.simple ASD:0x400A4400 %Long 0x0 // GPIOC_FSUB_0 PER.Set.simple ASD:0x400A4404 %Long 0x0 // GPIOC_FSUB_1 PER.Set.simple ASD:0x400A4444 %Long 0x0 // GPIOC_FPUB_0 PER.Set.simple ASD:0x400A4448 %Long 0x0 // GPIOC_FPUB_1 // GPIOC_GPRCM[%s] PER.Set.simple ASD:0x400A4800 %Long 0x1 // GPIOC_PWREN // PER.Set.simple ASD:0x400A4814 %Long 0x10000 // GPIOC_STAT; reason=read-only PER.Set.simple ASD:0x400A5010 %Long 0x0 // GPIOC_CLKOVR PER.Set.simple ASD:0x400A5018 %Long 0x1 // GPIOC_PDBGCTL // GPIOC_CPU_INT[%s] // PER.Set.simple ASD:0x400A5020 %Long 0x0 // GPIOC_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x400A5028 %Long 0x0 // GPIOC_CPU_INT_IMASK // PER.Set.simple ASD:0x400A5030 %Long 0x0 // GPIOC_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x400A5038 %Long 0x0 // GPIOC_CPU_INT_MIS; reason=read-only // GPIOC_GEN_EVENT0[%s] // PER.Set.simple ASD:0x400A5050 %Long 0x0 // GPIOC_GEN_EVENT0_IIDX; reason=read-only PER.Set.simple ASD:0x400A5058 %Long 0x0 // GPIOC_GEN_EVENT0_IMASK // PER.Set.simple ASD:0x400A5060 %Long 0x0 // GPIOC_GEN_EVENT0_RIS; reason=read-only // PER.Set.simple ASD:0x400A5068 %Long 0x0 // GPIOC_GEN_EVENT0_MIS; reason=read-only // GPIOC_GEN_EVENT1[%s] // PER.Set.simple ASD:0x400A5080 %Long 0x0 // GPIOC_GEN_EVENT1_IIDX; reason=read-only PER.Set.simple ASD:0x400A5088 %Long 0x0 // GPIOC_GEN_EVENT1_IMASK // PER.Set.simple ASD:0x400A5090 %Long 0x0 // GPIOC_GEN_EVENT1_RIS; reason=read-only // PER.Set.simple ASD:0x400A5098 %Long 0x0 // GPIOC_GEN_EVENT1_MIS; reason=read-only // PER.Set.simple ASD:0x400A50E0 %Long 0x29 // GPIOC_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400A50FC %Long 0x16110000 // GPIOC_DESC; reason=read-only PER.Set.simple ASD:0x400A5280 %Long 0x0 // GPIOC_DOUT31_0 PER.Set.simple ASD:0x400A52C0 %Long 0x0 // GPIOC_DOE31_0 // PER.Set.simple ASD:0x400A5300 %Long 0x0 // GPIOC_DIN3_0; reason=read-only // PER.Set.simple ASD:0x400A5304 %Long 0x0 // GPIOC_DIN7_4; reason=read-only // PER.Set.simple ASD:0x400A5308 %Long 0x0 // GPIOC_DIN11_8; reason=read-only // PER.Set.simple ASD:0x400A530C %Long 0x0 // GPIOC_DIN15_12; reason=read-only // PER.Set.simple ASD:0x400A5310 %Long 0x0 // GPIOC_DIN19_16; reason=read-only // PER.Set.simple ASD:0x400A5314 %Long 0x0 // GPIOC_DIN23_20; reason=read-only // PER.Set.simple ASD:0x400A5318 %Long 0x0 // GPIOC_DIN27_24; reason=read-only // PER.Set.simple ASD:0x400A531C %Long 0x0 // GPIOC_DIN31_28; reason=read-only // PER.Set.simple ASD:0x400A5380 %Long 0x0 // GPIOC_DIN31_0; reason=read-only PER.Set.simple ASD:0x400A5390 %Long 0x0 // GPIOC_POLARITY15_0 PER.Set.simple ASD:0x400A53A0 %Long 0x0 // GPIOC_POLARITY31_16 PER.Set.simple ASD:0x400A5400 %Long 0x0 // GPIOC_CTL PER.Set.simple ASD:0x400A5404 %Long 0x0 // GPIOC_FASTWAKE PER.Set.simple ASD:0x400A5500 %Long 0x0 // GPIOC_SUB0CFG PER.Set.simple ASD:0x400A5508 %Long 0x0 // GPIOC_FILTEREN15_0 PER.Set.simple ASD:0x400A550C %Long 0x0 // GPIOC_FILTEREN31_16 PER.Set.simple ASD:0x400A5510 %Long 0x0 // GPIOC_DMAMASK PER.Set.simple ASD:0x400A5520 %Long 0x0 // GPIOC_SUB1CFG // I2C (Inter-Integrated Circuit) // I2C0 // I2C0_GPRCM[%s] PER.Set.simple ASD:0x400F0800 %Long 0x0 // I2C0_PWREN PER.Set.simple ASD:0x400F0808 %Long 0x0 // I2C0_CLKCFG // PER.Set.simple ASD:0x400F0814 %Long 0x10000 // I2C0_STAT; reason=read-only PER.Set.simple ASD:0x400F1000 %Long 0x0 // I2C0_CLKDIV PER.Set.simple ASD:0x400F1004 %Long 0x0 // I2C0_CLKSEL PER.Set.simple ASD:0x400F1018 %Long 0x0 // I2C0_PDBGCTL // I2C0_CPU_INT[%s] // PER.Set.simple ASD:0x400F1020 %Long 0x0 // I2C0_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x400F1028 %Long 0x0 // I2C0_CPU_INT_IMASK // PER.Set.simple ASD:0x400F1030 %Long 0x0 // I2C0_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x400F1038 %Long 0x0 // I2C0_CPU_INT_MIS; reason=read-only // I2C0_DMA_TRIG0[%s] // PER.Set.simple ASD:0x400F1080 %Long 0x0 // I2C0_DMA_TRIG0_IIDX; reason=read-only PER.Set.simple ASD:0x400F1088 %Long 0x0 // I2C0_DMA_TRIG0_IMASK // PER.Set.simple ASD:0x400F1090 %Long 0x0 // I2C0_DMA_TRIG0_RIS; reason=read-only // PER.Set.simple ASD:0x400F1098 %Long 0x0 // I2C0_DMA_TRIG0_MIS; reason=read-only // I2C0_DMA_TRIG1[%s] // PER.Set.simple ASD:0x400F1050 %Long 0x0 // I2C0_DMA_TRIG1_IIDX; reason=read-only PER.Set.simple ASD:0x400F1058 %Long 0x0 // I2C0_DMA_TRIG1_IMASK // PER.Set.simple ASD:0x400F1060 %Long 0x0 // I2C0_DMA_TRIG1_RIS; reason=read-only // PER.Set.simple ASD:0x400F1068 %Long 0x0 // I2C0_DMA_TRIG1_MIS; reason=read-only // PER.Set.simple ASD:0x400F10E0 %Long 0x0 // I2C0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400F10FC %Long 0x0 // I2C0_DESC; reason=read-only PER.Set.simple ASD:0x400F1200 %Long 0x0 // I2C0_GFCTL PER.Set.simple ASD:0x400F1204 %Long 0x0 // I2C0_TIMEOUT_CTL // PER.Set.simple ASD:0x400F1208 %Long 0x0 // I2C0_TIMEOUT_CNT; reason=read-only // I2C0_CONTROLLER[%s] PER.Set.simple ASD:0x400F1210 %Long 0x0 // I2C0_CSA PER.Set.simple ASD:0x400F1214 %Long 0x0 // I2C0_CCTR // PER.Set.simple ASD:0x400F1218 %Long 0x0 // I2C0_CSR; reason=read-only // PER.Set.simple ASD:0x400F121C %Long 0x0 // I2C0_CRXDATA; reason=read-only PER.Set.simple ASD:0x400F1220 %Long 0x0 // I2C0_CTXDATA PER.Set.simple ASD:0x400F1224 %Long 0x0 // I2C0_CTPR PER.Set.simple ASD:0x400F1228 %Long 0x0 // I2C0_CCR // PER.Set.simple ASD:0x400F1234 %Long 0x0 // I2C0_CBMON; reason=read-only PER.Set.simple ASD:0x400F1238 %Long 0x0 // I2C0_CFIFOCTL // PER.Set.simple ASD:0x400F123C %Long 0x0 // I2C0_CFIFOSR; reason=read-only PER.Set.simple ASD:0x400F1240 %Long 0x0 // I2C0_CONTROLLER_I2CPECCTL // PER.Set.simple ASD:0x400F1244 %Long 0x0 // I2C0_CONTROLLER_PECSR; reason=read-only // I2C0_TARGET[%s] PER.Set.simple ASD:0x400F1250 %Long 0x0 // I2C0_TOAR PER.Set.simple ASD:0x400F1254 %Long 0x0 // I2C0_TOAR2 PER.Set.simple ASD:0x400F1258 %Long 0x0 // I2C0_TCTR // PER.Set.simple ASD:0x400F125C %Long 0x0 // I2C0_TSR; reason=read-only // PER.Set.simple ASD:0x400F1260 %Long 0x0 // I2C0_TRXDATA; reason=read-only PER.Set.simple ASD:0x400F1264 %Long 0x0 // I2C0_TTXDATA PER.Set.simple ASD:0x400F1268 %Long 0x0 // I2C0_TACKCTL PER.Set.simple ASD:0x400F126C %Long 0x0 // I2C0_TFIFOCTL // PER.Set.simple ASD:0x400F1270 %Long 0x0 // I2C0_TFIFOSR; reason=read-only PER.Set.simple ASD:0x400F1274 %Long 0x0 // I2C0_TARGET_PECCTL // PER.Set.simple ASD:0x400F1278 %Long 0x0 // I2C0_TARGET_PECSR; reason=read-only // I2C1 // I2C1_GPRCM[%s] PER.Set.simple ASD:0x400F2800 %Long 0x0 // I2C1_PWREN PER.Set.simple ASD:0x400F2808 %Long 0x0 // I2C1_CLKCFG // PER.Set.simple ASD:0x400F2814 %Long 0x10000 // I2C1_STAT; reason=read-only PER.Set.simple ASD:0x400F3000 %Long 0x0 // I2C1_CLKDIV PER.Set.simple ASD:0x400F3004 %Long 0x0 // I2C1_CLKSEL PER.Set.simple ASD:0x400F3018 %Long 0x0 // I2C1_PDBGCTL // I2C1_CPU_INT[%s] // PER.Set.simple ASD:0x400F3020 %Long 0x0 // I2C1_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x400F3028 %Long 0x0 // I2C1_CPU_INT_IMASK // PER.Set.simple ASD:0x400F3030 %Long 0x0 // I2C1_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x400F3038 %Long 0x0 // I2C1_CPU_INT_MIS; reason=read-only // I2C1_DMA_TRIG0[%s] // PER.Set.simple ASD:0x400F3080 %Long 0x0 // I2C1_DMA_TRIG0_IIDX; reason=read-only PER.Set.simple ASD:0x400F3088 %Long 0x0 // I2C1_DMA_TRIG0_IMASK // PER.Set.simple ASD:0x400F3090 %Long 0x0 // I2C1_DMA_TRIG0_RIS; reason=read-only // PER.Set.simple ASD:0x400F3098 %Long 0x0 // I2C1_DMA_TRIG0_MIS; reason=read-only // I2C1_DMA_TRIG1[%s] // PER.Set.simple ASD:0x400F3050 %Long 0x0 // I2C1_DMA_TRIG1_IIDX; reason=read-only PER.Set.simple ASD:0x400F3058 %Long 0x0 // I2C1_DMA_TRIG1_IMASK // PER.Set.simple ASD:0x400F3060 %Long 0x0 // I2C1_DMA_TRIG1_RIS; reason=read-only // PER.Set.simple ASD:0x400F3068 %Long 0x0 // I2C1_DMA_TRIG1_MIS; reason=read-only // PER.Set.simple ASD:0x400F30E0 %Long 0x0 // I2C1_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400F30FC %Long 0x0 // I2C1_DESC; reason=read-only PER.Set.simple ASD:0x400F3200 %Long 0x0 // I2C1_GFCTL PER.Set.simple ASD:0x400F3204 %Long 0x0 // I2C1_TIMEOUT_CTL // PER.Set.simple ASD:0x400F3208 %Long 0x0 // I2C1_TIMEOUT_CNT; reason=read-only // I2C1_CONTROLLER[%s] PER.Set.simple ASD:0x400F3210 %Long 0x0 // I2C1_CSA PER.Set.simple ASD:0x400F3214 %Long 0x0 // I2C1_CCTR // PER.Set.simple ASD:0x400F3218 %Long 0x0 // I2C1_CSR; reason=read-only // PER.Set.simple ASD:0x400F321C %Long 0x0 // I2C1_CRXDATA; reason=read-only PER.Set.simple ASD:0x400F3220 %Long 0x0 // I2C1_CTXDATA PER.Set.simple ASD:0x400F3224 %Long 0x0 // I2C1_CTPR PER.Set.simple ASD:0x400F3228 %Long 0x0 // I2C1_CCR // PER.Set.simple ASD:0x400F3234 %Long 0x0 // I2C1_CBMON; reason=read-only PER.Set.simple ASD:0x400F3238 %Long 0x0 // I2C1_CFIFOCTL // PER.Set.simple ASD:0x400F323C %Long 0x0 // I2C1_CFIFOSR; reason=read-only PER.Set.simple ASD:0x400F3240 %Long 0x0 // I2C1_CONTROLLER_I2CPECCTL // PER.Set.simple ASD:0x400F3244 %Long 0x0 // I2C1_CONTROLLER_PECSR; reason=read-only // I2C1_TARGET[%s] PER.Set.simple ASD:0x400F3250 %Long 0x0 // I2C1_TOAR PER.Set.simple ASD:0x400F3254 %Long 0x0 // I2C1_TOAR2 PER.Set.simple ASD:0x400F3258 %Long 0x0 // I2C1_TCTR // PER.Set.simple ASD:0x400F325C %Long 0x0 // I2C1_TSR; reason=read-only // PER.Set.simple ASD:0x400F3260 %Long 0x0 // I2C1_TRXDATA; reason=read-only PER.Set.simple ASD:0x400F3264 %Long 0x0 // I2C1_TTXDATA PER.Set.simple ASD:0x400F3268 %Long 0x0 // I2C1_TACKCTL PER.Set.simple ASD:0x400F326C %Long 0x0 // I2C1_TFIFOCTL // PER.Set.simple ASD:0x400F3270 %Long 0x0 // I2C1_TFIFOSR; reason=read-only PER.Set.simple ASD:0x400F3274 %Long 0x0 // I2C1_TARGET_PECCTL // PER.Set.simple ASD:0x400F3278 %Long 0x0 // I2C1_TARGET_PECSR; reason=read-only // I2C2 // I2C2_GPRCM[%s] PER.Set.simple ASD:0x400F4800 %Long 0x0 // I2C2_PWREN PER.Set.simple ASD:0x400F4808 %Long 0x0 // I2C2_CLKCFG // PER.Set.simple ASD:0x400F4814 %Long 0x10000 // I2C2_STAT; reason=read-only PER.Set.simple ASD:0x400F5000 %Long 0x0 // I2C2_CLKDIV PER.Set.simple ASD:0x400F5004 %Long 0x0 // I2C2_CLKSEL PER.Set.simple ASD:0x400F5018 %Long 0x0 // I2C2_PDBGCTL // I2C2_CPU_INT[%s] // PER.Set.simple ASD:0x400F5020 %Long 0x0 // I2C2_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x400F5028 %Long 0x0 // I2C2_CPU_INT_IMASK // PER.Set.simple ASD:0x400F5030 %Long 0x0 // I2C2_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x400F5038 %Long 0x0 // I2C2_CPU_INT_MIS; reason=read-only // I2C2_DMA_TRIG0[%s] // PER.Set.simple ASD:0x400F5080 %Long 0x0 // I2C2_DMA_TRIG0_IIDX; reason=read-only PER.Set.simple ASD:0x400F5088 %Long 0x0 // I2C2_DMA_TRIG0_IMASK // PER.Set.simple ASD:0x400F5090 %Long 0x0 // I2C2_DMA_TRIG0_RIS; reason=read-only // PER.Set.simple ASD:0x400F5098 %Long 0x0 // I2C2_DMA_TRIG0_MIS; reason=read-only // I2C2_DMA_TRIG1[%s] // PER.Set.simple ASD:0x400F5050 %Long 0x0 // I2C2_DMA_TRIG1_IIDX; reason=read-only PER.Set.simple ASD:0x400F5058 %Long 0x0 // I2C2_DMA_TRIG1_IMASK // PER.Set.simple ASD:0x400F5060 %Long 0x0 // I2C2_DMA_TRIG1_RIS; reason=read-only // PER.Set.simple ASD:0x400F5068 %Long 0x0 // I2C2_DMA_TRIG1_MIS; reason=read-only // PER.Set.simple ASD:0x400F50E0 %Long 0x0 // I2C2_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400F50FC %Long 0x0 // I2C2_DESC; reason=read-only PER.Set.simple ASD:0x400F5200 %Long 0x0 // I2C2_GFCTL PER.Set.simple ASD:0x400F5204 %Long 0x0 // I2C2_TIMEOUT_CTL // PER.Set.simple ASD:0x400F5208 %Long 0x0 // I2C2_TIMEOUT_CNT; reason=read-only // I2C2_CONTROLLER[%s] PER.Set.simple ASD:0x400F5210 %Long 0x0 // I2C2_CSA PER.Set.simple ASD:0x400F5214 %Long 0x0 // I2C2_CCTR // PER.Set.simple ASD:0x400F5218 %Long 0x0 // I2C2_CSR; reason=read-only // PER.Set.simple ASD:0x400F521C %Long 0x0 // I2C2_CRXDATA; reason=read-only PER.Set.simple ASD:0x400F5220 %Long 0x0 // I2C2_CTXDATA PER.Set.simple ASD:0x400F5224 %Long 0x0 // I2C2_CTPR PER.Set.simple ASD:0x400F5228 %Long 0x0 // I2C2_CCR // PER.Set.simple ASD:0x400F5234 %Long 0x0 // I2C2_CBMON; reason=read-only PER.Set.simple ASD:0x400F5238 %Long 0x0 // I2C2_CFIFOCTL // PER.Set.simple ASD:0x400F523C %Long 0x0 // I2C2_CFIFOSR; reason=read-only PER.Set.simple ASD:0x400F5240 %Long 0x0 // I2C2_CONTROLLER_I2CPECCTL // PER.Set.simple ASD:0x400F5244 %Long 0x0 // I2C2_CONTROLLER_PECSR; reason=read-only // I2C2_TARGET[%s] PER.Set.simple ASD:0x400F5250 %Long 0x0 // I2C2_TOAR PER.Set.simple ASD:0x400F5254 %Long 0x0 // I2C2_TOAR2 PER.Set.simple ASD:0x400F5258 %Long 0x0 // I2C2_TCTR // PER.Set.simple ASD:0x400F525C %Long 0x0 // I2C2_TSR; reason=read-only // PER.Set.simple ASD:0x400F5260 %Long 0x0 // I2C2_TRXDATA; reason=read-only PER.Set.simple ASD:0x400F5264 %Long 0x0 // I2C2_TTXDATA PER.Set.simple ASD:0x400F5268 %Long 0x0 // I2C2_TACKCTL PER.Set.simple ASD:0x400F526C %Long 0x0 // I2C2_TFIFOCTL // PER.Set.simple ASD:0x400F5270 %Long 0x0 // I2C2_TFIFOSR; reason=read-only PER.Set.simple ASD:0x400F5274 %Long 0x0 // I2C2_TARGET_PECCTL // PER.Set.simple ASD:0x400F5278 %Long 0x0 // I2C2_TARGET_PECSR; reason=read-only // IOMUX (I/O Multiplexer) // IOMUX (PERIPHERALREGION) PER.Set.simple ASD:0x40428004 %Long 0x81 // IOMUX_PINCM[0] PER.Set.simple ASD:0x40428008 %Long 0x0 // IOMUX_PINCM[1] PER.Set.simple ASD:0x4042800C %Long 0x0 // IOMUX_PINCM[2] PER.Set.simple ASD:0x40428010 %Long 0x0 // IOMUX_PINCM[3] PER.Set.simple ASD:0x40428014 %Long 0x0 // IOMUX_PINCM[4] PER.Set.simple ASD:0x40428018 %Long 0x0 // IOMUX_PINCM[5] PER.Set.simple ASD:0x4042801C %Long 0x0 // IOMUX_PINCM[6] PER.Set.simple ASD:0x40428020 %Long 0x0 // IOMUX_PINCM[7] PER.Set.simple ASD:0x40428024 %Long 0x0 // IOMUX_PINCM[8] PER.Set.simple ASD:0x40428028 %Long 0x0 // IOMUX_PINCM[9] PER.Set.simple ASD:0x4042802C %Long 0x0 // IOMUX_PINCM[10] PER.Set.simple ASD:0x40428030 %Long 0x0 // IOMUX_PINCM[11] PER.Set.simple ASD:0x40428034 %Long 0x0 // IOMUX_PINCM[12] PER.Set.simple ASD:0x40428038 %Long 0x0 // IOMUX_PINCM[13] PER.Set.simple ASD:0x4042803C %Long 0x0 // IOMUX_PINCM[14] PER.Set.simple ASD:0x40428040 %Long 0x60081 // IOMUX_PINCM[15] PER.Set.simple ASD:0x40428044 %Long 0x0 // IOMUX_PINCM[16] PER.Set.simple ASD:0x40428048 %Long 0x0 // IOMUX_PINCM[17] PER.Set.simple ASD:0x4042804C %Long 0x0 // IOMUX_PINCM[18] PER.Set.simple ASD:0x40428050 %Long 0x0 // IOMUX_PINCM[19] PER.Set.simple ASD:0x40428054 %Long 0x82 // IOMUX_PINCM[20] PER.Set.simple ASD:0x40428058 %Long 0x40082 // IOMUX_PINCM[21] PER.Set.simple ASD:0x4042805C %Long 0x0 // IOMUX_PINCM[22] PER.Set.simple ASD:0x40428060 %Long 0x0 // IOMUX_PINCM[23] PER.Set.simple ASD:0x40428064 %Long 0x0 // IOMUX_PINCM[24] PER.Set.simple ASD:0x40428068 %Long 0x0 // IOMUX_PINCM[25] PER.Set.simple ASD:0x4042806C %Long 0x0 // IOMUX_PINCM[26] PER.Set.simple ASD:0x40428070 %Long 0x0 // IOMUX_PINCM[27] PER.Set.simple ASD:0x40428074 %Long 0x0 // IOMUX_PINCM[28] PER.Set.simple ASD:0x40428078 %Long 0x0 // IOMUX_PINCM[29] PER.Set.simple ASD:0x4042807C %Long 0x0 // IOMUX_PINCM[30] PER.Set.simple ASD:0x40428080 %Long 0x0 // IOMUX_PINCM[31] PER.Set.simple ASD:0x40428084 %Long 0x0 // IOMUX_PINCM[32] PER.Set.simple ASD:0x40428088 %Long 0x0 // IOMUX_PINCM[33] PER.Set.simple ASD:0x4042808C %Long 0x0 // IOMUX_PINCM[34] PER.Set.simple ASD:0x40428090 %Long 0x0 // IOMUX_PINCM[35] PER.Set.simple ASD:0x40428094 %Long 0x0 // IOMUX_PINCM[36] PER.Set.simple ASD:0x40428098 %Long 0x0 // IOMUX_PINCM[37] PER.Set.simple ASD:0x4042809C %Long 0x0 // IOMUX_PINCM[38] PER.Set.simple ASD:0x404280A0 %Long 0x40081 // IOMUX_PINCM[39] PER.Set.simple ASD:0x404280A4 %Long 0x60082 // IOMUX_PINCM[40] PER.Set.simple ASD:0x404280A8 %Long 0x50082 // IOMUX_PINCM[41] PER.Set.simple ASD:0x404280AC %Long 0x0 // IOMUX_PINCM[42] PER.Set.simple ASD:0x404280B0 %Long 0x0 // IOMUX_PINCM[43] PER.Set.simple ASD:0x404280B4 %Long 0x0 // IOMUX_PINCM[44] PER.Set.simple ASD:0x404280B8 %Long 0x0 // IOMUX_PINCM[45] PER.Set.simple ASD:0x404280BC %Long 0x0 // IOMUX_PINCM[46] PER.Set.simple ASD:0x404280C0 %Long 0x0 // IOMUX_PINCM[47] PER.Set.simple ASD:0x404280C4 %Long 0x0 // IOMUX_PINCM[48] PER.Set.simple ASD:0x404280C8 %Long 0x0 // IOMUX_PINCM[49] PER.Set.simple ASD:0x404280CC %Long 0x0 // IOMUX_PINCM[50] PER.Set.simple ASD:0x404280D0 %Long 0x0 // IOMUX_PINCM[51] PER.Set.simple ASD:0x404280D4 %Long 0x0 // IOMUX_PINCM[52] PER.Set.simple ASD:0x404280D8 %Long 0x0 // IOMUX_PINCM[53] PER.Set.simple ASD:0x404280DC %Long 0x0 // IOMUX_PINCM[54] PER.Set.simple ASD:0x404280E0 %Long 0x0 // IOMUX_PINCM[55] PER.Set.simple ASD:0x404280E4 %Long 0x0 // IOMUX_PINCM[56] PER.Set.simple ASD:0x404280E8 %Long 0x0 // IOMUX_PINCM[57] PER.Set.simple ASD:0x404280EC %Long 0x0 // IOMUX_PINCM[58] PER.Set.simple ASD:0x404280F0 %Long 0x0 // IOMUX_PINCM[59] PER.Set.simple ASD:0x404280F4 %Long 0x0 // IOMUX_PINCM[60] PER.Set.simple ASD:0x404280F8 %Long 0x0 // IOMUX_PINCM[61] PER.Set.simple ASD:0x404280FC %Long 0x0 // IOMUX_PINCM[62] PER.Set.simple ASD:0x40428100 %Long 0x0 // IOMUX_PINCM[63] PER.Set.simple ASD:0x40428104 %Long 0x0 // IOMUX_PINCM[64] PER.Set.simple ASD:0x40428108 %Long 0x0 // IOMUX_PINCM[65] PER.Set.simple ASD:0x4042810C %Long 0x0 // IOMUX_PINCM[66] PER.Set.simple ASD:0x40428110 %Long 0x0 // IOMUX_PINCM[67] PER.Set.simple ASD:0x40428114 %Long 0x0 // IOMUX_PINCM[68] PER.Set.simple ASD:0x40428118 %Long 0x0 // IOMUX_PINCM[69] PER.Set.simple ASD:0x4042811C %Long 0x0 // IOMUX_PINCM[70] PER.Set.simple ASD:0x40428120 %Long 0x0 // IOMUX_PINCM[71] PER.Set.simple ASD:0x40428124 %Long 0x0 // IOMUX_PINCM[72] PER.Set.simple ASD:0x40428128 %Long 0x0 // IOMUX_PINCM[73] PER.Set.simple ASD:0x4042812C %Long 0x0 // IOMUX_PINCM[74] PER.Set.simple ASD:0x40428130 %Long 0x0 // IOMUX_PINCM[75] PER.Set.simple ASD:0x40428134 %Long 0x0 // IOMUX_PINCM[76] PER.Set.simple ASD:0x40428138 %Long 0x0 // IOMUX_PINCM[77] PER.Set.simple ASD:0x4042813C %Long 0x0 // IOMUX_PINCM[78] PER.Set.simple ASD:0x40428140 %Long 0x0 // IOMUX_PINCM[79] PER.Set.simple ASD:0x40428144 %Long 0x0 // IOMUX_PINCM[80] PER.Set.simple ASD:0x40428148 %Long 0x0 // IOMUX_PINCM[81] PER.Set.simple ASD:0x4042814C %Long 0x0 // IOMUX_PINCM[82] PER.Set.simple ASD:0x40428150 %Long 0x0 // IOMUX_PINCM[83] PER.Set.simple ASD:0x40428154 %Long 0x0 // IOMUX_PINCM[84] PER.Set.simple ASD:0x40428158 %Long 0x0 // IOMUX_PINCM[85] PER.Set.simple ASD:0x4042815C %Long 0x0 // IOMUX_PINCM[86] PER.Set.simple ASD:0x40428160 %Long 0x0 // IOMUX_PINCM[87] PER.Set.simple ASD:0x40428164 %Long 0x0 // IOMUX_PINCM[88] PER.Set.simple ASD:0x40428168 %Long 0x0 // IOMUX_PINCM[89] PER.Set.simple ASD:0x4042816C %Long 0x0 // IOMUX_PINCM[90] PER.Set.simple ASD:0x40428170 %Long 0x0 // IOMUX_PINCM[91] PER.Set.simple ASD:0x40428174 %Long 0x0 // IOMUX_PINCM[92] PER.Set.simple ASD:0x40428178 %Long 0x0 // IOMUX_PINCM[93] PER.Set.simple ASD:0x4042817C %Long 0x0 // IOMUX_PINCM[94] PER.Set.simple ASD:0x40428180 %Long 0x0 // IOMUX_PINCM[95] PER.Set.simple ASD:0x40428184 %Long 0x0 // IOMUX_PINCM[96] PER.Set.simple ASD:0x40428188 %Long 0x0 // IOMUX_PINCM[97] PER.Set.simple ASD:0x4042818C %Long 0x0 // IOMUX_PINCM[98] PER.Set.simple ASD:0x40428190 %Long 0x0 // IOMUX_PINCM[99] PER.Set.simple ASD:0x40428194 %Long 0x0 // IOMUX_PINCM[100] PER.Set.simple ASD:0x40428198 %Long 0x0 // IOMUX_PINCM[101] PER.Set.simple ASD:0x4042819C %Long 0x0 // IOMUX_PINCM[102] PER.Set.simple ASD:0x404281A0 %Long 0x0 // IOMUX_PINCM[103] PER.Set.simple ASD:0x404281A4 %Long 0x0 // IOMUX_PINCM[104] PER.Set.simple ASD:0x404281A8 %Long 0x0 // IOMUX_PINCM[105] PER.Set.simple ASD:0x404281AC %Long 0x0 // IOMUX_PINCM[106] PER.Set.simple ASD:0x404281B0 %Long 0x0 // IOMUX_PINCM[107] PER.Set.simple ASD:0x404281B4 %Long 0x0 // IOMUX_PINCM[108] PER.Set.simple ASD:0x404281B8 %Long 0x0 // IOMUX_PINCM[109] PER.Set.simple ASD:0x404281BC %Long 0x0 // IOMUX_PINCM[110] PER.Set.simple ASD:0x404281C0 %Long 0x0 // IOMUX_PINCM[111] PER.Set.simple ASD:0x404281C4 %Long 0x0 // IOMUX_PINCM[112] PER.Set.simple ASD:0x404281C8 %Long 0x0 // IOMUX_PINCM[113] PER.Set.simple ASD:0x404281CC %Long 0x0 // IOMUX_PINCM[114] PER.Set.simple ASD:0x404281D0 %Long 0x0 // IOMUX_PINCM[115] PER.Set.simple ASD:0x404281D4 %Long 0x0 // IOMUX_PINCM[116] PER.Set.simple ASD:0x404281D8 %Long 0x0 // IOMUX_PINCM[117] PER.Set.simple ASD:0x404281DC %Long 0x0 // IOMUX_PINCM[118] PER.Set.simple ASD:0x404281E0 %Long 0x0 // IOMUX_PINCM[119] PER.Set.simple ASD:0x404281E4 %Long 0x0 // IOMUX_PINCM[120] PER.Set.simple ASD:0x404281E8 %Long 0x0 // IOMUX_PINCM[121] PER.Set.simple ASD:0x404281EC %Long 0x0 // IOMUX_PINCM[122] PER.Set.simple ASD:0x404281F0 %Long 0x0 // IOMUX_PINCM[123] PER.Set.simple ASD:0x404281F4 %Long 0x0 // IOMUX_PINCM[124] PER.Set.simple ASD:0x404281F8 %Long 0x0 // IOMUX_PINCM[125] PER.Set.simple ASD:0x404281FC %Long 0x0 // IOMUX_PINCM[126] PER.Set.simple ASD:0x40428200 %Long 0x0 // IOMUX_PINCM[127] PER.Set.simple ASD:0x40428204 %Long 0x0 // IOMUX_PINCM[128] PER.Set.simple ASD:0x40428208 %Long 0x0 // IOMUX_PINCM[129] PER.Set.simple ASD:0x4042820C %Long 0x0 // IOMUX_PINCM[130] PER.Set.simple ASD:0x40428210 %Long 0x0 // IOMUX_PINCM[131] PER.Set.simple ASD:0x40428214 %Long 0x0 // IOMUX_PINCM[132] PER.Set.simple ASD:0x40428218 %Long 0x0 // IOMUX_PINCM[133] PER.Set.simple ASD:0x4042821C %Long 0x0 // IOMUX_PINCM[134] PER.Set.simple ASD:0x40428220 %Long 0x0 // IOMUX_PINCM[135] PER.Set.simple ASD:0x40428224 %Long 0x0 // IOMUX_PINCM[136] PER.Set.simple ASD:0x40428228 %Long 0x0 // IOMUX_PINCM[137] PER.Set.simple ASD:0x4042822C %Long 0x0 // IOMUX_PINCM[138] PER.Set.simple ASD:0x40428230 %Long 0x0 // IOMUX_PINCM[139] PER.Set.simple ASD:0x40428234 %Long 0x0 // IOMUX_PINCM[140] PER.Set.simple ASD:0x40428238 %Long 0x0 // IOMUX_PINCM[141] PER.Set.simple ASD:0x4042823C %Long 0x0 // IOMUX_PINCM[142] PER.Set.simple ASD:0x40428240 %Long 0x0 // IOMUX_PINCM[143] PER.Set.simple ASD:0x40428244 %Long 0x0 // IOMUX_PINCM[144] PER.Set.simple ASD:0x40428248 %Long 0x0 // IOMUX_PINCM[145] PER.Set.simple ASD:0x4042824C %Long 0x0 // IOMUX_PINCM[146] PER.Set.simple ASD:0x40428250 %Long 0x0 // IOMUX_PINCM[147] PER.Set.simple ASD:0x40428254 %Long 0x0 // IOMUX_PINCM[148] PER.Set.simple ASD:0x40428258 %Long 0x0 // IOMUX_PINCM[149] PER.Set.simple ASD:0x4042825C %Long 0x0 // IOMUX_PINCM[150] PER.Set.simple ASD:0x40428260 %Long 0x0 // IOMUX_PINCM[151] PER.Set.simple ASD:0x40428264 %Long 0x0 // IOMUX_PINCM[152] PER.Set.simple ASD:0x40428268 %Long 0x0 // IOMUX_PINCM[153] PER.Set.simple ASD:0x4042826C %Long 0x0 // IOMUX_PINCM[154] PER.Set.simple ASD:0x40428270 %Long 0x0 // IOMUX_PINCM[155] PER.Set.simple ASD:0x40428274 %Long 0x0 // IOMUX_PINCM[156] PER.Set.simple ASD:0x40428278 %Long 0x0 // IOMUX_PINCM[157] PER.Set.simple ASD:0x4042827C %Long 0x0 // IOMUX_PINCM[158] PER.Set.simple ASD:0x40428280 %Long 0x0 // IOMUX_PINCM[159] PER.Set.simple ASD:0x40428284 %Long 0x0 // IOMUX_PINCM[160] PER.Set.simple ASD:0x40428288 %Long 0x0 // IOMUX_PINCM[161] PER.Set.simple ASD:0x4042828C %Long 0x0 // IOMUX_PINCM[162] PER.Set.simple ASD:0x40428290 %Long 0x0 // IOMUX_PINCM[163] PER.Set.simple ASD:0x40428294 %Long 0x0 // IOMUX_PINCM[164] PER.Set.simple ASD:0x40428298 %Long 0x0 // IOMUX_PINCM[165] PER.Set.simple ASD:0x4042829C %Long 0x0 // IOMUX_PINCM[166] PER.Set.simple ASD:0x404282A0 %Long 0x0 // IOMUX_PINCM[167] PER.Set.simple ASD:0x404282A4 %Long 0x0 // IOMUX_PINCM[168] PER.Set.simple ASD:0x404282A8 %Long 0x0 // IOMUX_PINCM[169] PER.Set.simple ASD:0x404282AC %Long 0x0 // IOMUX_PINCM[170] PER.Set.simple ASD:0x404282B0 %Long 0x0 // IOMUX_PINCM[171] PER.Set.simple ASD:0x404282B4 %Long 0x0 // IOMUX_PINCM[172] PER.Set.simple ASD:0x404282B8 %Long 0x0 // IOMUX_PINCM[173] PER.Set.simple ASD:0x404282BC %Long 0x0 // IOMUX_PINCM[174] PER.Set.simple ASD:0x404282C0 %Long 0x0 // IOMUX_PINCM[175] PER.Set.simple ASD:0x404282C4 %Long 0x0 // IOMUX_PINCM[176] PER.Set.simple ASD:0x404282C8 %Long 0x0 // IOMUX_PINCM[177] PER.Set.simple ASD:0x404282CC %Long 0x0 // IOMUX_PINCM[178] PER.Set.simple ASD:0x404282D0 %Long 0x0 // IOMUX_PINCM[179] PER.Set.simple ASD:0x404282D4 %Long 0x0 // IOMUX_PINCM[180] PER.Set.simple ASD:0x404282D8 %Long 0x0 // IOMUX_PINCM[181] PER.Set.simple ASD:0x404282DC %Long 0x0 // IOMUX_PINCM[182] PER.Set.simple ASD:0x404282E0 %Long 0x0 // IOMUX_PINCM[183] PER.Set.simple ASD:0x404282E4 %Long 0x0 // IOMUX_PINCM[184] PER.Set.simple ASD:0x404282E8 %Long 0x0 // IOMUX_PINCM[185] PER.Set.simple ASD:0x404282EC %Long 0x0 // IOMUX_PINCM[186] PER.Set.simple ASD:0x404282F0 %Long 0x0 // IOMUX_PINCM[187] PER.Set.simple ASD:0x404282F4 %Long 0x0 // IOMUX_PINCM[188] PER.Set.simple ASD:0x404282F8 %Long 0x0 // IOMUX_PINCM[189] PER.Set.simple ASD:0x404282FC %Long 0x0 // IOMUX_PINCM[190] PER.Set.simple ASD:0x40428300 %Long 0x0 // IOMUX_PINCM[191] PER.Set.simple ASD:0x40428304 %Long 0x0 // IOMUX_PINCM[192] PER.Set.simple ASD:0x40428308 %Long 0x0 // IOMUX_PINCM[193] PER.Set.simple ASD:0x4042830C %Long 0x0 // IOMUX_PINCM[194] PER.Set.simple ASD:0x40428310 %Long 0x0 // IOMUX_PINCM[195] PER.Set.simple ASD:0x40428314 %Long 0x0 // IOMUX_PINCM[196] PER.Set.simple ASD:0x40428318 %Long 0x0 // IOMUX_PINCM[197] PER.Set.simple ASD:0x4042831C %Long 0x0 // IOMUX_PINCM[198] PER.Set.simple ASD:0x40428320 %Long 0x0 // IOMUX_PINCM[199] PER.Set.simple ASD:0x40428324 %Long 0x0 // IOMUX_PINCM[200] PER.Set.simple ASD:0x40428328 %Long 0x0 // IOMUX_PINCM[201] PER.Set.simple ASD:0x4042832C %Long 0x0 // IOMUX_PINCM[202] PER.Set.simple ASD:0x40428330 %Long 0x0 // IOMUX_PINCM[203] PER.Set.simple ASD:0x40428334 %Long 0x0 // IOMUX_PINCM[204] PER.Set.simple ASD:0x40428338 %Long 0x0 // IOMUX_PINCM[205] PER.Set.simple ASD:0x4042833C %Long 0x0 // IOMUX_PINCM[206] PER.Set.simple ASD:0x40428340 %Long 0x0 // IOMUX_PINCM[207] PER.Set.simple ASD:0x40428344 %Long 0x0 // IOMUX_PINCM[208] PER.Set.simple ASD:0x40428348 %Long 0x0 // IOMUX_PINCM[209] PER.Set.simple ASD:0x4042834C %Long 0x0 // IOMUX_PINCM[210] PER.Set.simple ASD:0x40428350 %Long 0x0 // IOMUX_PINCM[211] PER.Set.simple ASD:0x40428354 %Long 0x0 // IOMUX_PINCM[212] PER.Set.simple ASD:0x40428358 %Long 0x0 // IOMUX_PINCM[213] PER.Set.simple ASD:0x4042835C %Long 0x0 // IOMUX_PINCM[214] PER.Set.simple ASD:0x40428360 %Long 0x0 // IOMUX_PINCM[215] PER.Set.simple ASD:0x40428364 %Long 0x0 // IOMUX_PINCM[216] PER.Set.simple ASD:0x40428368 %Long 0x0 // IOMUX_PINCM[217] PER.Set.simple ASD:0x4042836C %Long 0x0 // IOMUX_PINCM[218] PER.Set.simple ASD:0x40428370 %Long 0x0 // IOMUX_PINCM[219] PER.Set.simple ASD:0x40428374 %Long 0x0 // IOMUX_PINCM[220] PER.Set.simple ASD:0x40428378 %Long 0x0 // IOMUX_PINCM[221] PER.Set.simple ASD:0x4042837C %Long 0x0 // IOMUX_PINCM[222] PER.Set.simple ASD:0x40428380 %Long 0x0 // IOMUX_PINCM[223] PER.Set.simple ASD:0x40428384 %Long 0x0 // IOMUX_PINCM[224] PER.Set.simple ASD:0x40428388 %Long 0x0 // IOMUX_PINCM[225] PER.Set.simple ASD:0x4042838C %Long 0x0 // IOMUX_PINCM[226] PER.Set.simple ASD:0x40428390 %Long 0x0 // IOMUX_PINCM[227] PER.Set.simple ASD:0x40428394 %Long 0x0 // IOMUX_PINCM[228] PER.Set.simple ASD:0x40428398 %Long 0x0 // IOMUX_PINCM[229] PER.Set.simple ASD:0x4042839C %Long 0x0 // IOMUX_PINCM[230] PER.Set.simple ASD:0x404283A0 %Long 0x0 // IOMUX_PINCM[231] PER.Set.simple ASD:0x404283A4 %Long 0x0 // IOMUX_PINCM[232] PER.Set.simple ASD:0x404283A8 %Long 0x0 // IOMUX_PINCM[233] PER.Set.simple ASD:0x404283AC %Long 0x0 // IOMUX_PINCM[234] PER.Set.simple ASD:0x404283B0 %Long 0x0 // IOMUX_PINCM[235] PER.Set.simple ASD:0x404283B4 %Long 0x0 // IOMUX_PINCM[236] PER.Set.simple ASD:0x404283B8 %Long 0x0 // IOMUX_PINCM[237] PER.Set.simple ASD:0x404283BC %Long 0x0 // IOMUX_PINCM[238] PER.Set.simple ASD:0x404283C0 %Long 0x0 // IOMUX_PINCM[239] PER.Set.simple ASD:0x404283C4 %Long 0x0 // IOMUX_PINCM[240] PER.Set.simple ASD:0x404283C8 %Long 0x0 // IOMUX_PINCM[241] PER.Set.simple ASD:0x404283CC %Long 0x0 // IOMUX_PINCM[242] PER.Set.simple ASD:0x404283D0 %Long 0x0 // IOMUX_PINCM[243] PER.Set.simple ASD:0x404283D4 %Long 0x0 // IOMUX_PINCM[244] PER.Set.simple ASD:0x404283D8 %Long 0x0 // IOMUX_PINCM[245] PER.Set.simple ASD:0x404283DC %Long 0x0 // IOMUX_PINCM[246] PER.Set.simple ASD:0x404283E0 %Long 0x0 // IOMUX_PINCM[247] PER.Set.simple ASD:0x404283E4 %Long 0x0 // IOMUX_PINCM[248] PER.Set.simple ASD:0x404283E8 %Long 0x0 // IOMUX_PINCM[249] PER.Set.simple ASD:0x404283EC %Long 0x0 // IOMUX_PINCM[250] // KEYSTORECTL // KEYSTORECTL (PERIPHERALREGION) PER.Set.simple ASD:0x400AD100 %Long 0x1 // KEYSTORECTL_CFG PER.Set.simple ASD:0x400AD104 %Long 0x0 // KEYSTORECTL_KEYWR PER.Set.simple ASD:0x400AD108 %Long 0x0 // KEYSTORECTL_KEYRD // PER.Set.simple ASD:0x400AD10C %Long 0x20000 // KEYSTORECTL_STATUS; reason=read-only PER.Set.simple ASD:0x400AD114 %Long 0x0 // KEYSTORECTL_KEYLOCK // LFSS // LFSS (PERIPHERALREGION) PER.Set.simple ASD:0x40094400 %Long 0x0 // LFSS_FSUB_0 PER.Set.simple ASD:0x40094444 %Long 0x0 // LFSS_FPUB_0 // PER.Set.simple ASD:0x40095004 %Long 0x2 // LFSS_CLKSEL; reason=read-only // LFSS_CPU_INT[%s] // PER.Set.simple ASD:0x40095020 %Long 0x0 // LFSS_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40095028 %Long 0x0 // LFSS_CPU_INT_IMASK // PER.Set.simple ASD:0x40095030 %Long 0x0 // LFSS_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40095038 %Long 0x0 // LFSS_CPU_INT_MIS; reason=read-only // LFSS_GEN_EVENT[%s] // PER.Set.simple ASD:0x40095050 %Long 0x0 // LFSS_GEN_EVENT_IIDX; reason=read-only PER.Set.simple ASD:0x40095058 %Long 0x0 // LFSS_GEN_EVENT_IMASK // PER.Set.simple ASD:0x40095060 %Long 0x0 // LFSS_GEN_EVENT_RIS; reason=read-only // PER.Set.simple ASD:0x40095068 %Long 0x0 // LFSS_GEN_EVENT_MIS; reason=read-only // PER.Set.simple ASD:0x400950E0 %Long 0x9 // LFSS_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400950FC %Long 0x29110000 // LFSS_DESC; reason=read-only PER.Set.simple ASD:0x40095100 %Long 0x0 // LFSS_CLKCTL PER.Set.simple ASD:0x40095104 %Long 0x0 // LFSS_DBGCTL PER.Set.simple ASD:0x40095108 %Long 0x0 // LFSS_CTL // PER.Set.simple ASD:0x4009510C %Long 0x0 // LFSS_STA; reason=read-only PER.Set.simple ASD:0x40095110 %Long 0x0 // LFSS_CAL PER.Set.simple ASD:0x40095114 %Long 0x0 // LFSS_TCMP PER.Set.simple ASD:0x40095118 %Long 0x8 // LFSS_SEC PER.Set.simple ASD:0x4009511C %Long 0x10 // LFSS_MIN PER.Set.simple ASD:0x40095120 %Long 0x7 // LFSS_HOUR PER.Set.simple ASD:0x40095124 %Long 0xA01 // LFSS_DAY PER.Set.simple ASD:0x40095128 %Long 0x0C // LFSS_MON PER.Set.simple ASD:0x4009512C %Long 0x8BB // LFSS_YEAR PER.Set.simple ASD:0x40095130 %Long 0x0 // LFSS_A1MIN PER.Set.simple ASD:0x40095134 %Long 0x0 // LFSS_A1HOUR PER.Set.simple ASD:0x40095138 %Long 0x0 // LFSS_A1DAY PER.Set.simple ASD:0x4009513C %Long 0x0 // LFSS_A2MIN PER.Set.simple ASD:0x40095140 %Long 0x0 // LFSS_A2HOUR PER.Set.simple ASD:0x40095144 %Long 0x0 // LFSS_A2DAY PER.Set.simple ASD:0x40095148 %Long 0x8 // LFSS_PSCTL PER.Set.simple ASD:0x4009514C %Long 0x0 // LFSS_EXTPSCTL // PER.Set.simple ASD:0x40095150 %Long 0x10 // LFSS_TSSEC; reason=read-only // PER.Set.simple ASD:0x40095154 %Long 0x0 // LFSS_TSMIN; reason=read-only // PER.Set.simple ASD:0x40095158 %Long 0x0 // LFSS_TSHOUR; reason=read-only // PER.Set.simple ASD:0x4009515C %Long 0x200 // LFSS_TSDAY; reason=read-only // PER.Set.simple ASD:0x40095160 %Long 0x4 // LFSS_TSMON; reason=read-only // PER.Set.simple ASD:0x40095164 %Long 0x159 // LFSS_TSYEAR; reason=read-only // PER.Set.simple ASD:0x40095168 %Long 0x0 // LFSS_TSSTAT; reason=read-only PER.Set.simple ASD:0x4009516C %Long 0x0 // LFSS_TSCTL PER.Set.simple ASD:0x400951F0 %Long 0x0 // LFSS_LFSSRST PER.Set.simple ASD:0x400951FC %Long 0x0 // LFSS_RTCLOCK PER.Set.simple ASD:0x40095200 %Long 0x0 // LFSS_TIOCTL[0] PER.Set.simple ASD:0x40095204 %Long 0x0 // LFSS_TIOCTL[1] PER.Set.simple ASD:0x40095208 %Long 0x0 // LFSS_TIOCTL[2] PER.Set.simple ASD:0x4009520C %Long 0x0 // LFSS_TIOCTL[3] PER.Set.simple ASD:0x40095210 %Long 0x0 // LFSS_TIOCTL[4] PER.Set.simple ASD:0x40095214 %Long 0x0 // LFSS_TIOCTL[5] PER.Set.simple ASD:0x40095218 %Long 0x0 // LFSS_TIOCTL[6] PER.Set.simple ASD:0x4009521C %Long 0x0 // LFSS_TIOCTL[7] PER.Set.simple ASD:0x40095220 %Long 0x0 // LFSS_TIOCTL[8] PER.Set.simple ASD:0x40095224 %Long 0x0 // LFSS_TIOCTL[9] PER.Set.simple ASD:0x40095228 %Long 0x0 // LFSS_TIOCTL[10] PER.Set.simple ASD:0x4009522C %Long 0x0 // LFSS_TIOCTL[11] PER.Set.simple ASD:0x40095230 %Long 0x0 // LFSS_TIOCTL[12] PER.Set.simple ASD:0x40095234 %Long 0x0 // LFSS_TIOCTL[13] PER.Set.simple ASD:0x40095238 %Long 0x0 // LFSS_TIOCTL[14] PER.Set.simple ASD:0x4009523C %Long 0x0 // LFSS_TIOCTL[15] PER.Set.simple ASD:0x40095280 %Long 0x0 // LFSS_TOUT3_0 PER.Set.simple ASD:0x40095284 %Long 0x0 // LFSS_TOUT7_4 PER.Set.simple ASD:0x40095288 %Long 0x0 // LFSS_TOUT11_8 PER.Set.simple ASD:0x4009528C %Long 0x0 // LFSS_TOUT15_12 PER.Set.simple ASD:0x40095290 %Long 0x0 // LFSS_TOE3_0 PER.Set.simple ASD:0x40095294 %Long 0x0 // LFSS_TOE7_4 PER.Set.simple ASD:0x40095298 %Long 0x0 // LFSS_TOE11_8 PER.Set.simple ASD:0x4009529C %Long 0x0 // LFSS_TOE15_12 // PER.Set.simple ASD:0x400952A0 %Long 0x0 // LFSS_TIN3_0; reason=read-only // PER.Set.simple ASD:0x400952A4 %Long 0x0 // LFSS_TIN7_4; reason=read-only // PER.Set.simple ASD:0x400952A8 %Long 0x0 // LFSS_TIN11_8; reason=read-only // PER.Set.simple ASD:0x400952AC %Long 0x0 // LFSS_TIN15_12; reason=read-only PER.Set.simple ASD:0x400952C0 %Long 0x0 // LFSS_HEARTBEAT PER.Set.simple ASD:0x400952FC %Long 0x0 // LFSS_TIOLOCK PER.Set.simple ASD:0x40095300 %Long 0x0 // LFSS_WDTEN PER.Set.simple ASD:0x40095304 %Long 0x0 // LFSS_WDTDBGCTL PER.Set.simple ASD:0x40095308 %Long 0x43 // LFSS_WDTCTL // PER.Set.simple ASD:0x40095310 %Long 0x0 // LFSS_WDTSTAT; reason=read-only PER.Set.simple ASD:0x400953FC %Long 0x0 // LFSS_WDTLOCK PER.Set.simple ASD:0x40095400 %Long 0x0 // LFSS_SPMEM[0] PER.Set.simple ASD:0x40095404 %Long 0x0 // LFSS_SPMEM[1] PER.Set.simple ASD:0x40095408 %Long 0x0 // LFSS_SPMEM[2] PER.Set.simple ASD:0x4009540C %Long 0x0 // LFSS_SPMEM[3] PER.Set.simple ASD:0x40095410 %Long 0x0 // LFSS_SPMEM[4] PER.Set.simple ASD:0x40095414 %Long 0x0 // LFSS_SPMEM[5] PER.Set.simple ASD:0x40095418 %Long 0x0 // LFSS_SPMEM[6] PER.Set.simple ASD:0x4009541C %Long 0x0 // LFSS_SPMEM[7] PER.Set.simple ASD:0x40095420 %Long 0x0 // LFSS_SPMEM[8] PER.Set.simple ASD:0x40095424 %Long 0x0 // LFSS_SPMEM[9] PER.Set.simple ASD:0x40095428 %Long 0x0 // LFSS_SPMEM[10] PER.Set.simple ASD:0x4009542C %Long 0x0 // LFSS_SPMEM[11] PER.Set.simple ASD:0x40095430 %Long 0x0 // LFSS_SPMEM[12] PER.Set.simple ASD:0x40095434 %Long 0x0 // LFSS_SPMEM[13] PER.Set.simple ASD:0x40095438 %Long 0x0 // LFSS_SPMEM[14] PER.Set.simple ASD:0x4009543C %Long 0x0 // LFSS_SPMEM[15] PER.Set.simple ASD:0x40095440 %Long 0x0 // LFSS_SPMEM[16] PER.Set.simple ASD:0x40095444 %Long 0x0 // LFSS_SPMEM[17] PER.Set.simple ASD:0x40095448 %Long 0x0 // LFSS_SPMEM[18] PER.Set.simple ASD:0x4009544C %Long 0x0 // LFSS_SPMEM[19] PER.Set.simple ASD:0x40095450 %Long 0x0 // LFSS_SPMEM[20] PER.Set.simple ASD:0x40095454 %Long 0x0 // LFSS_SPMEM[21] PER.Set.simple ASD:0x40095458 %Long 0x0 // LFSS_SPMEM[22] PER.Set.simple ASD:0x4009545C %Long 0x0 // LFSS_SPMEM[23] PER.Set.simple ASD:0x40095460 %Long 0x0 // LFSS_SPMEM[24] PER.Set.simple ASD:0x40095464 %Long 0x0 // LFSS_SPMEM[25] PER.Set.simple ASD:0x40095468 %Long 0x0 // LFSS_SPMEM[26] PER.Set.simple ASD:0x4009546C %Long 0x0 // LFSS_SPMEM[27] PER.Set.simple ASD:0x40095470 %Long 0x0 // LFSS_SPMEM[28] PER.Set.simple ASD:0x40095474 %Long 0x0 // LFSS_SPMEM[29] PER.Set.simple ASD:0x40095478 %Long 0x0 // LFSS_SPMEM[30] PER.Set.simple ASD:0x4009547C %Long 0x0 // LFSS_SPMEM[31] PER.Set.simple ASD:0x40095500 %Long 0x0 // LFSS_SPMWPROT0 PER.Set.simple ASD:0x40095504 %Long 0x0 // LFSS_SPMWPROT1 PER.Set.simple ASD:0x40095508 %Long 0x0 // LFSS_SPMWPROT2 PER.Set.simple ASD:0x4009550C %Long 0x0 // LFSS_SPMWPROT3 PER.Set.simple ASD:0x40095510 %Long 0x0 // LFSS_SPMWPROT4 PER.Set.simple ASD:0x40095514 %Long 0x0 // LFSS_SPMWPROT5 PER.Set.simple ASD:0x40095518 %Long 0x0 // LFSS_SPMWPROT6 PER.Set.simple ASD:0x4009551C %Long 0x0 // LFSS_SPMWPROT7 PER.Set.simple ASD:0x40095540 %Long 0x0 // LFSS_SPMTERASE0 PER.Set.simple ASD:0x40095544 %Long 0x0 // LFSS_SPMTERASE1 PER.Set.simple ASD:0x40095548 %Long 0x0 // LFSS_SPMTERASE2 PER.Set.simple ASD:0x4009554C %Long 0x0 // LFSS_SPMTERASE3 PER.Set.simple ASD:0x40095550 %Long 0x0 // LFSS_SPMTERASE4 PER.Set.simple ASD:0x40095554 %Long 0x0 // LFSS_SPMTERASE5 PER.Set.simple ASD:0x40095558 %Long 0x0 // LFSS_SPMTERASE6 PER.Set.simple ASD:0x4009555C %Long 0x0 // LFSS_SPMTERASE7 // MATHACL // MATHACL (PERIPHERALREGION) // MATHACL_GPRCM[%s] PER.Set.simple ASD:0x40410800 %Long 0x0 // MATHACL_PWREN // PER.Set.simple ASD:0x40410814 %Long 0x10000 // MATHACL_STAT; reason=read-only PER.Set.simple ASD:0x40411100 %Long 0x0 // MATHACL_CTL PER.Set.simple ASD:0x40411118 %Long 0x0 // MATHACL_OP2 PER.Set.simple ASD:0x4041111C %Long 0x0 // MATHACL_OP1 PER.Set.simple ASD:0x40411120 %Long 0x0 // MATHACL_RES1 PER.Set.simple ASD:0x40411124 %Long 0x0 // MATHACL_RES2 // PER.Set.simple ASD:0x40411130 %Long 0x0 // MATHACL_STATUS; reason=read-only // SPI (Serial Peripheral Interface) // SPI0 // SPI0_CPU_INT[%s] // PER.Set.simple ASD:0x40469020 %Long 0x0 // SPI0_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40469028 %Long 0x0 // SPI0_CPU_INT_IMASK // PER.Set.simple ASD:0x40469030 %Long 0x0 // SPI0_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40469038 %Long 0x0 // SPI0_CPU_INT_MIS; reason=read-only // SPI0_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40469050 %Long 0x0 // SPI0_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40469058 %Long 0x0 // SPI0_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40469060 %Long 0x0 // SPI0_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40469068 %Long 0x0 // SPI0_DMA_TRIG_RX_MIS; reason=read-only // SPI0_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40469080 %Long 0x0 // SPI0_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40469088 %Long 0x0 // SPI0_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40469090 %Long 0x0 // SPI0_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40469098 %Long 0x0 // SPI0_DMA_TRIG_TX_MIS; reason=read-only // SPI0_GPRCM[%s] PER.Set.simple ASD:0x40468800 %Long 0x0 // SPI0_PWREN PER.Set.simple ASD:0x40468808 %Long 0x0 // SPI0_CLKCFG // PER.Set.simple ASD:0x40468814 %Long 0x10000 // SPI0_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40469000 %Long 0x0 // SPI0_CLKDIV PER.Set.simple ASD:0x40469004 %Long 0x0 // SPI0_CLKSEL PER.Set.simple ASD:0x40469018 %Long 0x0 // SPI0_PDBGCTL // PER.Set.simple ASD:0x404690E0 %Long 0x0 // SPI0_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40469100 %Long 0x0 // SPI0_CTL0 PER.Set.simple ASD:0x40469104 %Long 0x0 // SPI0_CTL1 PER.Set.simple ASD:0x40469108 %Long 0x0 // SPI0_CLKCTL PER.Set.simple ASD:0x4046910C %Long 0x0 // SPI0_IFLS // PER.Set.simple ASD:0x40469110 %Long 0x0 // SPI0_STAT; reason=read-only // PER.Set.simple ASD:0x40469130 %Long 0x0 // SPI0_RXDATA; reason=read-only PER.Set.simple ASD:0x40469140 %Long 0x0 // SPI0_TXDATA // SPI1 // SPI1_CPU_INT[%s] // PER.Set.simple ASD:0x4046B020 %Long 0x0 // SPI1_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x4046B028 %Long 0x0 // SPI1_CPU_INT_IMASK // PER.Set.simple ASD:0x4046B030 %Long 0x0 // SPI1_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x4046B038 %Long 0x0 // SPI1_CPU_INT_MIS; reason=read-only // SPI1_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x4046B050 %Long 0x0 // SPI1_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x4046B058 %Long 0x0 // SPI1_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x4046B060 %Long 0x0 // SPI1_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x4046B068 %Long 0x0 // SPI1_DMA_TRIG_RX_MIS; reason=read-only // SPI1_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x4046B080 %Long 0x0 // SPI1_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x4046B088 %Long 0x0 // SPI1_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x4046B090 %Long 0x0 // SPI1_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x4046B098 %Long 0x0 // SPI1_DMA_TRIG_TX_MIS; reason=read-only // SPI1_GPRCM[%s] PER.Set.simple ASD:0x4046A800 %Long 0x0 // SPI1_PWREN PER.Set.simple ASD:0x4046A808 %Long 0x0 // SPI1_CLKCFG // PER.Set.simple ASD:0x4046A814 %Long 0x10000 // SPI1_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x4046B000 %Long 0x0 // SPI1_CLKDIV PER.Set.simple ASD:0x4046B004 %Long 0x0 // SPI1_CLKSEL PER.Set.simple ASD:0x4046B018 %Long 0x0 // SPI1_PDBGCTL // PER.Set.simple ASD:0x4046B0E0 %Long 0x0 // SPI1_EVT_MODE; reason=read-only PER.Set.simple ASD:0x4046B100 %Long 0x0 // SPI1_CTL0 PER.Set.simple ASD:0x4046B104 %Long 0x0 // SPI1_CTL1 PER.Set.simple ASD:0x4046B108 %Long 0x0 // SPI1_CLKCTL PER.Set.simple ASD:0x4046B10C %Long 0x0 // SPI1_IFLS // PER.Set.simple ASD:0x4046B110 %Long 0x0 // SPI1_STAT; reason=read-only // PER.Set.simple ASD:0x4046B130 %Long 0x0 // SPI1_RXDATA; reason=read-only PER.Set.simple ASD:0x4046B140 %Long 0x0 // SPI1_TXDATA // SPI2 // SPI2_CPU_INT[%s] // PER.Set.simple ASD:0x4046D020 %Long 0x0 // SPI2_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x4046D028 %Long 0x0 // SPI2_CPU_INT_IMASK // PER.Set.simple ASD:0x4046D030 %Long 0x0 // SPI2_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x4046D038 %Long 0x0 // SPI2_CPU_INT_MIS; reason=read-only // SPI2_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x4046D050 %Long 0x0 // SPI2_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x4046D058 %Long 0x0 // SPI2_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x4046D060 %Long 0x0 // SPI2_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x4046D068 %Long 0x0 // SPI2_DMA_TRIG_RX_MIS; reason=read-only // SPI2_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x4046D080 %Long 0x0 // SPI2_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x4046D088 %Long 0x0 // SPI2_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x4046D090 %Long 0x0 // SPI2_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x4046D098 %Long 0x0 // SPI2_DMA_TRIG_TX_MIS; reason=read-only // SPI2_GPRCM[%s] PER.Set.simple ASD:0x4046C800 %Long 0x0 // SPI2_PWREN PER.Set.simple ASD:0x4046C808 %Long 0x0 // SPI2_CLKCFG // PER.Set.simple ASD:0x4046C814 %Long 0x10000 // SPI2_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x4046D000 %Long 0x0 // SPI2_CLKDIV PER.Set.simple ASD:0x4046D004 %Long 0x0 // SPI2_CLKSEL PER.Set.simple ASD:0x4046D018 %Long 0x0 // SPI2_PDBGCTL // PER.Set.simple ASD:0x4046D0E0 %Long 0x0 // SPI2_EVT_MODE; reason=read-only PER.Set.simple ASD:0x4046D100 %Long 0x0 // SPI2_CTL0 PER.Set.simple ASD:0x4046D104 %Long 0x0 // SPI2_CTL1 PER.Set.simple ASD:0x4046D108 %Long 0x0 // SPI2_CLKCTL PER.Set.simple ASD:0x4046D10C %Long 0x0 // SPI2_IFLS // PER.Set.simple ASD:0x4046D110 %Long 0x0 // SPI2_STAT; reason=read-only // PER.Set.simple ASD:0x4046D130 %Long 0x0 // SPI2_RXDATA; reason=read-only PER.Set.simple ASD:0x4046D140 %Long 0x0 // SPI2_TXDATA // SYSCTL (System Controller) // SYSCTL (mem_map) PER.Set.simple ASD:0x400AF800 %Long 0x0 // SYSCTL_MGMT_ADC12B4MSPS0_PWREN PER.Set.simple ASD:0x400AF808 %Long 0x0 // SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG // PER.Set.simple ASD:0x400AF814 %Long 0x0 // SYSCTL_MGMT_ADC12B4MSPS0_STAT; reason=read-only // PER.Set.simple ASD:0x400B0020 %Long 0x0 // SYSCTL_IIDX; reason=read-only PER.Set.simple ASD:0x400B0028 %Long 0x0 // SYSCTL_IMASK // PER.Set.simple ASD:0x400B0030 %Long 0xE0 // SYSCTL_RIS; reason=read-only // PER.Set.simple ASD:0x400B0038 %Long 0x0 // SYSCTL_MIS; reason=read-only // PER.Set.simple ASD:0x400B0050 %Long 0x0 // SYSCTL_NMIIIDX; reason=read-only // PER.Set.simple ASD:0x400B0060 %Long 0x0 // SYSCTL_NMIRIS; reason=read-only PER.Set.simple ASD:0x400B0100 %Long 0x20000 // SYSCTL_SYSOSCCFG PER.Set.simple ASD:0x400B0104 %Long 0x10200 // SYSCTL_MCLKCFG PER.Set.simple ASD:0x400B0108 %Long 0x101 // SYSCTL_HSCLKEN PER.Set.simple ASD:0x400B010C %Long 0x0 // SYSCTL_HSCLKCFG PER.Set.simple ASD:0x400B0110 %Long 0x1000300A // SYSCTL_HFCLKCLKCFG PER.Set.simple ASD:0x400B0114 %Long 0x3 // SYSCTL_LFCLKCFG PER.Set.simple ASD:0x400B0120 %Long 0x31063 // SYSCTL_SYSPLLCFG0 PER.Set.simple ASD:0x400B0124 %Long 0x300 // SYSCTL_SYSPLLCFG1 PER.Set.simple ASD:0x400B0128 %Long 0x8103060A // SYSCTL_SYSPLLPARAM0 PER.Set.simple ASD:0x400B012C %Long 0xFF00011F // SYSCTL_SYSPLLPARAM1 PER.Set.simple ASD:0x400B0138 %Long 0x0 // SYSCTL_GENCLKCFG PER.Set.simple ASD:0x400B013C %Long 0x0 // SYSCTL_GENCLKEN PER.Set.simple ASD:0x400B0140 %Long 0x0 // SYSCTL_PMODECFG // PER.Set.simple ASD:0x400B0150 %Long 0x1BBC // SYSCTL_FCC; reason=read-only PER.Set.simple ASD:0x400B0170 %Long 0x0 // SYSCTL_SYSOSCTRIMUSER PER.Set.simple ASD:0x400B0178 %Long 0x0 // SYSCTL_SRAMBOUNDARY PER.Set.simple ASD:0x400B017C %Long 0x0 // SYSCTL_SRAMBOUNDARYHIGH PER.Set.simple ASD:0x400B0180 %Long 0x6 // SYSCTL_SYSTEMCFG PER.Set.simple ASD:0x400B0184 %Long 0x0 // SYSCTL_SRAMCFG PER.Set.simple ASD:0x400B0200 %Long 0x0 // SYSCTL_WRITELOCK // PER.Set.simple ASD:0x400B0204 %Long 0x20200B10 // SYSCTL_CLKSTATUS; reason=read-only // PER.Set.simple ASD:0x400B0208 %Long 0x20062 // SYSCTL_SYSSTATUS; reason=read-only // PER.Set.simple ASD:0x400B020C %Long 0xC400B0 // SYSCTL_DEDERRADDR; reason=read-only // PER.Set.simple ASD:0x400B0220 %Long 0x0 // SYSCTL_RSTCAUSE; reason=read-only PER.Set.simple ASD:0x400B0300 %Long 0x0 // SYSCTL_RESETLEVEL PER.Set.simple ASD:0x400B0308 %Long 0x0 // SYSCTL_BORTHRESHOLD PER.Set.simple ASD:0x400B0400 %Long 0x0 // SYSCTL_SHUTDNSTORE0 PER.Set.simple ASD:0x400B0404 %Long 0x0 // SYSCTL_SHUTDNSTORE1 PER.Set.simple ASD:0x400B0408 %Long 0x0 // SYSCTL_SHUTDNSTORE2 PER.Set.simple ASD:0x400B040C %Long 0x0 // SYSCTL_SHUTDNSTORE3 PER.Set.simple ASD:0x400B1800 %Long 0x0 // SYSCTL_MGMT_ADC12B4MSPS1_PWREN PER.Set.simple ASD:0x400B1808 %Long 0x0 // SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG // PER.Set.simple ASD:0x400B1814 %Long 0x0 // SYSCTL_MGMT_ADC12B4MSPS1_STAT; reason=read-only PER.Set.simple ASD:0x400B2000 %Long 0x0 // SYSCTL_FWEPROTMAIN PER.Set.simple ASD:0x400B2014 %Long 0x0 // SYSCTL_FWPROTMAINDATA PER.Set.simple ASD:0x400B2018 %Long 0x40 // SYSCTL_FRXPROTMAINSTART PER.Set.simple ASD:0x400B201C %Long 0x0 // SYSCTL_FRXPROTMAINEND PER.Set.simple ASD:0x400B2020 %Long 0x0 // SYSCTL_FIPPROTMAINSTART PER.Set.simple ASD:0x400B2024 %Long 0x0 // SYSCTL_FIPPROTMAINEND // PER.Set.simple ASD:0x400B2048 %Long 0x1 // SYSCTL_SECSTATUS; reason=read-only PER.Set.simple ASD:0x400B7800 %Long 0x0 // SYSCTL_MGMT_ANACOMP0_PWREN PER.Set.simple ASD:0x400B7808 %Long 0x0 // SYSCTL_MGMT_ANACOMP0_CLKCFG // PER.Set.simple ASD:0x400B7814 %Long 0x0 // SYSCTL_MGMT_ANACOMP0_STAT; reason=read-only PER.Set.simple ASD:0x400B9800 %Long 0x0 // SYSCTL_MGMT_ANACOMP1_PWREN PER.Set.simple ASD:0x400B9808 %Long 0x0 // SYSCTL_MGMT_ANACOMP1_CLKCFG // PER.Set.simple ASD:0x400B9814 %Long 0x0 // SYSCTL_MGMT_ANACOMP1_STAT; reason=read-only PER.Set.simple ASD:0x400BB800 %Long 0x0 // SYSCTL_MGMT_ANACOMP2_PWREN PER.Set.simple ASD:0x400BB808 %Long 0x0 // SYSCTL_MGMT_ANACOMP2_CLKCFG // PER.Set.simple ASD:0x400BB814 %Long 0x0 // SYSCTL_MGMT_ANACOMP2_STAT; reason=read-only PER.Set.simple ASD:0x400C7800 %Long 0x0 // SYSCTL_MGMT_DAC12B0_PWREN // PER.Set.simple ASD:0x400C7814 %Long 0x0 // SYSCTL_MGMT_DAC12B0_STAT; reason=read-only PER.Set.simple ASD:0x400DF800 %Long 0x0 // SYSCTL_MGMT_VREF_PWREN // PER.Set.simple ASD:0x400DF814 %Long 0x0 // SYSCTL_MGMT_VREF_STAT; reason=read-only PER.Set.simple ASD:0x4012F800 %Long 0x0 // SYSCTL_MGMT_WWDTLP0_PWREN // PER.Set.simple ASD:0x4012F814 %Long 0x0 // SYSCTL_MGMT_WWDTLP0_STAT; reason=read-only PER.Set.simple ASD:0x40131800 %Long 0x0 // SYSCTL_MGMT_WWDTLP1_PWREN // PER.Set.simple ASD:0x40131814 %Long 0x0 // SYSCTL_MGMT_WWDTLP1_STAT; reason=read-only PER.Set.simple ASD:0x40133800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN // PER.Set.simple ASD:0x40133814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT; reason=read-only PER.Set.simple ASD:0x4013F800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN // PER.Set.simple ASD:0x4013F814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT; reason=read-only PER.Set.simple ASD:0x40141800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCQEILP1_PWREN // PER.Set.simple ASD:0x40141814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCQEILP1_STAT; reason=read-only PER.Set.simple ASD:0x40143808 %Long 0x0 // SYSCTL_MGMT_RTC_CLKCFG PER.Set.simple ASD:0x40145800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCLP4_PWREN // PER.Set.simple ASD:0x40145814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCLP4_STAT; reason=read-only PER.Set.simple ASD:0x4014F800 %Long 0x0 // SYSCTL_MGMT_GPIO0_PWREN // PER.Set.simple ASD:0x4014F814 %Long 0x0 // SYSCTL_MGMT_GPIO0_STAT; reason=read-only PER.Set.simple ASD:0x40151800 %Long 0x0 // SYSCTL_MGMT_GPIO1_PWREN // PER.Set.simple ASD:0x40151814 %Long 0x0 // SYSCTL_MGMT_GPIO1_STAT; reason=read-only PER.Set.simple ASD:0x40153800 %Long 0x0 // SYSCTL_MGMT_GPIO2_PWREN // PER.Set.simple ASD:0x40153814 %Long 0x0 // SYSCTL_MGMT_GPIO2_STAT; reason=read-only PER.Set.simple ASD:0x4019F800 %Long 0x0 // SYSCTL_MGMT_I2C0_PWREN PER.Set.simple ASD:0x4019F808 %Long 0x0 // SYSCTL_MGMT_I2C0_CLKCFG // PER.Set.simple ASD:0x4019F814 %Long 0x0 // SYSCTL_MGMT_I2C0_STAT; reason=read-only PER.Set.simple ASD:0x401A1800 %Long 0x0 // SYSCTL_MGMT_I2C1_PWREN PER.Set.simple ASD:0x401A1808 %Long 0x0 // SYSCTL_MGMT_I2C1_CLKCFG // PER.Set.simple ASD:0x401A1814 %Long 0x0 // SYSCTL_MGMT_I2C1_STAT; reason=read-only PER.Set.simple ASD:0x401A3800 %Long 0x0 // SYSCTL_MGMT_I2C2_PWREN PER.Set.simple ASD:0x401A3808 %Long 0x0 // SYSCTL_MGMT_I2C2_CLKCFG // PER.Set.simple ASD:0x401A3814 %Long 0x0 // SYSCTL_MGMT_I2C2_STAT; reason=read-only PER.Set.simple ASD:0x401AF800 %Long 0x0 // SYSCTL_MGMT_UARTLP0_PWREN PER.Set.simple ASD:0x401AF808 %Long 0x0 // SYSCTL_MGMT_UARTLP0_CLKCFG // PER.Set.simple ASD:0x401AF814 %Long 0x0 // SYSCTL_MGMT_UARTLP0_STAT; reason=read-only PER.Set.simple ASD:0x401B7800 %Long 0x0 // SYSCTL_MGMT_UARTADVLP0_PWREN PER.Set.simple ASD:0x401B7808 %Long 0x0 // SYSCTL_MGMT_UARTADVLP0_CLKCFG // PER.Set.simple ASD:0x401B7814 %Long 0x0 // SYSCTL_MGMT_UARTADVLP0_STAT; reason=read-only PER.Set.simple ASD:0x401B9800 %Long 0x0 // SYSCTL_MGMT_UARTADVLP1_PWREN PER.Set.simple ASD:0x401B9808 %Long 0x0 // SYSCTL_MGMT_UARTADVLP1_CLKCFG // PER.Set.simple ASD:0x401B9814 %Long 0x0 // SYSCTL_MGMT_UARTADVLP1_STAT; reason=read-only PER.Set.simple ASD:0x404BF800 %Long 0x0 // SYSCTL_MGMT_MATHACL_PWREN // PER.Set.simple ASD:0x404BF814 %Long 0x0 // SYSCTL_MGMT_MATHACL_STAT; reason=read-only PER.Set.simple ASD:0x404EF800 %Long 0x0 // SYSCTL_MGMT_CRC0_PWREN // PER.Set.simple ASD:0x404EF814 %Long 0x0 // SYSCTL_MGMT_CRC0_STAT; reason=read-only PER.Set.simple ASD:0x404F1800 %Long 0x0 // SYSCTL_MGMT_AES_PWREN // PER.Set.simple ASD:0x404F1814 %Long 0x0 // SYSCTL_MGMT_AES_STAT; reason=read-only PER.Set.simple ASD:0x404F3800 %Long 0x0 // SYSCTL_MGMT_TRNG_PWREN // PER.Set.simple ASD:0x404F3814 %Long 0x0 // SYSCTL_MGMT_TRNG_STAT; reason=read-only PER.Set.simple ASD:0x40517800 %Long 0x0 // SYSCTL_MGMT_SPI0_PWREN PER.Set.simple ASD:0x40517808 %Long 0x0 // SYSCTL_MGMT_SPI0_CLKCFG // PER.Set.simple ASD:0x40517814 %Long 0x0 // SYSCTL_MGMT_SPI0_STAT; reason=read-only PER.Set.simple ASD:0x40519800 %Long 0x0 // SYSCTL_MGMT_SPI1_PWREN PER.Set.simple ASD:0x40519808 %Long 0x0 // SYSCTL_MGMT_SPI1_CLKCFG // PER.Set.simple ASD:0x40519814 %Long 0x0 // SYSCTL_MGMT_SPI1_STAT; reason=read-only PER.Set.simple ASD:0x4051B800 %Long 0x0 // SYSCTL_MGMT_SPI2_PWREN PER.Set.simple ASD:0x4051B808 %Long 0x0 // SYSCTL_MGMT_SPI2_CLKCFG // PER.Set.simple ASD:0x4051B814 %Long 0x0 // SYSCTL_MGMT_SPI2_STAT; reason=read-only PER.Set.simple ASD:0x405AF800 %Long 0x0 // SYSCTL_MGMT_UART0_PWREN PER.Set.simple ASD:0x405AF808 %Long 0x0 // SYSCTL_MGMT_UART0_CLKCFG // PER.Set.simple ASD:0x405AF814 %Long 0x0 // SYSCTL_MGMT_UART0_STAT; reason=read-only PER.Set.simple ASD:0x405B1800 %Long 0x0 // SYSCTL_MGMT_UART1_PWREN PER.Set.simple ASD:0x405B1808 %Long 0x0 // SYSCTL_MGMT_UART1_CLKCFG // PER.Set.simple ASD:0x405B1814 %Long 0x0 // SYSCTL_MGMT_UART1_STAT; reason=read-only PER.Set.simple ASD:0x405B3800 %Long 0x0 // SYSCTL_MGMT_UART2_PWREN PER.Set.simple ASD:0x405B3808 %Long 0x0 // SYSCTL_MGMT_UART2_CLKCFG // PER.Set.simple ASD:0x405B3814 %Long 0x0 // SYSCTL_MGMT_UART2_STAT; reason=read-only PER.Set.simple ASD:0x405B5800 %Long 0x0 // SYSCTL_MGMT_UART3_PWREN PER.Set.simple ASD:0x405B5808 %Long 0x0 // SYSCTL_MGMT_UART3_CLKCFG // PER.Set.simple ASD:0x405B5814 %Long 0x0 // SYSCTL_MGMT_UART3_STAT; reason=read-only PER.Set.simple ASD:0x405BD800 %Long 0x0 // SYSCTL_MGMT_MCAN0_PWREN // PER.Set.simple ASD:0x405BD814 %Long 0x0 // SYSCTL_MGMT_MCAN0_STAT; reason=read-only PER.Set.simple ASD:0x405C5800 %Long 0x0 // SYSCTL_MGMT_MCAN1_PWREN // PER.Set.simple ASD:0x405C5814 %Long 0x0 // SYSCTL_MGMT_MCAN1_STAT; reason=read-only PER.Set.simple ASD:0x4090F800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN // PER.Set.simple ASD:0x4090F814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT; reason=read-only PER.Set.simple ASD:0x40911800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN // PER.Set.simple ASD:0x40911814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT; reason=read-only PER.Set.simple ASD:0x40917800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN // PER.Set.simple ASD:0x40917814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT; reason=read-only PER.Set.simple ASD:0x40919800 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN // PER.Set.simple ASD:0x40919814 %Long 0x0 // SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT; reason=read-only PER.Set.simple ASD:0x4091F800 %Long 0x0 // SYSCTL_MGMT_GPTIMER32B2CC0_PWREN // PER.Set.simple ASD:0x4091F814 %Long 0x0 // SYSCTL_MGMT_GPTIMER32B2CC0_STAT; reason=read-only // TIMA (Advanced Timer) // TIMA0 PER.Set.simple ASD:0x40860400 %Long 0x0 // TIMA0_FSUB_0 PER.Set.simple ASD:0x40860404 %Long 0x0 // TIMA0_FSUB_1 PER.Set.simple ASD:0x40860444 %Long 0x0 // TIMA0_FPUB_0 PER.Set.simple ASD:0x40860448 %Long 0x0 // TIMA0_FPUB_1 // TIMA0_GPRCM[%s] PER.Set.simple ASD:0x40860800 %Long 0x1 // TIMA0_PWREN // PER.Set.simple ASD:0x40860814 %Long 0x10000 // TIMA0_STAT; reason=read-only PER.Set.simple ASD:0x40861000 %Long 0x0 // TIMA0_CLKDIV PER.Set.simple ASD:0x40861008 %Long 0x2 // TIMA0_CLKSEL PER.Set.simple ASD:0x40861018 %Long 0x3 // TIMA0_PDBGCTL // TIMA0_INT_EVENT[0] // PER.Set.simple ASD:0x40861020 %Long 0x0 // TIMA0_IIDX; reason=read-only PER.Set.simple ASD:0x40861028 %Long 0x0 // TIMA0_IMASK // PER.Set.simple ASD:0x40861030 %Long 0x0 // TIMA0_RIS; reason=read-only // PER.Set.simple ASD:0x40861038 %Long 0x0 // TIMA0_MIS; reason=read-only // TIMA0_INT_EVENT[1] // PER.Set.simple ASD:0x4086104C %Long 0x0 // TIMA0_IIDX; reason=read-only PER.Set.simple ASD:0x40861054 %Long 0x0 // TIMA0_IMASK // PER.Set.simple ASD:0x4086105C %Long 0x0 // TIMA0_RIS; reason=read-only // PER.Set.simple ASD:0x40861064 %Long 0x0 // TIMA0_MIS; reason=read-only // TIMA0_INT_EVENT[2] // PER.Set.simple ASD:0x40861078 %Long 0x0 // TIMA0_IIDX; reason=read-only PER.Set.simple ASD:0x40861080 %Long 0x0 // TIMA0_IMASK // PER.Set.simple ASD:0x40861088 %Long 0x0 // TIMA0_RIS; reason=read-only // PER.Set.simple ASD:0x40861090 %Long 0x0 // TIMA0_MIS; reason=read-only // PER.Set.simple ASD:0x408610E0 %Long 0x29 // TIMA0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x408610FC %Long 0x11110000 // TIMA0_DESC; reason=read-only // TIMA0_COMMONREGS[%s] PER.Set.simple ASD:0x40861100 %Long 0x0 // TIMA0_CCPD PER.Set.simple ASD:0x40861104 %Long 0x0 // TIMA0_ODIS PER.Set.simple ASD:0x40861108 %Long 0x1 // TIMA0_CCLKCTL PER.Set.simple ASD:0x4086110C %Long 0x0 // TIMA0_CPS // PER.Set.simple ASD:0x40861110 %Long 0x0 // TIMA0_CPSV; reason=read-only PER.Set.simple ASD:0x40861114 %Long 0x0 // TIMA0_CTTRIGCTL PER.Set.simple ASD:0x40861120 %Long 0x0 // TIMA0_FSCTL PER.Set.simple ASD:0x40861124 %Long 0x1 // TIMA0_GCTL // TIMA0_COUNTERREGS[%s] PER.Set.simple ASD:0x40861800 %Long 0x0 // TIMA0_CTR PER.Set.simple ASD:0x40861804 %Long 0xFF80 // TIMA0_CTRCTL PER.Set.simple ASD:0x40861808 %Long 0x0 // TIMA0_LOAD PER.Set.simple ASD:0x40861810 %Long 0x0 // TIMA0_CC_01[0] PER.Set.simple ASD:0x40861814 %Long 0x0 // TIMA0_CC_01[1] PER.Set.simple ASD:0x40861818 %Long 0x0 // TIMA0_CC_23[0] PER.Set.simple ASD:0x4086181C %Long 0x0 // TIMA0_CC_23[1] PER.Set.simple ASD:0x40861820 %Long 0x0 // TIMA0_CC_45[0] PER.Set.simple ASD:0x40861824 %Long 0x0 // TIMA0_CC_45[1] PER.Set.simple ASD:0x40861830 %Long 0x0 // TIMA0_CCCTL_01[0] PER.Set.simple ASD:0x40861834 %Long 0x0 // TIMA0_CCCTL_01[1] PER.Set.simple ASD:0x40861838 %Long 0x0 // TIMA0_CCCTL_23[0] PER.Set.simple ASD:0x4086183C %Long 0x0 // TIMA0_CCCTL_23[1] PER.Set.simple ASD:0x40861840 %Long 0x0 // TIMA0_CCCTL_45[0] PER.Set.simple ASD:0x40861844 %Long 0x0 // TIMA0_CCCTL_45[1] PER.Set.simple ASD:0x40861850 %Long 0x0 // TIMA0_OCTL_01[0] PER.Set.simple ASD:0x40861854 %Long 0x0 // TIMA0_OCTL_01[1] PER.Set.simple ASD:0x40861858 %Long 0x0 // TIMA0_OCTL_23[0] PER.Set.simple ASD:0x4086185C %Long 0x0 // TIMA0_OCTL_23[1] PER.Set.simple ASD:0x40861870 %Long 0x0 // TIMA0_CCACT_01[0] PER.Set.simple ASD:0x40861874 %Long 0x0 // TIMA0_CCACT_01[1] PER.Set.simple ASD:0x40861878 %Long 0x0 // TIMA0_CCACT_23[0] PER.Set.simple ASD:0x4086187C %Long 0x0 // TIMA0_CCACT_23[1] PER.Set.simple ASD:0x40861880 %Long 0x0 // TIMA0_IFCTL_01[0] PER.Set.simple ASD:0x40861884 %Long 0x0 // TIMA0_IFCTL_01[1] PER.Set.simple ASD:0x40861888 %Long 0x0 // TIMA0_IFCTL_23[0] PER.Set.simple ASD:0x4086188C %Long 0x0 // TIMA0_IFCTL_23[1] PER.Set.simple ASD:0x408618A0 %Long 0x0 // TIMA0_PL PER.Set.simple ASD:0x408618A4 %Long 0x0 // TIMA0_DBCTL PER.Set.simple ASD:0x408618B0 %Long 0x0 // TIMA0_TSEL // PER.Set.simple ASD:0x408618B4 %Long 0x0 // TIMA0_RC; reason=read-only PER.Set.simple ASD:0x408618B8 %Long 0x0 // TIMA0_RCLD PER.Set.simple ASD:0x408618D0 %Long 0x0 // TIMA0_FCTL PER.Set.simple ASD:0x408618D4 %Long 0x0 // TIMA0_FIFCTL // TIMA1 PER.Set.simple ASD:0x40862400 %Long 0x0 // TIMA1_FSUB_0 PER.Set.simple ASD:0x40862404 %Long 0x0 // TIMA1_FSUB_1 PER.Set.simple ASD:0x40862444 %Long 0x0 // TIMA1_FPUB_0 PER.Set.simple ASD:0x40862448 %Long 0x0 // TIMA1_FPUB_1 // TIMA1_GPRCM[%s] PER.Set.simple ASD:0x40862800 %Long 0x1 // TIMA1_PWREN // PER.Set.simple ASD:0x40862814 %Long 0x10000 // TIMA1_STAT; reason=read-only PER.Set.simple ASD:0x40863000 %Long 0x0 // TIMA1_CLKDIV PER.Set.simple ASD:0x40863008 %Long 0x2 // TIMA1_CLKSEL PER.Set.simple ASD:0x40863018 %Long 0x3 // TIMA1_PDBGCTL // TIMA1_INT_EVENT[0] // PER.Set.simple ASD:0x40863020 %Long 0x0 // TIMA1_IIDX; reason=read-only PER.Set.simple ASD:0x40863028 %Long 0x0 // TIMA1_IMASK // PER.Set.simple ASD:0x40863030 %Long 0x0 // TIMA1_RIS; reason=read-only // PER.Set.simple ASD:0x40863038 %Long 0x0 // TIMA1_MIS; reason=read-only // TIMA1_INT_EVENT[1] // PER.Set.simple ASD:0x4086304C %Long 0x0 // TIMA1_IIDX; reason=read-only PER.Set.simple ASD:0x40863054 %Long 0x0 // TIMA1_IMASK // PER.Set.simple ASD:0x4086305C %Long 0x0 // TIMA1_RIS; reason=read-only // PER.Set.simple ASD:0x40863064 %Long 0x0 // TIMA1_MIS; reason=read-only // TIMA1_INT_EVENT[2] // PER.Set.simple ASD:0x40863078 %Long 0x0 // TIMA1_IIDX; reason=read-only PER.Set.simple ASD:0x40863080 %Long 0x0 // TIMA1_IMASK // PER.Set.simple ASD:0x40863088 %Long 0x0 // TIMA1_RIS; reason=read-only // PER.Set.simple ASD:0x40863090 %Long 0x0 // TIMA1_MIS; reason=read-only // PER.Set.simple ASD:0x408630E0 %Long 0x29 // TIMA1_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x408630FC %Long 0x11110000 // TIMA1_DESC; reason=read-only // TIMA1_COMMONREGS[%s] PER.Set.simple ASD:0x40863100 %Long 0x0 // TIMA1_CCPD PER.Set.simple ASD:0x40863104 %Long 0x0 // TIMA1_ODIS PER.Set.simple ASD:0x40863108 %Long 0x1 // TIMA1_CCLKCTL PER.Set.simple ASD:0x4086310C %Long 0x0 // TIMA1_CPS // PER.Set.simple ASD:0x40863110 %Long 0x0 // TIMA1_CPSV; reason=read-only PER.Set.simple ASD:0x40863114 %Long 0x0 // TIMA1_CTTRIGCTL PER.Set.simple ASD:0x40863120 %Long 0x0 // TIMA1_FSCTL PER.Set.simple ASD:0x40863124 %Long 0x1 // TIMA1_GCTL // TIMA1_COUNTERREGS[%s] PER.Set.simple ASD:0x40863800 %Long 0x0 // TIMA1_CTR PER.Set.simple ASD:0x40863804 %Long 0xFF80 // TIMA1_CTRCTL PER.Set.simple ASD:0x40863808 %Long 0x0 // TIMA1_LOAD PER.Set.simple ASD:0x40863810 %Long 0x0 // TIMA1_CC_01[0] PER.Set.simple ASD:0x40863814 %Long 0x0 // TIMA1_CC_01[1] PER.Set.simple ASD:0x40863820 %Long 0x0 // TIMA1_CC_45[0] PER.Set.simple ASD:0x40863824 %Long 0x0 // TIMA1_CC_45[1] PER.Set.simple ASD:0x40863830 %Long 0x0 // TIMA1_CCCTL_01[0] PER.Set.simple ASD:0x40863834 %Long 0x0 // TIMA1_CCCTL_01[1] PER.Set.simple ASD:0x40863840 %Long 0x0 // TIMA1_CCCTL_45[0] PER.Set.simple ASD:0x40863844 %Long 0x0 // TIMA1_CCCTL_45[1] PER.Set.simple ASD:0x40863850 %Long 0x0 // TIMA1_OCTL_01[0] PER.Set.simple ASD:0x40863854 %Long 0x0 // TIMA1_OCTL_01[1] PER.Set.simple ASD:0x40863870 %Long 0x0 // TIMA1_CCACT_01[0] PER.Set.simple ASD:0x40863874 %Long 0x0 // TIMA1_CCACT_01[1] PER.Set.simple ASD:0x40863880 %Long 0x0 // TIMA1_IFCTL_01[0] PER.Set.simple ASD:0x40863884 %Long 0x0 // TIMA1_IFCTL_01[1] PER.Set.simple ASD:0x408638A0 %Long 0x0 // TIMA1_PL PER.Set.simple ASD:0x408638A4 %Long 0x0 // TIMA1_DBCTL PER.Set.simple ASD:0x408638B0 %Long 0x0 // TIMA1_TSEL PER.Set.simple ASD:0x408638D0 %Long 0x0 // TIMA1_FCTL PER.Set.simple ASD:0x408638D4 %Long 0x0 // TIMA1_FIFCTL // TIMG (General Purpose Timer) // TIMG12 PER.Set.simple ASD:0x40870400 %Long 0x0 // TIMG12_FSUB_0 PER.Set.simple ASD:0x40870404 %Long 0x0 // TIMG12_FSUB_1 PER.Set.simple ASD:0x40870444 %Long 0x0 // TIMG12_FPUB_0 PER.Set.simple ASD:0x40870448 %Long 0x0 // TIMG12_FPUB_1 // TIMG12_GPRCM[%s] PER.Set.simple ASD:0x40870800 %Long 0x1 // TIMG12_PWREN // PER.Set.simple ASD:0x40870814 %Long 0x10000 // TIMG12_STAT; reason=read-only PER.Set.simple ASD:0x40871000 %Long 0x0 // TIMG12_CLKDIV PER.Set.simple ASD:0x40871008 %Long 0x2 // TIMG12_CLKSEL PER.Set.simple ASD:0x40871018 %Long 0x3 // TIMG12_PDBGCTL // TIMG12_INT_EVENT[0] // PER.Set.simple ASD:0x40871020 %Long 0x9 // TIMG12_IIDX; reason=read-only PER.Set.simple ASD:0x40871028 %Long 0x100 // TIMG12_IMASK // PER.Set.simple ASD:0x40871030 %Long 0x100 // TIMG12_RIS; reason=read-only // PER.Set.simple ASD:0x40871038 %Long 0x100 // TIMG12_MIS; reason=read-only // TIMG12_INT_EVENT[1] // PER.Set.simple ASD:0x4087104C %Long 0x0 // TIMG12_IIDX; reason=read-only PER.Set.simple ASD:0x40871054 %Long 0x0 // TIMG12_IMASK // PER.Set.simple ASD:0x4087105C %Long 0x0 // TIMG12_RIS; reason=read-only // PER.Set.simple ASD:0x40871064 %Long 0x0 // TIMG12_MIS; reason=read-only // TIMG12_INT_EVENT[2] // PER.Set.simple ASD:0x40871078 %Long 0x0 // TIMG12_IIDX; reason=read-only PER.Set.simple ASD:0x40871080 %Long 0x0 // TIMG12_IMASK // PER.Set.simple ASD:0x40871088 %Long 0x0 // TIMG12_RIS; reason=read-only // PER.Set.simple ASD:0x40871090 %Long 0x301 // TIMG12_MIS; reason=read-only // PER.Set.simple ASD:0x408710E0 %Long 0x29 // TIMG12_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x408710FC %Long 0x11110000 // TIMG12_DESC; reason=read-only // TIMG12_COMMONREGS[%s] PER.Set.simple ASD:0x40871100 %Long 0x0 // TIMG12_CCPD PER.Set.simple ASD:0x40871104 %Long 0x0 // TIMG12_ODIS PER.Set.simple ASD:0x40871108 %Long 0x1 // TIMG12_CCLKCTL PER.Set.simple ASD:0x40871114 %Long 0x0 // TIMG12_CTTRIGCTL // TIMG12_COUNTERREGS[%s] PER.Set.simple ASD:0x40871800 %Long 0xF4CB3E // TIMG12_CTR PER.Set.simple ASD:0x40871804 %Long 0x20000023 // TIMG12_CTRCTL PER.Set.simple ASD:0x40871808 %Long 0xFFFFFFFF // TIMG12_LOAD PER.Set.simple ASD:0x40871810 %Long 0x297600 // TIMG12_CC_01[0] PER.Set.simple ASD:0x40871814 %Long 0x0 // TIMG12_CC_01[1] PER.Set.simple ASD:0x40871830 %Long 0x0 // TIMG12_CCCTL_01[0] PER.Set.simple ASD:0x40871834 %Long 0x0 // TIMG12_CCCTL_01[1] PER.Set.simple ASD:0x40871850 %Long 0x0 // TIMG12_OCTL_01[0] PER.Set.simple ASD:0x40871854 %Long 0x0 // TIMG12_OCTL_01[1] PER.Set.simple ASD:0x40871870 %Long 0x0 // TIMG12_CCACT_01[0] PER.Set.simple ASD:0x40871874 %Long 0x0 // TIMG12_CCACT_01[1] PER.Set.simple ASD:0x40871880 %Long 0x0 // TIMG12_IFCTL_01[0] PER.Set.simple ASD:0x40871884 %Long 0x0 // TIMG12_IFCTL_01[1] PER.Set.simple ASD:0x408718B0 %Long 0x0 // TIMG12_TSEL // TIMG7 PER.Set.simple ASD:0x4086A400 %Long 0x0 // TIMG7_FSUB_0 PER.Set.simple ASD:0x4086A404 %Long 0x0 // TIMG7_FSUB_1 PER.Set.simple ASD:0x4086A444 %Long 0x0 // TIMG7_FPUB_0 PER.Set.simple ASD:0x4086A448 %Long 0x0 // TIMG7_FPUB_1 // TIMG7_GPRCM[%s] PER.Set.simple ASD:0x4086A800 %Long 0x1 // TIMG7_PWREN // PER.Set.simple ASD:0x4086A814 %Long 0x10000 // TIMG7_STAT; reason=read-only PER.Set.simple ASD:0x4086B000 %Long 0x0 // TIMG7_CLKDIV PER.Set.simple ASD:0x4086B008 %Long 0x2 // TIMG7_CLKSEL PER.Set.simple ASD:0x4086B018 %Long 0x3 // TIMG7_PDBGCTL // TIMG7_INT_EVENT[0] // PER.Set.simple ASD:0x4086B020 %Long 0x0 // TIMG7_IIDX; reason=read-only PER.Set.simple ASD:0x4086B028 %Long 0x0 // TIMG7_IMASK // PER.Set.simple ASD:0x4086B030 %Long 0x0 // TIMG7_RIS; reason=read-only // PER.Set.simple ASD:0x4086B038 %Long 0x0 // TIMG7_MIS; reason=read-only // TIMG7_INT_EVENT[1] // PER.Set.simple ASD:0x4086B04C %Long 0x0 // TIMG7_IIDX; reason=read-only PER.Set.simple ASD:0x4086B054 %Long 0x0 // TIMG7_IMASK // PER.Set.simple ASD:0x4086B05C %Long 0x0 // TIMG7_RIS; reason=read-only // PER.Set.simple ASD:0x4086B064 %Long 0x0 // TIMG7_MIS; reason=read-only // TIMG7_INT_EVENT[2] // PER.Set.simple ASD:0x4086B078 %Long 0x0 // TIMG7_IIDX; reason=read-only PER.Set.simple ASD:0x4086B080 %Long 0x0 // TIMG7_IMASK // PER.Set.simple ASD:0x4086B088 %Long 0x0 // TIMG7_RIS; reason=read-only // PER.Set.simple ASD:0x4086B090 %Long 0x0 // TIMG7_MIS; reason=read-only // PER.Set.simple ASD:0x4086B0E0 %Long 0x29 // TIMG7_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x4086B0FC %Long 0x11110000 // TIMG7_DESC; reason=read-only // TIMG7_COMMONREGS[%s] PER.Set.simple ASD:0x4086B100 %Long 0x0 // TIMG7_CCPD PER.Set.simple ASD:0x4086B104 %Long 0x0 // TIMG7_ODIS PER.Set.simple ASD:0x4086B108 %Long 0x1 // TIMG7_CCLKCTL PER.Set.simple ASD:0x4086B10C %Long 0x0 // TIMG7_CPS // PER.Set.simple ASD:0x4086B110 %Long 0x0 // TIMG7_CPSV; reason=read-only PER.Set.simple ASD:0x4086B114 %Long 0x0 // TIMG7_CTTRIGCTL PER.Set.simple ASD:0x4086B124 %Long 0x1 // TIMG7_GCTL // TIMG7_COUNTERREGS[%s] PER.Set.simple ASD:0x4086B800 %Long 0x0 // TIMG7_CTR PER.Set.simple ASD:0x4086B804 %Long 0xFF80 // TIMG7_CTRCTL PER.Set.simple ASD:0x4086B808 %Long 0x0 // TIMG7_LOAD PER.Set.simple ASD:0x4086B810 %Long 0x0 // TIMG7_CC_01[0] PER.Set.simple ASD:0x4086B814 %Long 0x0 // TIMG7_CC_01[1] PER.Set.simple ASD:0x4086B830 %Long 0x0 // TIMG7_CCCTL_01[0] PER.Set.simple ASD:0x4086B834 %Long 0x0 // TIMG7_CCCTL_01[1] PER.Set.simple ASD:0x4086B850 %Long 0x0 // TIMG7_OCTL_01[0] PER.Set.simple ASD:0x4086B854 %Long 0x0 // TIMG7_OCTL_01[1] PER.Set.simple ASD:0x4086B870 %Long 0x0 // TIMG7_CCACT_01[0] PER.Set.simple ASD:0x4086B874 %Long 0x0 // TIMG7_CCACT_01[1] PER.Set.simple ASD:0x4086B880 %Long 0x0 // TIMG7_IFCTL_01[0] PER.Set.simple ASD:0x4086B884 %Long 0x0 // TIMG7_IFCTL_01[1] PER.Set.simple ASD:0x4086B8B0 %Long 0x0 // TIMG7_TSEL // TIMG6 PER.Set.simple ASD:0x40868400 %Long 0x0 // TIMG6_FSUB_0 PER.Set.simple ASD:0x40868404 %Long 0x0 // TIMG6_FSUB_1 PER.Set.simple ASD:0x40868444 %Long 0x0 // TIMG6_FPUB_0 PER.Set.simple ASD:0x40868448 %Long 0x0 // TIMG6_FPUB_1 // TIMG6_GPRCM[%s] PER.Set.simple ASD:0x40868800 %Long 0x1 // TIMG6_PWREN // PER.Set.simple ASD:0x40868814 %Long 0x10000 // TIMG6_STAT; reason=read-only PER.Set.simple ASD:0x40869000 %Long 0x0 // TIMG6_CLKDIV PER.Set.simple ASD:0x40869008 %Long 0x2 // TIMG6_CLKSEL PER.Set.simple ASD:0x40869018 %Long 0x3 // TIMG6_PDBGCTL // TIMG6_INT_EVENT[0] // PER.Set.simple ASD:0x40869020 %Long 0x0 // TIMG6_IIDX; reason=read-only PER.Set.simple ASD:0x40869028 %Long 0x0 // TIMG6_IMASK // PER.Set.simple ASD:0x40869030 %Long 0x0 // TIMG6_RIS; reason=read-only // PER.Set.simple ASD:0x40869038 %Long 0x0 // TIMG6_MIS; reason=read-only // TIMG6_INT_EVENT[1] // PER.Set.simple ASD:0x4086904C %Long 0x0 // TIMG6_IIDX; reason=read-only PER.Set.simple ASD:0x40869054 %Long 0x0 // TIMG6_IMASK // PER.Set.simple ASD:0x4086905C %Long 0x0 // TIMG6_RIS; reason=read-only // PER.Set.simple ASD:0x40869064 %Long 0x0 // TIMG6_MIS; reason=read-only // TIMG6_INT_EVENT[2] // PER.Set.simple ASD:0x40869078 %Long 0x0 // TIMG6_IIDX; reason=read-only PER.Set.simple ASD:0x40869080 %Long 0x0 // TIMG6_IMASK // PER.Set.simple ASD:0x40869088 %Long 0x0 // TIMG6_RIS; reason=read-only // PER.Set.simple ASD:0x40869090 %Long 0x0 // TIMG6_MIS; reason=read-only // PER.Set.simple ASD:0x408690E0 %Long 0x29 // TIMG6_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x408690FC %Long 0x11110000 // TIMG6_DESC; reason=read-only // TIMG6_COMMONREGS[%s] PER.Set.simple ASD:0x40869100 %Long 0x0 // TIMG6_CCPD PER.Set.simple ASD:0x40869104 %Long 0x0 // TIMG6_ODIS PER.Set.simple ASD:0x40869108 %Long 0x1 // TIMG6_CCLKCTL PER.Set.simple ASD:0x4086910C %Long 0x0 // TIMG6_CPS // PER.Set.simple ASD:0x40869110 %Long 0x0 // TIMG6_CPSV; reason=read-only PER.Set.simple ASD:0x40869114 %Long 0x0 // TIMG6_CTTRIGCTL PER.Set.simple ASD:0x40869124 %Long 0x1 // TIMG6_GCTL // TIMG6_COUNTERREGS[%s] PER.Set.simple ASD:0x40869800 %Long 0x0 // TIMG6_CTR PER.Set.simple ASD:0x40869804 %Long 0xFF80 // TIMG6_CTRCTL PER.Set.simple ASD:0x40869808 %Long 0x0 // TIMG6_LOAD PER.Set.simple ASD:0x40869810 %Long 0x0 // TIMG6_CC_01[0] PER.Set.simple ASD:0x40869814 %Long 0x0 // TIMG6_CC_01[1] PER.Set.simple ASD:0x40869830 %Long 0x0 // TIMG6_CCCTL_01[0] PER.Set.simple ASD:0x40869834 %Long 0x0 // TIMG6_CCCTL_01[1] PER.Set.simple ASD:0x40869850 %Long 0x0 // TIMG6_OCTL_01[0] PER.Set.simple ASD:0x40869854 %Long 0x0 // TIMG6_OCTL_01[1] PER.Set.simple ASD:0x40869870 %Long 0x0 // TIMG6_CCACT_01[0] PER.Set.simple ASD:0x40869874 %Long 0x0 // TIMG6_CCACT_01[1] PER.Set.simple ASD:0x40869880 %Long 0x0 // TIMG6_IFCTL_01[0] PER.Set.simple ASD:0x40869884 %Long 0x0 // TIMG6_IFCTL_01[1] PER.Set.simple ASD:0x408698B0 %Long 0x0 // TIMG6_TSEL // TIMG0 PER.Set.simple ASD:0x40084400 %Long 0x0 // TIMG0_FSUB_0 PER.Set.simple ASD:0x40084404 %Long 0x0 // TIMG0_FSUB_1 PER.Set.simple ASD:0x40084444 %Long 0x0 // TIMG0_FPUB_0 PER.Set.simple ASD:0x40084448 %Long 0x0 // TIMG0_FPUB_1 // TIMG0_GPRCM[%s] PER.Set.simple ASD:0x40084800 %Long 0x1 // TIMG0_PWREN // PER.Set.simple ASD:0x40084814 %Long 0x10000 // TIMG0_STAT; reason=read-only PER.Set.simple ASD:0x40085000 %Long 0x0 // TIMG0_CLKDIV PER.Set.simple ASD:0x40085008 %Long 0x2 // TIMG0_CLKSEL PER.Set.simple ASD:0x40085018 %Long 0x3 // TIMG0_PDBGCTL // TIMG0_INT_EVENT[0] // PER.Set.simple ASD:0x40085020 %Long 0x0 // TIMG0_IIDX; reason=read-only PER.Set.simple ASD:0x40085028 %Long 0x0 // TIMG0_IMASK // PER.Set.simple ASD:0x40085030 %Long 0x0 // TIMG0_RIS; reason=read-only // PER.Set.simple ASD:0x40085038 %Long 0x0 // TIMG0_MIS; reason=read-only // TIMG0_INT_EVENT[1] // PER.Set.simple ASD:0x4008504C %Long 0x0 // TIMG0_IIDX; reason=read-only PER.Set.simple ASD:0x40085054 %Long 0x0 // TIMG0_IMASK // PER.Set.simple ASD:0x4008505C %Long 0x0 // TIMG0_RIS; reason=read-only // PER.Set.simple ASD:0x40085064 %Long 0x0 // TIMG0_MIS; reason=read-only // TIMG0_INT_EVENT[2] // PER.Set.simple ASD:0x40085078 %Long 0x0 // TIMG0_IIDX; reason=read-only PER.Set.simple ASD:0x40085080 %Long 0x0 // TIMG0_IMASK // PER.Set.simple ASD:0x40085088 %Long 0x0 // TIMG0_RIS; reason=read-only // PER.Set.simple ASD:0x40085090 %Long 0x0 // TIMG0_MIS; reason=read-only // PER.Set.simple ASD:0x400850E0 %Long 0x29 // TIMG0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400850FC %Long 0x11110000 // TIMG0_DESC; reason=read-only // TIMG0_COMMONREGS[%s] PER.Set.simple ASD:0x40085100 %Long 0x0 // TIMG0_CCPD PER.Set.simple ASD:0x40085104 %Long 0x0 // TIMG0_ODIS PER.Set.simple ASD:0x40085108 %Long 0x1 // TIMG0_CCLKCTL PER.Set.simple ASD:0x4008510C %Long 0x0 // TIMG0_CPS // PER.Set.simple ASD:0x40085110 %Long 0x0 // TIMG0_CPSV; reason=read-only PER.Set.simple ASD:0x40085114 %Long 0x0 // TIMG0_CTTRIGCTL // TIMG0_COUNTERREGS[%s] PER.Set.simple ASD:0x40085800 %Long 0x0 // TIMG0_CTR PER.Set.simple ASD:0x40085804 %Long 0xFF80 // TIMG0_CTRCTL PER.Set.simple ASD:0x40085808 %Long 0x0 // TIMG0_LOAD PER.Set.simple ASD:0x40085810 %Long 0x0 // TIMG0_CC_01[0] PER.Set.simple ASD:0x40085814 %Long 0x0 // TIMG0_CC_01[1] PER.Set.simple ASD:0x40085830 %Long 0x0 // TIMG0_CCCTL_01[0] PER.Set.simple ASD:0x40085834 %Long 0x0 // TIMG0_CCCTL_01[1] PER.Set.simple ASD:0x40085850 %Long 0x0 // TIMG0_OCTL_01[0] PER.Set.simple ASD:0x40085854 %Long 0x0 // TIMG0_OCTL_01[1] PER.Set.simple ASD:0x40085870 %Long 0x0 // TIMG0_CCACT_01[0] PER.Set.simple ASD:0x40085874 %Long 0x0 // TIMG0_CCACT_01[1] PER.Set.simple ASD:0x40085880 %Long 0x0 // TIMG0_IFCTL_01[0] PER.Set.simple ASD:0x40085884 %Long 0x0 // TIMG0_IFCTL_01[1] PER.Set.simple ASD:0x400858B0 %Long 0x0 // TIMG0_TSEL // TIMG8 PER.Set.simple ASD:0x40090400 %Long 0x0 // TIMG8_FSUB_0 PER.Set.simple ASD:0x40090404 %Long 0x0 // TIMG8_FSUB_1 PER.Set.simple ASD:0x40090444 %Long 0x0 // TIMG8_FPUB_0 PER.Set.simple ASD:0x40090448 %Long 0x0 // TIMG8_FPUB_1 // TIMG8_GPRCM[%s] PER.Set.simple ASD:0x40090800 %Long 0x1 // TIMG8_PWREN // PER.Set.simple ASD:0x40090814 %Long 0x10000 // TIMG8_STAT; reason=read-only PER.Set.simple ASD:0x40091000 %Long 0x0 // TIMG8_CLKDIV PER.Set.simple ASD:0x40091008 %Long 0x2 // TIMG8_CLKSEL PER.Set.simple ASD:0x40091018 %Long 0x3 // TIMG8_PDBGCTL // TIMG8_INT_EVENT[0] // PER.Set.simple ASD:0x40091020 %Long 0x0 // TIMG8_IIDX; reason=read-only PER.Set.simple ASD:0x40091028 %Long 0x0 // TIMG8_IMASK // PER.Set.simple ASD:0x40091030 %Long 0x0 // TIMG8_RIS; reason=read-only // PER.Set.simple ASD:0x40091038 %Long 0x0 // TIMG8_MIS; reason=read-only // TIMG8_INT_EVENT[1] // PER.Set.simple ASD:0x4009104C %Long 0x0 // TIMG8_IIDX; reason=read-only PER.Set.simple ASD:0x40091054 %Long 0x0 // TIMG8_IMASK // PER.Set.simple ASD:0x4009105C %Long 0x0 // TIMG8_RIS; reason=read-only // PER.Set.simple ASD:0x40091064 %Long 0x0 // TIMG8_MIS; reason=read-only // TIMG8_INT_EVENT[2] // PER.Set.simple ASD:0x40091078 %Long 0x0 // TIMG8_IIDX; reason=read-only PER.Set.simple ASD:0x40091080 %Long 0x0 // TIMG8_IMASK // PER.Set.simple ASD:0x40091088 %Long 0x0 // TIMG8_RIS; reason=read-only // PER.Set.simple ASD:0x40091090 %Long 0x0 // TIMG8_MIS; reason=read-only // PER.Set.simple ASD:0x400910E0 %Long 0x29 // TIMG8_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400910FC %Long 0x11110000 // TIMG8_DESC; reason=read-only // TIMG8_COMMONREGS[%s] PER.Set.simple ASD:0x40091100 %Long 0x0 // TIMG8_CCPD PER.Set.simple ASD:0x40091104 %Long 0x0 // TIMG8_ODIS PER.Set.simple ASD:0x40091108 %Long 0x1 // TIMG8_CCLKCTL PER.Set.simple ASD:0x4009110C %Long 0x0 // TIMG8_CPS // PER.Set.simple ASD:0x40091110 %Long 0x0 // TIMG8_CPSV; reason=read-only PER.Set.simple ASD:0x40091114 %Long 0x0 // TIMG8_CTTRIGCTL // TIMG8_COUNTERREGS[%s] PER.Set.simple ASD:0x40091800 %Long 0x0 // TIMG8_CTR PER.Set.simple ASD:0x40091804 %Long 0xFF80 // TIMG8_CTRCTL PER.Set.simple ASD:0x40091808 %Long 0x0 // TIMG8_LOAD PER.Set.simple ASD:0x40091810 %Long 0x0 // TIMG8_CC_01[0] PER.Set.simple ASD:0x40091814 %Long 0x0 // TIMG8_CC_01[1] PER.Set.simple ASD:0x40091830 %Long 0x0 // TIMG8_CCCTL_01[0] PER.Set.simple ASD:0x40091834 %Long 0x0 // TIMG8_CCCTL_01[1] PER.Set.simple ASD:0x40091850 %Long 0x0 // TIMG8_OCTL_01[0] PER.Set.simple ASD:0x40091854 %Long 0x0 // TIMG8_OCTL_01[1] PER.Set.simple ASD:0x40091870 %Long 0x0 // TIMG8_CCACT_01[0] PER.Set.simple ASD:0x40091874 %Long 0x0 // TIMG8_CCACT_01[1] PER.Set.simple ASD:0x40091880 %Long 0x0 // TIMG8_IFCTL_01[0] PER.Set.simple ASD:0x40091884 %Long 0x0 // TIMG8_IFCTL_01[1] PER.Set.simple ASD:0x400918B0 %Long 0x0 // TIMG8_TSEL // PER.Set.simple ASD:0x400918BC %Long 0x0 // TIMG8_QDIR; reason=read-only // TIMG9 PER.Set.simple ASD:0x40092400 %Long 0x0 // TIMG9_FSUB_0 PER.Set.simple ASD:0x40092404 %Long 0x0 // TIMG9_FSUB_1 PER.Set.simple ASD:0x40092444 %Long 0x0 // TIMG9_FPUB_0 PER.Set.simple ASD:0x40092448 %Long 0x0 // TIMG9_FPUB_1 // TIMG9_GPRCM[%s] PER.Set.simple ASD:0x40092800 %Long 0x1 // TIMG9_PWREN // PER.Set.simple ASD:0x40092814 %Long 0x10000 // TIMG9_STAT; reason=read-only PER.Set.simple ASD:0x40093000 %Long 0x0 // TIMG9_CLKDIV PER.Set.simple ASD:0x40093008 %Long 0x2 // TIMG9_CLKSEL PER.Set.simple ASD:0x40093018 %Long 0x3 // TIMG9_PDBGCTL // TIMG9_INT_EVENT[0] // PER.Set.simple ASD:0x40093020 %Long 0x0 // TIMG9_IIDX; reason=read-only PER.Set.simple ASD:0x40093028 %Long 0x0 // TIMG9_IMASK // PER.Set.simple ASD:0x40093030 %Long 0x0 // TIMG9_RIS; reason=read-only // PER.Set.simple ASD:0x40093038 %Long 0x0 // TIMG9_MIS; reason=read-only // TIMG9_INT_EVENT[1] // PER.Set.simple ASD:0x4009304C %Long 0x0 // TIMG9_IIDX; reason=read-only PER.Set.simple ASD:0x40093054 %Long 0x0 // TIMG9_IMASK // PER.Set.simple ASD:0x4009305C %Long 0x0 // TIMG9_RIS; reason=read-only // PER.Set.simple ASD:0x40093064 %Long 0x0 // TIMG9_MIS; reason=read-only // TIMG9_INT_EVENT[2] // PER.Set.simple ASD:0x40093078 %Long 0x0 // TIMG9_IIDX; reason=read-only PER.Set.simple ASD:0x40093080 %Long 0x0 // TIMG9_IMASK // PER.Set.simple ASD:0x40093088 %Long 0x0 // TIMG9_RIS; reason=read-only // PER.Set.simple ASD:0x40093090 %Long 0x0 // TIMG9_MIS; reason=read-only // PER.Set.simple ASD:0x400930E0 %Long 0x29 // TIMG9_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400930FC %Long 0x11110000 // TIMG9_DESC; reason=read-only // TIMG9_COMMONREGS[%s] PER.Set.simple ASD:0x40093100 %Long 0x0 // TIMG9_CCPD PER.Set.simple ASD:0x40093104 %Long 0x0 // TIMG9_ODIS PER.Set.simple ASD:0x40093108 %Long 0x1 // TIMG9_CCLKCTL PER.Set.simple ASD:0x4009310C %Long 0x0 // TIMG9_CPS // PER.Set.simple ASD:0x40093110 %Long 0x0 // TIMG9_CPSV; reason=read-only PER.Set.simple ASD:0x40093114 %Long 0x0 // TIMG9_CTTRIGCTL // TIMG9_COUNTERREGS[%s] PER.Set.simple ASD:0x40093800 %Long 0x0 // TIMG9_CTR PER.Set.simple ASD:0x40093804 %Long 0xFF80 // TIMG9_CTRCTL PER.Set.simple ASD:0x40093808 %Long 0x0 // TIMG9_LOAD PER.Set.simple ASD:0x40093810 %Long 0x0 // TIMG9_CC_01[0] PER.Set.simple ASD:0x40093814 %Long 0x0 // TIMG9_CC_01[1] PER.Set.simple ASD:0x40093830 %Long 0x0 // TIMG9_CCCTL_01[0] PER.Set.simple ASD:0x40093834 %Long 0x0 // TIMG9_CCCTL_01[1] PER.Set.simple ASD:0x40093850 %Long 0x0 // TIMG9_OCTL_01[0] PER.Set.simple ASD:0x40093854 %Long 0x0 // TIMG9_OCTL_01[1] PER.Set.simple ASD:0x40093870 %Long 0x0 // TIMG9_CCACT_01[0] PER.Set.simple ASD:0x40093874 %Long 0x0 // TIMG9_CCACT_01[1] PER.Set.simple ASD:0x40093880 %Long 0x0 // TIMG9_IFCTL_01[0] PER.Set.simple ASD:0x40093884 %Long 0x0 // TIMG9_IFCTL_01[1] PER.Set.simple ASD:0x400938B0 %Long 0x0 // TIMG9_TSEL // PER.Set.simple ASD:0x400938BC %Long 0x0 // TIMG9_QDIR; reason=read-only // TIMG14 PER.Set.simple ASD:0x40096400 %Long 0x0 // TIMG14_FSUB_0 PER.Set.simple ASD:0x40096404 %Long 0x0 // TIMG14_FSUB_1 PER.Set.simple ASD:0x40096444 %Long 0x0 // TIMG14_FPUB_0 PER.Set.simple ASD:0x40096448 %Long 0x0 // TIMG14_FPUB_1 // TIMG14_GPRCM[%s] PER.Set.simple ASD:0x40096800 %Long 0x1 // TIMG14_PWREN // PER.Set.simple ASD:0x40096814 %Long 0x10000 // TIMG14_STAT; reason=read-only PER.Set.simple ASD:0x40097000 %Long 0x0 // TIMG14_CLKDIV PER.Set.simple ASD:0x40097008 %Long 0x2 // TIMG14_CLKSEL PER.Set.simple ASD:0x40097018 %Long 0x3 // TIMG14_PDBGCTL // TIMG14_INT_EVENT[0] // PER.Set.simple ASD:0x40097020 %Long 0x0 // TIMG14_IIDX; reason=read-only PER.Set.simple ASD:0x40097028 %Long 0x0 // TIMG14_IMASK // PER.Set.simple ASD:0x40097030 %Long 0x0 // TIMG14_RIS; reason=read-only // PER.Set.simple ASD:0x40097038 %Long 0x0 // TIMG14_MIS; reason=read-only // TIMG14_INT_EVENT[1] // PER.Set.simple ASD:0x4009704C %Long 0x0 // TIMG14_IIDX; reason=read-only PER.Set.simple ASD:0x40097054 %Long 0x0 // TIMG14_IMASK // PER.Set.simple ASD:0x4009705C %Long 0x0 // TIMG14_RIS; reason=read-only // PER.Set.simple ASD:0x40097064 %Long 0x0 // TIMG14_MIS; reason=read-only // TIMG14_INT_EVENT[2] // PER.Set.simple ASD:0x40097078 %Long 0x0 // TIMG14_IIDX; reason=read-only PER.Set.simple ASD:0x40097080 %Long 0x0 // TIMG14_IMASK // PER.Set.simple ASD:0x40097088 %Long 0x0 // TIMG14_RIS; reason=read-only // PER.Set.simple ASD:0x40097090 %Long 0x0 // TIMG14_MIS; reason=read-only // PER.Set.simple ASD:0x400970E0 %Long 0x29 // TIMG14_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400970FC %Long 0x11110000 // TIMG14_DESC; reason=read-only // TIMG14_COMMONREGS[%s] PER.Set.simple ASD:0x40097100 %Long 0x0 // TIMG14_CCPD PER.Set.simple ASD:0x40097104 %Long 0x0 // TIMG14_ODIS PER.Set.simple ASD:0x40097108 %Long 0x1 // TIMG14_CCLKCTL PER.Set.simple ASD:0x4009710C %Long 0x0 // TIMG14_CPS // PER.Set.simple ASD:0x40097110 %Long 0x0 // TIMG14_CPSV; reason=read-only PER.Set.simple ASD:0x40097114 %Long 0x0 // TIMG14_CTTRIGCTL // TIMG14_COUNTERREGS[%s] PER.Set.simple ASD:0x40097800 %Long 0x0 // TIMG14_CTR PER.Set.simple ASD:0x40097804 %Long 0xFF80 // TIMG14_CTRCTL PER.Set.simple ASD:0x40097808 %Long 0x0 // TIMG14_LOAD PER.Set.simple ASD:0x40097810 %Long 0x0 // TIMG14_CC_01[0] PER.Set.simple ASD:0x40097814 %Long 0x0 // TIMG14_CC_01[1] PER.Set.simple ASD:0x40097818 %Long 0x0 // TIMG14_CC_23[0] PER.Set.simple ASD:0x4009781C %Long 0x0 // TIMG14_CC_23[1] PER.Set.simple ASD:0x40097830 %Long 0x0 // TIMG14_CCCTL_01[0] PER.Set.simple ASD:0x40097834 %Long 0x0 // TIMG14_CCCTL_01[1] PER.Set.simple ASD:0x40097838 %Long 0x0 // TIMG14_CCCTL_23[0] PER.Set.simple ASD:0x4009783C %Long 0x0 // TIMG14_CCCTL_23[1] PER.Set.simple ASD:0x40097850 %Long 0x0 // TIMG14_OCTL_01[0] PER.Set.simple ASD:0x40097854 %Long 0x0 // TIMG14_OCTL_01[1] PER.Set.simple ASD:0x40097858 %Long 0x0 // TIMG14_OCTL_23[0] PER.Set.simple ASD:0x4009785C %Long 0x0 // TIMG14_OCTL_23[1] PER.Set.simple ASD:0x40097870 %Long 0x0 // TIMG14_CCACT_01[0] PER.Set.simple ASD:0x40097874 %Long 0x0 // TIMG14_CCACT_01[1] PER.Set.simple ASD:0x40097878 %Long 0x0 // TIMG14_CCACT_23[0] PER.Set.simple ASD:0x4009787C %Long 0x0 // TIMG14_CCACT_23[1] PER.Set.simple ASD:0x40097880 %Long 0x0 // TIMG14_IFCTL_01[0] PER.Set.simple ASD:0x40097884 %Long 0x0 // TIMG14_IFCTL_01[1] PER.Set.simple ASD:0x40097888 %Long 0x0 // TIMG14_IFCTL_23[0] PER.Set.simple ASD:0x4009788C %Long 0x0 // TIMG14_IFCTL_23[1] PER.Set.simple ASD:0x400978B0 %Long 0x0 // TIMG14_TSEL // TRNG (True Random Number Generator) // TRNG (PERIPHERALREGION) // TRNG_GPRCM[%s] PER.Set.simple ASD:0x40444800 %Long 0x0 // TRNG_PWREN // PER.Set.simple ASD:0x40444814 %Long 0x10000 // TRNG_GPRCM_STAT; reason=read-only // PER.Set.simple ASD:0x40445020 %Long 0x0 // TRNG_IIDX; reason=read-only PER.Set.simple ASD:0x40445028 %Long 0x0 // TRNG_IMASK // PER.Set.simple ASD:0x40445030 %Long 0x0 // TRNG_RIS; reason=read-only // PER.Set.simple ASD:0x40445038 %Long 0x0 // TRNG_MIS; reason=read-only // PER.Set.simple ASD:0x404450FC %Long 0x0 // TRNG_DESC; reason=read-only PER.Set.simple ASD:0x40445100 %Long 0x0 // TRNG_CTL // PER.Set.simple ASD:0x40445104 %Long 0x0 // TRNG_STAT; reason=read-only // PER.Set.simple ASD:0x40445108 %Long 0x0 // TRNG_DATA_CAPTURE; reason=read-only // PER.Set.simple ASD:0x4044510C %Long 0x0 // TRNG_TEST_RESULTS; reason=read-only PER.Set.simple ASD:0x40445110 %Long 0x0 // TRNG_CLKDIVIDE // UART (Universal Asynchronouns Receiver Transmitter) // UART0 // UART0_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40109080 %Long 0x0 // UART0_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40109088 %Long 0x0 // UART0_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40109090 %Long 0x800 // UART0_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40109098 %Long 0x0 // UART0_DMA_TRIG_TX_MIS; reason=read-only // UART0_GPRCM[%s] PER.Set.simple ASD:0x40108800 %Long 0x1 // UART0_PWREN PER.Set.simple ASD:0x40108808 %Long 0x0 // UART0_CLKCFG // PER.Set.simple ASD:0x40108814 %Long 0x10000 // UART0_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40109000 %Long 0x0 // UART0_CLKDIV PER.Set.simple ASD:0x40109008 %Long 0x8 // UART0_CLKSEL PER.Set.simple ASD:0x40109018 %Long 0x3 // UART0_PDBGCTL // UART0_CPU_INT[%s] // PER.Set.simple ASD:0x40109020 %Long 0x0 // UART0_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40109028 %Long 0x400 // UART0_CPU_INT_IMASK // PER.Set.simple ASD:0x40109030 %Long 0x4820 // UART0_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40109038 %Long 0x0 // UART0_CPU_INT_MIS; reason=read-only // UART0_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40109050 %Long 0x0 // UART0_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40109058 %Long 0x0 // UART0_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40109060 %Long 0x0 // UART0_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40109068 %Long 0x0 // UART0_DMA_TRIG_RX_MIS; reason=read-only // PER.Set.simple ASD:0x401090E0 %Long 0x29 // UART0_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40109100 %Long 0x39 // UART0_CTL0 PER.Set.simple ASD:0x40109104 %Long 0x30 // UART0_LCRH // PER.Set.simple ASD:0x40109108 %Long 0x44 // UART0_STAT; reason=read-only PER.Set.simple ASD:0x4010910C %Long 0x72 // UART0_IFLS PER.Set.simple ASD:0x40109110 %Long 0x11 // UART0_IBRD PER.Set.simple ASD:0x40109114 %Long 0x17 // UART0_FBRD PER.Set.simple ASD:0x40109118 %Long 0x0 // UART0_GFCTL PER.Set.simple ASD:0x40109120 %Long 0x0 // UART0_TXDATA // PER.Set.simple ASD:0x40109124 %Long 0x0 // UART0_RXDATA; reason=read-only PER.Set.simple ASD:0x40109130 %Long 0x0 // UART0_LINCNT PER.Set.simple ASD:0x40109134 %Long 0x0 // UART0_LINCTL PER.Set.simple ASD:0x40109138 %Long 0x0 // UART0_LINC0 PER.Set.simple ASD:0x4010913C %Long 0x0 // UART0_LINC1 PER.Set.simple ASD:0x40109140 %Long 0x0 // UART0_IRCTL PER.Set.simple ASD:0x40109148 %Long 0xFF // UART0_AMASK PER.Set.simple ASD:0x4010914C %Long 0x0 // UART0_ADDR PER.Set.simple ASD:0x40109160 %Long 0x0 // UART0_CLKDIV2 // UART1 // UART1_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40101050 %Long 0x0 // UART1_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40101058 %Long 0x0 // UART1_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40101060 %Long 0x0 // UART1_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40101068 %Long 0x0 // UART1_DMA_TRIG_RX_MIS; reason=read-only // UART1_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40101080 %Long 0x0 // UART1_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40101088 %Long 0x0 // UART1_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40101090 %Long 0x0 // UART1_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40101098 %Long 0x0 // UART1_DMA_TRIG_TX_MIS; reason=read-only // UART1_GPRCM[%s] PER.Set.simple ASD:0x40100800 %Long 0x0 // UART1_PWREN PER.Set.simple ASD:0x40100808 %Long 0x0 // UART1_CLKCFG // PER.Set.simple ASD:0x40100814 %Long 0x10000 // UART1_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40101000 %Long 0x0 // UART1_CLKDIV PER.Set.simple ASD:0x40101008 %Long 0x0 // UART1_CLKSEL PER.Set.simple ASD:0x40101018 %Long 0x0 // UART1_PDBGCTL // UART1_CPU_INT[%s] // PER.Set.simple ASD:0x40101020 %Long 0x0 // UART1_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40101028 %Long 0x0 // UART1_CPU_INT_IMASK // PER.Set.simple ASD:0x40101030 %Long 0x0 // UART1_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40101038 %Long 0x0 // UART1_CPU_INT_MIS; reason=read-only // PER.Set.simple ASD:0x401010E0 %Long 0x0 // UART1_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40101100 %Long 0x0 // UART1_CTL0 PER.Set.simple ASD:0x40101104 %Long 0x0 // UART1_LCRH // PER.Set.simple ASD:0x40101108 %Long 0x0 // UART1_STAT; reason=read-only PER.Set.simple ASD:0x4010110C %Long 0x0 // UART1_IFLS PER.Set.simple ASD:0x40101110 %Long 0x0 // UART1_IBRD PER.Set.simple ASD:0x40101114 %Long 0x0 // UART1_FBRD PER.Set.simple ASD:0x40101118 %Long 0x0 // UART1_GFCTL PER.Set.simple ASD:0x40101120 %Long 0x0 // UART1_TXDATA // PER.Set.simple ASD:0x40101124 %Long 0x0 // UART1_RXDATA; reason=read-only PER.Set.simple ASD:0x40101148 %Long 0x0 // UART1_AMASK PER.Set.simple ASD:0x4010114C %Long 0x0 // UART1_ADDR // UART3 // UART3_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40501050 %Long 0x0 // UART3_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40501058 %Long 0x0 // UART3_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40501060 %Long 0x0 // UART3_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40501068 %Long 0x0 // UART3_DMA_TRIG_RX_MIS; reason=read-only // UART3_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40501080 %Long 0x0 // UART3_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40501088 %Long 0x0 // UART3_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40501090 %Long 0x0 // UART3_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40501098 %Long 0x0 // UART3_DMA_TRIG_TX_MIS; reason=read-only // UART3_GPRCM[%s] PER.Set.simple ASD:0x40500800 %Long 0x0 // UART3_PWREN PER.Set.simple ASD:0x40500808 %Long 0x0 // UART3_CLKCFG // PER.Set.simple ASD:0x40500814 %Long 0x10000 // UART3_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40501000 %Long 0x0 // UART3_CLKDIV PER.Set.simple ASD:0x40501008 %Long 0x0 // UART3_CLKSEL PER.Set.simple ASD:0x40501018 %Long 0x0 // UART3_PDBGCTL // UART3_CPU_INT[%s] // PER.Set.simple ASD:0x40501020 %Long 0x0 // UART3_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40501028 %Long 0x0 // UART3_CPU_INT_IMASK // PER.Set.simple ASD:0x40501030 %Long 0x0 // UART3_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40501038 %Long 0x0 // UART3_CPU_INT_MIS; reason=read-only // PER.Set.simple ASD:0x405010E0 %Long 0x0 // UART3_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40501100 %Long 0x0 // UART3_CTL0 PER.Set.simple ASD:0x40501104 %Long 0x0 // UART3_LCRH // PER.Set.simple ASD:0x40501108 %Long 0x0 // UART3_STAT; reason=read-only PER.Set.simple ASD:0x4050110C %Long 0x0 // UART3_IFLS PER.Set.simple ASD:0x40501110 %Long 0x0 // UART3_IBRD PER.Set.simple ASD:0x40501114 %Long 0x0 // UART3_FBRD PER.Set.simple ASD:0x40501118 %Long 0x0 // UART3_GFCTL PER.Set.simple ASD:0x40501120 %Long 0x0 // UART3_TXDATA // PER.Set.simple ASD:0x40501124 %Long 0x0 // UART3_RXDATA; reason=read-only PER.Set.simple ASD:0x40501148 %Long 0x0 // UART3_AMASK PER.Set.simple ASD:0x4050114C %Long 0x0 // UART3_ADDR // UART7 // UART7_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x4010B080 %Long 0x0 // UART7_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x4010B088 %Long 0x0 // UART7_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x4010B090 %Long 0x0 // UART7_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x4010B098 %Long 0x0 // UART7_DMA_TRIG_TX_MIS; reason=read-only // UART7_GPRCM[%s] PER.Set.simple ASD:0x4010A800 %Long 0x0 // UART7_PWREN PER.Set.simple ASD:0x4010A808 %Long 0x0 // UART7_CLKCFG // PER.Set.simple ASD:0x4010A814 %Long 0x10000 // UART7_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x4010B000 %Long 0x0 // UART7_CLKDIV PER.Set.simple ASD:0x4010B008 %Long 0x0 // UART7_CLKSEL PER.Set.simple ASD:0x4010B018 %Long 0x0 // UART7_PDBGCTL // UART7_CPU_INT[%s] // PER.Set.simple ASD:0x4010B020 %Long 0x0 // UART7_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x4010B028 %Long 0x0 // UART7_CPU_INT_IMASK // PER.Set.simple ASD:0x4010B030 %Long 0x0 // UART7_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x4010B038 %Long 0x0 // UART7_CPU_INT_MIS; reason=read-only // UART7_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x4010B050 %Long 0x0 // UART7_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x4010B058 %Long 0x0 // UART7_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x4010B060 %Long 0x0 // UART7_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x4010B068 %Long 0x0 // UART7_DMA_TRIG_RX_MIS; reason=read-only // PER.Set.simple ASD:0x4010B0E0 %Long 0x0 // UART7_EVT_MODE; reason=read-only PER.Set.simple ASD:0x4010B100 %Long 0x0 // UART7_CTL0 PER.Set.simple ASD:0x4010B104 %Long 0x0 // UART7_LCRH // PER.Set.simple ASD:0x4010B108 %Long 0x0 // UART7_STAT; reason=read-only PER.Set.simple ASD:0x4010B10C %Long 0x0 // UART7_IFLS PER.Set.simple ASD:0x4010B110 %Long 0x0 // UART7_IBRD PER.Set.simple ASD:0x4010B114 %Long 0x0 // UART7_FBRD PER.Set.simple ASD:0x4010B118 %Long 0x0 // UART7_GFCTL PER.Set.simple ASD:0x4010B120 %Long 0x0 // UART7_TXDATA // PER.Set.simple ASD:0x4010B124 %Long 0x0 // UART7_RXDATA; reason=read-only PER.Set.simple ASD:0x4010B130 %Long 0x0 // UART7_LINCNT PER.Set.simple ASD:0x4010B134 %Long 0x0 // UART7_LINCTL PER.Set.simple ASD:0x4010B138 %Long 0x0 // UART7_LINC0 PER.Set.simple ASD:0x4010B13C %Long 0x0 // UART7_LINC1 PER.Set.simple ASD:0x4010B140 %Long 0x0 // UART7_IRCTL PER.Set.simple ASD:0x4010B148 %Long 0x0 // UART7_AMASK PER.Set.simple ASD:0x4010B14C %Long 0x0 // UART7_ADDR PER.Set.simple ASD:0x4010B160 %Long 0x0 // UART7_CLKDIV2 // UART4 // UART4_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40503050 %Long 0x0 // UART4_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40503058 %Long 0x0 // UART4_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40503060 %Long 0x0 // UART4_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40503068 %Long 0x0 // UART4_DMA_TRIG_RX_MIS; reason=read-only // UART4_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40503080 %Long 0x0 // UART4_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40503088 %Long 0x0 // UART4_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40503090 %Long 0x0 // UART4_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40503098 %Long 0x0 // UART4_DMA_TRIG_TX_MIS; reason=read-only // UART4_GPRCM[%s] PER.Set.simple ASD:0x40502800 %Long 0x0 // UART4_PWREN PER.Set.simple ASD:0x40502808 %Long 0x0 // UART4_CLKCFG // PER.Set.simple ASD:0x40502814 %Long 0x10000 // UART4_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40503000 %Long 0x0 // UART4_CLKDIV PER.Set.simple ASD:0x40503008 %Long 0x0 // UART4_CLKSEL PER.Set.simple ASD:0x40503018 %Long 0x0 // UART4_PDBGCTL // UART4_CPU_INT[%s] // PER.Set.simple ASD:0x40503020 %Long 0x0 // UART4_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40503028 %Long 0x0 // UART4_CPU_INT_IMASK // PER.Set.simple ASD:0x40503030 %Long 0x0 // UART4_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40503038 %Long 0x0 // UART4_CPU_INT_MIS; reason=read-only // PER.Set.simple ASD:0x405030E0 %Long 0x0 // UART4_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40503100 %Long 0x0 // UART4_CTL0 PER.Set.simple ASD:0x40503104 %Long 0x0 // UART4_LCRH // PER.Set.simple ASD:0x40503108 %Long 0x0 // UART4_STAT; reason=read-only PER.Set.simple ASD:0x4050310C %Long 0x0 // UART4_IFLS PER.Set.simple ASD:0x40503110 %Long 0x0 // UART4_IBRD PER.Set.simple ASD:0x40503114 %Long 0x0 // UART4_FBRD PER.Set.simple ASD:0x40503118 %Long 0x0 // UART4_GFCTL PER.Set.simple ASD:0x40503120 %Long 0x0 // UART4_TXDATA // PER.Set.simple ASD:0x40503124 %Long 0x0 // UART4_RXDATA; reason=read-only PER.Set.simple ASD:0x40503148 %Long 0x0 // UART4_AMASK PER.Set.simple ASD:0x4050314C %Long 0x0 // UART4_ADDR // UART5 // UART5_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40505050 %Long 0x0 // UART5_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40505058 %Long 0x0 // UART5_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40505060 %Long 0x0 // UART5_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40505068 %Long 0x0 // UART5_DMA_TRIG_RX_MIS; reason=read-only // UART5_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40505080 %Long 0x0 // UART5_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40505088 %Long 0x0 // UART5_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40505090 %Long 0x0 // UART5_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40505098 %Long 0x0 // UART5_DMA_TRIG_TX_MIS; reason=read-only // UART5_GPRCM[%s] PER.Set.simple ASD:0x40504800 %Long 0x0 // UART5_PWREN PER.Set.simple ASD:0x40504808 %Long 0x0 // UART5_CLKCFG // PER.Set.simple ASD:0x40504814 %Long 0x10000 // UART5_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40505000 %Long 0x0 // UART5_CLKDIV PER.Set.simple ASD:0x40505008 %Long 0x0 // UART5_CLKSEL PER.Set.simple ASD:0x40505018 %Long 0x0 // UART5_PDBGCTL // UART5_CPU_INT[%s] // PER.Set.simple ASD:0x40505020 %Long 0x0 // UART5_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40505028 %Long 0x0 // UART5_CPU_INT_IMASK // PER.Set.simple ASD:0x40505030 %Long 0x0 // UART5_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40505038 %Long 0x0 // UART5_CPU_INT_MIS; reason=read-only // PER.Set.simple ASD:0x405050E0 %Long 0x0 // UART5_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40505100 %Long 0x0 // UART5_CTL0 PER.Set.simple ASD:0x40505104 %Long 0x0 // UART5_LCRH // PER.Set.simple ASD:0x40505108 %Long 0x0 // UART5_STAT; reason=read-only PER.Set.simple ASD:0x4050510C %Long 0x0 // UART5_IFLS PER.Set.simple ASD:0x40505110 %Long 0x0 // UART5_IBRD PER.Set.simple ASD:0x40505114 %Long 0x0 // UART5_FBRD PER.Set.simple ASD:0x40505118 %Long 0x0 // UART5_GFCTL PER.Set.simple ASD:0x40505120 %Long 0x0 // UART5_TXDATA // PER.Set.simple ASD:0x40505124 %Long 0x0 // UART5_RXDATA; reason=read-only PER.Set.simple ASD:0x40505148 %Long 0x0 // UART5_AMASK PER.Set.simple ASD:0x4050514C %Long 0x0 // UART5_ADDR // UART6 // UART6_DMA_TRIG_RX[%s] // PER.Set.simple ASD:0x40507050 %Long 0x0 // UART6_DMA_TRIG_RX_IIDX; reason=read-only PER.Set.simple ASD:0x40507058 %Long 0x0 // UART6_DMA_TRIG_RX_IMASK // PER.Set.simple ASD:0x40507060 %Long 0x0 // UART6_DMA_TRIG_RX_RIS; reason=read-only // PER.Set.simple ASD:0x40507068 %Long 0x0 // UART6_DMA_TRIG_RX_MIS; reason=read-only // UART6_DMA_TRIG_TX[%s] // PER.Set.simple ASD:0x40507080 %Long 0x0 // UART6_DMA_TRIG_TX_IIDX; reason=read-only PER.Set.simple ASD:0x40507088 %Long 0x0 // UART6_DMA_TRIG_TX_IMASK // PER.Set.simple ASD:0x40507090 %Long 0x0 // UART6_DMA_TRIG_TX_RIS; reason=read-only // PER.Set.simple ASD:0x40507098 %Long 0x0 // UART6_DMA_TRIG_TX_MIS; reason=read-only // UART6_GPRCM[%s] PER.Set.simple ASD:0x40506800 %Long 0x0 // UART6_PWREN PER.Set.simple ASD:0x40506808 %Long 0x0 // UART6_CLKCFG // PER.Set.simple ASD:0x40506814 %Long 0x10000 // UART6_GPRCM_STAT; reason=read-only PER.Set.simple ASD:0x40507000 %Long 0x0 // UART6_CLKDIV PER.Set.simple ASD:0x40507008 %Long 0x0 // UART6_CLKSEL PER.Set.simple ASD:0x40507018 %Long 0x0 // UART6_PDBGCTL // UART6_CPU_INT[%s] // PER.Set.simple ASD:0x40507020 %Long 0x0 // UART6_CPU_INT_IIDX; reason=read-only PER.Set.simple ASD:0x40507028 %Long 0x0 // UART6_CPU_INT_IMASK // PER.Set.simple ASD:0x40507030 %Long 0x0 // UART6_CPU_INT_RIS; reason=read-only // PER.Set.simple ASD:0x40507038 %Long 0x0 // UART6_CPU_INT_MIS; reason=read-only // PER.Set.simple ASD:0x405070E0 %Long 0x0 // UART6_EVT_MODE; reason=read-only PER.Set.simple ASD:0x40507100 %Long 0x0 // UART6_CTL0 PER.Set.simple ASD:0x40507104 %Long 0x0 // UART6_LCRH // PER.Set.simple ASD:0x40507108 %Long 0x0 // UART6_STAT; reason=read-only PER.Set.simple ASD:0x4050710C %Long 0x0 // UART6_IFLS PER.Set.simple ASD:0x40507110 %Long 0x0 // UART6_IBRD PER.Set.simple ASD:0x40507114 %Long 0x0 // UART6_FBRD PER.Set.simple ASD:0x40507118 %Long 0x0 // UART6_GFCTL PER.Set.simple ASD:0x40507120 %Long 0x0 // UART6_TXDATA // PER.Set.simple ASD:0x40507124 %Long 0x0 // UART6_RXDATA; reason=read-only PER.Set.simple ASD:0x40507148 %Long 0x0 // UART6_AMASK PER.Set.simple ASD:0x4050714C %Long 0x0 // UART6_ADDR // VREF (Voltage Reference) // VREF (PERIPHERALREGION) // VREF_GPRCM[%s] PER.Set.simple ASD:0x40030800 %Long 0x0 // VREF_PWREN // PER.Set.simple ASD:0x40030814 %Long 0x10000 // VREF_STAT; reason=read-only PER.Set.simple ASD:0x40031000 %Long 0x0 // VREF_CLKDIV PER.Set.simple ASD:0x40031008 %Long 0x0 // VREF_CLKSEL PER.Set.simple ASD:0x40031100 %Long 0x0 // VREF_CTL0 // PER.Set.simple ASD:0x40031104 %Long 0x0 // VREF_CTL1; reason=read-only PER.Set.simple ASD:0x40031108 %Long 0x0 // VREF_CTL2 // WUC (Wake Up Controller) // WUC (PERIPHERALREGION) PER.Set.simple ASD:0x40424400 %Long 0x0 // WUC_FSUB_0 PER.Set.simple ASD:0x40424404 %Long 0x0 // WUC_FSUB_1 // WWDT (Window Watchdog Timer) // WWDT0 // WWDT0_GPRCM[%s] PER.Set.simple ASD:0x40080800 %Long 0x0 // WWDT0_PWREN // PER.Set.simple ASD:0x40080814 %Long 0x10000 // WWDT0_STAT; reason=read-only PER.Set.simple ASD:0x40081018 %Long 0x0 // WWDT0_PDBGCTL // WWDT0_INT_EVENT[%s] // PER.Set.simple ASD:0x40081020 %Long 0x0 // WWDT0_IIDX; reason=read-only PER.Set.simple ASD:0x40081028 %Long 0x0 // WWDT0_IMASK // PER.Set.simple ASD:0x40081030 %Long 0x0 // WWDT0_RIS; reason=read-only // PER.Set.simple ASD:0x40081038 %Long 0x0 // WWDT0_MIS; reason=read-only // PER.Set.simple ASD:0x400810E0 %Long 0x0 // WWDT0_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400810FC %Long 0x0 // WWDT0_DESC; reason=read-only PER.Set.simple ASD:0x40081100 %Long 0x0 // WWDT0_WWDTCTL0 PER.Set.simple ASD:0x40081104 %Long 0x0 // WWDT0_WWDTCTL1 PER.Set.simple ASD:0x40081108 %Long 0x0 // WWDT0_WWDTCNTRST // PER.Set.simple ASD:0x4008110C %Long 0x0 // WWDT0_WWDTSTAT; reason=read-only // WWDT1 // WWDT1_GPRCM[%s] PER.Set.simple ASD:0x40082800 %Long 0x0 // WWDT1_PWREN // PER.Set.simple ASD:0x40082814 %Long 0x10000 // WWDT1_STAT; reason=read-only PER.Set.simple ASD:0x40083018 %Long 0x0 // WWDT1_PDBGCTL // WWDT1_INT_EVENT[%s] // PER.Set.simple ASD:0x40083020 %Long 0x0 // WWDT1_IIDX; reason=read-only PER.Set.simple ASD:0x40083028 %Long 0x0 // WWDT1_IMASK // PER.Set.simple ASD:0x40083030 %Long 0x0 // WWDT1_RIS; reason=read-only // PER.Set.simple ASD:0x40083038 %Long 0x0 // WWDT1_MIS; reason=read-only // PER.Set.simple ASD:0x400830E0 %Long 0x0 // WWDT1_EVT_MODE; reason=read-only // PER.Set.simple ASD:0x400830FC %Long 0x0 // WWDT1_DESC; reason=read-only PER.Set.simple ASD:0x40083100 %Long 0x0 // WWDT1_WWDTCTL0 PER.Set.simple ASD:0x40083104 %Long 0x0 // WWDT1_WWDTCTL1 PER.Set.simple ASD:0x40083108 %Long 0x0 // WWDT1_WWDTCNTRST // PER.Set.simple ASD:0x4008310C %Long 0x0 // WWDT1_WWDTSTAT; reason=read-only