/** @file reg_m3core.h
*   @brief M3CORE Register Layer Header File
*   @date 15.March.2013
*   @version 03.05.00
*   
*   This file contains:
*   - Definitions
*   - Types
*   .
*   which are relevant for the System driver.
*/

/* (c) Texas Instruments 2009-2013, All rights reserved. */

#ifndef __REG_M3CORE_H__
#define __REG_M3CORE_H__

#include "sys_common.h"

/* USER CODE BEGIN (0) */
/* USER CODE END */

/* M3core Register Frame Definition */
/** @struct efcBase
*   @brief M3core Register Frame Definition
*
*   This type is used to access the M3core Registers.
*/
/** @typedef efcBASE_t
*   @brief M3core Register Frame Type Definition
*
*   This type is used to access the M3core Registers.
*/
/* M3 Core Register Frame Definition */

typedef volatile struct m3coreBase
{
    uint32 MASTERCTRL;      /* 0x0000        */
    uint32 INTCONTRTYPE;    /* 0x0004        */
    uint32 : 32;            /* 0x0008        */
    uint32 : 32;            /* 0x000C        */
    uint32 SYSTICKCTRLSR;   /* 0x0010        */
    uint32 SYSTICKRELOAD;   /* 0x0014        */
    uint32 SYSTICKCURRENT;  /* 0x0018        */
    uint32 SYSTICKCAL;      /* 0x001C        */
    uint32 Reserved_0[56];  /* 0x0020-0x00FF */
    uint32 SETENA[8];       /* 0x0100-0x011F */
    uint32 Reserved_1[24];  /* 0x0120-0x017F */
    uint32 CLRENA[8];       /* 0x0180-0x019F */
    uint32 Reserved_2[24];  /* 0x01A0-0x01FF */
    uint32 SETPEND[8];      /* 0x0200-0x021F */
    uint32 Reserved_3[24];  /* 0x0220-0x027F */
    uint32 CLRPEND[8];      /* 0x0280-0x029F */
    uint32 Reserved_4[24];  /* 0x02A0-0x02FF */
    uint32 ACTIVE[8];       /* 0x0300-0x031F */
    uint32 Reserved_5[24];  /* 0x0320-0x037F */
    uint32 Reserved_6[32];  /* 0x0380-0x03FF */
    uint32 INTPRIO[61];     /* 0x0400-0x07EF */
    uint32 Reserved_7[515]; /* 0x07F0-0x0CFF */
    uint32 CPUID;           /* 0x0D00        */
    uint32 INTCTRL;         /* 0x0D04        */
    uint32 VTBLOFF;         /* 0x0D08        */
    uint32 AIRCR;           /* 0x0D0C        */
    uint32 SYSCTRL;         /* 0x0D10        */
    uint32 CONFCTRL;        /* 0x0D14        */
    uint32 SYSPRIO[3];      /* 0x0D18-0x0D23 */
    uint32 SYSHCTRL;        /* 0x0D24        */
    uint32 CONFFAULTSR;     /* 0x0D28        */
    uint32 HARDFAULTSR;     /* 0x0D2C        */
    uint32 DEBUGFAULTSR;    /* 0x0D30        */
    uint32 MEMMANAGEADDR;   /* 0x0D34        */
    uint32 BUSFAULTADDR;    /* 0x0D38        */
    uint32 AUXFAULTADDR;    /* 0x0D3C        */
    uint32 PROCFEATURE0;    /* 0x0D40        */
    uint32 PROCFEATURE1;    /* 0x0D44        */
    uint32 DEBUGFEATURE;    /* 0x0D48        */
    uint32 AUXFEATURE;      /* 0x0D4C        */
    uint32 MEMMODFEATURE0;  /* 0x0D50        */
    uint32 MEMMODFEATURE1;  /* 0x0D54        */
    uint32 MEMMODFEATURE2;  /* 0x0D58        */
    uint32 MEMMODFEATURE3;  /* 0x0D5C        */
    uint32 ISAFEATURE0;     /* 0x0D60        */
    uint32 ISAFEATURE1;     /* 0x0D64        */
    uint32 ISAFEATURE2;     /* 0x0D68        */
    uint32 ISAFEATURE3;     /* 0x0D6C        */
    uint32 ISAFEATURE4;     /* 0x0D70        */
    uint32 ISAFEATURE5;     /* 0x0D74        */
    uint32 : 32;            /* 0x0D78        */
    uint32 : 32;            /* 0x0D7C        */
    uint32 : 32;            /* 0x0D80        */
    uint32 : 32;            /* 0x0D84        */
    uint32 COPROCACESS;     /* 0x0D88        */
    uint32 : 32;            /* 0x0D8C        */
    uint32 MPUTR;           /* 0x0D90        */
    uint32 MPUCR;           /* 0x0D94        */
    uint32 MPURNR;          /* 0x0D98        */
    uint32 MPURBAR0;        /* 0x0D9C        */
    uint32 MPURASR0;        /* 0x0DA0        */
    uint32 MPURBAR1;        /* 0x0DA4        */
    uint32 MPURASR1;        /* 0x0DA8        */
    uint32 MPURBAR2;        /* 0x0DAC        */
    uint32 MPURASR2;        /* 0x0DB0        */
    uint32 MPURBAR3;        /* 0x0DB4        */
    uint32 MPURASR3;        /* 0x0DB8        */
    uint32 Reserved_8[15];  /* 0x0DBC-0x0DEF */
    uint32 DHCSR;           /* 0x0DF0        */
    uint32 DCRSR;           /* 0x0DF4        */
    uint32 DCRDR;           /* 0x0DF8        */
    uint32 DEMCR;           /* 0x0DFC        */
    uint32 Reserved_9[64];  /* 0x0E00-0x0EFF */
    uint32 SWTRIGINT;       /* 0x0F00        */
    uint32 Reserved_10[51]; /* 0x0F04-0x0FCF */
    uint32 PERID[8];        /* 0x0FD0-0x0FEF */
    uint32 CID[4];          /* 0x0FF0-0x0FFF */
}m3coreBASE_t;

/** @def M3CORE
*   @brief M3 Core Register Frame Definition
*
*   This pointer is used by the system driver to access the M3 Core Registers
*/

#define NVIC_VTABLE    0xE000ED08
#define M3CORE ((m3coreBASE_t *)0xE000E000)

/* USER CODE BEGIN (1) */
/* USER CODE END */


#endif
