OLD Code without canupdateid function Can_ReturnType Can_Write (uint8 Hth, Can_PduType *PduInfo ) { #if CAN_TX_MO_DATAOVERWRITE == STD_OFF uint32 msgObjNr = 0; #endif uint8 PduData[8]; uint32 PduDataA; uint32 PduDataB; uint8_least txIndex; /* Module Base Address Initialization */ CAN_RegMapType *canCore; /* Message Details structure */ const Can_HardwareHandleType * msgDetails; Can_ReturnType Status = CAN_BUSY; /* Target address PduData */ /* Source address &PduInfo->sdu[0] */ /* Length 8 */ (void)memcpy( PduData, &PduInfo->sdu[0], 8); PduDataA = *((uint32*)&PduData[0]); PduDataB = *((uint32*)&PduData[4]); /* Start of Hardware independent code part */ CAN_DET_REPORT_ERROR_NOTOK(Can_DriverState != CAN_READY,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_UNINIT); /* Check for Max Controllers */ CAN_DET_REPORT_ERROR_NOTOK(Hth>=CAN_MAX_HANDLES,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_HANDLE); CAN_DET_REPORT_ERROR_NOTOK((PduInfo->length)>8,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_DLC); CAN_DET_REPORT_ERROR_NOTOK(PduInfo==NULL_PTR,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_POINTER); CAN_DET_REPORT_ERROR_NOTOK(PduInfo->sdu ==NULL_PTR,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_POINTER); /* End of hardware independent code part */ /* Address of Msg structure */ msgDetails = (&Can_HrdHndlTable[Hth]); canCore = (Can_DriverConfig[msgDetails->Node].BaseAddress); /* Start of hardware dependent code part. This code part is executed only if conditions in the hardware independent part are satisfied */ #if CAN_TX_MO_DATAOVERWRITE == STD_OFF msgObjNr = msgDetails->Buffer; /* Check whether the MsgObj is tranmsitted on the bus */ if ( ((msgObjNr <= 32) && (!IS_REGISTER_BIT_SET(canCore->MsgObj.TxRq1,(1< 32) && (!IS_REGISTER_BIT_SET(canCore->MsgObj.TxRq3,(1<Transmit.If1Cmd); /* calculate the txIndex */ txIndex = (msgDetails->Handle); /* Copy Txpduid to Global Variable */ Can_TxPduId[txIndex] = PduInfo->swPduHandle; /* Check if ID is extended Identifier */ // if(msgDetails->Idtype == CAN_STD) { // Build complete arbitration register value at once canCore->Transmit.If1Arb = ((uint32)PduInfo->id << CAN_STD_ID_ALIGNMENT) | CAN_IF1ARB_DIR | // TX direction CAN_IF1ARB_MSGVAL; // Message valid canCore->Transmit.If1Mask = msgDetails->AcceptanceMask << CAN_STD_ID_ALIGNMENT; } else { // Extended ID: Build complete arbitration register value at once canCore->Transmit.If1Arb = CAN_IF1ARB_XTD | // Extended ID (PduInfo->id) | // CAN ID CAN_IF1ARB_DIR | // TX direction CAN_IF1ARB_MSGVAL; // Message valid canCore->Transmit.If1Mask = msgDetails->AcceptanceMask; } /* Check if ID is extended Identifier */ /* if (msgDetails->Idtype == CAN_STD) { canCore->Transmit.If1Arb = (uint32)PduInfo->id << CAN_STD_ID_ALIGNMENT; canCore->Transmit.If1Mask = msgDetails->AcceptanceMask << CAN_STD_ID_ALIGNMENT; } else { // Write the acceptance mask to register canCore->Transmit.If1Arb = CAN_IF1ARB_XTD | (PduInfo->id); canCore->Transmit.If1Mask = msgDetails->AcceptanceMask; } SET_REGISTER_BIT(canCore->Transmit.If1Arb, ( CAN_IF1ARB_DIR | //Set message valid bit CAN_IF1ARB_MSGVAL));*/ /* Copy DLC to the Buffer */ canCore->Transmit.If1MsgCtrl = PduInfo->length; /* Check if ID is configired for Interrupts */ if(msgDetails->Interrupt==(boolean)TRUE) { /* Write the acceptance mask to register */ SET_REGISTER_BIT(canCore->Transmit.If1MsgCtrl ,CAN_IF1MSGCNT_TXIE); } /* Set respective bits in Msg Ctrl Register */ SET_REGISTER_BIT(canCore->Transmit.If1MsgCtrl, ( CAN_IF1MSGCNT_NEWDAT | #if (CAN_TRIGGER_TRANSMIT != STD_ON) CAN_IF1MSGCNT_TXRQST | #endif CAN_IF1MSGCNT_EOB )); #if (CAN_TRIGGER_TRANSMIT == STD_ON) /* Toyota: Store the TX information inorder of the calls mades to this function */ /* the Can_MsgTXStatus array holds the Hth information. this will be used in the 1ms */ /* Update the Global variable as configured */ Can_MsgTXStatus[Can_NumOfFrmScheduled] = Hth; /*Increment the count */ Can_NumOfFrmScheduled++; /* if the frames are not transmitted due to error conditions */ /* then the number of frame scheduled will not decrese. this */ /* check is introduced inorder to avoid overflow (exceeding the range) */ /* and accessing undesired location in the can_mainfunction_triggertransmit */ if(Can_NumOfFrmScheduled > CAN_NUM_TX_HANDLES) { Can_NumOfFrmScheduled = 0; } #endif /* Get the address of Data pointer 0 */ /* MISRA RULE 45 VIOLATION: The cast must take place here. */ canCore->Transmit.If1DataA = SWAP_HOST_TO_DCAN(PduDataA); canCore->Transmit.If1DataB = SWAP_HOST_TO_DCAN(PduDataB); canCore->Transmit.If1Cmd = CAN_IF1CMDMASK_DATAB | CAN_IF1CMDMASK_DATAA | CAN_IF1CMDMASK_CTRL | CAN_IF1CMDMASK_ARB | CAN_IF1CMDMASK_MASK | CAN_IF1CMDMASK_RDWR | /* Write the Message number */ msgDetails->Buffer; Can_FindIfxCmdBusy(&canCore->Transmit.If1Cmd); // /* Update the Global variable as configured */ Can_MsgStatus[txIndex] = CAN_TX_CONFIGURED; /* Update the Status Variable */ Status = CAN_OK; /* Return the status of the function */ //FUN_SYSResumeIRQs_V(); } return Status; } NEW Code with canupdateid function Can_ReturnType Can_Write (uint8 Hth, Can_PduType *PduInfo ) { #if CAN_TX_MO_DATAOVERWRITE == STD_OFF uint32 msgObjNr = 0; #endif uint8 PduData[8]; uint32 PduDataA; uint32 PduDataB; uint8_least txIndex; /* Module Base Address Initialization */ CAN_RegMapType *canCore; /* Message Details structure */ const Can_HardwareHandleType * msgDetails; Can_ReturnType Status = CAN_BUSY; /* Target address PduData */ /* Source address &PduInfo->sdu[0] */ /* Length 8 */ (void)memcpy( PduData, &PduInfo->sdu[0], 8); PduDataA = *((uint32*)&PduData[0]); PduDataB = *((uint32*)&PduData[4]); /* Start of Hardware independent code part */ CAN_DET_REPORT_ERROR_NOTOK(Can_DriverState != CAN_READY,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_UNINIT); /* Check for Max Controllers */ CAN_DET_REPORT_ERROR_NOTOK(Hth>=CAN_MAX_HANDLES,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_HANDLE); CAN_DET_REPORT_ERROR_NOTOK((PduInfo->length)>8,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_DLC); CAN_DET_REPORT_ERROR_NOTOK(PduInfo==NULL_PTR,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_POINTER); CAN_DET_REPORT_ERROR_NOTOK(PduInfo->sdu ==NULL_PTR,CAN_INSTANCE_ID,CAN_APIID_WRITE, CAN_E_PARAM_POINTER); /* End of hardware independent code part */ /* Address of Msg structure */ msgDetails = (&Can_HrdHndlTable[Hth]); canCore = (Can_DriverConfig[msgDetails->Node].BaseAddress); /* Start of hardware dependent code part. This code part is executed only if conditions in the hardware independent part are satisfied */ // //#if CAN_TX_MO_DATAOVERWRITE == STD_OFF // msgObjNr = msgDetails->Buffer; // /* Check whether the MsgObj is tranmsitted on the bus */ // if ( ((msgObjNr <= 32) && (!IS_REGISTER_BIT_SET(canCore->MsgObj.TxRq1,(1< 32) && (!IS_REGISTER_BIT_SET(canCore->MsgObj.TxRq3,(1<Transmit.If1Cmd); /* calculate the txIndex */ txIndex = (msgDetails->Handle); /* Copy Txpduid to Global Variable */ Can_TxPduId[txIndex] = PduInfo->swPduHandle; /* ============================================================ */ // /* DYNAMIC CAN ID UPDATE - Single Mailbox Multiple Messages */ /* ============================================================ */ { uint32 newArbValue; uint32 mailboxNum = msgDetails->Buffer; /* Build complete arbitration register value */ if(msgDetails->Idtype == CAN_STD) { /* Standard 11-bit ID */ newArbValue = ((uint32)PduInfo->id << 18U) | /* ID in bits 28-18 */ (0x1U << 29U) | /* MSGVAL - message valid */ (0x1U << 13U); /* DIR - transmit direction */ } else /* CAN_XTD */ { /* Extended 29-bit ID */ newArbValue = (PduInfo->id & 0x1FFFFFFFU) | /* ID in bits 28-0 */ (0x1U << 29U) | /* MSGVAL - message valid */ (0x1U << 30U) | /* XTD - extended ID flag */ (0x1U << 13U); /* DIR - transmit direction */ } canUpdateID((canBASE_t*)canCore, mailboxNum, newArbValue); // /* Wait for interface to be ready */ // Can_FindIfxCmdBusy(&canCore->Transmit.If1Cmd); // // /* Write the new arbitration value */ // canCore->Transmit.If1Arb = newArbValue; // // /* Write the acceptance mask */ // if(msgDetails->Idtype == CAN_STD) // { // canCore->Transmit.If1Mask = msgDetails->AcceptanceMask << CAN_STD_ID_ALIGNMENT; // } // else // { // canCore->Transmit.If1Mask = msgDetails->AcceptanceMask; // } // // /* Set mask bits */ // SET_REGISTER_BIT(canCore->Transmit.If1Mask, (CAN_IF1MASK_MDIR | CAN_IF1MASK_MXTD)); // // /* Write arbitration and mask to message object */ // canCore->Transmit.If1Cmd = CAN_IF1CMDMASK_ARB | // CAN_IF1CMDMASK_MASK | // CAN_IF1CMDMASK_RDWR | // mailboxNum; // // /* Wait for command to complete */ // Can_FindIfxCmdBusy(&canCore->Transmit.If1Cmd); } /* ============================================================ */ /* END DYNAMIC ID UPDATE */ /* ============================================================ */ // /* Check if ID is extended Identifier */ // // if(msgDetails->Idtype == CAN_STD) // { // // Build complete arbitration register value at once // canCore->Transmit.If1Arb = ((uint32)PduInfo->id << CAN_STD_ID_ALIGNMENT) | // CAN_IF1ARB_DIR | // TX direction // CAN_IF1ARB_MSGVAL; // Message valid // // canCore->Transmit.If1Mask = msgDetails->AcceptanceMask << CAN_STD_ID_ALIGNMENT; // } // else // { // // Extended ID: Build complete arbitration register value at once // canCore->Transmit.If1Arb = CAN_IF1ARB_XTD | // Extended ID // (PduInfo->id) | // CAN ID // CAN_IF1ARB_DIR | // TX direction // CAN_IF1ARB_MSGVAL; // Message valid // // canCore->Transmit.If1Mask = msgDetails->AcceptanceMask; // } /* Check if ID is extended Identifier */ /* if (msgDetails->Idtype == CAN_STD) { canCore->Transmit.If1Arb = (uint32)PduInfo->id << CAN_STD_ID_ALIGNMENT; canCore->Transmit.If1Mask = msgDetails->AcceptanceMask << CAN_STD_ID_ALIGNMENT; } else { // Write the acceptance mask to register canCore->Transmit.If1Arb = CAN_IF1ARB_XTD | (PduInfo->id); canCore->Transmit.If1Mask = msgDetails->AcceptanceMask; } SET_REGISTER_BIT(canCore->Transmit.If1Arb, ( CAN_IF1ARB_DIR | //Set message valid bit CAN_IF1ARB_MSGVAL));*/ /* Copy DLC to the Buffer */ canCore->Transmit.If1MsgCtrl = PduInfo->length; /* Check if ID is configired for Interrupts */ if(msgDetails->Interrupt==(boolean)TRUE) { /* Write the acceptance mask to register */ SET_REGISTER_BIT(canCore->Transmit.If1MsgCtrl ,CAN_IF1MSGCNT_TXIE); } /* Set respective bits in Msg Ctrl Register */ SET_REGISTER_BIT(canCore->Transmit.If1MsgCtrl, ( CAN_IF1MSGCNT_NEWDAT | #if (CAN_TRIGGER_TRANSMIT != STD_ON) CAN_IF1MSGCNT_TXRQST | #endif CAN_IF1MSGCNT_EOB )); #if (CAN_TRIGGER_TRANSMIT == STD_ON) /* Toyota: Store the TX information inorder of the calls mades to this function */ /* the Can_MsgTXStatus array holds the Hth information. this will be used in the 1ms */ /* Update the Global variable as configured */ Can_MsgTXStatus[Can_NumOfFrmScheduled] = Hth; /*Increment the count */ Can_NumOfFrmScheduled++; /* if the frames are not transmitted due to error conditions */ /* then the number of frame scheduled will not decrese. this */ /* check is introduced inorder to avoid overflow (exceeding the range) */ /* and accessing undesired location in the can_mainfunction_triggertransmit */ if(Can_NumOfFrmScheduled > CAN_NUM_TX_HANDLES) { Can_NumOfFrmScheduled = 0; } #endif /* Get the address of Data pointer 0 */ /* MISRA RULE 45 VIOLATION: The cast must take place here. */ canCore->Transmit.If1DataA = SWAP_HOST_TO_DCAN(PduDataA); canCore->Transmit.If1DataB = SWAP_HOST_TO_DCAN(PduDataB); canCore->Transmit.If1Cmd = CAN_IF1CMDMASK_DATAB | CAN_IF1CMDMASK_DATAA | CAN_IF1CMDMASK_CTRL | CAN_IF1CMDMASK_ARB | CAN_IF1CMDMASK_MASK | CAN_IF1CMDMASK_RDWR | /* Write the Message number */ msgDetails->Buffer; Can_FindIfxCmdBusy(&canCore->Transmit.If1Cmd); // /* Update the Global variable as configured */ Can_MsgStatus[txIndex] = CAN_TX_CONFIGURED; /* Update the Status Variable */ Status = CAN_OK; /* Return the status of the function */ //FUN_SYSResumeIRQs_V(); return Status; }