/** @file pinmux.h
*   @brief PINMUX Driver Implementation File
*   @date 25.May.2015
*   @version 01.00.00
*
*/

/*
* Copyright (C) 2022 Texas Instruments Incorporated - TI web adress www.ti.com
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


#ifndef PINMUX_H
#define PINMUX_H

#include "reg_pinmux.h"

#ifdef __cplusplus
extern "C" {
#endif

/* PIN E18, PADAA functionality */
#define PINE18_PADAA                          0X0U
#define PINE18_PADAA_GPIO_12                  0X0U
#define PINE18_PADAA_MIBSPIA_HOSTIRQ          0X1U
#define PINE18_PADAA_MIBSPIB_CS1              0X6U

/* PIN H1, PADAB functionality */
#define PINH1_PADAB                           0X4U
#define PINH1_PADAB_GPIO_13                   0X0U
#define PINH1_PADAB_GPIO_0                    0X1U
#define PINH1_PADAB_PMIC_CLKOUT               0X2U
#define PINH1_PADAB_EPWM_TZ2                  0X3U
#define PINH1_PADAB_FE1_REFCLK                0X7U
#define PINH1_PADAB_EPWMA1                    0XAU
#define PINH1_PADAB_EPWMB0                    0XBU

/* PIN J2, PADAC functionality */
#define PINJ2_PADAC                           0X8U
#define PINJ2_PADAC_GPIO_16                   0X0U
#define PINJ2_PADAC_GPIO_1                    0X1U
#define PINJ2_PADAC_EPWM_TZ1                  0X3U
#define PINJ2_PADAC_FE2_REFCLK                0X7U
#define PINJ2_PADAC_DMM_MUX_IN                0XCU
#define PINJ2_PADAC_MIBSPIB_CS1               0XDU
#define PINJ2_PADAC_MIBSPIB_CS2               0XEU

/* PIN C1, PADAD functionality */
#define PINC1_PADAD                           0XCU
#define PINC1_PADAD_GPIO_19                   0X0U
#define PINC1_PADAD_MIBSPIA_MOSI              0X1U
#define PINC1_PADAD_MCANA_RX                  0X2U
#define PINC1_PADAD_DSS_UARTA_TX              0X8U
#define PINC1_PADAD_MCANB_RX                  0X9U
#define PINC1_PADAD_I2CA_SCL                  0XAU

/* PIN B1, PADAE functionality */
#define PINB1_PADAE                           0X10U
#define PINB1_PADAE_GPIO_20                   0X0U
#define PINB1_PADAE_MIBSPIA_MISO              0X1U
#define PINB1_PADAE_MCANA_TX                  0X2U
#define PINB1_PADAE_MCANB_TX                  0X9U
#define PINB1_PADAE_I2CA_SDA                  0XAU

/* PIN B2, PADAF functionality */
#define PINB2_PADAF                           0X14U
#define PINB2_PADAF_GPIO_3                    0X0U
#define PINB2_PADAF_MIBSPIA_CLK               0X1U
#define PINB2_PADAF_RCOSC_CLK                 0X2U
#define PINB2_PADAF_MCANB_RX                  0X6U
#define PINB2_PADAF_DSS_UARTA_TX              0X7U
#define PINB2_PADAF_MCANA_RX                  0X9U

/* PIN A2, PADAG functionality */
#define PINA2_PADAG                           0X18U
#define PINA2_PADAG_GPIO_30                   0X0U
#define PINA2_PADAG_MIBSPIA_CS0               0X1U
#define PINA2_PADAG_RCOSC_CLK                 0X2U
#define PINA2_PADAG_MCANB_TX                  0X6U
#define PINA2_PADAG_MCANA_TX                  0X9U

/* PIN C18, PADAH functionality */
#define PINC18_PADAH                          0X1CU
#define PINC18_PADAH_GPIO_21                  0X0U
#define PINC18_PADAH_MIBSPIB_MOSI             0X1U
#define PINC18_PADAH_I2CA_SDA                 0X2U
#define PINC18_PADAH_EPWMA0                   0X3U
#define PINC18_PADAH_MCANB_RX                 0X7U

/* PIN C19, PADAI functionality */
#define PINC19_PADAI                          0X20U
#define PINC19_PADAI_GPIO_22                  0X0U
#define PINC19_PADAI_MIBSPIB_MISO             0X1U
#define PINC19_PADAI_I2CA_SCL                 0X2U
#define PINC19_PADAI_EPWMB0                   0X3U
#define PINC19_PADAI_DSS_UARTA_TX             0X6U
#define PINC19_PADAI_MCANB_TX                 0X7U

/* PIN D18, PADAJ functionality */
#define PIND18_PADAJ                          0X24U
#define PIND18_PADAJ_GPIO_5                   0X0U
#define PIND18_PADAJ_MIBSPIB_CLK              0X1U
#define PIND18_PADAJ_UARTA_RX                 0X2U
#define PIND18_PADAJ_EPWMC0                   0X3U
#define PIND18_PADAJ_UARTB_TX                 0X6U
#define PIND18_PADAJ_MCANA_RX                 0X8U

/* PIN D19, PADAK functionality */
#define PIND19_PADAK                          0X28U
#define PIND19_PADAK_GPIO_4                   0X0U
#define PIND19_PADAK_MIBSPIB_CS0              0X1U
#define PIND19_PADAK_UARTA_TX                 0X2U
#define PIND19_PADAK_UARTB_TX                 0X6U
#define PIND19_PADAK_MCANA_TX                 0X9U

/* PIN C2, PADAL functionality */
#define PINC2_PADAL                           0X2CU
#define PINC2_PADAL_GPIO_8                    0X0U
#define PINC2_PADAL_QSPI_0                    0X1U
#define PINC2_PADAL_MIBSPIB_MISO              0X2U

/* PIN D2, PADAM functionality */
#define PIND2_PADAM                           0X30U
#define PIND2_PADAM_GPIO_9                    0X0U
#define PIND2_PADAM_QSPI_1                    0X1U
#define PIND2_PADAM_MIBSPIB_MOSI              0X2U
#define PIND2_PADAM_MIBSPIB_CS2               0X8U

/* PIN D1, PADAN functionality */
#define PIND1_PADAN                           0X34U
#define PIND1_PADAN_GPIO_10                   0X0U
#define PIND1_PADAN_QSPI_2                    0X1U
#define PIND1_PADAN_MCANA_TX                  0X8U

/* PIN E2, PADAO functionality */
#define PINE2_PADAO                           0X38U
#define PINE2_PADAO_GPIO_11                   0X0U
#define PINE2_PADAO_QSPI_3                    0X1U
#define PINE2_PADAO_MCANA_RX                  0X8U

/* PIN E1, PADAP functionality */
#define PINE1_PADAP                           0X3CU
#define PINE1_PADAP_GPIO_7                    0X0U
#define PINE1_PADAP_QSPI_CLK                  0X1U
#define PINE1_PADAP_MIBSPIB_CLK               0X2U
#define PINE1_PADAP_DSS_UARTA_TX              0X6U

/* PIN F2, PADAQ functionality */
#define PINF2_PADAQ                           0X40U
#define PINF2_PADAQ_GPIO_6                    0X0U
#define PINF2_PADAQ_QSPI_CS                   0X1U
#define PINF2_PADAQ_MIBSPIB_CS0               0X2U

/* PIN L3, PADAR functionality */
#define PINL3_PADAR                           0X44U
#define PINL3_PADAR_NERROR_IN                 0X0U

/* PIN K1, PADAS functionality */
#define PINK1_PADAS                           0X48U
#define PINK1_PADAS_WARM_RESET                0X0U

/* PIN L1, PADAT functionality */
#define PINL1_PADAT                           0X4CU
#define PINL1_PADAT_NERROR_OUT                0X0U

/* PIN C3, PADAU functionality */
#define PINC3_PADAU                           0X50U
#define PINC3_PADAU_GPIO_17                   0X0U
#define PINC3_PADAU_TCK                       0X1U
#define PINC3_PADAU_UARTB_TX                  0X2U
#define PINC3_PADAU_MCANA_TX                  0X8U

/* PIN D4, PADAV functionality */
#define PIND4_PADAV                           0X54U
#define PIND4_PADAV_GPIO_18                   0X0U
#define PIND4_PADAV_TMS                       0X1U
#define PIND4_PADAV_MCANA_RX                  0X6U

/* PIN C5, PADAW functionality */
#define PINC5_PADAW                           0X58U
#define PINC5_PADAW_GPIO_23                   0X0U
#define PINC5_PADAW_TDI                       0X1U
#define PINC5_PADAW_UARTA_RX                  0X2U
#define PINC5_PADAW_DSS_UARTA_RX              0X7U

/* PIN D6, PADAX functionality */
#define PIND6_PADAX                           0X5CU
#define PIND6_PADAX_GPIO_24                   0X0U
#define PIND6_PADAX_TDO                       0X1U
#define PIND6_PADAX_UARTA_TX                  0X2U
#define PIND6_PADAX_UARTB_TX                  0X6U
#define PIND6_PADAX_NDMM_EN                   0X9U

/* PIN E3, PADAY functionality */
#define PINE3_PADAY                           0X60U
#define PINE3_PADAY_GPIO_25                   0X0U
#define PINE3_PADAY_MCU_CLKOUT                0X1U
#define PINE3_PADAY_EPWMA0                    0XCU

/* PIN H2, PADAZ functionality */
#define PINH2_PADAZ                           0X64U
#define PINH2_PADAZ_GPIO_26                   0X0U
#define PINH2_PADAZ_GPIO_2                    0X1U
#define PINH2_PADAZ_UARTB_TX                  0X7U
#define PINH2_PADAZ_RCSS_GPIO_34              0X8U
#define PINH2_PADAZ_PMIC_CLKOUT               0XAU
#define PINH2_PADAZ_EPWM_TZ0                  0XEU

/* PIN F1, PADBA functionality */
#define PINF1_PADBA                           0X68U
#define PINF1_PADBA_GPIO_27                   0X0U
#define PINF1_PADBA_PMIC_CLKOUT               0X1U
#define PINF1_PADBA_OBS_CLKOUT                0X2U
#define PINF1_PADBA_EPWMA1                    0XBU
#define PINF1_PADBA_EPWMB0                    0XCU

/* PIN G3, PADBB functionality */
#define PING3_PADBB                           0X6CU
#define PING3_PADBB_GPIO_28                   0X0U
#define PING3_PADBB_SYNC_IN                   0X1U
#define PING3_PADBB_RCSS_MCASPB_AHCLKR        0X3U
#define PING3_PADBB_UARTB_RX                  0X6U
#define PING3_PADBB_DMM_MUX_IN                0X7U
#define PING3_PADBB_DSS_UARTA_RX              0X8U

/* PIN E17, PADBC functionality */
#define PINE17_PADBC                          0X70U
#define PINE17_PADBC_GPIO_29                  0X0U
#define PINE17_PADBC_RCOSC_CLK                0X2U
#define PINE17_PADBC_DMM_MUX_IN               0X9U
#define PINE17_PADBC_MIBSPIB_CS1              0XAU
#define PINE17_PADBC_MIBSPIB_CS2              0XBU
#define PINE17_PADBC_EPWMB0                   0XCU
#define PINE17_PADBC_EPWMB1                   0XDU

/* PIN G2, PADBD functionality */
#define PING2_PADBD                           0X74U
#define PING2_PADBD_GPIO_15                   0X0U
#define PING2_PADBD_RS232_RX                  0X1U
#define PING2_PADBD_UARTA_RX                  0X2U
#define PING2_PADBD_UARTB_RX                  0X7U
#define PING2_PADBD_MCANA_RX                  0X8U
#define PING2_PADBD_I2CA_SCL                  0X9U
#define PING2_PADBD_EPWMB0                    0XAU
#define PING2_PADBD_EPWMB1                    0XBU
#define PING2_PADBD_EPWMC0                    0XCU

/* PIN G1, PADBE functionality */
#define PING1_PADBE                           0X78U
#define PING1_PADBE_GPIO_14                   0X0U
#define PING1_PADBE_RS232_TX                  0X1U
#define PING1_PADBE_UARTA_TX                  0X5U
#define PING1_PADBE_UARTB_TX                  0X6U
#define PING1_PADBE_MCANA_TX                  0XAU
#define PING1_PADBE_I2CA_SDA                  0XBU
#define PING1_PADBE_EPWMA0                    0XCU
#define PING1_PADBE_EPWMA1                    0XDU
#define PING1_PADBE_NDMM_EN                   0XEU

/* PIN V16, PADBF functionality */
#define PINV16_PADBF                          0X7CU
#define PINV16_PADBF_TRACE_DATA_0             0X0U
#define PINV16_PADBF_GPIO_31                  0X1U
#define PINV16_PADBF_DMM0                     0X2U
#define PINV16_PADBF_UARTA_TX                 0X4U
#define PINV16_PADBF_RCSS_MCASPC_DAT1         0X7U
#define PINV16_PADBF_I2CA_SDA                 0XAU

/* PIN U15, PADBG functionality */
#define PINU15_PADBG                          0X80U
#define PINU15_PADBG_TRACE_DATA_1             0X0U
#define PINU15_PADBG_RCSS_GPIO_32             0X1U
#define PINU15_PADBG_DMM1                     0X2U
#define PINU15_PADBG_EPWMC_SYNCI              0X3U
#define PINU15_PADBG_UARTA_RX                 0X4U
#define PINU15_PADBG_RCSS_MCASPC_DAT0         0X7U
#define PINU15_PADBG_I2CA_SCL                 0XAU

/* PIN W16, PADBH functionality */
#define PINW16_PADBH                          0X84U
#define PINW16_PADBH_TRACE_DATA_2             0X0U
#define PINW16_PADBH_RCSS_GPIO_33             0X1U
#define PINW16_PADBH_DMM2                     0X2U
#define PINW16_PADBH_EPWMB_SYNCI              0X3U
#define PINW16_PADBH_RCSS_MCASPC_FSR          0X7U

/* PIN V15, PADBI functionality */
#define PINV15_PADBI                          0X88U
#define PINV15_PADBI_TRACE_DATA_3             0X0U
#define PINV15_PADBI_RCSS_GPIO_34             0X1U
#define PINV15_PADBI_DMM3                     0X2U
#define PINV15_PADBI_EPWMC_SYNCO              0X4U
#define PINV15_PADBI_RCSS_MCASPC_ACLKR        0X7U

/* PIN W15, PADBJ functionality */
#define PINW15_PADBJ                          0X8CU
#define PINW15_PADBJ_TRACE_DATA_4             0X0U
#define PINW15_PADBJ_RCSS_GPIO_35             0X1U
#define PINW15_PADBJ_DMM4                     0X2U
#define PINW15_PADBJ_EPWMB_SYNCO              0X4U
#define PINW15_PADBJ_RCSS_MCASPC_FSX          0X7U

/* PIN V14, PADBK functionality */
#define PINV14_PADBK                          0X90U
#define PINV14_PADBK_TRACE_DATA_5             0X0U
#define PINV14_PADBK_RCSS_GPIO_36             0X1U
#define PINV14_PADBK_DMM5                     0X2U
#define PINV14_PADBK_EPWM_TZ2                 0X4U
#define PINV14_PADBK_UARTB_TX                 0X5U
#define PINV14_PADBK_RCSS_MCASPC_ACLKX        0X7U

/* PIN U13, PADBL functionality */
#define PINU13_PADBL                          0X94U
#define PINU13_PADBL_TRACE_DATA_6             0X0U
#define PINU13_PADBL_RCSS_GPIO_37             0X1U
#define PINU13_PADBL_DMM6                     0X2U
#define PINU13_PADBL_EPWM_TZ1                 0X4U
#define PINU13_PADBL_RCSS_MCASPC_AHCLKX       0X7U

/* PIN W14, PADBM functionality */
#define PINW14_PADBM                          0X98U
#define PINW14_PADBM_TRACE_DATA_7             0X0U
#define PINW14_PADBM_RCSS_GPIO_38             0X1U
#define PINW14_PADBM_DMM7                     0X2U
#define PINW14_PADBM_EPWM_TZ0                 0X4U
#define PINW14_PADBM_DSS_UARTA_TX             0X5U
#define PINW14_PADBM_RCSS_MCASPB_ACLKX        0X7U

/* PIN V13, PADBN functionality */
#define PINV13_PADBN                          0X9CU
#define PINV13_PADBN_TRACE_DATA_8             0X0U
#define PINV13_PADBN_RCSS_GPIO_39             0X1U
#define PINV13_PADBN_DMM8                     0X2U
#define PINV13_PADBN_MCANA_TX                 0X4U
#define PINV13_PADBN_EPWMA_SYNCI              0X5U
#define PINV13_PADBN_RCSS_MCASPB_FSX          0X7U

/* PIN W13, PADBO functionality */
#define PINW13_PADBO                          0XA0U
#define PINW13_PADBO_TRACE_DATA_9             0X0U
#define PINW13_PADBO_RCSS_GPIO_40             0X1U
#define PINW13_PADBO_DMM9                     0X2U
#define PINW13_PADBO_MCANA_RX                 0X4U
#define PINW13_PADBO_EPWMA_SYNCO              0X5U
#define PINW13_PADBO_RCSS_MCASPB_ACLKR        0X7U

/* PIN U11, PADBP functionality */
#define PINU11_PADBP                          0XA4U
#define PINU11_PADBP_TRACE_DATA_10            0X0U
#define PINU11_PADBP_RCSS_GPIO_41             0X1U
#define PINU11_PADBP_DMM10                    0X2U
#define PINU11_PADBP_EPWMC0                   0X4U
#define PINU11_PADBP_RCSS_MCASPB_FSR          0X7U

/* PIN V11, PADBQ functionality */
#define PINV11_PADBQ                          0XA8U
#define PINV11_PADBQ_TRACE_DATA_11            0X0U
#define PINV11_PADBQ_RCSS_GPIO_42             0X1U
#define PINV11_PADBQ_DMM11                    0X2U
#define PINV11_PADBQ_EPWMC1                   0X4U
#define PINV11_PADBQ_RCSS_MCASPB_DAT0         0X7U

/* PIN W11, PADBR functionality */
#define PINW11_PADBR                          0XACU
#define PINW11_PADBR_TRACE_DATA_12            0X0U
#define PINW11_PADBR_RCSS_GPIO_43             0X1U
#define PINW11_PADBR_DMM12                    0X2U
#define PINW11_PADBR_EPWMA0                   0X4U
#define PINW11_PADBR_MCANB_TX                 0X5U
#define PINW11_PADBR_RCSS_MCASPB_DAT1         0X7U

/* PIN V10, PADBS functionality */
#define PINV10_PADBS                          0XB0U
#define PINV10_PADBS_TRACE_DATA_13            0X0U
#define PINV10_PADBS_RCSS_GPIO_44             0X1U
#define PINV10_PADBS_DMM13                    0X2U
#define PINV10_PADBS_EPWMA1                   0X4U
#define PINV10_PADBS_MCANB_RX                 0X5U
#define PINV10_PADBS_RCSS_MCASPB_DAT2         0X7U

/* PIN W10, PADBT functionality */
#define PINW10_PADBT                          0XB4U
#define PINW10_PADBT_TRACE_DATA_14            0X0U
#define PINW10_PADBT_RCSS_GPIO_45             0X1U
#define PINW10_PADBT_DMM14                    0X2U
#define PINW10_PADBT_EPWMB0                   0X4U
#define PINW10_PADBT_RCSS_MCASPB_DAT3         0X7U

/* PIN T10, PADBU functionality */
#define PINT10_PADBU                          0XB8U
#define PINT10_PADBU_TRACE_DATA_15            0X0U
#define PINT10_PADBU_RCSS_GPIO_46             0X1U
#define PINT10_PADBU_DMM15                    0X2U
#define PINT10_PADBU_EPWMB1                   0X4U
#define PINT10_PADBU_RCSS_MCASPB_DAT4         0X7U
#define PINT10_PADBU_RCSS_I2CA_SDA            0XBU

/* PIN W12, PADBV functionality */
#define PINW12_PADBV                          0XBCU
#define PINW12_PADBV_TRACE_CLK                0X0U
#define PINW12_PADBV_RCSS_GPIO_47             0X1U
#define PINW12_PADBV_DMM_CLK                  0X2U
#define PINW12_PADBV_HW_SYNC_FE1              0X3U
#define PINW12_PADBV_HW_SYNC_FE2              0X4U
#define PINW12_PADBV_RCSS_MCASPB_DAT5         0X7U
#define PINW12_PADBV_DSS_UARTA_RX             0XAU
#define PINW12_PADBV_RCSS_I2CA_SCL            0XBU

/* PIN V12, PADBW functionality */
#define PINV12_PADBW                          0XC0U
#define PINV12_PADBW_TRACE_CTL                0X0U
#define PINV12_PADBW_RCSS_GPIO_48             0X1U
#define PINV12_PADBW_DMM_SYNC                 0X2U
#define PINV12_PADBW_HW_SYNC_FE2              0X3U
#define PINV12_PADBW_HW_SYNC_FE1              0X4U
#define PINV12_PADBW_RCSS_MCASPB_AHCLKX       0X7U
#define PINV12_PADBW_DSS_UARTA_TX             0XAU

/* PIN E19, PADBX functionality */
#define PINE19_PADBX                          0XC4U
#define PINE19_PADBX_RCSS_GPIO_49             0X0U
#define PINE19_PADBX_MII_COL                  0X1U
#define PINE19_PADBX_RMII_REFCLK              0X2U
#define PINE19_PADBX_RCSS_MCASPA_DAT3         0X4U
#define PINE19_PADBX_EPWMA1                   0X6U

/* PIN F16, PADBY functionality */
#define PINF16_PADBY                          0XC8U
#define PINF16_PADBY_RCSS_GPIO_50             0X0U
#define PINF16_PADBY_MII_CRS                  0X1U
#define PINF16_PADBY_RMII_CRS_DV              0X2U
#define PINF16_PADBY_I2CA_SDA                 0X3U
#define PINF16_PADBY_RCSS_MCASPA_DAT2         0X4U
#define PINF16_PADBY_EPWMB1                   0X6U

/* PIN F18, PADBZ functionality */
#define PINF18_PADBZ                          0XCCU
#define PINF18_PADBZ_RCSS_GPIO_51             0X0U
#define PINF18_PADBZ_MII_RXER                 0X1U
#define PINF18_PADBZ_RMII_RXER                0X2U
#define PINF18_PADBZ_I2CA_SCL                 0X3U
#define PINF18_PADBZ_RCSS_MCASPA_DAT1         0X4U
#define PINF18_PADBZ_EPWMC1                   0X6U

/* PIN J18, PADCA functionality */
#define PINJ18_PADCA                          0XD0U
#define PINJ18_PADCA_RCSS_GPIO_52             0X0U
#define PINJ18_PADCA_MII_TXEN                 0X1U
#define PINJ18_PADCA_RMII_TXEN                0X2U
#define PINJ18_PADCA_RGMII_TCTL               0X3U
#define PINJ18_PADCA_RCSS_MCASPA_DAT0         0X4U
#define PINJ18_PADCA_EPWMA0                   0X6U

/* PIN J17, PADCB functionality */
#define PINJ17_PADCB                          0XD4U
#define PINJ17_PADCB_RCSS_GPIO_53             0X0U
#define PINJ17_PADCB_MII_RXDV                 0X1U
#define PINJ17_PADCB_RGMII_RCTL               0X3U
#define PINJ17_PADCB_RCSS_MCASPA_FSR          0X4U
#define PINJ17_PADCB_UARTB_RX                 0X5U
#define PINJ17_PADCB_EPWMB0                   0X6U

/* PIN K18, PADCC functionality */
#define PINK18_PADCC                          0XD8U
#define PINK18_PADCC_RCSS_GPIO_54             0X0U
#define PINK18_PADCC_MII_TXD3                 0X1U
#define PINK18_PADCC_RGMII_TD3                0X3U
#define PINK18_PADCC_RCSS_MCASPA_ACLKR        0X4U
#define PINK18_PADCC_UARTB_TX                 0X5U
#define PINK18_PADCC_EPWMC0                   0X6U

/* PIN K16, PADCD functionality */
#define PINK16_PADCD                          0XDCU
#define PINK16_PADCD_RCSS_GPIO_55             0X0U
#define PINK16_PADCD_MII_TXD2                 0X1U
#define PINK16_PADCD_RGMII_TD2                0X3U
#define PINK16_PADCD_RCSS_MCASPA_FSX          0X4U

/* PIN L17, PADCE functionality */
#define PINL17_PADCE                          0XE0U
#define PINL17_PADCE_RCSS_GPIO_56             0X0U
#define PINL17_PADCE_MII_TXD1                 0X1U
#define PINL17_PADCE_RMII_TXD1                0X2U
#define PINL17_PADCE_RGMII_TD1                0X3U
#define PINL17_PADCE_RCSS_MCASPA_ACLKX        0X4U

/* PIN L18, PADCF functionality */
#define PINL18_PADCF                          0XE4U
#define PINL18_PADCF_RCSS_GPIO_57             0X0U
#define PINL18_PADCF_MII_TXD0                 0X1U
#define PINL18_PADCF_RMII_TXD0                0X2U
#define PINL18_PADCF_RGMII_TD0                0X3U
#define PINL18_PADCF_RCSS_MCASPA_AHCLKX       0X4U

/* PIN K19, PADCG functionality */
#define PINK19_PADCG                          0XE8U
#define PINK19_PADCG_RCSS_GPIO_58             0X0U
#define PINK19_PADCG_MII_TXCLK                0X1U
#define PINK19_PADCG_RGMII_TCLK               0X3U
#define PINK19_PADCG_RCSS_MCASPB_AHCLKX       0X4U
#define PINK19_PADCG_RCSS_I2CA_SDA            0X5U

/* PIN M19, PADCH functionality */
#define PINM19_PADCH                          0XECU
#define PINM19_PADCH_RCSS_GPIO_59             0X0U
#define PINM19_PADCH_MII_RXCLK                0X1U
#define PINM19_PADCH_RGMII_RCLK               0X3U
#define PINM19_PADCH_RCSS_MCASPB_AHCLKR       0X4U
#define PINM19_PADCH_RCSS_I2CA_SCL            0X5U

/* PIN L19, PADCI functionality */
#define PINL19_PADCI                          0XF0U
#define PINL19_PADCI_RCSS_GPIO_60             0X0U
#define PINL19_PADCI_MII_RXD3                 0X1U
#define PINL19_PADCI_RGMII_RD3                0X3U
#define PINL19_PADCI_RCSS_MCASPB_ACLKX        0X4U
#define PINL19_PADCI_RCSS_I2CB_SDA            0X5U

/* PIN M18, PADCJ functionality */
#define PINM18_PADCJ                          0XF4U
#define PINM18_PADCJ_RCSS_GPIO_61             0X0U
#define PINM18_PADCJ_MII_RXD2                 0X1U
#define PINM18_PADCJ_RGMII_RD2                0X3U
#define PINM18_PADCJ_RCSS_MCASPB_FSX          0X4U
#define PINM18_PADCJ_RCSS_I2CB_SCL            0X5U

/* PIN N19, PADCK functionality */
#define PINN19_PADCK                          0XF8U
#define PINN19_PADCK_RCSS_GPIO_62             0X0U
#define PINN19_PADCK_MII_RXD1                 0X1U
#define PINN19_PADCK_RMII_RXD1                0X2U
#define PINN19_PADCK_RGMII_RD1                0X3U
#define PINN19_PADCK_RCSS_MCASPB_ACLKR        0X4U

/* PIN P18, PADCL functionality */
#define PINP18_PADCL                          0XFCU
#define PINP18_PADCL_RCSS_GPIO_63             0X0U
#define PINP18_PADCL_MII_RXD0                 0X1U
#define PINP18_PADCL_RMII_RXD0                0X2U
#define PINP18_PADCL_RGMII_RD0                0X3U
#define PINP18_PADCL_RCSS_MCASPB_FSR          0X4U

/* PIN P19, PADCM functionality */
#define PINP19_PADCM                          0X100U
#define PINP19_PADCM_GPIO_30                  0X0U
#define PINP19_PADCM_MDIO_DATA                0X1U
#define PINP19_PADCM_RCSS_MCASPB_DAT0         0X4U

/* PIN R19, PADCN functionality */
#define PINR19_PADCN                          0X104U
#define PINR19_PADCN_GPIO_31                  0X0U
#define PINR19_PADCN_MDIO_CLK                 0X1U
#define PINR19_PADCN_RCSS_MCASPB_DAT1         0X4U

/* PIN R18, PADCO functionality */
#define PINR18_PADCO                          0X108U
#define PINR18_PADCO_RCSS_GPIO_32             0X0U
#define PINR18_PADCO_RCSS_MIBSPIA_MOSI        0X1U
#define PINR18_PADCO_RCSS_I2CA_SDA            0X2U
#define PINR18_PADCO_MIBSPIA_MOSI             0X5U

/* PIN R17, PADCP functionality */
#define PINR17_PADCP                          0X10CU
#define PINR17_PADCP_RCSS_GPIO_33             0X0U
#define PINR17_PADCP_RCSS_MIBSPIA_MISO        0X1U
#define PINR17_PADCP_RCSS_I2CA_SCL            0X2U
#define PINR17_PADCP_MIBSPIA_MISO             0X5U

/* PIN T18, PADCQ functionality */
#define PINT18_PADCQ                          0X110U
#define PINT18_PADCQ_RCSS_GPIO_34             0X0U
#define PINT18_PADCQ_RCSS_MIBSPIA_CLK         0X1U
#define PINT18_PADCQ_RCSS_I2CB_SDA            0X2U
#define PINT18_PADCQ_MIBSPIA_CLK              0X5U

/* PIN T19, PADCR functionality */
#define PINT19_PADCR                          0X114U
#define PINT19_PADCR_RCSS_GPIO_35             0X0U
#define PINT19_PADCR_RCSS_MIBSPIA_CS0         0X1U
#define PINT19_PADCR_RCSS_I2CB_SCL            0X2U
#define PINT19_PADCR_MIBSPIA_CS0              0X5U

/* PIN U18, PADCS functionality */
#define PINU18_PADCS                          0X118U
#define PINU18_PADCS_RCSS_GPIO_36             0X0U
#define PINU18_PADCS_RCSS_MIBSPIA_CS1         0X1U
#define PINU18_PADCS_GPIO_2                   0X2U
#define PINU18_PADCS_GPIO_8                   0X3U
#define PINU18_PADCS_MIBSPIA_HOSTIRQ          0X5U
#define PINU18_PADCS_MIBSPIB_CS2              0X6U
#define PINU18_PADCS_RCSS_GPIO_34             0X7U
#define PINU18_PADCS_RCSS_GPIO_40             0XAU

/* PIN U19, PADCT functionality */
#define PINU19_PADCT                          0X11CU
#define PINU19_PADCT_RCSS_GPIO_37             0X0U
#define PINU19_PADCT_RCSS_MIBSPIB_MOSI        0X1U
#define PINU19_PADCT_RCSS_I2CA_SDA            0X2U
#define PINU19_PADCT_CPTS0_HW1TSPUSH          0X3U
#define PINU19_PADCT_MIBSPIB_MOSI             0X5U

/* PIN V18, PADCU functionality */
#define PINV18_PADCU                          0X120U
#define PINV18_PADCU_RCSS_GPIO_38             0X0U
#define PINV18_PADCU_RCSS_MIBSPIB_MISO        0X1U
#define PINV18_PADCU_RCSS_I2CA_SCL            0X2U
#define PINV18_PADCU_CPTS0_HW2TSPUSH          0X3U
#define PINV18_PADCU_MIBSPIB_MISO             0X5U

/* PIN V19, PADCV functionality */
#define PINV19_PADCV                          0X124U
#define PINV19_PADCV_RCSS_GPIO_39             0X0U
#define PINV19_PADCV_RCSS_MIBSPIB_CLK         0X1U
#define PINV19_PADCV_RCSS_I2CB_SDA            0X2U
#define PINV19_PADCV_CPTS0_TS_SYNC            0X3U
#define PINV19_PADCV_MIBSPIB_CLK              0X5U

/* PIN U17, PADCW functionality */
#define PINU17_PADCW                          0X128U
#define PINU17_PADCW_RCSS_GPIO_40             0X0U
#define PINU17_PADCW_RCSS_MIBSPIB_CS0         0X1U
#define PINU17_PADCW_RCSS_I2CB_SCL            0X2U
#define PINU17_PADCW_CPTS0_TS_COMP            0X3U
#define PINU17_PADCW_RCSS_MCASPC_DAT5         0X4U
#define PINU17_PADCW_MIBSPIB_CS0              0X5U

/* PIN W18, PADCX functionality */
#define PINW18_PADCX                          0X12CU
#define PINW18_PADCX_RCSS_GPIO_41             0X0U
#define PINW18_PADCX_RCSS_MIBSPIB_CS1         0X1U
#define PINW18_PADCX_CPTS0_TS_GENF            0X3U
#define PINW18_PADCX_RCSS_MCASPC_DAT4         0X4U
#define PINW18_PADCX_MIBSPIB_CS1              0X5U
#define PINW18_PADCX_GPIO_3                   0X6U
#define PINW18_PADCX_GPIO_9                   0X7U
#define PINW18_PADCX_RCSS_GPIO_35             0XAU

/* PIN V17, PADCY functionality */
#define PINV17_PADCY                          0X130U
#define PINV17_PADCY_RCSS_GPIO_42             0X0U
#define PINV17_PADCY_CPTS0_TS_GENF            0X1U
#define PINV17_PADCY_HW_SYNC_FE2              0X2U
#define PINV17_PADCY_HW_SYNC_FE1              0X3U
#define PINV17_PADCY_RCSS_MCASPC_DAT3         0X4U

/* PIN W17, PADCZ functionality */
#define PINW17_PADCZ                          0X134U
#define PINW17_PADCZ_RCSS_GPIO_43             0X0U
#define PINW17_PADCZ_CPTS0_TS_COMP            0X1U
#define PINW17_PADCZ_HW_SYNC_FE1              0X2U
#define PINW17_PADCZ_HW_SYNC_FE2              0X3U
#define PINW17_PADCZ_RCSS_MCASPC_DAT2         0X4U

/* PIN U3, PADDA functionality */
#define PINU3_PADDA                           0X138U
#define PINU3_PADDA_RCSS_GPIO_44              0X0U
#define PINU3_PADDA_CPTS0_TS_SYNC             0X1U
#define PINU3_PADDA_UARTB_TX                  0X4U
#define PINU3_PADDA_UARTA_RX                  0X5U
#define PINU3_PADDA_DSS_UARTA_TX              0X6U

/* PIN W2, PADDB functionality */
#define PINW2_PADDB                           0X13CU
#define PINW2_PADDB_RCSS_GPIO_45              0X0U
#define PINW2_PADDB_CPTS0_HW2TSPUSH           0X1U
#define PINW2_PADDB_UARTB_RX                  0X4U
#define PINW2_PADDB_UARTA_TX                  0X5U
#define PINW2_PADDB_DSS_UARTA_RX              0X6U

/* PIN J19, PADDC functionality */
#define PINJ19_PADDC                          0X140U
#define PINJ19_PADDC_RCSS_GPIO_46             0X0U
#define PINJ19_PADDC_CPTS0_HW1TSPUSH          0X1U
#define PINJ19_PADDC_DSS_UARTA_TX             0X4U
#define PINJ19_PADDC_RCSS_UARTA_RX            0X5U
#define PINJ19_PADDC_UARTA_RX                 0X6U

/* PIN H19, PADDD functionality */
#define PINH19_PADDD                          0X144U
#define PINH19_PADDD_RCSS_GPIO_47             0X0U
#define PINH19_PADDD_DSS_UARTA_RX             0X1U
#define PINH19_PADDD_RCSS_UARTA_TX            0X5U
#define PINH19_PADDD_UARTA_TX                 0X6U

/* PIN V9, PADDE functionality */
#define PINV9_PADDE                           0X148U
#define PINV9_PADDE_GPIO_0                    0X0U
#define PINV9_PADDE_DSS_UARTA_TX              0X1U
#define PINV9_PADDE_EPWMB_SYNCI               0X3U
#define PINV9_PADDE_FE1_REFCLK                0X4U
#define PINV9_PADDE_UARTA_TX                  0X5U
#define PINV9_PADDE_UARTB_TX                  0X6U
#define PINV9_PADDE_RCSS_GPIO_32              0XCU

/* PIN J1, PADDF functionality */
#define PINJ1_PADDF                           0X14CU
#define PINJ1_PADDF_GPIO_1                    0X0U
#define PINJ1_PADDF_XREF_CLK0                 0X1U
#define PINJ1_PADDF_FE2_REFCLK                0X4U
#define PINJ1_PADDF_MCU_CLKOUT                0X6U
#define PINJ1_PADDF_RCSS_GPIO_33              0XCU

/* PIN K2, PADDG functionality */
#define PINK2_PADDG                           0X150U
#define PINK2_PADDG_GPIO_2                    0X0U
#define PINK2_PADDG_XREF_CLK1                 0X1U
#define PINK2_PADDG_RCSS_ECAPA_CAPIN_PWMO     0X3U
#define PINK2_PADDG_PMIC_CLKOUT               0X7U
#define PINK2_PADDG_RCSS_GPIO_34              0XCU

/* PIN H18, PADDH functionality */
#define PINH18_PADDH                          0X154U
#define PINH18_PADDH_GPIO_3                   0X0U
#define PINH18_PADDH_OBS_CLKOUT               0X1U
#define PINH18_PADDH_RCSS_ATL_CLK0            0X2U
#define PINH18_PADDH_RCSS_I2CB_SDA            0X4U
#define PINH18_PADDH_EPWMA1                   0X5U
#define PINH18_PADDH_RCSS_UARTA_RTS           0X9U
#define PINH18_PADDH_MIBSPIA_MOSI             0XAU
#define PINH18_PADDH_RCSS_GPIO_35             0XCU

/* PIN G17, PADDI functionality */
#define PING17_PADDI                          0X158U
#define PING17_PADDI_GPIO_4                   0X0U
#define PING17_PADDI_HW_SYNC_FE1              0X1U
#define PING17_PADDI_CPTS0_TS_GENF            0X2U
#define PING17_PADDI_RCSS_ATL_CLK1            0X3U
#define PING17_PADDI_RCSS_I2CB_SCL            0X4U
#define PING17_PADDI_EPWMB1                   0X5U
#define PING17_PADDI_EPWMB0                   0X6U
#define PING17_PADDI_HW_SYNC_FE2              0X7U
#define PING17_PADDI_OBS_CLKOUT               0X8U
#define PING17_PADDI_RCSS_UARTA_CTS           0X9U
#define PING17_PADDI_MIBSPIA_MISO             0XAU
#define PING17_PADDI_RCSS_GPIO_36             0XCU

/* PIN G19, PADDJ functionality */
#define PING19_PADDJ                          0X15CU
#define PING19_PADDJ_GPIO_5                   0X0U
#define PING19_PADDJ_HW_SYNC_FE2              0X1U
#define PING19_PADDJ_CPTS0_TS_COMP            0X2U
#define PING19_PADDJ_EPWMB1                   0X3U
#define PING19_PADDJ_RCSS_ECAPA_CAPIN_PWMO    0X4U
#define PING19_PADDJ_RCSS_I2CA_SDA            0X5U
#define PING19_PADDJ_UARTB_TX                 0X6U
#define PING19_PADDJ_HW_SYNC_FE1              0X7U
#define PING19_PADDJ_MIBSPIA_CLK              0XAU
#define PING19_PADDJ_RCSS_GPIO_37             0XCU

/* PIN F19, PADDK functionality */
#define PINF19_PADDK                          0X160U
#define PINF19_PADDK_GPIO_6                   0X0U
#define PINF19_PADDK_EPWMA_SYNCI              0X1U
#define PINF19_PADDK_HW_SYNC_FE1              0X3U
#define PINF19_PADDK_EPWMA0                   0X4U
#define PINF19_PADDK_RCSS_I2CA_SCL            0X5U
#define PINF19_PADDK_UARTB_RX                 0X6U
#define PINF19_PADDK_CPTS0_TS_GENF            0X7U
#define PINF19_PADDK_HW_SYNC_FE2              0X9U
#define PINF19_PADDK_MIBSPIA_CS0              0XAU
#define PINF19_PADDK_RCSS_GPIO_38             0XCU

/* PIN G18, PADDL functionality */
#define PING18_PADDL                          0X164U
#define PING18_PADDL_GPIO_7                   0X0U
#define PING18_PADDL_EPWMA_SYNCO              0X1U
#define PING18_PADDL_EPWMC1                   0X2U
#define PING18_PADDL_HW_SYNC_FE2              0X3U
#define PING18_PADDL_EPWMB0                   0X4U
#define PING18_PADDL_RCSS_I2CB_SDA            0X5U
#define PING18_PADDL_UARTA_RX                 0X6U
#define PING18_PADDL_CPTS0_TS_COMP            0X7U
#define PING18_PADDL_RCSS_ECAPA_SYNCIN        0X8U
#define PING18_PADDL_HW_SYNC_FE1              0X9U
#define PING18_PADDL_MIBSPIA_HOSTIRQ          0XAU
#define PING18_PADDL_RCSS_GPIO_39             0XCU

/* PIN B3, PADDM functionality */
#define PINB3_PADDM                           0X168U
#define PINB3_PADDM_GPIO_8                    0X0U
#define PINB3_PADDM_FE1_REFCLK                0X1U
#define PINB3_PADDM_EPWMA_SYNCO               0X2U
#define PINB3_PADDM_EPWMB_SYNCI               0X3U
#define PINB3_PADDM_EPWMC0                    0X4U
#define PINB3_PADDM_RCSS_I2CB_SCL             0X5U
#define PINB3_PADDM_UARTA_TX                  0X6U
#define PINB3_PADDM_CPTS0_TS_SYNC             0X7U
#define PINB3_PADDM_RCSS_ECAPA_SYNCOUT        0X8U
#define PINB3_PADDM_RCSS_GPIO_40              0XCU

/* PIN B19, PADDN functionality */
#define PINB19_PADDN                          0X16CU
#define PINB19_PADDN_GPIO_9                   0X0U
#define PINB19_PADDN_FE2_REFCLK               0X1U
#define PINB19_PADDN_RCSS_UARTA_TX            0X2U
#define PINB19_PADDN_EPWMB_SYNCO              0X3U
#define PINB19_PADDN_EPWMA1                   0X4U
#define PINB19_PADDN_DSS_UARTA_TX             0X6U
#define PINB19_PADDN_CPTS0_HW2TSPUSH          0X7U
#define PINB19_PADDN_RCSS_MCASPA_AHCLKX       0X8U
#define PINB19_PADDN_RCSS_ATL_CLK0            0XBU
#define PINB19_PADDN_RCSS_GPIO_41             0XCU

/* PIN B18, PADDO functionality */
#define PINB18_PADDO                          0X170U
#define PINB18_PADDO_GPIO_10                  0X0U
#define PINB18_PADDO_RCSS_UARTA_RX            0X2U
#define PINB18_PADDO_EPWMC_SYNCI              0X3U
#define PINB18_PADDO_EPWMB1                   0X4U
#define PINB18_PADDO_DSS_UARTA_RX             0X6U
#define PINB18_PADDO_CPTS0_HW1TSPUSH          0X7U
#define PINB18_PADDO_RCSS_MCASPA_ACLKX        0X8U
#define PINB18_PADDO_RCSS_GPIO_42             0XCU

/* PIN C17, PADDP functionality */
#define PINC17_PADDP                          0X174U
#define PINC17_PADDP_GPIO_11                  0X0U
#define PINC17_PADDP_RCSS_UARTA_RTS           0X2U
#define PINC17_PADDP_EPWMC_SYNCO              0X3U
#define PINC17_PADDP_EPWMC1                   0X4U
#define PINC17_PADDP_I2CA_SDA                 0X5U
#define PINC17_PADDP_UARTB_TX                 0X6U
#define PINC17_PADDP_RCSS_MCASPA_FSX          0X8U
#define PINC17_PADDP_RCSS_GPIO_43             0XCU

/* PIN A18, PADDQ functionality */
#define PINA18_PADDQ                          0X178U
#define PINA18_PADDQ_GPIO_12                  0X0U
#define PINA18_PADDQ_I2CA_SCL                 0X1U
#define PINA18_PADDQ_RCSS_UARTA_CTS           0X2U
#define PINA18_PADDQ_HW_SYNC_FE1              0X3U
#define PINA18_PADDQ_RCSS_ECAPA_CAPIN_PWMO    0X4U
#define PINA18_PADDQ_CPTS0_TS_GENF            0X5U
#define PINA18_PADDQ_UARTB_RX                 0X6U
#define PINA18_PADDQ_RCSS_ECAPA_CAPIN_PWMO    0X7U
#define PINA18_PADDQ_RCSS_MCASPA_ACLKR        0X8U
#define PINA18_PADDQ_RS232_RX                 0XBU
#define PINA18_PADDQ_RCSS_GPIO_44             0XCU

/* PIN B17, PADDR functionality */
#define PINB17_PADDR                          0X17CU
#define PINB17_PADDR_GPIO_13                  0X0U
#define PINB17_PADDR_I2CA_SDA                 0X1U
#define PINB17_PADDR_CPTS0_TS_COMP            0X2U
#define PINB17_PADDR_HW_SYNC_FE2              0X3U
#define PINB17_PADDR_RCSS_UARTA_TX            0X4U
#define PINB17_PADDR_UARTA_TX                 0X5U
#define PINB17_PADDR_UARTB_TX                 0X6U
#define PINB17_PADDR_DSS_UARTA_TX             0X7U
#define PINB17_PADDR_RCSS_MCASPA_FSR          0X8U
#define PINB17_PADDR_RS232_TX                 0XBU
#define PINB17_PADDR_RCSS_GPIO_45             0XCU

/* PIN A17, PADDS functionality */
#define PINA17_PADDS                          0X180U
#define PINA17_PADDS_GPIO_14                  0X0U
#define PINA17_PADDS_RCSS_UARTA_TX            0X2U
#define PINA17_PADDS_RCSS_I2CB_SDA            0X3U
#define PINA17_PADDS_RCSS_MCASPA_DAT8         0X7U
#define PINA17_PADDS_RCSS_MCASPA_DAT0         0X8U
#define PINA17_PADDS_RCSS_GPIO_46             0XCU

/* PIN B16, PADDT functionality */
#define PINB16_PADDT                          0X184U
#define PINB16_PADDT_GPIO_15                  0X0U
#define PINB16_PADDT_RCSS_UARTA_RX            0X2U
#define PINB16_PADDT_RCSS_I2CB_SCL            0X3U
#define PINB16_PADDT_RCSS_MCASPA_DAT9         0X7U
#define PINB16_PADDT_RCSS_MCASPA_DAT1         0X8U
#define PINB16_PADDT_RCSS_GPIO_47             0XCU

/* PIN C15, PADDU functionality */
#define PINC15_PADDU                          0X188U
#define PINC15_PADDU_GPIO_16                  0X0U
#define PINC15_PADDU_RCSS_MCASPA_DAT10        0X7U
#define PINC15_PADDU_RCSS_MCASPA_DAT2         0X8U
#define PINC15_PADDU_RCSS_GPIO_48             0XCU

/* PIN A16, PADDV functionality */
#define PINA16_PADDV                          0X18CU
#define PINA16_PADDV_GPIO_17                  0X0U
#define PINA16_PADDV_RCSS_MCASPA_DAT11        0X7U
#define PINA16_PADDV_RCSS_MCASPA_DAT3         0X8U
#define PINA16_PADDV_RCSS_GPIO_49             0XCU

/* PIN B15, PADDW functionality */
#define PINB15_PADDW                          0X190U
#define PINB15_PADDW_GPIO_18                  0X0U
#define PINB15_PADDW_RCSS_MCASPA_DAT12        0X7U
#define PINB15_PADDW_RCSS_MCASPA_DAT4         0X8U
#define PINB15_PADDW_RCSS_GPIO_50             0XCU

/* PIN A15, PADDX functionality */
#define PINA15_PADDX                          0X194U
#define PINA15_PADDX_GPIO_19                  0X0U
#define PINA15_PADDX_RCSS_I2CA_SDA            0X3U
#define PINA15_PADDX_RCSS_MCASPA_DAT13        0X7U
#define PINA15_PADDX_RCSS_MCASPA_DAT5         0X8U
#define PINA15_PADDX_RCSS_GPIO_51             0XCU

/* PIN B14, PADDY functionality */
#define PINB14_PADDY                          0X198U
#define PINB14_PADDY_GPIO_20                  0X0U
#define PINB14_PADDY_RCSS_I2CA_SCL            0X3U
#define PINB14_PADDY_RCSS_MCASPA_DAT14        0X7U
#define PINB14_PADDY_RCSS_MCASPA_DAT6         0X8U
#define PINB14_PADDY_RCSS_GPIO_52             0XCU

/* PIN C13, PADDZ functionality */
#define PINC13_PADDZ                          0X19CU
#define PINC13_PADDZ_GPIO_21                  0X0U
#define PINC13_PADDZ_RCSS_ECAPA_CAPIN_PWMO    0X4U
#define PINC13_PADDZ_RCSS_MCASPA_DAT15        0X7U
#define PINC13_PADDZ_RCSS_MCASPA_DAT7         0X8U
#define PINC13_PADDZ_RCSS_GPIO_53             0XCU


/* General pin configurations */
#define PIN_SLEW_BITPOS                 10U
#define PIN_SLEW_CONTROL_MASK          (~(uint32)((uint32)0x1U << PIN_SLEW_BITPOS))
#define SLEW_HIGH                      ((uint32)((uint32)0x1U << PIN_SLEW_BITPOS))
#define SLEW_LOW                       ((uint32)((uint32)0x0U << PIN_SLEW_BITPOS))

#define PIN_PULL_BITPOS                 0x8U
#define PIN_PULL_SELECT_MASK            (~(uint32)((uint32)0x3U << PIN_PULL_BITPOS))
#define PULLUP_EN                       ((uint32)((uint32)0x2U << PIN_PULL_BITPOS))
#define PULLDOWN_EN                     ((uint32)((uint32)0x0U << PIN_PULL_BITPOS))
#define DISABLE_PULLS                   ((uint32)((uint32)0x1U << PIN_PULL_BITPOS))

#define OUTPUT_EN_BITPOS                0x7U
#define PIN_OUTEN_MASK                  (~(uint32)((uint32)0x1U << OUTPUT_EN_BITPOS))
#define OUTPUT_EN                       ((uint32)((uint32)0x1U << OUTPUT_EN_BITPOS))
#define OUTPUT_DIS                      ((uint32)((uint32)0x0U << OUTPUT_EN_BITPOS))
#define OUTEN_RETAIN_HW_CTRL            0x2U

#define OUTEN_OVRRIDE_BITPOS            0x6U
#define PIN_OUTEN_OVRRIDE_MASK          (~(uint32)((uint32)0x1U << OUTEN_OVRRIDE_BITPOS))
#define OUTEN_OVRRIDE_EN                ((uint32)((uint32)0x1U << OUTEN_OVRRIDE_BITPOS))


#define INPUT_EN_BITPOS                 0x5U
#define PIN_INPUTEN_MASK                (~(uint32)((uint32)0x1U << INPUT_EN_BITPOS))
#define INPUT_EN                        ((uint32)((uint32)0x1U << INPUT_EN_BITPOS))
#define INPUT_DIS                       ((uint32)((uint32)0x0U << INPUT_EN_BITPOS))
#define INPEN_RETAIN_HW_CTRL            0x2U

#define INPEN_OVRRIDE_BITPOS            0x4U
#define PIN_INPEN_OVRRIDE_MASK          (~(uint32)((uint32)0x1U << INPEN_OVRRIDE_BITPOS))
#define INPEN_OVRRIDE_EN                ((uint32)((uint32)0x1U << INPEN_OVRRIDE_BITPOS))


#define PIN_FUNCTION_SEL_MASK          (~(uint32)((uint32)0xFU))

/* Setup the pin direction */
#define PIN_OUTPUT                     0x1U
#define PIN_INPUT                      0x2U
#define PIN_INOUT                      0x3U

/**
 *  @defgroup PINMUX PINMUX
 *  @brief Peripheral IO Muxing Interface Module.
 *
 *  The peripgeral IO muxing module is responsible to assign a HW signal functionality to the
 *  pins at the device boundary.
 *
 *    Related Files
 *   - reg_pinmux.h
 *   - pinmux.h
 *   - pinmux.c
  *  @addtogroup PINMUX
 *  @{
 */

/* Pinmux Interface Functions */
sint32 pinConfigOverrideCtrl(uint32 pin, uint32 outputCtrl, uint32 inputCtrl);
sint32 pinConfigPulls(uint32 pin, uint32 pullVal);
sint32 pinConfigSlew(uint32 pin, uint32 slewVal);
sint32 pinSelectFunc(uint32 pin, uint32 func);
void pinmuxUnlock(pinMuxBase_t *pinMuxRegp);
void pinmuxLock(pinMuxBase_t *pinMuxRegp);
void pinmuxInit(void);
void pinmuxLogger(void);
void pinmuxUartA(void);

/**@}*/
#ifdef __cplusplus
}
#endif

#endif
