/* ======================================================================
 *   Copyright (C) 2022 Texas Instruments Incorporated
 *
 *   All rights reserved. Property of Texas Instruments Incorporated.
 *   Restricted rights to use, duplicate or disclose this code are
 *   granted through contract.
 *
 *   The program may not be used without the written permission
 *   of Texas Instruments Incorporated or against the terms and conditions
 *   stipulated in the agreement under which this program has been
 *   supplied.
 * ==================================================================== */

/**
 *  \file     Eth_GeneralTypes.h
 *
 *  \brief    This file contains general Eth type declarations.
 *
 */

/**
 *  \ingroup MCAL_ETH_API
 *  @{
 */

/*
 * Below are the global requirements which are met by this Eth
 * driver which can't be mapped to a particular source ID
 */
/* Requirements : SWS_Eth_00026, SWS_Eth_00149, SWS_EthTrcv_00096*/

#ifndef ETH_GENERALTYPES_H_
#define ETH_GENERALTYPES_H_

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include "ComStack_Types.h"
#include "Eth_Cfg.h"

#ifdef __cplusplus
extern "C"
{
#endif

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/**
 *  \brief This type defines the Ethernet frame type used in the Ethernet
 *  frame header
 */
/* Requirements : SWS_Eth_00160 */
typedef uint16 Eth_FrameType;

/**
 *  \brief This type defines the Ethernet data type used for data
 *  transmission
 */
/* Requirements : SWS_Eth_00161 */
typedef uint32 Eth_DataType;

/** \brief Ethernet buffer identifier type */
/* Requirements : SWS_Eth_00175 */
typedef uint32 Eth_BufIdxType;

/*
 * Pre-Pad Packet Data Offset
 *
 *   The TCP/IP stack library requires that every packet device
 *   include enough L2 header room for all supported headers. In
 *   order to support PPPoE, this requires a 22 byte L2 header.
 *   Thus, since standard Ethernet is only 14 bytes, we must add
 *   on an additional 8 byte offset, or PPPoE can not function
 *   with our driver.
*/
#define ETH_PKT_PREPAD                  ((uint16)8U)

/** \brief MAC address length in bytes. */
#define ETH_MAC_ADDR_LEN                ((uint16) 6U)
/** \brief Total octets in header.  */
#define ETH_HLEN                        ((uint16) 14U)
/** \brief Min. octets in frame sans FCS */
#define ETH_ZLEN                        ((uint16) 60U)
/** \brief Max. octets in payload   */
#define ETH_DATA_LEN                    ((uint16) 1500U)
/** \brief Max. octets in payload   */
#define ETH_VLAN_TAG_SIZE               ((uint16) 4U)

/*
 * Requirements : SWS_Eth_00218 The Ethernet Driver shall ensure that the base
 * addresses of all reception and transmission buffers fulfill the memory
 * alignment requirements for all AUTOSAR data types of the respective platform.
 */
#define ETH_MAX_FRAME_LEN                   (1536U)

/**
 *  \brief Maximum number of CPSW ports supported by the controller.
 */
#define ETH_CPSW_MAX_PORT               ((uint32) 1U)

/** \brief Typedef for cache flush function pointer */
typedef P2FUNC (void, ETH_APPL_CODE, Eth_CacheFlushType)(
    P2VAR(uint8, AUTOMATIC, ETH_APPL_DAT)BufPtr,
    uint32 LenByte);

/** \brief Typedef for cache invalidate function pointer */
typedef P2FUNC (void, ETH_APPL_CODE, Eth_CacheInvalidateType)(
    P2VAR(uint8, AUTOMATIC, ETH_APPL_DAT)BufPtr,
    uint32 LenByte);


/**
 *  \brief List of macros for default config parameters.
 *         This can be used by application as reference to pass config to driver
 *         functions.
 */

/* CPTS related macros */
/* 266 MHz by default (L3 Frequency) */
#define ETH_CPSW_CPTSCFG_CPTSINPUTFREQ            (125000000U)

/* CPDMA related macros */
#define ETH_CPSW_DEFAULT_PACING_MAINCLKFREQ       (125000000U)

#define ETH_CPSW_DEFAULT_MDIOBUSFREQ              (2200000U)
#define ETH_CPSW_DEFAULT_MDIOCLOCKFREQ            (200000000U)
#define ETH_CPSW_DEFAULT_MAINCLKFREQ              (125000000U)

/* prescalar divides down to 1ms interval*/
#define ETH_CPSW_DEFAULT_ALEPRESCALE       (ETH_CPSW_DEFAULT_MAINCLKFREQ / \
                                              1000U)

/* ALE time out value in ms */
#define ETH_CPSW_ALE_AGE_OUT_TIME_IN_MS                        (300000U)

#define ETH_CPSW_MAC_CONFIG_MODEFLG_TXFLOWCNTL        (uint32) (0x08000U)
/**< Enable tx flow control                                                 */
#define ETH_CPSW_MAC_CONFIG_MODEFLG_RXBUFFERFLOWCNTL  (uint32) (0x10000U)
/**< Enable rx buffer flow control                                          */

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */

/* [SWS_Eth_91002 */
typedef struct
{
	uint32 RxStatsDropEvents;
	uint32 RxStatsOctets;
	uint32 RxStatsPkts;
	uint32 RxStatsBroadcastPkts;
	uint32 RxStatsMulticastPkts;
	uint32 RxStatsCrcAlignErrors;
	uint32 RxStatsUndersizePkts;
	uint32 RxStatsOversizePkts;
	uint32 RxStatsFragments;
	uint32 RxStatsJabbers;
	uint32 RxStatsCollisions;
	uint32 RxStatsPkts64Octets;
	uint32 RxStatsPkts65to127Octets;
	uint32 RxStatsPkts128to255Octets;
	uint32 RxStatsPkts256to511Octets;
	uint32 RxStatsPkts512to1023Octets;
	uint32 RxStatsPkts1024to1518Octets;
	uint32 RxUnicastFrames;
}Eth_RxStatsType;

/* [SWS_Eth_91004] */
typedef struct
{
	uint32 TxDroppedNoErrorPkts;
	uint32 TxDroppedErrorPkts;
	uint32 TxDeferredTrans;
	uint32 TxSingleCollision;
	uint32 TxMultipleCollision;
	uint32 TxLateCollision;
	uint32 TxExcessiveCollison;
}Eth_TxErrorCounterValuesType;

/* [SWS_Eth_91003] */
typedef struct
{
	uint32 TxNumberOfOctets;
	uint32 TxNUcastPkts;
	uint32 TxUniCastPkts;
}Eth_TxStatsType;

/* [SWS_Eth_91007] */
typedef struct
{
	uint32 DropPktBufOverrun;
	uint32 DropPktCrc;
	uint32 UndersizePkt;
	uint32 OversizePkt;
	uint32 AlgnmtErr;
	uint32 SqeTestErr;
	uint32 DiscInbdPkt;
	uint32 ErrInbdPkt;
	uint32 DiscOtbdPkt;
	uint32 ErrOtbdPkt;
	uint32 SnglCollPkt;
	uint32 MultCollPkt;
	uint32 DfrdPkt;
	uint32 LatCollPkt;
	uint32 HwDepCtr0;
	uint32 HwDepCtr1;
	uint32 HwDepCtr2;
	uint32 HwDepCtr3;
}Eth_CounterType;

/**
 * \brief  CPTS Ethernet Message Type Enumeration
 */
typedef enum
{
    ETH_CPTS_MESSAGE_SYNC                   = (0x1U),
    ETH_CPTS_MESSAGE_DELAY_REQ              = (0x2U),
    ETH_CPTS_MESSAGE_PDELAY_REQ             = (0x4U),
    ETH_CPTS_MESSAGE_PDELAY_RESP            = (0x8U),
    ETH_CPTS_MESSAGE_FOLLOW_UP              = (0x100U),
    ETH_CPTS_MESSAGE_DELAY_RESP             = (0x200U),
    ETH_CPTS_MESSAGE_PDELAY_RESP_FOLLOW_UP  = (0x400U),
    ETH_CPTS_MESSAGE_ANNOUNCE               = (0x800U),
    ETH_CPTS_MESSAGE_SIGNALING              = (0x1000U),
    ETH_CPTS_MESSAGE_MANAGEMENT             = (0x2000U),
    ETH_CPTS_MESSAGE_ALL                    =  0xFFFFU,
} Eth_CptsMessageCfg;


/**
 *  \brief Enum of VLAN usage type for CPTS packets
 */
typedef enum
{
    ETH_CPTS_VLAN_TYPE_NONE                 = 0x00U,
    ETH_CPTS_VLAN_TYPE_SINGLE_TAG           = 0x01U,
    ETH_CPTS_VLAN_TYPE_STACKED_TAGS         = 0x02U,
    ETH_CPTS_VLAN_TYPE_INVALID              = 0xFFFFFFFFU
} Eth_CptsVlanType;

/**
 *  \brief CPTS Module Init Configuration Structure
 *         Configuration information for the CPTS modules provided during
 *         initialization.
 */
typedef struct
{
    uint32 cptsInputFreq;
    /**< CPTS input clock frequency in Hz Ex- 266000000UL for L3 266MHz freq. */
    Eth_CptsVlanType vlanType;
    /**<  VLAN Type */
    uint32 msgTypeCfg;
    /**<  Message types on which time stamping is enabled*/
} Eth_CptsConfigType;


/** \brief ETH driver controller modes. */
/* Requirements : SWS_Eth_00158 */
typedef enum
{
    ETH_MODE_DOWN,
    /**< Controller disabled */
    ETH_MODE_ACTIVE
    /**< Controller enabled */
} Eth_ModeType;

/**
 *  \brief ETH driver status supervision used for development
 *  error detection.
 */
/* Requirements : SWS_Eth_00159 */
typedef enum
{
    ETH_STATE_UNINIT,
    /**< Driver is not yet configured */
    ETH_STATE_INIT,
    /**< Driver is configured */
} Eth_StateType;

/**
 *  \brief Used as out parameter in Eth_Receive() indicates whether
 *  a frame has been received and if so, whether more frames are available or
 *  frames got lost.
 */
/* Requirements : SWS_Eth_00162 */
typedef enum
{
    ETH_RECEIVED,
    /**< Ethernet frame has been received, no further frames available */
    ETH_NOT_RECEIVED,
    /**< Ethernet frame has not been received, no further frames available */
    ETH_RECEIVED_MORE_DATA_AVAILABLE
    /**< Ethernet frame has been received, more frames are available */
} Eth_RxStatusType;

/**
 *  \brief The Enumeration Type Eth_FilterActionType describes the action to
 *  be taklen for the MAC address given in *PhysAddrPtr.
 */
/* Requirements : SWS_Eth_00163 */
typedef enum
{
    ETH_ADD_TO_FILTER,
    /**< Add the MAC address to the filter, meaning allow reception */
    ETH_REMOVE_FROM_FILTER,
    /**< Remove the MAC address from the filter, meaning reception is blocked
     *   in the lower layer */
} Eth_FilterActionType;

/**
 *  \brief Quality information regarding the evaluated time stamp.
 *
 *   Note: Not supported on TDAxx MAC HW, the value is always Valid.
 */
/* Requirements : SWS_Eth_00177 */
typedef enum
{
    ETH_VALID,
    /**< Valid timestamp */
    ETH_INVALID,
    /**< Invalid timestamp */
    ETH_UNCERTAIN,
    /**< Uncertain timestamp */
} Eth_TimeStampQualType;

/**
 *  \brief Structure variable for expressing time stamps including relative
 *         & absolute calendar time.
 */
/* Requirements : SWS_Eth_00178 */
typedef struct
{
    uint32 nanoseconds;
    /**< Nanoseconds part of the time */
    uint32 seconds;
    /**< 32 bit LSB of the 48 bits Seconds part of the time */
    uint16 secondsHi;
    /**< 16 bit MSB of the 48 bits Seconds part of the time */
} Eth_TimeStampType;

/**
 *  \brief Structure variable to express time differences.
 */
/* Requirements : SWS_Eth_00179 */
typedef struct
{
    Eth_TimeStampType diff;
    /**< time difference */
    boolean sign;
    /**< Timestamp sign - Positive (True) / negative (False) time */
} Eth_TimeIntDiffType;

/**
 *  \brief Structure variable to express frequency ratios..
 */
/* Requirements : SWS_Eth_00180 */
typedef struct
{
    Eth_TimeIntDiffType IngressTimeStampDelta;
    /**< time difference (IngressTimeStampSync2 - IngressTimeStampSync1) */
    Eth_TimeIntDiffType OriginTimeStampDelta;
    /**< time difference (OriginTimeStampSync2[FUP2] - OriginTimeStampSync1[FUP1]) */
} Eth_RateRatioType;

/** \brief Enumerates speed configurations. */
typedef enum
{
    ETH_SPEED_10 = 0x00U,
    /**< 10 Mbps operation. */
    ETH_SPEED_100 = 0x01U,
    /**< 100 Mbps operation. */
    ETH_SPEED_1000 = 0x02U
                     /**< 1000 Mbps operation. */
} Eth_SpeedType;

/**
 *  \brief  Type/Speed/Duplex Connection Config Options
 *
 *  Connection Config Options
 *
 */
typedef enum
{
    ETH_MAC_CONN_TYPE_MII_10 = 0x00U,
    /**< MAC connection type for 10Mbps MII mode */
    ETH_MAC_CONN_TYPE_MII_100 = 0x01U,
    /**< MAC connection type for 100Mbps MII mode */
    ETH_MAC_CONN_TYPE_RMII_10 = 0x02U,
    /**< MAC connection type for 10Mbps RMII mode */
    ETH_MAC_CONN_TYPE_RMII_100 = 0x03U,
    /**< MAC connection type for 100Mbps RMII mode */
    ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF = 0x04U,
    /**< MAC connection type for forced half-duplex 100Mbps RGMII mode */
    ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL = 0x05U,
    /**< MAC connection type for forced full-duplex 100Mbps RGMII mode */
	ETH_MAC_CONN_TYPE_RGMII_FORCE_1000 = 0x06U,
    /**< MAC connection type for forced 1000Mbps RGMII mode */
    ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND = 0x07U,
    /**< MAC connection type for RGMII inband detection mode (speed determined
     *   based on received RGMII Rx clock) */
} Eth_MacConnectionType;

/** \brief Enumerates duplicity configuration modes. */
typedef enum
{
    ETH_DUPLEX_MODE_HALF = 0x00U,
    /**< Half duplex mode. */
    ETH_DUPLEX_MODE_FULL = 0x01U
                           /**< Full duplex mode. */
} Eth_DuplexModeType;

/**
 *  \brief   CPDMA Init Configuration
 *
 *  \details Configuration information for the CPDMA provided during
 *  initialization.
 *  Note: Most of CPDMA features are not implemented. Only interrupt
 *  pacing is enabled.
 */
typedef struct
{
    uint32 pacingClkFreq;
    /**< CPDMA ICLK frequency for interrupt pacing  */
    uint32 rxInterruptPacingEnabled;
    /**< Receive interrupt pacing enable flag    */
    uint32 rxInterruptsPerMsec;
    /**< Receive interrupt pacing conf  */
    uint32 txInterruptPacingEnabled;
    /**< Transmit interrupt pacing enable flag    */
    uint32 txInterruptsPerMsec;
    /**< Transmit interrupt pacing conf  */
    /**< Register control fields for DMA Control register      */
    uint32 dmaModeFlags;
    /**< Configuation Mode Flags.  */
    uint32 rxThreshCount;
    /**< Free buffer descriptors count threshold to trigger an RX_THRESH
     *  interrupt.Set to zero for no threshold interrupt enablement
     */
} Eth_CpdmaConfigType;

/**
 *  \brief MDIO Module Init Configuration
 *         Configuration information for the MDIO modules provided during
 *         initialization.
 */
typedef struct
{
    uint32 mdioBusFreq;
    /**< Bus frequency for the MII module */
    uint32 mdioClockFreq;
    /**< Clock frequency for MDIO link */
} Eth_MdioConfigType;

/** \brief Structure holding the PHY configuration .*/
typedef struct
{
    uint32 macModeFlags;
    /**< Configuation Mode Flags */
    Eth_MacConnectionType  macConnectionType;
    /**< MAC Connection Type. */
    uint8  macAddr[ETH_MAC_ADDR_LEN];
    /**< MAC address  */
} Eth_MacConfigType;

/**
 *  \brief Structure for buffer.
 */
typedef struct
{
    void  *payload;
    /**< length of this buffer */
    uint16 len;
    /**< pointer to the actual data in the buffer */
} Eth_BufType;

/**
 *  \brief Structure for port configuration.
 */
typedef struct
{
    Eth_MacConfigType macCfg;
    /**< MAC Init Configurations */
} Eth_PortConfigType;

/**
 * \brief Rate limit configuration for switch priorities on port
 *        Note: Highest priorities only can be rate limited.
 */
typedef enum
{
    ETH_PORT_RATE_LIMIT_PRI1_ENABLE = (0x1U),
    ETH_PORT_RATE_LIMIT_PRI2_ENABLE = (0x2U),
    ETH_PORT_RATE_LIMIT_PRI3_ENABLE = (0x4U),
    ETH_PORT_RATE_LIMIT_DISABLE     = (0x0U),
} Eth_portTxRateLimitPrioCfgType;

/**
 *  \brief Holds CPSW Port Rx Rate Limit Configuration for CPPI Port Ingress
 *         Rate Limitaion Operation.
 */
/* Rate limit configuration data structure */
typedef struct
{
   boolean       enableQoS;
   /**< Flag to set QoS (TRUE/FALSE)*/
   uint32        bandwidth[1];
   /**< desired bandwidth in Mbps for channel*/
   uint32        rateLimitCfg;
    /**<  Port rate limit priorities configuration of type
          Eth_portTxRateLimitPrioCfgType */
   uint32        prioPercArray[3U];
    /**<  percentage of bandwidth for each of rate limited priority
      *   Note: Array takes priority percentage in increasing order of priority
      *         i.e. prioPercArray[0] for ETH_PORT_RATE_LIMIT_PRI1_ENABLE,
      *         prioPercArray[1] for ETH_PORT_RATE_LIMIT_PRI2_ENABLE & likewise.
      */
} Eth_cpswQoSCfg;


/**
 *  \brief EgressFifo Configuration.
 */
typedef struct
{
    uint16         egressBufLenByte; 
    uint16         egressBufTotal;
    uint8          egressFifoIdx;
    uint8          egressFifoPriority;
} Eth_EgressFifoType;

/**
 *  \brief IngressFifo Configuration.
 */
typedef struct
{
    uint16         ingressBufLenByte;
    uint16         ingressBufTotal;
    uint8          ingressFifoIdx;
    uint8          ingressFifoPriority;
} Eth_IngressFifoType;
/**
 *  \brief Implementation specific structure of the Eth configuration.
 */
/* Requirements : SWS_Eth_00156 */
typedef struct Eth_ConfigType_s
{
    uint32              ctrlIdx;
    /**< CPSW controller index [Supported value 0 for port 1 ] */
	uint8               portIdx;
	/**< Port Idx >*/
    Eth_PortConfigType  portCfg;
    /**< Port configuration */
#if (ETH_TX_TRAFFIC_SHAPING_ENABLE == STD_ON)
    Eth_cpswQoSCfg    traffiShapingCfg;
    /**< Traffic shaping Configuration */
#endif /* (STD_ON == ETH_TX_TRAFFIC_SHAPING_ENABLE) */
#if (ETH_ENABLE_MII_API == STD_ON)
    Eth_MdioConfigType  mdioCfg;
    /**< MDIO configuration */
#endif

    Eth_CpdmaConfigType cpdmaCfg;
    /**< CPDMA Init Configurations */
#if (ETH_GLOBALTIMESUPPORT_API == STD_ON)
    Eth_CptsConfigType  cptsCfg;
    /**< Time stamp (CPTS) Configurations */
#endif
    uint32              enableCacheOps;
    /**< Since the Eth driver is updating (writing/reading) the packet header,
     *   if the packets are in cached region, then cache flush should be done
     *   for transmit and cache invalidate should be done for receive.
     *
     *   This flag determines whether the cache operations need to be enabled
     *   or not. If enabled, then the below two callback will be called to
     *   perform the cache operation
     */
    Eth_CacheFlushType      cacheFlushOps;
    /**< Cache flush function pointer */
    Eth_CacheInvalidateType cacheInvalidateOps;
    /**< Cache invalidate function pointer */
    Eth_EgressFifoType  egressFifo[8];
    /**< Egress FIFO configuration */
    Eth_IngressFifoType  ingressFifo[8];
    /**< Egress FIFO configuration */
} Eth_ConfigType;

/* Eth Transceiver types */

/**
 *  \brief Transceiver mode enum
 */
/* Requirements : SWS_EthTrcv_00099 */
typedef enum
{
    ETHTRCV_MODE_DOWN,
    ETHTRCV_MODE_ACTIVE,
} EthTrcv_ModeType;

/**
 *  \brief Transceiver Interface enum
 */
/* Requirements : SWS_EthTrcv_00039 */
typedef enum{
	LIGHT_MII,			
	MII,				
	RGMII
} EthTrcvMiiSelection;

/**
 *  \brief Transceiver link state enum
 */
/* Requirements : SWS_EthTrcv_00100 */
typedef enum
{
    ETHTRCV_LINK_STATE_DOWN,
    ETHTRCV_LINK_STATE_ACTIVE,
} EthTrcv_LinkStateType;

/**
 *  \brief Transceiver state enum
 */
/* Requirements : SWS_EthTrcv_00101 */
typedef enum
{
    ETHTRCV_STATE_UNINIT,
    ETHTRCV_STATE_INIT
} EthTrcv_StateType;

/**
 *  \brief Transceiver board rate enum
 */
/* Requirements : SWS_EthTrcv_00102 */
typedef enum
{
    ETHTRCV_BAUD_RATE_10MBIT,
    ETHTRCV_BAUD_RATE_100MBIT,
    ETHTRCV_BAUD_RATE_1000MBIT,		
} EthTrcv_BaudRateType;

/**
 *  \brief Transceiver duplex mode
 */
/* Requirements : SWS_EthTrcv_00103 */
typedef enum
{
    ETHTRCV_DUPLEX_MODE_HALF,
    ETHTRCV_DUPLEX_MODE_FULL,
} EthTrcv_DuplexModeType;

typedef enum
{
	ETHTRCV_PHYTESTMODE_NONE,
	ETHTRCV_PHYTESTMODE_1,
	ETHTRCV_PHYTESTMODE_2,
	ETHTRCV_PHYTESTMODE_3,
	ETHTRCV_PHYTESTMODE_4,
	ETHTRCV_PHYTESTMODE_5,
		
}EthTrcv_PhyTestModeType;
	

/**
 *  \brief Transceiver wake-up mode enum
 */
/* Requirements : SWS_EthTrcv_00113 */
typedef enum
{
    ETHTRCV_WUM_DISABLE,
    ETHTRCV_WUM_ENABLE,
    ETHTRCV_WUM_CLEAR
} EthTrcv_WakeupModeType;

/**
 *  \brief Transceiver Cable Diagnostic Results
 */
/* Requirements : SWS_EthTrcv_91008 */
typedef enum
{
	ETHTRCV_CABLEDIAG_OK,
	ETHTRCV_CABLEDIAG_ERROR,
	ETHTRCV_CABLEDIAG_SHORT,
	ETHTRCV_CABLEDIAG_OPEN	
} EthTrcv_CableDiagResultType;


/**
 *  \brief Transceiver Port MAC Layer Speed enum
 */

typedef enum
{
    ETH_MAC_LAYER_SPEED_100M,
	ETH_MAC_LAYER_SPEED_10G,		
    ETH_MAC_LAYER_SPEED_10M,
	ETH_MAC_LAYER_SPEED_1G				
} EthTrcvPortMacLayerSpeed;

/**
 *  \brief Transceiver Connection Negotiation of
 *  EthTrcv Link enum
 */

typedef enum
{
	TRCV_CONN_NEG_AUTO,
	TRCV_CONN_NEG_MASTER,
	TRCV_CONN_NEG_SLAVE
} EthTrcvConnNeg;

/**
 *  \brief Transceiver wake-up reason type enum
 */
/* Requirements : SWS_EthTrcv_00114 */
typedef enum
{
    ETHTRCV_WUR_NONE,
    ETHTRCV_WUR_GENERAL,
    ETHTRCV_WUR_BUS,			 
    ETHTRCV_WUR_INTERNAL,
    ETHTRCV_WUR_RESET,
    ETHTRCV_WUR_POWER_ON,
    ETHTRCV_WUR_PIN,
    ETHTRCV_WUR_SYSERR				
} EthTrcv_WakeupReasonType;

typedef enum
{
	ETHTRCV_WUR_MAGIC,			
	ETHTRCV_WUR_PATTERN,			
	ETHTRCV_WUR_BROADCAST,			
	ETHTRCV_WUR_UNICAST			
} EthTrcv_WakeupReasonType1;

/** \brief Enumerates Advertisement configurations. */
typedef enum
{
    ETHERNET_ADV_CAPAB_10_HALF = 0x1U, /* (0x1U << 0x0U) */
    /**< 10 Mbps half operation. */
    ETHERNET_ADV_CAPAB_10_FULL = 0x2U, /* (0x1U << 0x1U) */
    /**< 10 Mbps full operation. */
    ETHERNET_ADV_CAPAB_100_HALF = 0x4U, /* (0x1U << 0x2U) */
    /**< 100 Mbps half operation. */
    ETHERNET_ADV_CAPAB_100_FULL = 0x8U, /* (0x1U << 0x3U) */
    /**< 100 Mbps full operation. */
    ETHERNET_ADV_CAPAB_1000_HALF = 0x10U, /* (0x1U << 0x4U) */
    /**< 1000 Mbps half operation. */
    ETHERNET_ADV_CAPAB_1000_FULL = 0x20U, /* (0x1U << 0x5U) */
    /**< 1000 Mbps full operation. */
} EthTrcv_AdvCapabType;

/**
 *  \brief Transceiver MAC layer subtype of a switch port
 */
typedef enum
{
  REDUCED,
  REVERSED,				
  SERIAL,				
  STANDARD,				
  UNIVERSAL_SERIAL		
} EthTrcvPortMacLayerSubType;

/**
 *  \brief Transceiver MAC layer type of a switch port
 */

typedef enum
{
	TRCV_MAC_LAYER_TYPE_XGMII,				
	TRCV_MAC_LAYER_TYPE_XMII,
	TRCV_MAC_LAYER_TYPE_XXGMII				
} EthTrcvPortMacLayerType;

/**
 *  \brief Transceiver PHY loopback modes
 */
/* Requirements : SWS_EthTrcv_91004 */
typedef enum
{
	ETHTRCV_PHYLOOPBACK_NONE,
	ETHTRCV_PHYLOOPBACK_INTERNAL,
	ETHTRCV_PHYLOOPBACK_EXTERNAL,
	ETHTRCV_PHYLOOPBACK_REMOTE
} EthTrcv_PhyLoopbackModeType;

/**
 *  \brief Transceiver PHY transmit modes
 */
/* Requirements : SWS_EthTrcv_91006 */
typedef enum
{
	ETHTRCV_PHYTXMODE_NORMAL,
	ETHTRCV_PHYTXMODE_TX_OFF,
	ETHTRCV_PHYTXMODE_SCRAMBLER_OFF
} EthTrcv_PhyTxModeType;

typedef enum
{
   TRCV_PHYS_LAYER_TYPE_1000BASE_T,
   TRCV_PHYS_LAYER_TYPE_1000BASE_T1,
   TRCV_PHYS_LAYER_TYPE_100BASE_T1,
   TRCV_PHYS_LAYER_TYPE_100BASE_TX
	
}EthTrcvPhysLayerType;

/**
 *  \brief Implementation specific structure of the post build configuration.
 */
/* Requirements : SWS_EthTrcv_00098 */
typedef struct EthTrcv_ConfigType_s
{
	uint8			 ctrlIdx;
	/**< Index of the Controller */
	uint8 				trcvIdx;
	/**< Index of the transceiver */
	uint8 				phyAddr; 
	/**< PHY Address. */
	EthTrcvMiiSelection	MiiSel; 
	/**<MII Selection */
	uint32 				enableAutoNeg;   
	/**< Phy gigabit capability. */
	EthTrcvConnNeg		 connNeg;
	/**<Connection Negotiation of EthTrcv Link */
	uint32 				advertiseCapab;
	/**< Phy advertisement capability. */
	uint32 				linkPartCapab;
	/**< Link partner capability. */
	uint32				isGigCapab;
	/**< Phy gigabit capability. */
	EthTrcv_BaudRateType	 baudRate;
	/**< Phy operating speed. */
	EthTrcv_DuplexModeType	 duplexMode;
	/**< Phy operating duplexMode. */
	boolean 				loopbackEnable;
	/**< Phy loopback enable- for Test purpose. */
	EthTrcvPortMacLayerSpeed 	PortMacLaySpeed;
	/**<Baud Rate of MAC layer*/
	EthTrcvPortMacLayerSubType PortMacLaySubType;
	/**<MAC layer subtype of a switch port */
	EthTrcvPortMacLayerType 	PortMacLayType;
	/**<MAC layer type of the ethernet transceiver */
	EthTrcvPhysLayerType    PhysLayerType;
	/**<MAC layer type of the ethernet transceiver */
} EthTrcv_ConfigType;

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

/* None */

#ifdef __cplusplus
}
#endif

#endif  /* #ifndef ETH_GENERALTYPES_H_ */

/* @} */
