/* ======================================================================
 *   Copyright (C) 2022 Texas Instruments Incorporated
 *
 *   All rights reserved. Property of Texas Instruments Incorporated.
 *   Restricted rights to use, duplicate or disclose this code are
 *   granted through contract.
 *
 *   The program may not be used without the written permission
 *   of Texas Instruments Incorporated or against the terms and conditions
 *   stipulated in the agreement under which this program has been
 *   supplied.
 * ==================================================================== */

/**
 *  \file     Port_Cfg.h
 *
 *  \brief    This file contains generated pre compile configuration file
 *            for PORT MCAL driver
 *
 */

/**
 *  \defgroup MCAL_PORT_CFG PORT Configuration
 *
 *  This files defines PORT MCAL configuration structures
 *  @{
 */

/**********************************************************************************************************************
    Project: PORT_AM263
    Date   : 2022-08-06 03:07:34

    This file is generated by EB Tresos
    Do not modify this file, otherwise the software may behave in unexpected way.

 *********************************************************************************************************************/
#ifndef PORT_CFG_H
#define PORT_CFG_H

/**********************************************************************************************************************
 * INCLUDES
 *********************************************************************************************************************/
/*LDRA_NOANALYSIS*/
#include "Std_Types.h"
/*LDRA_ANALYSIS*/

#include "Dem.h"

#ifdef __cplusplus
extern "C" {
#endif

/**********************************************************************************************************************
 *  GLOBAL CONSTANT MACROS
 *********************************************************************************************************************/
/** \brief PORT Config ID */
#define PORT_CFG_ID                      (0x1U)

/**
 *  \name Port Driver Configuration SW Version Info
 *
 *  Defines for Port Driver configuration version
 *  @{
 */
/** \brief Port configuration Major Version */
#define PORT_CFG_MAJOR_VERSION           (0U)
/** \brief Port configuration Minor Version */
#define PORT_CFG_MINOR_VERSION           (9U)
/** \brief Port configuration Patch Version */
#define PORT_CFG_PATCH_VERSION           (0U)
/* @} */

/* List of symbolic names for Dio pin channels */
/*<PORT_PIN_CHANNEL_LIST>*/


#define PortConf_PortPin_PortPin_0 (97U)

#define PortConf_PortPin_PortPin_1 (105U)

#define PortConf_PortPin_PortPin_2 (41U)

#define PortConf_PortPin_PortPin_3 (24U)

#define PortConf_PortPin_PortPin_4 (6U)

#define PortConf_PortPin_PortPin_5 (14U)

#define PortConf_PortPin_PortPin_6 (13U)

#define PortConf_PortPin_PortPin_7 (2U)

#define PortConf_PortPin_PortPin_8 (37U)

#define PortConf_PortPin_PortPin_9 (36U)

#define PortConf_PortPin_PortPin_10 (19U)

#define PortConf_PortPin_PortPin_11 (126U)

#define PortConf_PortPin_PortPin_12 (122U)

#define PortConf_PortPin_PortPin_13 (127U)

#define PortConf_PortPin_PortPin_14 (121U)

#define PortConf_PortPin_PortPin_15 (134U)

#define PortConf_PortPin_PortPin_16 (128U)

#define PortConf_PortPin_PortPin_17 (102U)

#define PortConf_PortPin_PortPin_18 (103U)

#define PortConf_PortPin_PortPin_19 (95U)

#define PortConf_PortPin_PortPin_20 (94U)

#define PortConf_PortPin_PortPin_21 (101U)

#define PortConf_PortPin_PortPin_22 (100U)

#define PortConf_PortPin_PortPin_23 (116U)

#define PortConf_PortPin_PortPin_24 (115U)

#define PortConf_PortPin_PortPin_25 (90U)

#define PortConf_PortPin_PortPin_26 (89U)

#define PortConf_PortPin_PortPin_27 (108U)

#define PortConf_PortPin_PortPin_28 (91U)

#define PortConf_PortPin_PortPin_29 (117U)

#define PortConf_PortPin_PortPin_30 (123U)

#define PortConf_PortPin_PortPin_31 (142U)

#define PortConf_PortPin_PortPin_32 (140U)

#define PortConf_PortPin_PortPin_33 (143U)

#define PortConf_PortPin_PortPin_34 (141U)

#define PortConf_PortPin_PortPin_35 (137U)

#define PortConf_PortPin_PortPin_36 (136U)

#define PortConf_PortPin_PortPin_37 (130U)

#define PortConf_PortPin_PortPin_38 (131U)

#define PortConf_PortPin_PortPin_39 (132U)

#define PortConf_PortPin_PortPin_40 (124U)

#define PortConf_PortPin_PortPin_41 (118U)

#define PortConf_PortPin_PortPin_42 (125U)

#define PortConf_PortPin_PortPin_43 (4U)

#define PortConf_PortPin_PortPin_44 (21U)

#define PortConf_PortPin_PortPin_45 (49U)

#define PortConf_PortPin_PortPin_46 (32U)


/*</PORT_PIN_CHANNEL_LIST>*/

/**
 *  \name Port Driver Maximum number of modes per pin
 *
 *  Maximum number of runtime changeable port pin modes per pin
 *  This value is calculated based on actual configuration and is
 *  not the maximum number of modes supported by SoC (16)
 *  @{
 */
#define PORT_CFG_MAX_MUXMODE (1U)
/* @} */

/**
 *  \name Service enable/diable defines
 *
 *  Pre-compile switches for enabling/disabling PORT MCAL APIs
 *  @{
 */
/** \brief Enable/Disable Port_SetPinDirection() */
#define PORT_CFG_SET_PIN_DIRECTION_API       (STD_ON) 
/** \brief Enable/Disable Port_RefreshPinDirection() */
/*LDRA_INSPECTED 61 X MR:5.1,MR:5.2 "Custom type definition" */
#define PORT_CFG_REFRESH_PORT_DIRECTION_API  (STD_ON) 
/** \brief Enable/Disable Port_GetVersionInfo() */
#define PORT_CFG_VERSION_INFO_API            (STD_ON) 
/** \brief Enable/Disable Port_SetPinMode() */
#define PORT_CFG_SET_PIN_MODE_API            (STD_ON) 
/** \brief Enable/Disable development error detection */
#define PORT_CFG_DEV_ERROR_DETECT            (STD_OFF) 
/** \brief Enable/Disable SAFETI Configuration register readback */
#define PORT_SAFETI_API                      (STD_OFF) 
/* @} */

/**********************************************************************************************************************
 *  STATIC TESTS
 *********************************************************************************************************************/


/** \brief Counter ID for counter used to count wait ticks */
#define PORT_CFG_OS_COUNTER_ID               ((CounterType)0U)

/**
*  \brief PORT timeout.
*   Each tick is 31.25us (for 32K Counter). Wait for 5s which comes to
*   below value
*/
#define PORT_CFG_TIMEOUT_DURATION            (32000U)

/* DEM Error Definitions */
/* DEM Error Codes */
/** \brief No event error code */
#define PORT_DEM_NO_EVENT                (0xFFFFFFFFU)


#ifndef PORT_E_HARDWARE_ERROR
/** \brief Hardware failed */
#define PORT_E_HARDWARE_ERROR          (PORT_DEM_NO_EVENT)
#endif

/**
 *  \brief Pin Mode map structure
 *
 *  Structure to map selected mode to corresponding PAD CONFIG MUXMODE value
 */


/**********************************************************************************************************************
 *  GLOBAL DATA TYPES AND STRUCTURES
 *********************************************************************************************************************/
/*LDRA_INSPECTED 33 D: MISRAC_2012_8.6
 * "Reason -  Port configuration structure declaration" */

extern const struct Port_ConfigType_s * PortConfigSet_0_pt;


/**********************************************************************************************************************
 *  GLOBAL FUNCTION PROTOTYPES
 *********************************************************************************************************************/

#ifdef __cplusplus
}
#endif

#endif  /* PORT_CFG_H */


/**********************************************************************************************************************
 *  END OF FILE: Port_Cfg.h
 *********************************************************************************************************************/
