diff --git a/source/board/flash/ospi/flash_nor_ospi.c b/source/board/flash/ospi/flash_nor_ospi.c
index d211dcae60c..3ca4640ee49 100644
--- a/source/board/flash/ospi/flash_nor_ospi.c
+++ b/source/board/flash/ospi/flash_nor_ospi.c
@@ -661,12 +661,13 @@ static int32_t Flash_set888mode(Flash_Config *config, uint8_t seq)
     }
     if((seq & (1 << 2)) != 0)
     {
+        uint8_t regVal = 0x2;
         status = Flash_norOspiCmdWrite(config, devCfg->cmdWren, OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
         if(status == SystemP_SUCCESS)
         {
             status = Flash_norOspiWaitReady(config, devCfg->flashBusyTimeout);
         }
-        status = Flash_norOspiCmdWrite(config, 0x72, 0, 0, NULL, 0);
+        status = Flash_norOspiCmdWrite(config, 0x72, 0, 0, &regVal, 1);
         OSPI_setProtocol((OSPI_Handle)(obj->ospiHandle), gFlashToSpiProtocolMap[pCfg->protocol]);
         obj->currentProtocol = pCfg->protocol;
         if(status == SystemP_SUCCESS)
@@ -849,7 +850,9 @@ static int32_t Flash_norOspiReadId(Flash_Config *config)
     Flash_NorOspiObject *obj = (Flash_NorOspiObject *)(config->object);
     Flash_DevConfig *devCfg = config->devConfig;
     FlashCfg_ReadIDConfig *idCfg = &(devCfg->idCfg);
+    FlashCfg_ProtoEnConfig *pCfg = &(devCfg->protocolCfg);
 
+    uint8_t  seq = pCfg->enableSeq;
     uint8_t  idCode[FLASH_OSPI_JEDEC_ID_SIZE_MAX] = {0};
     uint32_t cmdAddr = OSPI_CMD_INVALID_ADDR;
     uint32_t dummyBits = 0;
@@ -859,9 +862,7 @@ static int32_t Flash_norOspiReadId(Flash_Config *config)
     if(obj->currentProtocol == FLASH_CFG_PROTO_8D_8D_8D)
     {
         dummyBits = idCfg->dummy8;
-        if(idCfg->dummy8 != 8){
-            cmdAddr = 0U;
-        }
+        cmdAddr = 0U;
         idNumBytes = 4; /* Can't read odd bytes in octal DDR */
     }
     else
@@ -876,13 +877,10 @@ static int32_t Flash_norOspiReadId(Flash_Config *config)
     {
         uint32_t manfID, devID;
 
-        manfID = (uint32_t)idCode[0];
-        devID = ((uint32_t)idCode[1] << 8) | ((uint32_t)idCode[2]);
-        if (!((manfID == config->attrs->manufacturerId) && (devID == config->attrs->deviceId)))
+        if((obj->currentProtocol == FLASH_CFG_PROTO_8D_8D_8D) &&  ((seq & (1 << 2)) != 0))
         {
-            /* Try the other 3 bytes */
             manfID = (uint32_t)idCode[3];
-            devID = ((uint32_t)idCode[4] << 8) | ((uint32_t)idCode[5]);
+            devID = ((uint32_t)idCode[0] << 8) | ((uint32_t)idCode[1]);
             if (!((manfID == config->attrs->manufacturerId) && (devID == config->attrs->deviceId)))
             {
                 status = SystemP_FAILURE;
@@ -890,8 +888,25 @@ static int32_t Flash_norOspiReadId(Flash_Config *config)
         }
         else
         {
-            /* Success, nothing to do */;
+            manfID = (uint32_t)idCode[0];
+            devID = ((uint32_t)idCode[1] << 8) | ((uint32_t)idCode[2]);
+
+            if (!((manfID == config->attrs->manufacturerId) && (devID == config->attrs->deviceId)))
+            {
+                /* Try the other 3 bytes */
+                manfID = (uint32_t)idCode[3];
+                devID = ((uint32_t)idCode[4] << 8) | ((uint32_t)idCode[5]);
+                if (!((manfID == config->attrs->manufacturerId) && (devID == config->attrs->deviceId)))
+                {
+                    status = SystemP_FAILURE;
+                }
+            }
+            else
+            {
+                /* Success, nothing to do */;
+            }
         }
+
     }
 
     return status;
@@ -1263,6 +1278,14 @@ static int32_t Flash_norOspiOpen(Flash_Config *config, Flash_Params *params)
                 Flash_norOspiEraseSector(config, sect);
                 Flash_norOspiWrite(config, phyTuningOffset, (uint8_t *)phyTuningData, phyTuningDataSize);
                 attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);
+
+                readDataCapDelay = 4U;
+                while((attackVectorStatus != SystemP_SUCCESS) && (readDataCapDelay > 0U))
+                {
+                    OSPI_setRdDataCaptureDelay(obj->ospiHandle, readDataCapDelay);
+                    attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);
+                    readDataCapDelay--;
+                }
             }
 
             if(attackVectorStatus == SystemP_SUCCESS)
@@ -1372,7 +1395,7 @@ static int32_t Flash_norOspiDacModeDisable(Flash_Config *config)
     if(obj && obj->ospiHandle)
     {
         status = OSPI_disableDacMode(obj->ospiHandle);
-    }    
+    }
 
     return status;
 }
diff --git a/source/drivers/ospi/v0/lld/ospi_v0_lld.c b/source/drivers/ospi/v0/lld/ospi_v0_lld.c
index b63bc185753..3c1cafdffa4 100644
--- a/source/drivers/ospi/v0/lld/ospi_v0_lld.c
+++ b/source/drivers/ospi/v0/lld/ospi_v0_lld.c
@@ -135,7 +135,7 @@ static int32_t OSPI_waitWriteSRAMLevel(const CSL_ospi_flash_cfgRegs *pReg,
 static int32_t OSPI_waitIndWriteComplete(const CSL_ospi_flash_cfgRegs *pReg);
 static int32_t OSPI_waitIdle(OSPILLD_Handle hOspi, uint32_t timeOut);
 
-static int32_t OSPI_flashExecCmd(OSPILLD_Handle hOspi, const CSL_ospi_flash_cfgRegs *pReg, 
+static int32_t OSPI_flashExecCmd(OSPILLD_Handle hOspi, const CSL_ospi_flash_cfgRegs *pReg,
                                 uint32_t timeout);
 static void OSPI_readFifoData(uintptr_t indAddr, uint8_t *dest, uint32_t rdLen);
 static void OSPI_writeFifoData(uintptr_t indAddr, const uint8_t *src, uint32_t wrLen);
@@ -145,7 +145,7 @@ static int32_t OSPI_isDmaRestrictedRegion(OSPILLD_Handle hOspi, uint32_t addr);
 static uint32_t OSPI_utilLog2(uint32_t num);
 static uint8_t OSPI_getCmdExt(OSPILLD_Handle hOspi, uint8_t cmd);
 
-/* LLD Parameter Validation */ 
+/* LLD Parameter Validation */
 static inline int32_t OSPI_lld_isFrameFormatValid(uint32_t frmFmt);
 static inline int32_t OSPI_lld_isChipSelectValid(uint32_t chipSelect);
 static inline int32_t OSPI_lld_isDecoderChipSelectValid(uint32_t decChipSelect);
@@ -498,6 +498,7 @@ int32_t OSPI_lld_enableDDR(OSPILLD_Handle hOspi)
         CSL_REG32_FINS(&pReg->CONFIG_REG,
                    OSPI_FLASH_CFG_CONFIG_REG_ENABLE_DTR_PROTOCOL_FLD,
                    TRUE);
+
     }
     else
     {
@@ -752,6 +753,7 @@ void OSPI_lld_setProtocol(OSPILLD_Handle hOspi, uint32_t protocol)
                 if(protocol == OSPI_NOR_PROTOCOL(8,8,8,1))
                 {
                     OSPI_lld_enableDDR(hOspi);
+                    OSPI_lld_enableDdrRdCmds(hOspi);
                     OSPI_lld_setDualOpCodeMode(hOspi);
                 }
                 if(protocol == OSPI_NOR_PROTOCOL(4,4,4,1))
@@ -1230,7 +1232,7 @@ int32_t OSPI_lld_readDirectDma(OSPILLD_Handle hOspi, OSPI_Transaction *trans)
         /* DMA Copy fails when copying to to certain memory regions. So in this case we switch to normal memcpy
         for copying even if dmaEnable is true. Also do DMA copy only if size > 1KB*/
         uint32_t isDmaCopy = (OSPI_isDmaRestrictedRegion(hOspi, (uint32_t)pDst) == FALSE) &&
-                             (trans->count > OSPI_DMA_COPY_LOWER_LIMIT);     
+                             (trans->count > OSPI_DMA_COPY_LOWER_LIMIT);
 
         if(isDmaCopy == TRUE)
         {
@@ -1489,7 +1491,7 @@ int32_t OSPI_lld_writeCmd(OSPILLD_Handle hOspi, OSPI_WriteCmdParams *wrParams)
 
 int32_t OSPI_lld_writeDirect(OSPILLD_Handle hOspi, OSPI_Transaction *trans)
 {
-    int32_t status = OSPI_SYSTEM_SUCCESS;   
+    int32_t status = OSPI_SYSTEM_SUCCESS;
     const CSL_ospi_flash_cfgRegs *pReg = (const CSL_ospi_flash_cfgRegs *)(hOspi->baseAddr);
 
     uint8_t *pSrc;
@@ -1853,7 +1855,7 @@ static int32_t OSPI_programInstance(OSPILLD_Handle hOspi)
 
         /* Set initial protocol to be 1s1s1s */
         OSPI_lld_setProtocol(hOspi, OSPI_NOR_PROTOCOL(1,1,1,0));
-    
+
         OSPI_lld_setXferOpCodes(hOspi, 0x03, 0x02);
 
         /* Set address bytes to 3 */
@@ -2239,7 +2241,7 @@ static uint32_t OSPI_utilLog2(uint32_t num)
 static inline int32_t OSPI_lld_isFrameFormatValid(uint32_t frmFmt)
 {
     int32_t status = OSPI_SYSTEM_FAILURE;
-    
+
     if((frmFmt == OSPI_FF_POL0_PHA0) || (frmFmt == OSPI_FF_POL0_PHA1) || \
        (frmFmt == OSPI_FF_POL1_PHA0) || (frmFmt == OSPI_FF_POL1_PHA1))
        {
@@ -2307,10 +2309,10 @@ void OSPI_lld_isr(void* args)
     uint32_t regVal;
     uint8_t *pDst;
     uint32_t sramLevel = 0U, readBytes = 0U, writeBytes = 0U;
-    
+
     switch (hOspi->currTrans->state)
     {
-    case OSPI_TRANS_IDLE:                   
+    case OSPI_TRANS_IDLE:
         break;
     case OSPI_TRANS_WRITE:
 
@@ -2352,7 +2354,7 @@ void OSPI_lld_isr(void* args)
         regVal = CSL_REG32_RD(&pReg->IRQ_STATUS_REG);
 
         if(hOspi->currTrans->count != 0U &&  hOspi->currTrans->buf != NULL)
-        {            
+        {
             pDst = (uint8_t *) (hOspi->currTrans->buf);
             pDst += hOspi->currTrans->transferOffset;
             if (0U != (regVal & CSL_OSPI_INTR_MASK_IND_XFER))
@@ -2371,7 +2373,7 @@ void OSPI_lld_isr(void* args)
 
                 hOspi->currTrans->transferOffset += readBytes;
                 hOspi->currTrans->count -= readBytes;
-            
+
             }
             if((0U == hOspi->currTrans->count) || (0U != (regVal & CSL_OSPI_FLASH_CFG_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK)))
             {
@@ -2384,14 +2386,14 @@ void OSPI_lld_isr(void* args)
                 hOspi->currTrans->state = OSPI_TRANS_IDLE;
                 hOspi->currTrans->status = OSPI_TRANSFER_COMPLETED;
                 hOspi->interruptCallback(args);
-            }            
-        }        
+            }
+        }
         break;
 
     default:
         break;
-    }    
-}       
+    }
+}
 
 static void OSPI_disableInterrupt(OSPILLD_Handle hOspi)
 {
diff --git a/source/drivers/soc/am261x/soc.h b/source/drivers/soc/am261x/soc.h
index 22345f986cd..898ba119478 100644
--- a/source/drivers/soc/am261x/soc.h
+++ b/source/drivers/soc/am261x/soc.h
@@ -121,11 +121,13 @@ static inline int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
                                              (baseAddr == CSL_I2C2_U_BASE))
 
 /** \brief Macro to check if the OSPI base address is valid */
-#define IS_OSPI_BASE_ADDR_VALID(baseAddr)    (baseAddr == CSL_FLASH_CONFIG_REG8_U_BASE)
+#define IS_OSPI_BASE_ADDR_VALID(baseAddr)    ((baseAddr == CSL_FLASH_CONFIG_REG8_U_BASE) || \
+                                                (baseAddr == CSL_FSS_UL_128_FSS_OF_UL_OSPI0_OSPI_CFG_VBUSP_VBP2APB_WRAP_OSPI_CFG_VBP_OSPI_FLASH_APB_U_BASE))
 
 /** \brief Macro to check if the OSPI base address is valid */
-#define IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr)    (baseAddr == CSL_FLASH_DATA_REG0_U_BASE)
-
+#define IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr)    ((baseAddr == CSL_FLASH_DATA_REG0_U_BASE) || \
+                                                    (baseAddr == CSL_FLASH_DATA_REG1_U_BASE) || \
+                                                     (baseAddr == CSL_FSS_UL_128_FSS_OF_UL_DAT_REG0_U_BASE))
 /**
  * \brief Enable clock to specified module
  *
