menuitem "ICSS configuration"

/*
 * Setup PRU_ICSSG in SYNC mode (250 MHz)
 *  PRU_ICSS core clocking options
 *             Core_clk : 0 : PER1HSDIV_CLKOUT1 (CTRLMMR_ICSSG0_CLKSEL) [Default]
 *                        1 : CPSWHSDIV_CLKOUT2 (CTRLMMR_ICSSG0_CLKSEL)
 *                        2 : VBUS_CLK (SYNC_Mode)  (PRU_ICSSG0_CFG_CORE_SYNC_REG)  [Module level setting to be in sync with system CBASS clock]
 *
 */
 /*

hotmenu PRU_ICSSG_SyncMode_250MHz()
{
    unsigned int * p_address0 = PRU_ICSSG0_CFG_CORE_SYNC_REG;
    unsigned int * p_address1 = PRU_ICSSG1_CFG_CORE_SYNC_REG;
    unsigned int * p_address2 = PRU_ICSSG2_CFG_CORE_SYNC_REG;

    *p_address0 = 0x1;
    *p_address1 = 0x1;
    *p_address2 = 0x1;
    GEL_TextOut("\n All PRU_ICSS CLK are configured in SYNC mode (250 MHz) \n");
}
*/





//AM26x
#define HW_ICSS_MII_MDIO_USERACCESS0 0x48032480
#define HW_ICSS_MII_MDIO_USERACCESS1 0x48032488
#define PHY0_ADDR 0x0
#define PHY1_ADDR 0x1

PRU_ICSSG_Read_Phy (int instance, int phyaddr, int reg_offset)
{
    unsigned int * p_address;
    if (instance == 0)
    {
        p_address = HW_ICSS_MII_MDIO_USERACCESS0;
    }
    if (instance == 1)
    {
        p_address = HW_ICSS_MII_MDIO_USERACCESS1;
    }
    if (instance == 2)
    {
        p_address = PRU_ICSSG2_MDIO_USER_ACCES0_REG;
    }
    *p_address = (0x8000FFFF) | (phyaddr << 16) | (reg_offset << 21);
    GEL_TextOut("PhyAddr: %x Reg : %x Val : %x\n",,,,, phyaddr, reg_offset, (*p_address & 0xffff));
}


PRU_ICSSG_Ext_Read_Phy (int instance, int phyaddr, int reg_offset)
{
    unsigned int * p_address;
    if (instance == 0)
    {
        p_address = HW_ICSS_MII_MDIO_USERACCESS0;
    }
    if (instance == 1)
    {
        p_address = HW_ICSS_MII_MDIO_USERACCESS1;
    }
    if (instance == 2)
    {
        p_address = PRU_ICSSG2_MDIO_USER_ACCES0_REG;
    }
     //Write 0x1F to 0xD
     //Write reg_offset to 0xE
     //Write 0x401F to 0xD
     //Read  0xE
    *p_address = 0xC000001F | (phyaddr << 16) | (0xD << 21);
    *p_address = 0xC0000000 | (phyaddr << 16) | (0xE << 21) | reg_offset;
    *p_address = 0xC000401F | (phyaddr << 16) | (0xD << 21);
    *p_address = (0x8000FFFF) | (phyaddr << 16) | (0xE << 21);
    GEL_TextOut("PhyAddr: %x Reg : %x Val : %x\n",,,,, phyaddr, reg_offset, (*p_address & 0xffff));
}


hotmenu PRU_ICSSG_Phy_Reg_Dump()
{
    unsigned int loopcnt = 0;

    GEL_TextOut("\n ICSSG0 PHY0 Registers \n");
    while (loopcnt < 32)
    {
        PRU_ICSSG_Read_Phy (1, PHY0_ADDR, loopcnt++);
    }
    PRU_ICSSG_Ext_Read_Phy (1, PHY0_ADDR, 0x467);
    PRU_ICSSG_Ext_Read_Phy (1, PHY0_ADDR, 0x468);

    GEL_TextOut("\n ICSSG0 PHY1 Registers \n");

    loopcnt = 0;
    while (loopcnt < 32)
    {
        PRU_ICSSG_Read_Phy (1, PHY1_ADDR, loopcnt++);
    }
    PRU_ICSSG_Ext_Read_Phy (1, PHY1_ADDR, 0x467);
    PRU_ICSSG_Ext_Read_Phy (1, PHY1_ADDR, 0x468);
    
    
}