| Project Statistics |
| PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
| PROP_ReduceControlSets_virtex5=Auto |
PROP_Simulator=ISim (VHDL/Verilog) |
| PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
| PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2018-11-26T16:42:19 |
PROP_intWbtProjectID=5860A13C70C540668563B3CB0DD78550 |
| PROP_intWbtProjectIteration=3 |
PROP_intWorkingDirLocWRTProjDir=Same |
| PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.appsfpga_e |
| PROP_xilxBitgStart_IntDone_virtex5=true |
PROP_xstLUTCombining_virtex5=Auto |
| PROP_AutoTop=true |
PROP_DevFamily=Virtex5 |
| PROP_DevDevice=xc5vlx50 |
PROP_DevFamilyPMName=virtex5 |
| PROP_DevPackage=ff1153 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
| PROP_DevSpeed=-2 |
PROP_PreferredLanguage=Verilog |
| FILE_UCF=1 |
FILE_VHDL=31 |