appsfpga Project Status (11/30/2018 - 13:11:51)
Project File: discovery4100.xise Parser Errors: No Errors
Module Name: appsfpga Implementation State: Programming File Generated
Target Device: xc5vlx50-2ff1153
  • Errors:
No Errors
Product Version:ISE 14.5
  • Warnings:
799 Warnings (155 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 2,136 28,800 7%  
    Number used as Flip Flops 2,136      
Number of Slice LUTs 1,615 28,800 5%  
    Number used as logic 1,601 28,800 5%  
        Number using O6 output only 1,387      
        Number using O5 output only 64      
        Number using O5 and O6 150      
    Number used as Memory 9 7,680 1%  
        Number used as Shift Register 9      
            Number using O6 output only 9      
    Number used as exclusive route-thru 5      
Number of route-thrus 68      
    Number using O6 output only 68      
Number of occupied Slices 966 7,200 13%  
Number of LUT Flip Flop pairs used 2,828      
    Number with an unused Flip Flop 692 2,828 24%  
    Number with an unused LUT 1,213 2,828 42%  
    Number of fully used LUT-FF pairs 923 2,828 32%  
    Number of unique control sets 87      
    Number of slice register sites lost
        to control set restrictions
119 28,800 1%  
Number of bonded IOBs 258 560 46%  
    Number of LOCed IOBs 255 258 98%  
    IOB Master Pads 72      
    IOB Slave Pads 72      
Number of BlockRAM/FIFO 33 48 68%  
    Number using BlockRAM only 33      
        Number of 36k BlockRAM used 32      
        Number of 18k BlockRAM used 2      
    Total Memory used (KB) 1,188 1,728 68%  
Number of BUFG/BUFGCTRLs 7 32 21%  
    Number used as BUFGs 7      
Number of OSERDESs 91      
Number of PLL_ADVs 2 6 33%  
Average Fanout of Non-Clock Nets 3.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Nov 30 13:09:43 20180599 Warnings (151 new)222 Infos (11 new)
Translation ReportCurrentFri Nov 30 13:09:51 201804 Warnings (0 new)4 Infos (0 new)
Map ReportCurrentFri Nov 30 13:10:36 20180132 Warnings (2 new)14 Infos (1 new)
Place and Route ReportCurrentFri Nov 30 13:11:03 2018024 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Nov 30 13:11:14 2018038 Warnings (0 new)4 Infos (0 new)
Bitgen ReportCurrentFri Nov 30 13:11:44 201802 Warnings (2 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateFri Nov 30 13:11:45 2018
WebTalk Log FileOut of DateFri Nov 30 13:11:51 2018

Date Generated: 11/30/2018 - 15:32:37