[15:48:16.601]收←◆In Bootloader: v10.0

Debug opened on URT0
\0Fetching data from EEPROM device 3280 bytes

[15:48:16.856]收←◆eeprom: EEPROM content is valid
EEPROM: Initializing Slave EEPROM: 3280 bytes

[15:48:17.111]收←◆sysmon: System Startup State From AppCfg is 0
sysmon: Notify uC ASIC is running.
sysmon: 1.8V power enabled via PMD

[15:48:17.159]收←◆
Serial Flash NVM = 0xEFCF

sysmon: Low-power mode change cc = 1
sysmon: Memory test cc = 1
sysmon: System mailbox ID = f7ff6670
API version: 0a.01.01
App version: 0a.01.01
ASIC ID: 50
ASIC Configuration: 4422
Configuration layout versions:
     Seq Map: 44.21.0021
     SW Map: 44.21.0000
     EEPROM: 10.01.0001
DMD_Init - Complete 
*****Through DDP_Init cw & seq*****
projectorCtl: Opening projector control on 
[15:48:17.222]收←◆USB

illumination: Starting SSI Initialization...
  Configuring PWM Driver...
  PWM Driver initialized...
  Setting PWM Drive Levels to 0...
  Configuring Sensor. Type = 1.
  Initializing CCI configuration...
SSI_Calibration  EE_GetVAR command Successful...
  SSI initialization complete
illumination: DDP_ILLUMINATION_TYPE_SSI illum_Init Completed 
sysmon: Through _sysReset
sysmon: System Startup State From AppCfg is 0
sysEvent: SYSEVENT_START
sysmon: MASTER ASIC
Sysmon: Transitioning to normal run mode
datapathf: StopCurrentOperation complete
systemmode: There are 4 defined SDED 
\0
[15:48:17.254]收←◆odes 

datapathf: Transition to SUSPENDED 
systemmode: TwoD System Mode Table Created 
systemmode: HighSpeed System Mode Table Created 
systemmode: XPR System Mode Table Created 
systemmode: ThreeD System Mode Table Created 
DMD_Init - Complete 
DMD_Power On... 
******** DMD_DEVICE_ID 152 ******** 
**
[15:48:17.301]收←◆****** DMD_FUSE_ID 7 ******** 
source: EEPROM defined
DMD_ConfigDMDReg for HEP DMD 
source: SetUserSFGColor = 0
source: DisplaySFG Color = 0
source: DisplaySFG size = 960 x 1080

[15:48:17.344]收←◆illumination: Transition DMD to operating mode
illumination: Enabling SSI Driver...

[15:48:18.537]收←◆API: Degamma Transfer to XPR FPGA Complete
pictcont: Set gamma 0
datapathf: autolock initialization passed 
digcontrolf: Cfg complete
digcontrolf: Init complete
digcontrolf: powerNormal complete
datapathf: dig powerNormal
datapath_SourceDetectMode is AUTOLOCK 
pictcont: Setting the new system mode_num 0 
pictcont: Disable BrilliantColor 
pictcont: pictcont_SSI_CompleteSystemMode completed 
pictcont: pictcont_CompleteSystemMode completed 
pictcont: Setting the new system mode_num 0 completed after 0 ms 
datapath: Set the default system mode Num: 0 complete 

[15:48:18.605]收←◆source: SPLASH_LoadImage reload addresses:  0xf92d0880, 0xf7ff3c18

[15:48:18.669]收←◆source: SPLASH_LoadImage addresses:  0xf92d0880, 0xffffffff
source: Loading RGB -> RGB CSC table
source: DisplaySplash size = 992 x 1080
datapathf: SplashAtStartup is enabled - displaying SPLASH

[15:48:18.792]收←◆dispfmt: minPan, pan, maxPan:0, 0, 0
         data = { 992, 0, 992 }
dispfmt: minScan, Scan, maxScan:0, 0, 0
         data = { 1080, 0, 1080 }
datapathf: XPR FPGA power normal
datapathf: XPR FPGA Type is 1 
datapathf: FPGAcontrol_UHD_XPRInit 
FPGAcontrol: FPGAcontrol_UHD_XPRInit - UHD Type = 0

[15:48:19.845]收←◆FPGA XPR Read Values A,B: 68065842 , 9a806390 
FPGA XPR write Values A,B: 2e709be4 , 6314a71 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 228 
FPGA Read Back successful , data 2 : 155 
FPGA Read Back successful , data 3 : 112 
FPGA Read Back successful , data 4 : 46 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 113 
FPGA Read Back successful , data 2 : 74 
FPGA Read Back successful , data 3 : 49 
FPGA Read Back successful , data 4 : 6 
FPGAcontrol: FPGAcontrol_UHD_XPRInit - FPGA initialization complete

[15:48:21.397]收←◆API: Degamma Transfer to XPR FPGA Complete
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 0 
FPGA Read Back successful , data 2 : 15 
FPGA Read Back successful , data 3 : 112 
FPGA Read Back successful , data 4 : 8 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 0 
FPGA Read Back successful , data 2 : 15 
FPGA Read Back successful , data 3 : 112 
FPGA Read Back successful , data 4 : 8 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 112 
FPGA Read Back successful , data 2 : 8 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 128 
FPGA Read Back successful , data 2 : 7 
FPGA Read Back successful , data 3 : 56 
FPGA Read Back successful , data 4 : 4 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 0 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 240 
FPGA Read Back successful , data 4 : 4 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 224 
FPGA Read Back successful , data 2 : 9 
FPGA Read Back successful , data 3 : 230 
FPGA Read Back successful , data 4 : 10 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 31 
FPGA Read Back successful , data 2 : 5 
FPGA Read Back successful , data 3 : 15 
FPGA Read Back successful , data 4 : 10 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 255 
FPGA Read Back successful , data 2 : 14 
FPGA Read Back successful , data 3 : 255 
FPGA Read Back successful , data 4 : 14 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 16 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 5 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 16 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 5 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 64 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 17 
FPGA Read Back successful , data 3 : 17 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 18 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 56 
FPGA Read Back successful , data 2 : 4 
FPGA Read Back successful , data 3 : 160 
FPGA Read Back successful , data 4 : 7 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 56 
FPGA Read Back successful , data 2 : 4 
FPGA Read Back successful , data 3 : 160 
FPGA Read Back successful , data 4 : 7 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Rea
[15:48:21.746]收←◆d Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 56 
FPGA Read Back successful , data 2 : 4 
FPGA Read Back successful , data 3 : 240 
FPGA Read Back successful , data 4 : 1 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 4 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 25 
FPGA Read Back successful , data 2 : 80 
FPGA Read Back successful , data 3 : 64 
FPGA Read Back successful , data 4 : 1 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 3 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 15 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 15 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 49 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 128 
FPGA Read Back successful , data 2 : 7 
FPGA Read Back successful , data 3 : 224 
FPGA Read Back successful , data 4 : 3 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 230 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 0 
FPGA Read Back successful , data 2 : 1 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 1 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 0 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGAcontrol: FPGAcontrol_UHD_XPROnConfig complete 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 31 
FPGA Read Back successful , data 2 : 0 
FPGA Read Back successful , data 3 : 0 
FPGA Read Back successful , data 4 : 0 
FPGA Write successful, returned 1 
FPGA Read Back successful , data 1 : 1 
FPGA Read Back successful , data 2 : 16 
FPGA Read Back successful , data 3 : 17 
FPGA Read Back successful , data 4 : 0 
datapathf: datapath_ConfigFPGAatStartup complete - isUHD = 1
refCmdI2C: Batch file executing... batchFileIndex = 0
           batch file address f93a1d50
refCmdI2C: Reached the batch_endaddr f93a1d50
sysmon : AUTOINIT Batchfile execution Complete

datapathf: Transition to SPLASH_AT_STARTUP 
illumination: DMD Unparked

[15:48:21.846]收←◆illumination: Setting SSI Currents on Primary Ports.
illumination: Setting SSI Currents on Secondary Ports.
illumination: Enabling SSI Illuminators.
illumination: Transition Illumination to operating mode
sysmon: Transition to normal run mode complete

[15:48:26.844]收←◆source: DisplaySFG Color = 0
source: DisplaySFG size = 960 x 1080

datapathf: Transition to BEGIN_SCAN 
digcontrolf: Input Video Stable
datapath_SourceDetectMode is AUTOLOCK 
digcontrolf: ConfigureForSearch complete

datapathf: Transition to LOOK_FOR_SYNCS 

[15:48:26.956]收←◆ALC:    1	     1813	AL_MODE_DETECT

[15:48:28.263]收←◆Event: Source No Syncs on channel