appsfpga Project Status (12/13/2018 - 17:22:54)
Project File: discovery4100.xise Parser Errors: No Errors
Module Name: appsfpga Implementation State: Programming File Generated
Target Device: xc5vlx50-2ff1153
  • Errors:
No Errors
Product Version:ISE 14.5
  • Warnings:
792 Warnings (591 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 2,157 28,800 7%  
    Number used as Flip Flops 2,157      
Number of Slice LUTs 1,631 28,800 5%  
    Number used as logic 1,612 28,800 5%  
        Number using O6 output only 1,397      
        Number using O5 output only 63      
        Number using O5 and O6 152      
    Number used as Memory 14 7,680 1%  
        Number used as Shift Register 14      
            Number using O6 output only 14      
    Number used as exclusive route-thru 5      
Number of route-thrus 68      
    Number using O6 output only 68      
Number of occupied Slices 1,006 7,200 13%  
Number of LUT Flip Flop pairs used 2,837      
    Number with an unused Flip Flop 680 2,837 23%  
    Number with an unused LUT 1,206 2,837 42%  
    Number of fully used LUT-FF pairs 951 2,837 33%  
    Number of unique control sets 87      
    Number of slice register sites lost
        to control set restrictions
117 28,800 1%  
Number of bonded IOBs 258 560 46%  
    Number of LOCed IOBs 255 258 98%  
    IOB Master Pads 72      
    IOB Slave Pads 72      
Number of BlockRAM/FIFO 33 48 68%  
    Number using BlockRAM only 33      
        Number of 36k BlockRAM used 32      
        Number of 18k BlockRAM used 2      
    Total Memory used (KB) 1,188 1,728 68%  
Number of BUFG/BUFGCTRLs 7 32 21%  
    Number used as BUFGs 7      
Number of OSERDESs 91      
Number of PLL_ADVs 2 6 33%  
Average Fanout of Non-Clock Nets 3.84      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Dec 13 17:20:32 20180591 Warnings (591 new)202 Infos (202 new)
Translation ReportCurrentThu Dec 13 17:20:41 201804 Warnings (0 new)4 Infos (0 new)
Map ReportCurrentThu Dec 13 17:21:36 20180132 Warnings (0 new)14 Infos (0 new)
Place and Route ReportCurrentThu Dec 13 17:22:05 2018025 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Dec 13 17:22:17 2018038 Warnings (0 new)4 Infos (0 new)
Bitgen ReportCurrentThu Dec 13 17:22:48 201802 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Dec 13 15:54:30 2018
WebTalk ReportCurrentThu Dec 13 17:22:49 2018
WebTalk Log FileCurrentThu Dec 13 17:22:54 2018

Date Generated: 12/13/2018 - 17:22:54