appsfpga Project Status (12/12/2018 - 10:43:11)
Project File: discovery4100.xise Parser Errors: No Errors
Module Name: appcore Implementation State: Programming File Not Generated
Target Device: xc5vlx50-2ff1153
  • Errors:
 
Product Version:ISE 14.5
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 3246 28800 11%
Number of Slice LUTs 2826 28800 9%
Number of fully used LUT-FF pairs 1933 4139 46%
Number of bonded IOBs 334 560 59%
Number of Block RAM/FIFO 33 48 68%
Number of BUFG/BUFGCTRLs 5 32 15%
Number of PLL_ADVs 1 6 16%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 12 10:14:56 2018   
Translation ReportCurrentWed Dec 12 10:16:17 2018   
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Dec 5 10:34:52 2018
WebTalk ReportCurrentWed Dec 12 10:43:04 2018
WebTalk Log FileCurrentWed Dec 12 10:43:10 2018

Date Generated: 12/12/2018 - 10:43:11