#select Device Used ORCA=0 TRIO=0 DIAMOND=1 #select loopback mode, 0-disable, 1-enable loopback_enable=0 #select Device Role, 1-Master, 0-Slave Master_nSlave=0 ################################ select parameters for on board Codec Configuration ######################################### #codec clock as master is configured fixed MCLK/4=3072k (mclk/4=3072, mclk/8=1536, mclk/16=768) #codec clock as salve-can be any clock #select Codec Role, 1-master, 0-slave [bits 6] codec_master_nslave=1 #codec Fsync can be 8k-0x0c 48k-0x00 96k-0x1c 16k - 0x14 codec_Fsync=0x14 #pcm_clock = 3072 then #select data width, 0=16bit, 1=20bit, 2=24bit, 3=32bit [bits 3:2] data_width=0 #select data offset, 1=offset 0,MSB on 1nd bit 0-offset 1, MSB on 2nd clock [bits 4] noffset=0 #select I2S/PCM mode, 3 - PCM mode (DSP mode), 2-I2S mode format=3 if (codec_Fsync==0x0c)then device_fSync=8000 elseif (codec_Fsync==0x00) then device_fSync=48000 elseif (codec_Fsync==0x1c) then device_fSync=96000 elseif (codec_Fsync==0x14) then device_fSync=16000 endif format_hex=format &0x3 noffset_hex=noffset<<4 codec_master_nslave_reg=codec_master_nslave<<6 data_width_hex=(data_width & 0x3)<<3 codec_config=data_width_hex|codec_master_nslave_reg|noffset_hex|format_hex ############################### end of on board codec configuration ############################################### ############################### Config Device PCM parameters ############################################### if (Master_nSlave) then Send_HCI_VS_Write_CODEC_Config 0xFD06, 3072, 0x00, device_fSync, 0x0001, 1, 0x00, 0x00, 16, 0x0001, 1, 16, 0x0001, 0, 0x00, 16, 17, 0x01, 16, 17, 0x00, 0x00 Wait_HCI_Command_Complete_VS_Write_CODEC_Config_Event 5000, any, HCI_VS_Write_CODEC_Config, 0x00 else Send_HCI_VS_Write_CODEC_Config 0xFD06, 3072, 0x01, device_fSync, 0x0001, 0, 0x00, 0x00, 0x0010, 0x0001, 1, 0x0010, 0x0001, 0, 0x00, 0x0010, 0x0011, 0x01, 0x0010, 0x0011, 0x00, 0x00 Wait_HCI_Command_Complete_VS_Write_CODEC_Config_Event 5000, any, HCI_VS_Write_CODEC_Config, 0x00 end if # TEMP - change Dout mode to "always output" Send_HCI_VS_Write_CODEC_Config_Enhanced 0xFD07, 0x00, 0x0000, 0x0000, 0x00, 0x04, 0x04, 0x01, 0x00, 0x000000, 0x00, 0x00, 0x04, 0x04, 0x01, 0x00, 0x000000, 0x00, 0x00 Wait_HCI_Command_Complete_VS_Write_CODEC_Config_Enhanced_Event 5000, any, HCI_VS_Write_CODEC_Config_Enhanced, 0x00 ###################################################################################################################### ########################## Mux I2C bus for codec configuration ################################################### if ORCA then Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A7c9c, 0x1600 Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00 Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7cac, 0x0010, 0x0010 Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 #Send_Set_IO_Pin_Mux_BTIP 0x10, 0x06 #Send_Set_IO_Pin_Mux_BTIP 0x0f, 0x06 Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001Af616, 0x6600, 0xff00 Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 #Send_Set_IO_Pin_Mux_Orca_top 0x11, 0x04 #Send_Set_IO_Pin_Mux_Orca_top 0x12, 0x04 #read value for restore Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x001A7c96 Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &ORCA_TOP_I2C Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7c96, 0x0404, 0x0f0f Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 #allowe I2C both on FM and Codec Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001a400c, 0x0001, 0x0003 Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 endif if TRIO then Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x1a7c8c Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &TRIO_I2C_TOP #select bt_func6,7 on top Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1a7c8c, 0x0000 Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00 #Send_Set_IO_Pin_Mux_BTIP 0x10, 0x06 #Send_Set_IO_Pin_Mux_BTIP 0x0f, 0x06 Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001Af616, 0x6600, 0xff00 Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 endif if DIAMOND then # Read BT_FUNC6_SEL Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x200ce122 Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &I2C_BTFUNC6_18xx # Read BT_FUNC7_SEL Send_HCI_VS_Read_Hardware_Register 0xFF00, 0x200ce124 Wait_HCI_Command_Complete_VS_Read_Hardware_Register_Event 5000, any, HCI_VS_Read_Hardware_Register, 0x00, &I2C_BTFUNC7_18xx #select bt_func6 on bt_func6 Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200ce122, 0x0000, 0x001f Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 #select bt_func7 on bt_func7 Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200ce124, 0x0000, 0x001f Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 # btfanc 6 --> sda & btfanc 7 --> scl Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200Ef516, 0x6600 Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00 # Send_Set_IO_Pin_Mux_BTIP 0x0f, 0x06 # Send_Set_IO_Pin_Mux_BTIP 0x10, 0x06 endif ################################# end I2C mux configuration ############################################################# ################################# This script is for WM8750 codec ################################################################# #CODEC ID = 0x1a #CODEC Register address=HEX{[I2C Sub Address]/2} # reset codec Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x1e, 0x01, "00" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 # set device power management Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x32, 0x01, "FE" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 # Enable All Analog inputs and outputs # DACL = (bit8) # DACR = (bit7) # Lout1 = (bit6) # Rout1 = (bit5) # Lout2 = (bit4) # Rout2 = (bit3) Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x35, 0x01, "FE" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 # set left line input (codec address = 0x00) vol = default, un-mute , bit 8 - update now (LIVU) Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x01, 0x01, "17" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 # set right line input (address = 0x02) vol = default, un-mute , update now (RIVU) Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x03, 0x01, "17" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 #Wait_HCI_Command_Complete_VS_Write_I2C_Register_Event 5000, any, 0xFE0E, 0x00 # digital path - unmute the DAC (bit4=0) Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x0a, 0x01, "00" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 #set codec left input to input2 , LINSEL=01 (bits 7:6)- sutable for 18xx HDMB and ORCA/TRIO MB Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x40, 0x01, "40" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 #set codec right input to input2 , RINSEL=01 (bits 7:6)- sutable for 18xx HDMB and ORCA/TRIO MB Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x42, 0x01, "40" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 #set left ADC to output (enable left dac to left mixer), left mixer volume set, bits 6:4, set to 0x1 Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x45, 0x01, "50" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 #set right ADC to output (enable right dac to right mixer) Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x4b, 0x01, "50" Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 #Wait_HCI_Command_Complete_VS_Write_I2C_Register_Event 5000, any, 0xFE0E, 0x00 # Digital Interface Activation-clocking & sample rate 8k-0x0c 48k-0x00 96k-0x1c 16k - 0x14 Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x10, 0x01, codec_Fsync Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 # PCM, MSB on 2nd bit, codec master=43 * # PCM, MSB on 2nd bit, codec slave=03 * # PCM, MSB on 1nd bit, codec master=53 # PCM, MSB on 1nd bit, codec slave=13 # I2S, MSB on 2nd clock, codec master=42 * # I2S, MSB on 2nd clock, codec slave=02 * Send_HCI_VS_Write_I2C_Register_Enhanced 0xFD36, 0x1a, 0, 100, 0x01, 0x0E, 0x01, codec_config Wait_HCI_Command_Complete_VS_Write_I2C_Register_Enhanced_Event 5000, any, HCI_VS_Write_I2C_Register_Enhanced, 0x00 ####################################### End of codec configuration WM8750 ########################################## ####################################### Restore I2C pads to their original function ################################## #for DIAMOND if DIAMOND then #restore bt_func6 top func Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200ce122, I2C_BTFUNC6_18xx, 0xffff Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 #restore bt_func7 top func Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200ce124, I2C_BTFUNC7_18xx, 0xffff Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 endif if ORCA then #restore FM_SCL/FM_SDA top func Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x001A7c96, ORCA_TOP_I2C, 0xffff Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 endif if TRIO then #restore bt_func6,7 on top Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x1a7c8c, TRIO_I2C_TOP Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00 endif ################################ end of pinmux restore ######################################### ################################ loopback mode ################################################# Send_HCI_VS_Set_Pcm_Loopback_Enable 0xFE28, 1 Wait_HCI_Command_Complete_VS_Set_Pcm_Loopback_Enable_Event 5000, any, HCI_VS_Set_Pcm_Loopback_Enable, 0x00 Exit Send_HCI_VS_Set_Pcm_Loopback_Enable 0xFE28, 0 Send_HCI_VS_Set_Pcm_Loopback_Enable 0xFE28, 1