/***********************************************************************************
 * DefaultInterruptHandlers.c
 * --------------------------
 * This file defines dummy interrupt handlers for interrupt vector locations that are
 * not used in the application and is a debugging aid.  For each dummy ISR, the interrupt
 * level/location in the interrupt vector is recorded in static variable, IntN, and an infinite
 * loop is entered.  The debugger can then halt the MCU and query IntN (or look at the routine
 * name on the stack) to see which interrupt level was not properly handled.
 * Note 1: This file SHOULD be automatically generated by Grace.
 * Note 2: This file's vector layout is specific to the MSP430F2274 MCU.
 * If an interrupt level is used, the lines below should contain a symbol definition of the
 * form "#define INTLVLnnISR isrSymbol" where nn is the interrupt level and isrSymbol is the
 * name of the external ISR (or some meaningful name if the level drives multiple ISRs)
 * ********************************************************************************** */
 
 // Interrupt levels and their explicitly defined ISRs for this application.
 //-------------------------------------------------------------------------
#define INTLVL15ISR PowerOn			// Defined by CCS, probably in c_init
#define INTLVL09ISR TIMERA0_ISR		// Virtual UART bit timing, 9600bps
#define INTLVL08ISR TIMERA1_ISR		// RTC clock ticks, 10bps
#define INTLVL07ISR AccelXcvrRx		// USCI A&B Rx
#define INTLVL06ISR AccelXcvrTx		// USCI A&B Tx
#define INTLVL03ISR Port2ISR		// Port 2: <7>: TxStringISR, <0>: XcvrSenISR


#include <msp430.h>

//	Global to save the interrupt # encountered.
extern int IntN = 0;

/*
 *  ======== Default interrupt hooks ======== 
 */
 
// Level 15
#ifndef INTLVL15ISR
void MY_RESET_ISR(void) {IntN = 15; while (1);}
#pragma vector=RESET_VECTOR
__interrupt void MY_RESET_ISR_HOOK(void) {MY_RESET_ISR();}
#endif

// Level 14
#ifndef INTLVL14ISR
void MY_NMI_ISR(void) {IntN = 14; while (1);}
#pragma vector=NMI_VECTOR
__interrupt void MY_NMI_ISR_HOOK(void){MY_NMI_ISR();}
#endif

// Level 13
#ifndef INTLVL13ISR
void MY_TIMERB0_ISR(void) {IntN = 13; while (1);}
#pragma vector=TIMERB0_VECTOR
__interrupt void MY_TIMERB0_ISR_HOOK(void) {MY_TIMERB0_ISR();}
#endif

// Level 12
#ifndef INTLVL12ISR
void MY_TIMERB1_ISR(void) {IntN = 12; while (1);}
#pragma vector=TIMERB1_VECTOR
__interrupt void MY_TIMERB1_ISR_HOOK(void) {MY_TIMERB1_ISR();}
#endif

// Level 11 (not used by hardware)

// Level 10
#ifndef INTLVL10ISR
void MY_WDT_ISR(void) {IntN = 10; while (1);}
#pragma vector=WDT_VECTOR
__interrupt void MY_WDT_ISR_HOOK(void) {MY_WDT_ISR();}
#endif

// Level 09
#ifndef INTLVL09ISR
void MY_TIMERA0_ISR(void) {IntN = 9; while (1);}
#pragma vector=TIMERA0_VECTOR
__interrupt void MY_TIMERA0_ISR_HOOK(void) {MY_TIMERA0_ISR();}
#endif

// Level 08
#ifndef INTLVL08ISR
void MY_TIMERA1_ISR(void) {IntN = 8; while (1);}
#pragma vector=TIMERA1_VECTOR
__interrupt void MY_TIMERA1_ISR_HOOK(void) {MY_TIMERA1_ISR();}
#endif

// Level 07
#ifndef INTLVL07ISR
void MY_USCIAB0RX_ISR(void) {IntN = 7; 	while (1);}
#pragma vector=USCIAB0RX_VECTOR
__interrupt void MY_USCIAB0RX_ISR_HOOK(void) {MY_USCIAB0RX_ISR();}
#endif

// Level 06
#ifndef INTLVL06ISR
void MY_USCIAB0TX_ISR(void) {IntN = 6; while (1);}
#pragma vector=USCIAB0TX_VECTOR
__interrupt void MY_USCIAB0TX_ISR_HOOK(void) {MY_USCIAB0TX_ISR();}
#endif

// Level 05
#ifndef INTLVL05ISR
void MY_ADC10_ISR(void) {IntN = 5; 	while (1);}
#pragma vector=ADC10_VECTOR
__interrupt void MY_ADC10_ISR_HOOK(void) {MY_ADC10_ISR();}
#endif

// Level 04 (not used by hardware)

// Level 03
#ifndef INTLVL03ISR
 void MY_PORT2_ISR(void) {IntN = 3; while (1);}
#pragma vector=PORT2_VECTOR
__interrupt void MY_PORT2_ISR_HOOK(void) {MY_PORT2_ISR();}
#endif

// Level 02
#ifndef INTLVL02ISR
void MY_PORT1_ISR(void) {IntN = 2; while (1);}
#pragma vector=PORT1_VECTOR
__interrupt void MY_PORT1_ISR_HOOK(void) {MY_PORT1_ISR();}
#endif

// Level 01 (not used by hardware)
// Level 00 (not used by hardware)

