//###########################################################################
/*
   FILE:	Test_Send4.c

   TITLE:	DSP28 CAN Transmit of 4 mailboxes
			sequential setting of TRS bits 0..3
			Polling of register TA until 0xF 
            100 Kbps, Extended Identifier 
			Mailboxes 0,1,2 and 3 in use
			Self Test Mode active,if bit ECanaRegs.CANMC.bit.STM = 1;
			for real physical CAN transmission set STM to zero.
*/
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.0 | 13 Apr 2010 | F.B. | test setup
//###########################################################################

#include "DSP281x_Device.h"

// External Prototype statements 
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitCpuTimers(void);
extern void ConfigCpuTimer(struct CPUTIMER_VARS *,float,float);

// Prototype statements for functions found within this file.

void Gpio_select(void);
void InitSystem(void);
void InitCan(void);
void prepare_MBx(void);
interrupt void cpu_timer0_isr(void);

struct ECAN_REGS ECanaShadow;

void main(void)
{
  InitSystem();  // Initialize the DSP's core Registers
  Gpio_select(); // Setup the GPIO Multiplex Registers
	
  InitPieCtrl();
  InitPieVectTable();
  EALLOW;
  PieVectTable.TINT0 = &cpu_timer0_isr;
  EDIS;
	
  InitCpuTimers();
  ConfigCpuTimer(&CpuTimer0,150,50000);
 
  InitCan();
  prepare_MBx();

  PieCtrlRegs.PIEIER1.bit.INTx7 = 1;  // TINT0
  IER |= 0x0001;
  IFR &= 0xFFFE;
  EINT;
  
  CpuTimer0Regs.TCR.bit.TSS = 0;

//++++++++++++++++++++++++++++++++++++++++++++++++
  while(1)
  {    
    if(CpuTimer0.InterruptCount >= 10)
    {
      //CpuTimer0.InterruptCount = 0;
	  CpuTimer0.InterruptCount = 0;
      ECanaMboxes.MBOX0.MDL.byte.BYTE0 = 0x00;
      ECanaMboxes.MBOX1.MDL.byte.BYTE0 = 0x11;
      ECanaMboxes.MBOX2.MDL.byte.BYTE0 = 0x22;
      ECanaMboxes.MBOX3.MDL.byte.BYTE0 = 0x33;
     
	  ECanaRegs.CANTRS.bit.TRS0 = 1;
	  ECanaRegs.CANTRS.bit.TRS1 = 1;
	  ECanaRegs.CANTRS.bit.TRS2 = 1;
	  ECanaRegs.CANTRS.bit.TRS3 = 1;;
	
	  while(ECanaRegs.CANTA.all != 0xF);
	  ECanaRegs.CANTA.all = 0xF;
	}
  }
} 	
//++++++++++++++++++++++++++++++++++++++++++++++++

interrupt void cpu_timer0_isr(void)
{
  EALLOW;
  SysCtrlRegs.WDKEY = 0x55;
  SysCtrlRegs.WDKEY = 0xAA;
  EDIS;
  CpuTimer0.InterruptCount++;
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}


void Gpio_select(void)
{
  EALLOW;
  GpioMuxRegs.GPAMUX.all = 0x0000;	// all GPIO port Pin's to I/O
  GpioMuxRegs.GPBMUX.all = 0x0000;   
  GpioMuxRegs.GPDMUX.all = 0x0000;
  GpioMuxRegs.GPEMUX.all = 0x0000; 
    
  GpioMuxRegs.GPFMUX.all = 0x0000;
  GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
  GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;

  GpioMuxRegs.GPGMUX.all = 0x0000;			

  GpioMuxRegs.GPADIR.all = 0x0040;	// GPIO PORT  as input; A6 output
  GpioMuxRegs.GPBDIR.all = 0x00FF;	// GPIO Port B15-B8 input , B7-B0 output
  GpioMuxRegs.GPDDIR.all = 0x0000;	// GPIO PORT  as input
  GpioMuxRegs.GPEDIR.all = 0x0000;	// GPIO PORT  as input
  GpioMuxRegs.GPFDIR.all = 0x0000;	// GPIO PORT  as input
  GpioMuxRegs.GPGDIR.all = 0x0000;	// GPIO PORT  as input

  GpioMuxRegs.GPAQUAL.all = 0x0000;	// Set GPIO input qualifier values to zero
  GpioMuxRegs.GPBQUAL.all = 0x0000;
  GpioMuxRegs.GPDQUAL.all = 0x0000;
  GpioMuxRegs.GPEQUAL.all = 0x0000;
  EDIS;
}     

void InitSystem(void)
{
  EALLOW;
  SysCtrlRegs.WDCR= 0x00AE;         // Setup the watchdog 
  SysCtrlRegs.PLLCR.bit.DIV = 10;   // Setup the Clock PLL to multiply by 5
  SysCtrlRegs.SCSR = 0x0;           // Watchdog(WDENINT)to generate a RESET
  SysCtrlRegs.HISPCP.all = 0x0001;  // Setup Highspeed Clock Prescaler to divide by 2
  SysCtrlRegs.LOSPCP.all = 0x0002;  // Setup Lowspeed CLock Prescaler to divide by 4
      	
  // Peripheral clock enables set for the selected peripherals.   
  SysCtrlRegs.PCLKCR.bit.EVAENCLK=0;
  SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;
  SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0;
  SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0;
  SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;
  SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;
  SysCtrlRegs.PCLKCR.bit.ECANENCLK=1;
  SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;
  EDIS;
}

void InitCan(void)
{
  EALLOW;
  ECanaRegs.CANTIOC.bit.TXFUNC = 1;
  ECanaRegs.CANRIOC.bit.RXFUNC = 1;
  ECanaRegs.CANMC.bit.SCB = 1;  // HECC mode
  ECanaRegs.CANMC.bit.CCR = 1;
  while(ECanaRegs.CANES.bit.CCE == 0);
  ECanaRegs.CANBTC.bit.BRPREG = 99;
  ECanaRegs.CANBTC.bit.TSEG1REG = 10;
  ECanaRegs.CANBTC.bit.TSEG2REG = 2;
  ECanaRegs.CANBTC.bit.SJWREG = 1;  // SJW = 2*Tq
  ECanaRegs.CANBTC.bit.SAM = 0;  // one sample at sample point
  ECanaRegs.CANMC.bit.CCR = 0;
  ECanaRegs.CANMC.bit.STM = 0;  // self-test mode 1=ON ; 0=OFF
								// physical transmission with STM = 0
  ECanaRegs.CANMC.bit.CCR = 0;
  while(ECanaRegs.CANES.bit.CCE == 1);
  ECanaRegs.CANME.all = 0;  //disable all mailboxes
  EDIS;
}

void prepare_MBx(void)
{
  // ----------- use shadow-register -------------------------------
  ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
  ECanaShadow.CANME.all = ECanaRegs.CANME.all;
  
  // MB#0
  ECanaMboxes.MBOX0.MSGID.all = 0;
  ECanaMboxes.MBOX0.MSGID.all = 0x100;
  ECanaMboxes.MBOX0.MSGID.bit.IDE = 1;    // Ext. Identifier
  ECanaMboxes.MBOX0.MSGCTRL.all = 0;
  ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 1;
  ECanaShadow.CANMD.bit.MD0 = 0;          // transmit
  ECanaShadow.CANME.bit.ME0 = 1;          // enable Mailbox #0
  
  // MB#1
  ECanaMboxes.MBOX1.MSGID.all = 0;
  ECanaMboxes.MBOX1.MSGID.all = 0x101;
  ECanaMboxes.MBOX1.MSGID.bit.IDE = 1;    // Ext. Identifier
  ECanaMboxes.MBOX1.MSGCTRL.all = 0;
  ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 1;
  ECanaShadow.CANMD.bit.MD1 = 0;          // transmit
  ECanaShadow.CANME.bit.ME1 = 1;          // enable Mailbox #1
  // MB#2
  ECanaMboxes.MBOX2.MSGID.all = 0;
  ECanaMboxes.MBOX2.MSGID.all = 0x102;
  ECanaMboxes.MBOX2.MSGID.bit.IDE = 1;    // Ext. Identifier
  ECanaMboxes.MBOX2.MSGCTRL.all = 0;
  ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 1;
  ECanaShadow.CANMD.bit.MD2 = 0;          // transmit
  ECanaShadow.CANME.bit.ME2 = 1;          // enable Mailbox #2
  // MB#3
  ECanaMboxes.MBOX3.MSGID.all = 0;
  ECanaMboxes.MBOX3.MSGID.all = 0x103;
  ECanaMboxes.MBOX3.MSGID.bit.IDE = 1;    // Ext. Identifier
  ECanaMboxes.MBOX3.MSGCTRL.all = 0;
  ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 1;
  ECanaShadow.CANMD.bit.MD3 = 0;          // transmit
  ECanaShadow.CANME.bit.ME3 = 1;          // enable Mailbox #3

  ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
  ECanaRegs.CANME.all = ECanaShadow.CANME.all;
  // ----------- use shadow-register -------------------------------
}

//===========================================================================
// End of SourceCode.
//===========================================================================