void SPI_Init()
{
// Initialize SPI FIFO registers
    SpiaRegs.SPIFFTX.bit.SPIRST     = 1;       // enable fifo - 0xE040;
    SpiaRegs.SPIFFTX.bit.SPIFFENA   = 1;       // enable fifo enhancements
    
    SpiaRegs.SPIFFTX.bit.TXFIFO     = 1;       // re-enable tx fifo
    SpiaRegs.SPIFFTX.bit.TXFFIENA   = 0;       // disable tx fifo int based on txffil match
    SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;       // clr TXFFINT flag in SPIFFTX

    SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;      // re-enable rx fifo
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR  = 1;      // clr RXFFINT flag in SPIFFRX
    SpiaRegs.SPIFFRX.bit.RXFFIENA    = 0;      // disable rx fifo int based on rxffil match

    SpiaRegs.SPIFFCT.all=0x0;                  // no time space between consecutive words in a packet

// Initialize SPI registers
    SpiaRegs.SPICCR.bit.SPISWRESET  = 0;       // reset SPI - 0x000F
    SpiaRegs.SPICCR.bit.SPILBK      = 0;       // no loop back
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 1;       // clk polarity is rising edge
    SpiaRegs.SPICCR.bit.SPICHAR     = 0x9;     // data length = 10b

    SpiaRegs.SPICTL.bit.OVERRUNINTENA = 0;     // disable rx overrun flag bit interrupts (SPISTS.7)
    SpiaRegs.SPICTL.bit.CLK_PHASE     = 0;     // Enable normal phase - 0x0002
    SpiaRegs.SPICTL.bit.MASTER_SLAVE  = 1;     // master mode
    SpiaRegs.SPICTL.bit.TALK          = 1;     // enable talk
    SpiaRegs.SPICTL.bit.SPIINTENA     = 0;     // SPI int disable

    SpiaRegs.SPIBRR = 11;                       // Baud rate

    SpiaRegs.SPICCR.bit.SPISWRESET    = 1;     // Relinquish SPI from Reset

    SpiaRegs.SPIPRI.bit.FREE          = 1;     // Set so breakpoints don't disturb xmission
    SpiaRegs.SPIPRI.bit.STEINV        = 0;     // SPISTE pin in normal mode (no inversion)
    SpiaRegs.SPIPRI.bit.TRIWIRE       = 0;     // 4 wire SPI
}

void SPI_Tx()
{
    // send out data
    SpiaRegs.SPITXBUF = 0;          //  TX 0x0000 to generate 10 clks for slave
    SpiaRegs.SPITXBUF = 0;          //  TX 0x0000 to generate 10 more clks for slave
}

void SPI_Rx()
{
    int16 i;

    // read out RXFIFO to empty it
    for (i=0; SpiaRegs.SPIFFRX.bit.RXFFST; i++)
        data[i] = SpiaRegs.SPIRXBUF;     

    // Clr RXFIFO interrupts
    #warn next two lines are likely not needed.  Check before release.
    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1;
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1;    
}