Software (GEL file): GEL_ONTARGERCONNECT: 0 OnTargetConnect( ) 1 { 2 GEL_TextOut( "\nDM6437 Startup Sequence\n\n" ); 3 4 Setup_Cache( ); // Setup L1P/L1D Cache 5 Setup_Pin_Mux( ); // Setup Pin Mux 6 Setup_Psc_All_On( ); // Setup All Power Domains 7 8 Setup_PLL1_378_MHz_OscIn( ); // Setup Pll1 [DSP @ 378MHz][1.20V] 9 Setup_PLL2_DDR_162_MHz_OscIn( );// Setup Pll2 [VPSS @ 54MHz, DDR @ 162MHz] 10 Setup_DDR_162_MHz( ); // Setup DDR2 [162MHz] 11 CheckDDR (); 12 GEL_TextOut( "\nStartup Complete.\n\n" ); 13 } GEL_SETUPPLL1: 0 setup_pll_1( int clock_source, int pll_multiplier ) 1 { 2 unsigned int* pll_ctl = ( unsigned int* )( 0x01c40900 ); 3 unsigned int* pll_pllm = ( unsigned int* )( 0x01c40910 ); 4 unsigned int* pll_cmd = ( unsigned int* )( 0x01c40938 ); 5 unsigned int* pll_stat = ( unsigned int* )( 0x01c4093c ); 6 unsigned int* pll_div1 = ( unsigned int* )( 0x01c40918 ); 7 unsigned int* pll_div2 = ( unsigned int* )( 0x01c4091c ); 8 unsigned int* pll_div3 = ( unsigned int* )( 0x01c40920 ); 9 unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c4092c ); 10 11 int pll1_freq = 27 * ( pll_multiplier + 1 ); 12 int div1 = 0; 13 int div2 = 2; 14 int div3 = 5; 15 int bypass_div = 0; 16 int power_up_pll = ( *pll_ctl & 0x0002 ) >> 1; 17 18 GEL_TextOut( "Setup PLL1 " ); 19 20 /* 21 * Step 0 - Ignore request if the PLL is already set as is 22 */ 23 if ( ( ( *pll_ctl & 0x0100 ) >> 8 ) == clock_source ) 24 { 25 if ( ( *pll_pllm & 0x3f ) == ( pll_multiplier & 0x3f ) ) 26 { 27 if ( ( ( *pll_div1 & 0x1f ) == div1 ) 28 || ( ( *pll_div2 & 0x1f ) == div2 ) 29 || ( ( *pll_div3 & 0x1f ) == div3 ) ) 30 { 31 GEL_TextOut( "(DSP = %d MHz + ",,,,, pll1_freq / ( div1 + 1 ) ); 32 GEL_TextOut( "SYSCLK2 = %d MHz + ",,,,, pll1_freq / ( div2 + 1 ) ); 33 GEL_TextOut( "SYSCLK3 = %d MHz + ",,,,, pll1_freq / ( div3 + 1 ) ); 34 if ( clock_source == 0 ) 35 GEL_TextOut( "Onchip Oscillator)... " ); 36 else 37 GEL_TextOut( "External Clock)... " ); 38 GEL_TextOut( "[Already Set]\n" ); 39 return; 40 } 41 } 42 } 43 44 /* 45 * Step 1 - Set clock mode 46 */ 47 if ( power_up_pll == 1 ) 48 { 49 GEL_TextOut( "(Powering up PLL)... " ); 50 if ( clock_source == 0 ) 51 *pll_ctl &= ~0x0100; // Onchip Oscillator 52 else 53 *pll_ctl |= 0x0100; // External Clock 54 } 55 56 /* 57 * Step 2 - Set PLL to bypass 58 * - Wait for PLL to stabilize 59 */ 60 *pll_ctl &= ~0x0021; 61 _wait( 150 ); 62 63 /* 64 * Step 3 - Reset PLL 65 */ 66 *pll_ctl &= ~0x0008; 67 68 /* 69 * Step 4 - Disable PLL 70 * Step 5 - Powerup PLL 71 * Step 6 - Enable PLL 72 * Step 7 - Wait for PLL to stabilize 73 */ 74 if ( power_up_pll == 1 ) 75 { 76 *pll_ctl |= 0x0010; // Disable PLL 77 *pll_ctl &= ~0x0002; // Power up PLL 78 *pll_ctl &= ~0x0010; // Enable PLL 79 _wait( 150 ); // Wait for PLL to stabilize 80 } 81 else 82 *pll_ctl &= ~0x0010; // Enable PLL 83 84 /* 85 * Step 8 - Load PLL multiplier 86 */ 87 *pll_pllm = pll_multiplier & 0x3f; 88 89 /* 90 * Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio ) 91 * 1:DSP, 2:SCR,EMDA,VPSS, 3:Peripherals 92 */ 93 *pll_bpdiv = 0x8000 | bypass_div; // Bypass divider 94 *pll_div1 = 0x8000 | div1; // Divide-by-1 or Divide-by-2 95 *pll_div2 = 0x8000 | div2; // Divide-by-3 or Divide-by-6 96 *pll_div3 = 0x8000 | div3; // Divide-by-6 or Divide-by-12 97 *pll_cmd |= 0x0001; // Set phase alignment 98 while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment 99 _wait( 2000 ); 100 101 /* 102 * Step 10 - Wait for PLL to reset ( 2000 cycles ) 103 * Step 11 - Release from reset 104 */ 105 *pll_ctl |= 0x0008; 106 _wait( 2000 ); 107 108 /* 109 * Step 12 - Wait for PLL to re-lock ( 2000 cycles ) 110 * Step 13 - Switch out of BYPASS mode 111 */ 112 GEL_TextOut( "PLL OFF!!!" ); 113 *pll_ctl |= 0x0001; 114 _wait( 2000 ); 115 GEL_TextOut( "PLL ON!!!" ); 116 117 pll1_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 ); 118 div1 = ( *pll_div1 & 0x1f ); 119 div2 = ( *pll_div2 & 0x1f ); 120 div3 = ( *pll_div3 & 0x1f ); 121 122 GEL_TextOut( "(DSP = %d MHz + ",,,,, pll1_freq / ( div1 + 1 ) ); 123 GEL_TextOut( "SYSCLK2 = %d MHz + ",,,,, pll1_freq / ( div2 + 1 ) ); 124 GEL_TextOut( "SYSCLK3 = %d MHz + ",,,,, pll1_freq / ( div3 + 1 ) ); 125 126 if ( clock_source == 0 ) 127 GEL_TextOut( "Onchip Oscillator)... " ); 128 else 129 GEL_TextOut( "External Clock)... " ); 130 GEL_TextOut( "[Done]\n" ); 131 } GEL_SETUPCACHE: 0 Setup_Cache( ) 1 { 2 int l1p, l1d, l2; 3 4 GEL_TextOut( "Setup Cache " ); 5 #define CACHE_L2CFG *( unsigned int* )( 0x01840000 ) 6 #define CACHE_L2INV *( unsigned int* )( 0x01845008 ) 7 #define CACHE_L1PCFG *( unsigned int* )( 0x01840020 ) 8 #define CACHE_L1PINV *( unsigned int* )( 0x01845028 ) 9 #define CACHE_L1DCFG *( unsigned int* )( 0x01840040 ) 10 #define CACHE_L1DINV *( unsigned int* )( 0x01845048 ) 11 12 CACHE_L1PINV = 1; // L1P invalidated 13 CACHE_L1PCFG = 7; // L1P on, MAX size 14 15 CACHE_L1DINV = 1; // L1D invalidated 16 CACHE_L1DCFG = 7; // L1D on, MAX size 17 18 CACHE_L2INV = 1; // L2 invalidated 19 CACHE_L2CFG = 0; // L2 off, use as RAM 20 21 l1p = CACHE_L1PCFG; 22 if ( l1p == 0 ) 23 GEL_TextOut( "(L1P = 0K) + " ); 24 if ( l1p == 1 ) 25 GEL_TextOut( "(L1P = 4K) + " ); 26 if ( l1p == 2 ) 27 GEL_TextOut( "(L1P = 8K) + " ); 28 if ( l1p == 3 ) 29 GEL_TextOut( "(L1P = 16K) + " ); 30 if ( l1p >= 4 ) 31 GEL_TextOut( "(L1P = 32K) + " ); 32 33 l1d = CACHE_L1DCFG; 34 if ( l1d == 0 ) 35 GEL_TextOut( "(L1D = 0K) + " ); 36 if ( l1d == 1 ) 37 GEL_TextOut( "(L1D = 4K) + " ); 38 if ( l1d == 2 ) 39 GEL_TextOut( "(L1D = 8K) + " ); 40 if ( l1d == 3 ) 41 GEL_TextOut( "(L1D = 16K) + " ); 42 if ( l1d >= 4 ) 43 GEL_TextOut( "(L1D = 32K) + " ); 44 45 l2 = CACHE_L2CFG; 46 if ( l2 == 0 ) 47 GEL_TextOut( "(L2 = 0K)... " ); 48 else if ( l2 == 1 ) 49 GEL_TextOut( "(L2 = 32K)... " ); 50 else if ( l2 == 2 ) 51 GEL_TextOut( "(L2 = 64K)... " ); 52 else if ( l2 == 3 ) 53 GEL_TextOut( "(L2 = 128K)... " ); 54 else if ( l2 == 4 ) 55 GEL_TextOut( "(L2 = 256K)... " ); 56 else if ( l2 > 4 ) 57 GEL_TextOut( "(L2 = MAX CACHE)... " ); 58 59 GEL_TextOut( "[Done]\n" ); 60 } GEL_SETUPPINMUX: 0 Setup_Pin_Mux( ) 1 { 2 #define PINMUX0 *( unsigned int* )( 0x01C40000 ) 3 #define PINMUX1 *( unsigned int* )( 0x01C40004 ) 4 #define VDD3P3V_PWDN *( unsigned int* )( 0x01C40048 ) 5 6 GEL_TextOut( "PinMux setup.. " ); 7 8 PINMUX0 = 0x00040101; 9 10 PINMUX1 = 0x01404140; 11 12 VDD3P3V_PWDN = 0x00000000; // Everything on 13 14 GEL_TextOut( "[Done]\n" ); 15 } GEL_SETUPPSC: 0 Setup_Psc_All_On( ) 1 { 2 int i; 3 GEL_TextOut( "Setup Power Modules (All on)... " ); 4 5 /* 6 * Enable all non-reserved power modules 7 */ 8 for ( i = 0 ; i <= 9 ; i++ ) 9 psc_change_state( i, 3 ); 10 for ( i = 11 ; i <= 28 ; i++ ) 11 psc_change_state( i, 3 ); 12 i = 39; 13 psc_change_state( i, 3 ); 14 15 GEL_TextOut( "[Done]\n" ); 16 } SOURCE_MAIN: 0 void main( void ) 1 { 2 unsigned int* pll_ctl = ( unsigned int* )( 0x01c40900 ); 3 unsigned int* wdt_tgcr = ( unsigned int* )( 0x01c21424 ); 4 unsigned int* wdt_wdtcr = ( unsigned int* )( 0x01c21420 ); 5 unsigned int* timerctl = ( unsigned int* )( 0x01c40084 ); 6 7 Setup_Cache( ); // Setup L1P/L1D Cache 8 Setup_Pin_Mux( ); // Setup Pin Mux 9 Setup_Psc_All_On( ); // Setup All Power Domains 10 11 GPIO_DIR01 = 0xFFFFFFFE; 12 GPIO_DIR6 = 0xFFFFFFDF; 13 14 GPIO_OUT_DATA01 = 0x00000001; 15 16 Setup_PLL_1( 13 ); // Setup Pll1 [DSP @ 378 MHz][1.20V] 17 *pll_ctl |= 0x0001; 18 GPIO_OUT_DATA6 = 0x00000020; 19 Setup_PLL_2( ); // Setup Pll2 [VPSS @ 54 MHz, DDR @ 162MHz] 20 Setup_DDR2( ); // Setup DDR2 [162 MHz] 21 22 Setup_UART(); 23 24 while( EVMDM6437_UART_xmtReady( uart0 ) ) 25 { 26 EVMDM6437_UART_getChar( uart0, &rx ); 27 rx; 28 EVMDM6437_UART_putChar( uart0, 0x39 ); 29 } 30 31 EVMDM6437_UART_putChar( uart0, 'F' ); 32 EVMDM6437_UART_putChar( uart0, 'I' ); 33 EVMDM6437_UART_putChar( uart0, 'N' ); 34 EVMDM6437_UART_putChar( uart0, 'E' ); 35 for(;;); 36 } SOURCE_SETUPCACHE: 0 Setup_Cache( ) 1 { 2 CACHE_L1PINV = 1; // L1P invalidated 3 CACHE_L1PCFG = 7; // L1P on, MAX size 4 CACHE_L1DINV = 1; // L1D invalidated 5 CACHE_L1DCFG = 7; // L1D on, MAX size 6 CACHE_L2INV = 1; // L2 invalidated 7 CACHE_L2CFG = 0; // L2 off, use as RAM 8 } SOURCE_SETUPPINMUX: 0 Setup_Pin_Mux( ) 1 { 2 CFG_PINMUX0 = 0x00040101; 3 4 CFG_PINMUX1 = 0x01004140; 5 6 CFG_VDD3P3V_PWDN = 0x00000000; // Everything on 7 } SOURCE_SETUPPSC: 0 Setup_Psc_All_On( ) 1 { 2 //VPSS (MASTER) 3 psc_change_state( 0, 3 ); 4 //VPSS (SLAVE) 5 psc_change_state( 1, 3 ); 6 //EDMACC 7 psc_change_state( 2, 3 ); 8 //EDMATC0 9 psc_change_state( 3, 3 ); 10 //EDMATC1 11 psc_change_state( 4, 3 ); 12 //EDMATC2 13 psc_change_state( 5, 3 ); 14 //EMAC Memory Controller 15 psc_change_state( 6, 3 ); 16 //MDIO 17 psc_change_state( 7, 3 ); 18 //EMAC 19 psc_change_state( 8, 3 ); 20 //McASP0 21 psc_change_state( 9, 3 ); 22 //VLYNQ 23 psc_change_state( 11, 3 ); 24 //HPI 25 psc_change_state( 12, 3 ); 26 //DDR2 Memory Controller 27 psc_change_state( 13, 3 ); 28 //EMIFA 29 psc_change_state( 14, 3 ); 30 //PCI 31 psc_change_state( 15, 3 ); 32 //McBSP0 33 psc_change_state( 16, 3 ); 34 //McBSP1 35 psc_change_state( 17, 3 ); 36 //I2C 37 psc_change_state( 18, 3 ); 38 //UART0 39 psc_change_state( 19, 3 ); 40 //UART1 41 psc_change_state( 20, 3 ); 42 //RESERVED - Write 43 psc_change_state( 21, 3 ); 44 //HECC 45 psc_change_state( 22, 3 ); 46 //PWM0 47 psc_change_state( 23, 3 ); 48 //PWM1 49 psc_change_state( 24, 3 ); 50 //PWM2 51 psc_change_state( 25, 3 ); 52 //GPIO 53 psc_change_state( 26, 3 ); 54 //TIMER0 55 psc_change_state( 27, 3 ); 56 //TIMER1 57 psc_change_state( 28, 3 ); 58 //C64x+ CPU 59 psc_change_state( 39, 3 ); 60 } SOURCE_PSCCHANGESTATE: 0 psc_change_state( int id, int state ) 1 { 2 unsigned int* mdstat = ( unsigned int* )( 0x01c41800 + ( 4 * id ) ); 3 unsigned int* mdctl = ( unsigned int* )( 0x01c41a00 + ( 4 * id ) ); 4 5 /* 6 * Step 0 - Ignore request if the state is already set as is 7 */ 8 if ( ( *mdstat & 0x1f ) == state ) 9 return; 10 11 /* 12 * Step 1 - Wait for PTSTAT.GOSTAT to clear 13 */ 14 while( PSC_PTSTAT & 1 ); 15 16 /* 17 * Step 2 - Set MDCTLx.NEXT to new state 18 */ 19 *mdctl &= ~0x1f; 20 *mdctl |= state; 21 22 /* 23 * Step 3 - Start power transition ( set PTCMD.GO to 1 ) 24 */ 25 PSC_PTCMD = 1; 26 27 /* 28 * Step 4 - Wait for PTSTAT.GOSTAT to clear 29 */ 30 while( PSC_PTSTAT & 1 ); 31 32 /* 33 * Step 5 - Verify state changed 34 */ 35 while( ( *mdstat & 0x1f ) != state ); 36 } SOURCE_SETUPPLL1: 0 Setup_PLL_1( unsigned int value ) 1 { 2 unsigned int* pll_ctl = ( unsigned int* )( 0x01c40900 ); 3 unsigned int* pll_pllm = ( unsigned int* )( 0x01c40910 ); 4 unsigned int* pll_cmd = ( unsigned int* )( 0x01c40938 ); 5 unsigned int* pll_stat = ( unsigned int* )( 0x01c4093c ); 6 unsigned int* pll_div1 = ( unsigned int* )( 0x01c40918 ); 7 unsigned int* pll_div2 = ( unsigned int* )( 0x01c4091c ); 8 unsigned int* pll_div3 = ( unsigned int* )( 0x01c40920 ); 9 unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c4092c ); 10 11 int clock_source = 0; 12 int pll_mult = value; 13 14 int div1 = 0; 15 int div2 = 2; 16 int div3 = 5; 17 int bypass_div = 0; 18 int power_up_pll = ( *pll_ctl & 0x0002 ) >> 1; 19 20 /* 21 * Step 0 - Ignore request if the PLL is already set as is 22 */ 23 if ( ( ( *pll_ctl & 0x0100 ) >> 8 ) == clock_source ) 24 { 25 if ( ( *pll_pllm & 0x3f ) == ( pll_mult & 0x3f ) ) 26 { 27 if ( ( ( *pll_div1 & 0x1f ) == div1 ) 28 || ( ( *pll_div2 & 0x1f ) == div2 ) 29 || ( ( *pll_div3 & 0x1f ) == div3 ) ) 30 { 31 return; 32 } 33 } 34 } 35 36 /* 37 * Step 1 - Set clock mode 38 */ 39 if ( power_up_pll == 1 ) 40 { 41 if ( clock_source == 0 ) 42 *pll_ctl &= ~0x0100; // Onchip Oscillator 43 else 44 *pll_ctl |= 0x0100; // External Clock 45 } 46 47 /* 48 * Step 2 - Set PLL to bypass 49 * - Wait for PLL to stabilize 50 */ 51 *pll_ctl &= ~0x0021; 52 53 wait( 5000 ); 54 55 /* 56 * Step 3 - Reset PLL 57 */ 58 *pll_ctl &= ~0x0008; 59 60 wait( 200 ); 61 /* 62 * Step 4 - Disable PLL 63 * Step 5 - Powerup PLL 64 * Step 6 - Enable PLL 65 * Step 7 - Wait for PLL to stabilize 66 */ 67 if ( power_up_pll == 1 ) 68 { 69 *pll_ctl |= 0x0010; // Disable PLL 70 wait( 5000 ); // Wait for PLL to stabilize 71 *pll_ctl &= ~0x0002; // Power up PLL 72 wait( 5000 ); // Wait for PLL to stabilize 73 *pll_ctl &= ~0x0010; // Enable PLL 74 75 wait( 5000 ); // Wait for PLL to stabilize 76 } 77 else 78 *pll_ctl &= ~0x0010; // Enable PLL 79 80 /* 81 * Step 8 - Load PLL multiplier 82 */ 83 *pll_pllm = pll_mult & 0x3f; 84 85 /* 86 * Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio ) 87 * 1:DSP, 2:SCR,EMDA,VPSS, 3:Peripherals 88 */ 89 *pll_bpdiv = 0x8000 | bypass_div; // Bypass divider 90 *pll_div1 = 0x8000 | div1; // Divide-by-1 or Divide-by-2 91 *pll_div2 = 0x8000 | div2; // Divide-by-3 or Divide-by-6 92 *pll_div3 = 0x8000 | div3; // Divide-by-6 or Divide-by-12 93 *pll_cmd |= 0x0001; // Set phase alignment 94 while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment 95 96 wait( 5000 ); 97 98 /* 99 * Step 10 - Wait for PLL to reset ( 2000 cycles ) 100 * Step 11 - Release from reset 101 */ 102 *pll_ctl |= 0x0008; 103 104 wait( 50000 ); 105 106 /* 107 * Step 12 - Wait for PLL to re-lock ( 2000 cycles ) 108 * Step 13 - Switch out of BYPASS mode 109 */ 110// *pll_ctl |= 0x0001; 111 wait( 5000 ); 112 wait(1 ); 113 }