/*
 * Hardware modules present on the DRA7xx chips
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 *
 * Paul Walmsley
 * Benoit Cousson
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/i2c-omap.h>

#include <linux/omap-dma.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/iommu-omap.h>
#include <plat/dmtimer.h>

#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_7xx.h"
#include "cm2_7xx.h"
#include "prm7xx.h"
#include "prm-regbits-7xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"

/* Base offset for all DRA7XX interrupts external to MPUSS */
#define DRA7XX_IRQ_GIC_START	32

/* Base offset for all DRA7XX dma requests */
#define DRA7XX_DMA_REQ_START	1


/*
 * IP blocks
 */

/*
 * 'dmm' class
 * instance(s): dmm
 */
static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
	.name	= "dmm",
};

/* dmm */
static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
	{ .irq = 113 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_dmm_hwmod = {
	.name		= "dmm",
	.class		= &dra7xx_dmm_hwmod_class,
	.clkdm_name	= "emif_clkdm",
	.mpu_irqs	= dra7xx_dmm_irqs,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'emif_ocp_fw' class
 * instance(s): emif_ocp_fw
 */
static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
	.name	= "emif_ocp_fw",
};

/* emif_ocp_fw */
static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
	.name		= "emif_ocp_fw",
	.class		= &dra7xx_emif_ocp_fw_hwmod_class,
	.clkdm_name	= "emif_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'l3' class
 * instance(s): l3_instr, l3_main_1, l3_main_2
 */
static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
	.name	= "l3",
};

/* l3_instr */
static struct omap_hwmod dra7xx_l3_instr_hwmod = {
	.name		= "l3_instr",
	.class		= &dra7xx_l3_hwmod_class,
	.clkdm_name	= "l3instr_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/* l3_main_1 */
static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
	{ .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
	{ .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
	{ .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
	.name		= "l3_main_1",
	.class		= &dra7xx_l3_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.mpu_irqs	= dra7xx_l3_main_1_irqs,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
		},
	},
};

/* l3_main_2 */
static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
	.name		= "l3_main_2",
	.class		= &dra7xx_l3_hwmod_class,
	.clkdm_name	= "l3instr_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'l4' class
 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 */
static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
	.name	= "l4",
};

/* l4_cfg */
static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
	.name		= "l4_cfg",
	.class		= &dra7xx_l4_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
		},
	},
};

/* l4_per1 */
static struct omap_hwmod dra7xx_l4_per1_hwmod = {
	.name		= "l4_per1",
	.class		= &dra7xx_l4_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/* l4_per2 */
static struct omap_hwmod dra7xx_l4_per2_hwmod = {
	.name		= "l4_per2",
	.class		= &dra7xx_l4_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/* l4_per3 */
static struct omap_hwmod dra7xx_l4_per3_hwmod = {
	.name		= "l4_per3",
	.class		= &dra7xx_l4_hwmod_class,
	.clkdm_name	= "l4per3_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/* l4_wkup */
static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &dra7xx_l4_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'mpu_bus' class
 * instance(s): mpu_private
 */
static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
	.name	= "mpu_bus",
};

/* mpu_private */
static struct omap_hwmod dra7xx_mpu_private_hwmod = {
	.name		= "mpu_private",
	.class		= &dra7xx_mpu_bus_hwmod_class,
	.clkdm_name	= "mpu_clkdm",
	.prcm = {
		.omap4 = {
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/*
 * 'ocp_wp_noc' class
 * instance(s): ocp_wp_noc
 */
static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
	.name	= "ocp_wp_noc",
};

/* ocp_wp_noc */
static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
	.name		= "ocp_wp_noc",
	.class		= &dra7xx_ocp_wp_noc_hwmod_class,
	.clkdm_name	= "l3instr_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'atl' class
 *
 */

static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
	.name	= "atl",
};

/* atl */
static struct omap_hwmod dra7xx_atl_hwmod = {
	.name		= "atl",
	.class		= &dra7xx_atl_hwmod_class,
	.clkdm_name	= "atl_clkdm",
	.main_clk	= "atl_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'bb2d' class
 *
 */

static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
	.name	= "bb2d",
};

/* bb2d */
static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
	{ .irq = 125 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_bb2d_hwmod = {
	.name		= "bb2d",
	.class		= &dra7xx_bb2d_hwmod_class,
	.clkdm_name	= "dss_clkdm",
	.mpu_irqs	= dra7xx_bb2d_irqs,
	.main_clk	= "dpll_core_h24x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'counter' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
	.name	= "counter",
	.sysc	= &dra7xx_counter_sysc,
};

/* counter_32k */
static struct omap_hwmod dra7xx_counter_32k_hwmod = {
	.name		= "counter_32k",
	.class		= &dra7xx_counter_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE,
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'ctrl_module' class
 *
 */

static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
	.name	= "ctrl_module",
};

/* ctrl_module_wkup */
static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
	.name		= "ctrl_module_wkup",
	.class		= &dra7xx_ctrl_module_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.prcm = {
		.omap4 = {
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
};

/*
 * 'gmac' class
 * cpsw/gmac sub system
 */
static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x8,
	.syss_offs	= 0x4,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
			   MSTANDBY_NO),
	.sysc_fields	= &omap_hwmod_sysc_type3,
};

static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
	.name		= "gmac",
	.sysc		= &dra7xx_gmac_sysc,
};

static struct omap_hwmod_irq_info dra7xx_gmac_irqs[] = {
	{ .name = "c0_rx_thresh_pend", .irq = 50 + DRA7XX_IRQ_GIC_START, },
	{ .name = "c0_rx_pend", .irq = 51 + DRA7XX_IRQ_GIC_START, },
	{ .name = "c0_tx_pend", .irq = 52 + DRA7XX_IRQ_GIC_START, },
	{ .name = "c0_misc_pend", .irq = 53 + DRA7XX_IRQ_GIC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_addr_space dra7xx_gmac_addr_space[] = {
	/* cpsw ss */
	{
		.pa_start	= 0x48484000,
		.pa_end		= 0x48484000 + SZ_2K - 1,
	},
    /* cpsw wr */
	{
		.pa_start	= 0x48485200,
		.pa_end		= 0x48485200 + SZ_256 - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod dra7xx_gmac_hwmod = {
	.name		= "gmac",
	.class		= &dra7xx_gmac_hwmod_class,
	.clkdm_name	= "gmac_clkdm",
	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
	.mpu_irqs	= dra7xx_gmac_irqs,
	.main_clk	= "dpll_gmac_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
			.context_offs	= DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'mdio' class
 */
static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
	.name		= "davinci_mdio",
};

static struct omap_hwmod_addr_space dra7xx_mdio_addr_space[] = {
	{
		.pa_start	= 0x48485000,
		.pa_end		= 0x48485000 + SZ_256 - 1,
	},
	{ }
};

static struct omap_hwmod dra7xx_mdio_hwmod = {
	.name		= "davinci_mdio",
	.class		= &dra7xx_mdio_hwmod_class,
	.clkdm_name	= "gmac_clkdm",
	.main_clk	= "dpll_gmac_ck",
};

/*
 * 'dcan' class
 *
 */

static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
	.name	= "dcan",
};

/* dcan1 */
static struct omap_hwmod dra7xx_dcan1_hwmod = {
	.name		= "dcan1",
	.class		= &dra7xx_dcan_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "dcan1_sys_clk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* dcan2 */
static struct omap_hwmod dra7xx_dcan2_hwmod = {
	.name		= "dcan2",
	.class		= &dra7xx_dcan_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "sys_clkin1",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'dma' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x002c,
	.syss_offs	= 0x0028,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
	.name	= "dma",
	.sysc	= &dra7xx_dma_sysc,
};

/* dma dev_attr */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
	.lch_count	= 32,
};

/* dma_system */
static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
	{ .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
	{ .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
	{ .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_dma_system_hwmod = {
	.name		= "dma_system",
	.class		= &dra7xx_dma_hwmod_class,
	.clkdm_name	= "dma_clkdm",
	.mpu_irqs	= dra7xx_dma_system_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
		},
	},
	.dev_attr	= &dma_dev_attr,
};

/*
 * 'dsp' class
 * dsp sub-system
 */

static struct omap_hwmod_class dra7xx_dsp_hwmod_class = {
	.name   = "dsp",
};

static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = {
	{ .name = "dsp", .rst_shift = 0 },
};

/* dsp1 processor */
static struct omap_hwmod dra7xx_dsp1_hwmod = {
	.name		= "dsp1",
	.class		= &dra7xx_dsp_hwmod_class,
	.clkdm_name	= "dsp1_clkdm",
	.rst_lines	= dra7xx_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_dsp_resets),
	.main_clk	= "dpll_dsp_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/* dsp2 processor */
static struct omap_hwmod dra7xx_dsp2_hwmod = {
	.name		= "dsp2",
	.class		= &dra7xx_dsp_hwmod_class,
	.clkdm_name	= "dsp2_clkdm",
	.rst_lines	= dra7xx_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_dsp_resets),
	.main_clk	= "dpll_dsp_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'dss' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
	.rev_offs	= 0x0000,
	.syss_offs	= 0x0014,
	.sysc_flags	= SYSS_HAS_RESET_STATUS,
};

static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
	.name	= "dss",
	.sysc	= &dra7xx_dss_sysc,
	.reset	= omap_dss_reset,
};

/* dss */
static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
	{ .dma_req = 75 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod_opt_clk dss_opt_clks[] = {
	{ .role = "dss_clk", .clk = "dss_dss_clk" },
	{ .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
	{ .role = "32khz_clk", .clk = "dss_32khz_clk" },
	{ .role = "video2_clk", .clk = "dss_video2_clk" },
	{ .role = "video1_clk", .clk = "dss_video1_clk" },
	{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
};

static struct omap_hwmod dra7xx_dss_hwmod = {
	.name		= "dss_core",
	.class		= &dra7xx_dss_hwmod_class,
	.clkdm_name	= "dss_clkdm",
#ifdef CONFIG_DISPLAY_SKIP_INIT
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
#else
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
#endif
	.sdma_reqs	= dra7xx_dss_sdma_reqs,
	.main_clk	= "dss_dss_clk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= dss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &dra7xx_dispc_sysc,
};

/* dss_dispc */
static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
	{ .irq = 25 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
	{ .dma_req = 5 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

/* dss_dispc dev_attr */
static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
	.has_framedonetv_irq	= 1,
	.manager_count		= 4,
};

static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
	.name		= "dss_dispc",
	.class		= &dra7xx_dispc_hwmod_class,
	.clkdm_name	= "dss_clkdm",
	.mpu_irqs	= dra7xx_dss_dispc_irqs,
	.sdma_reqs	= dra7xx_dss_dispc_sdma_reqs,
	.main_clk	= "dss_dss_clk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
	.dev_attr	= &dss_dispc_dev_attr,
#ifdef CONFIG_DISPLAY_SKIP_INIT
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
#endif
};

/*
 * 'hdmi' class
 * hdmi controller
 */

static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
	.name	= "hdmi",
	.sysc	= &dra7xx_hdmi_sysc,
};

/* dss_hdmi */
static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
	{ .irq = 101 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
	{ .dma_req = 75 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_hdmi_clk" },
};

static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
	.name		= "dss_hdmi",
	.class		= &dra7xx_hdmi_hwmod_class,
	.clkdm_name	= "dss_clkdm",
	.mpu_irqs	= dra7xx_dss_hdmi_irqs,
	.sdma_reqs	= dra7xx_dss_hdmi_sdma_reqs,
	.main_clk	= "dss_48mhz_clk",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
		},
	},
	.opt_clks	= dss_hdmi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
};

/*
 * 'elm' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
	.name	= "elm",
	.sysc	= &dra7xx_elm_sysc,
};

/* elm */
static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
	{ .irq = 4 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_elm_hwmod = {
	.name		= "elm",
	.class		= &dra7xx_elm_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_elm_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'emif' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
	.rev_offs	= 0x0000,
};

static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
	.name	= "emif",
	.sysc	= &dra7xx_emif_sysc,
};

/* emif1 */
static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
	{ .irq = 110 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_emif1_hwmod = {
	.name		= "emif1",
	.class		= &dra7xx_emif_hwmod_class,
	.clkdm_name	= "emif_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
	.mpu_irqs	= dra7xx_emif1_irqs,
	.main_clk	= "dpll_ddr_h11x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/* emif2 */
static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
	{ .irq = 111 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_emif2_hwmod = {
	.name		= "emif2",
	.class		= &dra7xx_emif_hwmod_class,
	.clkdm_name	= "emif_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
	.mpu_irqs	= dra7xx_emif2_irqs,
	.main_clk	= "dpll_ddr_h11x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'gpio' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0114,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
	.name	= "gpio",
	.sysc	= &dra7xx_gpio_sysc,
	.rev	= 2,
};

/* gpio dev_attr */
static struct omap_gpio_dev_attr gpio_dev_attr = {
	.bank_width	= 32,
	.dbck_flag	= true,
};

/* gpio1 */
static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
	{ .irq = 29 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio1_dbclk" },
};

static struct omap_hwmod dra7xx_gpio1_hwmod = {
	.name		= "gpio1",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.mpu_irqs	= dra7xx_gpio1_irqs,
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio2 */
static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
	{ .irq = 30 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio2_dbclk" },
};

static struct omap_hwmod dra7xx_gpio2_hwmod = {
	.name		= "gpio2",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio2_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio3 */
static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
	{ .irq = 31 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio3_dbclk" },
};

static struct omap_hwmod dra7xx_gpio3_hwmod = {
	.name		= "gpio3",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio3_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio3_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio4 */
static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
	{ .irq = 32 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio4_dbclk" },
};

static struct omap_hwmod dra7xx_gpio4_hwmod = {
	.name		= "gpio4",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio4_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio4_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio5 */
static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
	{ .irq = 33 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio5_dbclk" },
};

static struct omap_hwmod dra7xx_gpio5_hwmod = {
	.name		= "gpio5",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio5_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio5_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio6 */
static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
	{ .irq = 34 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio6_dbclk" },
};

static struct omap_hwmod dra7xx_gpio6_hwmod = {
	.name		= "gpio6",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio6_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio6_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio7 */
static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
	{ .irq = 35 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio7_dbclk" },
};

static struct omap_hwmod dra7xx_gpio7_hwmod = {
	.name		= "gpio7",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio7_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio7_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio7_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* gpio8 */
static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
	{ .irq = 121 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio8_dbclk" },
};

static struct omap_hwmod dra7xx_gpio8_hwmod = {
	.name		= "gpio8",
	.class		= &dra7xx_gpio_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= dra7xx_gpio8_irqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= gpio8_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio8_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/*
 * 'gpmc' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
	.name	= "gpmc",
	.sysc	= &dra7xx_gpmc_sysc,
};

/* gpmc */
static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
	{ .irq = 20 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
	{ .dma_req = 3 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_gpmc_hwmod = {
	.name		= "gpmc",
	.class		= &dra7xx_gpmc_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
	.mpu_irqs	= dra7xx_gpmc_irqs,
	.sdma_reqs	= dra7xx_gpmc_sdma_reqs,
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'gpu' class
 * 2d/3d graphics accelerator
 */

static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
	.name	= "gpu",
	.sysc	= &dra7xx_gpu_sysc,
};

/* gpu */
static struct omap_hwmod_irq_info dra7xx_gpu_irqs[] = {
	{ .irq = 21 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_gpu_hwmod = {
	.name		= "gpu",
	.class		= &dra7xx_gpu_hwmod_class,
	.clkdm_name	= "gpu_clkdm",
	.mpu_irqs	= dra7xx_gpu_irqs,
	.main_clk	= "gpu_core_gclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'hdq1w' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0014,
	.syss_offs	= 0x0018,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
	.name	= "hdq1w",
	.sysc	= &dra7xx_hdq1w_sysc,
};

/* hdq1w */
static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
	{ .irq = 58 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_hdq1w_hwmod = {
	.name		= "hdq1w",
	.class		= &dra7xx_hdq1w_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_INIT_NO_RESET,
	.mpu_irqs	= dra7xx_hdq1w_irqs,
	.main_clk	= "func_12m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'i2c' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0090,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.clockact	= CLOCKACT_TEST_ICLK,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
	.name	= "i2c",
	.sysc	= &dra7xx_i2c_sysc,
	.reset	= &omap_i2c_reset,
	.rev	= OMAP_I2C_IP_VERSION_2,
};

/* i2c dev_attr */
static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags	= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
};

/* i2c1 */
static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
	{ .irq = 56 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
	{ .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
	{ .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_i2c1_hwmod = {
	.name		= "i2c1",
	.class		= &dra7xx_i2c_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.mpu_irqs	= dra7xx_i2c1_irqs,
	.sdma_reqs	= dra7xx_i2c1_sdma_reqs,
	.main_clk	= "func_96m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/* i2c2 */
static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
	{ .irq = 57 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
	{ .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
	{ .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_i2c2_hwmod = {
	.name		= "i2c2",
	.class		= &dra7xx_i2c_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.mpu_irqs	= dra7xx_i2c2_irqs,
	.sdma_reqs	= dra7xx_i2c2_sdma_reqs,
	.main_clk	= "func_96m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/* i2c3 */
static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
	{ .irq = 61 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
	{ .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
	{ .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_i2c3_hwmod = {
	.name		= "i2c3",
	.class		= &dra7xx_i2c_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.mpu_irqs	= dra7xx_i2c3_irqs,
	.sdma_reqs	= dra7xx_i2c3_sdma_reqs,
	.main_clk	= "func_96m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/* i2c4 */
static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
	{ .irq = 62 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
	{ .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
	{ .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_i2c4_hwmod = {
	.name		= "i2c4",
	.class		= &dra7xx_i2c_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.mpu_irqs	= dra7xx_i2c4_irqs,
	.sdma_reqs	= dra7xx_i2c4_sdma_reqs,
	.main_clk	= "func_96m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/* i2c5 */
static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
	{ .irq = 60 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_i2c5_hwmod = {
	.name		= "i2c5",
	.class		= &dra7xx_i2c_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
	.mpu_irqs	= dra7xx_i2c5_irqs,
	.main_clk	= "func_96m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &i2c_dev_attr,
};

/*
 * 'ipu' class
 * imaging processor unit
 */

static struct omap_hwmod_class dra7xx_ipu_hwmod_class = {
	.name	= "ipu",
};

static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = {
	{ .name = "cpu0", .rst_shift = 0 },
	{ .name = "cpu1", .rst_shift = 1 },
};

/* ipu1 processor */
static struct omap_hwmod dra7xx_ipu1_hwmod = {
	.name		= "ipu1",
	.class		= &dra7xx_ipu_hwmod_class,
	.clkdm_name	= "ipu1_clkdm",
	.rst_lines	= dra7xx_ipu_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_ipu_resets),
	.main_clk	= "ipu1_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
#if defined(CONFIG_OMAP_REMOTEPROC_LATE_ATTACH_IPU1) || \
		defined(CONFIG_EARLYCAMERA_IPU)
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
#endif
};

/* ipu2 processor */
static struct omap_hwmod dra7xx_ipu2_hwmod = {
	.name		= "ipu2",
	.class		= &dra7xx_ipu_hwmod_class,
	.clkdm_name	= "ipu2_clkdm",
	.rst_lines	= dra7xx_ipu_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_ipu_resets),
	.main_clk	= "dpll_core_h22x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
#ifdef CONFIG_OMAP_REMOTEPROC_LATE_ATTACH_IPU2
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
#endif
};

/*
 * 'mailbox' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
	.name	= "mailbox",
	.sysc	= &dra7xx_mailbox_sysc,
};

/* mailbox1 */
static struct omap_hwmod dra7xx_mailbox1_hwmod = {
	.name		= "mailbox1",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
		},
	},
};

/* mailbox2 */
static struct omap_hwmod dra7xx_mailbox2_hwmod = {
	.name		= "mailbox2",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
		},
	},
};

/* mailbox3 */
static struct omap_hwmod dra7xx_mailbox3_hwmod = {
	.name		= "mailbox3",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
		},
	},
};

/* mailbox4 */
static struct omap_hwmod dra7xx_mailbox4_hwmod = {
	.name		= "mailbox4",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
		},
	},
};

/* mailbox5 */
static struct omap_hwmod dra7xx_mailbox5_hwmod = {
	.name		= "mailbox5",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
		},
	},
};

/* mailbox6 */
static struct omap_hwmod dra7xx_mailbox6_hwmod = {
	.name		= "mailbox6",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
		},
	},
};

/* mailbox7 */
static struct omap_hwmod dra7xx_mailbox7_hwmod = {
	.name		= "mailbox7",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
		},
	},
};

/* mailbox8 */
static struct omap_hwmod dra7xx_mailbox8_hwmod = {
	.name		= "mailbox8",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
		},
	},
};

/* mailbox9 */
static struct omap_hwmod dra7xx_mailbox9_hwmod = {
	.name		= "mailbox9",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
		},
	},
};

/* mailbox10 */
static struct omap_hwmod dra7xx_mailbox10_hwmod = {
	.name		= "mailbox10",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
		},
	},
};

/* mailbox11 */
static struct omap_hwmod dra7xx_mailbox11_hwmod = {
	.name		= "mailbox11",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
		},
	},
};

/* mailbox12 */
static struct omap_hwmod dra7xx_mailbox12_hwmod = {
	.name		= "mailbox12",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
		},
	},
};

/* mailbox13 */
static struct omap_hwmod dra7xx_mailbox13_hwmod = {
	.name		= "mailbox13",
	.class		= &dra7xx_mailbox_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'mcasp' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
	.sysc_offs	= 0x0004,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type3,
};

static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
	.name	= "mcasp",
	.sysc	= &dra7xx_mcasp_sysc,
};

/* mcasp1 */
static struct omap_hwmod dra7xx_mcasp1_hwmod = {
	.name		= "mcasp1",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.main_clk	= "mcasp1_ahclkx_mux",
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_dma_info dra7xx_mcasp2_sdma_reqs[] = {
        { .name = "tx", .dma_req = 62 + DRA7XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 63 + DRA7XX_DMA_REQ_START },
        { .dma_req = -1 }
};

/* mcasp2 */
static struct omap_hwmod dra7xx_mcasp2_hwmod = {
	.name		= "mcasp2",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp2_ahclkx_mux",
	.sdma_reqs	= dra7xx_mcasp2_sdma_reqs,
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_dma_info dra7xx_mcasp3_sdma_reqs[] = {
        { .name = "tx", .dma_req = 78 + DRA7XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 79 + DRA7XX_DMA_REQ_START },
        { .dma_req = -1 }
};

/* mcasp3 */
static struct omap_hwmod dra7xx_mcasp3_hwmod = {
	.name		= "mcasp3",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp3_ahclkx_mux",
	.sdma_reqs	= dra7xx_mcasp3_sdma_reqs,
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* mcasp4 */
static struct omap_hwmod dra7xx_mcasp4_hwmod = {
	.name		= "mcasp4",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp4_ahclkx_mux",
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* mcasp5 */
static struct omap_hwmod_dma_info dra7xx_mcasp5_sdma_reqs[] = {
        { .name = "tx", .dma_req = 69 + DRA7XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 70 + DRA7XX_DMA_REQ_START },
        { .dma_req = -1 }
};


static struct omap_hwmod dra7xx_mcasp5_hwmod = {
	.name		= "mcasp5",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp5_ahclkx_mux",
	.sdma_reqs	= dra7xx_mcasp5_sdma_reqs,
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};
/*
static struct omap_hwmod_dma_info dra7xx_mcasp6_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 62 + DRA7XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 63 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};
*/
/* mcasp6 */
static struct omap_hwmod dra7xx_mcasp6_hwmod = {
	.name		= "mcasp6",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp6_ahclkx_mux",
//	.sdma_reqs	= dra7xx_mcasp6_sdma_reqs,
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};
/*
static struct omap_hwmod_dma_info dra7xx_mcasp7_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 69 + DRA7XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 70 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};
*/
/* mcasp7 */
static struct omap_hwmod dra7xx_mcasp7_hwmod = {
	.name		= "mcasp7",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp7_ahclkx_mux",
//	.sdma_reqs	= dra7xx_mcasp7_sdma_reqs,
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* mcasp8 */
static struct omap_hwmod dra7xx_mcasp8_hwmod = {
	.name		= "mcasp8",
	.class		= &dra7xx_mcasp_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "mcasp8_ahclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'mcspi' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
	.name	= "mcspi",
	.sysc	= &dra7xx_mcspi_sysc,
	.rev	= OMAP4_MCSPI_REV,
};

/* mcspi1 */
static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
	{ .irq = 65 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
	{ .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
	{ .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
	{ .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
	{ .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
	{ .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
	{ .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
	{ .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
	{ .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

/* mcspi1 dev_attr */
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
	.num_chipselect	= 4,
};

static struct omap_hwmod dra7xx_mcspi1_hwmod = {
	.name		= "mcspi1",
	.class		= &dra7xx_mcspi_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_mcspi1_irqs,
	.sdma_reqs	= dra7xx_mcspi1_sdma_reqs,
	.main_clk	= "func_48m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi1_dev_attr,
};

/* mcspi2 */
static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
	{ .irq = 66 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
	{ .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
	{ .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
	{ .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
	{ .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

/* mcspi2 dev_attr */
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
	.num_chipselect	= 2,
};

static struct omap_hwmod dra7xx_mcspi2_hwmod = {
	.name		= "mcspi2",
	.class		= &dra7xx_mcspi_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_mcspi2_irqs,
	.sdma_reqs	= dra7xx_mcspi2_sdma_reqs,
	.main_clk	= "func_48m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi2_dev_attr,
};

/* mcspi3 */
static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
	{ .irq = 91 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
	{ .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
	{ .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
	{ .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
	{ .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

/* mcspi3 dev_attr */
static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
	.num_chipselect	= 2,
};

static struct omap_hwmod dra7xx_mcspi3_hwmod = {
	.name		= "mcspi3",
	.class		= &dra7xx_mcspi_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_mcspi3_irqs,
	.sdma_reqs	= dra7xx_mcspi3_sdma_reqs,
	.main_clk	= "func_48m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi3_dev_attr,
};

/* mcspi4 */
static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
	{ .irq = 48 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

/* mcspi4 dev_attr */
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
	.num_chipselect	= 1,
};

static struct omap_hwmod dra7xx_mcspi4_hwmod = {
	.name		= "mcspi4",
	.class		= &dra7xx_mcspi_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_mcspi4_irqs,
	.main_clk	= "func_48m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi4_dev_attr,
};

/*
 * 'mmc' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
	.name	= "mmc",
	.sysc	= &dra7xx_mmc_sysc,
};

/* mmc1 */
static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
	{ .irq = 83 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 60 + DRA7XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 61 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
	{ .role = "clk32k", .clk = "mmc1_clk32k" },
};

/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};

static struct omap_hwmod dra7xx_mmc1_hwmod = {
	.name		= "mmc1",
	.class		= &dra7xx_mmc_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.mpu_irqs	= dra7xx_mmc1_irqs,
	.sdma_reqs	= dra7xx_mmc1_sdma_reqs,
	.main_clk	= "mmc1_fclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= mmc1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mmc1_opt_clks),
	.dev_attr	= &mmc1_dev_attr,
};

/* mmc2 */
static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
	{ .irq = 86 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 46 + DRA7XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 47 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
	{ .role = "clk32k", .clk = "mmc2_clk32k" },
};

static struct omap_hwmod dra7xx_mmc2_hwmod = {
	.name		= "mmc2",
	.class		= &dra7xx_mmc_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.mpu_irqs	= dra7xx_mmc2_irqs,
	.sdma_reqs	= dra7xx_mmc2_sdma_reqs,
	.main_clk	= "mmc2_fclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= mmc2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mmc2_opt_clks),
};

/* mmc3 */
static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
	{ .irq = 94 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};


static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
	{ .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
	{ .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};


static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
	{ .role = "clk32k", .clk = "mmc3_clk32k" },
};

static struct omap_hwmod dra7xx_mmc3_hwmod = {
	.name		= "mmc3",
	.class		= &dra7xx_mmc_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_mmc3_irqs,
	.sdma_reqs	= dra7xx_mmc3_sdma_reqs,
	.main_clk	= "mmc3_gfclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= mmc3_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mmc3_opt_clks),
};

/* mmc4 */
static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
	{ .irq = 96 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 56 + DRA7XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 57 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
	{ .role = "clk32k", .clk = "mmc4_clk32k" },
};

static struct omap_hwmod dra7xx_mmc4_hwmod = {
	.name		= "mmc4",
	.class		= &dra7xx_mmc_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_mmc4_irqs,
	.sdma_reqs	= dra7xx_mmc4_sdma_reqs,
	.main_clk	= "mmc4_gfclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= mmc4_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mmc4_opt_clks),
};

/*
 * 'mmu' class
 * The memory management unit performs virtual to physical address translation
 * for its requestors.
 */

static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_mmu_hwmod_class = {
	.name = "mmu",
	.sysc = &dra7xx_mmu_sysc,
};

/* IPU MMUs */
static struct omap_mmu_dev_attr dra7xx_mmu_ipu_dev_attr = {
	.da_start	= 0x0,
	.da_end		= 0xfffff000,
	.nr_tlb_entries = 32,
	.has_bus_err_back = 1,
};

static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 2 },
};

/* mmu ipu1 */
static struct omap_hwmod_irq_info dra7xx_mmu_ipu1_irqs[] = {
	{ .irq = 100 + DRA7XX_IRQ_GIC_START, },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = {
	.name		= "mmu_ipu1",
	.class		= &dra7xx_mmu_hwmod_class,
	.clkdm_name	= "ipu1_clkdm",
	.mpu_irqs	= dra7xx_mmu_ipu1_irqs,
	.rst_lines	= dra7xx_mmu_ipu_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_mmu_ipu_resets),
	.main_clk	= "ipu1_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= &dra7xx_mmu_ipu_dev_attr,
#if defined(CONFIG_OMAP_REMOTEPROC_LATE_ATTACH_IPU1) || \
		defined(CONFIG_EARLYCAMERA_IPU)
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
#endif
};

/* mmu ipu2 */
static struct omap_hwmod_irq_info dra7xx_mmu_ipu2_irqs[] = {
	/* map IRQ 142 to the actual crossbar input 396 */
	{ .irq = 142 + DRA7XX_IRQ_GIC_START, },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = {
	.name		= "mmu_ipu2",
	.class		= &dra7xx_mmu_hwmod_class,
	.clkdm_name	= "ipu2_clkdm",
	.mpu_irqs	= dra7xx_mmu_ipu2_irqs,
	.rst_lines	= dra7xx_mmu_ipu_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_mmu_ipu_resets),
	.main_clk	= "dpll_core_h22x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= &dra7xx_mmu_ipu_dev_attr,
#ifdef CONFIG_OMAP_REMOTEPROC_LATE_ATTACH_IPU2
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
#endif
};

/* DSP MMUs */
static struct omap_mmu_dev_attr dra7xx_mmu0_dsp_dev_attr = {
	.da_start	= 0x20000000,
	.da_end		= 0xfffff000,
	.nr_tlb_entries = 32,
	.index		= 0,
};

static struct omap_mmu_dev_attr dra7xx_mmu1_dsp_dev_attr = {
	.da_start	= 0x20000000,
	.da_end		= 0xfffff000,
	.nr_tlb_entries = 32,
	.index		= 1,
};

static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 1 },
};

/* mmu0 - dsp1 */
static struct omap_hwmod_irq_info dra7xx_mmu0_dsp1_irqs[] = {
	{ .irq = 28 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = {
	.name		= "mmu0_dsp1",
	.class		= &dra7xx_mmu_hwmod_class,
	.clkdm_name	= "dsp1_clkdm",
	.mpu_irqs	= dra7xx_mmu0_dsp1_irqs,
	.rst_lines	= dra7xx_mmu_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_mmu_dsp_resets),
	.main_clk	= "dpll_dsp_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= &dra7xx_mmu0_dsp_dev_attr,
};

/* mmu1 - dsp1 */
static struct omap_hwmod_irq_info dra7xx_mmu1_dsp1_irqs[] = {
	/* map IRQ 143 to the actual crossbar input 145 */
	{ .irq = 143 + DRA7XX_IRQ_GIC_START, },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = {
	.name		= "mmu1_dsp1",
	.class		= &dra7xx_mmu_hwmod_class,
	.clkdm_name	= "dsp1_clkdm",
	.mpu_irqs	= dra7xx_mmu1_dsp1_irqs,
	.main_clk	= "dpll_dsp_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= &dra7xx_mmu1_dsp_dev_attr,
};

/* mmu0 - dsp2 */
static struct omap_hwmod_irq_info dra7xx_mmu0_dsp2_irqs[] = {
	/* map IRQ 144 to the actual crossbar input 146 */
	{ .irq = 144 + DRA7XX_IRQ_GIC_START, },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = {
	.name		= "mmu0_dsp2",
	.class		= &dra7xx_mmu_hwmod_class,
	.clkdm_name	= "dsp2_clkdm",
	.mpu_irqs	= dra7xx_mmu0_dsp2_irqs,
	.rst_lines	= dra7xx_mmu_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_mmu_dsp_resets),
	.main_clk	= "dpll_dsp_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= &dra7xx_mmu0_dsp_dev_attr,
};

/* mmu1 - dsp2 */
static struct omap_hwmod_irq_info dra7xx_mmu1_dsp2_irqs[] = {
	/* map IRQ 145 to the actual crossbar input 147 */
	{ .irq = 145 + DRA7XX_IRQ_GIC_START, },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = {
	.name		= "mmu1_dsp2",
	.class		= &dra7xx_mmu_hwmod_class,
	.clkdm_name	= "dsp2_clkdm",
	.mpu_irqs	= dra7xx_mmu1_dsp2_irqs,
	.main_clk	= "dpll_dsp_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
			.rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
			.context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= &dra7xx_mmu1_dsp_dev_attr,
};

/*
 * 'mpu' class
 *
 */

static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
	.name	= "mpu",
};

/* mpu */
static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
	{ .irq = 132 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_mpu_hwmod = {
	.name		= "mpu",
	.class		= &dra7xx_mpu_hwmod_class,
	.clkdm_name	= "mpu_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
	.mpu_irqs	= dra7xx_mpu_irqs,
	.main_clk	= "dpll_mpu_m2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'ocmc_ram' class
 *
 */

static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
	.name	= "ocmc_ram",
};

/* ocmc_ram1 */
static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
	.name		= "ocmc_ram1",
	.class		= &dra7xx_ocmc_ram_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
		},
	},
};

/* ocmc_ram2 */
static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
	.name		= "ocmc_ram2",
	.class		= &dra7xx_ocmc_ram_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
		},
	},
};

/* ocmc_ram3 */
static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
	.name		= "ocmc_ram3",
	.class		= &dra7xx_ocmc_ram_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'ocmc_rom' class
 *
 */

static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
	.name	= "ocmc_rom",
};

/* ocmc_rom */
static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
	.name		= "ocmc_rom",
	.class		= &dra7xx_ocmc_rom_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'ocp2scp' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
	.name	= "ocp2scp",
	.sysc	= &dra7xx_ocp2scp_sysc,
};

/* ocp2scp1 */
static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
	.name		= "ocp2scp1",
	.class		= &dra7xx_ocp2scp_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};
static struct resource dra7xx_sata_phy_addrs[] = {
	{
		.name		= "sata_phy_rx",
		.start		= 0x4A096000,
		.end		= 0x4A096080,
		.flags		= IORESOURCE_MEM,
	},
	{
		.name		= "sata_phy_tx",
		.start		= 0x4A096400,
		.end		= 0x4A096464,
		.flags		= IORESOURCE_MEM,
	},
	{
		.name		= "sata_pll",
		.start		= 0x4A096800,
		.end		= 0x4A096840,
		.flags		= IORESOURCE_MEM,
	},
	{ }
};

static struct omap_ocp2scp_dev ocp2scp3_dev_attr[] = {
	{
		.drv_name       = "omap-sata",
		.res		= dra7xx_sata_phy_addrs,
	},
	{ }
};

/* ocp2scp3 */
static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
static struct omap_hwmod_addr_space dra7xx_ocp2scp3_addrs[] = {
	{
		.name		= "ocp2scp3",
		.pa_start	= 0x4a090000,
		.pa_end		= 0x4a09001f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> ocp2scp3 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_ocp2scp3_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_ocp2scp3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
	.name		= "ocp2scp3",
	.class		= &dra7xx_ocp2scp_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.prcm = {
		.omap4 = {
			.clkctrl_offs =
				DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
			.context_offs =
				DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.dev_attr	= ocp2scp3_dev_attr,
};


/*
 * 'pruss' class
 *
 */

static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
	.name	= "pruss",
};

/* pruss1 */
static struct omap_hwmod dra7xx_pruss1_hwmod = {
	.name		= "pruss1",
	.class		= &dra7xx_pruss_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "dpll_per_m2x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* pruss2 */
static struct omap_hwmod dra7xx_pruss2_hwmod = {
	.name		= "pruss2",
	.class		= &dra7xx_pruss_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "dpll_per_m2x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'pwmss' class
 *
 */

static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
	.name	= "pwmss",
};

/* pwmss1 */
static struct omap_hwmod dra7xx_pwmss1_hwmod = {
	.name		= "pwmss1",
	.class		= &dra7xx_pwmss_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* pwmss2 */
static struct omap_hwmod dra7xx_pwmss2_hwmod = {
	.name		= "pwmss2",
	.class		= &dra7xx_pwmss_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* pwmss3 */
static struct omap_hwmod dra7xx_pwmss3_hwmod = {
	.name		= "pwmss3",
	.class		= &dra7xx_pwmss_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'qspi' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
	.sysc_offs	= 0x0010,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
	.name	= "qspi",
	.sysc	= &dra7xx_qspi_sysc,
};

/* qspi */
static struct omap_hwmod dra7xx_qspi_hwmod = {
	.name		= "qspi",
	.class		= &dra7xx_qspi_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "qspi_gfclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'rtcss' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
	.sysc_offs	= 0x0078,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type3,
};

static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
	.name	= "rtcss",
	.sysc	= &dra7xx_rtcss_sysc,
};

/* rtcss */
static struct omap_hwmod dra7xx_rtcss_hwmod = {
	.name		= "rtcss",
	.class		= &dra7xx_rtcss_hwmod_class,
	.clkdm_name	= "rtc_clkdm",
	.main_clk	= "sys_32k_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'sata' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
	.sysc_offs	= 0x0000,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
	.name	= "sata",
	.sysc	= &dra7xx_sata_sysc,
};

/* sata */
static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
	{ .irq = 54 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_opt_clk sata_opt_clks[] = {
	{ .role = "ref_clk", .clk = "sata_ref_clk" },
};

static struct omap_hwmod dra7xx_sata_hwmod = {
	.name		= "sata",
	.class		= &dra7xx_sata_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.mpu_irqs	= dra7xx_sata_irqs,
	.main_clk	= "func_48m_fclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= sata_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
};

/*
 * 'smartreflex' class
 *
 */

/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
	.sidle_shift	= 24,
	.enwkup_shift	= 26,
};

static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
	.sysc_offs	= 0x0038,
	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
};

static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
	.name	= "smartreflex",
	.sysc	= &dra7xx_smartreflex_sysc,
	.rev	= 2,
};

/* smartreflex_core */
static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
	{ .irq = 19 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

/* smartreflex_core dev_attr */
static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
	.sensor_voltdm_name	= "core",
};

static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
	.name		= "smartreflex_core",
	.class		= &dra7xx_smartreflex_hwmod_class,
	.clkdm_name	= "coreaon_clkdm",
	.mpu_irqs	= dra7xx_smartreflex_core_irqs,
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &smartreflex_core_dev_attr,
};

/* smartreflex_dspeve */
static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
	.name		= "smartreflex_dspeve",
	.class		= &dra7xx_smartreflex_hwmod_class,
	.clkdm_name	= "coreaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* smartreflex_gpu */
static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
	.name		= "smartreflex_gpu",
	.class		= &dra7xx_smartreflex_hwmod_class,
	.clkdm_name	= "coreaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* smartreflex_mpu */
static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
	{ .irq = 18 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

/* smartreflex_mpu dev_attr */
static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
	.sensor_voltdm_name	= "mpu",
};

static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
	.name		= "smartreflex_mpu",
	.class		= &dra7xx_smartreflex_hwmod_class,
	.clkdm_name	= "coreaon_clkdm",
	.mpu_irqs	= dra7xx_smartreflex_mpu_irqs,
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &smartreflex_mpu_dev_attr,
};

/*
 * 'spare' class
 *
 */

static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
	.name	= "spare",
};

/* spare_cme */
static struct omap_hwmod dra7xx_spare_cme_hwmod = {
	.name		= "spare_cme",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
		},
	},
};

/* spare_icm */
static struct omap_hwmod dra7xx_spare_icm_hwmod = {
	.name		= "spare_icm",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
		},
	},
};

/* spare_iva2 */
static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
	.name		= "spare_iva2",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
		},
	},
};

/* spare_safety1 */
static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
	.name		= "spare_safety1",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
		},
	},
};

/* spare_safety2 */
static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
	.name		= "spare_safety2",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
		},
	},
};

/* spare_safety3 */
static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
	.name		= "spare_safety3",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
		},
	},
};

/* spare_safety4 */
static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
	.name		= "spare_safety4",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
		},
	},
};

/* spare_unknown2 */
static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
	.name		= "spare_unknown2",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
		},
	},
};

/* spare_unknown3 */
static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
	.name		= "spare_unknown3",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "wkupaon_iclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
		},
	},
};

/* spare_unknown4 */
static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
	.name		= "spare_unknown4",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
		},
	},
};

/* spare_unknown5 */
static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
	.name		= "spare_unknown5",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
		},
	},
};

/* spare_unknown6 */
static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
	.name		= "spare_unknown6",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
		},
	},
};

/* spare_videopll1 */
static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
	.name		= "spare_videopll1",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
		},
	},
};

/* spare_videopll2 */
static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
	.name		= "spare_videopll2",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
		},
	},
};

/* spare_videopll3 */
static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
	.name		= "spare_videopll3",
	.class		= &dra7xx_spare_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'spare_sata2' class
 *
 */

static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
	.name	= "spare_sata2",
};

/* spare_sata2 */
static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
	.name		= "spare_sata2",
	.class		= &dra7xx_spare_sata2_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'spare_smartreflex' class
 *
 */

static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
	.name	= "spare_smartreflex",
};

/* spare_smartreflex_rtc */
static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
	.name		= "spare_smartreflex_rtc",
	.class		= &dra7xx_spare_smartreflex_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
		},
	},
};

/* spare_smartreflex_sdram */
static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
	.name		= "spare_smartreflex_sdram",
	.class		= &dra7xx_spare_smartreflex_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
		},
	},
};

/* spare_smartreflex_wkup */
static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
	.name		= "spare_smartreflex_wkup",
	.class		= &dra7xx_spare_smartreflex_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l4_root_clk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'spinlock' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
	.name	= "spinlock",
	.sysc	= &dra7xx_spinlock_sysc,
};

/* spinlock */
static struct omap_hwmod dra7xx_spinlock_hwmod = {
	.name		= "spinlock",
	.class		= &dra7xx_spinlock_hwmod_class,
	.clkdm_name	= "l4cfg_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'timer' class
 *
 * This class contains several variants: ['timer_1ms', 'timer_secure',
 * 'timer']
 */

static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
	.name	= "timer",
	.sysc	= &dra7xx_timer_1ms_sysc,
};

static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
	.name	= "timer",
	.sysc	= &dra7xx_timer_secure_sysc,
};

static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
	.name	= "timer",
	.sysc	= &dra7xx_timer_sysc,
};

/* timer1 */
static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
	{ .irq = 37 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer1_hwmod = {
	.name		= "timer1",
	.class		= &dra7xx_timer_1ms_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.mpu_irqs	= dra7xx_timer1_irqs,
	.main_clk	= "timer1_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer2 */
static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
	{ .irq = 38 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer2_hwmod = {
	.name		= "timer2",
	.class		= &dra7xx_timer_1ms_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_timer2_irqs,
	.main_clk	= "timer2_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer3 */
static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
	{ .irq = 39 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer3_hwmod = {
	.name		= "timer3",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_timer3_irqs,
	.main_clk	= "timer3_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
#ifdef CONFIG_OMAP_REMOTEPROC_LATE_ATTACH_IPU2
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
#endif
};

/* timer4 */
static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
	{ .irq = 40 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer4_hwmod = {
	.name		= "timer4",
	.class		= &dra7xx_timer_secure_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_timer4_irqs,
	.main_clk	= "timer4_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer5 */
static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
	{ .irq = 41 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer5_hwmod = {
	.name		= "timer5",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.mpu_irqs	= dra7xx_timer5_irqs,
	.main_clk	= "timer5_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer6 */
static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
	{ .irq = 42 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer6_hwmod = {
	.name		= "timer6",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.mpu_irqs	= dra7xx_timer6_irqs,
	.main_clk	= "timer6_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer7 */
static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
	{ .irq = 43 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer7_hwmod = {
	.name		= "timer7",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.mpu_irqs	= dra7xx_timer7_irqs,
	.main_clk	= "timer7_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer8 */
static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
	{ .irq = 44 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer8_hwmod = {
	.name		= "timer8",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.mpu_irqs	= dra7xx_timer8_irqs,
	.main_clk	= "timer8_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer9 */
static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
	{ .irq = 45 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer9_hwmod = {
	.name		= "timer9",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_timer9_irqs,
	.main_clk	= "timer9_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer10 */
static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
	{ .irq = 46 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer10_hwmod = {
	.name		= "timer10",
	.class		= &dra7xx_timer_1ms_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_timer10_irqs,
	.main_clk	= "timer10_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer11 */
static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
	{ .irq = 47 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_timer11_hwmod = {
	.name		= "timer11",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_timer11_irqs,
	.main_clk	= "timer11_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
#ifdef CONFIG_OMAP_REMOTEPROC_LATE_ATTACH_IPU1
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
#endif
};

/* timer13 */
static struct omap_hwmod dra7xx_timer13_hwmod = {
	.name		= "timer13",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per3_clkdm",
	.main_clk	= "timer13_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer14 */
static struct omap_hwmod dra7xx_timer14_hwmod = {
	.name		= "timer14",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per3_clkdm",
	.main_clk	= "timer14_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer15 */
static struct omap_hwmod dra7xx_timer15_hwmod = {
	.name		= "timer15",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per3_clkdm",
	.main_clk	= "timer15_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* timer16 */
static struct omap_hwmod dra7xx_timer16_hwmod = {
	.name		= "timer16",
	.class		= &dra7xx_timer_hwmod_class,
	.clkdm_name	= "l4per3_clkdm",
	.main_clk	= "timer16_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'uart' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
	.rev_offs	= 0x0050,
	.sysc_offs	= 0x0054,
	.syss_offs	= 0x0058,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
	.name	= "uart",
	.sysc	= &dra7xx_uart_sysc,
};

/* uart1 */
static struct omap_hwmod_irq_info dra7xx_uart1_irqs[] = {
	{ .irq = 72 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_uart1_sdma_reqs[] = {
	{ .name = "49", .dma_req = 48 + DRA7XX_DMA_REQ_START },
	{ .name = "50", .dma_req = 49 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_uart1_hwmod = {
	.name		= "uart1",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_uart1_irqs,
	.sdma_reqs	= dra7xx_uart1_sdma_reqs,
	.main_clk	= "uart1_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart2 */
static struct omap_hwmod_irq_info dra7xx_uart2_irqs[] = {
	{ .irq = 73 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_uart2_sdma_reqs[] = {
	{ .name = "51", .dma_req = 50 + DRA7XX_DMA_REQ_START },
	{ .name = "52", .dma_req = 51 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_uart2_hwmod = {
	.name		= "uart2",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_uart2_irqs,
	.sdma_reqs	= dra7xx_uart2_sdma_reqs,
	.main_clk	= "uart2_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart3 */
static struct omap_hwmod_irq_info dra7xx_uart3_irqs[] = {
	{ .irq = 74 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_uart3_sdma_reqs[] = {
	{ .name = "53", .dma_req = 52 + DRA7XX_DMA_REQ_START },
	{ .name = "54", .dma_req = 53 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_uart3_hwmod = {
	.name		= "uart3",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
				HWMOD_SWSUP_SIDLE_ACT,
	.mpu_irqs	= dra7xx_uart3_irqs,
	.sdma_reqs	= dra7xx_uart3_sdma_reqs,
	.main_clk	= "uart3_gfclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart4 */
static struct omap_hwmod_irq_info dra7xx_uart4_irqs[] = {
	{ .irq = 70 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_uart4_sdma_reqs[] = {
	{ .name = "55", .dma_req = 54 + DRA7XX_DMA_REQ_START },
	{ .name = "56", .dma_req = 55 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_uart4_hwmod = {
	.name		= "uart4",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_uart4_irqs,
	.sdma_reqs	= dra7xx_uart4_sdma_reqs,
	.main_clk	= "uart4_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};


/* uart5 */
static struct omap_hwmod_irq_info dra7xx_uart5_irqs[] = {
	{ .irq = 105 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

/*
static struct omap_hwmod_dma_info dra7xx_uart5_sdma_reqs[] = {
	{ .name = "63", .dma_req = 62 + DRA7XX_DMA_REQ_START },
	{ .name = "64", .dma_req = 63 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};
*/
static struct omap_hwmod dra7xx_uart5_hwmod = {
	.name		= "uart5",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per_clkdm",
	.mpu_irqs	= dra7xx_uart5_irqs,
//	.sdma_reqs	= dra7xx_uart5_sdma_reqs,
	.main_clk	= "uart5_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart6 */
static struct omap_hwmod_irq_info dra7xx_uart6_irqs[] = {
	{ .irq = 106 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod_dma_info dra7xx_uart6_sdma_reqs[] = {
	{ .name = "79", .dma_req = 78 + DRA7XX_DMA_REQ_START },
	{ .name = "80", .dma_req = 79 + DRA7XX_DMA_REQ_START },
	{ .dma_req = -1 }
};

static struct omap_hwmod dra7xx_uart6_hwmod = {
	.name		= "uart6",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "ipu_clkdm",
	.mpu_irqs	= dra7xx_uart6_irqs,
	.sdma_reqs	= dra7xx_uart6_sdma_reqs,
	.main_clk	= "uart6_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart7 */
static struct omap_hwmod dra7xx_uart7_hwmod = {
	.name		= "uart7",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "uart7_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart8 */
static struct omap_hwmod dra7xx_uart8_hwmod = {
	.name		= "uart8",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "uart8_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart9 */
static struct omap_hwmod dra7xx_uart9_hwmod = {
	.name		= "uart9",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "l4per2_clkdm",
	.main_clk	= "uart9_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/* uart10 */
static struct omap_hwmod dra7xx_uart10_hwmod = {
	.name		= "uart10",
	.class		= &dra7xx_uart_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.main_clk	= "uart10_gfclk_mux",
	.flags		= HWMOD_SWSUP_SIDLE_ACT,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'usb_otg_ss' class
 *
 */

static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
	.name	= "usb_otg_ss",
};

/* usb_otg_ss1 */
static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
	{ .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
};

static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
	.name		= "usb_otg_ss1",
	.class		= &dra7xx_usb_otg_ss_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.main_clk	= "dpll_core_h13x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= usb_otg_ss1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_ss1_opt_clks),
};

/* usb_otg_ss2 */
static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
	{ .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
};

static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
	.name		= "usb_otg_ss2",
	.class		= &dra7xx_usb_otg_ss_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.main_clk	= "dpll_core_h13x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
	.opt_clks	= usb_otg_ss2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_ss2_opt_clks),
};

/* usb_otg_ss3 */
static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
	.name		= "usb_otg_ss3",
	.class		= &dra7xx_usb_otg_ss_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.main_clk	= "dpll_core_h13x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/* usb_otg_ss4 */
static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
	.name		= "usb_otg_ss4",
	.class		= &dra7xx_usb_otg_ss_hwmod_class,
	.clkdm_name	= "l3init_clkdm",
	.main_clk	= "dpll_core_h13x2_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'vcp' class
 *
 */

static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
	.name	= "vcp",
};

/* vcp1 */
static struct omap_hwmod dra7xx_vcp1_hwmod = {
	.name		= "vcp1",
	.class		= &dra7xx_vcp_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
		},
	},
};

/* vcp2 */
static struct omap_hwmod dra7xx_vcp2_hwmod = {
	.name		= "vcp2",
	.class		= &dra7xx_vcp_hwmod_class,
	.clkdm_name	= "l3main1_clkdm",
	.main_clk	= "l3_iclk_div",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
		},
	},
};

/*
 * 'vip' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
	.name	= "vip",
	.sysc	= &dra7xx_vip_sysc,
};

/* vip1 */
static struct omap_hwmod dra7xx_vip1_hwmod = {
	.name		= "vip1",
	.class		= &dra7xx_vip_hwmod_class,
	.clkdm_name	= "cam_clkdm",
	.main_clk	= "vip1_gclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
#ifdef CONFIG_EARLYCAMERA_IPU
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
#endif
};

/* vip2 */
static struct omap_hwmod dra7xx_vip2_hwmod = {
	.name		= "vip2",
	.class		= &dra7xx_vip_hwmod_class,
	.clkdm_name	= "cam_clkdm",
	.main_clk	= "vip2_gclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/* vip3 */
static struct omap_hwmod dra7xx_vip3_hwmod = {
	.name		= "vip3",
	.class		= &dra7xx_vip_hwmod_class,
	.clkdm_name	= "cam_clkdm",
	.main_clk	= "vip3_gclk_mux",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'vpe' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
	.name	= "vpe",
	.sysc	= &dra7xx_vpe_sysc,
};

static struct omap_hwmod_irq_info dra7xx_vpe_irqs[] = {
	/*
	 * Using a reserved interrupt line, mapping crossbar 354 to the irq line
	 * in the driver
	 */
	{ .irq = 158 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

/* vpe */
static struct omap_hwmod dra7xx_vpe_hwmod = {
	.name		= "vpe",
	.class		= &dra7xx_vpe_hwmod_class,
	.clkdm_name	= "vpe_clkdm",
	.main_clk	= "dpll_core_h23x2_ck",
	.mpu_irqs	= dra7xx_vpe_irqs,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_HWCTRL,
		},
	},
};

/*
 * 'wd_timer' class
 *
 */

static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
	.name		= "wd_timer",
	.sysc		= &dra7xx_wd_timer_sysc,
	.pre_shutdown	= &omap2_wd_timer_disable,
	.reset		= &omap2_wd_timer_reset,
};

/* wd_timer2 */
static struct omap_hwmod_irq_info dra7xx_wd_timer2_irqs[] = {
	{ .irq = 80 + DRA7XX_IRQ_GIC_START },
	{ .irq = -1 }
};

static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
	.name		= "wd_timer2",
	.class		= &dra7xx_wd_timer_hwmod_class,
	.clkdm_name	= "wkupaon_clkdm",
	.mpu_irqs	= dra7xx_wd_timer2_irqs,
	.main_clk	= "sys_32k_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
			.context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};


/*
 * Interfaces
 */

static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
	{
		.pa_start	= 0x4e000000,
		.pa_end		= 0x4e0007ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_dmm_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_dmm_addrs,
	.user		= OCP_USER_SDMA,
};

/* dmm -> emif_ocp_fw */
static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
	.master		= &dra7xx_dmm_hwmod,
	.slave		= &dra7xx_emif_ocp_fw_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> emif_ocp_fw */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__emif_ocp_fw = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_emif_ocp_fw_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_2 -> l3_instr */
static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
	.master		= &dra7xx_l3_main_2_hwmod,
	.slave		= &dra7xx_l3_instr_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* ocp_wp_noc -> l3_instr */
static struct omap_hwmod_ocp_if dra7xx_ocp_wp_noc__l3_instr = {
	.master		= &dra7xx_ocp_wp_noc_hwmod,
	.slave		= &dra7xx_l3_instr_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_l3_main_1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_l3_main_1_addrs[] = {
	{
		.pa_start	= 0x44000000,
		.pa_end		= 0x44805fff,
	},
	{ }
};

/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
	.master		= &dra7xx_mpu_hwmod,
	.slave		= &dra7xx_l3_main_1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_l3_main_1_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dra7xx_l3_main_2_addrs[] = {
	{
		.pa_start	= 0x45000000,
		.pa_end		= 0x4500afff,
	},
	{ }
};

/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_l3_main_2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_l3_main_2_addrs,
	.user		= OCP_USER_MPU,
};

/* l4_cfg -> l3_main_2 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_l3_main_2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_l4_cfg_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmu0_dsp1_addrs[] = {
	{
		.pa_start	= 0x40d01000,
		.pa_end		= 0x40d010ff,
		.flags		= ADDR_TYPE_RT,
	},
	{
		.name		= "dsp_system",
		.pa_start	= 0x40d00000,
		.pa_end		= 0x40d000ff,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l3_main_1 -> mmu0_dsp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mmu0_dsp1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmu0_dsp1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmu1_dsp1_addrs[] = {
	{
		.pa_start	= 0x40d02000,
		.pa_end		= 0x40d020ff,
		.flags		= ADDR_TYPE_RT,
	},
	{
		.name		= "dsp_system",
		.pa_start	= 0x40d00000,
		.pa_end		= 0x40d000ff,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l3_main_1 -> mmu1_dsp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mmu1_dsp1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmu1_dsp1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmu0_dsp2_addrs[] = {
	{
		.pa_start	= 0x41501000,
		.pa_end		= 0x415010ff,
		.flags		= ADDR_TYPE_RT,
	},
	{
		.name		= "dsp_system",
		.pa_start	= 0x41500000,
		.pa_end		= 0x415000ff,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l3_main_1 -> mmu0_dsp2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mmu0_dsp2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmu0_dsp2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmu1_dsp2_addrs[] = {
	{
		.pa_start	= 0x41502000,
		.pa_end		= 0x415020ff,
		.flags		= ADDR_TYPE_RT,
	},
	{
		.name		= "dsp_system",
		.pa_start	= 0x41500000,
		.pa_end		= 0x415000ff,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l3_main_1 -> mmu1_dsp2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mmu1_dsp2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmu1_dsp2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmu_ipu1_addrs[] = {
	{
		.name		= "ipu_mmu",
		.pa_start	= 0x58882000,
		.pa_end		= 0x588820ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "unicache_mmu",
		.pa_start	= 0x58880800,
		.pa_end		= 0x58880fff,
	},
	{ }
};

/* l3_main_1 -> mmu_ipu1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mmu_ipu1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmu_ipu1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
#ifdef CONFIG_EARLYCAMERA_IPU
	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
#endif
};

static struct omap_hwmod_addr_space dra7xx_mmu_ipu2_addrs[] = {
	{
		.name		= "ipu_mmu",
		.pa_start	= 0x55082000,
		.pa_end		= 0x550820ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "unicache_mmu",
		.pa_start	= 0x55080800,
		.pa_end		= 0x55080fff,
	},
	{ }
};

/* l3_main_1 -> mmu_ipu2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mmu_ipu2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmu_ipu2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> l4_per1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_l4_per1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> l4_per2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_l4_per2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> l4_per3 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_l4_per3_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> l4_wkup */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_l4_wkup_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu -> mpu_private */
static struct omap_hwmod_ocp_if dra7xx_mpu__mpu_private = {
	.master		= &dra7xx_mpu_hwmod,
	.slave		= &dra7xx_mpu_private_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_2 -> ocp_wp_noc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_2__ocp_wp_noc = {
	.master		= &dra7xx_l3_main_2_hwmod,
	.slave		= &dra7xx_ocp_wp_noc_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_ocp_wp_noc_addrs[] = {
	{
		.pa_start	= 0x4a102000,
		.pa_end		= 0x4a10207f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> ocp_wp_noc */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp_wp_noc = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_ocp_wp_noc_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_ocp_wp_noc_addrs,
	.user		= OCP_USER_MPU,
};

/* l4_per2 -> atl */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_atl_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_bb2d_addrs[] = {
	{
		.pa_start	= 0x59000000,
		.pa_end		= 0x590007ff,
		.flags      = ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> bb2d */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_bb2d_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_bb2d_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_counter_32k_addrs[] = {
	{
		.pa_start	= 0x4ae04000,
		.pa_end		= 0x4ae0403f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_counter_32k_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.addr		= dra7xx_counter_32k_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_ctrl_module_wkup_addrs[] = {
	{
		.name		= "avatar_control_wkup_ocpintf",
		.pa_start	= 0x4ae0c100,
		.pa_end		= 0x4ae0c8ff,
	},
	{
		.name		= "avatar_control_wkup_pad_ocpintf",
		.pa_start	= 0x4ae0c5a0,
		.pa_end		= 0x4ae0c61f,
	},
	{ }
};

/* l4_wkup -> ctrl_module_wkup */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_ctrl_module_wkup_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.addr		= dra7xx_ctrl_module_wkup_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if dra7xx_l4_per2__gmac = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_gmac_hwmod,
	.clk		= "dpll_gmac_ck",
	.addr		= dra7xx_gmac_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
	.master		= &dra7xx_gmac_hwmod,
	.slave		= &dra7xx_mdio_hwmod,
	.addr		= dra7xx_mdio_addr_space,
	.user		= OCP_USER_MPU,
};

/* l4_wkup -> dcan1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_dcan1_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> dcan2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_dcan2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
	{
		.pa_start	= 0x4a056000,
		.pa_end		= 0x4a056fff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_dma_system_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dsp1 -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = {
	.master		= &dra7xx_dsp1_hwmod,
	.slave		= &dra7xx_l3_main_1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dsp2 -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
	.master		= &dra7xx_dsp2_hwmod,
	.slave		= &dra7xx_l3_main_1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
	{
		.name		= "family",
		.pa_start	= 0x58000000,
		.pa_end		= 0x5800007f,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "pllctrl1",
		.pa_start	= 0x58004000,
		.pa_end		= 0x5800433f,
	},
	{
		.name		= "pllctrl2",
		.pa_start	= 0x58009000,
		.pa_end		= 0x5800933f,
	},
};

/* l3_main_1 -> dss */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_dss_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_dss_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
	{
		.name		= "dispc",
		.pa_start	= 0x58001000,
		.pa_end		= 0x58001fff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_1 -> dispc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_dss_dispc_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_dss_dispc_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
	{
		.name		= "hdmi_wp",
		.pa_start	= 0x58040000,
		.pa_end		= 0x580400ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "pllctrl",
		.pa_start	= 0x58040200,
		.pa_end		= 0x5804023f,
	},
	{
		.name		= "hdmitxphy",
		.pa_start	= 0x58040300,
		.pa_end		= 0x5804033f,
	},
	{
		.name		= "hdmi_core",
		.pa_start	= 0x58060000,
		.pa_end		= 0x58078fff,
	},
	{
		.name		= "deshdcp",
		.pa_start	= 0x58007000,
		.pa_end		= 0x5800707f,
	},
	{ }
};

/* l3_main_1 -> dispc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_dss_hdmi_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_dss_hdmi_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
	{
		.pa_start	= 0x48078000,
		.pa_end		= 0x48078fff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> elm */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_elm_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_elm_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* emif_ocp_fw -> emif1 */
static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif1 = {
	.master		= &dra7xx_emif_ocp_fw_hwmod,
	.slave		= &dra7xx_emif1_hwmod,
	.clk		= "dpll_ddr_h11x2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_emif1_addrs[] = {
	{
		.pa_start	= 0x4c000000,
		.pa_end		= 0x4c0003ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* mpu -> emif1 */
static struct omap_hwmod_ocp_if dra7xx_mpu__emif1 = {
	.master		= &dra7xx_mpu_hwmod,
	.slave		= &dra7xx_emif1_hwmod,
	.clk		= "dpll_ddr_h11x2_ck",
	.addr		= dra7xx_emif1_addrs,
	.user		= OCP_USER_MPU,
};

/* emif_ocp_fw -> emif2 */
static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif2 = {
	.master		= &dra7xx_emif_ocp_fw_hwmod,
	.slave		= &dra7xx_emif2_hwmod,
	.clk		= "dpll_ddr_h11x2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_emif2_addrs[] = {
	{
		.pa_start	= 0x4d000000,
		.pa_end		= 0x4d0003ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* mpu -> emif2 */
static struct omap_hwmod_ocp_if dra7xx_mpu__emif2 = {
	.master		= &dra7xx_mpu_hwmod,
	.slave		= &dra7xx_emif2_hwmod,
	.clk		= "dpll_ddr_h11x2_ck",
	.addr		= dra7xx_emif2_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dra7xx_gpio1_addrs[] = {
	{
		.pa_start	= 0x4ae10000,
		.pa_end		= 0x4ae101ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_gpio1_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.addr		= dra7xx_gpio1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio2_addrs[] = {
	{
		.pa_start	= 0x48055000,
		.pa_end		= 0x480551ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio3_addrs[] = {
	{
		.pa_start	= 0x48057000,
		.pa_end		= 0x480571ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio4_addrs[] = {
	{
		.pa_start	= 0x48059000,
		.pa_end		= 0x480591ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio5_addrs[] = {
	{
		.pa_start	= 0x4805b000,
		.pa_end		= 0x4805b1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio5_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio6_addrs[] = {
	{
		.pa_start	= 0x4805d000,
		.pa_end		= 0x4805d1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio6_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio7_addrs[] = {
	{
		.pa_start	= 0x48051000,
		.pa_end		= 0x480511ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio7_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpio8_addrs[] = {
	{
		.pa_start	= 0x48053000,
		.pa_end		= 0x480531ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> gpio8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_gpio8_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpio8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
	{
		.pa_start	= 0x50000000,
		.pa_end		= 0x500003ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_gpmc_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_gpmc_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
	{
		.name		= "klio",
		.pa_start	= 0x56000000,
		.pa_end		= 0x56001fff,
	},
	{
		.name		= "hydra2",
		.pa_start	= 0x56004000,
		.pa_end		= 0x56004fff,
	},
	{
		.name		= "klio_0",
		.pa_start	= 0x56008000,
		.pa_end		= 0x56009fff,
	},
	{
		.name		= "klio_1",
		.pa_start	= 0x5600c000,
		.pa_end		= 0x5600dfff,
	},
	{
		.name		= "klio_hl",
		.pa_start	= 0x5600fe00,
		.pa_end		= 0x5600ffff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> gpu */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_gpu_hwmod,
	.clk		= "gpu_l3_iclk",
	.addr		= dra7xx_gpu_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
	{
		.pa_start	= 0x480b2000,
		.pa_end		= 0x480b201f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> hdq1w */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_hdq1w_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_hdq1w_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_i2c1_addrs[] = {
	{
		.pa_start	= 0x48070000,
		.pa_end		= 0x480700ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> i2c1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_i2c1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_i2c1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_i2c2_addrs[] = {
	{
		.pa_start	= 0x48072000,
		.pa_end		= 0x480720ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> i2c2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_i2c2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_i2c2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_i2c3_addrs[] = {
	{
		.pa_start	= 0x48060000,
		.pa_end		= 0x480600ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> i2c3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_i2c3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_i2c3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_i2c4_addrs[] = {
	{
		.pa_start	= 0x4807a000,
		.pa_end		= 0x4807a0ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> i2c4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_i2c4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_i2c4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_i2c5_addrs[] = {
	{
		.pa_start	= 0x4807c000,
		.pa_end		= 0x4807c0ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> i2c5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_i2c5_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_i2c5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox1_addrs[] = {
	{
		.pa_start	= 0x4a0f4000,
		.pa_end		= 0x4a0f41ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* ipu1 -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = {
	.master		= &dra7xx_ipu1_hwmod,
	.slave		= &dra7xx_l3_main_1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* ipu2 -> l3_main_1 */
static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = {
	.master		= &dra7xx_ipu2_hwmod,
	.slave		= &dra7xx_l3_main_1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> mailbox1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_mailbox1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox2_addrs[] = {
	{
		.pa_start	= 0x4883a000,
		.pa_end		= 0x4883a1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox3_addrs[] = {
	{
		.pa_start	= 0x4883c000,
		.pa_end		= 0x4883c1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox4_addrs[] = {
	{
		.pa_start	= 0x4883e000,
		.pa_end		= 0x4883e1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox5_addrs[] = {
	{
		.pa_start	= 0x48840000,
		.pa_end		= 0x488401ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox5_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox6_addrs[] = {
	{
		.pa_start	= 0x48842000,
		.pa_end		= 0x488421ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox6_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox7_addrs[] = {
	{
		.pa_start	= 0x48844000,
		.pa_end		= 0x488441ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox7_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox8_addrs[] = {
	{
		.pa_start	= 0x48846000,
		.pa_end		= 0x488461ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox8_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox9_addrs[] = {
	{
		.pa_start	= 0x4885e000,
		.pa_end		= 0x4885e1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox9 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox9_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox10_addrs[] = {
	{
		.pa_start	= 0x48860000,
		.pa_end		= 0x488601ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox10 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox10_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox11_addrs[] = {
	{
		.pa_start	= 0x48862000,
		.pa_end		= 0x488621ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox11 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox11_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox11_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox12_addrs[] = {
	{
		.pa_start	= 0x48864000,
		.pa_end		= 0x488641ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox12 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox12_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox12_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mailbox13_addrs[] = {
	{
		.pa_start	= 0x48802000,
		.pa_end		= 0x488021ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> mailbox13 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_mailbox13_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mailbox13_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> mcasp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mcasp1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp1_addrs[] = {
	{
		.pa_start	= 0x48460000,
		.pa_end		= 0x484603ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> mcasp1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_mcasp1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp1_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dra7xx_mcasp2_addrs[] = {
	{
		.pa_start	= 0x48464000,
		.pa_end		= 0x484643ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> mcasp2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mcasp2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp3_addrs[] = {
	{
		.pa_start	= 0x48468000,
		.pa_end		= 0x484683ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> mcasp3 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_mcasp3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp4_addrs[] = {
	{
		.pa_start	= 0x4846c000,
		.pa_end		= 0x4846c3ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> mcasp4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_mcasp4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp5_addrs[] = {
	{
		.pa_start	= 0x48470000,
		.pa_end		= 0x484703ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> mcasp5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_mcasp5_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp6_addrs[] = {
	{
		.pa_start	= 0x48474000,
		.pa_end		= 0x484743ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> mcasp6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_mcasp6_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp7_addrs[] = {
	{
		.pa_start	= 0x48478000,
		.pa_end		= 0x484783ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> mcasp7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_mcasp7_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcasp8_addrs[] = {
	{
		.pa_start	= 0x4847c000,
		.pa_end		= 0x4847c3ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> mcasp8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_mcasp8_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcasp8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcspi1_addrs[] = {
	{
		.pa_start	= 0x48098000,
		.pa_end		= 0x480981ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mcspi1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mcspi1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcspi1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcspi2_addrs[] = {
	{
		.pa_start	= 0x4809a000,
		.pa_end		= 0x4809a1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mcspi2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mcspi2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcspi2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcspi3_addrs[] = {
	{
		.pa_start	= 0x480b8000,
		.pa_end		= 0x480b81ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mcspi3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mcspi3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcspi3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mcspi4_addrs[] = {
	{
		.pa_start	= 0x480ba000,
		.pa_end		= 0x480ba1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mcspi4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mcspi4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mcspi4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmc1_addrs[] = {
	{
		.pa_start	= 0x4809c000,
		.pa_end		= 0x4809c3ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mmc1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mmc1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmc1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmc2_addrs[] = {
	{
		.pa_start	= 0x480b4000,
		.pa_end		= 0x480b43ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mmc2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mmc2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmc2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmc3_addrs[] = {
	{
		.pa_start	= 0x480ad000,
		.pa_end		= 0x480ad3ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mmc3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mmc3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmc3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mmc4_addrs[] = {
	{
		.pa_start	= 0x480d1000,
		.pa_end		= 0x480d13ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> mmc4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_mmc4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mmc4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_mpu_addrs[] = {
	{
		.pa_start	= 0x47000000,
		.pa_end		= 0x482af27f,
	},
	{ }
};

/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_mpu_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_mpu_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> ocmc_ram1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram1 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_ocmc_ram1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> ocmc_ram2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram2 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_ocmc_ram2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> ocmc_ram3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram3 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_ocmc_ram3_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> ocmc_rom */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__ocmc_rom = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_ocmc_rom_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
	{
		.pa_start	= 0x4a080000,
		.pa_end		= 0x4a08001f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> ocp2scp1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_ocp2scp1_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_ocp2scp1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_pruss1_addrs[] = {
	{
		.name		= "u_intc",
		.pa_start	= 0x4b220000,
		.pa_end		= 0x4b221fff,
	},
	{
		.name		= "u_pru0_ctrl",
		.pa_start	= 0x4b222000,
		.pa_end		= 0x4b22203f,
	},
	{
		.name		= "u_pru0_debug",
		.pa_start	= 0x4b222400,
		.pa_end		= 0x4b2224ff,
	},
	{
		.name		= "u_pru1_ctrl",
		.pa_start	= 0x4b224000,
		.pa_end		= 0x4b22403f,
	},
	{
		.name		= "u_pru1_debug",
		.pa_start	= 0x4b224400,
		.pa_end		= 0x4b2244ff,
	},
	{
		.name		= "u_cfg",
		.pa_start	= 0x4b226000,
		.pa_end		= 0x4b22607f,
	},
	{
		.name		= "u_uart",
		.pa_start	= 0x4b228000,
		.pa_end		= 0x4b22803f,
	},
	{
		.name		= "u_iep",
		.pa_start	= 0x4b22e000,
		.pa_end		= 0x4b22e3ff,
	},
	{
		.name		= "u_ecap",
		.pa_start	= 0x4b230000,
		.pa_end		= 0x4b23007f,
	},
	{
		.name		= "u_mii_rt_cfg",
		.pa_start	= 0x4b232000,
		.pa_end		= 0x4b23207f,
	},
	{
		.name		= "u_mii_mdio",
		.pa_start	= 0x4b232400,
		.pa_end		= 0x4b2324ff,
	},
	{ }
};

/* l3_main_1 -> pruss1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_pruss1_hwmod,
	.clk		= "dpll_gmac_h13x2_ck",
	.addr		= dra7xx_pruss1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_pruss2_addrs[] = {
	{
		.name		= "u_intc",
		.pa_start	= 0x4b2a0000,
		.pa_end		= 0x4b2a1fff,
	},
	{
		.name		= "u_pru0_ctrl",
		.pa_start	= 0x4b2a2000,
		.pa_end		= 0x4b2a203f,
	},
	{
		.name		= "u_pru0_debug",
		.pa_start	= 0x4b2a2400,
		.pa_end		= 0x4b2a24ff,
	},
	{
		.name		= "u_pru1_ctrl",
		.pa_start	= 0x4b2a4000,
		.pa_end		= 0x4b2a403f,
	},
	{
		.name		= "u_pru1_debug",
		.pa_start	= 0x4b2a4400,
		.pa_end		= 0x4b2a44ff,
	},
	{
		.name		= "u_cfg",
		.pa_start	= 0x4b2a6000,
		.pa_end		= 0x4b2a607f,
	},
	{
		.name		= "u_uart",
		.pa_start	= 0x4b2a8000,
		.pa_end		= 0x4b2a803f,
	},
	{
		.name		= "u_iep",
		.pa_start	= 0x4b2ae000,
		.pa_end		= 0x4b2ae3ff,
	},
	{
		.name		= "u_ecap",
		.pa_start	= 0x4b2b0000,
		.pa_end		= 0x4b2b007f,
	},
	{
		.name		= "u_mii_rt_cfg",
		.pa_start	= 0x4b2b2000,
		.pa_end		= 0x4b2b207f,
	},
	{
		.name		= "u_mii_mdio",
		.pa_start	= 0x4b2b2400,
		.pa_end		= 0x4b2b24ff,
	},
	{ }
};

/* l3_main_1 -> pruss2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_pruss2_hwmod,
	.clk		= "dpll_gmac_h13x2_ck",
	.addr		= dra7xx_pruss2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> pwmss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss1 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_pwmss1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> pwmss2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss2 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_pwmss2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> pwmss3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss3 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_pwmss3_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
	{
		.pa_start	= 0x4b300000,
		.pa_end		= 0x4b30007f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l3_main_1 -> qspi */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_qspi_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_qspi_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_rtcss_addrs[] = {
	{
		.pa_start	= 0x48838000,
		.pa_end		= 0x488380ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> rtcss */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_rtcss_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_rtcss_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
	{
		.name		= "ahci",
		.pa_start	= 0x4a140000,
		.pa_end		= 0x4a1401ff,
	},
	{
		.name		= "sysc",
		.pa_start	= 0x4a141100,
		.pa_end		= 0x4a141107,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> sata */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_sata_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_sata_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
	{
		.pa_start	= 0x4a0dd000,
		.pa_end		= 0x4a0dd07f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> smartreflex_core */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_smartreflex_core_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_smartreflex_core_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_smartreflex_dspeve_addrs[] = {
	{
		.pa_start	= 0x4a183000,
		.pa_end		= 0x4a18307f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> smartreflex_dspeve */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_dspeve = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_smartreflex_dspeve_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_smartreflex_dspeve_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_smartreflex_gpu_addrs[] = {
	{
		.pa_start	= 0x4a185000,
		.pa_end		= 0x4a18507f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> smartreflex_gpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_gpu = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_smartreflex_gpu_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_smartreflex_gpu_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
	{
		.pa_start	= 0x4a0d9000,
		.pa_end		= 0x4a0d907f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> smartreflex_mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_smartreflex_mpu_hwmod,
	.clk		= "l4_root_clk_div",
	.addr		= dra7xx_smartreflex_mpu_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> spare_cme */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_cme = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_spare_cme_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> spare_icm */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_icm = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_spare_icm_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> spare_iva2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__spare_iva2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_spare_iva2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> spare_safety1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety1 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_spare_safety1_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> spare_safety2 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety2 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_spare_safety2_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> spare_safety3 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety3 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_spare_safety3_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> spare_safety4 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety4 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_spare_safety4_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> spare_unknown2 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown2 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_spare_unknown2_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> spare_unknown3 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown3 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_spare_unknown3_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> spare_unknown4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown4 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_spare_unknown4_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> spare_unknown5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown5 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_spare_unknown5_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> spare_unknown6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown6 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_spare_unknown6_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> spare_videopll1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll1 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_spare_videopll1_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> spare_videopll2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll2 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_spare_videopll2_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> spare_videopll3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll3 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_spare_videopll3_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> spare_sata2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_sata2 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_spare_sata2_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> spare_smartreflex_rtc */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_rtc = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_spare_smartreflex_rtc_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> spare_smartreflex_sdram */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_sdram = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_spare_smartreflex_sdram_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> spare_smartreflex_wkup */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_wkup = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_spare_smartreflex_wkup_hwmod,
	.clk		= "l4_root_clk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
	{
		.pa_start	= 0x4a0f6000,
		.pa_end		= 0x4a0f6fff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
	.master		= &dra7xx_l4_cfg_hwmod,
	.slave		= &dra7xx_spinlock_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_spinlock_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer1_addrs[] = {
	{
		.pa_start	= 0x4ae18000,
		.pa_end		= 0x4ae1807f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_timer1_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.addr		= dra7xx_timer1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer2_addrs[] = {
	{
		.pa_start	= 0x48032000,
		.pa_end		= 0x4803207f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> timer2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_timer2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer3_addrs[] = {
	{
		.pa_start	= 0x48034000,
		.pa_end		= 0x4803407f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> timer3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_timer3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer4_addrs[] = {
	{
		.pa_start	= 0x48036000,
		.pa_end		= 0x4803607f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> timer4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_timer4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer5_addrs[] = {
	{
		.pa_start	= 0x48820000,
		.pa_end		= 0x4882007f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer5_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer6_addrs[] = {
	{
		.pa_start	= 0x48822000,
		.pa_end		= 0x4882207f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer6_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer7_addrs[] = {
	{
		.pa_start	= 0x48824000,
		.pa_end		= 0x4882407f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer7_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer8_addrs[] = {
	{
		.pa_start	= 0x48826000,
		.pa_end		= 0x4882607f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer8_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer9_addrs[] = {
	{
		.pa_start	= 0x4803e000,
		.pa_end		= 0x4803e07f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> timer9 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_timer9_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer10_addrs[] = {
	{
		.pa_start	= 0x48086000,
		.pa_end		= 0x4808607f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> timer10 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_timer10_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer11_addrs[] = {
	{
		.pa_start	= 0x48088000,
		.pa_end		= 0x4808807f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> timer11 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_timer11_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer11_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer13_addrs[] = {
	{
		.pa_start	= 0x48828000,
		.pa_end		= 0x4882807f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer13 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer13_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer13_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer14_addrs[] = {
	{
		.pa_start	= 0x4882a000,
		.pa_end		= 0x4882a07f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer14 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer14_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer14_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer15_addrs[] = {
	{
		.pa_start	= 0x4882c000,
		.pa_end		= 0x4882c07f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer15 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer15_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer15_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_timer16_addrs[] = {
	{
		.pa_start	= 0x4882e000,
		.pa_end		= 0x4882e07f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per3 -> timer16 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_timer16_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_timer16_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart1_addrs[] = {
	{
		.pa_start	= 0x4806a000,
		.pa_end		= 0x4806a0ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> uart1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_uart1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart2_addrs[] = {
	{
		.pa_start	= 0x4806c000,
		.pa_end		= 0x4806c0ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> uart2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_uart2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart3_addrs[] = {
	{
		.pa_start	= 0x48020000,
		.pa_end		= 0x480200ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> uart3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_uart3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart4_addrs[] = {
	{
		.pa_start	= 0x4806e000,
		.pa_end		= 0x4806e0ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> uart4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_uart4_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart5_addrs[] = {
	{
		.pa_start	= 0x48066000,
		.pa_end		= 0x480660ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> uart5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_uart5_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart6_addrs[] = {
	{
		.pa_start	= 0x48068000,
		.pa_end		= 0x480680ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per1 -> uart6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
	.master		= &dra7xx_l4_per1_hwmod,
	.slave		= &dra7xx_uart6_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart7_addrs[] = {
	{
		.pa_start	= 0x48420000,
		.pa_end		= 0x484200ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> uart7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_uart7_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart8_addrs[] = {
	{
		.pa_start	= 0x48422000,
		.pa_end		= 0x484220ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> uart8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_uart8_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart9_addrs[] = {
	{
		.pa_start	= 0x48424000,
		.pa_end		= 0x484240ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_per2 -> uart9 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_uart9_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_uart9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_uart10_addrs[] = {
	{
		.pa_start	= 0x4ae2b000,
		.pa_end		= 0x4ae2b0ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> uart10 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_uart10_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.addr		= dra7xx_uart10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> usb_otg_ss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_usb_otg_ss1_hwmod,
	.clk		= "dpll_core_h13x2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> usb_otg_ss2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_usb_otg_ss2_hwmod,
	.clk		= "dpll_core_h13x2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> usb_otg_ss3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_usb_otg_ss3_hwmod,
	.clk		= "dpll_core_h13x2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per3 -> usb_otg_ss4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_usb_otg_ss4_hwmod,
	.clk		= "dpll_core_h13x2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> vcp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_vcp1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> vcp1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_vcp1_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 -> vcp2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
	.master		= &dra7xx_l3_main_1_hwmod,
	.slave		= &dra7xx_vcp2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per2 -> vcp2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
	.master		= &dra7xx_l4_per2_hwmod,
	.slave		= &dra7xx_vcp2_hwmod,
	.clk		= "l3_iclk_div",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_vip1_addrs[] = {
	{
		.name		= "vip_top_level",
		.pa_start	= 0x48970000,
		.pa_end		= 0x489701ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "vip_slice0_parser",
		.pa_start	= 0x48975500,
		.pa_end		= 0x489755ff,
	},
	{
		.name		= "vip_slice0_csc",
		.pa_start	= 0x48975700,
		.pa_end		= 0x4897571f,
	},
	{
		.name		= "vip_slice0_sc",
		.pa_start	= 0x48975800,
		.pa_end		= 0x4897587f,
	},
	{
		.name		= "vip_slice1_parser",
		.pa_start	= 0x48975a00,
		.pa_end		= 0x48975aff,
	},
	{
		.name		= "vip_slice1_csc",
		.pa_start	= 0x48975c00,
		.pa_end		= 0x48975c1f,
	},
	{
		.name		= "vip_slice1_sc",
		.pa_start	= 0x48975d00,
		.pa_end		= 0x48975d7f,
	},
	{
		.name		= "vip_vpdma",
		.pa_start	= 0x4897d000,
		.pa_end		= 0x4897d3ff,
	},
	{ }
};

/* l4_per3 -> vip1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_vip1_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_vip1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_vip2_addrs[] = {
	{
		.name		= "vip_top_level",
		.pa_start	= 0x48990000,
		.pa_end		= 0x489901ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "vip_slice0_parser",
		.pa_start	= 0x48995500,
		.pa_end		= 0x489955ff,
	},
	{
		.name		= "vip_slice0_csc",
		.pa_start	= 0x48995700,
		.pa_end		= 0x4899571f,
	},
	{
		.name		= "vip_slice0_sc",
		.pa_start	= 0x48995800,
		.pa_end		= 0x4899587f,
	},
	{
		.name		= "vip_slice1_parser",
		.pa_start	= 0x48995a00,
		.pa_end		= 0x48995aff,
	},
	{
		.name		= "vip_slice1_csc",
		.pa_start	= 0x48995c00,
		.pa_end		= 0x48995c1f,
	},
	{
		.name		= "vip_slice1_sc",
		.pa_start	= 0x48995d00,
		.pa_end		= 0x48995d7f,
	},
	{
		.name		= "vip_vpdma",
		.pa_start	= 0x4899d000,
		.pa_end		= 0x4899d3ff,
	},
	{ }
};

/* l4_per3 -> vip2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_vip2_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_vip2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_vip3_addrs[] = {
	{
		.name		= "vip_top_level",
		.pa_start	= 0x489b0000,
		.pa_end		= 0x489b01ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name		= "vip_slice0_parser",
		.pa_start	= 0x489b5500,
		.pa_end		= 0x489b55ff,
	},
	{
		.name		= "vip_slice0_csc",
		.pa_start	= 0x489b5700,
		.pa_end		= 0x489b571f,
	},
	{
		.name		= "vip_slice0_sc",
		.pa_start	= 0x489b5800,
		.pa_end		= 0x489b587f,
	},
	{
		.name		= "vip_slice1_parser",
		.pa_start	= 0x489b5a00,
		.pa_end		= 0x489b5aff,
	},
	{
		.name		= "vip_slice1_csc",
		.pa_start	= 0x489b5c00,
		.pa_end		= 0x489b5c1f,
	},
	{
		.name		= "vip_slice1_sc",
		.pa_start	= 0x489b5d00,
		.pa_end		= 0x489b5d7f,
	},
	{
		.name		= "vip_vpdma",
		.pa_start	= 0x489bd000,
		.pa_end		= 0x489bd3ff,
	},
	{ }
};

/* l4_per3 -> vip3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_vip3_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_vip3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_vpe_addrs[] = {
	{
		.name		= "vpe",
		.pa_start	= 0x489d0000,
		.pa_end		= 0x489d06ff,
		.flags		= ADDR_TYPE_RT
	},
	{
		.name           = "vpe_sc",
		.pa_start       = 0x489d0700,
		.pa_end         = 0x489d56ff,
	},
	{
		.name           = "vpe_csc",
		.pa_start       = 0x489d5700,
		.pa_end         = 0x489dcfff,
	},
	{
		.name		= "vpdma",
		.pa_start	= 0x489dd000,
		.pa_end		= 0x489dd3ff,
	},
	{ }
};

/* l4_per3 -> vpe */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
	.master		= &dra7xx_l4_per3_hwmod,
	.slave		= &dra7xx_vpe_hwmod,
	.clk		= "l3_iclk_div",
	.addr		= dra7xx_vpe_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space dra7xx_wd_timer2_addrs[] = {
	{
		.pa_start	= 0x4ae14000,
		.pa_end		= 0x4ae1407f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
	.master		= &dra7xx_l4_wkup_hwmod,
	.slave		= &dra7xx_wd_timer2_hwmod,
	.clk		= "wkupaon_iclk_mux",
	.addr		= dra7xx_wd_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
	&dra7xx_l3_main_1__dmm,
	&dra7xx_dmm__emif_ocp_fw,
	&dra7xx_l4_cfg__emif_ocp_fw,
	&dra7xx_l3_main_2__l3_instr,
	&dra7xx_ocp_wp_noc__l3_instr,
	&dra7xx_l4_cfg__l3_main_1,
	&dra7xx_mpu__l3_main_1,
	&dra7xx_l3_main_1__l3_main_2,
	&dra7xx_l4_cfg__l3_main_2,
	&dra7xx_l3_main_1__l4_cfg,
	&dra7xx_l3_main_1__l4_per1,
	&dra7xx_l3_main_1__l4_per2,
	&dra7xx_l3_main_1__l4_per3,
	&dra7xx_l3_main_1__l4_wkup,
	&dra7xx_mpu__mpu_private,
	&dra7xx_l3_main_2__ocp_wp_noc,
	&dra7xx_l4_cfg__ocp_wp_noc,
	&dra7xx_l4_per2__atl,
	&dra7xx_l3_main_1__bb2d,
	&dra7xx_l4_wkup__counter_32k,
	&dra7xx_l4_wkup__ctrl_module_wkup,
	&dra7xx_l4_wkup__dcan1,
	&dra7xx_l4_per2__dcan2,
	&dra7xx_l4_per2__gmac,
	&dra7xx_gmac__mdio,
	&dra7xx_l4_cfg__dma_system,
	&dra7xx_l3_main_1__dss,
	&dra7xx_l3_main_1__dispc,
	&dra7xx_dsp1__l3_main_1,
	&dra7xx_dsp2__l3_main_1,
	&dra7xx_l3_main_1__hdmi,
	&dra7xx_l4_per1__elm,
	&dra7xx_emif_ocp_fw__emif1,
	&dra7xx_mpu__emif1,
	&dra7xx_emif_ocp_fw__emif2,
	&dra7xx_mpu__emif2,
	&dra7xx_l4_wkup__gpio1,
	&dra7xx_l4_per1__gpio2,
	&dra7xx_l4_per1__gpio3,
	&dra7xx_l4_per1__gpio4,
	&dra7xx_l4_per1__gpio5,
	&dra7xx_l4_per1__gpio6,
	&dra7xx_l4_per1__gpio7,
	&dra7xx_l4_per1__gpio8,
	&dra7xx_l3_main_1__gpmc,
	&dra7xx_l3_main_1__gpu,
	&dra7xx_l4_per1__hdq1w,
	&dra7xx_l4_per1__i2c1,
	&dra7xx_l4_per1__i2c2,
	&dra7xx_l4_per1__i2c3,
	&dra7xx_l4_per1__i2c4,
	&dra7xx_l4_per1__i2c5,
	&dra7xx_ipu1__l3_main_1,
	&dra7xx_ipu2__l3_main_1,
	&dra7xx_l4_cfg__mailbox1,
	&dra7xx_l4_per3__mailbox2,
	&dra7xx_l4_per3__mailbox3,
	&dra7xx_l4_per3__mailbox4,
	&dra7xx_l4_per3__mailbox5,
	&dra7xx_l4_per3__mailbox6,
	&dra7xx_l4_per3__mailbox7,
	&dra7xx_l4_per3__mailbox8,
	&dra7xx_l4_per3__mailbox9,
	&dra7xx_l4_per3__mailbox10,
	&dra7xx_l4_per3__mailbox11,
	&dra7xx_l4_per3__mailbox12,
	&dra7xx_l4_per3__mailbox13,
	&dra7xx_l3_main_1__mcasp1,
	&dra7xx_l4_per2__mcasp1,
	&dra7xx_l3_main_1__mcasp2,
	&dra7xx_l3_main_1__mcasp3,
	&dra7xx_l4_per2__mcasp4,
	&dra7xx_l4_per2__mcasp5,
	&dra7xx_l4_per2__mcasp6,
	&dra7xx_l4_per2__mcasp7,
	&dra7xx_l4_per2__mcasp8,
	&dra7xx_l4_per1__mcspi1,
	&dra7xx_l4_per1__mcspi2,
	&dra7xx_l4_per1__mcspi3,
	&dra7xx_l4_per1__mcspi4,
	&dra7xx_l4_per1__mmc1,
	&dra7xx_l4_per1__mmc2,
	&dra7xx_l4_per1__mmc3,
	&dra7xx_l4_per1__mmc4,
	&dra7xx_l3_main_1__mmu0_dsp1,
	&dra7xx_l3_main_1__mmu1_dsp1,
	&dra7xx_l3_main_1__mmu0_dsp2,
	&dra7xx_l3_main_1__mmu1_dsp2,
	&dra7xx_l3_main_1__mmu_ipu1,
	&dra7xx_l3_main_1__mmu_ipu2,
	&dra7xx_l4_cfg__mpu,
	&dra7xx_l4_per3__ocmc_ram1,
	&dra7xx_l4_per3__ocmc_ram2,
	&dra7xx_l4_per3__ocmc_ram3,
	&dra7xx_l3_main_1__ocmc_rom,
	&dra7xx_l4_cfg__ocp2scp1,
	&dra7xx_l4_cfg__ocp2scp3,
	&dra7xx_l3_main_1__pruss1,
	&dra7xx_l3_main_1__pruss2,
	&dra7xx_l4_per2__pwmss1,
	&dra7xx_l4_per2__pwmss2,
	&dra7xx_l4_per2__pwmss3,
	&dra7xx_l3_main_1__qspi,
	&dra7xx_l4_per3__rtcss,
	&dra7xx_l4_cfg__sata,
	&dra7xx_l4_cfg__smartreflex_core,
	&dra7xx_l4_cfg__smartreflex_dspeve,
	&dra7xx_l4_cfg__smartreflex_gpu,
	&dra7xx_l4_cfg__smartreflex_mpu,
	&dra7xx_l4_per3__spare_cme,
	&dra7xx_l4_per3__spare_icm,
	&dra7xx_l3_main_1__spare_iva2,
	&dra7xx_l4_wkup__spare_safety1,
	&dra7xx_l4_wkup__spare_safety2,
	&dra7xx_l4_wkup__spare_safety3,
	&dra7xx_l4_wkup__spare_safety4,
	&dra7xx_l4_wkup__spare_unknown2,
	&dra7xx_l4_wkup__spare_unknown3,
	&dra7xx_l4_per2__spare_unknown4,
	&dra7xx_l4_per2__spare_unknown5,
	&dra7xx_l4_per2__spare_unknown6,
	&dra7xx_l4_per3__spare_videopll1,
	&dra7xx_l4_per3__spare_videopll2,
	&dra7xx_l4_per3__spare_videopll3,
	&dra7xx_l4_per3__spare_sata2,
	&dra7xx_l4_cfg__spare_smartreflex_rtc,
	&dra7xx_l4_cfg__spare_smartreflex_sdram,
	&dra7xx_l4_cfg__spare_smartreflex_wkup,
	&dra7xx_l4_cfg__spinlock,
	&dra7xx_l4_wkup__timer1,
	&dra7xx_l4_per1__timer2,
	&dra7xx_l4_per1__timer3,
	&dra7xx_l4_per1__timer4,
	&dra7xx_l4_per3__timer5,
	&dra7xx_l4_per3__timer6,
	&dra7xx_l4_per3__timer7,
	&dra7xx_l4_per3__timer8,
	&dra7xx_l4_per1__timer9,
	&dra7xx_l4_per1__timer10,
	&dra7xx_l4_per1__timer11,
	&dra7xx_l4_per3__timer13,
	&dra7xx_l4_per3__timer14,
	&dra7xx_l4_per3__timer15,
	&dra7xx_l4_per3__timer16,
	&dra7xx_l4_per1__uart1,
	&dra7xx_l4_per1__uart2,
	&dra7xx_l4_per1__uart3,
	&dra7xx_l4_per1__uart4,
	&dra7xx_l4_per1__uart5,
	&dra7xx_l4_per1__uart6,
	&dra7xx_l4_per2__uart7,
	&dra7xx_l4_per2__uart8,
	&dra7xx_l4_per2__uart9,
	&dra7xx_l4_wkup__uart10,
	&dra7xx_l4_per3__usb_otg_ss1,
	&dra7xx_l4_per3__usb_otg_ss2,
	&dra7xx_l4_per3__usb_otg_ss3,
	&dra7xx_l4_per3__usb_otg_ss4,
	&dra7xx_l3_main_1__vcp1,
	&dra7xx_l4_per2__vcp1,
	&dra7xx_l3_main_1__vcp2,
	&dra7xx_l4_per2__vcp2,
	&dra7xx_l4_per3__vip1,
	&dra7xx_l4_per3__vip2,
	&dra7xx_l4_per3__vip3,
	&dra7xx_l4_per3__vpe,
	&dra7xx_l4_wkup__wd_timer2,
	NULL,
};

int __init dra7xx_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
}
