From 1118175c063cf00fb23cd1814a26513c7110928f Mon Sep 17 00:00:00 2001 From: tejas Date: Mon, 10 Nov 2014 17:50:50 +0530 Subject: [PATCH] DDR3 chnages Signed-off-by: tejas --- Makefile | 3 +- arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h | 57 +++++++++++--------- board/ti/ti813x/evm.c | 7 +++ board/ti/ti8148_ipnc/evm.c | 63 ++++++++++++++++------ board/ti/ti8148_ipnc/mux.h | 44 +++++++-------- 5 files changed, 109 insertions(+), 65 deletions(-) diff --git a/Makefile b/Makefile index d6a28ff..cfbec09 100755 --- a/Makefile +++ b/Makefile @@ -3332,7 +3332,7 @@ ti8148_ipnc_min_sd: unconfig @echo "#define CONFIG_TI814X" >>$(obj)include/config.h @echo "#define CONFIG_TI814X_IPNC" >>$(obj)include/config.h @if [ "$(findstring _min_,$@)" ] ; then \ - echo "TEXT_BASE = 0x80700000" >> $(obj)board/ti/ti8148_ipnc/config.tmp; \ + echo "TEXT_BASE = 0x40300000" >> $(obj)board/ti/ti8148_ipnc/config.tmp; \ echo "#define CONFIG_TI814X_MIN_CONFIG" >>$(obj)include/config.h ; \ echo "Setting up TI8148 minimal build for 1st stage..." ; \ if [ "$(findstring nand,$@)" ] ; then \ @@ -3529,6 +3529,7 @@ ti813x_evm_min_sd: unconfig @echo "#define CONFIG_TI813X" >>$(obj)include/config.h @if [ "$(findstring _min_,$@)" ] ; then \ + echo "TEXT_BASE = 0x40300000" >> $(obj)board/ti/ti8148/config.tmp; \ echo "#define CONFIG_TI813X_MIN_CONFIG" >>$(obj)include/config.h ; \ echo "Setting up TI813X minimal build for 1st stage..." ; \ if [ "$(findstring nand,$@)" ] ; then \ diff --git a/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h b/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h index 689fec8..65afbbd 100755 --- a/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h +++ b/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h @@ -23,6 +23,11 @@ #include +/* select the emif instance */ +#define USE_EMIF0 1 +#define USE_EMIF1 0 + + /* DDR Phy MMRs OFFSETs */ #define CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 0x01C #define CMD0_REG_PHY_DLL_LOCK_DIFF_0 0x028 @@ -211,25 +216,25 @@ #else /* TI814X DDR3 PHY CFG parameters */ -#define DDR3_PHY_RD_DQS_CS0_BYTE0 ((emif == 0) ? 0x3d : 0x39) //((emif == 0) ? 0x30 : 0x30) -#define DDR3_PHY_RD_DQS_CS0_BYTE1 ((emif == 0) ? 0x3c : 0x3c) //((emif == 0) ? 0x30 : 0x30) -#define DDR3_PHY_RD_DQS_CS0_BYTE2 ((emif == 0) ? 0x3e : 0x3c) //((emif == 0) ? 0x30 : 0x30) -#define DDR3_PHY_RD_DQS_CS0_BYTE3 ((emif == 0) ? 0x3d : 0x3e) //((emif == 0) ? 0x30 : 0x30) - -#define DDR3_PHY_WR_DQS_CS0_BYTE0 ((emif == 0) ? 0x45 : 0x40) //((emif == 0) ? 0x21 : 0x21) -#define DDR3_PHY_WR_DQS_CS0_BYTE1 ((emif == 0) ? 0x44 : 0x3f) //((emif == 0) ? 0x21 : 0x21) -#define DDR3_PHY_WR_DQS_CS0_BYTE2 ((emif == 0) ? 0x47 : 0x45) //((emif == 0) ? 0x21 : 0x21) -#define DDR3_PHY_WR_DQS_CS0_BYTE3 ((emif == 0) ? 0x47 : 0x42) //((emif == 0) ? 0x21 : 0x21) - -#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0 ((emif == 0) ? 0x9d : 0x9e) //((emif == 0) ? 0xc0 : 0xc0) -#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1 ((emif == 0) ? 0x9e : 0x9c) //((emif == 0) ? 0xc0 : 0xc0) -#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2 ((emif == 0) ? 0xa7 : 0xa3) //((emif == 0) ? 0xc0 : 0xc0) -#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3 ((emif == 0) ? 0xa9 : 0xa9) //((emif == 0) ? 0xc0 : 0xc0) - -#define DDR3_PHY_WR_DATA_CS0_BYTE0 ((emif == 0) ? 0x7e : 0x78) //((emif == 0) ? 0x44 : 0x44) -#define DDR3_PHY_WR_DATA_CS0_BYTE1 ((emif == 0) ? 0x7f : 0x7b) //((emif == 0) ? 0x44 : 0x44) -#define DDR3_PHY_WR_DATA_CS0_BYTE2 ((emif == 0) ? 0x7f : 0x7b) //((emif == 0) ? 0x44 : 0x44) -#define DDR3_PHY_WR_DATA_CS0_BYTE3 ((emif == 0) ? 0x80 : 0x7e) //((emif == 0) ? 0x44 : 0x44) +#define DDR3_PHY_RD_DQS_CS0_BYTE0 ((emif == 0) ? 0x39 : 0x39) //((emif == 0) ? 0x30 : 0x30) +#define DDR3_PHY_RD_DQS_CS0_BYTE1 ((emif == 0) ? 0x39 : 0x39) //((emif == 0) ? 0x30 : 0x30) +#define DDR3_PHY_RD_DQS_CS0_BYTE2 ((emif == 0) ? 0x37 : 0x37) //((emif == 0) ? 0x30 : 0x30) +#define DDR3_PHY_RD_DQS_CS0_BYTE3 ((emif == 0) ? 0x38 : 0x38) //((emif == 0) ? 0x30 : 0x30) + +#define DDR3_PHY_WR_DQS_CS0_BYTE0 ((emif == 0) ? 0x44 : 0x44) //((emif == 0) ? 0x21 : 0x21) +#define DDR3_PHY_WR_DQS_CS0_BYTE1 ((emif == 0) ? 0x45 : 0x45) //((emif == 0) ? 0x21 : 0x21) +#define DDR3_PHY_WR_DQS_CS0_BYTE2 ((emif == 0) ? 0x4c : 0x4c) //((emif == 0) ? 0x21 : 0x21) +#define DDR3_PHY_WR_DQS_CS0_BYTE3 ((emif == 0) ? 0x4d : 0x4d) //((emif == 0) ? 0x21 : 0x21) + +#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0 ((emif == 0) ? 0x9f : 0x9f) //((emif == 0) ? 0xc0 : 0xc0) +#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1 ((emif == 0) ? 0xa0 : 0xa0) //((emif == 0) ? 0xc0 : 0xc0) +#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2 ((emif == 0) ? 0xa6 : 0xa6) //((emif == 0) ? 0xc0 : 0xc0) +#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3 ((emif == 0) ? 0xa6 : 0xa6) //((emif == 0) ? 0xc0 : 0xc0) + +#define DDR3_PHY_WR_DATA_CS0_BYTE0 ((emif == 0) ? 0x87 : 0x87) //((emif == 0) ? 0x44 : 0x44) +#define DDR3_PHY_WR_DATA_CS0_BYTE1 ((emif == 0) ? 0x87 : 0x87) //((emif == 0) ? 0x44 : 0x44) +#define DDR3_PHY_WR_DATA_CS0_BYTE2 ((emif == 0) ? 0x86 : 0x86) //((emif == 0) ? 0x44 : 0x44) +#define DDR3_PHY_WR_DATA_CS0_BYTE3 ((emif == 0) ? 0x88 : 0x88) //((emif == 0) ? 0x44 : 0x44) #define DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE 0x80 #endif @@ -311,11 +316,11 @@ #else /* TI814X DDR3 EMIF CFG Registers values 400MHz */ #define DDR3_EMIF_READ_LATENCY 0x00170208 //RD_ODT=0x2, IDLE_ODT=0x0, Dynamic power_down enabled -#define DDR3_EMIF_TIM1 0x0AAAD4DB -#define DDR3_EMIF_TIM2 0x682F7FDA -#define DDR3_EMIF_TIM3 0x501F82BF -#define DDR3_EMIF_REF_CTRL 0x00000C30 -#define DDR3_EMIF_SDRAM_CONFIG 0x61C011B2 +#define DDR3_EMIF_TIM1 0x088AE4E3 +#define DDR3_EMIF_TIM2 0x20437FDA +#define DDR3_EMIF_TIM3 0x507F83FF +#define DDR3_EMIF_REF_CTRL 0x00000c30 +#define DDR3_EMIF_SDRAM_CONFIG 0x61C40AB2 #define DDR3_EMIF_SDRAM_ZQCR 0x50074BE1 #endif @@ -335,7 +340,9 @@ #define PG2_1_DMM_LISA_MAP__0 0x0 #define PG2_1_DMM_LISA_MAP__1 0x0 #define PG2_1_DMM_LISA_MAP__2 0x805C0300 -#define PG2_1_DMM_LISA_MAP__3 0xA05C0300 +#define PG2_1_DMM_LISA_MAP__3 0x805C0300 + +#define MIN_DMM_LISA_MAP__3 0x80600100 /* * TI813X DM385 DMM LISA MAPPING diff --git a/board/ti/ti813x/evm.c b/board/ti/ti813x/evm.c index eea2f34..9439961 100755 --- a/board/ti/ti813x/evm.c +++ b/board/ti/ti813x/evm.c @@ -101,6 +101,7 @@ static void iva_pll_config(void); static void usb_pll_config(void); #endif +void ipnc_ff_pll_init(int); static void unlock_pll_control_mmr(void); #ifdef CONFIG_DRIVER_TI_CPSW static void cpsw_pad_config(void); @@ -114,7 +115,13 @@ static inline void delay(unsigned long loops) __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b" : "=r" (loops) : "0"(loops)); } +void ipnc_ff_pll_init(int option) +{ + if(option == 1) { + } else { + } +} /* * Basic board specific setup */ diff --git a/board/ti/ti8148_ipnc/evm.c b/board/ti/ti8148_ipnc/evm.c index 0591a34..d5ab731 100755 --- a/board/ti/ti8148_ipnc/evm.c +++ b/board/ti/ti8148_ipnc/evm.c @@ -349,25 +349,33 @@ static void config_ti814x_ddr(void) /*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/ __raw_writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL); __raw_writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL); /*Enable EMIF0 Clock*/ - __raw_writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); /*Enable EMIF1 Clock*/ + + if(USE_EMIF1) { + __raw_writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); /*Enable EMIF1 Clock*/ + } __raw_writel(0x2, CM_DEFAULT_DMM_CLKCTRL); /*Poll for L3_FAST_GCLK & DDR_GCLK are active*/ while ((__raw_readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300); /*Poll for Module is functional*/ while ((__raw_readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2); - while ((__raw_readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2); + if(USE_EMIF1) { + while ((__raw_readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2); + } while ((__raw_readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2); if (is_ddr3()) { cmd_macro_config(DDR_PHY0, DDR3_PHY_INVERT_CLKOUT_OFF, DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE, PHY_CMD0_DLL_LOCK_DIFF_DEFINE); - cmd_macro_config(DDR_PHY1, DDR3_PHY_INVERT_CLKOUT_OFF, - DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE, - PHY_CMD0_DLL_LOCK_DIFF_DEFINE); - for (emif = 0; emif <= DDR_PHY1; emif++) { + if(USE_EMIF1){ + cmd_macro_config(DDR_PHY1, DDR3_PHY_INVERT_CLKOUT_OFF, + DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE, + PHY_CMD0_DLL_LOCK_DIFF_DEFINE); + } + + for (emif = 0; emif <= USE_EMIF1; emif++) { data_macro_config(DATA_MACRO_0, emif, DDR3_PHY_RD_DQS_CS0_BYTE0, DDR3_PHY_WR_DQS_CS0_BYTE0, @@ -396,9 +404,11 @@ static void config_ti814x_ddr(void) cmd_macro_config(DDR_PHY0, PHY_INVERT_CLKOUT_DEFINE, DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE, PHY_CMD0_DLL_LOCK_DIFF_DEFINE); +#if 0 cmd_macro_config(DDR_PHY1, PHY_INVERT_CLKOUT_DEFINE, DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE, PHY_CMD0_DLL_LOCK_DIFF_DEFINE); +#endif for (emif = 0; emif <= DDR_PHY1; emif++) { for (macro = 0; macro <= DATA_MACRO_3; macro++) { @@ -413,23 +423,34 @@ static void config_ti814x_ddr(void) /* DDR IO CTRL config */ __raw_writel(DDR0_IO_CTRL_DEFINE, DDR0_IO_CTRL); - __raw_writel(DDR1_IO_CTRL_DEFINE, DDR1_IO_CTRL); - + if(USE_EMIF1) { + __raw_writel(DDR1_IO_CTRL_DEFINE, DDR1_IO_CTRL); + } + __raw_writel(__raw_readl(VTP0_CTRL_REG) | 0x00000040 , VTP0_CTRL_REG); - __raw_writel(__raw_readl(VTP1_CTRL_REG) | 0x00000040 , VTP1_CTRL_REG); + if(USE_EMIF1) { + __raw_writel(__raw_readl(VTP1_CTRL_REG) | 0x00000040 , VTP1_CTRL_REG); + } // Write 0 to CLRZ bit __raw_writel(__raw_readl(VTP0_CTRL_REG) & 0xfffffffe , VTP0_CTRL_REG); - __raw_writel(__raw_readl(VTP1_CTRL_REG) & 0xfffffffe , VTP1_CTRL_REG); - + if(USE_EMIF1) { + __raw_writel(__raw_readl(VTP1_CTRL_REG) & 0xfffffffe , VTP1_CTRL_REG); + } // Write 1 to CLRZ bit __raw_writel(__raw_readl(VTP0_CTRL_REG) | 0x00000001 , VTP0_CTRL_REG); - __raw_writel(__raw_readl(VTP1_CTRL_REG) | 0x00000001 , VTP1_CTRL_REG); - + if(USE_EMIF1) { + __raw_writel(__raw_readl(VTP1_CTRL_REG) | 0x00000001 , VTP1_CTRL_REG); + } + + // Read VTP control registers & check READY bits while ((__raw_readl(VTP0_CTRL_REG) & 0x00000020) != 0x20); - while ((__raw_readl(VTP1_CTRL_REG) & 0x00000020) != 0x20); + //while ((__raw_readl(VTP1_CTRL_REG) & 0x00000020) != 0x20); +// if(USE_EMIF1) { +// while ((__raw_readl(VTP1_CTRL_REG) & 0x00000020) != 0x20); +// } /* * Program the PG2.1 DMM to Access EMIF0 and EMIF1 * 512MB sections with 512-byte interleaving @@ -437,8 +458,12 @@ static void config_ti814x_ddr(void) __raw_writel(PG2_1_DMM_LISA_MAP__0, DMM_LISA_MAP__0); __raw_writel(PG2_1_DMM_LISA_MAP__1, DMM_LISA_MAP__1); __raw_writel(PG2_1_DMM_LISA_MAP__2, DMM_LISA_MAP__2); - __raw_writel(PG2_1_DMM_LISA_MAP__3, DMM_LISA_MAP__3); + if(USE_EMIF1) { + __raw_writel(PG2_1_DMM_LISA_MAP__3, DMM_LISA_MAP__3); + } else { + __raw_writel(MIN_DMM_LISA_MAP__3, DMM_LISA_MAP__3); + } while (__raw_readl(DMM_LISA_MAP__0) != PG2_1_DMM_LISA_MAP__0); while (__raw_readl(DMM_LISA_MAP__1) != PG2_1_DMM_LISA_MAP__1); while (__raw_readl(DMM_LISA_MAP__2) != PG2_1_DMM_LISA_MAP__2); @@ -510,7 +535,7 @@ static void config_ti814x_ddr(void) __raw_writel(DDR3_EMIF_REF_CTRL, EMIF4_0_SDRAM_REF_CTRL); __raw_writel(DDR3_EMIF_REF_CTRL, EMIF4_0_SDRAM_REF_CTRL_SHADOW); - + if(USE_EMIF1) { /*Program EMIF1 CFG Registers*/ __raw_writel(DDR3_EMIF_READ_LATENCY, EMIF4_1_DDR_PHY_CTRL_1); __raw_writel(DDR3_EMIF_READ_LATENCY, EMIF4_1_DDR_PHY_CTRL_1_SHADOW); @@ -531,6 +556,7 @@ static void config_ti814x_ddr(void) __raw_writel(DDR3_EMIF_REF_CTRL, EMIF4_1_SDRAM_REF_CTRL); __raw_writel(DDR3_EMIF_REF_CTRL, EMIF4_1_SDRAM_REF_CTRL_SHADOW); + } } } @@ -901,6 +927,7 @@ void per_clocks_enable(void) * configured to unfreeze the timer. * Note: It is important to stop the watchdog before unfreezing it */ +#if 0 __raw_writel(0xAAAA, WDT_WSPR); while (__raw_readl(WDT_WWPS) != 0x0); __raw_writel(0x5555, WDT_WSPR); @@ -908,6 +935,7 @@ void per_clocks_enable(void) /* Unfreeze WDT */ __raw_writel(0x13, WDT_UNFREEZE); +#endif } void DDR1_PHY_PWRDN(void) @@ -971,7 +999,7 @@ void prcm_init(u32 in_ddr) void ipnc_ff_pll_init(int option) { unlock_pll_control_mmr(); - +#if 0 if(option == 1) { PLL_CLKOUT_ENABLE(DSS_PLL_BASE); PLL_CLKOUT_ENABLE(VIDEO_0_PLL_BASE); @@ -988,6 +1016,7 @@ void ipnc_ff_pll_init(int option) PLL_CLKOUT_DISABLE(DSP_PLL_BASE); } +#endif } #define PADCTRL_BASE 0x48140000 diff --git a/board/ti/ti8148_ipnc/mux.h b/board/ti/ti8148_ipnc/mux.h index 87244c4..ebb064c 100755 --- a/board/ti/ti8148_ipnc/mux.h +++ b/board/ti/ti8148_ipnc/mux.h @@ -15,12 +15,12 @@ */ /* 1-MMC1_CMD */ /* 1-4 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -8 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -12 */ BIT(0), BIT(0), BIT(0), BIT(0), +/* -8 */ BIT(0), BIT(0), BIT(0), BIT(7), +/* -12 */ BIT(7), BIT(7), BIT(7), BIT(7), /* 14 usb1_drvvbus, fn8, pulldn enable 15-AIC_RSTn */ -/* -16 */ BIT(0), BIT(7), BIT(7), BIT(0), +/* -16 */ BIT(7), BIT(7), BIT(7), BIT(0), /* -20 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -24 */ BIT(0), BIT(0), BIT(0), BIT(0), +/* -24 */ BIT(0), BIT(5), BIT(5), BIT(0), /* -28 */ BIT(0), BIT(0), BIT(0), BIT(0), /* -32 */ BIT(0), BIT(0), BIT(0), BIT(0), /* -36 */ BIT(0), BIT(0), BIT(0), BIT(0), @@ -28,16 +28,16 @@ /* -44 */ BIT(0), BIT(0), BIT(0), BIT(0), /* -48 */ BIT(0), BIT(0), BIT(0), BIT(0), /* -52 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -56 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -60 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -64 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -68 */ BIT(0), BIT(0), BIT(0), BIT(0), +/* -56 */ BIT(0), BIT(7), BIT(0), BIT(0), +/* -60 */ BIT(0), BIT(7), BIT(7), BIT(0), +/* -64 */ BIT(0), BIT(7), BIT(7), BIT(7), +/* -68 */ BIT(7), BIT(0), BIT(0), BIT(0), /* 69-RS485_RDE */ /* -72 */ BIT(7), BIT(0), BIT(0), BIT(0), /* 74-I2C[2]_SCL 75-I2C[2]_SDA 76-UART1_TXD */ -/* -76 */ BIT(0), BIT(5), BIT(5), BIT(2), +/* -76 */ BIT(0), BIT(1), BIT(1), BIT(1), /* 77-UART1_RXD 78-HDMI_SCL 79-HDMI_SDA */ -/* -80 */ BIT(2), BIT(1), BIT(1), BIT(0), +/* -80 */ BIT(1), BIT(1), BIT(1), BIT(1), /* -84 */ BIT(0), BIT(0), BIT(0), BIT(0), /* 85-GP1[16] */ /* -88 */ BIT(7), BIT(0), BIT(0), BIT(0), @@ -49,17 +49,17 @@ /* 111-HDMI_CEC 112-HDMI_HPDET */ /* -112 */ BIT(0), BIT(0), BIT(4), BIT(4), /* 115 TIM6_IO 116 TIM7_IO */ -/* -116 */ BIT(0), BIT(0), BIT(6), BIT(6), -/* -120 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -124 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -128 */ BIT(0), BIT(0), BIT(0), BIT(0), +/* -116 */ BIT(7), BIT(7), BIT(7), BIT(7), +/* -120 */ BIT(0), BIT(0), BIT(7), BIT(7), +/* -124 */ BIT(7), BIT(0), BIT(0), BIT(0), +/* -128 */ BIT(0), BIT(7), BIT(0), BIT(0), /* -132 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -136 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -140 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -144 */ BIT(0), BIT(0), BIT(0), BIT(0), -/* -148 */ BIT(0), BIT(0), BIT(0), BIT(0), +/* -136 */ BIT(0), BIT(0), BIT(5), BIT(5), +/* -140 */ BIT(7), BIT(5), BIT(5), BIT(7), +/* -144 */ BIT(7), BIT(7), BIT(7), BIT(7), +/* -148 */ BIT(7), BIT(7), BIT(7), BIT(0), /* 150 MMC_CD 151 MMC_WP */ -/* -152 */ BIT(0), BIT(7), BIT(7), BIT(0), +/* -152 */ BIT(0), BIT(7), BIT(7), BIT(7), /* 153 CAM_RST 154-mmc1_pow 155 -ENET_RST 156-CAM_D[8] */ /* -156 */ BIT(7), BIT(7), BIT(7), BIT(1), /* 157-CAM_D[9] 158-CAM_D[10] 159-CAM_D[11] 160-CAM_D[12] */ @@ -73,7 +73,7 @@ /* 173-CAM_VS 174-gp0_28 175-CAM_PCLK */ /* -176 */ BIT(1), BIT(7), BIT(1), BIT(0), /* 179-RE_SETING 180-gp2_22(WLAN_EN) */ -/* -180 */ BIT(0), BIT(0), BIT(7), BIT(7), +/* -180 */ BIT(0), BIT(0), BIT(0), BIT(7), /* 181-LED3_ON */ /* -184 */ BIT(7), BIT(0), BIT(0), BIT(0), /* 188-gp2_24(WLAN_IRQ) */ @@ -101,8 +101,8 @@ /* 251-UART4_RXD 252-UART4_TXD */ /* -252 */ BIT(0), BIT(0), BIT(5), BIT(5), /* 253-UART4_CTS 254-UART4_RTS */ -/* -256 */ BIT(5), BIT(5), BIT(0), BIT(0), -/* -260 */ BIT(0), BIT(0), BIT(0), BIT(0), +/* -256 */ BIT(5), BIT(5), BIT(5), BIT(5), +/* -260 */ BIT(5), BIT(5), BIT(0), BIT(0), /* -264 */ BIT(0), BIT(0), BIT(0), BIT(0), /* -268 */ BIT(0), BIT(0), BIT(0), BIT(0), /* 270 usb0_drvvbus, fn1, pulldn enable */ -- 1.9.1