/*
 * Copyright (C) 2006 Texas Instruments Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
/* ccdc_davinci.c */

#include <linux/device.h>
#include <media/davinci/ccdc_davinci.h>
#include <asm/page.h>

/* Object for OV7670 mode */
ccdc_params_ycbcr ccdc_hw_params_ov7670 = {
	.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
	.frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
	.win = VPFE_WIN_VGA,
	.fid_pol = CCDC_PINPOL_POSITIVE,
	.vd_pol = CCDC_PINPOL_POSITIVE,
	.hd_pol = CCDC_PINPOL_POSITIVE,
	.bt656_enable = FALSE,
	.pix_order = CCDC_PIXORDER_CBYCRY,//LBOZ 9-feb: simulating TVP as much as possible......
	.buf_type = CCDC_BUFTYPE_FLD_SEPARATED //LBOZ 4-feb: it was _INTERLEAVED
};

extern struct device *vpfe_dev;

 * ======== ccdc_config_ov7670  ======== 
 */
/*This function will configure CCDC for OV7670 parameters*/
void ccdc_config_ov7670(void)
{
	u32 syn_mode;
	unsigned int val;
	ccdc_params_ycbcr *params = &ccdc_hw_params_ov7670;

	/* first reset the CCDC                                          */
	/* all registers have default values after reset                 */
	/* This is important since we assume default values to be set in */
	/* a lot of registers that we didn't touch                       */
	dev_dbg(vpfe_dev, "\nStarting ccdc_config_ycbcr...");
	ccdc_reset();

	/* configure pixel format */
	syn_mode = (params->pix_fmt & 0x3) << 12;

	/* configure video frame format */
	syn_mode |= (params->frm_fmt & 0x1) << 7;

	/* setup BT.656 sync mode */
	if (params->bt656_enable) {
		regw(3, REC656IF);

		/* configure the FID, VD, HD pin polarity */
		/* fld,hd pol positive, vd negative, 8-bit pack mode */
		syn_mode |= 0x00000F04;
	} else {		/* y/c external sync mode */
//		syn_mode |= ((params->fid_pol & 0x1) << 4); LBOZ 3-feb: no FID for OV7670
		syn_mode |= ((params->hd_pol & 0x1) << 3);
		syn_mode |= ((params->vd_pol & 0x1) << 2);
		syn_mode |= 0x00000700;//LBOZ 5-feb: DATSIZ 8 bit
	}

	/* configure video window */
	ccdc_setwin(&params->win, params->frm_fmt, 2);

	/* configure the order of y cb cr in SD-RAM */
//LBOZ3-feb	regw((params->pix_order << 11) | 0x8000, CCDCFG);
//	regw((params->pix_order << 11) | (1 << 6), CCDCFG); //LBOZ 3-feb: FID not latched to VSYNC and 0x8000 it would have enabled VSYNC latching....
	regw((params->pix_order << 11) | (1 << 6) | 0x8000, CCDCFG); //LBOZ 9-feb: added 0x8000

	/* configure the horizontal line offset */
	/* this is done by rounding up width to a multiple of 16 pixels */
	/* and multiply by two to account for y:cb:cr 4:2:2 data */
	regw(((params->win.width * 2) + 31) & 0xffffffe0, HSIZE_OFF);

	/* configure the memory line offset */
	if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) {
		/* two fields are interleaved in memory */
		regw(0x00000249, SDOFST);
	}
	/* enable output to SDRAM */
	syn_mode |= (0x1 << 17);
	/* synchronize with VD/HD */
	syn_mode |= (0x1 << 16);

	syn_mode |= CCDC_DATA_PACK_ENABLE;
	regw(syn_mode, SYN_MODE);

	val = (unsigned int)ccdc_sbl_reset();
	dev_dbg(vpfe_dev, "\nReading 0x%x from SBL...\n", val);

	dev_dbg(vpfe_dev, "\nEnd of ccdc_config_ycbcr...\n");
	ccdc_readregs();
}